1 /* 2 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef ARM_DEF_H 7 #define ARM_DEF_H 8 9 #include <arch.h> 10 #include <common/interrupt_props.h> 11 #include <common/tbbr/tbbr_img_def.h> 12 #include <drivers/arm/gic_common.h> 13 #include <lib/utils_def.h> 14 #include <lib/xlat_tables/xlat_tables_defs.h> 15 #include <plat/arm/common/smccc_def.h> 16 #include <plat/common/common_def.h> 17 18 /****************************************************************************** 19 * Definitions common to all ARM standard platforms 20 *****************************************************************************/ 21 22 /* 23 * Root of trust key lengths 24 */ 25 #define ARM_ROTPK_HEADER_LEN 19 26 #define ARM_ROTPK_HASH_LEN 32 27 /* ARM_ROTPK_KEY_LEN includes DER header + raw key material */ 28 #define ARM_ROTPK_KEY_LEN 294 29 30 /* Special value used to verify platform parameters from BL2 to BL31 */ 31 #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) 32 33 #define ARM_SYSTEM_COUNT U(1) 34 35 #define ARM_CACHE_WRITEBACK_SHIFT 6 36 37 /* 38 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 39 * power levels have a 1:1 mapping with the MPIDR affinity levels. 40 */ 41 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 42 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 43 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 44 #define ARM_PWR_LVL3 MPIDR_AFFLVL3 45 46 /* 47 * Macros for local power states in ARM platforms encoded by State-ID field 48 * within the power-state parameter. 49 */ 50 /* Local power state for power domains in Run state. */ 51 #define ARM_LOCAL_STATE_RUN U(0) 52 /* Local power state for retention. Valid only for CPU power domains */ 53 #define ARM_LOCAL_STATE_RET U(1) 54 /* Local power state for OFF/power-down. Valid for CPU and cluster power 55 domains */ 56 #define ARM_LOCAL_STATE_OFF U(2) 57 58 /* Memory location options for TSP */ 59 #define ARM_TRUSTED_SRAM_ID 0 60 #define ARM_TRUSTED_DRAM_ID 1 61 #define ARM_DRAM_ID 2 62 63 #ifdef PLAT_ARM_TRUSTED_SRAM_BASE 64 #define ARM_TRUSTED_SRAM_BASE PLAT_ARM_TRUSTED_SRAM_BASE 65 #else 66 #define ARM_TRUSTED_SRAM_BASE UL(0x04000000) 67 #endif /* PLAT_ARM_TRUSTED_SRAM_BASE */ 68 69 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 70 #define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ 71 72 /* The remaining Trusted SRAM is used to load the BL images */ 73 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 74 ARM_SHARED_RAM_SIZE) 75 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 76 ARM_SHARED_RAM_SIZE) 77 78 /* 79 * The top 16MB (or 64MB if RME is enabled) of DRAM1 is configured as 80 * follows: 81 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 82 * - L1 GPT DRAM: Reserved for L1 GPT if RME is enabled 83 * - REALM DRAM: Reserved for Realm world if RME is enabled 84 * - TF-A <-> RMM SHARED: Area shared for communication between TF-A and RMM 85 * - Event Log: Area for Event Log if MEASURED_BOOT feature is enabled 86 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 87 * 88 * RME enabled(64MB) RME not enabled(16MB) 89 * -------------------- ------------------- 90 * | | | | 91 * | AP TZC (~28MB) | | AP TZC (~14MB) | 92 * -------------------- ------------------- 93 * | Event Log | | Event Log | 94 * | (4KB) | | (4KB) | 95 * -------------------- ------------------- 96 * | REALM (RMM) | | | 97 * | (32MB - 4KB) | | EL3 TZC (2MB) | 98 * -------------------- ------------------- 99 * | | | | 100 * | TF-A <-> RMM | | SCP TZC | 101 * | SHARED (4KB) | 0xFFFF_FFFF------------------- 102 * -------------------- 103 * | | 104 * | EL3 TZC (3MB) | 105 * -------------------- 106 * | L1 GPT + SCP TZC | 107 * | (~1MB) | 108 * 0xFFFF_FFFF -------------------- 109 */ 110 #if ENABLE_RME 111 #define ARM_TZC_DRAM1_SIZE UL(0x04000000) /* 64MB */ 112 /* 113 * Define a region within the TZC secured DRAM for use by EL3 runtime 114 * firmware. This region is meant to be NOLOAD and will not be zero 115 * initialized. Data sections with the attribute `.arm_el3_tzc_dram` will be 116 * placed here. 3MB region is reserved if RME is enabled, 2MB otherwise. 117 */ 118 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00300000) /* 3MB */ 119 #define ARM_L1_GPT_SIZE UL(0x00100000) /* 1MB */ 120 /* 32MB - ARM_EL3_RMM_SHARED_SIZE */ 121 #define ARM_REALM_SIZE (UL(0x02000000) - \ 122 ARM_EL3_RMM_SHARED_SIZE) 123 #define ARM_EL3_RMM_SHARED_SIZE (PAGE_SIZE) /* 4KB */ 124 #else 125 #define ARM_TZC_DRAM1_SIZE UL(0x01000000) /* 16MB */ 126 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2MB */ 127 #define ARM_L1_GPT_SIZE UL(0) 128 #define ARM_REALM_SIZE UL(0) 129 #define ARM_EL3_RMM_SHARED_SIZE UL(0) 130 #endif /* ENABLE_RME */ 131 132 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 133 ARM_DRAM1_SIZE - \ 134 (ARM_SCP_TZC_DRAM1_SIZE + \ 135 ARM_L1_GPT_SIZE)) 136 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 137 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 138 ARM_SCP_TZC_DRAM1_SIZE - 1U) 139 140 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 141 MEASURED_BOOT 142 #define ARM_EVENT_LOG_DRAM1_SIZE UL(0x00001000) /* 4KB */ 143 144 #if ENABLE_RME 145 #define ARM_EVENT_LOG_DRAM1_BASE (ARM_REALM_BASE - \ 146 ARM_EVENT_LOG_DRAM1_SIZE) 147 #else 148 #define ARM_EVENT_LOG_DRAM1_BASE (ARM_EL3_TZC_DRAM1_BASE - \ 149 ARM_EVENT_LOG_DRAM1_SIZE) 150 #endif /* ENABLE_RME */ 151 #define ARM_EVENT_LOG_DRAM1_END (ARM_EVENT_LOG_DRAM1_BASE + \ 152 ARM_EVENT_LOG_DRAM1_SIZE - \ 153 1U) 154 #else 155 #define ARM_EVENT_LOG_DRAM1_SIZE UL(0) 156 #endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && MEASURED_BOOT */ 157 158 #if ENABLE_RME 159 #define ARM_L1_GPT_ADDR_BASE (ARM_DRAM1_BASE + \ 160 ARM_DRAM1_SIZE - \ 161 ARM_L1_GPT_SIZE) 162 #define ARM_L1_GPT_END (ARM_L1_GPT_ADDR_BASE + \ 163 ARM_L1_GPT_SIZE - 1U) 164 165 #define ARM_REALM_BASE (ARM_EL3_RMM_SHARED_BASE - \ 166 ARM_REALM_SIZE) 167 168 #define ARM_REALM_END (ARM_REALM_BASE + ARM_REALM_SIZE - 1U) 169 170 #define ARM_EL3_RMM_SHARED_BASE (ARM_DRAM1_BASE + \ 171 ARM_DRAM1_SIZE - \ 172 (ARM_SCP_TZC_DRAM1_SIZE + \ 173 ARM_L1_GPT_SIZE + \ 174 ARM_EL3_RMM_SHARED_SIZE + \ 175 ARM_EL3_TZC_DRAM1_SIZE)) 176 177 #define ARM_EL3_RMM_SHARED_END (ARM_EL3_RMM_SHARED_BASE + \ 178 ARM_EL3_RMM_SHARED_SIZE - 1U) 179 #endif /* ENABLE_RME */ 180 181 #define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - \ 182 ARM_EL3_TZC_DRAM1_SIZE) 183 #define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ 184 ARM_EL3_TZC_DRAM1_SIZE - 1U) 185 186 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 187 ARM_DRAM1_SIZE - \ 188 ARM_TZC_DRAM1_SIZE) 189 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 190 (ARM_SCP_TZC_DRAM1_SIZE + \ 191 ARM_EL3_TZC_DRAM1_SIZE + \ 192 ARM_EL3_RMM_SHARED_SIZE + \ 193 ARM_REALM_SIZE + \ 194 ARM_L1_GPT_SIZE + \ 195 ARM_EVENT_LOG_DRAM1_SIZE)) 196 197 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 198 ARM_AP_TZC_DRAM1_SIZE - 1U) 199 200 /* Define the Access permissions for Secure peripherals to NS_DRAM */ 201 #if ARM_CRYPTOCELL_INTEG 202 /* 203 * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell. 204 * This is required by CryptoCell to authenticate BL33 which is loaded 205 * into the Non Secure DDR. 206 */ 207 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD 208 #else 209 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE 210 #endif 211 212 #ifdef SPD_opteed 213 /* 214 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to 215 * load/authenticate the trusted os extra image. The first 512KB of 216 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading 217 * for OPTEE is paged image which only include the paging part using 218 * virtual memory but without "init" data. OPTEE will copy the "init" data 219 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the 220 * extra image behind the "init" data. 221 */ 222 #define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \ 223 ARM_AP_TZC_DRAM1_SIZE - \ 224 ARM_OPTEE_PAGEABLE_LOAD_SIZE) 225 #define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000) 226 #define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ 227 ARM_OPTEE_PAGEABLE_LOAD_BASE, \ 228 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ 229 MT_MEMORY | MT_RW | MT_SECURE) 230 231 /* 232 * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging 233 * support is enabled). 234 */ 235 #define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ 236 BL32_BASE, \ 237 BL32_LIMIT - BL32_BASE, \ 238 MT_MEMORY | MT_RW | MT_SECURE) 239 #endif /* SPD_opteed */ 240 241 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 242 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 243 ARM_TZC_DRAM1_SIZE) 244 245 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 246 ARM_NS_DRAM1_SIZE - 1U) 247 #ifdef PLAT_ARM_DRAM1_BASE 248 #define ARM_DRAM1_BASE PLAT_ARM_DRAM1_BASE 249 #else 250 #define ARM_DRAM1_BASE ULL(0x80000000) 251 #endif /* PLAT_ARM_DRAM1_BASE */ 252 253 #define ARM_DRAM1_SIZE ULL(0x80000000) 254 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 255 ARM_DRAM1_SIZE - 1U) 256 257 #define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE 258 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 259 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 260 ARM_DRAM2_SIZE - 1U) 261 /* Number of DRAM banks */ 262 #define ARM_DRAM_NUM_BANKS 2UL 263 264 #define ARM_IRQ_SEC_PHY_TIMER 29 265 266 #define ARM_IRQ_SEC_SGI_0 8 267 #define ARM_IRQ_SEC_SGI_1 9 268 #define ARM_IRQ_SEC_SGI_2 10 269 #define ARM_IRQ_SEC_SGI_3 11 270 #define ARM_IRQ_SEC_SGI_4 12 271 #define ARM_IRQ_SEC_SGI_5 13 272 #define ARM_IRQ_SEC_SGI_6 14 273 #define ARM_IRQ_SEC_SGI_7 15 274 275 /* 276 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 277 * terminology. On a GICv2 system or mode, the lists will be merged and treated 278 * as Group 0 interrupts. 279 */ 280 #define ARM_G1S_IRQ_PROPS(grp) \ 281 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 282 GIC_INTR_CFG_LEVEL), \ 283 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 284 GIC_INTR_CFG_EDGE), \ 285 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 286 GIC_INTR_CFG_EDGE), \ 287 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 288 GIC_INTR_CFG_EDGE), \ 289 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 290 GIC_INTR_CFG_EDGE), \ 291 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 292 GIC_INTR_CFG_EDGE), \ 293 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 294 GIC_INTR_CFG_EDGE) 295 296 #define ARM_G0_IRQ_PROPS(grp) \ 297 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ 298 GIC_INTR_CFG_EDGE), \ 299 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 300 GIC_INTR_CFG_EDGE) 301 302 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 303 ARM_SHARED_RAM_BASE, \ 304 ARM_SHARED_RAM_SIZE, \ 305 MT_DEVICE | MT_RW | EL3_PAS) 306 307 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 308 ARM_NS_DRAM1_BASE, \ 309 ARM_NS_DRAM1_SIZE, \ 310 MT_MEMORY | MT_RW | MT_NS) 311 312 #define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ 313 ARM_DRAM2_BASE, \ 314 ARM_DRAM2_SIZE, \ 315 MT_MEMORY | MT_RW | MT_NS) 316 317 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 318 TSP_SEC_MEM_BASE, \ 319 TSP_SEC_MEM_SIZE, \ 320 MT_MEMORY | MT_RW | MT_SECURE) 321 322 #if ARM_BL31_IN_DRAM 323 #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ 324 BL31_BASE, \ 325 PLAT_ARM_MAX_BL31_SIZE, \ 326 MT_MEMORY | MT_RW | MT_SECURE) 327 #endif 328 329 #define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ 330 ARM_EL3_TZC_DRAM1_BASE, \ 331 ARM_EL3_TZC_DRAM1_SIZE, \ 332 MT_MEMORY | MT_RW | EL3_PAS) 333 334 #define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \ 335 PLAT_ARM_TRUSTED_DRAM_BASE, \ 336 PLAT_ARM_TRUSTED_DRAM_SIZE, \ 337 MT_MEMORY | MT_RW | MT_SECURE) 338 339 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 340 MEASURED_BOOT 341 #define ARM_MAP_EVENT_LOG_DRAM1 \ 342 MAP_REGION_FLAT( \ 343 ARM_EVENT_LOG_DRAM1_BASE, \ 344 ARM_EVENT_LOG_DRAM1_SIZE, \ 345 MT_MEMORY | MT_RW | MT_SECURE) 346 #endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && MEASURED_BOOT */ 347 348 #if ENABLE_RME 349 /* 350 * We add the EL3_RMM_SHARED size to RMM mapping to map the region as a block. 351 * Else we end up requiring more pagetables in BL2 for ROMLIB build. 352 */ 353 #define ARM_MAP_RMM_DRAM MAP_REGION_FLAT( \ 354 PLAT_ARM_RMM_BASE, \ 355 (PLAT_ARM_RMM_SIZE + \ 356 ARM_EL3_RMM_SHARED_SIZE), \ 357 MT_MEMORY | MT_RW | MT_REALM) 358 359 360 #define ARM_MAP_GPT_L1_DRAM MAP_REGION_FLAT( \ 361 ARM_L1_GPT_ADDR_BASE, \ 362 ARM_L1_GPT_SIZE, \ 363 MT_MEMORY | MT_RW | EL3_PAS) 364 365 #define ARM_MAP_EL3_RMM_SHARED_MEM \ 366 MAP_REGION_FLAT( \ 367 ARM_EL3_RMM_SHARED_BASE, \ 368 ARM_EL3_RMM_SHARED_SIZE, \ 369 MT_MEMORY | MT_RW | MT_REALM) 370 371 #endif /* ENABLE_RME */ 372 373 /* 374 * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to 375 * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides 376 * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order 377 * to be able to access the heap. 378 */ 379 #define ARM_MAP_BL1_RW MAP_REGION_FLAT( \ 380 BL1_RW_BASE, \ 381 BL1_RW_LIMIT - BL1_RW_BASE, \ 382 MT_MEMORY | MT_RW | EL3_PAS) 383 384 /* 385 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section 386 * otherwise one region is defined containing both. 387 */ 388 #if SEPARATE_CODE_AND_RODATA 389 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 390 BL_CODE_BASE, \ 391 BL_CODE_END - BL_CODE_BASE, \ 392 MT_CODE | EL3_PAS), \ 393 MAP_REGION_FLAT( \ 394 BL_RO_DATA_BASE, \ 395 BL_RO_DATA_END \ 396 - BL_RO_DATA_BASE, \ 397 MT_RO_DATA | EL3_PAS) 398 #else 399 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 400 BL_CODE_BASE, \ 401 BL_CODE_END - BL_CODE_BASE, \ 402 MT_CODE | EL3_PAS) 403 #endif 404 #if USE_COHERENT_MEM 405 #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 406 BL_COHERENT_RAM_BASE, \ 407 BL_COHERENT_RAM_END \ 408 - BL_COHERENT_RAM_BASE, \ 409 MT_DEVICE | MT_RW | EL3_PAS) 410 #endif 411 #if USE_ROMLIB 412 #define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \ 413 ROMLIB_RO_BASE, \ 414 ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\ 415 MT_CODE | EL3_PAS) 416 417 #define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \ 418 ROMLIB_RW_BASE, \ 419 ROMLIB_RW_END - ROMLIB_RW_BASE,\ 420 MT_MEMORY | MT_RW | EL3_PAS) 421 #endif 422 423 /* 424 * Map mem_protect flash region with read and write permissions 425 */ 426 #define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \ 427 V2M_FLASH_BLOCK_SIZE, \ 428 MT_DEVICE | MT_RW | MT_SECURE) 429 /* 430 * Map the region for device tree configuration with read and write permissions 431 */ 432 #define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \ 433 (ARM_FW_CONFIGS_LIMIT \ 434 - ARM_BL_RAM_BASE), \ 435 MT_MEMORY | MT_RW | EL3_PAS) 436 /* 437 * Map L0_GPT with read and write permissions 438 */ 439 #if ENABLE_RME 440 #define ARM_MAP_L0_GPT_REGION MAP_REGION_FLAT(ARM_L0_GPT_ADDR_BASE, \ 441 ARM_L0_GPT_SIZE, \ 442 MT_MEMORY | MT_RW | MT_ROOT) 443 #endif 444 445 /* 446 * The max number of regions like RO(code), coherent and data required by 447 * different BL stages which need to be mapped in the MMU. 448 */ 449 #define ARM_BL_REGIONS 7 450 451 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 452 ARM_BL_REGIONS) 453 454 /* Memory mapped Generic timer interfaces */ 455 #ifdef PLAT_ARM_SYS_CNTCTL_BASE 456 #define ARM_SYS_CNTCTL_BASE PLAT_ARM_SYS_CNTCTL_BASE 457 #else 458 #define ARM_SYS_CNTCTL_BASE UL(0x2a430000) 459 #endif 460 461 #ifdef PLAT_ARM_SYS_CNTREAD_BASE 462 #define ARM_SYS_CNTREAD_BASE PLAT_ARM_SYS_CNTREAD_BASE 463 #else 464 #define ARM_SYS_CNTREAD_BASE UL(0x2a800000) 465 #endif 466 467 #ifdef PLAT_ARM_SYS_TIMCTL_BASE 468 #define ARM_SYS_TIMCTL_BASE PLAT_ARM_SYS_TIMCTL_BASE 469 #else 470 #define ARM_SYS_TIMCTL_BASE UL(0x2a810000) 471 #endif 472 473 #ifdef PLAT_ARM_SYS_CNT_BASE_S 474 #define ARM_SYS_CNT_BASE_S PLAT_ARM_SYS_CNT_BASE_S 475 #else 476 #define ARM_SYS_CNT_BASE_S UL(0x2a820000) 477 #endif 478 479 #ifdef PLAT_ARM_SYS_CNT_BASE_NS 480 #define ARM_SYS_CNT_BASE_NS PLAT_ARM_SYS_CNT_BASE_NS 481 #else 482 #define ARM_SYS_CNT_BASE_NS UL(0x2a830000) 483 #endif 484 485 #define ARM_CONSOLE_BAUDRATE 115200 486 487 /* Trusted Watchdog constants */ 488 #ifdef PLAT_ARM_SP805_TWDG_BASE 489 #define ARM_SP805_TWDG_BASE PLAT_ARM_SP805_TWDG_BASE 490 #else 491 #define ARM_SP805_TWDG_BASE UL(0x2a490000) 492 #endif 493 #define ARM_SP805_TWDG_CLK_HZ 32768 494 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 495 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ 496 #define ARM_TWDG_TIMEOUT_SEC 128 497 #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ 498 ARM_TWDG_TIMEOUT_SEC) 499 500 /****************************************************************************** 501 * Required platform porting definitions common to all ARM standard platforms 502 *****************************************************************************/ 503 504 /* 505 * This macro defines the deepest retention state possible. A higher state 506 * id will represent an invalid or a power down state. 507 */ 508 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 509 510 /* 511 * This macro defines the deepest power down states possible. Any state ID 512 * higher than this is invalid. 513 */ 514 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 515 516 /* 517 * Some data must be aligned on the biggest cache line size in the platform. 518 * This is known only to the platform as it might have a combination of 519 * integrated and external caches. 520 */ 521 #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) 522 523 /* 524 * To enable FW_CONFIG to be loaded by BL1, define the corresponding base 525 * and limit. Leave enough space of BL2 meminfo. 526 */ 527 #define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) 528 #define ARM_FW_CONFIG_LIMIT ((ARM_BL_RAM_BASE + PAGE_SIZE) \ 529 + (PAGE_SIZE / 2U)) 530 531 /* 532 * Boot parameters passed from BL2 to BL31/BL32 are stored here 533 */ 534 #define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT) 535 #define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \ 536 + (PAGE_SIZE / 2U)) 537 538 /* 539 * Define limit of firmware configuration memory: 540 * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory 541 */ 542 #define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2)) 543 544 #if ENABLE_RME 545 /* 546 * Store the L0 GPT on Trusted SRAM next to firmware 547 * configuration memory, 4KB aligned. 548 */ 549 #define ARM_L0_GPT_SIZE (PAGE_SIZE) 550 #define ARM_L0_GPT_ADDR_BASE (ARM_FW_CONFIGS_LIMIT) 551 #define ARM_L0_GPT_LIMIT (ARM_L0_GPT_ADDR_BASE + ARM_L0_GPT_SIZE) 552 #else 553 #define ARM_L0_GPT_SIZE U(0) 554 #endif 555 556 /******************************************************************************* 557 * BL1 specific defines. 558 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 559 * addresses. 560 ******************************************************************************/ 561 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 562 #ifdef PLAT_BL1_RO_LIMIT 563 #define BL1_RO_LIMIT PLAT_BL1_RO_LIMIT 564 #else 565 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ 566 + (PLAT_ARM_TRUSTED_ROM_SIZE - \ 567 PLAT_ARM_MAX_ROMLIB_RO_SIZE)) 568 #endif 569 570 /* 571 * Put BL1 RW at the top of the Trusted SRAM. 572 */ 573 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 574 ARM_BL_RAM_SIZE - \ 575 (PLAT_ARM_MAX_BL1_RW_SIZE +\ 576 PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 577 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ 578 (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 579 580 #define ROMLIB_RO_BASE BL1_RO_LIMIT 581 #define ROMLIB_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE) 582 583 #define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE) 584 #define ROMLIB_RW_END (ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE) 585 586 /******************************************************************************* 587 * BL2 specific defines. 588 ******************************************************************************/ 589 #if RESET_TO_BL2 590 #if ENABLE_PIE 591 /* 592 * As the BL31 image size appears to be increased when built with the ENABLE_PIE 593 * option, set BL2 base address to have enough space for BL31 in Trusted SRAM. 594 */ 595 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ 596 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \ 597 0x3000) 598 #else 599 /* Put BL2 towards the middle of the Trusted SRAM */ 600 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ 601 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \ 602 0x2000) 603 #endif /* ENABLE_PIE */ 604 #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 605 606 #else 607 /* 608 * Put BL2 just below BL1. 609 */ 610 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) 611 #define BL2_LIMIT BL1_RW_BASE 612 #endif 613 614 /******************************************************************************* 615 * BL31 specific defines. 616 ******************************************************************************/ 617 #if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION 618 /* 619 * Put BL31 at the bottom of TZC secured DRAM 620 */ 621 #define BL31_BASE ARM_AP_TZC_DRAM1_BASE 622 #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 623 PLAT_ARM_MAX_BL31_SIZE) 624 /* 625 * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM. 626 * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten. 627 */ 628 #if SEPARATE_NOBITS_REGION 629 #define BL31_NOBITS_BASE BL2_BASE 630 #define BL31_NOBITS_LIMIT BL2_LIMIT 631 #endif /* SEPARATE_NOBITS_REGION */ 632 #elif (RESET_TO_BL31) 633 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 634 # if !ENABLE_PIE 635 # error "BL31 must be a PIE if RESET_TO_BL31=1." 636 #endif 637 /* 638 * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely 639 * used for building BL31 and not used for loading BL31. 640 */ 641 # define BL31_BASE 0x0 642 # define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE 643 #else 644 /* Put BL31 below BL2 in the Trusted SRAM.*/ 645 #define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 646 - PLAT_ARM_MAX_BL31_SIZE) 647 #define BL31_PROGBITS_LIMIT BL2_BASE 648 /* 649 * For RESET_TO_BL2 make sure the BL31 can grow up until BL2_BASE. 650 * This is because in the RESET_TO_BL2 configuration, 651 * BL2 is always resident. 652 */ 653 #if RESET_TO_BL2 654 #define BL31_LIMIT BL2_BASE 655 #else 656 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 657 #endif 658 #endif 659 660 /****************************************************************************** 661 * RMM specific defines 662 *****************************************************************************/ 663 #if ENABLE_RME 664 #define RMM_BASE (ARM_REALM_BASE) 665 #define RMM_LIMIT (RMM_BASE + ARM_REALM_SIZE) 666 #define RMM_SHARED_BASE (ARM_EL3_RMM_SHARED_BASE) 667 #define RMM_SHARED_SIZE (ARM_EL3_RMM_SHARED_SIZE) 668 #endif 669 670 #if !defined(__aarch64__) || JUNO_AARCH32_EL3_RUNTIME 671 /******************************************************************************* 672 * BL32 specific defines for EL3 runtime in AArch32 mode 673 ******************************************************************************/ 674 # if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME 675 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 676 # if !ENABLE_PIE 677 # error "BL32 must be a PIE if RESET_TO_SP_MIN=1." 678 #endif 679 /* 680 * Since this is PIE, we can define BL32_BASE to 0x0 since this macro is solely 681 * used for building BL32 and not used for loading BL32. 682 */ 683 # define BL32_BASE 0x0 684 # define BL32_LIMIT PLAT_ARM_MAX_BL32_SIZE 685 # else 686 /* Put BL32 below BL2 in the Trusted SRAM.*/ 687 # define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 688 - PLAT_ARM_MAX_BL32_SIZE) 689 # define BL32_PROGBITS_LIMIT BL2_BASE 690 # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 691 # endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */ 692 693 #else 694 /******************************************************************************* 695 * BL32 specific defines for EL3 runtime in AArch64 mode 696 ******************************************************************************/ 697 /* 698 * On ARM standard platforms, the TSP can execute from Trusted SRAM, 699 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone 700 * controller. 701 */ 702 # if SPM_MM || SPMC_AT_EL3 703 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 704 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 705 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 706 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 707 ARM_AP_TZC_DRAM1_SIZE) 708 # elif defined(SPD_spmd) 709 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 710 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 711 # define BL32_BASE PLAT_ARM_SPMC_BASE 712 # define BL32_LIMIT (PLAT_ARM_SPMC_BASE + \ 713 PLAT_ARM_SPMC_SIZE) 714 # elif ARM_BL31_IN_DRAM 715 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ 716 PLAT_ARM_MAX_BL31_SIZE) 717 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \ 718 PLAT_ARM_MAX_BL31_SIZE) 719 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \ 720 PLAT_ARM_MAX_BL31_SIZE) 721 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 722 ARM_AP_TZC_DRAM1_SIZE) 723 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID 724 # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE 725 # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE 726 # define TSP_PROGBITS_LIMIT BL31_BASE 727 # define BL32_BASE ARM_FW_CONFIGS_LIMIT 728 # define BL32_LIMIT BL31_BASE 729 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID 730 # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE 731 # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE 732 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 733 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 734 + SZ_4M) 735 # elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID 736 # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 737 # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 738 # define BL32_BASE ARM_AP_TZC_DRAM1_BASE 739 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 740 ARM_AP_TZC_DRAM1_SIZE) 741 # else 742 # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" 743 # endif 744 #endif /* !__aarch64__ || JUNO_AARCH32_EL3_RUNTIME */ 745 746 /* 747 * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no 748 * SPD and no SPM-MM and no SPMC-AT-EL3, as they are the only ones that can be 749 * used as BL32. 750 */ 751 #if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME 752 # if defined(SPD_none) && !SPM_MM && !SPMC_AT_EL3 753 # undef BL32_BASE 754 # endif /* defined(SPD_none) && !SPM_MM || !SPMC_AT_EL3 */ 755 #endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */ 756 757 /******************************************************************************* 758 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. 759 ******************************************************************************/ 760 #define BL2U_BASE BL2_BASE 761 #define BL2U_LIMIT BL2_LIMIT 762 763 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE 764 #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000)) 765 766 /* 767 * ID of the secure physical generic timer interrupt used by the TSP. 768 */ 769 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 770 771 772 /* 773 * One cache line needed for bakery locks on ARM platforms 774 */ 775 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 776 777 /* Priority levels for ARM platforms */ 778 #define PLAT_RAS_PRI 0x10 779 #define PLAT_SDEI_CRITICAL_PRI 0x60 780 #define PLAT_SDEI_NORMAL_PRI 0x70 781 782 /* ARM platforms use 3 upper bits of secure interrupt priority */ 783 #define PLAT_PRI_BITS 3 784 785 /* SGI used for SDEI signalling */ 786 #define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0 787 788 #if SDEI_IN_FCONF 789 /* ARM SDEI dynamic private event max count */ 790 #define ARM_SDEI_DP_EVENT_MAX_CNT 3 791 792 /* ARM SDEI dynamic shared event max count */ 793 #define ARM_SDEI_DS_EVENT_MAX_CNT 3 794 #else 795 /* ARM SDEI dynamic private event numbers */ 796 #define ARM_SDEI_DP_EVENT_0 1000 797 #define ARM_SDEI_DP_EVENT_1 1001 798 #define ARM_SDEI_DP_EVENT_2 1002 799 800 /* ARM SDEI dynamic shared event numbers */ 801 #define ARM_SDEI_DS_EVENT_0 2000 802 #define ARM_SDEI_DS_EVENT_1 2001 803 #define ARM_SDEI_DS_EVENT_2 2002 804 805 #define ARM_SDEI_PRIVATE_EVENTS \ 806 SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ 807 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 808 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 809 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 810 811 #define ARM_SDEI_SHARED_EVENTS \ 812 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 813 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 814 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 815 #endif /* SDEI_IN_FCONF */ 816 817 #endif /* ARM_DEF_H */ 818
