1 /* 2 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef ARM_DEF_H 7 #define ARM_DEF_H 8 9 #include <arch.h> 10 #include <common/interrupt_props.h> 11 #include <common/tbbr/tbbr_img_def.h> 12 #include <drivers/arm/gic_common.h> 13 #include <lib/utils_def.h> 14 #include <lib/xlat_tables/xlat_tables_defs.h> 15 #include <plat/arm/common/smccc_def.h> 16 #include <plat/common/common_def.h> 17 18 /****************************************************************************** 19 * Definitions common to all ARM standard platforms 20 *****************************************************************************/ 21 22 /* 23 * Root of trust key lengths 24 */ 25 #define ARM_ROTPK_HEADER_LEN 19 26 #define ARM_ROTPK_HASH_LEN 32 27 28 /* Special value used to verify platform parameters from BL2 to BL31 */ 29 #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) 30 31 #define ARM_SYSTEM_COUNT U(1) 32 33 #define ARM_CACHE_WRITEBACK_SHIFT 6 34 35 /* 36 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 37 * power levels have a 1:1 mapping with the MPIDR affinity levels. 38 */ 39 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 40 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 41 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 42 #define ARM_PWR_LVL3 MPIDR_AFFLVL3 43 44 /* 45 * Macros for local power states in ARM platforms encoded by State-ID field 46 * within the power-state parameter. 47 */ 48 /* Local power state for power domains in Run state. */ 49 #define ARM_LOCAL_STATE_RUN U(0) 50 /* Local power state for retention. Valid only for CPU power domains */ 51 #define ARM_LOCAL_STATE_RET U(1) 52 /* Local power state for OFF/power-down. Valid for CPU and cluster power 53 domains */ 54 #define ARM_LOCAL_STATE_OFF U(2) 55 56 /* Memory location options for TSP */ 57 #define ARM_TRUSTED_SRAM_ID 0 58 #define ARM_TRUSTED_DRAM_ID 1 59 #define ARM_DRAM_ID 2 60 61 #ifdef PLAT_ARM_TRUSTED_SRAM_BASE 62 #define ARM_TRUSTED_SRAM_BASE PLAT_ARM_TRUSTED_SRAM_BASE 63 #else 64 #define ARM_TRUSTED_SRAM_BASE UL(0x04000000) 65 #endif /* PLAT_ARM_TRUSTED_SRAM_BASE */ 66 67 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 68 #define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ 69 70 /* The remaining Trusted SRAM is used to load the BL images */ 71 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 72 ARM_SHARED_RAM_SIZE) 73 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 74 ARM_SHARED_RAM_SIZE) 75 76 /* 77 * The top 16MB (or 64MB if RME is enabled) of DRAM1 is configured as 78 * follows: 79 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 80 * - L1 GPT DRAM: Reserved for L1 GPT if RME is enabled 81 * - REALM DRAM: Reserved for Realm world if RME is enabled 82 * - TF-A <-> RMM SHARED: Area shared for communication between TF-A and RMM 83 * - Event Log: Area for Event Log if MEASURED_BOOT feature is enabled 84 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 85 * 86 * RME enabled(64MB) RME not enabled(16MB) 87 * -------------------- ------------------- 88 * | | | | 89 * | AP TZC (~28MB) | | AP TZC (~14MB) | 90 * -------------------- ------------------- 91 * | Event Log | | Event Log | 92 * | (4KB) | | (4KB) | 93 * -------------------- ------------------- 94 * | REALM (RMM) | | | 95 * | (32MB - 4KB) | | EL3 TZC (2MB) | 96 * -------------------- ------------------- 97 * | | | | 98 * | TF-A <-> RMM | | SCP TZC | 99 * | SHARED (4KB) | 0xFFFF_FFFF------------------- 100 * -------------------- 101 * | | 102 * | EL3 TZC (3MB) | 103 * -------------------- 104 * | L1 GPT + SCP TZC | 105 * | (~1MB) | 106 * 0xFFFF_FFFF -------------------- 107 */ 108 #if ENABLE_RME 109 #define ARM_TZC_DRAM1_SIZE UL(0x04000000) /* 64MB */ 110 /* 111 * Define a region within the TZC secured DRAM for use by EL3 runtime 112 * firmware. This region is meant to be NOLOAD and will not be zero 113 * initialized. Data sections with the attribute `.arm_el3_tzc_dram` will be 114 * placed here. 3MB region is reserved if RME is enabled, 2MB otherwise. 115 */ 116 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00300000) /* 3MB */ 117 #define ARM_L1_GPT_SIZE UL(0x00100000) /* 1MB */ 118 /* 32MB - ARM_EL3_RMM_SHARED_SIZE */ 119 #define ARM_REALM_SIZE (UL(0x02000000) - \ 120 ARM_EL3_RMM_SHARED_SIZE) 121 #define ARM_EL3_RMM_SHARED_SIZE (PAGE_SIZE) /* 4KB */ 122 #else 123 #define ARM_TZC_DRAM1_SIZE UL(0x01000000) /* 16MB */ 124 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2MB */ 125 #define ARM_L1_GPT_SIZE UL(0) 126 #define ARM_REALM_SIZE UL(0) 127 #define ARM_EL3_RMM_SHARED_SIZE UL(0) 128 #endif /* ENABLE_RME */ 129 130 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 131 ARM_DRAM1_SIZE - \ 132 (ARM_SCP_TZC_DRAM1_SIZE + \ 133 ARM_L1_GPT_SIZE)) 134 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 135 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 136 ARM_SCP_TZC_DRAM1_SIZE - 1U) 137 138 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 139 MEASURED_BOOT 140 #define ARM_EVENT_LOG_DRAM1_SIZE UL(0x00001000) /* 4KB */ 141 142 #if ENABLE_RME 143 #define ARM_EVENT_LOG_DRAM1_BASE (ARM_REALM_BASE - \ 144 ARM_EVENT_LOG_DRAM1_SIZE) 145 #else 146 #define ARM_EVENT_LOG_DRAM1_BASE (ARM_EL3_TZC_DRAM1_BASE - \ 147 ARM_EVENT_LOG_DRAM1_SIZE) 148 #endif /* ENABLE_RME */ 149 #define ARM_EVENT_LOG_DRAM1_END (ARM_EVENT_LOG_DRAM1_BASE + \ 150 ARM_EVENT_LOG_DRAM1_SIZE - \ 151 1U) 152 #else 153 #define ARM_EVENT_LOG_DRAM1_SIZE UL(0) 154 #endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && MEASURED_BOOT */ 155 156 #if ENABLE_RME 157 #define ARM_L1_GPT_ADDR_BASE (ARM_DRAM1_BASE + \ 158 ARM_DRAM1_SIZE - \ 159 ARM_L1_GPT_SIZE) 160 #define ARM_L1_GPT_END (ARM_L1_GPT_ADDR_BASE + \ 161 ARM_L1_GPT_SIZE - 1U) 162 163 #define ARM_REALM_BASE (ARM_EL3_RMM_SHARED_BASE - \ 164 ARM_REALM_SIZE) 165 166 #define ARM_REALM_END (ARM_REALM_BASE + ARM_REALM_SIZE - 1U) 167 168 #define ARM_EL3_RMM_SHARED_BASE (ARM_DRAM1_BASE + \ 169 ARM_DRAM1_SIZE - \ 170 (ARM_SCP_TZC_DRAM1_SIZE + \ 171 ARM_L1_GPT_SIZE + \ 172 ARM_EL3_RMM_SHARED_SIZE + \ 173 ARM_EL3_TZC_DRAM1_SIZE)) 174 175 #define ARM_EL3_RMM_SHARED_END (ARM_EL3_RMM_SHARED_BASE + \ 176 ARM_EL3_RMM_SHARED_SIZE - 1U) 177 #endif /* ENABLE_RME */ 178 179 #define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - \ 180 ARM_EL3_TZC_DRAM1_SIZE) 181 #define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ 182 ARM_EL3_TZC_DRAM1_SIZE - 1U) 183 184 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 185 ARM_DRAM1_SIZE - \ 186 ARM_TZC_DRAM1_SIZE) 187 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 188 (ARM_SCP_TZC_DRAM1_SIZE + \ 189 ARM_EL3_TZC_DRAM1_SIZE + \ 190 ARM_EL3_RMM_SHARED_SIZE + \ 191 ARM_REALM_SIZE + \ 192 ARM_L1_GPT_SIZE + \ 193 ARM_EVENT_LOG_DRAM1_SIZE)) 194 195 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 196 ARM_AP_TZC_DRAM1_SIZE - 1U) 197 198 /* Define the Access permissions for Secure peripherals to NS_DRAM */ 199 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE 200 201 #ifdef SPD_opteed 202 /* 203 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to 204 * load/authenticate the trusted os extra image. The first 512KB of 205 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading 206 * for OPTEE is paged image which only include the paging part using 207 * virtual memory but without "init" data. OPTEE will copy the "init" data 208 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the 209 * extra image behind the "init" data. 210 */ 211 #define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \ 212 ARM_AP_TZC_DRAM1_SIZE - \ 213 ARM_OPTEE_PAGEABLE_LOAD_SIZE) 214 #define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000) 215 #define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ 216 ARM_OPTEE_PAGEABLE_LOAD_BASE, \ 217 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ 218 MT_MEMORY | MT_RW | MT_SECURE) 219 220 /* 221 * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging 222 * support is enabled). 223 */ 224 #define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ 225 BL32_BASE, \ 226 BL32_LIMIT - BL32_BASE, \ 227 MT_MEMORY | MT_RW | MT_SECURE) 228 #endif /* SPD_opteed */ 229 230 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 231 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 232 ARM_TZC_DRAM1_SIZE) 233 234 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 235 ARM_NS_DRAM1_SIZE - 1U) 236 #ifdef PLAT_ARM_DRAM1_BASE 237 #define ARM_DRAM1_BASE PLAT_ARM_DRAM1_BASE 238 #else 239 #define ARM_DRAM1_BASE ULL(0x80000000) 240 #endif /* PLAT_ARM_DRAM1_BASE */ 241 242 #define ARM_DRAM1_SIZE ULL(0x80000000) 243 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 244 ARM_DRAM1_SIZE - 1U) 245 246 #define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE 247 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 248 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 249 ARM_DRAM2_SIZE - 1U) 250 /* Number of DRAM banks */ 251 #define ARM_DRAM_NUM_BANKS 2UL 252 253 #define ARM_IRQ_SEC_PHY_TIMER 29 254 255 #define ARM_IRQ_SEC_SGI_0 8 256 #define ARM_IRQ_SEC_SGI_1 9 257 #define ARM_IRQ_SEC_SGI_2 10 258 #define ARM_IRQ_SEC_SGI_3 11 259 #define ARM_IRQ_SEC_SGI_4 12 260 #define ARM_IRQ_SEC_SGI_5 13 261 #define ARM_IRQ_SEC_SGI_6 14 262 #define ARM_IRQ_SEC_SGI_7 15 263 264 /* 265 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 266 * terminology. On a GICv2 system or mode, the lists will be merged and treated 267 * as Group 0 interrupts. 268 */ 269 #define ARM_G1S_IRQ_PROPS(grp) \ 270 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 271 GIC_INTR_CFG_LEVEL), \ 272 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 273 GIC_INTR_CFG_EDGE), \ 274 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 275 GIC_INTR_CFG_EDGE), \ 276 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 277 GIC_INTR_CFG_EDGE), \ 278 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 279 GIC_INTR_CFG_EDGE), \ 280 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 281 GIC_INTR_CFG_EDGE), \ 282 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 283 GIC_INTR_CFG_EDGE) 284 285 #define ARM_G0_IRQ_PROPS(grp) \ 286 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ 287 GIC_INTR_CFG_EDGE), \ 288 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 289 GIC_INTR_CFG_EDGE) 290 291 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 292 ARM_SHARED_RAM_BASE, \ 293 ARM_SHARED_RAM_SIZE, \ 294 MT_DEVICE | MT_RW | EL3_PAS) 295 296 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 297 ARM_NS_DRAM1_BASE, \ 298 ARM_NS_DRAM1_SIZE, \ 299 MT_MEMORY | MT_RW | MT_NS) 300 301 #define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ 302 ARM_DRAM2_BASE, \ 303 ARM_DRAM2_SIZE, \ 304 MT_MEMORY | MT_RW | MT_NS) 305 306 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 307 TSP_SEC_MEM_BASE, \ 308 TSP_SEC_MEM_SIZE, \ 309 MT_MEMORY | MT_RW | MT_SECURE) 310 311 #if ARM_BL31_IN_DRAM 312 #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ 313 BL31_BASE, \ 314 PLAT_ARM_MAX_BL31_SIZE, \ 315 MT_MEMORY | MT_RW | MT_SECURE) 316 #endif 317 318 #define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ 319 ARM_EL3_TZC_DRAM1_BASE, \ 320 ARM_EL3_TZC_DRAM1_SIZE, \ 321 MT_MEMORY | MT_RW | EL3_PAS) 322 323 #define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \ 324 PLAT_ARM_TRUSTED_DRAM_BASE, \ 325 PLAT_ARM_TRUSTED_DRAM_SIZE, \ 326 MT_MEMORY | MT_RW | MT_SECURE) 327 328 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 329 MEASURED_BOOT 330 #define ARM_MAP_EVENT_LOG_DRAM1 \ 331 MAP_REGION_FLAT( \ 332 ARM_EVENT_LOG_DRAM1_BASE, \ 333 ARM_EVENT_LOG_DRAM1_SIZE, \ 334 MT_MEMORY | MT_RW | MT_SECURE) 335 #endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && MEASURED_BOOT */ 336 337 #if ENABLE_RME 338 /* 339 * We add the EL3_RMM_SHARED size to RMM mapping to map the region as a block. 340 * Else we end up requiring more pagetables in BL2 for ROMLIB build. 341 */ 342 #define ARM_MAP_RMM_DRAM MAP_REGION_FLAT( \ 343 PLAT_ARM_RMM_BASE, \ 344 (PLAT_ARM_RMM_SIZE + \ 345 ARM_EL3_RMM_SHARED_SIZE), \ 346 MT_MEMORY | MT_RW | MT_REALM) 347 348 349 #define ARM_MAP_GPT_L1_DRAM MAP_REGION_FLAT( \ 350 ARM_L1_GPT_ADDR_BASE, \ 351 ARM_L1_GPT_SIZE, \ 352 MT_MEMORY | MT_RW | EL3_PAS) 353 354 #define ARM_MAP_EL3_RMM_SHARED_MEM \ 355 MAP_REGION_FLAT( \ 356 ARM_EL3_RMM_SHARED_BASE, \ 357 ARM_EL3_RMM_SHARED_SIZE, \ 358 MT_MEMORY | MT_RW | MT_REALM) 359 360 #endif /* ENABLE_RME */ 361 362 /* 363 * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to 364 * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides 365 * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order 366 * to be able to access the heap. 367 */ 368 #define ARM_MAP_BL1_RW MAP_REGION_FLAT( \ 369 BL1_RW_BASE, \ 370 BL1_RW_LIMIT - BL1_RW_BASE, \ 371 MT_MEMORY | MT_RW | EL3_PAS) 372 373 /* 374 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section 375 * otherwise one region is defined containing both. 376 */ 377 #if SEPARATE_CODE_AND_RODATA 378 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 379 BL_CODE_BASE, \ 380 BL_CODE_END - BL_CODE_BASE, \ 381 MT_CODE | EL3_PAS), \ 382 MAP_REGION_FLAT( \ 383 BL_RO_DATA_BASE, \ 384 BL_RO_DATA_END \ 385 - BL_RO_DATA_BASE, \ 386 MT_RO_DATA | EL3_PAS) 387 #else 388 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 389 BL_CODE_BASE, \ 390 BL_CODE_END - BL_CODE_BASE, \ 391 MT_CODE | EL3_PAS) 392 #endif 393 #if USE_COHERENT_MEM 394 #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 395 BL_COHERENT_RAM_BASE, \ 396 BL_COHERENT_RAM_END \ 397 - BL_COHERENT_RAM_BASE, \ 398 MT_DEVICE | MT_RW | EL3_PAS) 399 #endif 400 #if USE_ROMLIB 401 #define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \ 402 ROMLIB_RO_BASE, \ 403 ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\ 404 MT_CODE | EL3_PAS) 405 406 #define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \ 407 ROMLIB_RW_BASE, \ 408 ROMLIB_RW_END - ROMLIB_RW_BASE,\ 409 MT_MEMORY | MT_RW | EL3_PAS) 410 #endif 411 412 /* 413 * Map mem_protect flash region with read and write permissions 414 */ 415 #define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \ 416 V2M_FLASH_BLOCK_SIZE, \ 417 MT_DEVICE | MT_RW | MT_SECURE) 418 /* 419 * Map the region for device tree configuration with read and write permissions 420 */ 421 #define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \ 422 (ARM_FW_CONFIGS_LIMIT \ 423 - ARM_BL_RAM_BASE), \ 424 MT_MEMORY | MT_RW | EL3_PAS) 425 /* 426 * Map L0_GPT with read and write permissions 427 */ 428 #if ENABLE_RME 429 #define ARM_MAP_L0_GPT_REGION MAP_REGION_FLAT(ARM_L0_GPT_ADDR_BASE, \ 430 ARM_L0_GPT_SIZE, \ 431 MT_MEMORY | MT_RW | MT_ROOT) 432 #endif 433 434 /* 435 * The max number of regions like RO(code), coherent and data required by 436 * different BL stages which need to be mapped in the MMU. 437 */ 438 #define ARM_BL_REGIONS 7 439 440 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 441 ARM_BL_REGIONS) 442 443 /* Memory mapped Generic timer interfaces */ 444 #ifdef PLAT_ARM_SYS_CNTCTL_BASE 445 #define ARM_SYS_CNTCTL_BASE PLAT_ARM_SYS_CNTCTL_BASE 446 #else 447 #define ARM_SYS_CNTCTL_BASE UL(0x2a430000) 448 #endif 449 450 #ifdef PLAT_ARM_SYS_CNTREAD_BASE 451 #define ARM_SYS_CNTREAD_BASE PLAT_ARM_SYS_CNTREAD_BASE 452 #else 453 #define ARM_SYS_CNTREAD_BASE UL(0x2a800000) 454 #endif 455 456 #ifdef PLAT_ARM_SYS_TIMCTL_BASE 457 #define ARM_SYS_TIMCTL_BASE PLAT_ARM_SYS_TIMCTL_BASE 458 #else 459 #define ARM_SYS_TIMCTL_BASE UL(0x2a810000) 460 #endif 461 462 #ifdef PLAT_ARM_SYS_CNT_BASE_S 463 #define ARM_SYS_CNT_BASE_S PLAT_ARM_SYS_CNT_BASE_S 464 #else 465 #define ARM_SYS_CNT_BASE_S UL(0x2a820000) 466 #endif 467 468 #ifdef PLAT_ARM_SYS_CNT_BASE_NS 469 #define ARM_SYS_CNT_BASE_NS PLAT_ARM_SYS_CNT_BASE_NS 470 #else 471 #define ARM_SYS_CNT_BASE_NS UL(0x2a830000) 472 #endif 473 474 #define ARM_CONSOLE_BAUDRATE 115200 475 476 /* Trusted Watchdog constants */ 477 #ifdef PLAT_ARM_SP805_TWDG_BASE 478 #define ARM_SP805_TWDG_BASE PLAT_ARM_SP805_TWDG_BASE 479 #else 480 #define ARM_SP805_TWDG_BASE UL(0x2a490000) 481 #endif 482 #define ARM_SP805_TWDG_CLK_HZ 32768 483 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 484 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ 485 #define ARM_TWDG_TIMEOUT_SEC 128 486 #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ 487 ARM_TWDG_TIMEOUT_SEC) 488 489 /****************************************************************************** 490 * Required platform porting definitions common to all ARM standard platforms 491 *****************************************************************************/ 492 493 /* 494 * This macro defines the deepest retention state possible. A higher state 495 * id will represent an invalid or a power down state. 496 */ 497 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 498 499 /* 500 * This macro defines the deepest power down states possible. Any state ID 501 * higher than this is invalid. 502 */ 503 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 504 505 /* 506 * Some data must be aligned on the biggest cache line size in the platform. 507 * This is known only to the platform as it might have a combination of 508 * integrated and external caches. 509 */ 510 #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) 511 512 /* 513 * To enable FW_CONFIG to be loaded by BL1, define the corresponding base 514 * and limit. Leave enough space of BL2 meminfo. 515 */ 516 #define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) 517 #define ARM_FW_CONFIG_LIMIT ((ARM_BL_RAM_BASE + PAGE_SIZE) \ 518 + (PAGE_SIZE / 2U)) 519 520 /* 521 * Boot parameters passed from BL2 to BL31/BL32 are stored here 522 */ 523 #define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT) 524 #define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \ 525 + (PAGE_SIZE / 2U)) 526 527 /* 528 * Define limit of firmware configuration memory: 529 * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory 530 */ 531 #define ARM_FW_CONFIGS_SIZE (PAGE_SIZE * 2) 532 #define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + ARM_FW_CONFIGS_SIZE) 533 534 #if ENABLE_RME 535 /* 536 * Store the L0 GPT on Trusted SRAM next to firmware 537 * configuration memory, 4KB aligned. 538 */ 539 #define ARM_L0_GPT_SIZE (PAGE_SIZE) 540 #define ARM_L0_GPT_ADDR_BASE (ARM_FW_CONFIGS_LIMIT) 541 #define ARM_L0_GPT_LIMIT (ARM_L0_GPT_ADDR_BASE + ARM_L0_GPT_SIZE) 542 #else 543 #define ARM_L0_GPT_SIZE U(0) 544 #endif 545 546 /******************************************************************************* 547 * BL1 specific defines. 548 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 549 * addresses. 550 ******************************************************************************/ 551 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 552 #ifdef PLAT_BL1_RO_LIMIT 553 #define BL1_RO_LIMIT PLAT_BL1_RO_LIMIT 554 #else 555 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ 556 + (PLAT_ARM_TRUSTED_ROM_SIZE - \ 557 PLAT_ARM_MAX_ROMLIB_RO_SIZE)) 558 #endif 559 560 /* 561 * Put BL1 RW at the top of the Trusted SRAM. 562 */ 563 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 564 ARM_BL_RAM_SIZE - \ 565 (PLAT_ARM_MAX_BL1_RW_SIZE +\ 566 PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 567 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ 568 (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 569 570 #define ROMLIB_RO_BASE BL1_RO_LIMIT 571 #define ROMLIB_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE) 572 573 #define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE) 574 #define ROMLIB_RW_END (ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE) 575 576 /******************************************************************************* 577 * BL2 specific defines. 578 ******************************************************************************/ 579 #if RESET_TO_BL2 580 #if ENABLE_PIE 581 /* 582 * As the BL31 image size appears to be increased when built with the ENABLE_PIE 583 * option, set BL2 base address to have enough space for BL31 in Trusted SRAM. 584 */ 585 #define BL2_OFFSET (0x5000) 586 #else 587 /* Put BL2 towards the middle of the Trusted SRAM */ 588 #define BL2_OFFSET (0x2000) 589 #endif /* ENABLE_PIE */ 590 591 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ 592 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \ 593 BL2_OFFSET) 594 #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 595 596 #else 597 /* 598 * Put BL2 just below BL1. 599 */ 600 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) 601 #define BL2_LIMIT BL1_RW_BASE 602 #endif 603 604 /******************************************************************************* 605 * BL31 specific defines. 606 ******************************************************************************/ 607 #if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION 608 /* 609 * Put BL31 at the bottom of TZC secured DRAM 610 */ 611 #define BL31_BASE ARM_AP_TZC_DRAM1_BASE 612 #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 613 PLAT_ARM_MAX_BL31_SIZE) 614 /* 615 * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM. 616 * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten. 617 */ 618 #if SEPARATE_NOBITS_REGION 619 #define BL31_NOBITS_BASE BL2_BASE 620 #define BL31_NOBITS_LIMIT BL2_LIMIT 621 #endif /* SEPARATE_NOBITS_REGION */ 622 #elif (RESET_TO_BL31) 623 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 624 # if !ENABLE_PIE 625 # error "BL31 must be a PIE if RESET_TO_BL31=1." 626 #endif 627 /* 628 * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely 629 * used for building BL31 and not used for loading BL31. 630 */ 631 # define BL31_BASE 0x0 632 # define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE 633 #else 634 /* Put BL31 below BL2 in the Trusted SRAM.*/ 635 #define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 636 - PLAT_ARM_MAX_BL31_SIZE) 637 #define BL31_PROGBITS_LIMIT BL2_BASE 638 /* 639 * For RESET_TO_BL2 make sure the BL31 can grow up until BL2_BASE. 640 * This is because in the RESET_TO_BL2 configuration, 641 * BL2 is always resident. 642 */ 643 #if RESET_TO_BL2 644 #define BL31_LIMIT BL2_BASE 645 #else 646 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 647 #endif 648 #endif 649 650 /****************************************************************************** 651 * RMM specific defines 652 *****************************************************************************/ 653 #if ENABLE_RME 654 #define RMM_BASE (ARM_REALM_BASE) 655 #define RMM_LIMIT (RMM_BASE + ARM_REALM_SIZE) 656 #define RMM_SHARED_BASE (ARM_EL3_RMM_SHARED_BASE) 657 #define RMM_SHARED_SIZE (ARM_EL3_RMM_SHARED_SIZE) 658 #endif 659 660 #if !defined(__aarch64__) || JUNO_AARCH32_EL3_RUNTIME 661 /******************************************************************************* 662 * BL32 specific defines for EL3 runtime in AArch32 mode 663 ******************************************************************************/ 664 # if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME 665 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 666 # if !ENABLE_PIE 667 # error "BL32 must be a PIE if RESET_TO_SP_MIN=1." 668 #endif 669 /* 670 * Since this is PIE, we can define BL32_BASE to 0x0 since this macro is solely 671 * used for building BL32 and not used for loading BL32. 672 */ 673 # define BL32_BASE 0x0 674 # define BL32_LIMIT PLAT_ARM_MAX_BL32_SIZE 675 # else 676 /* Put BL32 below BL2 in the Trusted SRAM.*/ 677 # define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 678 - PLAT_ARM_MAX_BL32_SIZE) 679 # define BL32_PROGBITS_LIMIT BL2_BASE 680 # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 681 # endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */ 682 683 #else 684 /******************************************************************************* 685 * BL32 specific defines for EL3 runtime in AArch64 mode 686 ******************************************************************************/ 687 /* 688 * On ARM standard platforms, the TSP can execute from Trusted SRAM, 689 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone 690 * controller. 691 */ 692 # if SPM_MM || SPMC_AT_EL3 693 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 694 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 695 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 696 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 697 ARM_AP_TZC_DRAM1_SIZE) 698 # elif defined(SPD_spmd) 699 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 700 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 701 # define BL32_BASE PLAT_ARM_SPMC_BASE 702 # define BL32_LIMIT (PLAT_ARM_SPMC_BASE + \ 703 PLAT_ARM_SPMC_SIZE) 704 # elif ARM_BL31_IN_DRAM 705 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ 706 PLAT_ARM_MAX_BL31_SIZE) 707 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \ 708 PLAT_ARM_MAX_BL31_SIZE) 709 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \ 710 PLAT_ARM_MAX_BL31_SIZE) 711 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 712 ARM_AP_TZC_DRAM1_SIZE) 713 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID 714 # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE 715 # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE 716 # define TSP_PROGBITS_LIMIT BL31_BASE 717 # define BL32_BASE ARM_FW_CONFIGS_LIMIT 718 # define BL32_LIMIT BL31_BASE 719 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID 720 # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE 721 # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE 722 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 723 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 724 + SZ_4M) 725 # elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID 726 # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 727 # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 728 # define BL32_BASE ARM_AP_TZC_DRAM1_BASE 729 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 730 ARM_AP_TZC_DRAM1_SIZE) 731 # else 732 # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" 733 # endif 734 #endif /* !__aarch64__ || JUNO_AARCH32_EL3_RUNTIME */ 735 736 /* 737 * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no 738 * SPD and no SPM-MM and no SPMC-AT-EL3, as they are the only ones that can be 739 * used as BL32. 740 */ 741 #if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME 742 # if defined(SPD_none) && !SPM_MM && !SPMC_AT_EL3 743 # undef BL32_BASE 744 # endif /* defined(SPD_none) && !SPM_MM || !SPMC_AT_EL3 */ 745 #endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */ 746 747 /******************************************************************************* 748 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. 749 ******************************************************************************/ 750 #define BL2U_BASE BL2_BASE 751 #define BL2U_LIMIT BL2_LIMIT 752 753 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE 754 #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000)) 755 756 /* 757 * ID of the secure physical generic timer interrupt used by the TSP. 758 */ 759 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 760 761 762 /* 763 * One cache line needed for bakery locks on ARM platforms 764 */ 765 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 766 767 /* Priority levels for ARM platforms */ 768 #if ENABLE_FEAT_RAS && FFH_SUPPORT 769 #define PLAT_RAS_PRI 0x10 770 #endif 771 #define PLAT_SDEI_CRITICAL_PRI 0x60 772 #define PLAT_SDEI_NORMAL_PRI 0x70 773 774 /* CPU Fault Handling Interrupt(FHI) PPI interrupt ID */ 775 #define PLAT_CORE_FAULT_IRQ 17 776 777 /* ARM platforms use 3 upper bits of secure interrupt priority */ 778 #define PLAT_PRI_BITS 3 779 780 /* SGI used for SDEI signalling */ 781 #define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0 782 783 #if SDEI_IN_FCONF 784 /* ARM SDEI dynamic private event max count */ 785 #define ARM_SDEI_DP_EVENT_MAX_CNT 3 786 787 /* ARM SDEI dynamic shared event max count */ 788 #define ARM_SDEI_DS_EVENT_MAX_CNT 3 789 #else 790 /* ARM SDEI dynamic private event numbers */ 791 #define ARM_SDEI_DP_EVENT_0 1000 792 #define ARM_SDEI_DP_EVENT_1 1001 793 #define ARM_SDEI_DP_EVENT_2 1002 794 795 /* ARM SDEI dynamic shared event numbers */ 796 #define ARM_SDEI_DS_EVENT_0 2000 797 #define ARM_SDEI_DS_EVENT_1 2001 798 #define ARM_SDEI_DS_EVENT_2 2002 799 800 #define ARM_SDEI_PRIVATE_EVENTS \ 801 SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ 802 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 803 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 804 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 805 806 #define ARM_SDEI_SHARED_EVENTS \ 807 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 808 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 809 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 810 #endif /* SDEI_IN_FCONF */ 811 812 #endif /* ARM_DEF_H */ 813
