1 /* 2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the 14 * distribution. 15 * 16 * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 #ifndef __HW_APPS_RCM_H__ 35 #define __HW_APPS_RCM_H__ 36 37 //***************************************************************************** 38 // 39 // The following are defines for the APPS_RCM register offsets. 40 // 41 //***************************************************************************** 42 #define APPS_RCM_O_CAMERA_CLK_GEN \ 43 0x00000000 44 45 #define APPS_RCM_O_CAMERA_CLK_GATING \ 46 0x00000004 47 48 #define APPS_RCM_O_CAMERA_SOFT_RESET \ 49 0x00000008 50 51 #define APPS_RCM_O_MCASP_CLK_GATING \ 52 0x00000014 53 54 #define APPS_RCM_O_MCASP_SOFT_RESET \ 55 0x00000018 56 57 #define APPS_RCM_O_MMCHS_CLK_GEN \ 58 0x00000020 59 60 #define APPS_RCM_O_MMCHS_CLK_GATING \ 61 0x00000024 62 63 #define APPS_RCM_O_MMCHS_SOFT_RESET \ 64 0x00000028 65 66 #define APPS_RCM_O_MCSPI_A1_CLK_GEN \ 67 0x0000002C 68 69 #define APPS_RCM_O_MCSPI_A1_CLK_GATING \ 70 0x00000030 71 72 #define APPS_RCM_O_MCSPI_A1_SOFT_RESET \ 73 0x00000034 74 75 #define APPS_RCM_O_MCSPI_A2_CLK_GEN \ 76 0x00000038 77 78 #define APPS_RCM_O_MCSPI_A2_CLK_GATING \ 79 0x00000040 80 81 #define APPS_RCM_O_MCSPI_A2_SOFT_RESET \ 82 0x00000044 83 84 #define APPS_RCM_O_UDMA_A_CLK_GATING \ 85 0x00000048 86 87 #define APPS_RCM_O_UDMA_A_SOFT_RESET \ 88 0x0000004C 89 90 #define APPS_RCM_O_GPIO_A_CLK_GATING \ 91 0x00000050 92 93 #define APPS_RCM_O_GPIO_A_SOFT_RESET \ 94 0x00000054 95 96 #define APPS_RCM_O_GPIO_B_CLK_GATING \ 97 0x00000058 98 99 #define APPS_RCM_O_GPIO_B_SOFT_RESET \ 100 0x0000005C 101 102 #define APPS_RCM_O_GPIO_C_CLK_GATING \ 103 0x00000060 104 105 #define APPS_RCM_O_GPIO_C_SOFT_RESET \ 106 0x00000064 107 108 #define APPS_RCM_O_GPIO_D_CLK_GATING \ 109 0x00000068 110 111 #define APPS_RCM_O_GPIO_D_SOFT_RESET \ 112 0x0000006C 113 114 #define APPS_RCM_O_GPIO_E_CLK_GATING \ 115 0x00000070 116 117 #define APPS_RCM_O_GPIO_E_SOFT_RESET \ 118 0x00000074 119 120 #define APPS_RCM_O_WDOG_A_CLK_GATING \ 121 0x00000078 122 123 #define APPS_RCM_O_WDOG_A_SOFT_RESET \ 124 0x0000007C 125 126 #define APPS_RCM_O_UART_A0_CLK_GATING \ 127 0x00000080 128 129 #define APPS_RCM_O_UART_A0_SOFT_RESET \ 130 0x00000084 131 132 #define APPS_RCM_O_UART_A1_CLK_GATING \ 133 0x00000088 134 135 #define APPS_RCM_O_UART_A1_SOFT_RESET \ 136 0x0000008C 137 138 #define APPS_RCM_O_GPT_A0_CLK_GATING \ 139 0x00000090 140 141 #define APPS_RCM_O_GPT_A0_SOFT_RESET \ 142 0x00000094 143 144 #define APPS_RCM_O_GPT_A1_CLK_GATING \ 145 0x00000098 146 147 #define APPS_RCM_O_GPT_A1_SOFT_RESET \ 148 0x0000009C 149 150 #define APPS_RCM_O_GPT_A2_CLK_GATING \ 151 0x000000A0 152 153 #define APPS_RCM_O_GPT_A2_SOFT_RESET \ 154 0x000000A4 155 156 #define APPS_RCM_O_GPT_A3_CLK_GATING \ 157 0x000000A8 158 159 #define APPS_RCM_O_GPT_A3_SOFT_RESET \ 160 0x000000AC 161 162 #define APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0 \ 163 0x000000B0 164 165 #define APPS_RCM_O_MCASP_FRAC_CLK_CONFIG1 \ 166 0x000000B4 167 168 #define APPS_RCM_O_CRYPTO_CLK_GATING \ 169 0x000000B8 170 171 #define APPS_RCM_O_CRYPTO_SOFT_RESET \ 172 0x000000BC 173 174 #define APPS_RCM_O_MCSPI_S0_CLK_GATING \ 175 0x000000C8 176 177 #define APPS_RCM_O_MCSPI_S0_SOFT_RESET \ 178 0x000000CC 179 180 #define APPS_RCM_O_MCSPI_S0_CLKDIV_CFG \ 181 0x000000D0 182 183 #define APPS_RCM_O_I2C_CLK_GATING \ 184 0x000000D8 185 186 #define APPS_RCM_O_I2C_SOFT_RESET \ 187 0x000000DC 188 189 #define APPS_RCM_O_APPS_LPDS_REQ \ 190 0x000000E4 191 192 #define APPS_RCM_O_APPS_TURBO_REQ \ 193 0x000000EC 194 195 #define APPS_RCM_O_APPS_DSLP_WAKE_CONFIG \ 196 0x00000108 197 198 #define APPS_RCM_O_APPS_DSLP_WAKE_TIMER_CFG \ 199 0x0000010C 200 201 #define APPS_RCM_O_APPS_RCM_SLP_WAKE_ENABLE \ 202 0x00000110 203 204 #define APPS_RCM_O_APPS_SLP_WAKETIMER_CFG \ 205 0x00000114 206 207 #define APPS_RCM_O_APPS_TO_NWP_WAKE_REQUEST \ 208 0x00000118 209 210 #define APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS \ 211 0x00000120 212 213 #define APPS_RCM_O_APPS_RCM_INTERRUPT_ENABLE \ 214 0x00000124 215 216 217 218 219 220 //****************************************************************************** 221 // 222 // The following are defines for the bit fields in the 223 // APPS_RCM_O_CAMERA_CLK_GEN register. 224 // 225 //****************************************************************************** 226 #define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_OFF_TIME_M \ 227 0x00000700 // Configuration of OFF-TIME for 228 // dividing PLL clk (240 MHz) in 229 // generation of Camera func-clk : 230 // "000" - 1 "001" - 2 "010" - 3 231 // "011" - 4 "100" - 5 "101" - 6 232 // "110" - 7 "111" - 8 233 234 #define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_OFF_TIME_S 8 235 #define APPS_RCM_CAMERA_CLK_GEN_NU1_M \ 236 0x000000F8 237 238 #define APPS_RCM_CAMERA_CLK_GEN_NU1_S 3 239 #define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_ON_TIME_M \ 240 0x00000007 // Configuration of ON-TIME for 241 // dividing PLL clk (240 MHz) in 242 // generation of Camera func-clk : 243 // "000" - 1 "001" - 2 "010" - 3 244 // "011" - 4 "100" - 5 "101" - 6 245 // "110" - 7 "111" - 8 246 247 #define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_ON_TIME_S 0 248 //****************************************************************************** 249 // 250 // The following are defines for the bit fields in the 251 // APPS_RCM_O_CAMERA_CLK_GATING register. 252 // 253 //****************************************************************************** 254 #define APPS_RCM_CAMERA_CLK_GATING_NU1_M \ 255 0x00FE0000 256 257 #define APPS_RCM_CAMERA_CLK_GATING_NU1_S 17 258 #define APPS_RCM_CAMERA_CLK_GATING_CAMERA_DSLP_CLK_ENABLE \ 259 0x00010000 // 0 - Disable camera clk during 260 // deep-sleep mode 261 262 #define APPS_RCM_CAMERA_CLK_GATING_NU2_M \ 263 0x0000FE00 264 265 #define APPS_RCM_CAMERA_CLK_GATING_NU2_S 9 266 #define APPS_RCM_CAMERA_CLK_GATING_CAMERA_SLP_CLK_ENABLE \ 267 0x00000100 // 1- Enable camera clk during 268 // sleep mode ; 0- Disable camera 269 // clk during sleep mode 270 271 #define APPS_RCM_CAMERA_CLK_GATING_NU3_M \ 272 0x000000FE 273 274 #define APPS_RCM_CAMERA_CLK_GATING_NU3_S 1 275 #define APPS_RCM_CAMERA_CLK_GATING_CAMERA_RUN_CLK_ENABLE \ 276 0x00000001 // 1- Enable camera clk during run 277 // mode ; 0- Disable camera clk 278 // during run mode 279 280 //****************************************************************************** 281 // 282 // The following are defines for the bit fields in the 283 // APPS_RCM_O_CAMERA_SOFT_RESET register. 284 // 285 //****************************************************************************** 286 #define APPS_RCM_CAMERA_SOFT_RESET_CAMERA_ENABLED_STATUS \ 287 0x00000002 // 1 - Camera clocks/resets are 288 // enabled ; 0 - Camera 289 // clocks/resets are disabled 290 291 #define APPS_RCM_CAMERA_SOFT_RESET_CAMERA_SOFT_RESET \ 292 0x00000001 // 1 - Assert reset for Camera-core 293 // ; 0 - De-assert reset for 294 // Camera-core 295 296 //****************************************************************************** 297 // 298 // The following are defines for the bit fields in the 299 // APPS_RCM_O_MCASP_CLK_GATING register. 300 // 301 //****************************************************************************** 302 #define APPS_RCM_MCASP_CLK_GATING_NU1_M \ 303 0x00FE0000 304 305 #define APPS_RCM_MCASP_CLK_GATING_NU1_S 17 306 #define APPS_RCM_MCASP_CLK_GATING_MCASP_DSLP_CLK_ENABLE \ 307 0x00010000 // 0 - Disable MCASP clk during 308 // deep-sleep mode 309 310 #define APPS_RCM_MCASP_CLK_GATING_NU2_M \ 311 0x0000FE00 312 313 #define APPS_RCM_MCASP_CLK_GATING_NU2_S 9 314 #define APPS_RCM_MCASP_CLK_GATING_MCASP_SLP_CLK_ENABLE \ 315 0x00000100 // 1- Enable MCASP clk during sleep 316 // mode ; 0- Disable MCASP clk 317 // during sleep mode 318 319 #define APPS_RCM_MCASP_CLK_GATING_NU3_M \ 320 0x000000FE 321 322 #define APPS_RCM_MCASP_CLK_GATING_NU3_S 1 323 #define APPS_RCM_MCASP_CLK_GATING_MCASP_RUN_CLK_ENABLE \ 324 0x00000001 // 1- Enable MCASP clk during run 325 // mode ; 0- Disable MCASP clk 326 // during run mode 327 328 //****************************************************************************** 329 // 330 // The following are defines for the bit fields in the 331 // APPS_RCM_O_MCASP_SOFT_RESET register. 332 // 333 //****************************************************************************** 334 #define APPS_RCM_MCASP_SOFT_RESET_MCASP_ENABLED_STATUS \ 335 0x00000002 // 1 - MCASP Clocks/resets are 336 // enabled ; 0 - MCASP Clocks/resets 337 // are disabled 338 339 #define APPS_RCM_MCASP_SOFT_RESET_MCASP_SOFT_RESET \ 340 0x00000001 // 1 - Assert reset for MCASP-core 341 // ; 0 - De-assert reset for 342 // MCASP-core 343 344 //****************************************************************************** 345 // 346 // The following are defines for the bit fields in the 347 // APPS_RCM_O_MMCHS_CLK_GEN register. 348 // 349 //****************************************************************************** 350 #define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_OFF_TIME_M \ 351 0x00000700 // Configuration of OFF-TIME for 352 // dividing PLL clk (240 MHz) in 353 // generation of MMCHS func-clk : 354 // "000" - 1 "001" - 2 "010" - 3 355 // "011" - 4 "100" - 5 "101" - 6 356 // "110" - 7 "111" - 8 357 358 #define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_OFF_TIME_S 8 359 #define APPS_RCM_MMCHS_CLK_GEN_NU1_M \ 360 0x000000F8 361 362 #define APPS_RCM_MMCHS_CLK_GEN_NU1_S 3 363 #define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_ON_TIME_M \ 364 0x00000007 // Configuration of ON-TIME for 365 // dividing PLL clk (240 MHz) in 366 // generation of MMCHS func-clk : 367 // "000" - 1 "001" - 2 "010" - 3 368 // "011" - 4 "100" - 5 "101" - 6 369 // "110" - 7 "111" - 8 370 371 #define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_ON_TIME_S 0 372 //****************************************************************************** 373 // 374 // The following are defines for the bit fields in the 375 // APPS_RCM_O_MMCHS_CLK_GATING register. 376 // 377 //****************************************************************************** 378 #define APPS_RCM_MMCHS_CLK_GATING_NU1_M \ 379 0x00FE0000 380 381 #define APPS_RCM_MMCHS_CLK_GATING_NU1_S 17 382 #define APPS_RCM_MMCHS_CLK_GATING_MMCHS_DSLP_CLK_ENABLE \ 383 0x00010000 // 0 - Disable MMCHS clk during 384 // deep-sleep mode 385 386 #define APPS_RCM_MMCHS_CLK_GATING_NU2_M \ 387 0x0000FE00 388 389 #define APPS_RCM_MMCHS_CLK_GATING_NU2_S 9 390 #define APPS_RCM_MMCHS_CLK_GATING_MMCHS_SLP_CLK_ENABLE \ 391 0x00000100 // 1- Enable MMCHS clk during sleep 392 // mode ; 0- Disable MMCHS clk 393 // during sleep mode 394 395 #define APPS_RCM_MMCHS_CLK_GATING_NU3_M \ 396 0x000000FE 397 398 #define APPS_RCM_MMCHS_CLK_GATING_NU3_S 1 399 #define APPS_RCM_MMCHS_CLK_GATING_MMCHS_RUN_CLK_ENABLE \ 400 0x00000001 // 1- Enable MMCHS clk during run 401 // mode ; 0- Disable MMCHS clk 402 // during run mode 403 404 //****************************************************************************** 405 // 406 // The following are defines for the bit fields in the 407 // APPS_RCM_O_MMCHS_SOFT_RESET register. 408 // 409 //****************************************************************************** 410 #define APPS_RCM_MMCHS_SOFT_RESET_MMCHS_ENABLED_STATUS \ 411 0x00000002 // 1 - MMCHS Clocks/resets are 412 // enabled ; 0 - MMCHS Clocks/resets 413 // are disabled 414 415 #define APPS_RCM_MMCHS_SOFT_RESET_MMCHS_SOFT_RESET \ 416 0x00000001 // 1 - Assert reset for MMCHS-core 417 // ; 0 - De-assert reset for 418 // MMCHS-core 419 420 //****************************************************************************** 421 // 422 // The following are defines for the bit fields in the 423 // APPS_RCM_O_MCSPI_A1_CLK_GEN register. 424 // 425 //****************************************************************************** 426 #define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_BAUD_CLK_SEL \ 427 0x00010000 // 0 - XTAL clk is used as baud clk 428 // for MCSPI_A1 ; 1 - PLL divclk is 429 // used as baud clk for MCSPI_A1. 430 431 #define APPS_RCM_MCSPI_A1_CLK_GEN_NU1_M \ 432 0x0000F800 433 434 #define APPS_RCM_MCSPI_A1_CLK_GEN_NU1_S 11 435 #define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_OFF_TIME_M \ 436 0x00000700 // Configuration of OFF-TIME for 437 // dividing PLL clk (240 MHz) in 438 // generation of MCSPI_A1 func-clk : 439 // "000" - 1 "001" - 2 "010" - 3 440 // "011" - 4 "100" - 5 "101" - 6 441 // "110" - 7 "111" - 8 442 443 #define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_OFF_TIME_S 8 444 #define APPS_RCM_MCSPI_A1_CLK_GEN_NU2_M \ 445 0x000000F8 446 447 #define APPS_RCM_MCSPI_A1_CLK_GEN_NU2_S 3 448 #define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_ON_TIME_M \ 449 0x00000007 // Configuration of ON-TIME for 450 // dividing PLL clk (240 MHz) in 451 // generation of MCSPI_A1 func-clk : 452 // "000" - 1 "001" - 2 "010" - 3 453 // "011" - 4 "100" - 5 "101" - 6 454 // "110" - 7 "111" - 8 455 456 #define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_ON_TIME_S 0 457 //****************************************************************************** 458 // 459 // The following are defines for the bit fields in the 460 // APPS_RCM_O_MCSPI_A1_CLK_GATING register. 461 // 462 //****************************************************************************** 463 #define APPS_RCM_MCSPI_A1_CLK_GATING_NU1_M \ 464 0x00FE0000 465 466 #define APPS_RCM_MCSPI_A1_CLK_GATING_NU1_S 17 467 #define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_DSLP_CLK_ENABLE \ 468 0x00010000 // 0 - Disable MCSPI_A1 clk during 469 // deep-sleep mode 470 471 #define APPS_RCM_MCSPI_A1_CLK_GATING_NU2_M \ 472 0x0000FE00 473 474 #define APPS_RCM_MCSPI_A1_CLK_GATING_NU2_S 9 475 #define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_SLP_CLK_ENABLE \ 476 0x00000100 // 1- Enable MCSPI_A1 clk during 477 // sleep mode ; 0- Disable MCSPI_A1 478 // clk during sleep mode 479 480 #define APPS_RCM_MCSPI_A1_CLK_GATING_NU3_M \ 481 0x000000FE 482 483 #define APPS_RCM_MCSPI_A1_CLK_GATING_NU3_S 1 484 #define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_RUN_CLK_ENABLE \ 485 0x00000001 // 1- Enable MCSPI_A1 clk during 486 // run mode ; 0- Disable MCSPI_A1 487 // clk during run mode 488 489 //****************************************************************************** 490 // 491 // The following are defines for the bit fields in the 492 // APPS_RCM_O_MCSPI_A1_SOFT_RESET register. 493 // 494 //****************************************************************************** 495 #define APPS_RCM_MCSPI_A1_SOFT_RESET_MCSPI_A1_ENABLED_STATUS \ 496 0x00000002 // 1 - MCSPI_A1 Clocks/Resets are 497 // enabled ; 0 - MCSPI_A1 498 // Clocks/Resets are disabled 499 500 #define APPS_RCM_MCSPI_A1_SOFT_RESET_MCSPI_A1_SOFT_RESET \ 501 0x00000001 // 1 - Assert reset for 502 // MCSPI_A1-core ; 0 - De-assert 503 // reset for MCSPI_A1-core 504 505 //****************************************************************************** 506 // 507 // The following are defines for the bit fields in the 508 // APPS_RCM_O_MCSPI_A2_CLK_GEN register. 509 // 510 //****************************************************************************** 511 #define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_BAUD_CLK_SEL \ 512 0x00010000 // 0 - XTAL clk is used as baud-clk 513 // for MCSPI_A2 ; 1 - PLL divclk is 514 // used as baud-clk for MCSPI_A2 515 516 #define APPS_RCM_MCSPI_A2_CLK_GEN_NU1_M \ 517 0x0000F800 518 519 #define APPS_RCM_MCSPI_A2_CLK_GEN_NU1_S 11 520 #define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_OFF_TIME_M \ 521 0x00000700 // Configuration of OFF-TIME for 522 // dividing PLL clk (240 MHz) in 523 // generation of MCSPI_A2 func-clk : 524 // "000" - 1 "001" - 2 "010" - 3 525 // "011" - 4 "100" - 5 "101" - 6 526 // "110" - 7 "111" - 8 527 528 #define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_OFF_TIME_S 8 529 #define APPS_RCM_MCSPI_A2_CLK_GEN_NU2_M \ 530 0x000000F8 531 532 #define APPS_RCM_MCSPI_A2_CLK_GEN_NU2_S 3 533 #define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_ON_TIME_M \ 534 0x00000007 // Configuration of OFF-TIME for 535 // dividing PLL clk (240 MHz) in 536 // generation of MCSPI_A2 func-clk : 537 // "000" - 1 "001" - 2 "010" - 3 538 // "011" - 4 "100" - 5 "101" - 6 539 // "110" - 7 "111" - 8 540 541 #define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_ON_TIME_S 0 542 //****************************************************************************** 543 // 544 // The following are defines for the bit fields in the 545 // APPS_RCM_O_MCSPI_A2_CLK_GATING register. 546 // 547 //****************************************************************************** 548 #define APPS_RCM_MCSPI_A2_CLK_GATING_NU1_M \ 549 0x00FE0000 550 551 #define APPS_RCM_MCSPI_A2_CLK_GATING_NU1_S 17 552 #define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_DSLP_CLK_ENABLE \ 553 0x00010000 // 0 - Disable MCSPI_A2 clk during 554 // deep-sleep mode 555 556 #define APPS_RCM_MCSPI_A2_CLK_GATING_NU2_M \ 557 0x0000FE00 558 559 #define APPS_RCM_MCSPI_A2_CLK_GATING_NU2_S 9 560 #define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_SLP_CLK_ENABLE \ 561 0x00000100 // 1- Enable MCSPI_A2 clk during 562 // sleep mode ; 0- Disable MCSPI_A2 563 // clk during sleep mode 564 565 #define APPS_RCM_MCSPI_A2_CLK_GATING_NU3_M \ 566 0x000000FE 567 568 #define APPS_RCM_MCSPI_A2_CLK_GATING_NU3_S 1 569 #define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_RUN_CLK_ENABLE \ 570 0x00000001 // 1- Enable MCSPI_A2 clk during 571 // run mode ; 0- Disable MCSPI_A2 572 // clk during run mode 573 574 //****************************************************************************** 575 // 576 // The following are defines for the bit fields in the 577 // APPS_RCM_O_MCSPI_A2_SOFT_RESET register. 578 // 579 //****************************************************************************** 580 #define APPS_RCM_MCSPI_A2_SOFT_RESET_MCSPI_A2_ENABLED_STATUS \ 581 0x00000002 // 1 - MCSPI_A2 Clocks/Resets are 582 // enabled ; 0 - MCSPI_A2 583 // Clocks/Resets are disabled 584 585 #define APPS_RCM_MCSPI_A2_SOFT_RESET_MCSPI_A2_SOFT_RESET \ 586 0x00000001 // 1 - Assert reset for 587 // MCSPI_A2-core ; 0 - De-assert 588 // reset for MCSPI_A2-core 589 590 //****************************************************************************** 591 // 592 // The following are defines for the bit fields in the 593 // APPS_RCM_O_UDMA_A_CLK_GATING register. 594 // 595 //****************************************************************************** 596 #define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_DSLP_CLK_ENABLE \ 597 0x00010000 // 1 - Enable UDMA_A clk during 598 // deep-sleep mode 0 - Disable 599 // UDMA_A clk during deep-sleep mode 600 // ; 601 602 #define APPS_RCM_UDMA_A_CLK_GATING_NU1_M \ 603 0x0000FE00 604 605 #define APPS_RCM_UDMA_A_CLK_GATING_NU1_S 9 606 #define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_SLP_CLK_ENABLE \ 607 0x00000100 // 1 - Enable UDMA_A clk during 608 // sleep mode 0 - Disable UDMA_A clk 609 // during sleep mode ; 610 611 #define APPS_RCM_UDMA_A_CLK_GATING_NU2_M \ 612 0x000000FE 613 614 #define APPS_RCM_UDMA_A_CLK_GATING_NU2_S 1 615 #define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_RUN_CLK_ENABLE \ 616 0x00000001 // 1 - Enable UDMA_A clk during run 617 // mode 0 - Disable UDMA_A clk 618 // during run mode ; 619 620 //****************************************************************************** 621 // 622 // The following are defines for the bit fields in the 623 // APPS_RCM_O_UDMA_A_SOFT_RESET register. 624 // 625 //****************************************************************************** 626 #define APPS_RCM_UDMA_A_SOFT_RESET_UDMA_A_ENABLED_STATUS \ 627 0x00000002 // 1 - UDMA_A Clocks/Resets are 628 // enabled ; 0 - UDMA_A 629 // Clocks/Resets are disabled 630 631 #define APPS_RCM_UDMA_A_SOFT_RESET_UDMA_A_SOFT_RESET \ 632 0x00000001 // 1 - Assert reset for DMA_A ; 0 - 633 // De-assert reset for DMA_A 634 635 //****************************************************************************** 636 // 637 // The following are defines for the bit fields in the 638 // APPS_RCM_O_GPIO_A_CLK_GATING register. 639 // 640 //****************************************************************************** 641 #define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_DSLP_CLK_ENABLE \ 642 0x00010000 // 1 - Enable GPIO_A clk during 643 // deep-sleep mode 0 - Disable 644 // GPIO_A clk during deep-sleep mode 645 // ; 646 647 #define APPS_RCM_GPIO_A_CLK_GATING_NU1_M \ 648 0x0000FE00 649 650 #define APPS_RCM_GPIO_A_CLK_GATING_NU1_S 9 651 #define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_SLP_CLK_ENABLE \ 652 0x00000100 // 1 - Enable GPIO_A clk during 653 // sleep mode 0 - Disable GPIO_A clk 654 // during sleep mode ; 655 656 #define APPS_RCM_GPIO_A_CLK_GATING_NU2_M \ 657 0x000000FE 658 659 #define APPS_RCM_GPIO_A_CLK_GATING_NU2_S 1 660 #define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_RUN_CLK_ENABLE \ 661 0x00000001 // 1 - Enable GPIO_A clk during run 662 // mode 0 - Disable GPIO_A clk 663 // during run mode ; 664 665 //****************************************************************************** 666 // 667 // The following are defines for the bit fields in the 668 // APPS_RCM_O_GPIO_A_SOFT_RESET register. 669 // 670 //****************************************************************************** 671 #define APPS_RCM_GPIO_A_SOFT_RESET_GPIO_A_ENABLED_STATUS \ 672 0x00000002 // 1 - GPIO_A Clocks/Resets are 673 // enabled ; 0 - GPIO_A 674 // Clocks/Resets are disabled 675 676 #define APPS_RCM_GPIO_A_SOFT_RESET_GPIO_A_SOFT_RESET \ 677 0x00000001 // 1 - Assert reset for GPIO_A ; 0 678 // - De-assert reset for GPIO_A 679 680 //****************************************************************************** 681 // 682 // The following are defines for the bit fields in the 683 // APPS_RCM_O_GPIO_B_CLK_GATING register. 684 // 685 //****************************************************************************** 686 #define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_DSLP_CLK_ENABLE \ 687 0x00010000 // 1 - Enable GPIO_B clk during 688 // deep-sleep mode 0 - Disable 689 // GPIO_B clk during deep-sleep mode 690 // ; 691 692 #define APPS_RCM_GPIO_B_CLK_GATING_NU1_M \ 693 0x0000FE00 694 695 #define APPS_RCM_GPIO_B_CLK_GATING_NU1_S 9 696 #define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_SLP_CLK_ENABLE \ 697 0x00000100 // 1 - Enable GPIO_B clk during 698 // sleep mode 0 - Disable GPIO_B clk 699 // during sleep mode ; 700 701 #define APPS_RCM_GPIO_B_CLK_GATING_NU2_M \ 702 0x000000FE 703 704 #define APPS_RCM_GPIO_B_CLK_GATING_NU2_S 1 705 #define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_RUN_CLK_ENABLE \ 706 0x00000001 // 1 - Enable GPIO_B clk during run 707 // mode 0 - Disable GPIO_B clk 708 // during run mode ; 709 710 //****************************************************************************** 711 // 712 // The following are defines for the bit fields in the 713 // APPS_RCM_O_GPIO_B_SOFT_RESET register. 714 // 715 //****************************************************************************** 716 #define APPS_RCM_GPIO_B_SOFT_RESET_GPIO_B_ENABLED_STATUS \ 717 0x00000002 // 1 - GPIO_B Clocks/Resets are 718 // enabled ; 0 - GPIO_B 719 // Clocks/Resets are disabled 720 721 #define APPS_RCM_GPIO_B_SOFT_RESET_GPIO_B_SOFT_RESET \ 722 0x00000001 // 1 - Assert reset for GPIO_B ; 0 723 // - De-assert reset for GPIO_B 724 725 //****************************************************************************** 726 // 727 // The following are defines for the bit fields in the 728 // APPS_RCM_O_GPIO_C_CLK_GATING register. 729 // 730 //****************************************************************************** 731 #define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_DSLP_CLK_ENABLE \ 732 0x00010000 // 1 - Enable GPIO_C clk during 733 // deep-sleep mode 0 - Disable 734 // GPIO_C clk during deep-sleep mode 735 // ; 736 737 #define APPS_RCM_GPIO_C_CLK_GATING_NU1_M \ 738 0x0000FE00 739 740 #define APPS_RCM_GPIO_C_CLK_GATING_NU1_S 9 741 #define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_SLP_CLK_ENABLE \ 742 0x00000100 // 1 - Enable GPIO_C clk during 743 // sleep mode 0 - Disable GPIO_C clk 744 // during sleep mode ; 745 746 #define APPS_RCM_GPIO_C_CLK_GATING_NU2_M \ 747 0x000000FE 748 749 #define APPS_RCM_GPIO_C_CLK_GATING_NU2_S 1 750 #define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_RUN_CLK_ENABLE \ 751 0x00000001 // 1 - Enable GPIO_C clk during run 752 // mode 0 - Disable GPIO_C clk 753 // during run mode ; 754 755 //****************************************************************************** 756 // 757 // The following are defines for the bit fields in the 758 // APPS_RCM_O_GPIO_C_SOFT_RESET register. 759 // 760 //****************************************************************************** 761 #define APPS_RCM_GPIO_C_SOFT_RESET_GPIO_C_ENABLED_STATUS \ 762 0x00000002 // 1 - GPIO_C Clocks/Resets are 763 // enabled ; 0 - GPIO_C 764 // Clocks/Resets are disabled 765 766 #define APPS_RCM_GPIO_C_SOFT_RESET_GPIO_C_SOFT_RESET \ 767 0x00000001 // 1 - Assert reset for GPIO_C ; 0 768 // - De-assert reset for GPIO_C 769 770 //****************************************************************************** 771 // 772 // The following are defines for the bit fields in the 773 // APPS_RCM_O_GPIO_D_CLK_GATING register. 774 // 775 //****************************************************************************** 776 #define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_DSLP_CLK_ENABLE \ 777 0x00010000 // 1 - Enable GPIO_D clk during 778 // deep-sleep mode 0 - Disable 779 // GPIO_D clk during deep-sleep mode 780 // ; 781 782 #define APPS_RCM_GPIO_D_CLK_GATING_NU1_M \ 783 0x0000FE00 784 785 #define APPS_RCM_GPIO_D_CLK_GATING_NU1_S 9 786 #define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_SLP_CLK_ENABLE \ 787 0x00000100 // 1 - Enable GPIO_D clk during 788 // sleep mode 0 - Disable GPIO_D clk 789 // during sleep mode ; 790 791 #define APPS_RCM_GPIO_D_CLK_GATING_NU2_M \ 792 0x000000FE 793 794 #define APPS_RCM_GPIO_D_CLK_GATING_NU2_S 1 795 #define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_RUN_CLK_ENABLE \ 796 0x00000001 // 1 - Enable GPIO_D clk during run 797 // mode 0 - Disable GPIO_D clk 798 // during run mode ; 799 800 //****************************************************************************** 801 // 802 // The following are defines for the bit fields in the 803 // APPS_RCM_O_GPIO_D_SOFT_RESET register. 804 // 805 //****************************************************************************** 806 #define APPS_RCM_GPIO_D_SOFT_RESET_GPIO_D_ENABLED_STATUS \ 807 0x00000002 // 1 - GPIO_D Clocks/Resets are 808 // enabled ; 0 - GPIO_D 809 // Clocks/Resets are disabled 810 811 #define APPS_RCM_GPIO_D_SOFT_RESET_GPIO_D_SOFT_RESET \ 812 0x00000001 // 1 - Assert reset for GPIO_D ; 0 813 // - De-assert reset for GPIO_D 814 815 //****************************************************************************** 816 // 817 // The following are defines for the bit fields in the 818 // APPS_RCM_O_GPIO_E_CLK_GATING register. 819 // 820 //****************************************************************************** 821 #define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_DSLP_CLK_ENABLE \ 822 0x00010000 // 1 - Enable GPIO_E clk during 823 // deep-sleep mode 0 - Disable 824 // GPIO_E clk during deep-sleep mode 825 // ; 826 827 #define APPS_RCM_GPIO_E_CLK_GATING_NU1_M \ 828 0x0000FE00 829 830 #define APPS_RCM_GPIO_E_CLK_GATING_NU1_S 9 831 #define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_SLP_CLK_ENABLE \ 832 0x00000100 // 1 - Enable GPIO_E clk during 833 // sleep mode 0 - Disable GPIO_E clk 834 // during sleep mode ; 835 836 #define APPS_RCM_GPIO_E_CLK_GATING_NU2_M \ 837 0x000000FE 838 839 #define APPS_RCM_GPIO_E_CLK_GATING_NU2_S 1 840 #define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_RUN_CLK_ENABLE \ 841 0x00000001 // 1 - Enable GPIO_E clk during run 842 // mode 0 - Disable GPIO_E clk 843 // during run mode ; 844 845 //****************************************************************************** 846 // 847 // The following are defines for the bit fields in the 848 // APPS_RCM_O_GPIO_E_SOFT_RESET register. 849 // 850 //****************************************************************************** 851 #define APPS_RCM_GPIO_E_SOFT_RESET_GPIO_E_ENABLED_STATUS \ 852 0x00000002 // 1 - GPIO_E Clocks/Resets are 853 // enabled ; 0 - GPIO_E 854 // Clocks/Resets are disabled 855 856 #define APPS_RCM_GPIO_E_SOFT_RESET_GPIO_E_SOFT_RESET \ 857 0x00000001 // 1 - Assert reset for GPIO_E ; 0 858 // - De-assert reset for GPIO_E 859 860 //****************************************************************************** 861 // 862 // The following are defines for the bit fields in the 863 // APPS_RCM_O_WDOG_A_CLK_GATING register. 864 // 865 //****************************************************************************** 866 #define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_BAUD_CLK_SEL_M \ 867 0x03000000 // "00" - Sysclk ; "01" - REF_CLK 868 // (38.4 MHz) ; "10/11" - Slow_clk 869 870 #define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_BAUD_CLK_SEL_S 24 871 #define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_DSLP_CLK_ENABLE \ 872 0x00010000 // 1 - Enable WDOG_A clk during 873 // deep-sleep mode 0 - Disable 874 // WDOG_A clk during deep-sleep mode 875 // ; 876 877 #define APPS_RCM_WDOG_A_CLK_GATING_NU1_M \ 878 0x0000FE00 879 880 #define APPS_RCM_WDOG_A_CLK_GATING_NU1_S 9 881 #define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_SLP_CLK_ENABLE \ 882 0x00000100 // 1 - Enable WDOG_A clk during 883 // sleep mode 0 - Disable WDOG_A clk 884 // during sleep mode ; 885 886 #define APPS_RCM_WDOG_A_CLK_GATING_NU2_M \ 887 0x000000FE 888 889 #define APPS_RCM_WDOG_A_CLK_GATING_NU2_S 1 890 #define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_RUN_CLK_ENABLE \ 891 0x00000001 // 1 - Enable WDOG_A clk during run 892 // mode 0 - Disable WDOG_A clk 893 // during run mode ; 894 895 //****************************************************************************** 896 // 897 // The following are defines for the bit fields in the 898 // APPS_RCM_O_WDOG_A_SOFT_RESET register. 899 // 900 //****************************************************************************** 901 #define APPS_RCM_WDOG_A_SOFT_RESET_WDOG_A_ENABLED_STATUS \ 902 0x00000002 // 1 - WDOG_A Clocks/Resets are 903 // enabled ; 0 - WDOG_A 904 // Clocks/Resets are disabled 905 906 #define APPS_RCM_WDOG_A_SOFT_RESET_WDOG_A_SOFT_RESET \ 907 0x00000001 // 1 - Assert reset for WDOG_A ; 0 908 // - De-assert reset for WDOG_A 909 910 //****************************************************************************** 911 // 912 // The following are defines for the bit fields in the 913 // APPS_RCM_O_UART_A0_CLK_GATING register. 914 // 915 //****************************************************************************** 916 #define APPS_RCM_UART_A0_CLK_GATING_UART_A0_DSLP_CLK_ENABLE \ 917 0x00010000 // 1 - Enable UART_A0 clk during 918 // deep-sleep mode 0 - Disable 919 // UART_A0 clk during deep-sleep 920 // mode ; 921 922 #define APPS_RCM_UART_A0_CLK_GATING_NU1_M \ 923 0x0000FE00 924 925 #define APPS_RCM_UART_A0_CLK_GATING_NU1_S 9 926 #define APPS_RCM_UART_A0_CLK_GATING_UART_A0_SLP_CLK_ENABLE \ 927 0x00000100 // 1 - Enable UART_A0 clk during 928 // sleep mode 0 - Disable UART_A0 929 // clk during sleep mode ; 930 931 #define APPS_RCM_UART_A0_CLK_GATING_NU2_M \ 932 0x000000FE 933 934 #define APPS_RCM_UART_A0_CLK_GATING_NU2_S 1 935 #define APPS_RCM_UART_A0_CLK_GATING_UART_A0_RUN_CLK_ENABLE \ 936 0x00000001 // 1 - Enable UART_A0 clk during 937 // run mode 0 - Disable UART_A0 clk 938 // during run mode ; 939 940 //****************************************************************************** 941 // 942 // The following are defines for the bit fields in the 943 // APPS_RCM_O_UART_A0_SOFT_RESET register. 944 // 945 //****************************************************************************** 946 #define APPS_RCM_UART_A0_SOFT_RESET_UART_A0_ENABLED_STATUS \ 947 0x00000002 // 1 - UART_A0 Clocks/Resets are 948 // enabled ; 0 - UART_A0 949 // Clocks/Resets are disabled 950 951 #define APPS_RCM_UART_A0_SOFT_RESET_UART_A0_SOFT_RESET \ 952 0x00000001 // 1 - Assert reset for UART_A0 ; 0 953 // - De-assert reset for UART_A0 954 955 //****************************************************************************** 956 // 957 // The following are defines for the bit fields in the 958 // APPS_RCM_O_UART_A1_CLK_GATING register. 959 // 960 //****************************************************************************** 961 #define APPS_RCM_UART_A1_CLK_GATING_UART_A1_DSLP_CLK_ENABLE \ 962 0x00010000 // 1 - Enable UART_A1 clk during 963 // deep-sleep mode 0 - Disable 964 // UART_A1 clk during deep-sleep 965 // mode ; 966 967 #define APPS_RCM_UART_A1_CLK_GATING_NU1_M \ 968 0x0000FE00 969 970 #define APPS_RCM_UART_A1_CLK_GATING_NU1_S 9 971 #define APPS_RCM_UART_A1_CLK_GATING_UART_A1_SLP_CLK_ENABLE \ 972 0x00000100 // 1 - Enable UART_A1 clk during 973 // sleep mode 0 - Disable UART_A1 974 // clk during sleep mode ; 975 976 #define APPS_RCM_UART_A1_CLK_GATING_NU2_M \ 977 0x000000FE 978 979 #define APPS_RCM_UART_A1_CLK_GATING_NU2_S 1 980 #define APPS_RCM_UART_A1_CLK_GATING_UART_A1_RUN_CLK_ENABLE \ 981 0x00000001 // 1 - Enable UART_A1 clk during 982 // run mode 0 - Disable UART_A1 clk 983 // during run mode ; 984 985 //****************************************************************************** 986 // 987 // The following are defines for the bit fields in the 988 // APPS_RCM_O_UART_A1_SOFT_RESET register. 989 // 990 //****************************************************************************** 991 #define APPS_RCM_UART_A1_SOFT_RESET_UART_A1_ENABLED_STATUS \ 992 0x00000002 // 1 - UART_A1 Clocks/Resets are 993 // enabled ; 0 - UART_A1 994 // Clocks/Resets are disabled 995 996 #define APPS_RCM_UART_A1_SOFT_RESET_UART_A1_SOFT_RESET \ 997 0x00000001 // 1 - Assert the soft reset for 998 // UART_A1 ; 0 - De-assert the soft 999 // reset for UART_A1 1000 1001 //****************************************************************************** 1002 // 1003 // The following are defines for the bit fields in the 1004 // APPS_RCM_O_GPT_A0_CLK_GATING register. 1005 // 1006 //****************************************************************************** 1007 #define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_DSLP_CLK_ENABLE \ 1008 0x00010000 // 1 - Enable the GPT_A0 clock 1009 // during deep-sleep ; 0 - Disable 1010 // the GPT_A0 clock during 1011 // deep-sleep 1012 1013 #define APPS_RCM_GPT_A0_CLK_GATING_NU1_M \ 1014 0x0000FE00 1015 1016 #define APPS_RCM_GPT_A0_CLK_GATING_NU1_S 9 1017 #define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_SLP_CLK_ENABLE \ 1018 0x00000100 // 1 - Enable the GPT_A0 clock 1019 // during sleep ; 0 - Disable the 1020 // GPT_A0 clock during sleep 1021 1022 #define APPS_RCM_GPT_A0_CLK_GATING_NU2_M \ 1023 0x000000FE 1024 1025 #define APPS_RCM_GPT_A0_CLK_GATING_NU2_S 1 1026 #define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_RUN_CLK_ENABLE \ 1027 0x00000001 // 1 - Enable the GPT_A0 clock 1028 // during run ; 0 - Disable the 1029 // GPT_A0 clock during run 1030 1031 //****************************************************************************** 1032 // 1033 // The following are defines for the bit fields in the 1034 // APPS_RCM_O_GPT_A0_SOFT_RESET register. 1035 // 1036 //****************************************************************************** 1037 #define APPS_RCM_GPT_A0_SOFT_RESET_GPT_A0_ENABLED_STATUS \ 1038 0x00000002 // 1 - GPT_A0 clocks/resets are 1039 // enabled ; 0 - GPT_A0 1040 // clocks/resets are disabled 1041 1042 #define APPS_RCM_GPT_A0_SOFT_RESET_GPT_A0_SOFT_RESET \ 1043 0x00000001 // 1 - Assert the soft reset for 1044 // GPT_A0 ; 0 - De-assert the soft 1045 // reset for GPT_A0 1046 1047 //****************************************************************************** 1048 // 1049 // The following are defines for the bit fields in the 1050 // APPS_RCM_O_GPT_A1_CLK_GATING register. 1051 // 1052 //****************************************************************************** 1053 #define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_DSLP_CLK_ENABLE \ 1054 0x00010000 // 1 - Enable the GPT_A1 clock 1055 // during deep-sleep ; 0 - Disable 1056 // the GPT_A1 clock during 1057 // deep-sleep 1058 1059 #define APPS_RCM_GPT_A1_CLK_GATING_NU1_M \ 1060 0x0000FE00 1061 1062 #define APPS_RCM_GPT_A1_CLK_GATING_NU1_S 9 1063 #define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_SLP_CLK_ENABLE \ 1064 0x00000100 // 1 - Enable the GPT_A1 clock 1065 // during sleep ; 0 - Disable the 1066 // GPT_A1 clock during sleep 1067 1068 #define APPS_RCM_GPT_A1_CLK_GATING_NU2_M \ 1069 0x000000FE 1070 1071 #define APPS_RCM_GPT_A1_CLK_GATING_NU2_S 1 1072 #define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_RUN_CLK_ENABLE \ 1073 0x00000001 // 1 - Enable the GPT_A1 clock 1074 // during run ; 0 - Disable the 1075 // GPT_A1 clock during run 1076 1077 //****************************************************************************** 1078 // 1079 // The following are defines for the bit fields in the 1080 // APPS_RCM_O_GPT_A1_SOFT_RESET register. 1081 // 1082 //****************************************************************************** 1083 #define APPS_RCM_GPT_A1_SOFT_RESET_GPT_A1_ENABLED_STATUS \ 1084 0x00000002 // 1 - GPT_A1 clocks/resets are 1085 // enabled ; 0 - GPT_A1 1086 // clocks/resets are disabled 1087 1088 #define APPS_RCM_GPT_A1_SOFT_RESET_GPT_A1_SOFT_RESET \ 1089 0x00000001 // 1 - Assert the soft reset for 1090 // GPT_A1 ; 0 - De-assert the soft 1091 // reset for GPT_A1 1092 1093 //****************************************************************************** 1094 // 1095 // The following are defines for the bit fields in the 1096 // APPS_RCM_O_GPT_A2_CLK_GATING register. 1097 // 1098 //****************************************************************************** 1099 #define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_DSLP_CLK_ENABLE \ 1100 0x00010000 // 1 - Enable the GPT_A2 clock 1101 // during deep-sleep ; 0 - Disable 1102 // the GPT_A2 clock during 1103 // deep-sleep 1104 1105 #define APPS_RCM_GPT_A2_CLK_GATING_NU1_M \ 1106 0x0000FE00 1107 1108 #define APPS_RCM_GPT_A2_CLK_GATING_NU1_S 9 1109 #define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_SLP_CLK_ENABLE \ 1110 0x00000100 // 1 - Enable the GPT_A2 clock 1111 // during sleep ; 0 - Disable the 1112 // GPT_A2 clock during sleep 1113 1114 #define APPS_RCM_GPT_A2_CLK_GATING_NU2_M \ 1115 0x000000FE 1116 1117 #define APPS_RCM_GPT_A2_CLK_GATING_NU2_S 1 1118 #define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_RUN_CLK_ENABLE \ 1119 0x00000001 // 1 - Enable the GPT_A2 clock 1120 // during run ; 0 - Disable the 1121 // GPT_A2 clock during run 1122 1123 //****************************************************************************** 1124 // 1125 // The following are defines for the bit fields in the 1126 // APPS_RCM_O_GPT_A2_SOFT_RESET register. 1127 // 1128 //****************************************************************************** 1129 #define APPS_RCM_GPT_A2_SOFT_RESET_GPT_A2_ENABLED_STATUS \ 1130 0x00000002 // 1 - GPT_A2 clocks/resets are 1131 // enabled ; 0 - GPT_A2 1132 // clocks/resets are disabled 1133 1134 #define APPS_RCM_GPT_A2_SOFT_RESET_GPT_A2_SOFT_RESET \ 1135 0x00000001 // 1 - Assert the soft reset for 1136 // GPT_A2 ; 0 - De-assert the soft 1137 // reset for GPT_A2 1138 1139 //****************************************************************************** 1140 // 1141 // The following are defines for the bit fields in the 1142 // APPS_RCM_O_GPT_A3_CLK_GATING register. 1143 // 1144 //****************************************************************************** 1145 #define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_DSLP_CLK_ENABLE \ 1146 0x00010000 // 1 - Enable the GPT_A3 clock 1147 // during deep-sleep ; 0 - Disable 1148 // the GPT_A3 clock during 1149 // deep-sleep 1150 1151 #define APPS_RCM_GPT_A3_CLK_GATING_NU1_M \ 1152 0x0000FE00 1153 1154 #define APPS_RCM_GPT_A3_CLK_GATING_NU1_S 9 1155 #define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_SLP_CLK_ENABLE \ 1156 0x00000100 // 1 - Enable the GPT_A3 clock 1157 // during sleep ; 0 - Disable the 1158 // GPT_A3 clock during sleep 1159 1160 #define APPS_RCM_GPT_A3_CLK_GATING_NU2_M \ 1161 0x000000FE 1162 1163 #define APPS_RCM_GPT_A3_CLK_GATING_NU2_S 1 1164 #define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_RUN_CLK_ENABLE \ 1165 0x00000001 // 1 - Enable the GPT_A3 clock 1166 // during run ; 0 - Disable the 1167 // GPT_A3 clock during run 1168 1169 //****************************************************************************** 1170 // 1171 // The following are defines for the bit fields in the 1172 // APPS_RCM_O_GPT_A3_SOFT_RESET register. 1173 // 1174 //****************************************************************************** 1175 #define APPS_RCM_GPT_A3_SOFT_RESET_GPT_A3_ENABLED_STATUS \ 1176 0x00000002 // 1 - GPT_A3 Clocks/resets are 1177 // enabled ; 0 - GPT_A3 1178 // Clocks/resets are disabled 1179 1180 #define APPS_RCM_GPT_A3_SOFT_RESET_GPT_A3_SOFT_RESET \ 1181 0x00000001 // 1 - Assert the soft reset for 1182 // GPT_A3 ; 0 - De-assert the soft 1183 // reset for GPT_A3 1184 1185 //****************************************************************************** 1186 // 1187 // The following are defines for the bit fields in the 1188 // APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0 register. 1189 // 1190 //****************************************************************************** 1191 #define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_DIVISOR_M \ 1192 0x03FF0000 1193 1194 #define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_DIVISOR_S 16 1195 #define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_FRACTION_M \ 1196 0x0000FFFF 1197 1198 #define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_FRACTION_S 0 1199 //****************************************************************************** 1200 // 1201 // The following are defines for the bit fields in the 1202 // APPS_RCM_O_MCASP_FRAC_CLK_CONFIG1 register. 1203 // 1204 //****************************************************************************** 1205 #define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_SOFT_RESET \ 1206 0x00010000 // 1 - Assert the reset for MCASP 1207 // Frac-clk div; 0 - Donot assert 1208 // the reset for MCASP frac clk-div 1209 1210 #define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_PERIOD_M \ 1211 0x000003FF 1212 1213 #define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_PERIOD_S 0 1214 //****************************************************************************** 1215 // 1216 // The following are defines for the bit fields in the 1217 // APPS_RCM_O_CRYPTO_CLK_GATING register. 1218 // 1219 //****************************************************************************** 1220 #define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_DSLP_CLK_ENABLE \ 1221 0x00010000 // 0 - Disable the Crypto clock 1222 // during deep-sleep 1223 1224 #define APPS_RCM_CRYPTO_CLK_GATING_NU1_M \ 1225 0x0000FE00 1226 1227 #define APPS_RCM_CRYPTO_CLK_GATING_NU1_S 9 1228 #define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_SLP_CLK_ENABLE \ 1229 0x00000100 // 1 - Enable the Crypto clock 1230 // during sleep ; 0 - Disable the 1231 // Crypto clock during sleep 1232 1233 #define APPS_RCM_CRYPTO_CLK_GATING_NU2_M \ 1234 0x000000FE 1235 1236 #define APPS_RCM_CRYPTO_CLK_GATING_NU2_S 1 1237 #define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_RUN_CLK_ENABLE \ 1238 0x00000001 // 1 - Enable the Crypto clock 1239 // during run ; 0 - Disable the 1240 // Crypto clock during run 1241 1242 //****************************************************************************** 1243 // 1244 // The following are defines for the bit fields in the 1245 // APPS_RCM_O_CRYPTO_SOFT_RESET register. 1246 // 1247 //****************************************************************************** 1248 #define APPS_RCM_CRYPTO_SOFT_RESET_CRYPTO_ENABLED_STATUS \ 1249 0x00000002 // 1 - Crypto clocks/resets are 1250 // enabled ; 0 - Crypto 1251 // clocks/resets are disabled 1252 1253 #define APPS_RCM_CRYPTO_SOFT_RESET_CRYPTO_SOFT_RESET \ 1254 0x00000001 // 1 - Assert the soft reset for 1255 // Crypto ; 0 - De-assert the soft 1256 // reset for Crypto 1257 1258 //****************************************************************************** 1259 // 1260 // The following are defines for the bit fields in the 1261 // APPS_RCM_O_MCSPI_S0_CLK_GATING register. 1262 // 1263 //****************************************************************************** 1264 #define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_DSLP_CLK_ENABLE \ 1265 0x00010000 // 0 - Disable the MCSPI_S0 clock 1266 // during deep-sleep 1267 1268 #define APPS_RCM_MCSPI_S0_CLK_GATING_NU1_M \ 1269 0x0000FE00 1270 1271 #define APPS_RCM_MCSPI_S0_CLK_GATING_NU1_S 9 1272 #define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_SLP_CLK_ENABLE \ 1273 0x00000100 // 1 - Enable the MCSPI_S0 clock 1274 // during sleep ; 0 - Disable the 1275 // MCSPI_S0 clock during sleep 1276 1277 #define APPS_RCM_MCSPI_S0_CLK_GATING_NU2_M \ 1278 0x000000FE 1279 1280 #define APPS_RCM_MCSPI_S0_CLK_GATING_NU2_S 1 1281 #define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_RUN_CLK_ENABLE \ 1282 0x00000001 // 1 - Enable the MCSPI_S0 clock 1283 // during run ; 0 - Disable the 1284 // MCSPI_S0 clock during run 1285 1286 //****************************************************************************** 1287 // 1288 // The following are defines for the bit fields in the 1289 // APPS_RCM_O_MCSPI_S0_SOFT_RESET register. 1290 // 1291 //****************************************************************************** 1292 #define APPS_RCM_MCSPI_S0_SOFT_RESET_MCSPI_S0_ENABLED_STATUS \ 1293 0x00000002 // 1 - MCSPI_S0 Clocks/Resets are 1294 // enabled ; 0 - MCSPI_S0 1295 // Clocks/resets are disabled 1296 1297 #define APPS_RCM_MCSPI_S0_SOFT_RESET_MCSPI_S0_SOFT_RESET \ 1298 0x00000001 // 1 - Assert the soft reset for 1299 // MCSPI_S0 ; 0 - De-assert the soft 1300 // reset for MCSPI_S0 1301 1302 //****************************************************************************** 1303 // 1304 // The following are defines for the bit fields in the 1305 // APPS_RCM_O_MCSPI_S0_CLKDIV_CFG register. 1306 // 1307 //****************************************************************************** 1308 #define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_BAUD_CLK_SEL \ 1309 0x00010000 // 0 - XTAL clk is used as baud-clk 1310 // for MCSPI_S0 ; 1 - PLL divclk is 1311 // used as buad-clk for MCSPI_S0 1312 1313 #define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU1_M \ 1314 0x0000F800 1315 1316 #define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU1_S 11 1317 #define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_OFF_TIME_M \ 1318 0x00000700 // Configuration of OFF-TIME for 1319 // dividing PLL clk (240 MHz) in 1320 // generation of MCSPI_S0 func-clk : 1321 // "000" - 1 "001" - 2 "010" - 3 1322 // "011" - 4 "100" - 5 "101" - 6 1323 // "110" - 7 "111" - 8 1324 1325 #define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_OFF_TIME_S 8 1326 #define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU2_M \ 1327 0x000000F8 1328 1329 #define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU2_S 3 1330 #define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_ON_TIME_M \ 1331 0x00000007 // Configuration of ON-TIME for 1332 // dividing PLL clk (240 MHz) in 1333 // generation of MCSPI_S0 func-clk : 1334 // "000" - 1 "001" - 2 "010" - 3 1335 // "011" - 4 "100" - 5 "101" - 6 1336 // "110" - 7 "111" - 8 1337 1338 #define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_ON_TIME_S 0 1339 //****************************************************************************** 1340 // 1341 // The following are defines for the bit fields in the 1342 // APPS_RCM_O_I2C_CLK_GATING register. 1343 // 1344 //****************************************************************************** 1345 #define APPS_RCM_I2C_CLK_GATING_I2C_DSLP_CLK_ENABLE \ 1346 0x00010000 // 1 - Enable the I2C Clock during 1347 // deep-sleep 0 - Disable the I2C 1348 // clock during deep-sleep 1349 1350 #define APPS_RCM_I2C_CLK_GATING_NU1_M \ 1351 0x0000FE00 1352 1353 #define APPS_RCM_I2C_CLK_GATING_NU1_S 9 1354 #define APPS_RCM_I2C_CLK_GATING_I2C_SLP_CLK_ENABLE \ 1355 0x00000100 // 1 - Enable the I2C clock during 1356 // sleep ; 0 - Disable the I2C clock 1357 // during sleep 1358 1359 #define APPS_RCM_I2C_CLK_GATING_NU2_M \ 1360 0x000000FE 1361 1362 #define APPS_RCM_I2C_CLK_GATING_NU2_S 1 1363 #define APPS_RCM_I2C_CLK_GATING_I2C_RUN_CLK_ENABLE \ 1364 0x00000001 // 1 - Enable the I2C clock during 1365 // run ; 0 - Disable the I2C clock 1366 // during run 1367 1368 //****************************************************************************** 1369 // 1370 // The following are defines for the bit fields in the 1371 // APPS_RCM_O_I2C_SOFT_RESET register. 1372 // 1373 //****************************************************************************** 1374 #define APPS_RCM_I2C_SOFT_RESET_I2C_ENABLED_STATUS \ 1375 0x00000002 // 1 - I2C Clocks/Resets are 1376 // enabled ; 0 - I2C clocks/resets 1377 // are disabled 1378 1379 #define APPS_RCM_I2C_SOFT_RESET_I2C_SOFT_RESET \ 1380 0x00000001 // 1 - Assert the soft reset for 1381 // Shared-I2C ; 0 - De-assert the 1382 // soft reset for Shared-I2C 1383 1384 //****************************************************************************** 1385 // 1386 // The following are defines for the bit fields in the 1387 // APPS_RCM_O_APPS_LPDS_REQ register. 1388 // 1389 //****************************************************************************** 1390 #define APPS_RCM_APPS_LPDS_REQ_APPS_LPDS_REQ \ 1391 0x00000001 // 1 - Request for LPDS 1392 1393 //****************************************************************************** 1394 // 1395 // The following are defines for the bit fields in the 1396 // APPS_RCM_O_APPS_TURBO_REQ register. 1397 // 1398 //****************************************************************************** 1399 #define APPS_RCM_APPS_TURBO_REQ_APPS_TURBO_REQ \ 1400 0x00000001 // 1 - Request for TURBO 1401 1402 //****************************************************************************** 1403 // 1404 // The following are defines for the bit fields in the 1405 // APPS_RCM_O_APPS_DSLP_WAKE_CONFIG register. 1406 // 1407 //****************************************************************************** 1408 #define APPS_RCM_APPS_DSLP_WAKE_CONFIG_DSLP_WAKE_FROM_NWP_ENABLE \ 1409 0x00000002 // 1 - Enable the NWP to wake APPS 1410 // from deep-sleep ; 0 - Disable NWP 1411 // to wake APPS from deep-sleep 1412 1413 #define APPS_RCM_APPS_DSLP_WAKE_CONFIG_DSLP_WAKE_TIMER_ENABLE \ 1414 0x00000001 // 1 - Enable deep-sleep wake timer 1415 // in APPS RCM for deep-sleep; 0 - 1416 // Disable deep-sleep wake timer in 1417 // APPS RCM 1418 1419 //****************************************************************************** 1420 // 1421 // The following are defines for the bit fields in the 1422 // APPS_RCM_O_APPS_DSLP_WAKE_TIMER_CFG register. 1423 // 1424 //****************************************************************************** 1425 #define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_OPP_CFG_M \ 1426 0xFFFF0000 // Configuration (in slow_clks) 1427 // which says when to request for 1428 // OPP during deep-sleep exit 1429 1430 #define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_OPP_CFG_S 16 1431 #define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_WAKE_CFG_M \ 1432 0x0000FFFF // Configuration (in slow_clks) 1433 // which says when to request for 1434 // WAKE during deep-sleep exit 1435 1436 #define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_WAKE_CFG_S 0 1437 //****************************************************************************** 1438 // 1439 // The following are defines for the bit fields in the 1440 // APPS_RCM_O_APPS_RCM_SLP_WAKE_ENABLE register. 1441 // 1442 //****************************************************************************** 1443 #define APPS_RCM_APPS_RCM_SLP_WAKE_ENABLE_SLP_WAKE_FROM_NWP_ENABLE \ 1444 0x00000002 // 1- Enable the sleep wakeup due 1445 // to NWP request. 0- Disable the 1446 // sleep wakeup due to NWP request 1447 1448 #define APPS_RCM_APPS_RCM_SLP_WAKE_ENABLE_SLP_WAKE_TIMER_ENABLE \ 1449 0x00000001 // 1- Enable the sleep wakeup due 1450 // to sleep-timer; 0-Disable the 1451 // sleep wakeup due to sleep-timer 1452 1453 //****************************************************************************** 1454 // 1455 // The following are defines for the bit fields in the 1456 // APPS_RCM_O_APPS_SLP_WAKETIMER_CFG register. 1457 // 1458 //****************************************************************************** 1459 #define APPS_RCM_APPS_SLP_WAKETIMER_CFG_SLP_WAKE_TIMER_CFG_M \ 1460 0xFFFFFFFF // Configuration (number of 1461 // sysclks-80MHz) for the Sleep 1462 // wakeup timer 1463 1464 #define APPS_RCM_APPS_SLP_WAKETIMER_CFG_SLP_WAKE_TIMER_CFG_S 0 1465 //****************************************************************************** 1466 // 1467 // The following are defines for the bit fields in the 1468 // APPS_RCM_O_APPS_TO_NWP_WAKE_REQUEST register. 1469 // 1470 //****************************************************************************** 1471 #define APPS_RCM_APPS_TO_NWP_WAKE_REQUEST_APPS_TO_NWP_WAKEUP_REQUEST \ 1472 0x00000001 // When 1 => APPS generated a wake 1473 // request to NWP (When NWP is in 1474 // any of its low-power modes : 1475 // SLP/DSLP/LPDS) 1476 1477 //****************************************************************************** 1478 // 1479 // The following are defines for the bit fields in the 1480 // APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS register. 1481 // 1482 //****************************************************************************** 1483 #define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_deep_sleep_timer_wake \ 1484 0x00000008 // 1 - Indicates that deep-sleep 1485 // timer expiry had caused the 1486 // wakeup from deep-sleep 1487 1488 #define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_sleep_timer_wake \ 1489 0x00000004 // 1 - Indicates that sleep timer 1490 // expiry had caused the wakeup from 1491 // sleep 1492 1493 #define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_deep_sleep_wake_from_nwp \ 1494 0x00000002 // 1 - Indicates that NWP had 1495 // caused the wakeup from deep-sleep 1496 1497 #define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_sleep_wake_from_nwp \ 1498 0x00000001 // 1 - Indicates that NWP had 1499 // caused the wakeup from Sleep 1500 1501 1502 1503 1504 #endif // __HW_APPS_RCM_H__ 1505
