1 /* 2 3 Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. 4 5 SPDX-License-Identifier: BSD-3-Clause 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, this 11 list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of Nordic Semiconductor ASA nor the names of its 18 contributors may be used to endorse or promote products derived from this 19 software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 */ 34 35 #ifndef __NRF9120_BITS_H 36 #define __NRF9120_BITS_H 37 38 /*lint ++flb "Enter library region" */ 39 40 /* Peripheral: APPROTECT */ 41 /* Description: Access Port Protection 0 */ 42 43 /* Register: APPROTECT_SECUREAPPROTECT_DISABLE */ 44 /* Description: Software disable SECUREAPPROTECT mechanism */ 45 46 /* Bits 7..0 : Software disable SECUREAPPROTECT mechanism */ 47 #define APPROTECT_SECUREAPPROTECT_DISABLE_DISABLE_Pos (0UL) /*!< Position of DISABLE field. */ 48 #define APPROTECT_SECUREAPPROTECT_DISABLE_DISABLE_Msk (0xFFUL << APPROTECT_SECUREAPPROTECT_DISABLE_DISABLE_Pos) /*!< Bit mask of DISABLE field. */ 49 #define APPROTECT_SECUREAPPROTECT_DISABLE_DISABLE_SwUnprotected (0x5AUL) /*!< Software disable SECUREAPPROTECT mechanism */ 50 51 /* Register: APPROTECT_SECUREAPPROTECT_FORCEPROTECT */ 52 /* Description: Software force SECUREAPPROTECT mechanism */ 53 54 /* Bit 9 : Write 0x1 to force enable SECUREAPPROTECT mechanism, which will remain set until the next reset */ 55 #define APPROTECT_SECUREAPPROTECT_FORCEPROTECT_FORCEPROTECT_Pos (9UL) /*!< Position of FORCEPROTECT field. */ 56 #define APPROTECT_SECUREAPPROTECT_FORCEPROTECT_FORCEPROTECT_Msk (0x1UL << APPROTECT_SECUREAPPROTECT_FORCEPROTECT_FORCEPROTECT_Pos) /*!< Bit mask of FORCEPROTECT field. */ 57 #define APPROTECT_SECUREAPPROTECT_FORCEPROTECT_FORCEPROTECT_Force (0x1UL) /*!< Software force enable SECUREAPPROTECT mechanism */ 58 59 /* Register: APPROTECT_APPROTECT_DISABLE */ 60 /* Description: Software disable APPROTECT mechanism */ 61 62 /* Bits 7..0 : Software disable APPROTECT mechanism */ 63 #define APPROTECT_APPROTECT_DISABLE_DISABLE_Pos (0UL) /*!< Position of DISABLE field. */ 64 #define APPROTECT_APPROTECT_DISABLE_DISABLE_Msk (0xFFUL << APPROTECT_APPROTECT_DISABLE_DISABLE_Pos) /*!< Bit mask of DISABLE field. */ 65 #define APPROTECT_APPROTECT_DISABLE_DISABLE_SwUnprotected (0x5AUL) /*!< Software disable APPROTECT mechanism */ 66 67 /* Register: APPROTECT_APPROTECT_FORCEPROTECT */ 68 /* Description: Software force APPROTECT mechanism */ 69 70 /* Bit 9 : Write 0x1 to force enable APPROTECT mechanism, which will remain set until the next reset */ 71 #define APPROTECT_APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos (9UL) /*!< Position of FORCEPROTECT field. */ 72 #define APPROTECT_APPROTECT_FORCEPROTECT_FORCEPROTECT_Msk (0x1UL << APPROTECT_APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos) /*!< Bit mask of FORCEPROTECT field. */ 73 #define APPROTECT_APPROTECT_FORCEPROTECT_FORCEPROTECT_Force (0x1UL) /*!< Software force enable APPROTECT mechanism */ 74 75 76 /* Peripheral: CC_HOST_RGF */ 77 /* Description: CRYPTOCELL HOST_RGF interface */ 78 79 /* Register: CC_HOST_RGF_HOST_CRYPTOKEY_SEL */ 80 /* Description: AES hardware key select */ 81 82 /* Bits 1..0 : Select the source of the HW key that is used by the AES engine */ 83 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Pos (0UL) /*!< Position of HOST_CRYPTOKEY_SEL field. */ 84 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Msk (0x3UL << CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Pos) /*!< Bit mask of HOST_CRYPTOKEY_SEL field. */ 85 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_DR (0UL) /*!< Use device root key K_DR from CRYPTOCELL AO power domain */ 86 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_PRTL (1UL) /*!< Use hard-coded RTL key K_PRTL */ 87 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Session (2UL) /*!< Use provided session key */ 88 89 /* Register: CC_HOST_RGF_HOST_IOT_KPRTL_LOCK */ 90 /* Description: This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */ 91 92 /* Bit 0 : This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */ 93 #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos (0UL) /*!< Position of HOST_IOT_KPRTL_LOCK field. */ 94 #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos) /*!< Bit mask of HOST_IOT_KPRTL_LOCK field. */ 95 #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Disabled (0UL) /*!< K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL */ 96 #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Enabled (1UL) /*!< K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead. */ 97 98 /* Register: CC_HOST_RGF_HOST_IOT_KDR0 */ 99 /* Description: This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. */ 100 101 /* Bits 31..0 : Write: K_DR bits 31:0. Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain. Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain. */ 102 #define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos (0UL) /*!< Position of HOST_IOT_KDR0 field. */ 103 #define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos) /*!< Bit mask of HOST_IOT_KDR0 field. */ 104 105 /* Register: CC_HOST_RGF_HOST_IOT_KDR1 */ 106 /* Description: This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */ 107 108 /* Bits 31..0 : K_DR bits 63:32 */ 109 #define CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Pos (0UL) /*!< Position of HOST_IOT_KDR1 field. */ 110 #define CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Pos) /*!< Bit mask of HOST_IOT_KDR1 field. */ 111 112 /* Register: CC_HOST_RGF_HOST_IOT_KDR2 */ 113 /* Description: This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */ 114 115 /* Bits 31..0 : K_DR bits 95:64 */ 116 #define CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Pos (0UL) /*!< Position of HOST_IOT_KDR2 field. */ 117 #define CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Pos) /*!< Bit mask of HOST_IOT_KDR2 field. */ 118 119 /* Register: CC_HOST_RGF_HOST_IOT_KDR3 */ 120 /* Description: This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */ 121 122 /* Bits 31..0 : K_DR bits 127:96 */ 123 #define CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Pos (0UL) /*!< Position of HOST_IOT_KDR3 field. */ 124 #define CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Pos) /*!< Bit mask of HOST_IOT_KDR3 field. */ 125 126 /* Register: CC_HOST_RGF_HOST_IOT_LCS */ 127 /* Description: Controls lifecycle state (LCS) for CRYPTOCELL subsystem */ 128 129 /* Bit 8 : Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset. */ 130 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos (8UL) /*!< Position of LCS_IS_VALID field. */ 131 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos) /*!< Bit mask of LCS_IS_VALID field. */ 132 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Invalid (0UL) /*!< Valid LCS not yet retained in the CRYPTOCELL AO power domain */ 133 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Valid (1UL) /*!< Valid LCS successfully retained in the CRYPTOCELL AO power domain */ 134 135 /* Bits 2..0 : Lifecycle state value. This field is write-once per reset. */ 136 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos (0UL) /*!< Position of LCS field. */ 137 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_Msk (0x7UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos) /*!< Bit mask of LCS field. */ 138 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_Debug (0UL) /*!< CC310 operates in debug mode */ 139 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_Secure (2UL) /*!< CC310 operates in secure mode */ 140 141 142 /* Peripheral: CLOCK */ 143 /* Description: Clock management 0 */ 144 145 /* Register: CLOCK_TASKS_HFCLKSTART */ 146 /* Description: Start HFCLK source */ 147 148 /* Bit 0 : Start HFCLK source */ 149 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */ 150 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */ 151 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL) /*!< Trigger task */ 152 153 /* Register: CLOCK_TASKS_HFCLKSTOP */ 154 /* Description: Stop HFCLK source */ 155 156 /* Bit 0 : Stop HFCLK source */ 157 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */ 158 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */ 159 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL) /*!< Trigger task */ 160 161 /* Register: CLOCK_TASKS_LFCLKSTART */ 162 /* Description: Start LFCLK source */ 163 164 /* Bit 0 : Start LFCLK source */ 165 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */ 166 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */ 167 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL) /*!< Trigger task */ 168 169 /* Register: CLOCK_TASKS_LFCLKSTOP */ 170 /* Description: Stop LFCLK source */ 171 172 /* Bit 0 : Stop LFCLK source */ 173 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */ 174 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */ 175 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL) /*!< Trigger task */ 176 177 /* Register: CLOCK_SUBSCRIBE_HFCLKSTART */ 178 /* Description: Subscribe configuration for task HFCLKSTART */ 179 180 /* Bit 31 : */ 181 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos (31UL) /*!< Position of EN field. */ 182 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos) /*!< Bit mask of EN field. */ 183 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Disabled (0UL) /*!< Disable subscription */ 184 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */ 185 186 /* Bits 7..0 : DPPI channel that task HFCLKSTART will subscribe to */ 187 #define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 188 #define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 189 190 /* Register: CLOCK_SUBSCRIBE_HFCLKSTOP */ 191 /* Description: Subscribe configuration for task HFCLKSTOP */ 192 193 /* Bit 31 : */ 194 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos (31UL) /*!< Position of EN field. */ 195 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos) /*!< Bit mask of EN field. */ 196 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Disabled (0UL) /*!< Disable subscription */ 197 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */ 198 199 /* Bits 7..0 : DPPI channel that task HFCLKSTOP will subscribe to */ 200 #define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 201 #define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 202 203 /* Register: CLOCK_SUBSCRIBE_LFCLKSTART */ 204 /* Description: Subscribe configuration for task LFCLKSTART */ 205 206 /* Bit 31 : */ 207 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos (31UL) /*!< Position of EN field. */ 208 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos) /*!< Bit mask of EN field. */ 209 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Disabled (0UL) /*!< Disable subscription */ 210 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */ 211 212 /* Bits 7..0 : DPPI channel that task LFCLKSTART will subscribe to */ 213 #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 214 #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 215 216 /* Register: CLOCK_SUBSCRIBE_LFCLKSTOP */ 217 /* Description: Subscribe configuration for task LFCLKSTOP */ 218 219 /* Bit 31 : */ 220 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos (31UL) /*!< Position of EN field. */ 221 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos) /*!< Bit mask of EN field. */ 222 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Disabled (0UL) /*!< Disable subscription */ 223 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */ 224 225 /* Bits 7..0 : DPPI channel that task LFCLKSTOP will subscribe to */ 226 #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 227 #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 228 229 /* Register: CLOCK_EVENTS_HFCLKSTARTED */ 230 /* Description: HFCLK oscillator started */ 231 232 /* Bit 0 : HFCLK oscillator started */ 233 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */ 234 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */ 235 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */ 236 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL) /*!< Event generated */ 237 238 /* Register: CLOCK_EVENTS_LFCLKSTARTED */ 239 /* Description: LFCLK started */ 240 241 /* Bit 0 : LFCLK started */ 242 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */ 243 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */ 244 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */ 245 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL) /*!< Event generated */ 246 247 /* Register: CLOCK_PUBLISH_HFCLKSTARTED */ 248 /* Description: Publish configuration for event HFCLKSTARTED */ 249 250 /* Bit 31 : */ 251 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ 252 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos) /*!< Bit mask of EN field. */ 253 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ 254 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ 255 256 /* Bits 7..0 : DPPI channel that event HFCLKSTARTED will publish to */ 257 #define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 258 #define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 259 260 /* Register: CLOCK_PUBLISH_LFCLKSTARTED */ 261 /* Description: Publish configuration for event LFCLKSTARTED */ 262 263 /* Bit 31 : */ 264 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ 265 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos) /*!< Bit mask of EN field. */ 266 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ 267 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ 268 269 /* Bits 7..0 : DPPI channel that event LFCLKSTARTED will publish to */ 270 #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 271 #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 272 273 /* Register: CLOCK_INTEN */ 274 /* Description: Enable or disable interrupt */ 275 276 /* Bit 1 : Enable or disable interrupt for event LFCLKSTARTED */ 277 #define CLOCK_INTEN_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ 278 #define CLOCK_INTEN_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ 279 #define CLOCK_INTEN_LFCLKSTARTED_Disabled (0UL) /*!< Disable */ 280 #define CLOCK_INTEN_LFCLKSTARTED_Enabled (1UL) /*!< Enable */ 281 282 /* Bit 0 : Enable or disable interrupt for event HFCLKSTARTED */ 283 #define CLOCK_INTEN_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ 284 #define CLOCK_INTEN_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ 285 #define CLOCK_INTEN_HFCLKSTARTED_Disabled (0UL) /*!< Disable */ 286 #define CLOCK_INTEN_HFCLKSTARTED_Enabled (1UL) /*!< Enable */ 287 288 /* Register: CLOCK_INTENSET */ 289 /* Description: Enable interrupt */ 290 291 /* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */ 292 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ 293 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ 294 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ 295 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ 296 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */ 297 298 /* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */ 299 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ 300 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ 301 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ 302 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ 303 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */ 304 305 /* Register: CLOCK_INTENCLR */ 306 /* Description: Disable interrupt */ 307 308 /* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */ 309 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ 310 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ 311 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ 312 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ 313 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */ 314 315 /* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */ 316 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ 317 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ 318 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ 319 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ 320 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */ 321 322 /* Register: CLOCK_INTPEND */ 323 /* Description: Pending interrupts */ 324 325 /* Bit 1 : Read pending status of interrupt for event LFCLKSTARTED */ 326 #define CLOCK_INTPEND_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ 327 #define CLOCK_INTPEND_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ 328 #define CLOCK_INTPEND_LFCLKSTARTED_NotPending (0UL) /*!< Read: Not pending */ 329 #define CLOCK_INTPEND_LFCLKSTARTED_Pending (1UL) /*!< Read: Pending */ 330 331 /* Bit 0 : Read pending status of interrupt for event HFCLKSTARTED */ 332 #define CLOCK_INTPEND_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ 333 #define CLOCK_INTPEND_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ 334 #define CLOCK_INTPEND_HFCLKSTARTED_NotPending (0UL) /*!< Read: Not pending */ 335 #define CLOCK_INTPEND_HFCLKSTARTED_Pending (1UL) /*!< Read: Pending */ 336 337 /* Register: CLOCK_HFCLKRUN */ 338 /* Description: Status indicating that HFCLKSTART task has been triggered */ 339 340 /* Bit 0 : HFCLKSTART task triggered or not */ 341 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 342 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ 343 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ 344 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ 345 346 /* Register: CLOCK_HFCLKSTAT */ 347 /* Description: The register shows if HFXO has been requested by triggering HFCLKSTART task and if it has been started (STATE) */ 348 349 /* Bit 16 : HFCLK state */ 350 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ 351 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ 352 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFXO has not been started or HFCLKSTOP task has been triggered */ 353 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFXO has been started (HFCLKSTARTED event has been generated) */ 354 355 /* Bit 0 : Active clock source */ 356 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ 357 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ 358 #define CLOCK_HFCLKSTAT_SRC_HFINT (0UL) /*!< HFINT - 64 MHz on-chip oscillator */ 359 #define CLOCK_HFCLKSTAT_SRC_HFXO (1UL) /*!< HFXO - 64 MHz clock derived from external 32 MHz crystal oscillator */ 360 361 /* Register: CLOCK_LFCLKRUN */ 362 /* Description: Status indicating that LFCLKSTART task has been triggered */ 363 364 /* Bit 0 : LFCLKSTART task triggered or not */ 365 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 366 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ 367 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ 368 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ 369 370 /* Register: CLOCK_LFCLKSTAT */ 371 /* Description: The register shows which LFCLK source has been requested (SRC) when triggering LFCLKSTART task and if the source has been started (STATE) */ 372 373 /* Bit 16 : LFCLK state */ 374 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ 375 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ 376 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< Requested LFCLK source has not been started or LFCLKSTOP task has been triggered */ 377 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< Requested LFCLK source has been started (LFCLKSTARTED event has been generated) */ 378 379 /* Bits 1..0 : Active clock source */ 380 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ 381 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ 382 #define CLOCK_LFCLKSTAT_SRC_RFU (0UL) /*!< Reserved for future use */ 383 #define CLOCK_LFCLKSTAT_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */ 384 #define CLOCK_LFCLKSTAT_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */ 385 386 /* Register: CLOCK_LFCLKSRCCOPY */ 387 /* Description: Copy of LFCLKSRC register, set after LFCLKSTART task has been triggered */ 388 389 /* Bits 1..0 : Clock source */ 390 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ 391 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ 392 #define CLOCK_LFCLKSRCCOPY_SRC_RFU (0UL) /*!< Reserved for future use */ 393 #define CLOCK_LFCLKSRCCOPY_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */ 394 #define CLOCK_LFCLKSRCCOPY_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */ 395 396 /* Register: CLOCK_LFCLKSRC */ 397 /* Description: Clock source for the LFCLK. LFCLKSTART task starts starts a clock source selected with this register. */ 398 399 /* Bits 1..0 : Clock source */ 400 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ 401 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ 402 #define CLOCK_LFCLKSRC_SRC_RFU (0UL) /*!< Reserved for future use (equals selecting LFRC) */ 403 #define CLOCK_LFCLKSRC_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */ 404 #define CLOCK_LFCLKSRC_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */ 405 406 407 /* Peripheral: CRYPTOCELL */ 408 /* Description: ARM TrustZone CryptoCell register interface */ 409 410 /* Register: CRYPTOCELL_ENABLE */ 411 /* Description: Enable CRYPTOCELL subsystem */ 412 413 /* Bit 0 : Enable or disable the CRYPTOCELL subsystem */ 414 #define CRYPTOCELL_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 415 #define CRYPTOCELL_ENABLE_ENABLE_Msk (0x1UL << CRYPTOCELL_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 416 #define CRYPTOCELL_ENABLE_ENABLE_Disabled (0UL) /*!< CRYPTOCELL subsystem disabled */ 417 #define CRYPTOCELL_ENABLE_ENABLE_Enabled (1UL) /*!< CRYPTOCELL subsystem enabled. */ 418 419 420 /* Peripheral: CTRLAPPERI */ 421 /* Description: Control access port */ 422 423 /* Register: CTRLAPPERI_MAILBOX_RXDATA */ 424 /* Description: Data sent from the debugger to the CPU. */ 425 426 /* Bits 31..0 : Data received from debugger */ 427 #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos (0UL) /*!< Position of RXDATA field. */ 428 #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos) /*!< Bit mask of RXDATA field. */ 429 430 /* Register: CTRLAPPERI_MAILBOX_RXSTATUS */ 431 /* Description: This register shows a status that indicates if data sent from the debugger to the CPU has been read. */ 432 433 /* Bit 0 : Status of data in register RXDATA */ 434 #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos (0UL) /*!< Position of RXSTATUS field. */ 435 #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos) /*!< Bit mask of RXSTATUS field. */ 436 #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_NoDataPending (0UL) /*!< No data pending in register RXDATA */ 437 #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_DataPending (1UL) /*!< Data pending in register RXDATA */ 438 439 /* Register: CTRLAPPERI_MAILBOX_TXDATA */ 440 /* Description: Data sent from the CPU to the debugger. */ 441 442 /* Bits 31..0 : Data sent to debugger */ 443 #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos (0UL) /*!< Position of TXDATA field. */ 444 #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos) /*!< Bit mask of TXDATA field. */ 445 446 /* Register: CTRLAPPERI_MAILBOX_TXSTATUS */ 447 /* Description: This register shows a status that indicates if the data sent from the CPU to the debugger has been read. */ 448 449 /* Bit 0 : Status of data in register TXDATA */ 450 #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos (0UL) /*!< Position of TXSTATUS field. */ 451 #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos) /*!< Bit mask of TXSTATUS field. */ 452 #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_NoDataPending (0UL) /*!< No data pending in register TXDATA */ 453 #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_DataPending (1UL) /*!< Data pending in register TXDATA */ 454 455 /* Register: CTRLAPPERI_ERASEPROTECT_LOCK */ 456 /* Description: This register locks the ERASEPROTECT.DISABLE register from being written until next reset. */ 457 458 /* Bit 0 : Lock ERASEPROTECT.DISABLE register from being written until next reset */ 459 #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */ 460 #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Msk (0x1UL << CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */ 461 #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Unlocked (0UL) /*!< Register ERASEPROTECT.DISABLE is writeable */ 462 #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Locked (1UL) /*!< Register ERASEPROTECT.DISABLE is read-only */ 463 464 /* Register: CTRLAPPERI_ERASEPROTECT_DISABLE */ 465 /* Description: This register disables the ERASEPROTECT register and performs an ERASEALL operation. */ 466 467 /* Bits 31..0 : The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. */ 468 #define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos (0UL) /*!< Position of KEY field. */ 469 #define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos) /*!< Bit mask of KEY field. */ 470 471 472 /* Peripheral: DPPIC */ 473 /* Description: Distributed programmable peripheral interconnect controller 0 */ 474 475 /* Register: DPPIC_TASKS_CHG_EN */ 476 /* Description: Description cluster: Enable channel group n */ 477 478 /* Bit 0 : Enable channel group n */ 479 #define DPPIC_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */ 480 #define DPPIC_TASKS_CHG_EN_EN_Msk (0x1UL << DPPIC_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */ 481 #define DPPIC_TASKS_CHG_EN_EN_Trigger (1UL) /*!< Trigger task */ 482 483 /* Register: DPPIC_TASKS_CHG_DIS */ 484 /* Description: Description cluster: Disable channel group n */ 485 486 /* Bit 0 : Disable channel group n */ 487 #define DPPIC_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */ 488 #define DPPIC_TASKS_CHG_DIS_DIS_Msk (0x1UL << DPPIC_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */ 489 #define DPPIC_TASKS_CHG_DIS_DIS_Trigger (1UL) /*!< Trigger task */ 490 491 /* Register: DPPIC_SUBSCRIBE_CHG_EN */ 492 /* Description: Description cluster: Subscribe configuration for task CHG[n].EN */ 493 494 /* Bit 31 : */ 495 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Pos (31UL) /*!< Position of EN field. */ 496 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */ 497 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Disabled (0UL) /*!< Disable subscription */ 498 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Enabled (1UL) /*!< Enable subscription */ 499 500 /* Bits 7..0 : DPPI channel that task CHG[n].EN will subscribe to */ 501 #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 502 #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 503 504 /* Register: DPPIC_SUBSCRIBE_CHG_DIS */ 505 /* Description: Description cluster: Subscribe configuration for task CHG[n].DIS */ 506 507 /* Bit 31 : */ 508 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos (31UL) /*!< Position of EN field. */ 509 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos) /*!< Bit mask of EN field. */ 510 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Disabled (0UL) /*!< Disable subscription */ 511 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Enabled (1UL) /*!< Enable subscription */ 512 513 /* Bits 7..0 : DPPI channel that task CHG[n].DIS will subscribe to */ 514 #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 515 #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 516 517 /* Register: DPPIC_CHEN */ 518 /* Description: Channel enable register */ 519 520 /* Bit 15 : Enable or disable channel 15 */ 521 #define DPPIC_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */ 522 #define DPPIC_CHEN_CH15_Msk (0x1UL << DPPIC_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */ 523 #define DPPIC_CHEN_CH15_Disabled (0UL) /*!< Disable channel */ 524 #define DPPIC_CHEN_CH15_Enabled (1UL) /*!< Enable channel */ 525 526 /* Bit 14 : Enable or disable channel 14 */ 527 #define DPPIC_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */ 528 #define DPPIC_CHEN_CH14_Msk (0x1UL << DPPIC_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */ 529 #define DPPIC_CHEN_CH14_Disabled (0UL) /*!< Disable channel */ 530 #define DPPIC_CHEN_CH14_Enabled (1UL) /*!< Enable channel */ 531 532 /* Bit 13 : Enable or disable channel 13 */ 533 #define DPPIC_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */ 534 #define DPPIC_CHEN_CH13_Msk (0x1UL << DPPIC_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */ 535 #define DPPIC_CHEN_CH13_Disabled (0UL) /*!< Disable channel */ 536 #define DPPIC_CHEN_CH13_Enabled (1UL) /*!< Enable channel */ 537 538 /* Bit 12 : Enable or disable channel 12 */ 539 #define DPPIC_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */ 540 #define DPPIC_CHEN_CH12_Msk (0x1UL << DPPIC_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */ 541 #define DPPIC_CHEN_CH12_Disabled (0UL) /*!< Disable channel */ 542 #define DPPIC_CHEN_CH12_Enabled (1UL) /*!< Enable channel */ 543 544 /* Bit 11 : Enable or disable channel 11 */ 545 #define DPPIC_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */ 546 #define DPPIC_CHEN_CH11_Msk (0x1UL << DPPIC_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */ 547 #define DPPIC_CHEN_CH11_Disabled (0UL) /*!< Disable channel */ 548 #define DPPIC_CHEN_CH11_Enabled (1UL) /*!< Enable channel */ 549 550 /* Bit 10 : Enable or disable channel 10 */ 551 #define DPPIC_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */ 552 #define DPPIC_CHEN_CH10_Msk (0x1UL << DPPIC_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */ 553 #define DPPIC_CHEN_CH10_Disabled (0UL) /*!< Disable channel */ 554 #define DPPIC_CHEN_CH10_Enabled (1UL) /*!< Enable channel */ 555 556 /* Bit 9 : Enable or disable channel 9 */ 557 #define DPPIC_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */ 558 #define DPPIC_CHEN_CH9_Msk (0x1UL << DPPIC_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */ 559 #define DPPIC_CHEN_CH9_Disabled (0UL) /*!< Disable channel */ 560 #define DPPIC_CHEN_CH9_Enabled (1UL) /*!< Enable channel */ 561 562 /* Bit 8 : Enable or disable channel 8 */ 563 #define DPPIC_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */ 564 #define DPPIC_CHEN_CH8_Msk (0x1UL << DPPIC_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */ 565 #define DPPIC_CHEN_CH8_Disabled (0UL) /*!< Disable channel */ 566 #define DPPIC_CHEN_CH8_Enabled (1UL) /*!< Enable channel */ 567 568 /* Bit 7 : Enable or disable channel 7 */ 569 #define DPPIC_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */ 570 #define DPPIC_CHEN_CH7_Msk (0x1UL << DPPIC_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */ 571 #define DPPIC_CHEN_CH7_Disabled (0UL) /*!< Disable channel */ 572 #define DPPIC_CHEN_CH7_Enabled (1UL) /*!< Enable channel */ 573 574 /* Bit 6 : Enable or disable channel 6 */ 575 #define DPPIC_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */ 576 #define DPPIC_CHEN_CH6_Msk (0x1UL << DPPIC_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */ 577 #define DPPIC_CHEN_CH6_Disabled (0UL) /*!< Disable channel */ 578 #define DPPIC_CHEN_CH6_Enabled (1UL) /*!< Enable channel */ 579 580 /* Bit 5 : Enable or disable channel 5 */ 581 #define DPPIC_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */ 582 #define DPPIC_CHEN_CH5_Msk (0x1UL << DPPIC_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */ 583 #define DPPIC_CHEN_CH5_Disabled (0UL) /*!< Disable channel */ 584 #define DPPIC_CHEN_CH5_Enabled (1UL) /*!< Enable channel */ 585 586 /* Bit 4 : Enable or disable channel 4 */ 587 #define DPPIC_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */ 588 #define DPPIC_CHEN_CH4_Msk (0x1UL << DPPIC_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */ 589 #define DPPIC_CHEN_CH4_Disabled (0UL) /*!< Disable channel */ 590 #define DPPIC_CHEN_CH4_Enabled (1UL) /*!< Enable channel */ 591 592 /* Bit 3 : Enable or disable channel 3 */ 593 #define DPPIC_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */ 594 #define DPPIC_CHEN_CH3_Msk (0x1UL << DPPIC_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */ 595 #define DPPIC_CHEN_CH3_Disabled (0UL) /*!< Disable channel */ 596 #define DPPIC_CHEN_CH3_Enabled (1UL) /*!< Enable channel */ 597 598 /* Bit 2 : Enable or disable channel 2 */ 599 #define DPPIC_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */ 600 #define DPPIC_CHEN_CH2_Msk (0x1UL << DPPIC_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */ 601 #define DPPIC_CHEN_CH2_Disabled (0UL) /*!< Disable channel */ 602 #define DPPIC_CHEN_CH2_Enabled (1UL) /*!< Enable channel */ 603 604 /* Bit 1 : Enable or disable channel 1 */ 605 #define DPPIC_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */ 606 #define DPPIC_CHEN_CH1_Msk (0x1UL << DPPIC_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */ 607 #define DPPIC_CHEN_CH1_Disabled (0UL) /*!< Disable channel */ 608 #define DPPIC_CHEN_CH1_Enabled (1UL) /*!< Enable channel */ 609 610 /* Bit 0 : Enable or disable channel 0 */ 611 #define DPPIC_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ 612 #define DPPIC_CHEN_CH0_Msk (0x1UL << DPPIC_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ 613 #define DPPIC_CHEN_CH0_Disabled (0UL) /*!< Disable channel */ 614 #define DPPIC_CHEN_CH0_Enabled (1UL) /*!< Enable channel */ 615 616 /* Register: DPPIC_CHENSET */ 617 /* Description: Channel enable set register */ 618 619 /* Bit 15 : Channel 15 enable set register. Writing 0 has no effect. */ 620 #define DPPIC_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ 621 #define DPPIC_CHENSET_CH15_Msk (0x1UL << DPPIC_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ 622 #define DPPIC_CHENSET_CH15_Disabled (0UL) /*!< Read: Channel disabled */ 623 #define DPPIC_CHENSET_CH15_Enabled (1UL) /*!< Read: Channel enabled */ 624 #define DPPIC_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */ 625 626 /* Bit 14 : Channel 14 enable set register. Writing 0 has no effect. */ 627 #define DPPIC_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ 628 #define DPPIC_CHENSET_CH14_Msk (0x1UL << DPPIC_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ 629 #define DPPIC_CHENSET_CH14_Disabled (0UL) /*!< Read: Channel disabled */ 630 #define DPPIC_CHENSET_CH14_Enabled (1UL) /*!< Read: Channel enabled */ 631 #define DPPIC_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */ 632 633 /* Bit 13 : Channel 13 enable set register. Writing 0 has no effect. */ 634 #define DPPIC_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ 635 #define DPPIC_CHENSET_CH13_Msk (0x1UL << DPPIC_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ 636 #define DPPIC_CHENSET_CH13_Disabled (0UL) /*!< Read: Channel disabled */ 637 #define DPPIC_CHENSET_CH13_Enabled (1UL) /*!< Read: Channel enabled */ 638 #define DPPIC_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */ 639 640 /* Bit 12 : Channel 12 enable set register. Writing 0 has no effect. */ 641 #define DPPIC_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ 642 #define DPPIC_CHENSET_CH12_Msk (0x1UL << DPPIC_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ 643 #define DPPIC_CHENSET_CH12_Disabled (0UL) /*!< Read: Channel disabled */ 644 #define DPPIC_CHENSET_CH12_Enabled (1UL) /*!< Read: Channel enabled */ 645 #define DPPIC_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */ 646 647 /* Bit 11 : Channel 11 enable set register. Writing 0 has no effect. */ 648 #define DPPIC_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ 649 #define DPPIC_CHENSET_CH11_Msk (0x1UL << DPPIC_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ 650 #define DPPIC_CHENSET_CH11_Disabled (0UL) /*!< Read: Channel disabled */ 651 #define DPPIC_CHENSET_CH11_Enabled (1UL) /*!< Read: Channel enabled */ 652 #define DPPIC_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */ 653 654 /* Bit 10 : Channel 10 enable set register. Writing 0 has no effect. */ 655 #define DPPIC_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ 656 #define DPPIC_CHENSET_CH10_Msk (0x1UL << DPPIC_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ 657 #define DPPIC_CHENSET_CH10_Disabled (0UL) /*!< Read: Channel disabled */ 658 #define DPPIC_CHENSET_CH10_Enabled (1UL) /*!< Read: Channel enabled */ 659 #define DPPIC_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */ 660 661 /* Bit 9 : Channel 9 enable set register. Writing 0 has no effect. */ 662 #define DPPIC_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ 663 #define DPPIC_CHENSET_CH9_Msk (0x1UL << DPPIC_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ 664 #define DPPIC_CHENSET_CH9_Disabled (0UL) /*!< Read: Channel disabled */ 665 #define DPPIC_CHENSET_CH9_Enabled (1UL) /*!< Read: Channel enabled */ 666 #define DPPIC_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */ 667 668 /* Bit 8 : Channel 8 enable set register. Writing 0 has no effect. */ 669 #define DPPIC_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ 670 #define DPPIC_CHENSET_CH8_Msk (0x1UL << DPPIC_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ 671 #define DPPIC_CHENSET_CH8_Disabled (0UL) /*!< Read: Channel disabled */ 672 #define DPPIC_CHENSET_CH8_Enabled (1UL) /*!< Read: Channel enabled */ 673 #define DPPIC_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */ 674 675 /* Bit 7 : Channel 7 enable set register. Writing 0 has no effect. */ 676 #define DPPIC_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ 677 #define DPPIC_CHENSET_CH7_Msk (0x1UL << DPPIC_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ 678 #define DPPIC_CHENSET_CH7_Disabled (0UL) /*!< Read: Channel disabled */ 679 #define DPPIC_CHENSET_CH7_Enabled (1UL) /*!< Read: Channel enabled */ 680 #define DPPIC_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */ 681 682 /* Bit 6 : Channel 6 enable set register. Writing 0 has no effect. */ 683 #define DPPIC_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ 684 #define DPPIC_CHENSET_CH6_Msk (0x1UL << DPPIC_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ 685 #define DPPIC_CHENSET_CH6_Disabled (0UL) /*!< Read: Channel disabled */ 686 #define DPPIC_CHENSET_CH6_Enabled (1UL) /*!< Read: Channel enabled */ 687 #define DPPIC_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */ 688 689 /* Bit 5 : Channel 5 enable set register. Writing 0 has no effect. */ 690 #define DPPIC_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ 691 #define DPPIC_CHENSET_CH5_Msk (0x1UL << DPPIC_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ 692 #define DPPIC_CHENSET_CH5_Disabled (0UL) /*!< Read: Channel disabled */ 693 #define DPPIC_CHENSET_CH5_Enabled (1UL) /*!< Read: Channel enabled */ 694 #define DPPIC_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */ 695 696 /* Bit 4 : Channel 4 enable set register. Writing 0 has no effect. */ 697 #define DPPIC_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ 698 #define DPPIC_CHENSET_CH4_Msk (0x1UL << DPPIC_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ 699 #define DPPIC_CHENSET_CH4_Disabled (0UL) /*!< Read: Channel disabled */ 700 #define DPPIC_CHENSET_CH4_Enabled (1UL) /*!< Read: Channel enabled */ 701 #define DPPIC_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */ 702 703 /* Bit 3 : Channel 3 enable set register. Writing 0 has no effect. */ 704 #define DPPIC_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ 705 #define DPPIC_CHENSET_CH3_Msk (0x1UL << DPPIC_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ 706 #define DPPIC_CHENSET_CH3_Disabled (0UL) /*!< Read: Channel disabled */ 707 #define DPPIC_CHENSET_CH3_Enabled (1UL) /*!< Read: Channel enabled */ 708 #define DPPIC_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */ 709 710 /* Bit 2 : Channel 2 enable set register. Writing 0 has no effect. */ 711 #define DPPIC_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ 712 #define DPPIC_CHENSET_CH2_Msk (0x1UL << DPPIC_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ 713 #define DPPIC_CHENSET_CH2_Disabled (0UL) /*!< Read: Channel disabled */ 714 #define DPPIC_CHENSET_CH2_Enabled (1UL) /*!< Read: Channel enabled */ 715 #define DPPIC_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */ 716 717 /* Bit 1 : Channel 1 enable set register. Writing 0 has no effect. */ 718 #define DPPIC_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ 719 #define DPPIC_CHENSET_CH1_Msk (0x1UL << DPPIC_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ 720 #define DPPIC_CHENSET_CH1_Disabled (0UL) /*!< Read: Channel disabled */ 721 #define DPPIC_CHENSET_CH1_Enabled (1UL) /*!< Read: Channel enabled */ 722 #define DPPIC_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */ 723 724 /* Bit 0 : Channel 0 enable set register. Writing 0 has no effect. */ 725 #define DPPIC_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ 726 #define DPPIC_CHENSET_CH0_Msk (0x1UL << DPPIC_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ 727 #define DPPIC_CHENSET_CH0_Disabled (0UL) /*!< Read: Channel disabled */ 728 #define DPPIC_CHENSET_CH0_Enabled (1UL) /*!< Read: Channel enabled */ 729 #define DPPIC_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */ 730 731 /* Register: DPPIC_CHENCLR */ 732 /* Description: Channel enable clear register */ 733 734 /* Bit 15 : Channel 15 enable clear register. Writing 0 has no effect. */ 735 #define DPPIC_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ 736 #define DPPIC_CHENCLR_CH15_Msk (0x1UL << DPPIC_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ 737 #define DPPIC_CHENCLR_CH15_Disabled (0UL) /*!< Read: Channel disabled */ 738 #define DPPIC_CHENCLR_CH15_Enabled (1UL) /*!< Read: Channel enabled */ 739 #define DPPIC_CHENCLR_CH15_Clear (1UL) /*!< Write: Disable channel */ 740 741 /* Bit 14 : Channel 14 enable clear register. Writing 0 has no effect. */ 742 #define DPPIC_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ 743 #define DPPIC_CHENCLR_CH14_Msk (0x1UL << DPPIC_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ 744 #define DPPIC_CHENCLR_CH14_Disabled (0UL) /*!< Read: Channel disabled */ 745 #define DPPIC_CHENCLR_CH14_Enabled (1UL) /*!< Read: Channel enabled */ 746 #define DPPIC_CHENCLR_CH14_Clear (1UL) /*!< Write: Disable channel */ 747 748 /* Bit 13 : Channel 13 enable clear register. Writing 0 has no effect. */ 749 #define DPPIC_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ 750 #define DPPIC_CHENCLR_CH13_Msk (0x1UL << DPPIC_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ 751 #define DPPIC_CHENCLR_CH13_Disabled (0UL) /*!< Read: Channel disabled */ 752 #define DPPIC_CHENCLR_CH13_Enabled (1UL) /*!< Read: Channel enabled */ 753 #define DPPIC_CHENCLR_CH13_Clear (1UL) /*!< Write: Disable channel */ 754 755 /* Bit 12 : Channel 12 enable clear register. Writing 0 has no effect. */ 756 #define DPPIC_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ 757 #define DPPIC_CHENCLR_CH12_Msk (0x1UL << DPPIC_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ 758 #define DPPIC_CHENCLR_CH12_Disabled (0UL) /*!< Read: Channel disabled */ 759 #define DPPIC_CHENCLR_CH12_Enabled (1UL) /*!< Read: Channel enabled */ 760 #define DPPIC_CHENCLR_CH12_Clear (1UL) /*!< Write: Disable channel */ 761 762 /* Bit 11 : Channel 11 enable clear register. Writing 0 has no effect. */ 763 #define DPPIC_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ 764 #define DPPIC_CHENCLR_CH11_Msk (0x1UL << DPPIC_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ 765 #define DPPIC_CHENCLR_CH11_Disabled (0UL) /*!< Read: Channel disabled */ 766 #define DPPIC_CHENCLR_CH11_Enabled (1UL) /*!< Read: Channel enabled */ 767 #define DPPIC_CHENCLR_CH11_Clear (1UL) /*!< Write: Disable channel */ 768 769 /* Bit 10 : Channel 10 enable clear register. Writing 0 has no effect. */ 770 #define DPPIC_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ 771 #define DPPIC_CHENCLR_CH10_Msk (0x1UL << DPPIC_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ 772 #define DPPIC_CHENCLR_CH10_Disabled (0UL) /*!< Read: Channel disabled */ 773 #define DPPIC_CHENCLR_CH10_Enabled (1UL) /*!< Read: Channel enabled */ 774 #define DPPIC_CHENCLR_CH10_Clear (1UL) /*!< Write: Disable channel */ 775 776 /* Bit 9 : Channel 9 enable clear register. Writing 0 has no effect. */ 777 #define DPPIC_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ 778 #define DPPIC_CHENCLR_CH9_Msk (0x1UL << DPPIC_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ 779 #define DPPIC_CHENCLR_CH9_Disabled (0UL) /*!< Read: Channel disabled */ 780 #define DPPIC_CHENCLR_CH9_Enabled (1UL) /*!< Read: Channel enabled */ 781 #define DPPIC_CHENCLR_CH9_Clear (1UL) /*!< Write: Disable channel */ 782 783 /* Bit 8 : Channel 8 enable clear register. Writing 0 has no effect. */ 784 #define DPPIC_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ 785 #define DPPIC_CHENCLR_CH8_Msk (0x1UL << DPPIC_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ 786 #define DPPIC_CHENCLR_CH8_Disabled (0UL) /*!< Read: Channel disabled */ 787 #define DPPIC_CHENCLR_CH8_Enabled (1UL) /*!< Read: Channel enabled */ 788 #define DPPIC_CHENCLR_CH8_Clear (1UL) /*!< Write: Disable channel */ 789 790 /* Bit 7 : Channel 7 enable clear register. Writing 0 has no effect. */ 791 #define DPPIC_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ 792 #define DPPIC_CHENCLR_CH7_Msk (0x1UL << DPPIC_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ 793 #define DPPIC_CHENCLR_CH7_Disabled (0UL) /*!< Read: Channel disabled */ 794 #define DPPIC_CHENCLR_CH7_Enabled (1UL) /*!< Read: Channel enabled */ 795 #define DPPIC_CHENCLR_CH7_Clear (1UL) /*!< Write: Disable channel */ 796 797 /* Bit 6 : Channel 6 enable clear register. Writing 0 has no effect. */ 798 #define DPPIC_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ 799 #define DPPIC_CHENCLR_CH6_Msk (0x1UL << DPPIC_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ 800 #define DPPIC_CHENCLR_CH6_Disabled (0UL) /*!< Read: Channel disabled */ 801 #define DPPIC_CHENCLR_CH6_Enabled (1UL) /*!< Read: Channel enabled */ 802 #define DPPIC_CHENCLR_CH6_Clear (1UL) /*!< Write: Disable channel */ 803 804 /* Bit 5 : Channel 5 enable clear register. Writing 0 has no effect. */ 805 #define DPPIC_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ 806 #define DPPIC_CHENCLR_CH5_Msk (0x1UL << DPPIC_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ 807 #define DPPIC_CHENCLR_CH5_Disabled (0UL) /*!< Read: Channel disabled */ 808 #define DPPIC_CHENCLR_CH5_Enabled (1UL) /*!< Read: Channel enabled */ 809 #define DPPIC_CHENCLR_CH5_Clear (1UL) /*!< Write: Disable channel */ 810 811 /* Bit 4 : Channel 4 enable clear register. Writing 0 has no effect. */ 812 #define DPPIC_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ 813 #define DPPIC_CHENCLR_CH4_Msk (0x1UL << DPPIC_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ 814 #define DPPIC_CHENCLR_CH4_Disabled (0UL) /*!< Read: Channel disabled */ 815 #define DPPIC_CHENCLR_CH4_Enabled (1UL) /*!< Read: Channel enabled */ 816 #define DPPIC_CHENCLR_CH4_Clear (1UL) /*!< Write: Disable channel */ 817 818 /* Bit 3 : Channel 3 enable clear register. Writing 0 has no effect. */ 819 #define DPPIC_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ 820 #define DPPIC_CHENCLR_CH3_Msk (0x1UL << DPPIC_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ 821 #define DPPIC_CHENCLR_CH3_Disabled (0UL) /*!< Read: Channel disabled */ 822 #define DPPIC_CHENCLR_CH3_Enabled (1UL) /*!< Read: Channel enabled */ 823 #define DPPIC_CHENCLR_CH3_Clear (1UL) /*!< Write: Disable channel */ 824 825 /* Bit 2 : Channel 2 enable clear register. Writing 0 has no effect. */ 826 #define DPPIC_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ 827 #define DPPIC_CHENCLR_CH2_Msk (0x1UL << DPPIC_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ 828 #define DPPIC_CHENCLR_CH2_Disabled (0UL) /*!< Read: Channel disabled */ 829 #define DPPIC_CHENCLR_CH2_Enabled (1UL) /*!< Read: Channel enabled */ 830 #define DPPIC_CHENCLR_CH2_Clear (1UL) /*!< Write: Disable channel */ 831 832 /* Bit 1 : Channel 1 enable clear register. Writing 0 has no effect. */ 833 #define DPPIC_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ 834 #define DPPIC_CHENCLR_CH1_Msk (0x1UL << DPPIC_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ 835 #define DPPIC_CHENCLR_CH1_Disabled (0UL) /*!< Read: Channel disabled */ 836 #define DPPIC_CHENCLR_CH1_Enabled (1UL) /*!< Read: Channel enabled */ 837 #define DPPIC_CHENCLR_CH1_Clear (1UL) /*!< Write: Disable channel */ 838 839 /* Bit 0 : Channel 0 enable clear register. Writing 0 has no effect. */ 840 #define DPPIC_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ 841 #define DPPIC_CHENCLR_CH0_Msk (0x1UL << DPPIC_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ 842 #define DPPIC_CHENCLR_CH0_Disabled (0UL) /*!< Read: Channel disabled */ 843 #define DPPIC_CHENCLR_CH0_Enabled (1UL) /*!< Read: Channel enabled */ 844 #define DPPIC_CHENCLR_CH0_Clear (1UL) /*!< Write: Disable channel */ 845 846 /* Register: DPPIC_CHG */ 847 /* Description: Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled */ 848 849 /* Bit 15 : Include or exclude channel 15 */ 850 #define DPPIC_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */ 851 #define DPPIC_CHG_CH15_Msk (0x1UL << DPPIC_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */ 852 #define DPPIC_CHG_CH15_Excluded (0UL) /*!< Exclude */ 853 #define DPPIC_CHG_CH15_Included (1UL) /*!< Include */ 854 855 /* Bit 14 : Include or exclude channel 14 */ 856 #define DPPIC_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */ 857 #define DPPIC_CHG_CH14_Msk (0x1UL << DPPIC_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */ 858 #define DPPIC_CHG_CH14_Excluded (0UL) /*!< Exclude */ 859 #define DPPIC_CHG_CH14_Included (1UL) /*!< Include */ 860 861 /* Bit 13 : Include or exclude channel 13 */ 862 #define DPPIC_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */ 863 #define DPPIC_CHG_CH13_Msk (0x1UL << DPPIC_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */ 864 #define DPPIC_CHG_CH13_Excluded (0UL) /*!< Exclude */ 865 #define DPPIC_CHG_CH13_Included (1UL) /*!< Include */ 866 867 /* Bit 12 : Include or exclude channel 12 */ 868 #define DPPIC_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */ 869 #define DPPIC_CHG_CH12_Msk (0x1UL << DPPIC_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */ 870 #define DPPIC_CHG_CH12_Excluded (0UL) /*!< Exclude */ 871 #define DPPIC_CHG_CH12_Included (1UL) /*!< Include */ 872 873 /* Bit 11 : Include or exclude channel 11 */ 874 #define DPPIC_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */ 875 #define DPPIC_CHG_CH11_Msk (0x1UL << DPPIC_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */ 876 #define DPPIC_CHG_CH11_Excluded (0UL) /*!< Exclude */ 877 #define DPPIC_CHG_CH11_Included (1UL) /*!< Include */ 878 879 /* Bit 10 : Include or exclude channel 10 */ 880 #define DPPIC_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */ 881 #define DPPIC_CHG_CH10_Msk (0x1UL << DPPIC_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */ 882 #define DPPIC_CHG_CH10_Excluded (0UL) /*!< Exclude */ 883 #define DPPIC_CHG_CH10_Included (1UL) /*!< Include */ 884 885 /* Bit 9 : Include or exclude channel 9 */ 886 #define DPPIC_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */ 887 #define DPPIC_CHG_CH9_Msk (0x1UL << DPPIC_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */ 888 #define DPPIC_CHG_CH9_Excluded (0UL) /*!< Exclude */ 889 #define DPPIC_CHG_CH9_Included (1UL) /*!< Include */ 890 891 /* Bit 8 : Include or exclude channel 8 */ 892 #define DPPIC_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */ 893 #define DPPIC_CHG_CH8_Msk (0x1UL << DPPIC_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */ 894 #define DPPIC_CHG_CH8_Excluded (0UL) /*!< Exclude */ 895 #define DPPIC_CHG_CH8_Included (1UL) /*!< Include */ 896 897 /* Bit 7 : Include or exclude channel 7 */ 898 #define DPPIC_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */ 899 #define DPPIC_CHG_CH7_Msk (0x1UL << DPPIC_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */ 900 #define DPPIC_CHG_CH7_Excluded (0UL) /*!< Exclude */ 901 #define DPPIC_CHG_CH7_Included (1UL) /*!< Include */ 902 903 /* Bit 6 : Include or exclude channel 6 */ 904 #define DPPIC_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */ 905 #define DPPIC_CHG_CH6_Msk (0x1UL << DPPIC_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */ 906 #define DPPIC_CHG_CH6_Excluded (0UL) /*!< Exclude */ 907 #define DPPIC_CHG_CH6_Included (1UL) /*!< Include */ 908 909 /* Bit 5 : Include or exclude channel 5 */ 910 #define DPPIC_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */ 911 #define DPPIC_CHG_CH5_Msk (0x1UL << DPPIC_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */ 912 #define DPPIC_CHG_CH5_Excluded (0UL) /*!< Exclude */ 913 #define DPPIC_CHG_CH5_Included (1UL) /*!< Include */ 914 915 /* Bit 4 : Include or exclude channel 4 */ 916 #define DPPIC_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */ 917 #define DPPIC_CHG_CH4_Msk (0x1UL << DPPIC_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */ 918 #define DPPIC_CHG_CH4_Excluded (0UL) /*!< Exclude */ 919 #define DPPIC_CHG_CH4_Included (1UL) /*!< Include */ 920 921 /* Bit 3 : Include or exclude channel 3 */ 922 #define DPPIC_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */ 923 #define DPPIC_CHG_CH3_Msk (0x1UL << DPPIC_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */ 924 #define DPPIC_CHG_CH3_Excluded (0UL) /*!< Exclude */ 925 #define DPPIC_CHG_CH3_Included (1UL) /*!< Include */ 926 927 /* Bit 2 : Include or exclude channel 2 */ 928 #define DPPIC_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */ 929 #define DPPIC_CHG_CH2_Msk (0x1UL << DPPIC_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */ 930 #define DPPIC_CHG_CH2_Excluded (0UL) /*!< Exclude */ 931 #define DPPIC_CHG_CH2_Included (1UL) /*!< Include */ 932 933 /* Bit 1 : Include or exclude channel 1 */ 934 #define DPPIC_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */ 935 #define DPPIC_CHG_CH1_Msk (0x1UL << DPPIC_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */ 936 #define DPPIC_CHG_CH1_Excluded (0UL) /*!< Exclude */ 937 #define DPPIC_CHG_CH1_Included (1UL) /*!< Include */ 938 939 /* Bit 0 : Include or exclude channel 0 */ 940 #define DPPIC_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */ 941 #define DPPIC_CHG_CH0_Msk (0x1UL << DPPIC_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */ 942 #define DPPIC_CHG_CH0_Excluded (0UL) /*!< Exclude */ 943 #define DPPIC_CHG_CH0_Included (1UL) /*!< Include */ 944 945 946 /* Peripheral: EGU */ 947 /* Description: Event generator unit 0 */ 948 949 /* Register: EGU_TASKS_TRIGGER */ 950 /* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */ 951 952 /* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */ 953 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */ 954 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */ 955 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL) /*!< Trigger task */ 956 957 /* Register: EGU_SUBSCRIBE_TRIGGER */ 958 /* Description: Description collection: Subscribe configuration for task TRIGGER[n] */ 959 960 /* Bit 31 : */ 961 #define EGU_SUBSCRIBE_TRIGGER_EN_Pos (31UL) /*!< Position of EN field. */ 962 #define EGU_SUBSCRIBE_TRIGGER_EN_Msk (0x1UL << EGU_SUBSCRIBE_TRIGGER_EN_Pos) /*!< Bit mask of EN field. */ 963 #define EGU_SUBSCRIBE_TRIGGER_EN_Disabled (0UL) /*!< Disable subscription */ 964 #define EGU_SUBSCRIBE_TRIGGER_EN_Enabled (1UL) /*!< Enable subscription */ 965 966 /* Bits 7..0 : DPPI channel that task TRIGGER[n] will subscribe to */ 967 #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 968 #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Msk (0xFFUL << EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 969 970 /* Register: EGU_EVENTS_TRIGGERED */ 971 /* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */ 972 973 /* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */ 974 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */ 975 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */ 976 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0UL) /*!< Event not generated */ 977 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL) /*!< Event generated */ 978 979 /* Register: EGU_PUBLISH_TRIGGERED */ 980 /* Description: Description collection: Publish configuration for event TRIGGERED[n] */ 981 982 /* Bit 31 : */ 983 #define EGU_PUBLISH_TRIGGERED_EN_Pos (31UL) /*!< Position of EN field. */ 984 #define EGU_PUBLISH_TRIGGERED_EN_Msk (0x1UL << EGU_PUBLISH_TRIGGERED_EN_Pos) /*!< Bit mask of EN field. */ 985 #define EGU_PUBLISH_TRIGGERED_EN_Disabled (0UL) /*!< Disable publishing */ 986 #define EGU_PUBLISH_TRIGGERED_EN_Enabled (1UL) /*!< Enable publishing */ 987 988 /* Bits 7..0 : DPPI channel that event TRIGGERED[n] will publish to */ 989 #define EGU_PUBLISH_TRIGGERED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 990 #define EGU_PUBLISH_TRIGGERED_CHIDX_Msk (0xFFUL << EGU_PUBLISH_TRIGGERED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 991 992 /* Register: EGU_INTEN */ 993 /* Description: Enable or disable interrupt */ 994 995 /* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */ 996 #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ 997 #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ 998 #define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */ 999 #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */ 1000 1001 /* Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */ 1002 #define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ 1003 #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ 1004 #define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */ 1005 #define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */ 1006 1007 /* Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */ 1008 #define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ 1009 #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ 1010 #define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */ 1011 #define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */ 1012 1013 /* Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */ 1014 #define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ 1015 #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ 1016 #define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */ 1017 #define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */ 1018 1019 /* Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */ 1020 #define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ 1021 #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ 1022 #define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */ 1023 #define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */ 1024 1025 /* Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */ 1026 #define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ 1027 #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ 1028 #define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */ 1029 #define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */ 1030 1031 /* Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */ 1032 #define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ 1033 #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ 1034 #define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */ 1035 #define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */ 1036 1037 /* Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */ 1038 #define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ 1039 #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ 1040 #define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */ 1041 #define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */ 1042 1043 /* Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */ 1044 #define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ 1045 #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ 1046 #define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */ 1047 #define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */ 1048 1049 /* Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */ 1050 #define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ 1051 #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ 1052 #define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */ 1053 #define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */ 1054 1055 /* Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */ 1056 #define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ 1057 #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ 1058 #define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */ 1059 #define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */ 1060 1061 /* Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */ 1062 #define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ 1063 #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ 1064 #define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */ 1065 #define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */ 1066 1067 /* Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */ 1068 #define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ 1069 #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ 1070 #define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */ 1071 #define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */ 1072 1073 /* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */ 1074 #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ 1075 #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ 1076 #define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */ 1077 #define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */ 1078 1079 /* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */ 1080 #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ 1081 #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ 1082 #define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */ 1083 #define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */ 1084 1085 /* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */ 1086 #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ 1087 #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ 1088 #define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */ 1089 #define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */ 1090 1091 /* Register: EGU_INTENSET */ 1092 /* Description: Enable interrupt */ 1093 1094 /* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */ 1095 #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ 1096 #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ 1097 #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ 1098 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ 1099 #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */ 1100 1101 /* Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */ 1102 #define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ 1103 #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ 1104 #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ 1105 #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ 1106 #define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */ 1107 1108 /* Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */ 1109 #define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ 1110 #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ 1111 #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ 1112 #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ 1113 #define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */ 1114 1115 /* Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */ 1116 #define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ 1117 #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ 1118 #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ 1119 #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ 1120 #define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */ 1121 1122 /* Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */ 1123 #define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ 1124 #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ 1125 #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ 1126 #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ 1127 #define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */ 1128 1129 /* Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */ 1130 #define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ 1131 #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ 1132 #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ 1133 #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ 1134 #define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */ 1135 1136 /* Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */ 1137 #define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ 1138 #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ 1139 #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ 1140 #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ 1141 #define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */ 1142 1143 /* Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */ 1144 #define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ 1145 #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ 1146 #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ 1147 #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ 1148 #define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */ 1149 1150 /* Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */ 1151 #define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ 1152 #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ 1153 #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ 1154 #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ 1155 #define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */ 1156 1157 /* Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */ 1158 #define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ 1159 #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ 1160 #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ 1161 #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ 1162 #define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */ 1163 1164 /* Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */ 1165 #define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ 1166 #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ 1167 #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ 1168 #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ 1169 #define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */ 1170 1171 /* Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */ 1172 #define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ 1173 #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ 1174 #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ 1175 #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ 1176 #define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */ 1177 1178 /* Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */ 1179 #define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ 1180 #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ 1181 #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ 1182 #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ 1183 #define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */ 1184 1185 /* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */ 1186 #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ 1187 #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ 1188 #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ 1189 #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ 1190 #define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */ 1191 1192 /* Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */ 1193 #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ 1194 #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ 1195 #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ 1196 #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ 1197 #define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */ 1198 1199 /* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */ 1200 #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ 1201 #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ 1202 #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ 1203 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ 1204 #define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */ 1205 1206 /* Register: EGU_INTENCLR */ 1207 /* Description: Disable interrupt */ 1208 1209 /* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */ 1210 #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ 1211 #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ 1212 #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ 1213 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ 1214 #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */ 1215 1216 /* Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */ 1217 #define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ 1218 #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ 1219 #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ 1220 #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ 1221 #define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */ 1222 1223 /* Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */ 1224 #define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ 1225 #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ 1226 #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ 1227 #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ 1228 #define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */ 1229 1230 /* Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */ 1231 #define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ 1232 #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ 1233 #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ 1234 #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ 1235 #define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */ 1236 1237 /* Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */ 1238 #define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ 1239 #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ 1240 #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ 1241 #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ 1242 #define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */ 1243 1244 /* Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */ 1245 #define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ 1246 #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ 1247 #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ 1248 #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ 1249 #define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */ 1250 1251 /* Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */ 1252 #define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ 1253 #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ 1254 #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ 1255 #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ 1256 #define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */ 1257 1258 /* Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */ 1259 #define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ 1260 #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ 1261 #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ 1262 #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ 1263 #define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */ 1264 1265 /* Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */ 1266 #define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ 1267 #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ 1268 #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ 1269 #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ 1270 #define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */ 1271 1272 /* Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */ 1273 #define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ 1274 #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ 1275 #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ 1276 #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ 1277 #define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */ 1278 1279 /* Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */ 1280 #define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ 1281 #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ 1282 #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ 1283 #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ 1284 #define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */ 1285 1286 /* Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */ 1287 #define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ 1288 #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ 1289 #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ 1290 #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ 1291 #define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */ 1292 1293 /* Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */ 1294 #define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ 1295 #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ 1296 #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ 1297 #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ 1298 #define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */ 1299 1300 /* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */ 1301 #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ 1302 #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ 1303 #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ 1304 #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ 1305 #define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */ 1306 1307 /* Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */ 1308 #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ 1309 #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ 1310 #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ 1311 #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ 1312 #define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */ 1313 1314 /* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */ 1315 #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ 1316 #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ 1317 #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ 1318 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ 1319 #define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */ 1320 1321 1322 /* Peripheral: FICR */ 1323 /* Description: Factory Information Configuration Registers */ 1324 1325 /* Register: FICR_SIPINFO_PARTNO */ 1326 /* Description: SIP part number */ 1327 1328 /* Bits 31..0 : */ 1329 #define FICR_SIPINFO_PARTNO_PARTNO_Pos (0UL) /*!< Position of PARTNO field. */ 1330 #define FICR_SIPINFO_PARTNO_PARTNO_Msk (0xFFFFFFFFUL << FICR_SIPINFO_PARTNO_PARTNO_Pos) /*!< Bit mask of PARTNO field. */ 1331 #define FICR_SIPINFO_PARTNO_PARTNO_9160 (0x00009160UL) /*!< Device is an nRF9160 sip */ 1332 1333 /* Register: FICR_SIPINFO_HWREVISION */ 1334 /* Description: Description collection: SIP hardware revision, encoded in ASCII, ex B0A or B1A */ 1335 1336 /* Bits 7..0 : */ 1337 #define FICR_SIPINFO_HWREVISION_HWREVISION_Pos (0UL) /*!< Position of HWREVISION field. */ 1338 #define FICR_SIPINFO_HWREVISION_HWREVISION_Msk (0xFFUL << FICR_SIPINFO_HWREVISION_HWREVISION_Pos) /*!< Bit mask of HWREVISION field. */ 1339 1340 /* Register: FICR_SIPINFO_VARIANT */ 1341 /* Description: Description collection: SIP VARIANT, encoded in ASCII, ex SIAA, SIBA or SICA */ 1342 1343 /* Bits 7..0 : */ 1344 #define FICR_SIPINFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ 1345 #define FICR_SIPINFO_VARIANT_VARIANT_Msk (0xFFUL << FICR_SIPINFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ 1346 1347 /* Register: FICR_INFO_DEVICEID */ 1348 /* Description: Description collection: Device identifier */ 1349 1350 /* Bits 31..0 : 64 bit unique device identifier */ 1351 #define FICR_INFO_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */ 1352 #define FICR_INFO_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */ 1353 1354 /* Register: FICR_INFO_PART */ 1355 /* Description: Part code */ 1356 1357 /* Bits 31..0 : Part code */ 1358 #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */ 1359 #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */ 1360 #define FICR_INFO_PART_PART_N9120 (0x9120UL) /*!< nRF9120 */ 1361 #define FICR_INFO_PART_PART_N9160 (0x9160UL) /*!< nRF9160 */ 1362 1363 /* Register: FICR_INFO_VARIANT */ 1364 /* Description: Part Variant, Hardware version and Production configuration */ 1365 1366 /* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */ 1367 #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ 1368 #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ 1369 #define FICR_INFO_VARIANT_VARIANT_AAA0 (0x41414130UL) /*!< AAA0 */ 1370 #define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */ 1371 #define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */ 1372 #define FICR_INFO_VARIANT_VARIANT_AAC0 (0x41414330UL) /*!< AAC0 */ 1373 1374 /* Register: FICR_INFO_PACKAGE */ 1375 /* Description: Package option */ 1376 1377 /* Bits 31..0 : Package option */ 1378 #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ 1379 #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ 1380 #define FICR_INFO_PACKAGE_PACKAGE_CF (0x2002UL) /*!< CFxx - 236 ball wlCSP */ 1381 1382 /* Register: FICR_INFO_RAM */ 1383 /* Description: RAM variant */ 1384 1385 /* Bits 31..0 : RAM variant */ 1386 #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */ 1387 #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */ 1388 #define FICR_INFO_RAM_RAM_K256 (0x100UL) /*!< 256 kByte RAM */ 1389 #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ 1390 1391 /* Register: FICR_INFO_FLASH */ 1392 /* Description: Flash variant */ 1393 1394 /* Bits 31..0 : Flash variant */ 1395 #define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */ 1396 #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */ 1397 #define FICR_INFO_FLASH_FLASH_K1024 (0x400UL) /*!< 1 MByte FLASH */ 1398 1399 /* Register: FICR_INFO_CODEPAGESIZE */ 1400 /* Description: Code memory page size */ 1401 1402 /* Bits 31..0 : Code memory page size */ 1403 #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */ 1404 #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */ 1405 #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_K4096 (0x1000UL) /*!< 4 kByte */ 1406 1407 /* Register: FICR_INFO_CODESIZE */ 1408 /* Description: Code memory size */ 1409 1410 /* Bits 31..0 : Code memory size in number of pages Total code space is: CODEPAGESIZE * CODESIZE */ 1411 #define FICR_INFO_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */ 1412 #define FICR_INFO_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */ 1413 #define FICR_INFO_CODESIZE_CODESIZE_P256 (256UL) /*!< 256 pages */ 1414 1415 /* Register: FICR_INFO_DEVICETYPE */ 1416 /* Description: Device type */ 1417 1418 /* Bits 31..0 : Device type */ 1419 #define FICR_INFO_DEVICETYPE_DEVICETYPE_Pos (0UL) /*!< Position of DEVICETYPE field. */ 1420 #define FICR_INFO_DEVICETYPE_DEVICETYPE_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICETYPE_DEVICETYPE_Pos) /*!< Bit mask of DEVICETYPE field. */ 1421 #define FICR_INFO_DEVICETYPE_DEVICETYPE_Die (0x0000000UL) /*!< Device is an physical DIE */ 1422 #define FICR_INFO_DEVICETYPE_DEVICETYPE_FPGA (0xFFFFFFFFUL) /*!< Device is an FPGA */ 1423 1424 /* Register: FICR_TRIMCNF_ADDR */ 1425 /* Description: Description cluster: Address */ 1426 1427 /* Bits 31..0 : Address */ 1428 #define FICR_TRIMCNF_ADDR_Address_Pos (0UL) /*!< Position of Address field. */ 1429 #define FICR_TRIMCNF_ADDR_Address_Msk (0xFFFFFFFFUL << FICR_TRIMCNF_ADDR_Address_Pos) /*!< Bit mask of Address field. */ 1430 1431 /* Register: FICR_TRIMCNF_DATA */ 1432 /* Description: Description cluster: Data */ 1433 1434 /* Bits 31..0 : Data */ 1435 #define FICR_TRIMCNF_DATA_Data_Pos (0UL) /*!< Position of Data field. */ 1436 #define FICR_TRIMCNF_DATA_Data_Msk (0xFFFFFFFFUL << FICR_TRIMCNF_DATA_Data_Pos) /*!< Bit mask of Data field. */ 1437 1438 /* Register: FICR_TRNG90B_BYTES */ 1439 /* Description: Amount of bytes for the required entropy bits */ 1440 1441 /* Bits 31..0 : Amount of bytes for the required entropy bits */ 1442 #define FICR_TRNG90B_BYTES_BYTES_Pos (0UL) /*!< Position of BYTES field. */ 1443 #define FICR_TRNG90B_BYTES_BYTES_Msk (0xFFFFFFFFUL << FICR_TRNG90B_BYTES_BYTES_Pos) /*!< Bit mask of BYTES field. */ 1444 1445 /* Register: FICR_TRNG90B_RCCUTOFF */ 1446 /* Description: Repetition counter cutoff */ 1447 1448 /* Bits 31..0 : Repetition counter cutoff */ 1449 #define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos (0UL) /*!< Position of RCCUTOFF field. */ 1450 #define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos) /*!< Bit mask of RCCUTOFF field. */ 1451 1452 /* Register: FICR_TRNG90B_APCUTOFF */ 1453 /* Description: Adaptive proportion cutoff */ 1454 1455 /* Bits 31..0 : Adaptive proportion cutoff */ 1456 #define FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos (0UL) /*!< Position of APCUTOFF field. */ 1457 #define FICR_TRNG90B_APCUTOFF_APCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos) /*!< Bit mask of APCUTOFF field. */ 1458 1459 /* Register: FICR_TRNG90B_STARTUP */ 1460 /* Description: Amount of bytes for the startup tests */ 1461 1462 /* Bits 31..0 : Amount of bytes for the startup tests */ 1463 #define FICR_TRNG90B_STARTUP_STARTUP_Pos (0UL) /*!< Position of STARTUP field. */ 1464 #define FICR_TRNG90B_STARTUP_STARTUP_Msk (0xFFFFFFFFUL << FICR_TRNG90B_STARTUP_STARTUP_Pos) /*!< Bit mask of STARTUP field. */ 1465 1466 /* Register: FICR_TRNG90B_ROSC1 */ 1467 /* Description: Sample count for ring oscillator 1 */ 1468 1469 /* Bits 31..0 : Sample count for ring oscillator 1 */ 1470 #define FICR_TRNG90B_ROSC1_ROSC1_Pos (0UL) /*!< Position of ROSC1 field. */ 1471 #define FICR_TRNG90B_ROSC1_ROSC1_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC1_ROSC1_Pos) /*!< Bit mask of ROSC1 field. */ 1472 1473 /* Register: FICR_TRNG90B_ROSC2 */ 1474 /* Description: Sample count for ring oscillator 2 */ 1475 1476 /* Bits 31..0 : Sample count for ring oscillator 2 */ 1477 #define FICR_TRNG90B_ROSC2_ROSC2_Pos (0UL) /*!< Position of ROSC2 field. */ 1478 #define FICR_TRNG90B_ROSC2_ROSC2_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC2_ROSC2_Pos) /*!< Bit mask of ROSC2 field. */ 1479 1480 /* Register: FICR_TRNG90B_ROSC3 */ 1481 /* Description: Sample count for ring oscillator 3 */ 1482 1483 /* Bits 31..0 : Sample count for ring oscillator 3 */ 1484 #define FICR_TRNG90B_ROSC3_ROSC3_Pos (0UL) /*!< Position of ROSC3 field. */ 1485 #define FICR_TRNG90B_ROSC3_ROSC3_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC3_ROSC3_Pos) /*!< Bit mask of ROSC3 field. */ 1486 1487 /* Register: FICR_TRNG90B_ROSC4 */ 1488 /* Description: Sample count for ring oscillator 4 */ 1489 1490 /* Bits 31..0 : Sample count for ring oscillator 4 */ 1491 #define FICR_TRNG90B_ROSC4_ROSC4_Pos (0UL) /*!< Position of ROSC4 field. */ 1492 #define FICR_TRNG90B_ROSC4_ROSC4_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC4_ROSC4_Pos) /*!< Bit mask of ROSC4 field. */ 1493 1494 1495 /* Peripheral: GPIOTE */ 1496 /* Description: GPIO Tasks and Events 0 */ 1497 1498 /* Register: GPIOTE_TASKS_OUT */ 1499 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ 1500 1501 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ 1502 #define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */ 1503 #define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */ 1504 #define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (1UL) /*!< Trigger task */ 1505 1506 /* Register: GPIOTE_TASKS_SET */ 1507 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ 1508 1509 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ 1510 #define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */ 1511 #define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */ 1512 #define GPIOTE_TASKS_SET_TASKS_SET_Trigger (1UL) /*!< Trigger task */ 1513 1514 /* Register: GPIOTE_TASKS_CLR */ 1515 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ 1516 1517 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ 1518 #define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */ 1519 #define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */ 1520 #define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (1UL) /*!< Trigger task */ 1521 1522 /* Register: GPIOTE_SUBSCRIBE_OUT */ 1523 /* Description: Description collection: Subscribe configuration for task OUT[n] */ 1524 1525 /* Bit 31 : */ 1526 #define GPIOTE_SUBSCRIBE_OUT_EN_Pos (31UL) /*!< Position of EN field. */ 1527 #define GPIOTE_SUBSCRIBE_OUT_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_OUT_EN_Pos) /*!< Bit mask of EN field. */ 1528 #define GPIOTE_SUBSCRIBE_OUT_EN_Disabled (0UL) /*!< Disable subscription */ 1529 #define GPIOTE_SUBSCRIBE_OUT_EN_Enabled (1UL) /*!< Enable subscription */ 1530 1531 /* Bits 7..0 : DPPI channel that task OUT[n] will subscribe to */ 1532 #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1533 #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1534 1535 /* Register: GPIOTE_SUBSCRIBE_SET */ 1536 /* Description: Description collection: Subscribe configuration for task SET[n] */ 1537 1538 /* Bit 31 : */ 1539 #define GPIOTE_SUBSCRIBE_SET_EN_Pos (31UL) /*!< Position of EN field. */ 1540 #define GPIOTE_SUBSCRIBE_SET_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_SET_EN_Pos) /*!< Bit mask of EN field. */ 1541 #define GPIOTE_SUBSCRIBE_SET_EN_Disabled (0UL) /*!< Disable subscription */ 1542 #define GPIOTE_SUBSCRIBE_SET_EN_Enabled (1UL) /*!< Enable subscription */ 1543 1544 /* Bits 7..0 : DPPI channel that task SET[n] will subscribe to */ 1545 #define GPIOTE_SUBSCRIBE_SET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1546 #define GPIOTE_SUBSCRIBE_SET_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_SET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1547 1548 /* Register: GPIOTE_SUBSCRIBE_CLR */ 1549 /* Description: Description collection: Subscribe configuration for task CLR[n] */ 1550 1551 /* Bit 31 : */ 1552 #define GPIOTE_SUBSCRIBE_CLR_EN_Pos (31UL) /*!< Position of EN field. */ 1553 #define GPIOTE_SUBSCRIBE_CLR_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_CLR_EN_Pos) /*!< Bit mask of EN field. */ 1554 #define GPIOTE_SUBSCRIBE_CLR_EN_Disabled (0UL) /*!< Disable subscription */ 1555 #define GPIOTE_SUBSCRIBE_CLR_EN_Enabled (1UL) /*!< Enable subscription */ 1556 1557 /* Bits 7..0 : DPPI channel that task CLR[n] will subscribe to */ 1558 #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1559 #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1560 1561 /* Register: GPIOTE_EVENTS_IN */ 1562 /* Description: Description collection: Event generated from pin specified in CONFIG[n].PSEL */ 1563 1564 /* Bit 0 : Event generated from pin specified in CONFIG[n].PSEL */ 1565 #define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */ 1566 #define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */ 1567 #define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0UL) /*!< Event not generated */ 1568 #define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (1UL) /*!< Event generated */ 1569 1570 /* Register: GPIOTE_EVENTS_PORT */ 1571 /* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */ 1572 1573 /* Bit 0 : Event generated from multiple input GPIO pins with SENSE mechanism enabled */ 1574 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */ 1575 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */ 1576 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0UL) /*!< Event not generated */ 1577 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (1UL) /*!< Event generated */ 1578 1579 /* Register: GPIOTE_PUBLISH_IN */ 1580 /* Description: Description collection: Publish configuration for event IN[n] */ 1581 1582 /* Bit 31 : */ 1583 #define GPIOTE_PUBLISH_IN_EN_Pos (31UL) /*!< Position of EN field. */ 1584 #define GPIOTE_PUBLISH_IN_EN_Msk (0x1UL << GPIOTE_PUBLISH_IN_EN_Pos) /*!< Bit mask of EN field. */ 1585 #define GPIOTE_PUBLISH_IN_EN_Disabled (0UL) /*!< Disable publishing */ 1586 #define GPIOTE_PUBLISH_IN_EN_Enabled (1UL) /*!< Enable publishing */ 1587 1588 /* Bits 7..0 : DPPI channel that event IN[n] will publish to */ 1589 #define GPIOTE_PUBLISH_IN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1590 #define GPIOTE_PUBLISH_IN_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_IN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1591 1592 /* Register: GPIOTE_PUBLISH_PORT */ 1593 /* Description: Publish configuration for event PORT */ 1594 1595 /* Bit 31 : */ 1596 #define GPIOTE_PUBLISH_PORT_EN_Pos (31UL) /*!< Position of EN field. */ 1597 #define GPIOTE_PUBLISH_PORT_EN_Msk (0x1UL << GPIOTE_PUBLISH_PORT_EN_Pos) /*!< Bit mask of EN field. */ 1598 #define GPIOTE_PUBLISH_PORT_EN_Disabled (0UL) /*!< Disable publishing */ 1599 #define GPIOTE_PUBLISH_PORT_EN_Enabled (1UL) /*!< Enable publishing */ 1600 1601 /* Bits 7..0 : DPPI channel that event PORT will publish to */ 1602 #define GPIOTE_PUBLISH_PORT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1603 #define GPIOTE_PUBLISH_PORT_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_PORT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1604 1605 /* Register: GPIOTE_INTENSET */ 1606 /* Description: Enable interrupt */ 1607 1608 /* Bit 31 : Write '1' to enable interrupt for event PORT */ 1609 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ 1610 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ 1611 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */ 1612 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */ 1613 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */ 1614 1615 /* Bit 7 : Write '1' to enable interrupt for event IN[7] */ 1616 #define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */ 1617 #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */ 1618 #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */ 1619 #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */ 1620 #define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */ 1621 1622 /* Bit 6 : Write '1' to enable interrupt for event IN[6] */ 1623 #define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */ 1624 #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */ 1625 #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */ 1626 #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */ 1627 #define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */ 1628 1629 /* Bit 5 : Write '1' to enable interrupt for event IN[5] */ 1630 #define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */ 1631 #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */ 1632 #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */ 1633 #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */ 1634 #define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */ 1635 1636 /* Bit 4 : Write '1' to enable interrupt for event IN[4] */ 1637 #define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */ 1638 #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */ 1639 #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */ 1640 #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */ 1641 #define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */ 1642 1643 /* Bit 3 : Write '1' to enable interrupt for event IN[3] */ 1644 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ 1645 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ 1646 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */ 1647 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */ 1648 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */ 1649 1650 /* Bit 2 : Write '1' to enable interrupt for event IN[2] */ 1651 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ 1652 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ 1653 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */ 1654 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */ 1655 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */ 1656 1657 /* Bit 1 : Write '1' to enable interrupt for event IN[1] */ 1658 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ 1659 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ 1660 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */ 1661 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */ 1662 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */ 1663 1664 /* Bit 0 : Write '1' to enable interrupt for event IN[0] */ 1665 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ 1666 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ 1667 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */ 1668 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */ 1669 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */ 1670 1671 /* Register: GPIOTE_INTENCLR */ 1672 /* Description: Disable interrupt */ 1673 1674 /* Bit 31 : Write '1' to disable interrupt for event PORT */ 1675 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ 1676 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ 1677 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */ 1678 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */ 1679 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */ 1680 1681 /* Bit 7 : Write '1' to disable interrupt for event IN[7] */ 1682 #define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */ 1683 #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */ 1684 #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */ 1685 #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */ 1686 #define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */ 1687 1688 /* Bit 6 : Write '1' to disable interrupt for event IN[6] */ 1689 #define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */ 1690 #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */ 1691 #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */ 1692 #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */ 1693 #define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */ 1694 1695 /* Bit 5 : Write '1' to disable interrupt for event IN[5] */ 1696 #define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */ 1697 #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */ 1698 #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */ 1699 #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */ 1700 #define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */ 1701 1702 /* Bit 4 : Write '1' to disable interrupt for event IN[4] */ 1703 #define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */ 1704 #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */ 1705 #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */ 1706 #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */ 1707 #define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */ 1708 1709 /* Bit 3 : Write '1' to disable interrupt for event IN[3] */ 1710 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ 1711 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ 1712 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */ 1713 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */ 1714 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */ 1715 1716 /* Bit 2 : Write '1' to disable interrupt for event IN[2] */ 1717 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ 1718 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ 1719 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */ 1720 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */ 1721 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */ 1722 1723 /* Bit 1 : Write '1' to disable interrupt for event IN[1] */ 1724 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ 1725 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ 1726 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */ 1727 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */ 1728 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */ 1729 1730 /* Bit 0 : Write '1' to disable interrupt for event IN[0] */ 1731 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ 1732 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ 1733 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */ 1734 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */ 1735 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */ 1736 1737 /* Register: GPIOTE_CONFIG */ 1738 /* Description: Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event */ 1739 1740 /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */ 1741 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ 1742 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */ 1743 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */ 1744 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */ 1745 1746 /* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */ 1747 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */ 1748 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */ 1749 #define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */ 1750 #define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */ 1751 #define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */ 1752 #define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */ 1753 1754 /* Bits 12..8 : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event */ 1755 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ 1756 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ 1757 1758 /* Bits 1..0 : Mode */ 1759 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ 1760 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ 1761 #define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */ 1762 #define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */ 1763 #define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */ 1764 1765 1766 /* Peripheral: I2S */ 1767 /* Description: Inter-IC Sound 0 */ 1768 1769 /* Register: I2S_TASKS_START */ 1770 /* Description: Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */ 1771 1772 /* Bit 0 : Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */ 1773 #define I2S_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 1774 #define I2S_TASKS_START_TASKS_START_Msk (0x1UL << I2S_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 1775 #define I2S_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ 1776 1777 /* Register: I2S_TASKS_STOP */ 1778 /* Description: Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */ 1779 1780 /* Bit 0 : Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */ 1781 #define I2S_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 1782 #define I2S_TASKS_STOP_TASKS_STOP_Msk (0x1UL << I2S_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 1783 #define I2S_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 1784 1785 /* Register: I2S_SUBSCRIBE_START */ 1786 /* Description: Subscribe configuration for task START */ 1787 1788 /* Bit 31 : */ 1789 #define I2S_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ 1790 #define I2S_SUBSCRIBE_START_EN_Msk (0x1UL << I2S_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ 1791 #define I2S_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ 1792 #define I2S_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ 1793 1794 /* Bits 7..0 : DPPI channel that task START will subscribe to */ 1795 #define I2S_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1796 #define I2S_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << I2S_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1797 1798 /* Register: I2S_SUBSCRIBE_STOP */ 1799 /* Description: Subscribe configuration for task STOP */ 1800 1801 /* Bit 31 : */ 1802 #define I2S_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 1803 #define I2S_SUBSCRIBE_STOP_EN_Msk (0x1UL << I2S_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 1804 #define I2S_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ 1805 #define I2S_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ 1806 1807 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 1808 #define I2S_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1809 #define I2S_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << I2S_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1810 1811 /* Register: I2S_EVENTS_RXPTRUPD */ 1812 /* Description: The RXD.PTR register has been copied to internal double-buffers. 1813 When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */ 1814 1815 /* Bit 0 : The RXD.PTR register has been copied to internal double-buffers. 1816 When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */ 1817 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos (0UL) /*!< Position of EVENTS_RXPTRUPD field. */ 1818 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Msk (0x1UL << I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos) /*!< Bit mask of EVENTS_RXPTRUPD field. */ 1819 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_NotGenerated (0UL) /*!< Event not generated */ 1820 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Generated (1UL) /*!< Event generated */ 1821 1822 /* Register: I2S_EVENTS_STOPPED */ 1823 /* Description: I2S transfer stopped. */ 1824 1825 /* Bit 0 : I2S transfer stopped. */ 1826 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ 1827 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ 1828 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ 1829 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ 1830 1831 /* Register: I2S_EVENTS_TXPTRUPD */ 1832 /* Description: The TDX.PTR register has been copied to internal double-buffers. 1833 When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */ 1834 1835 /* Bit 0 : The TDX.PTR register has been copied to internal double-buffers. 1836 When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */ 1837 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos (0UL) /*!< Position of EVENTS_TXPTRUPD field. */ 1838 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Msk (0x1UL << I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos) /*!< Bit mask of EVENTS_TXPTRUPD field. */ 1839 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_NotGenerated (0UL) /*!< Event not generated */ 1840 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Generated (1UL) /*!< Event generated */ 1841 1842 /* Register: I2S_PUBLISH_RXPTRUPD */ 1843 /* Description: Publish configuration for event RXPTRUPD */ 1844 1845 /* Bit 31 : */ 1846 #define I2S_PUBLISH_RXPTRUPD_EN_Pos (31UL) /*!< Position of EN field. */ 1847 #define I2S_PUBLISH_RXPTRUPD_EN_Msk (0x1UL << I2S_PUBLISH_RXPTRUPD_EN_Pos) /*!< Bit mask of EN field. */ 1848 #define I2S_PUBLISH_RXPTRUPD_EN_Disabled (0UL) /*!< Disable publishing */ 1849 #define I2S_PUBLISH_RXPTRUPD_EN_Enabled (1UL) /*!< Enable publishing */ 1850 1851 /* Bits 7..0 : DPPI channel that event RXPTRUPD will publish to */ 1852 #define I2S_PUBLISH_RXPTRUPD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1853 #define I2S_PUBLISH_RXPTRUPD_CHIDX_Msk (0xFFUL << I2S_PUBLISH_RXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1854 1855 /* Register: I2S_PUBLISH_STOPPED */ 1856 /* Description: Publish configuration for event STOPPED */ 1857 1858 /* Bit 31 : */ 1859 #define I2S_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ 1860 #define I2S_PUBLISH_STOPPED_EN_Msk (0x1UL << I2S_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ 1861 #define I2S_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ 1862 #define I2S_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ 1863 1864 /* Bits 7..0 : DPPI channel that event STOPPED will publish to */ 1865 #define I2S_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1866 #define I2S_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << I2S_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1867 1868 /* Register: I2S_PUBLISH_TXPTRUPD */ 1869 /* Description: Publish configuration for event TXPTRUPD */ 1870 1871 /* Bit 31 : */ 1872 #define I2S_PUBLISH_TXPTRUPD_EN_Pos (31UL) /*!< Position of EN field. */ 1873 #define I2S_PUBLISH_TXPTRUPD_EN_Msk (0x1UL << I2S_PUBLISH_TXPTRUPD_EN_Pos) /*!< Bit mask of EN field. */ 1874 #define I2S_PUBLISH_TXPTRUPD_EN_Disabled (0UL) /*!< Disable publishing */ 1875 #define I2S_PUBLISH_TXPTRUPD_EN_Enabled (1UL) /*!< Enable publishing */ 1876 1877 /* Bits 7..0 : DPPI channel that event TXPTRUPD will publish to */ 1878 #define I2S_PUBLISH_TXPTRUPD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1879 #define I2S_PUBLISH_TXPTRUPD_CHIDX_Msk (0xFFUL << I2S_PUBLISH_TXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1880 1881 /* Register: I2S_INTEN */ 1882 /* Description: Enable or disable interrupt */ 1883 1884 /* Bit 5 : Enable or disable interrupt for event TXPTRUPD */ 1885 #define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ 1886 #define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ 1887 #define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */ 1888 #define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */ 1889 1890 /* Bit 2 : Enable or disable interrupt for event STOPPED */ 1891 #define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ 1892 #define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 1893 #define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ 1894 #define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ 1895 1896 /* Bit 1 : Enable or disable interrupt for event RXPTRUPD */ 1897 #define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ 1898 #define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ 1899 #define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */ 1900 #define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */ 1901 1902 /* Register: I2S_INTENSET */ 1903 /* Description: Enable interrupt */ 1904 1905 /* Bit 5 : Write '1' to enable interrupt for event TXPTRUPD */ 1906 #define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ 1907 #define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ 1908 #define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ 1909 #define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ 1910 #define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */ 1911 1912 /* Bit 2 : Write '1' to enable interrupt for event STOPPED */ 1913 #define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ 1914 #define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 1915 #define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 1916 #define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 1917 #define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */ 1918 1919 /* Bit 1 : Write '1' to enable interrupt for event RXPTRUPD */ 1920 #define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ 1921 #define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ 1922 #define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ 1923 #define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ 1924 #define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */ 1925 1926 /* Register: I2S_INTENCLR */ 1927 /* Description: Disable interrupt */ 1928 1929 /* Bit 5 : Write '1' to disable interrupt for event TXPTRUPD */ 1930 #define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ 1931 #define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ 1932 #define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ 1933 #define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ 1934 #define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */ 1935 1936 /* Bit 2 : Write '1' to disable interrupt for event STOPPED */ 1937 #define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ 1938 #define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 1939 #define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 1940 #define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 1941 #define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ 1942 1943 /* Bit 1 : Write '1' to disable interrupt for event RXPTRUPD */ 1944 #define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ 1945 #define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ 1946 #define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ 1947 #define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ 1948 #define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */ 1949 1950 /* Register: I2S_ENABLE */ 1951 /* Description: Enable I2S module. */ 1952 1953 /* Bit 0 : Enable I2S module. */ 1954 #define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 1955 #define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 1956 #define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ 1957 #define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ 1958 1959 /* Register: I2S_CONFIG_MODE */ 1960 /* Description: I2S mode. */ 1961 1962 /* Bit 0 : I2S mode. */ 1963 #define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ 1964 #define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ 1965 #define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */ 1966 #define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */ 1967 1968 /* Register: I2S_CONFIG_RXEN */ 1969 /* Description: Reception (RX) enable. */ 1970 1971 /* Bit 0 : Reception (RX) enable. */ 1972 #define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */ 1973 #define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */ 1974 #define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */ 1975 #define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */ 1976 1977 /* Register: I2S_CONFIG_TXEN */ 1978 /* Description: Transmission (TX) enable. */ 1979 1980 /* Bit 0 : Transmission (TX) enable. */ 1981 #define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */ 1982 #define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */ 1983 #define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */ 1984 #define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */ 1985 1986 /* Register: I2S_CONFIG_MCKEN */ 1987 /* Description: Master clock generator enable. */ 1988 1989 /* Bit 0 : Master clock generator enable. */ 1990 #define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */ 1991 #define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */ 1992 #define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */ 1993 #define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */ 1994 1995 /* Register: I2S_CONFIG_MCKFREQ */ 1996 /* Description: Master clock generator frequency. */ 1997 1998 /* Bits 31..0 : Master clock generator frequency. */ 1999 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */ 2000 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */ 2001 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */ 2002 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */ 2003 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */ 2004 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */ 2005 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */ 2006 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */ 2007 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */ 2008 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */ 2009 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */ 2010 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */ 2011 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */ 2012 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */ 2013 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */ 2014 2015 /* Register: I2S_CONFIG_RATIO */ 2016 /* Description: MCK / LRCK ratio. */ 2017 2018 /* Bits 3..0 : MCK / LRCK ratio. */ 2019 #define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */ 2020 #define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */ 2021 #define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */ 2022 #define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */ 2023 #define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */ 2024 #define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */ 2025 #define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */ 2026 #define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */ 2027 #define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */ 2028 #define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */ 2029 #define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */ 2030 2031 /* Register: I2S_CONFIG_SWIDTH */ 2032 /* Description: Sample width. */ 2033 2034 /* Bits 1..0 : Sample width. */ 2035 #define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */ 2036 #define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */ 2037 #define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */ 2038 #define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */ 2039 #define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */ 2040 2041 /* Register: I2S_CONFIG_ALIGN */ 2042 /* Description: Alignment of sample within a frame. */ 2043 2044 /* Bit 0 : Alignment of sample within a frame. */ 2045 #define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */ 2046 #define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */ 2047 #define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */ 2048 #define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */ 2049 2050 /* Register: I2S_CONFIG_FORMAT */ 2051 /* Description: Frame format. */ 2052 2053 /* Bit 0 : Frame format. */ 2054 #define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */ 2055 #define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */ 2056 #define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */ 2057 #define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */ 2058 2059 /* Register: I2S_CONFIG_CHANNELS */ 2060 /* Description: Enable channels. */ 2061 2062 /* Bits 1..0 : Enable channels. */ 2063 #define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */ 2064 #define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */ 2065 #define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */ 2066 #define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */ 2067 #define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */ 2068 2069 /* Register: I2S_RXD_PTR */ 2070 /* Description: Receive buffer RAM start address. */ 2071 2072 /* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */ 2073 #define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 2074 #define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 2075 2076 /* Register: I2S_TXD_PTR */ 2077 /* Description: Transmit buffer RAM start address. */ 2078 2079 /* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */ 2080 #define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 2081 #define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 2082 2083 /* Register: I2S_RXTXD_MAXCNT */ 2084 /* Description: Size of RXD and TXD buffers. */ 2085 2086 /* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */ 2087 #define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 2088 #define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 2089 2090 /* Register: I2S_PSEL_MCK */ 2091 /* Description: Pin select for MCK signal. */ 2092 2093 /* Bit 31 : Connection */ 2094 #define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 2095 #define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 2096 #define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */ 2097 #define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ 2098 2099 /* Bits 4..0 : Pin number */ 2100 #define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */ 2101 #define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */ 2102 2103 /* Register: I2S_PSEL_SCK */ 2104 /* Description: Pin select for SCK signal. */ 2105 2106 /* Bit 31 : Connection */ 2107 #define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 2108 #define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 2109 #define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ 2110 #define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ 2111 2112 /* Bits 4..0 : Pin number */ 2113 #define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ 2114 #define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ 2115 2116 /* Register: I2S_PSEL_LRCK */ 2117 /* Description: Pin select for LRCK signal. */ 2118 2119 /* Bit 31 : Connection */ 2120 #define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 2121 #define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 2122 #define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */ 2123 #define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ 2124 2125 /* Bits 4..0 : Pin number */ 2126 #define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */ 2127 #define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */ 2128 2129 /* Register: I2S_PSEL_SDIN */ 2130 /* Description: Pin select for SDIN signal. */ 2131 2132 /* Bit 31 : Connection */ 2133 #define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 2134 #define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 2135 #define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */ 2136 #define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */ 2137 2138 /* Bits 4..0 : Pin number */ 2139 #define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */ 2140 #define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */ 2141 2142 /* Register: I2S_PSEL_SDOUT */ 2143 /* Description: Pin select for SDOUT signal. */ 2144 2145 /* Bit 31 : Connection */ 2146 #define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 2147 #define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 2148 #define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */ 2149 #define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */ 2150 2151 /* Bits 4..0 : Pin number */ 2152 #define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */ 2153 #define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */ 2154 2155 2156 /* Peripheral: IPC */ 2157 /* Description: Interprocessor communication 0 */ 2158 2159 /* Register: IPC_TASKS_SEND */ 2160 /* Description: Description collection: Trigger events on IPC channel enabled in SEND_CNF[n] */ 2161 2162 /* Bit 0 : Trigger events on IPC channel enabled in SEND_CNF[n] */ 2163 #define IPC_TASKS_SEND_TASKS_SEND_Pos (0UL) /*!< Position of TASKS_SEND field. */ 2164 #define IPC_TASKS_SEND_TASKS_SEND_Msk (0x1UL << IPC_TASKS_SEND_TASKS_SEND_Pos) /*!< Bit mask of TASKS_SEND field. */ 2165 #define IPC_TASKS_SEND_TASKS_SEND_Trigger (1UL) /*!< Trigger task */ 2166 2167 /* Register: IPC_SUBSCRIBE_SEND */ 2168 /* Description: Description collection: Subscribe configuration for task SEND[n] */ 2169 2170 /* Bit 31 : */ 2171 #define IPC_SUBSCRIBE_SEND_EN_Pos (31UL) /*!< Position of EN field. */ 2172 #define IPC_SUBSCRIBE_SEND_EN_Msk (0x1UL << IPC_SUBSCRIBE_SEND_EN_Pos) /*!< Bit mask of EN field. */ 2173 #define IPC_SUBSCRIBE_SEND_EN_Disabled (0UL) /*!< Disable subscription */ 2174 #define IPC_SUBSCRIBE_SEND_EN_Enabled (1UL) /*!< Enable subscription */ 2175 2176 /* Bits 7..0 : DPPI channel that task SEND[n] will subscribe to */ 2177 #define IPC_SUBSCRIBE_SEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2178 #define IPC_SUBSCRIBE_SEND_CHIDX_Msk (0xFFUL << IPC_SUBSCRIBE_SEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2179 2180 /* Register: IPC_EVENTS_RECEIVE */ 2181 /* Description: Description collection: Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] */ 2182 2183 /* Bit 0 : Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] */ 2184 #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos (0UL) /*!< Position of EVENTS_RECEIVE field. */ 2185 #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Msk (0x1UL << IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos) /*!< Bit mask of EVENTS_RECEIVE field. */ 2186 #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_NotGenerated (0UL) /*!< Event not generated */ 2187 #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Generated (1UL) /*!< Event generated */ 2188 2189 /* Register: IPC_PUBLISH_RECEIVE */ 2190 /* Description: Description collection: Publish configuration for event RECEIVE[n] */ 2191 2192 /* Bit 31 : */ 2193 #define IPC_PUBLISH_RECEIVE_EN_Pos (31UL) /*!< Position of EN field. */ 2194 #define IPC_PUBLISH_RECEIVE_EN_Msk (0x1UL << IPC_PUBLISH_RECEIVE_EN_Pos) /*!< Bit mask of EN field. */ 2195 #define IPC_PUBLISH_RECEIVE_EN_Disabled (0UL) /*!< Disable publishing */ 2196 #define IPC_PUBLISH_RECEIVE_EN_Enabled (1UL) /*!< Enable publishing */ 2197 2198 /* Bits 7..0 : DPPI channel that event RECEIVE[n] will publish to */ 2199 #define IPC_PUBLISH_RECEIVE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2200 #define IPC_PUBLISH_RECEIVE_CHIDX_Msk (0xFFUL << IPC_PUBLISH_RECEIVE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2201 2202 /* Register: IPC_INTEN */ 2203 /* Description: Enable or disable interrupt */ 2204 2205 /* Bit 7 : Enable or disable interrupt for event RECEIVE[7] */ 2206 #define IPC_INTEN_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ 2207 #define IPC_INTEN_RECEIVE7_Msk (0x1UL << IPC_INTEN_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ 2208 #define IPC_INTEN_RECEIVE7_Disabled (0UL) /*!< Disable */ 2209 #define IPC_INTEN_RECEIVE7_Enabled (1UL) /*!< Enable */ 2210 2211 /* Bit 6 : Enable or disable interrupt for event RECEIVE[6] */ 2212 #define IPC_INTEN_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ 2213 #define IPC_INTEN_RECEIVE6_Msk (0x1UL << IPC_INTEN_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ 2214 #define IPC_INTEN_RECEIVE6_Disabled (0UL) /*!< Disable */ 2215 #define IPC_INTEN_RECEIVE6_Enabled (1UL) /*!< Enable */ 2216 2217 /* Bit 5 : Enable or disable interrupt for event RECEIVE[5] */ 2218 #define IPC_INTEN_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ 2219 #define IPC_INTEN_RECEIVE5_Msk (0x1UL << IPC_INTEN_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ 2220 #define IPC_INTEN_RECEIVE5_Disabled (0UL) /*!< Disable */ 2221 #define IPC_INTEN_RECEIVE5_Enabled (1UL) /*!< Enable */ 2222 2223 /* Bit 4 : Enable or disable interrupt for event RECEIVE[4] */ 2224 #define IPC_INTEN_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ 2225 #define IPC_INTEN_RECEIVE4_Msk (0x1UL << IPC_INTEN_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ 2226 #define IPC_INTEN_RECEIVE4_Disabled (0UL) /*!< Disable */ 2227 #define IPC_INTEN_RECEIVE4_Enabled (1UL) /*!< Enable */ 2228 2229 /* Bit 3 : Enable or disable interrupt for event RECEIVE[3] */ 2230 #define IPC_INTEN_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ 2231 #define IPC_INTEN_RECEIVE3_Msk (0x1UL << IPC_INTEN_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ 2232 #define IPC_INTEN_RECEIVE3_Disabled (0UL) /*!< Disable */ 2233 #define IPC_INTEN_RECEIVE3_Enabled (1UL) /*!< Enable */ 2234 2235 /* Bit 2 : Enable or disable interrupt for event RECEIVE[2] */ 2236 #define IPC_INTEN_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ 2237 #define IPC_INTEN_RECEIVE2_Msk (0x1UL << IPC_INTEN_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ 2238 #define IPC_INTEN_RECEIVE2_Disabled (0UL) /*!< Disable */ 2239 #define IPC_INTEN_RECEIVE2_Enabled (1UL) /*!< Enable */ 2240 2241 /* Bit 1 : Enable or disable interrupt for event RECEIVE[1] */ 2242 #define IPC_INTEN_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ 2243 #define IPC_INTEN_RECEIVE1_Msk (0x1UL << IPC_INTEN_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ 2244 #define IPC_INTEN_RECEIVE1_Disabled (0UL) /*!< Disable */ 2245 #define IPC_INTEN_RECEIVE1_Enabled (1UL) /*!< Enable */ 2246 2247 /* Bit 0 : Enable or disable interrupt for event RECEIVE[0] */ 2248 #define IPC_INTEN_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ 2249 #define IPC_INTEN_RECEIVE0_Msk (0x1UL << IPC_INTEN_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ 2250 #define IPC_INTEN_RECEIVE0_Disabled (0UL) /*!< Disable */ 2251 #define IPC_INTEN_RECEIVE0_Enabled (1UL) /*!< Enable */ 2252 2253 /* Register: IPC_INTENSET */ 2254 /* Description: Enable interrupt */ 2255 2256 /* Bit 7 : Write '1' to enable interrupt for event RECEIVE[7] */ 2257 #define IPC_INTENSET_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ 2258 #define IPC_INTENSET_RECEIVE7_Msk (0x1UL << IPC_INTENSET_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ 2259 #define IPC_INTENSET_RECEIVE7_Disabled (0UL) /*!< Read: Disabled */ 2260 #define IPC_INTENSET_RECEIVE7_Enabled (1UL) /*!< Read: Enabled */ 2261 #define IPC_INTENSET_RECEIVE7_Set (1UL) /*!< Enable */ 2262 2263 /* Bit 6 : Write '1' to enable interrupt for event RECEIVE[6] */ 2264 #define IPC_INTENSET_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ 2265 #define IPC_INTENSET_RECEIVE6_Msk (0x1UL << IPC_INTENSET_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ 2266 #define IPC_INTENSET_RECEIVE6_Disabled (0UL) /*!< Read: Disabled */ 2267 #define IPC_INTENSET_RECEIVE6_Enabled (1UL) /*!< Read: Enabled */ 2268 #define IPC_INTENSET_RECEIVE6_Set (1UL) /*!< Enable */ 2269 2270 /* Bit 5 : Write '1' to enable interrupt for event RECEIVE[5] */ 2271 #define IPC_INTENSET_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ 2272 #define IPC_INTENSET_RECEIVE5_Msk (0x1UL << IPC_INTENSET_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ 2273 #define IPC_INTENSET_RECEIVE5_Disabled (0UL) /*!< Read: Disabled */ 2274 #define IPC_INTENSET_RECEIVE5_Enabled (1UL) /*!< Read: Enabled */ 2275 #define IPC_INTENSET_RECEIVE5_Set (1UL) /*!< Enable */ 2276 2277 /* Bit 4 : Write '1' to enable interrupt for event RECEIVE[4] */ 2278 #define IPC_INTENSET_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ 2279 #define IPC_INTENSET_RECEIVE4_Msk (0x1UL << IPC_INTENSET_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ 2280 #define IPC_INTENSET_RECEIVE4_Disabled (0UL) /*!< Read: Disabled */ 2281 #define IPC_INTENSET_RECEIVE4_Enabled (1UL) /*!< Read: Enabled */ 2282 #define IPC_INTENSET_RECEIVE4_Set (1UL) /*!< Enable */ 2283 2284 /* Bit 3 : Write '1' to enable interrupt for event RECEIVE[3] */ 2285 #define IPC_INTENSET_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ 2286 #define IPC_INTENSET_RECEIVE3_Msk (0x1UL << IPC_INTENSET_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ 2287 #define IPC_INTENSET_RECEIVE3_Disabled (0UL) /*!< Read: Disabled */ 2288 #define IPC_INTENSET_RECEIVE3_Enabled (1UL) /*!< Read: Enabled */ 2289 #define IPC_INTENSET_RECEIVE3_Set (1UL) /*!< Enable */ 2290 2291 /* Bit 2 : Write '1' to enable interrupt for event RECEIVE[2] */ 2292 #define IPC_INTENSET_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ 2293 #define IPC_INTENSET_RECEIVE2_Msk (0x1UL << IPC_INTENSET_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ 2294 #define IPC_INTENSET_RECEIVE2_Disabled (0UL) /*!< Read: Disabled */ 2295 #define IPC_INTENSET_RECEIVE2_Enabled (1UL) /*!< Read: Enabled */ 2296 #define IPC_INTENSET_RECEIVE2_Set (1UL) /*!< Enable */ 2297 2298 /* Bit 1 : Write '1' to enable interrupt for event RECEIVE[1] */ 2299 #define IPC_INTENSET_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ 2300 #define IPC_INTENSET_RECEIVE1_Msk (0x1UL << IPC_INTENSET_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ 2301 #define IPC_INTENSET_RECEIVE1_Disabled (0UL) /*!< Read: Disabled */ 2302 #define IPC_INTENSET_RECEIVE1_Enabled (1UL) /*!< Read: Enabled */ 2303 #define IPC_INTENSET_RECEIVE1_Set (1UL) /*!< Enable */ 2304 2305 /* Bit 0 : Write '1' to enable interrupt for event RECEIVE[0] */ 2306 #define IPC_INTENSET_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ 2307 #define IPC_INTENSET_RECEIVE0_Msk (0x1UL << IPC_INTENSET_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ 2308 #define IPC_INTENSET_RECEIVE0_Disabled (0UL) /*!< Read: Disabled */ 2309 #define IPC_INTENSET_RECEIVE0_Enabled (1UL) /*!< Read: Enabled */ 2310 #define IPC_INTENSET_RECEIVE0_Set (1UL) /*!< Enable */ 2311 2312 /* Register: IPC_INTENCLR */ 2313 /* Description: Disable interrupt */ 2314 2315 /* Bit 7 : Write '1' to disable interrupt for event RECEIVE[7] */ 2316 #define IPC_INTENCLR_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ 2317 #define IPC_INTENCLR_RECEIVE7_Msk (0x1UL << IPC_INTENCLR_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ 2318 #define IPC_INTENCLR_RECEIVE7_Disabled (0UL) /*!< Read: Disabled */ 2319 #define IPC_INTENCLR_RECEIVE7_Enabled (1UL) /*!< Read: Enabled */ 2320 #define IPC_INTENCLR_RECEIVE7_Clear (1UL) /*!< Disable */ 2321 2322 /* Bit 6 : Write '1' to disable interrupt for event RECEIVE[6] */ 2323 #define IPC_INTENCLR_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ 2324 #define IPC_INTENCLR_RECEIVE6_Msk (0x1UL << IPC_INTENCLR_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ 2325 #define IPC_INTENCLR_RECEIVE6_Disabled (0UL) /*!< Read: Disabled */ 2326 #define IPC_INTENCLR_RECEIVE6_Enabled (1UL) /*!< Read: Enabled */ 2327 #define IPC_INTENCLR_RECEIVE6_Clear (1UL) /*!< Disable */ 2328 2329 /* Bit 5 : Write '1' to disable interrupt for event RECEIVE[5] */ 2330 #define IPC_INTENCLR_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ 2331 #define IPC_INTENCLR_RECEIVE5_Msk (0x1UL << IPC_INTENCLR_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ 2332 #define IPC_INTENCLR_RECEIVE5_Disabled (0UL) /*!< Read: Disabled */ 2333 #define IPC_INTENCLR_RECEIVE5_Enabled (1UL) /*!< Read: Enabled */ 2334 #define IPC_INTENCLR_RECEIVE5_Clear (1UL) /*!< Disable */ 2335 2336 /* Bit 4 : Write '1' to disable interrupt for event RECEIVE[4] */ 2337 #define IPC_INTENCLR_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ 2338 #define IPC_INTENCLR_RECEIVE4_Msk (0x1UL << IPC_INTENCLR_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ 2339 #define IPC_INTENCLR_RECEIVE4_Disabled (0UL) /*!< Read: Disabled */ 2340 #define IPC_INTENCLR_RECEIVE4_Enabled (1UL) /*!< Read: Enabled */ 2341 #define IPC_INTENCLR_RECEIVE4_Clear (1UL) /*!< Disable */ 2342 2343 /* Bit 3 : Write '1' to disable interrupt for event RECEIVE[3] */ 2344 #define IPC_INTENCLR_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ 2345 #define IPC_INTENCLR_RECEIVE3_Msk (0x1UL << IPC_INTENCLR_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ 2346 #define IPC_INTENCLR_RECEIVE3_Disabled (0UL) /*!< Read: Disabled */ 2347 #define IPC_INTENCLR_RECEIVE3_Enabled (1UL) /*!< Read: Enabled */ 2348 #define IPC_INTENCLR_RECEIVE3_Clear (1UL) /*!< Disable */ 2349 2350 /* Bit 2 : Write '1' to disable interrupt for event RECEIVE[2] */ 2351 #define IPC_INTENCLR_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ 2352 #define IPC_INTENCLR_RECEIVE2_Msk (0x1UL << IPC_INTENCLR_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ 2353 #define IPC_INTENCLR_RECEIVE2_Disabled (0UL) /*!< Read: Disabled */ 2354 #define IPC_INTENCLR_RECEIVE2_Enabled (1UL) /*!< Read: Enabled */ 2355 #define IPC_INTENCLR_RECEIVE2_Clear (1UL) /*!< Disable */ 2356 2357 /* Bit 1 : Write '1' to disable interrupt for event RECEIVE[1] */ 2358 #define IPC_INTENCLR_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ 2359 #define IPC_INTENCLR_RECEIVE1_Msk (0x1UL << IPC_INTENCLR_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ 2360 #define IPC_INTENCLR_RECEIVE1_Disabled (0UL) /*!< Read: Disabled */ 2361 #define IPC_INTENCLR_RECEIVE1_Enabled (1UL) /*!< Read: Enabled */ 2362 #define IPC_INTENCLR_RECEIVE1_Clear (1UL) /*!< Disable */ 2363 2364 /* Bit 0 : Write '1' to disable interrupt for event RECEIVE[0] */ 2365 #define IPC_INTENCLR_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ 2366 #define IPC_INTENCLR_RECEIVE0_Msk (0x1UL << IPC_INTENCLR_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ 2367 #define IPC_INTENCLR_RECEIVE0_Disabled (0UL) /*!< Read: Disabled */ 2368 #define IPC_INTENCLR_RECEIVE0_Enabled (1UL) /*!< Read: Enabled */ 2369 #define IPC_INTENCLR_RECEIVE0_Clear (1UL) /*!< Disable */ 2370 2371 /* Register: IPC_INTPEND */ 2372 /* Description: Pending interrupts */ 2373 2374 /* Bit 7 : Read pending status of interrupt for event RECEIVE[7] */ 2375 #define IPC_INTPEND_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ 2376 #define IPC_INTPEND_RECEIVE7_Msk (0x1UL << IPC_INTPEND_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ 2377 #define IPC_INTPEND_RECEIVE7_NotPending (0UL) /*!< Read: Not pending */ 2378 #define IPC_INTPEND_RECEIVE7_Pending (1UL) /*!< Read: Pending */ 2379 2380 /* Bit 6 : Read pending status of interrupt for event RECEIVE[6] */ 2381 #define IPC_INTPEND_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ 2382 #define IPC_INTPEND_RECEIVE6_Msk (0x1UL << IPC_INTPEND_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ 2383 #define IPC_INTPEND_RECEIVE6_NotPending (0UL) /*!< Read: Not pending */ 2384 #define IPC_INTPEND_RECEIVE6_Pending (1UL) /*!< Read: Pending */ 2385 2386 /* Bit 5 : Read pending status of interrupt for event RECEIVE[5] */ 2387 #define IPC_INTPEND_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ 2388 #define IPC_INTPEND_RECEIVE5_Msk (0x1UL << IPC_INTPEND_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ 2389 #define IPC_INTPEND_RECEIVE5_NotPending (0UL) /*!< Read: Not pending */ 2390 #define IPC_INTPEND_RECEIVE5_Pending (1UL) /*!< Read: Pending */ 2391 2392 /* Bit 4 : Read pending status of interrupt for event RECEIVE[4] */ 2393 #define IPC_INTPEND_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ 2394 #define IPC_INTPEND_RECEIVE4_Msk (0x1UL << IPC_INTPEND_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ 2395 #define IPC_INTPEND_RECEIVE4_NotPending (0UL) /*!< Read: Not pending */ 2396 #define IPC_INTPEND_RECEIVE4_Pending (1UL) /*!< Read: Pending */ 2397 2398 /* Bit 3 : Read pending status of interrupt for event RECEIVE[3] */ 2399 #define IPC_INTPEND_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ 2400 #define IPC_INTPEND_RECEIVE3_Msk (0x1UL << IPC_INTPEND_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ 2401 #define IPC_INTPEND_RECEIVE3_NotPending (0UL) /*!< Read: Not pending */ 2402 #define IPC_INTPEND_RECEIVE3_Pending (1UL) /*!< Read: Pending */ 2403 2404 /* Bit 2 : Read pending status of interrupt for event RECEIVE[2] */ 2405 #define IPC_INTPEND_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ 2406 #define IPC_INTPEND_RECEIVE2_Msk (0x1UL << IPC_INTPEND_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ 2407 #define IPC_INTPEND_RECEIVE2_NotPending (0UL) /*!< Read: Not pending */ 2408 #define IPC_INTPEND_RECEIVE2_Pending (1UL) /*!< Read: Pending */ 2409 2410 /* Bit 1 : Read pending status of interrupt for event RECEIVE[1] */ 2411 #define IPC_INTPEND_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ 2412 #define IPC_INTPEND_RECEIVE1_Msk (0x1UL << IPC_INTPEND_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ 2413 #define IPC_INTPEND_RECEIVE1_NotPending (0UL) /*!< Read: Not pending */ 2414 #define IPC_INTPEND_RECEIVE1_Pending (1UL) /*!< Read: Pending */ 2415 2416 /* Bit 0 : Read pending status of interrupt for event RECEIVE[0] */ 2417 #define IPC_INTPEND_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ 2418 #define IPC_INTPEND_RECEIVE0_Msk (0x1UL << IPC_INTPEND_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ 2419 #define IPC_INTPEND_RECEIVE0_NotPending (0UL) /*!< Read: Not pending */ 2420 #define IPC_INTPEND_RECEIVE0_Pending (1UL) /*!< Read: Pending */ 2421 2422 /* Register: IPC_SEND_CNF */ 2423 /* Description: Description collection: Send event configuration for TASKS_SEND[n] */ 2424 2425 /* Bit 7 : Enable broadcasting on IPC channel 7 */ 2426 #define IPC_SEND_CNF_CHEN7_Pos (7UL) /*!< Position of CHEN7 field. */ 2427 #define IPC_SEND_CNF_CHEN7_Msk (0x1UL << IPC_SEND_CNF_CHEN7_Pos) /*!< Bit mask of CHEN7 field. */ 2428 #define IPC_SEND_CNF_CHEN7_Disable (0UL) /*!< Disable broadcast */ 2429 #define IPC_SEND_CNF_CHEN7_Enable (1UL) /*!< Enable broadcast */ 2430 2431 /* Bit 6 : Enable broadcasting on IPC channel 6 */ 2432 #define IPC_SEND_CNF_CHEN6_Pos (6UL) /*!< Position of CHEN6 field. */ 2433 #define IPC_SEND_CNF_CHEN6_Msk (0x1UL << IPC_SEND_CNF_CHEN6_Pos) /*!< Bit mask of CHEN6 field. */ 2434 #define IPC_SEND_CNF_CHEN6_Disable (0UL) /*!< Disable broadcast */ 2435 #define IPC_SEND_CNF_CHEN6_Enable (1UL) /*!< Enable broadcast */ 2436 2437 /* Bit 5 : Enable broadcasting on IPC channel 5 */ 2438 #define IPC_SEND_CNF_CHEN5_Pos (5UL) /*!< Position of CHEN5 field. */ 2439 #define IPC_SEND_CNF_CHEN5_Msk (0x1UL << IPC_SEND_CNF_CHEN5_Pos) /*!< Bit mask of CHEN5 field. */ 2440 #define IPC_SEND_CNF_CHEN5_Disable (0UL) /*!< Disable broadcast */ 2441 #define IPC_SEND_CNF_CHEN5_Enable (1UL) /*!< Enable broadcast */ 2442 2443 /* Bit 4 : Enable broadcasting on IPC channel 4 */ 2444 #define IPC_SEND_CNF_CHEN4_Pos (4UL) /*!< Position of CHEN4 field. */ 2445 #define IPC_SEND_CNF_CHEN4_Msk (0x1UL << IPC_SEND_CNF_CHEN4_Pos) /*!< Bit mask of CHEN4 field. */ 2446 #define IPC_SEND_CNF_CHEN4_Disable (0UL) /*!< Disable broadcast */ 2447 #define IPC_SEND_CNF_CHEN4_Enable (1UL) /*!< Enable broadcast */ 2448 2449 /* Bit 3 : Enable broadcasting on IPC channel 3 */ 2450 #define IPC_SEND_CNF_CHEN3_Pos (3UL) /*!< Position of CHEN3 field. */ 2451 #define IPC_SEND_CNF_CHEN3_Msk (0x1UL << IPC_SEND_CNF_CHEN3_Pos) /*!< Bit mask of CHEN3 field. */ 2452 #define IPC_SEND_CNF_CHEN3_Disable (0UL) /*!< Disable broadcast */ 2453 #define IPC_SEND_CNF_CHEN3_Enable (1UL) /*!< Enable broadcast */ 2454 2455 /* Bit 2 : Enable broadcasting on IPC channel 2 */ 2456 #define IPC_SEND_CNF_CHEN2_Pos (2UL) /*!< Position of CHEN2 field. */ 2457 #define IPC_SEND_CNF_CHEN2_Msk (0x1UL << IPC_SEND_CNF_CHEN2_Pos) /*!< Bit mask of CHEN2 field. */ 2458 #define IPC_SEND_CNF_CHEN2_Disable (0UL) /*!< Disable broadcast */ 2459 #define IPC_SEND_CNF_CHEN2_Enable (1UL) /*!< Enable broadcast */ 2460 2461 /* Bit 1 : Enable broadcasting on IPC channel 1 */ 2462 #define IPC_SEND_CNF_CHEN1_Pos (1UL) /*!< Position of CHEN1 field. */ 2463 #define IPC_SEND_CNF_CHEN1_Msk (0x1UL << IPC_SEND_CNF_CHEN1_Pos) /*!< Bit mask of CHEN1 field. */ 2464 #define IPC_SEND_CNF_CHEN1_Disable (0UL) /*!< Disable broadcast */ 2465 #define IPC_SEND_CNF_CHEN1_Enable (1UL) /*!< Enable broadcast */ 2466 2467 /* Bit 0 : Enable broadcasting on IPC channel 0 */ 2468 #define IPC_SEND_CNF_CHEN0_Pos (0UL) /*!< Position of CHEN0 field. */ 2469 #define IPC_SEND_CNF_CHEN0_Msk (0x1UL << IPC_SEND_CNF_CHEN0_Pos) /*!< Bit mask of CHEN0 field. */ 2470 #define IPC_SEND_CNF_CHEN0_Disable (0UL) /*!< Disable broadcast */ 2471 #define IPC_SEND_CNF_CHEN0_Enable (1UL) /*!< Enable broadcast */ 2472 2473 /* Register: IPC_RECEIVE_CNF */ 2474 /* Description: Description collection: Receive event configuration for EVENTS_RECEIVE[n] */ 2475 2476 /* Bit 7 : Enable subscription to IPC channel 7 */ 2477 #define IPC_RECEIVE_CNF_CHEN7_Pos (7UL) /*!< Position of CHEN7 field. */ 2478 #define IPC_RECEIVE_CNF_CHEN7_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN7_Pos) /*!< Bit mask of CHEN7 field. */ 2479 #define IPC_RECEIVE_CNF_CHEN7_Disable (0UL) /*!< Disable events */ 2480 #define IPC_RECEIVE_CNF_CHEN7_Enable (1UL) /*!< Enable events */ 2481 2482 /* Bit 6 : Enable subscription to IPC channel 6 */ 2483 #define IPC_RECEIVE_CNF_CHEN6_Pos (6UL) /*!< Position of CHEN6 field. */ 2484 #define IPC_RECEIVE_CNF_CHEN6_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN6_Pos) /*!< Bit mask of CHEN6 field. */ 2485 #define IPC_RECEIVE_CNF_CHEN6_Disable (0UL) /*!< Disable events */ 2486 #define IPC_RECEIVE_CNF_CHEN6_Enable (1UL) /*!< Enable events */ 2487 2488 /* Bit 5 : Enable subscription to IPC channel 5 */ 2489 #define IPC_RECEIVE_CNF_CHEN5_Pos (5UL) /*!< Position of CHEN5 field. */ 2490 #define IPC_RECEIVE_CNF_CHEN5_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN5_Pos) /*!< Bit mask of CHEN5 field. */ 2491 #define IPC_RECEIVE_CNF_CHEN5_Disable (0UL) /*!< Disable events */ 2492 #define IPC_RECEIVE_CNF_CHEN5_Enable (1UL) /*!< Enable events */ 2493 2494 /* Bit 4 : Enable subscription to IPC channel 4 */ 2495 #define IPC_RECEIVE_CNF_CHEN4_Pos (4UL) /*!< Position of CHEN4 field. */ 2496 #define IPC_RECEIVE_CNF_CHEN4_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN4_Pos) /*!< Bit mask of CHEN4 field. */ 2497 #define IPC_RECEIVE_CNF_CHEN4_Disable (0UL) /*!< Disable events */ 2498 #define IPC_RECEIVE_CNF_CHEN4_Enable (1UL) /*!< Enable events */ 2499 2500 /* Bit 3 : Enable subscription to IPC channel 3 */ 2501 #define IPC_RECEIVE_CNF_CHEN3_Pos (3UL) /*!< Position of CHEN3 field. */ 2502 #define IPC_RECEIVE_CNF_CHEN3_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN3_Pos) /*!< Bit mask of CHEN3 field. */ 2503 #define IPC_RECEIVE_CNF_CHEN3_Disable (0UL) /*!< Disable events */ 2504 #define IPC_RECEIVE_CNF_CHEN3_Enable (1UL) /*!< Enable events */ 2505 2506 /* Bit 2 : Enable subscription to IPC channel 2 */ 2507 #define IPC_RECEIVE_CNF_CHEN2_Pos (2UL) /*!< Position of CHEN2 field. */ 2508 #define IPC_RECEIVE_CNF_CHEN2_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN2_Pos) /*!< Bit mask of CHEN2 field. */ 2509 #define IPC_RECEIVE_CNF_CHEN2_Disable (0UL) /*!< Disable events */ 2510 #define IPC_RECEIVE_CNF_CHEN2_Enable (1UL) /*!< Enable events */ 2511 2512 /* Bit 1 : Enable subscription to IPC channel 1 */ 2513 #define IPC_RECEIVE_CNF_CHEN1_Pos (1UL) /*!< Position of CHEN1 field. */ 2514 #define IPC_RECEIVE_CNF_CHEN1_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN1_Pos) /*!< Bit mask of CHEN1 field. */ 2515 #define IPC_RECEIVE_CNF_CHEN1_Disable (0UL) /*!< Disable events */ 2516 #define IPC_RECEIVE_CNF_CHEN1_Enable (1UL) /*!< Enable events */ 2517 2518 /* Bit 0 : Enable subscription to IPC channel 0 */ 2519 #define IPC_RECEIVE_CNF_CHEN0_Pos (0UL) /*!< Position of CHEN0 field. */ 2520 #define IPC_RECEIVE_CNF_CHEN0_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN0_Pos) /*!< Bit mask of CHEN0 field. */ 2521 #define IPC_RECEIVE_CNF_CHEN0_Disable (0UL) /*!< Disable events */ 2522 #define IPC_RECEIVE_CNF_CHEN0_Enable (1UL) /*!< Enable events */ 2523 2524 /* Register: IPC_GPMEM */ 2525 /* Description: Description collection: General purpose memory */ 2526 2527 /* Bits 31..0 : General purpose memory */ 2528 #define IPC_GPMEM_GPMEM_Pos (0UL) /*!< Position of GPMEM field. */ 2529 #define IPC_GPMEM_GPMEM_Msk (0xFFFFFFFFUL << IPC_GPMEM_GPMEM_Pos) /*!< Bit mask of GPMEM field. */ 2530 2531 2532 /* Peripheral: KMU */ 2533 /* Description: Key management unit 0 */ 2534 2535 /* Register: KMU_TASKS_PUSH_KEYSLOT */ 2536 /* Description: Push a key slot over secure APB */ 2537 2538 /* Bit 0 : Push a key slot over secure APB */ 2539 #define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Pos (0UL) /*!< Position of TASKS_PUSH_KEYSLOT field. */ 2540 #define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Msk (0x1UL << KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Pos) /*!< Bit mask of TASKS_PUSH_KEYSLOT field. */ 2541 #define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Trigger (1UL) /*!< Trigger task */ 2542 2543 /* Register: KMU_EVENTS_KEYSLOT_PUSHED */ 2544 /* Description: Key slot successfully pushed over secure APB */ 2545 2546 /* Bit 0 : Key slot successfully pushed over secure APB */ 2547 #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_PUSHED field. */ 2548 #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Msk (0x1UL << KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Pos) /*!< Bit mask of EVENTS_KEYSLOT_PUSHED field. */ 2549 #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_NotGenerated (0UL) /*!< Event not generated */ 2550 #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Generated (1UL) /*!< Event generated */ 2551 2552 /* Register: KMU_EVENTS_KEYSLOT_REVOKED */ 2553 /* Description: Key slot has been revoked and cannot be tasked for selection */ 2554 2555 /* Bit 0 : Key slot has been revoked and cannot be tasked for selection */ 2556 #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_REVOKED field. */ 2557 #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Msk (0x1UL << KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Pos) /*!< Bit mask of EVENTS_KEYSLOT_REVOKED field. */ 2558 #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_NotGenerated (0UL) /*!< Event not generated */ 2559 #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Generated (1UL) /*!< Event generated */ 2560 2561 /* Register: KMU_EVENTS_KEYSLOT_ERROR */ 2562 /* Description: No key slot selected, no destination address defined, or error during push operation */ 2563 2564 /* Bit 0 : No key slot selected, no destination address defined, or error during push operation */ 2565 #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_ERROR field. */ 2566 #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Msk (0x1UL << KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Pos) /*!< Bit mask of EVENTS_KEYSLOT_ERROR field. */ 2567 #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_NotGenerated (0UL) /*!< Event not generated */ 2568 #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Generated (1UL) /*!< Event generated */ 2569 2570 /* Register: KMU_INTEN */ 2571 /* Description: Enable or disable interrupt */ 2572 2573 /* Bit 2 : Enable or disable interrupt for event KEYSLOT_ERROR */ 2574 #define KMU_INTEN_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */ 2575 #define KMU_INTEN_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTEN_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */ 2576 #define KMU_INTEN_KEYSLOT_ERROR_Disabled (0UL) /*!< Disable */ 2577 #define KMU_INTEN_KEYSLOT_ERROR_Enabled (1UL) /*!< Enable */ 2578 2579 /* Bit 1 : Enable or disable interrupt for event KEYSLOT_REVOKED */ 2580 #define KMU_INTEN_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */ 2581 #define KMU_INTEN_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTEN_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */ 2582 #define KMU_INTEN_KEYSLOT_REVOKED_Disabled (0UL) /*!< Disable */ 2583 #define KMU_INTEN_KEYSLOT_REVOKED_Enabled (1UL) /*!< Enable */ 2584 2585 /* Bit 0 : Enable or disable interrupt for event KEYSLOT_PUSHED */ 2586 #define KMU_INTEN_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */ 2587 #define KMU_INTEN_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTEN_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */ 2588 #define KMU_INTEN_KEYSLOT_PUSHED_Disabled (0UL) /*!< Disable */ 2589 #define KMU_INTEN_KEYSLOT_PUSHED_Enabled (1UL) /*!< Enable */ 2590 2591 /* Register: KMU_INTENSET */ 2592 /* Description: Enable interrupt */ 2593 2594 /* Bit 2 : Write '1' to enable interrupt for event KEYSLOT_ERROR */ 2595 #define KMU_INTENSET_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */ 2596 #define KMU_INTENSET_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTENSET_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */ 2597 #define KMU_INTENSET_KEYSLOT_ERROR_Disabled (0UL) /*!< Read: Disabled */ 2598 #define KMU_INTENSET_KEYSLOT_ERROR_Enabled (1UL) /*!< Read: Enabled */ 2599 #define KMU_INTENSET_KEYSLOT_ERROR_Set (1UL) /*!< Enable */ 2600 2601 /* Bit 1 : Write '1' to enable interrupt for event KEYSLOT_REVOKED */ 2602 #define KMU_INTENSET_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */ 2603 #define KMU_INTENSET_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTENSET_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */ 2604 #define KMU_INTENSET_KEYSLOT_REVOKED_Disabled (0UL) /*!< Read: Disabled */ 2605 #define KMU_INTENSET_KEYSLOT_REVOKED_Enabled (1UL) /*!< Read: Enabled */ 2606 #define KMU_INTENSET_KEYSLOT_REVOKED_Set (1UL) /*!< Enable */ 2607 2608 /* Bit 0 : Write '1' to enable interrupt for event KEYSLOT_PUSHED */ 2609 #define KMU_INTENSET_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */ 2610 #define KMU_INTENSET_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTENSET_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */ 2611 #define KMU_INTENSET_KEYSLOT_PUSHED_Disabled (0UL) /*!< Read: Disabled */ 2612 #define KMU_INTENSET_KEYSLOT_PUSHED_Enabled (1UL) /*!< Read: Enabled */ 2613 #define KMU_INTENSET_KEYSLOT_PUSHED_Set (1UL) /*!< Enable */ 2614 2615 /* Register: KMU_INTENCLR */ 2616 /* Description: Disable interrupt */ 2617 2618 /* Bit 2 : Write '1' to disable interrupt for event KEYSLOT_ERROR */ 2619 #define KMU_INTENCLR_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */ 2620 #define KMU_INTENCLR_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */ 2621 #define KMU_INTENCLR_KEYSLOT_ERROR_Disabled (0UL) /*!< Read: Disabled */ 2622 #define KMU_INTENCLR_KEYSLOT_ERROR_Enabled (1UL) /*!< Read: Enabled */ 2623 #define KMU_INTENCLR_KEYSLOT_ERROR_Clear (1UL) /*!< Disable */ 2624 2625 /* Bit 1 : Write '1' to disable interrupt for event KEYSLOT_REVOKED */ 2626 #define KMU_INTENCLR_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */ 2627 #define KMU_INTENCLR_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */ 2628 #define KMU_INTENCLR_KEYSLOT_REVOKED_Disabled (0UL) /*!< Read: Disabled */ 2629 #define KMU_INTENCLR_KEYSLOT_REVOKED_Enabled (1UL) /*!< Read: Enabled */ 2630 #define KMU_INTENCLR_KEYSLOT_REVOKED_Clear (1UL) /*!< Disable */ 2631 2632 /* Bit 0 : Write '1' to disable interrupt for event KEYSLOT_PUSHED */ 2633 #define KMU_INTENCLR_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */ 2634 #define KMU_INTENCLR_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */ 2635 #define KMU_INTENCLR_KEYSLOT_PUSHED_Disabled (0UL) /*!< Read: Disabled */ 2636 #define KMU_INTENCLR_KEYSLOT_PUSHED_Enabled (1UL) /*!< Read: Enabled */ 2637 #define KMU_INTENCLR_KEYSLOT_PUSHED_Clear (1UL) /*!< Disable */ 2638 2639 /* Register: KMU_INTPEND */ 2640 /* Description: Pending interrupts */ 2641 2642 /* Bit 2 : Read pending status of interrupt for event KEYSLOT_ERROR */ 2643 #define KMU_INTPEND_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */ 2644 #define KMU_INTPEND_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTPEND_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */ 2645 #define KMU_INTPEND_KEYSLOT_ERROR_NotPending (0UL) /*!< Read: Not pending */ 2646 #define KMU_INTPEND_KEYSLOT_ERROR_Pending (1UL) /*!< Read: Pending */ 2647 2648 /* Bit 1 : Read pending status of interrupt for event KEYSLOT_REVOKED */ 2649 #define KMU_INTPEND_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */ 2650 #define KMU_INTPEND_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTPEND_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */ 2651 #define KMU_INTPEND_KEYSLOT_REVOKED_NotPending (0UL) /*!< Read: Not pending */ 2652 #define KMU_INTPEND_KEYSLOT_REVOKED_Pending (1UL) /*!< Read: Pending */ 2653 2654 /* Bit 0 : Read pending status of interrupt for event KEYSLOT_PUSHED */ 2655 #define KMU_INTPEND_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */ 2656 #define KMU_INTPEND_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTPEND_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */ 2657 #define KMU_INTPEND_KEYSLOT_PUSHED_NotPending (0UL) /*!< Read: Not pending */ 2658 #define KMU_INTPEND_KEYSLOT_PUSHED_Pending (1UL) /*!< Read: Pending */ 2659 2660 /* Register: KMU_STATUS */ 2661 /* Description: Status bits for KMU operation */ 2662 2663 /* Bit 1 : Violation status */ 2664 #define KMU_STATUS_BLOCKED_Pos (1UL) /*!< Position of BLOCKED field. */ 2665 #define KMU_STATUS_BLOCKED_Msk (0x1UL << KMU_STATUS_BLOCKED_Pos) /*!< Bit mask of BLOCKED field. */ 2666 #define KMU_STATUS_BLOCKED_Disabled (0UL) /*!< No access violation detected */ 2667 #define KMU_STATUS_BLOCKED_Enabled (1UL) /*!< Access violation detected and blocked */ 2668 2669 /* Bit 0 : Key slot ID successfully selected by the KMU */ 2670 #define KMU_STATUS_SELECTED_Pos (0UL) /*!< Position of SELECTED field. */ 2671 #define KMU_STATUS_SELECTED_Msk (0x1UL << KMU_STATUS_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ 2672 #define KMU_STATUS_SELECTED_Disabled (0UL) /*!< No key slot ID selected by KMU */ 2673 #define KMU_STATUS_SELECTED_Enabled (1UL) /*!< Key slot ID successfully selected by KMU */ 2674 2675 /* Register: KMU_SELECTKEYSLOT */ 2676 /* Description: Select key slot to be read over AHB or pushed over secure APB when TASKS_PUSH_KEYSLOT is started */ 2677 2678 /* Bits 7..0 : Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started. NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use. NOTE: Index N in UICR->KEYSLOT.KEY[N] and UICR->KEYSLOT.CONFIG[N] corresponds to KMU key slot ID=N+1. */ 2679 #define KMU_SELECTKEYSLOT_ID_Pos (0UL) /*!< Position of ID field. */ 2680 #define KMU_SELECTKEYSLOT_ID_Msk (0xFFUL << KMU_SELECTKEYSLOT_ID_Pos) /*!< Bit mask of ID field. */ 2681 2682 2683 /* Peripheral: NVMC */ 2684 /* Description: Non-volatile memory controller 0 */ 2685 2686 /* Register: NVMC_READY */ 2687 /* Description: Ready flag */ 2688 2689 /* Bit 0 : NVMC is ready or busy */ 2690 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ 2691 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ 2692 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */ 2693 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */ 2694 2695 /* Register: NVMC_READYNEXT */ 2696 /* Description: Ready flag */ 2697 2698 /* Bit 0 : NVMC can accept a new write operation */ 2699 #define NVMC_READYNEXT_READYNEXT_Pos (0UL) /*!< Position of READYNEXT field. */ 2700 #define NVMC_READYNEXT_READYNEXT_Msk (0x1UL << NVMC_READYNEXT_READYNEXT_Pos) /*!< Bit mask of READYNEXT field. */ 2701 #define NVMC_READYNEXT_READYNEXT_Busy (0UL) /*!< NVMC cannot accept any write operation */ 2702 #define NVMC_READYNEXT_READYNEXT_Ready (1UL) /*!< NVMC is ready */ 2703 2704 /* Register: NVMC_CONFIG */ 2705 /* Description: Configuration register */ 2706 2707 /* Bits 2..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */ 2708 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ 2709 #define NVMC_CONFIG_WEN_Msk (0x7UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ 2710 #define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */ 2711 #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */ 2712 #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */ 2713 #define NVMC_CONFIG_WEN_PEen (4UL) /*!< Partial erase enabled */ 2714 2715 /* Register: NVMC_ERASEALL */ 2716 /* Description: Register for erasing all non-volatile user memory */ 2717 2718 /* Bit 0 : Erase all non-volatile memory including UICR registers. Note that erasing must be enabled by setting CONFIG.WEN = Een before the non-volatile memory can be erased. */ 2719 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ 2720 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ 2721 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */ 2722 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */ 2723 2724 /* Register: NVMC_ERASEPAGEPARTIALCFG */ 2725 /* Description: Register for partial erase configuration */ 2726 2727 /* Bits 6..0 : Duration of the partial erase in milliseconds */ 2728 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL) /*!< Position of DURATION field. */ 2729 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */ 2730 2731 /* Register: NVMC_ICACHECNF */ 2732 /* Description: I-code cache configuration register */ 2733 2734 /* Bit 8 : Cache profiling enable */ 2735 #define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */ 2736 #define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */ 2737 #define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */ 2738 #define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */ 2739 2740 /* Bit 0 : Cache enable */ 2741 #define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */ 2742 #define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */ 2743 #define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */ 2744 #define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */ 2745 2746 /* Register: NVMC_IHIT */ 2747 /* Description: I-code cache hit counter */ 2748 2749 /* Bits 31..0 : Number of cache hits Write zero to clear */ 2750 #define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */ 2751 #define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */ 2752 2753 /* Register: NVMC_IMISS */ 2754 /* Description: I-code cache miss counter */ 2755 2756 /* Bits 31..0 : Number of cache misses Write zero to clear */ 2757 #define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */ 2758 #define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */ 2759 2760 /* Register: NVMC_CONFIGNS */ 2761 /* Description: Unspecified */ 2762 2763 /* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */ 2764 #define NVMC_CONFIGNS_WEN_Pos (0UL) /*!< Position of WEN field. */ 2765 #define NVMC_CONFIGNS_WEN_Msk (0x3UL << NVMC_CONFIGNS_WEN_Pos) /*!< Bit mask of WEN field. */ 2766 #define NVMC_CONFIGNS_WEN_Ren (0UL) /*!< Read only access */ 2767 #define NVMC_CONFIGNS_WEN_Wen (1UL) /*!< Write enabled */ 2768 #define NVMC_CONFIGNS_WEN_Een (2UL) /*!< Erase enabled */ 2769 2770 /* Register: NVMC_WRITEUICRNS */ 2771 /* Description: Non-secure APPROTECT enable register */ 2772 2773 /* Bits 31..4 : Key to write in order to validate the write operation */ 2774 #define NVMC_WRITEUICRNS_KEY_Pos (4UL) /*!< Position of KEY field. */ 2775 #define NVMC_WRITEUICRNS_KEY_Msk (0xFFFFFFFUL << NVMC_WRITEUICRNS_KEY_Pos) /*!< Bit mask of KEY field. */ 2776 #define NVMC_WRITEUICRNS_KEY_Keyvalid (0xAFBE5A7UL) /*!< Key value */ 2777 2778 /* Bit 0 : Allow non-secure code to set APPROTECT */ 2779 #define NVMC_WRITEUICRNS_SET_Pos (0UL) /*!< Position of SET field. */ 2780 #define NVMC_WRITEUICRNS_SET_Msk (0x1UL << NVMC_WRITEUICRNS_SET_Pos) /*!< Bit mask of SET field. */ 2781 #define NVMC_WRITEUICRNS_SET_Set (1UL) /*!< Set value */ 2782 2783 2784 /* Peripheral: GPIO */ 2785 /* Description: GPIO Port 0 */ 2786 2787 /* Register: GPIO_OUT */ 2788 /* Description: Write GPIO port */ 2789 2790 /* Bit 31 : Pin 31 */ 2791 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 2792 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 2793 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */ 2794 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */ 2795 2796 /* Bit 30 : Pin 30 */ 2797 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 2798 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 2799 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */ 2800 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */ 2801 2802 /* Bit 29 : Pin 29 */ 2803 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 2804 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 2805 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */ 2806 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */ 2807 2808 /* Bit 28 : Pin 28 */ 2809 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 2810 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 2811 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */ 2812 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */ 2813 2814 /* Bit 27 : Pin 27 */ 2815 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 2816 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 2817 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */ 2818 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */ 2819 2820 /* Bit 26 : Pin 26 */ 2821 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 2822 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 2823 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */ 2824 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */ 2825 2826 /* Bit 25 : Pin 25 */ 2827 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 2828 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 2829 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */ 2830 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */ 2831 2832 /* Bit 24 : Pin 24 */ 2833 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 2834 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 2835 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */ 2836 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */ 2837 2838 /* Bit 23 : Pin 23 */ 2839 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 2840 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 2841 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */ 2842 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */ 2843 2844 /* Bit 22 : Pin 22 */ 2845 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 2846 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 2847 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */ 2848 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */ 2849 2850 /* Bit 21 : Pin 21 */ 2851 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 2852 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 2853 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */ 2854 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */ 2855 2856 /* Bit 20 : Pin 20 */ 2857 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 2858 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 2859 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */ 2860 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */ 2861 2862 /* Bit 19 : Pin 19 */ 2863 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 2864 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 2865 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */ 2866 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */ 2867 2868 /* Bit 18 : Pin 18 */ 2869 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 2870 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 2871 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */ 2872 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */ 2873 2874 /* Bit 17 : Pin 17 */ 2875 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 2876 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 2877 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */ 2878 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */ 2879 2880 /* Bit 16 : Pin 16 */ 2881 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 2882 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 2883 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */ 2884 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */ 2885 2886 /* Bit 15 : Pin 15 */ 2887 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 2888 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 2889 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */ 2890 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */ 2891 2892 /* Bit 14 : Pin 14 */ 2893 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 2894 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 2895 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */ 2896 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */ 2897 2898 /* Bit 13 : Pin 13 */ 2899 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 2900 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 2901 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */ 2902 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */ 2903 2904 /* Bit 12 : Pin 12 */ 2905 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 2906 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 2907 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */ 2908 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */ 2909 2910 /* Bit 11 : Pin 11 */ 2911 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 2912 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 2913 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */ 2914 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */ 2915 2916 /* Bit 10 : Pin 10 */ 2917 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 2918 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 2919 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */ 2920 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */ 2921 2922 /* Bit 9 : Pin 9 */ 2923 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 2924 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 2925 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */ 2926 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */ 2927 2928 /* Bit 8 : Pin 8 */ 2929 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 2930 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 2931 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */ 2932 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */ 2933 2934 /* Bit 7 : Pin 7 */ 2935 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 2936 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 2937 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */ 2938 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */ 2939 2940 /* Bit 6 : Pin 6 */ 2941 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 2942 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 2943 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */ 2944 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */ 2945 2946 /* Bit 5 : Pin 5 */ 2947 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 2948 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 2949 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */ 2950 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */ 2951 2952 /* Bit 4 : Pin 4 */ 2953 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 2954 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 2955 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */ 2956 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */ 2957 2958 /* Bit 3 : Pin 3 */ 2959 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 2960 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 2961 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */ 2962 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */ 2963 2964 /* Bit 2 : Pin 2 */ 2965 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 2966 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 2967 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */ 2968 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */ 2969 2970 /* Bit 1 : Pin 1 */ 2971 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 2972 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 2973 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */ 2974 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */ 2975 2976 /* Bit 0 : Pin 0 */ 2977 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 2978 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 2979 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */ 2980 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */ 2981 2982 /* Register: GPIO_OUTSET */ 2983 /* Description: Set individual bits in GPIO port */ 2984 2985 /* Bit 31 : Pin 31 */ 2986 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 2987 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 2988 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */ 2989 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */ 2990 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2991 2992 /* Bit 30 : Pin 30 */ 2993 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 2994 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 2995 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */ 2996 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */ 2997 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2998 2999 /* Bit 29 : Pin 29 */ 3000 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 3001 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 3002 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */ 3003 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */ 3004 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 3005 3006 /* Bit 28 : Pin 28 */ 3007 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 3008 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 3009 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */ 3010 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */ 3011 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 3012 3013 /* Bit 27 : Pin 27 */ 3014 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 3015 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 3016 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */ 3017 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */ 3018 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 3019 3020 /* Bit 26 : Pin 26 */ 3021 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 3022 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 3023 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */ 3024 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */ 3025 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 3026 3027 /* Bit 25 : Pin 25 */ 3028 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 3029 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 3030 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */ 3031 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */ 3032 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 3033 3034 /* Bit 24 : Pin 24 */ 3035 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 3036 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 3037 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */ 3038 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */ 3039 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 3040 3041 /* Bit 23 : Pin 23 */ 3042 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 3043 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 3044 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */ 3045 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */ 3046 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 3047 3048 /* Bit 22 : Pin 22 */ 3049 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 3050 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 3051 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */ 3052 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */ 3053 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 3054 3055 /* Bit 21 : Pin 21 */ 3056 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 3057 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 3058 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */ 3059 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */ 3060 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 3061 3062 /* Bit 20 : Pin 20 */ 3063 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 3064 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 3065 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */ 3066 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */ 3067 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 3068 3069 /* Bit 19 : Pin 19 */ 3070 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 3071 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 3072 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */ 3073 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */ 3074 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 3075 3076 /* Bit 18 : Pin 18 */ 3077 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 3078 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 3079 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */ 3080 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */ 3081 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 3082 3083 /* Bit 17 : Pin 17 */ 3084 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 3085 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 3086 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */ 3087 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */ 3088 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 3089 3090 /* Bit 16 : Pin 16 */ 3091 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 3092 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 3093 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */ 3094 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */ 3095 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 3096 3097 /* Bit 15 : Pin 15 */ 3098 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 3099 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 3100 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */ 3101 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */ 3102 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 3103 3104 /* Bit 14 : Pin 14 */ 3105 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 3106 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 3107 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */ 3108 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */ 3109 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 3110 3111 /* Bit 13 : Pin 13 */ 3112 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 3113 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 3114 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */ 3115 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */ 3116 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 3117 3118 /* Bit 12 : Pin 12 */ 3119 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 3120 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 3121 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */ 3122 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */ 3123 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 3124 3125 /* Bit 11 : Pin 11 */ 3126 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 3127 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 3128 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */ 3129 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */ 3130 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 3131 3132 /* Bit 10 : Pin 10 */ 3133 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 3134 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 3135 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */ 3136 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */ 3137 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 3138 3139 /* Bit 9 : Pin 9 */ 3140 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 3141 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 3142 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */ 3143 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */ 3144 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 3145 3146 /* Bit 8 : Pin 8 */ 3147 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 3148 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 3149 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */ 3150 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */ 3151 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 3152 3153 /* Bit 7 : Pin 7 */ 3154 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 3155 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 3156 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */ 3157 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */ 3158 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 3159 3160 /* Bit 6 : Pin 6 */ 3161 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 3162 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 3163 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */ 3164 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */ 3165 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 3166 3167 /* Bit 5 : Pin 5 */ 3168 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 3169 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 3170 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */ 3171 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */ 3172 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 3173 3174 /* Bit 4 : Pin 4 */ 3175 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 3176 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 3177 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */ 3178 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */ 3179 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 3180 3181 /* Bit 3 : Pin 3 */ 3182 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 3183 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 3184 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */ 3185 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */ 3186 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 3187 3188 /* Bit 2 : Pin 2 */ 3189 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 3190 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 3191 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */ 3192 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */ 3193 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 3194 3195 /* Bit 1 : Pin 1 */ 3196 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 3197 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 3198 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */ 3199 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */ 3200 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 3201 3202 /* Bit 0 : Pin 0 */ 3203 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 3204 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 3205 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */ 3206 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */ 3207 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 3208 3209 /* Register: GPIO_OUTCLR */ 3210 /* Description: Clear individual bits in GPIO port */ 3211 3212 /* Bit 31 : Pin 31 */ 3213 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 3214 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 3215 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */ 3216 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */ 3217 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3218 3219 /* Bit 30 : Pin 30 */ 3220 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 3221 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 3222 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */ 3223 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */ 3224 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3225 3226 /* Bit 29 : Pin 29 */ 3227 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 3228 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 3229 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */ 3230 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */ 3231 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3232 3233 /* Bit 28 : Pin 28 */ 3234 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 3235 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 3236 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */ 3237 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */ 3238 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3239 3240 /* Bit 27 : Pin 27 */ 3241 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 3242 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 3243 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */ 3244 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */ 3245 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3246 3247 /* Bit 26 : Pin 26 */ 3248 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 3249 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 3250 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */ 3251 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */ 3252 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3253 3254 /* Bit 25 : Pin 25 */ 3255 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 3256 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 3257 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */ 3258 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */ 3259 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3260 3261 /* Bit 24 : Pin 24 */ 3262 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 3263 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 3264 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */ 3265 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */ 3266 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3267 3268 /* Bit 23 : Pin 23 */ 3269 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 3270 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 3271 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */ 3272 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */ 3273 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3274 3275 /* Bit 22 : Pin 22 */ 3276 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 3277 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 3278 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */ 3279 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */ 3280 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3281 3282 /* Bit 21 : Pin 21 */ 3283 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 3284 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 3285 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */ 3286 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */ 3287 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3288 3289 /* Bit 20 : Pin 20 */ 3290 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 3291 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 3292 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */ 3293 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */ 3294 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3295 3296 /* Bit 19 : Pin 19 */ 3297 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 3298 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 3299 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */ 3300 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */ 3301 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3302 3303 /* Bit 18 : Pin 18 */ 3304 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 3305 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 3306 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */ 3307 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */ 3308 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3309 3310 /* Bit 17 : Pin 17 */ 3311 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 3312 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 3313 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */ 3314 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */ 3315 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3316 3317 /* Bit 16 : Pin 16 */ 3318 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 3319 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 3320 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */ 3321 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */ 3322 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3323 3324 /* Bit 15 : Pin 15 */ 3325 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 3326 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 3327 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */ 3328 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */ 3329 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3330 3331 /* Bit 14 : Pin 14 */ 3332 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 3333 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 3334 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */ 3335 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */ 3336 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3337 3338 /* Bit 13 : Pin 13 */ 3339 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 3340 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 3341 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */ 3342 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */ 3343 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3344 3345 /* Bit 12 : Pin 12 */ 3346 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 3347 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 3348 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */ 3349 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */ 3350 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3351 3352 /* Bit 11 : Pin 11 */ 3353 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 3354 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 3355 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */ 3356 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */ 3357 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3358 3359 /* Bit 10 : Pin 10 */ 3360 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 3361 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 3362 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */ 3363 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */ 3364 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3365 3366 /* Bit 9 : Pin 9 */ 3367 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 3368 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 3369 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */ 3370 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */ 3371 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3372 3373 /* Bit 8 : Pin 8 */ 3374 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 3375 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 3376 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */ 3377 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */ 3378 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3379 3380 /* Bit 7 : Pin 7 */ 3381 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 3382 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 3383 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */ 3384 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */ 3385 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3386 3387 /* Bit 6 : Pin 6 */ 3388 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 3389 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 3390 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */ 3391 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */ 3392 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3393 3394 /* Bit 5 : Pin 5 */ 3395 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 3396 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 3397 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */ 3398 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */ 3399 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3400 3401 /* Bit 4 : Pin 4 */ 3402 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 3403 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 3404 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */ 3405 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */ 3406 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3407 3408 /* Bit 3 : Pin 3 */ 3409 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 3410 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 3411 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */ 3412 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */ 3413 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3414 3415 /* Bit 2 : Pin 2 */ 3416 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 3417 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 3418 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */ 3419 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */ 3420 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3421 3422 /* Bit 1 : Pin 1 */ 3423 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 3424 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 3425 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */ 3426 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */ 3427 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3428 3429 /* Bit 0 : Pin 0 */ 3430 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 3431 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 3432 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */ 3433 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */ 3434 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 3435 3436 /* Register: GPIO_IN */ 3437 /* Description: Read GPIO port */ 3438 3439 /* Bit 31 : Pin 31 */ 3440 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 3441 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 3442 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */ 3443 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */ 3444 3445 /* Bit 30 : Pin 30 */ 3446 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 3447 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 3448 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */ 3449 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */ 3450 3451 /* Bit 29 : Pin 29 */ 3452 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 3453 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 3454 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */ 3455 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */ 3456 3457 /* Bit 28 : Pin 28 */ 3458 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 3459 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 3460 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */ 3461 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */ 3462 3463 /* Bit 27 : Pin 27 */ 3464 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 3465 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 3466 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */ 3467 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */ 3468 3469 /* Bit 26 : Pin 26 */ 3470 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 3471 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 3472 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */ 3473 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */ 3474 3475 /* Bit 25 : Pin 25 */ 3476 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 3477 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 3478 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */ 3479 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */ 3480 3481 /* Bit 24 : Pin 24 */ 3482 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 3483 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 3484 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */ 3485 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */ 3486 3487 /* Bit 23 : Pin 23 */ 3488 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 3489 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 3490 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */ 3491 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */ 3492 3493 /* Bit 22 : Pin 22 */ 3494 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 3495 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 3496 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */ 3497 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */ 3498 3499 /* Bit 21 : Pin 21 */ 3500 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 3501 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 3502 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */ 3503 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */ 3504 3505 /* Bit 20 : Pin 20 */ 3506 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 3507 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 3508 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */ 3509 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */ 3510 3511 /* Bit 19 : Pin 19 */ 3512 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 3513 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 3514 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */ 3515 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */ 3516 3517 /* Bit 18 : Pin 18 */ 3518 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 3519 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 3520 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */ 3521 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */ 3522 3523 /* Bit 17 : Pin 17 */ 3524 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 3525 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 3526 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */ 3527 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */ 3528 3529 /* Bit 16 : Pin 16 */ 3530 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 3531 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 3532 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */ 3533 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */ 3534 3535 /* Bit 15 : Pin 15 */ 3536 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 3537 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 3538 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */ 3539 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */ 3540 3541 /* Bit 14 : Pin 14 */ 3542 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 3543 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 3544 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */ 3545 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */ 3546 3547 /* Bit 13 : Pin 13 */ 3548 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 3549 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 3550 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */ 3551 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */ 3552 3553 /* Bit 12 : Pin 12 */ 3554 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 3555 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 3556 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */ 3557 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */ 3558 3559 /* Bit 11 : Pin 11 */ 3560 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 3561 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 3562 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */ 3563 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */ 3564 3565 /* Bit 10 : Pin 10 */ 3566 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 3567 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 3568 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */ 3569 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */ 3570 3571 /* Bit 9 : Pin 9 */ 3572 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 3573 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 3574 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */ 3575 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */ 3576 3577 /* Bit 8 : Pin 8 */ 3578 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 3579 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 3580 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */ 3581 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */ 3582 3583 /* Bit 7 : Pin 7 */ 3584 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 3585 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 3586 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */ 3587 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */ 3588 3589 /* Bit 6 : Pin 6 */ 3590 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 3591 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 3592 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */ 3593 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */ 3594 3595 /* Bit 5 : Pin 5 */ 3596 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 3597 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 3598 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */ 3599 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */ 3600 3601 /* Bit 4 : Pin 4 */ 3602 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 3603 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 3604 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */ 3605 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */ 3606 3607 /* Bit 3 : Pin 3 */ 3608 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 3609 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 3610 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */ 3611 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */ 3612 3613 /* Bit 2 : Pin 2 */ 3614 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 3615 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 3616 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */ 3617 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */ 3618 3619 /* Bit 1 : Pin 1 */ 3620 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 3621 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 3622 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */ 3623 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */ 3624 3625 /* Bit 0 : Pin 0 */ 3626 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 3627 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 3628 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */ 3629 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */ 3630 3631 /* Register: GPIO_DIR */ 3632 /* Description: Direction of GPIO pins */ 3633 3634 /* Bit 31 : Pin 31 */ 3635 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 3636 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 3637 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */ 3638 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */ 3639 3640 /* Bit 30 : Pin 30 */ 3641 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 3642 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 3643 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */ 3644 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */ 3645 3646 /* Bit 29 : Pin 29 */ 3647 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 3648 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 3649 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */ 3650 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */ 3651 3652 /* Bit 28 : Pin 28 */ 3653 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 3654 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 3655 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */ 3656 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */ 3657 3658 /* Bit 27 : Pin 27 */ 3659 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 3660 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 3661 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */ 3662 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */ 3663 3664 /* Bit 26 : Pin 26 */ 3665 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 3666 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 3667 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */ 3668 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */ 3669 3670 /* Bit 25 : Pin 25 */ 3671 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 3672 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 3673 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */ 3674 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */ 3675 3676 /* Bit 24 : Pin 24 */ 3677 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 3678 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 3679 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */ 3680 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */ 3681 3682 /* Bit 23 : Pin 23 */ 3683 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 3684 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 3685 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */ 3686 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */ 3687 3688 /* Bit 22 : Pin 22 */ 3689 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 3690 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 3691 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */ 3692 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */ 3693 3694 /* Bit 21 : Pin 21 */ 3695 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 3696 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 3697 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */ 3698 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */ 3699 3700 /* Bit 20 : Pin 20 */ 3701 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 3702 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 3703 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */ 3704 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */ 3705 3706 /* Bit 19 : Pin 19 */ 3707 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 3708 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 3709 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */ 3710 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */ 3711 3712 /* Bit 18 : Pin 18 */ 3713 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 3714 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 3715 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */ 3716 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */ 3717 3718 /* Bit 17 : Pin 17 */ 3719 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 3720 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 3721 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */ 3722 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */ 3723 3724 /* Bit 16 : Pin 16 */ 3725 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 3726 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 3727 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */ 3728 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */ 3729 3730 /* Bit 15 : Pin 15 */ 3731 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 3732 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 3733 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */ 3734 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */ 3735 3736 /* Bit 14 : Pin 14 */ 3737 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 3738 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 3739 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */ 3740 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */ 3741 3742 /* Bit 13 : Pin 13 */ 3743 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 3744 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 3745 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */ 3746 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */ 3747 3748 /* Bit 12 : Pin 12 */ 3749 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 3750 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 3751 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */ 3752 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */ 3753 3754 /* Bit 11 : Pin 11 */ 3755 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 3756 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 3757 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */ 3758 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */ 3759 3760 /* Bit 10 : Pin 10 */ 3761 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 3762 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 3763 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */ 3764 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */ 3765 3766 /* Bit 9 : Pin 9 */ 3767 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 3768 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 3769 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */ 3770 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */ 3771 3772 /* Bit 8 : Pin 8 */ 3773 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 3774 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 3775 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */ 3776 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */ 3777 3778 /* Bit 7 : Pin 7 */ 3779 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 3780 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 3781 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */ 3782 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */ 3783 3784 /* Bit 6 : Pin 6 */ 3785 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 3786 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 3787 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */ 3788 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */ 3789 3790 /* Bit 5 : Pin 5 */ 3791 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 3792 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 3793 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */ 3794 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */ 3795 3796 /* Bit 4 : Pin 4 */ 3797 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 3798 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 3799 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */ 3800 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */ 3801 3802 /* Bit 3 : Pin 3 */ 3803 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 3804 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 3805 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */ 3806 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */ 3807 3808 /* Bit 2 : Pin 2 */ 3809 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 3810 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 3811 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */ 3812 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */ 3813 3814 /* Bit 1 : Pin 1 */ 3815 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 3816 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 3817 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */ 3818 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */ 3819 3820 /* Bit 0 : Pin 0 */ 3821 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 3822 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 3823 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */ 3824 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */ 3825 3826 /* Register: GPIO_DIRSET */ 3827 /* Description: DIR set register */ 3828 3829 /* Bit 31 : Set as output pin 31 */ 3830 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 3831 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 3832 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */ 3833 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */ 3834 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3835 3836 /* Bit 30 : Set as output pin 30 */ 3837 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 3838 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 3839 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */ 3840 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */ 3841 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3842 3843 /* Bit 29 : Set as output pin 29 */ 3844 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 3845 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 3846 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */ 3847 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */ 3848 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3849 3850 /* Bit 28 : Set as output pin 28 */ 3851 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 3852 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 3853 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */ 3854 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */ 3855 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3856 3857 /* Bit 27 : Set as output pin 27 */ 3858 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 3859 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 3860 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */ 3861 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */ 3862 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3863 3864 /* Bit 26 : Set as output pin 26 */ 3865 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 3866 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 3867 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */ 3868 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */ 3869 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3870 3871 /* Bit 25 : Set as output pin 25 */ 3872 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 3873 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 3874 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */ 3875 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */ 3876 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3877 3878 /* Bit 24 : Set as output pin 24 */ 3879 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 3880 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 3881 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */ 3882 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */ 3883 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3884 3885 /* Bit 23 : Set as output pin 23 */ 3886 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 3887 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 3888 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */ 3889 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */ 3890 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3891 3892 /* Bit 22 : Set as output pin 22 */ 3893 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 3894 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 3895 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */ 3896 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */ 3897 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3898 3899 /* Bit 21 : Set as output pin 21 */ 3900 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 3901 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 3902 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */ 3903 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */ 3904 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3905 3906 /* Bit 20 : Set as output pin 20 */ 3907 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 3908 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 3909 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */ 3910 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */ 3911 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3912 3913 /* Bit 19 : Set as output pin 19 */ 3914 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 3915 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 3916 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */ 3917 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */ 3918 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3919 3920 /* Bit 18 : Set as output pin 18 */ 3921 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 3922 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 3923 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */ 3924 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */ 3925 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3926 3927 /* Bit 17 : Set as output pin 17 */ 3928 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 3929 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 3930 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */ 3931 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */ 3932 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3933 3934 /* Bit 16 : Set as output pin 16 */ 3935 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 3936 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 3937 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */ 3938 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */ 3939 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3940 3941 /* Bit 15 : Set as output pin 15 */ 3942 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 3943 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 3944 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */ 3945 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */ 3946 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3947 3948 /* Bit 14 : Set as output pin 14 */ 3949 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 3950 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 3951 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */ 3952 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */ 3953 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3954 3955 /* Bit 13 : Set as output pin 13 */ 3956 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 3957 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 3958 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */ 3959 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */ 3960 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3961 3962 /* Bit 12 : Set as output pin 12 */ 3963 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 3964 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 3965 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */ 3966 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */ 3967 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3968 3969 /* Bit 11 : Set as output pin 11 */ 3970 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 3971 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 3972 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */ 3973 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */ 3974 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3975 3976 /* Bit 10 : Set as output pin 10 */ 3977 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 3978 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 3979 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */ 3980 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */ 3981 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3982 3983 /* Bit 9 : Set as output pin 9 */ 3984 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 3985 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 3986 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */ 3987 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */ 3988 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3989 3990 /* Bit 8 : Set as output pin 8 */ 3991 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 3992 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 3993 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */ 3994 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */ 3995 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3996 3997 /* Bit 7 : Set as output pin 7 */ 3998 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 3999 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 4000 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */ 4001 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */ 4002 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 4003 4004 /* Bit 6 : Set as output pin 6 */ 4005 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 4006 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 4007 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */ 4008 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */ 4009 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 4010 4011 /* Bit 5 : Set as output pin 5 */ 4012 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 4013 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 4014 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */ 4015 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */ 4016 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 4017 4018 /* Bit 4 : Set as output pin 4 */ 4019 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 4020 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 4021 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */ 4022 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */ 4023 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 4024 4025 /* Bit 3 : Set as output pin 3 */ 4026 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 4027 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 4028 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */ 4029 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */ 4030 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 4031 4032 /* Bit 2 : Set as output pin 2 */ 4033 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 4034 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 4035 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */ 4036 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */ 4037 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 4038 4039 /* Bit 1 : Set as output pin 1 */ 4040 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 4041 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 4042 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */ 4043 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */ 4044 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 4045 4046 /* Bit 0 : Set as output pin 0 */ 4047 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 4048 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 4049 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */ 4050 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */ 4051 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 4052 4053 /* Register: GPIO_DIRCLR */ 4054 /* Description: DIR clear register */ 4055 4056 /* Bit 31 : Set as input pin 31 */ 4057 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 4058 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 4059 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */ 4060 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */ 4061 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4062 4063 /* Bit 30 : Set as input pin 30 */ 4064 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 4065 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 4066 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */ 4067 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */ 4068 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4069 4070 /* Bit 29 : Set as input pin 29 */ 4071 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 4072 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 4073 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */ 4074 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */ 4075 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4076 4077 /* Bit 28 : Set as input pin 28 */ 4078 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 4079 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 4080 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */ 4081 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */ 4082 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4083 4084 /* Bit 27 : Set as input pin 27 */ 4085 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 4086 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 4087 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */ 4088 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */ 4089 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4090 4091 /* Bit 26 : Set as input pin 26 */ 4092 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 4093 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 4094 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */ 4095 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */ 4096 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4097 4098 /* Bit 25 : Set as input pin 25 */ 4099 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 4100 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 4101 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */ 4102 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */ 4103 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4104 4105 /* Bit 24 : Set as input pin 24 */ 4106 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 4107 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 4108 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */ 4109 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */ 4110 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4111 4112 /* Bit 23 : Set as input pin 23 */ 4113 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 4114 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 4115 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */ 4116 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */ 4117 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4118 4119 /* Bit 22 : Set as input pin 22 */ 4120 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 4121 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 4122 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */ 4123 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */ 4124 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4125 4126 /* Bit 21 : Set as input pin 21 */ 4127 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 4128 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 4129 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */ 4130 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */ 4131 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4132 4133 /* Bit 20 : Set as input pin 20 */ 4134 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 4135 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 4136 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */ 4137 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */ 4138 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4139 4140 /* Bit 19 : Set as input pin 19 */ 4141 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 4142 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 4143 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */ 4144 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */ 4145 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4146 4147 /* Bit 18 : Set as input pin 18 */ 4148 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 4149 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 4150 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */ 4151 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */ 4152 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4153 4154 /* Bit 17 : Set as input pin 17 */ 4155 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 4156 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 4157 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */ 4158 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */ 4159 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4160 4161 /* Bit 16 : Set as input pin 16 */ 4162 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 4163 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 4164 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */ 4165 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */ 4166 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4167 4168 /* Bit 15 : Set as input pin 15 */ 4169 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 4170 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 4171 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */ 4172 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */ 4173 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4174 4175 /* Bit 14 : Set as input pin 14 */ 4176 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 4177 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 4178 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */ 4179 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */ 4180 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4181 4182 /* Bit 13 : Set as input pin 13 */ 4183 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 4184 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 4185 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */ 4186 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */ 4187 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4188 4189 /* Bit 12 : Set as input pin 12 */ 4190 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 4191 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 4192 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */ 4193 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */ 4194 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4195 4196 /* Bit 11 : Set as input pin 11 */ 4197 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 4198 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 4199 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */ 4200 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */ 4201 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4202 4203 /* Bit 10 : Set as input pin 10 */ 4204 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 4205 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 4206 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */ 4207 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */ 4208 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4209 4210 /* Bit 9 : Set as input pin 9 */ 4211 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 4212 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 4213 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */ 4214 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */ 4215 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4216 4217 /* Bit 8 : Set as input pin 8 */ 4218 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 4219 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 4220 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */ 4221 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */ 4222 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4223 4224 /* Bit 7 : Set as input pin 7 */ 4225 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 4226 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 4227 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */ 4228 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */ 4229 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4230 4231 /* Bit 6 : Set as input pin 6 */ 4232 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 4233 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 4234 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */ 4235 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */ 4236 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4237 4238 /* Bit 5 : Set as input pin 5 */ 4239 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 4240 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 4241 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */ 4242 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */ 4243 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4244 4245 /* Bit 4 : Set as input pin 4 */ 4246 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 4247 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 4248 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */ 4249 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */ 4250 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4251 4252 /* Bit 3 : Set as input pin 3 */ 4253 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 4254 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 4255 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */ 4256 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */ 4257 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4258 4259 /* Bit 2 : Set as input pin 2 */ 4260 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 4261 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 4262 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */ 4263 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */ 4264 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4265 4266 /* Bit 1 : Set as input pin 1 */ 4267 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 4268 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 4269 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */ 4270 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */ 4271 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4272 4273 /* Bit 0 : Set as input pin 0 */ 4274 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 4275 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 4276 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */ 4277 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */ 4278 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 4279 4280 /* Register: GPIO_LATCH */ 4281 /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ 4282 4283 /* Bit 31 : Status on whether PIN[31] has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. */ 4284 #define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 4285 #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 4286 #define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */ 4287 #define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */ 4288 4289 /* Bit 30 : Status on whether PIN[30] has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. */ 4290 #define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 4291 #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 4292 #define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */ 4293 #define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */ 4294 4295 /* Bit 29 : Status on whether PIN[29] has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. */ 4296 #define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 4297 #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 4298 #define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */ 4299 #define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */ 4300 4301 /* Bit 28 : Status on whether PIN[28] has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. */ 4302 #define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 4303 #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 4304 #define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */ 4305 #define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */ 4306 4307 /* Bit 27 : Status on whether PIN[27] has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. */ 4308 #define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 4309 #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 4310 #define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */ 4311 #define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */ 4312 4313 /* Bit 26 : Status on whether PIN[26] has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. */ 4314 #define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 4315 #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 4316 #define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */ 4317 #define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */ 4318 4319 /* Bit 25 : Status on whether PIN[25] has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. */ 4320 #define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 4321 #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 4322 #define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */ 4323 #define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */ 4324 4325 /* Bit 24 : Status on whether PIN[24] has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. */ 4326 #define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 4327 #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 4328 #define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */ 4329 #define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */ 4330 4331 /* Bit 23 : Status on whether PIN[23] has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. */ 4332 #define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 4333 #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 4334 #define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */ 4335 #define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */ 4336 4337 /* Bit 22 : Status on whether PIN[22] has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. */ 4338 #define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 4339 #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 4340 #define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */ 4341 #define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */ 4342 4343 /* Bit 21 : Status on whether PIN[21] has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. */ 4344 #define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 4345 #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 4346 #define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */ 4347 #define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */ 4348 4349 /* Bit 20 : Status on whether PIN[20] has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. */ 4350 #define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 4351 #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 4352 #define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */ 4353 #define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */ 4354 4355 /* Bit 19 : Status on whether PIN[19] has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. */ 4356 #define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 4357 #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 4358 #define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */ 4359 #define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */ 4360 4361 /* Bit 18 : Status on whether PIN[18] has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. */ 4362 #define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 4363 #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 4364 #define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */ 4365 #define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */ 4366 4367 /* Bit 17 : Status on whether PIN[17] has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. */ 4368 #define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 4369 #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 4370 #define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */ 4371 #define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */ 4372 4373 /* Bit 16 : Status on whether PIN[16] has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. */ 4374 #define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 4375 #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 4376 #define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */ 4377 #define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */ 4378 4379 /* Bit 15 : Status on whether PIN[15] has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. */ 4380 #define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 4381 #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 4382 #define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */ 4383 #define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */ 4384 4385 /* Bit 14 : Status on whether PIN[14] has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. */ 4386 #define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 4387 #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 4388 #define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */ 4389 #define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */ 4390 4391 /* Bit 13 : Status on whether PIN[13] has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. */ 4392 #define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 4393 #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 4394 #define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */ 4395 #define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */ 4396 4397 /* Bit 12 : Status on whether PIN[12] has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. */ 4398 #define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 4399 #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 4400 #define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */ 4401 #define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */ 4402 4403 /* Bit 11 : Status on whether PIN[11] has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. */ 4404 #define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 4405 #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 4406 #define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */ 4407 #define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */ 4408 4409 /* Bit 10 : Status on whether PIN[10] has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. */ 4410 #define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 4411 #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 4412 #define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */ 4413 #define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */ 4414 4415 /* Bit 9 : Status on whether PIN[9] has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. */ 4416 #define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 4417 #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 4418 #define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */ 4419 #define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */ 4420 4421 /* Bit 8 : Status on whether PIN[8] has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. */ 4422 #define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 4423 #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 4424 #define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */ 4425 #define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */ 4426 4427 /* Bit 7 : Status on whether PIN[7] has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. */ 4428 #define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 4429 #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 4430 #define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */ 4431 #define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */ 4432 4433 /* Bit 6 : Status on whether PIN[6] has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. */ 4434 #define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 4435 #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 4436 #define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */ 4437 #define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */ 4438 4439 /* Bit 5 : Status on whether PIN[5] has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. */ 4440 #define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 4441 #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 4442 #define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */ 4443 #define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */ 4444 4445 /* Bit 4 : Status on whether PIN[4] has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. */ 4446 #define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 4447 #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 4448 #define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */ 4449 #define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */ 4450 4451 /* Bit 3 : Status on whether PIN[3] has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. */ 4452 #define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 4453 #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 4454 #define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */ 4455 #define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */ 4456 4457 /* Bit 2 : Status on whether PIN[2] has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. */ 4458 #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 4459 #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 4460 #define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */ 4461 #define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */ 4462 4463 /* Bit 1 : Status on whether PIN[1] has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. */ 4464 #define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 4465 #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 4466 #define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */ 4467 #define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */ 4468 4469 /* Bit 0 : Status on whether PIN[0] has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. */ 4470 #define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 4471 #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 4472 #define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */ 4473 #define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */ 4474 4475 /* Register: GPIO_DETECTMODE */ 4476 /* Description: Select between default DETECT signal behavior and LDETECT mode (For non-secure pin only) */ 4477 4478 /* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */ 4479 #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */ 4480 #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */ 4481 #define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */ 4482 #define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behavior */ 4483 4484 /* Register: GPIO_DETECTMODE_SEC */ 4485 /* Description: Select between default DETECT signal behavior and LDETECT mode (For secure pin only) */ 4486 4487 /* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */ 4488 #define GPIO_DETECTMODE_SEC_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */ 4489 #define GPIO_DETECTMODE_SEC_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_SEC_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */ 4490 #define GPIO_DETECTMODE_SEC_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */ 4491 #define GPIO_DETECTMODE_SEC_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behavior */ 4492 4493 /* Register: GPIO_PIN_CNF */ 4494 /* Description: Description collection: Configuration of GPIO pins */ 4495 4496 /* Bits 17..16 : Pin sensing mechanism */ 4497 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ 4498 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */ 4499 #define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */ 4500 #define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */ 4501 #define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */ 4502 4503 /* Bits 10..8 : Drive configuration */ 4504 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */ 4505 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */ 4506 #define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */ 4507 #define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */ 4508 #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */ 4509 #define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */ 4510 #define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0', standard '1' (normally used for wired-or connections) */ 4511 #define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */ 4512 #define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0', disconnect '1' (normally used for wired-and connections) */ 4513 #define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */ 4514 4515 /* Bits 3..2 : Pull configuration */ 4516 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */ 4517 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */ 4518 #define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */ 4519 #define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */ 4520 #define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */ 4521 4522 /* Bit 1 : Connect or disconnect input buffer */ 4523 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */ 4524 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */ 4525 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */ 4526 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */ 4527 4528 /* Bit 0 : Pin direction. Same physical register as DIR register */ 4529 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */ 4530 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ 4531 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */ 4532 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */ 4533 4534 4535 /* Peripheral: PDM */ 4536 /* Description: Pulse Density Modulation (Digital Microphone) Interface 0 */ 4537 4538 /* Register: PDM_TASKS_START */ 4539 /* Description: Starts continuous PDM transfer */ 4540 4541 /* Bit 0 : Starts continuous PDM transfer */ 4542 #define PDM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 4543 #define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 4544 #define PDM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ 4545 4546 /* Register: PDM_TASKS_STOP */ 4547 /* Description: Stops PDM transfer */ 4548 4549 /* Bit 0 : Stops PDM transfer */ 4550 #define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 4551 #define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 4552 #define PDM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 4553 4554 /* Register: PDM_SUBSCRIBE_START */ 4555 /* Description: Subscribe configuration for task START */ 4556 4557 /* Bit 31 : */ 4558 #define PDM_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ 4559 #define PDM_SUBSCRIBE_START_EN_Msk (0x1UL << PDM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ 4560 #define PDM_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ 4561 #define PDM_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ 4562 4563 /* Bits 7..0 : DPPI channel that task START will subscribe to */ 4564 #define PDM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4565 #define PDM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << PDM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4566 4567 /* Register: PDM_SUBSCRIBE_STOP */ 4568 /* Description: Subscribe configuration for task STOP */ 4569 4570 /* Bit 31 : */ 4571 #define PDM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 4572 #define PDM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PDM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 4573 #define PDM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ 4574 #define PDM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ 4575 4576 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 4577 #define PDM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4578 #define PDM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << PDM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4579 4580 /* Register: PDM_EVENTS_STARTED */ 4581 /* Description: PDM transfer has started */ 4582 4583 /* Bit 0 : PDM transfer has started */ 4584 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ 4585 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ 4586 #define PDM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ 4587 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ 4588 4589 /* Register: PDM_EVENTS_STOPPED */ 4590 /* Description: PDM transfer has finished */ 4591 4592 /* Bit 0 : PDM transfer has finished */ 4593 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ 4594 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ 4595 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ 4596 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ 4597 4598 /* Register: PDM_EVENTS_END */ 4599 /* Description: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */ 4600 4601 /* Bit 0 : The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */ 4602 #define PDM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ 4603 #define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ 4604 #define PDM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ 4605 #define PDM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ 4606 4607 /* Register: PDM_PUBLISH_STARTED */ 4608 /* Description: Publish configuration for event STARTED */ 4609 4610 /* Bit 31 : */ 4611 #define PDM_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */ 4612 #define PDM_PUBLISH_STARTED_EN_Msk (0x1UL << PDM_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */ 4613 #define PDM_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */ 4614 #define PDM_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */ 4615 4616 /* Bits 7..0 : DPPI channel that event STARTED will publish to */ 4617 #define PDM_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4618 #define PDM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << PDM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4619 4620 /* Register: PDM_PUBLISH_STOPPED */ 4621 /* Description: Publish configuration for event STOPPED */ 4622 4623 /* Bit 31 : */ 4624 #define PDM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ 4625 #define PDM_PUBLISH_STOPPED_EN_Msk (0x1UL << PDM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ 4626 #define PDM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ 4627 #define PDM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ 4628 4629 /* Bits 7..0 : DPPI channel that event STOPPED will publish to */ 4630 #define PDM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4631 #define PDM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << PDM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4632 4633 /* Register: PDM_PUBLISH_END */ 4634 /* Description: Publish configuration for event END */ 4635 4636 /* Bit 31 : */ 4637 #define PDM_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ 4638 #define PDM_PUBLISH_END_EN_Msk (0x1UL << PDM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ 4639 #define PDM_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */ 4640 #define PDM_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */ 4641 4642 /* Bits 7..0 : DPPI channel that event END will publish to */ 4643 #define PDM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4644 #define PDM_PUBLISH_END_CHIDX_Msk (0xFFUL << PDM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4645 4646 /* Register: PDM_INTEN */ 4647 /* Description: Enable or disable interrupt */ 4648 4649 /* Bit 2 : Enable or disable interrupt for event END */ 4650 #define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */ 4651 #define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */ 4652 #define PDM_INTEN_END_Disabled (0UL) /*!< Disable */ 4653 #define PDM_INTEN_END_Enabled (1UL) /*!< Enable */ 4654 4655 /* Bit 1 : Enable or disable interrupt for event STOPPED */ 4656 #define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 4657 #define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 4658 #define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ 4659 #define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ 4660 4661 /* Bit 0 : Enable or disable interrupt for event STARTED */ 4662 #define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ 4663 #define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ 4664 #define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */ 4665 #define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */ 4666 4667 /* Register: PDM_INTENSET */ 4668 /* Description: Enable interrupt */ 4669 4670 /* Bit 2 : Write '1' to enable interrupt for event END */ 4671 #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */ 4672 #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */ 4673 #define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ 4674 #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ 4675 #define PDM_INTENSET_END_Set (1UL) /*!< Enable */ 4676 4677 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */ 4678 #define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 4679 #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 4680 #define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 4681 #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 4682 #define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ 4683 4684 /* Bit 0 : Write '1' to enable interrupt for event STARTED */ 4685 #define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ 4686 #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ 4687 #define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ 4688 #define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ 4689 #define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */ 4690 4691 /* Register: PDM_INTENCLR */ 4692 /* Description: Disable interrupt */ 4693 4694 /* Bit 2 : Write '1' to disable interrupt for event END */ 4695 #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */ 4696 #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 4697 #define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ 4698 #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ 4699 #define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */ 4700 4701 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */ 4702 #define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 4703 #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 4704 #define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 4705 #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 4706 #define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ 4707 4708 /* Bit 0 : Write '1' to disable interrupt for event STARTED */ 4709 #define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ 4710 #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ 4711 #define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ 4712 #define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ 4713 #define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ 4714 4715 /* Register: PDM_ENABLE */ 4716 /* Description: PDM module enable register */ 4717 4718 /* Bit 0 : Enable or disable PDM module */ 4719 #define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 4720 #define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 4721 #define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ 4722 #define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ 4723 4724 /* Register: PDM_PDMCLKCTRL */ 4725 /* Description: PDM clock generator control */ 4726 4727 /* Bits 31..0 : PDM_CLK frequency configuration. */ 4728 #define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */ 4729 #define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */ 4730 #define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */ 4731 #define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. */ 4732 #define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */ 4733 #define PDM_PDMCLKCTRL_FREQ_1231K (0x09800000UL) /*!< PDM_CLK = 32 MHz / 26 = 1.231 MHz */ 4734 #define PDM_PDMCLKCTRL_FREQ_1280K (0x0A000000UL) /*!< PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. */ 4735 #define PDM_PDMCLKCTRL_FREQ_1333K (0x0A800000UL) /*!< PDM_CLK = 32 MHz / 24 = 1.333 MHz */ 4736 4737 /* Register: PDM_MODE */ 4738 /* Description: Defines the routing of the connected PDM microphones' signals */ 4739 4740 /* Bit 1 : Defines on which PDM_CLK edge left (or mono) is sampled */ 4741 #define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */ 4742 #define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */ 4743 #define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */ 4744 #define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */ 4745 4746 /* Bit 0 : Mono or stereo operation */ 4747 #define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */ 4748 #define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */ 4749 #define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] */ 4750 #define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] */ 4751 4752 /* Register: PDM_GAINL */ 4753 /* Description: Left output gain adjustment */ 4754 4755 /* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust */ 4756 #define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */ 4757 #define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */ 4758 #define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */ 4759 #define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */ 4760 #define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */ 4761 4762 /* Register: PDM_GAINR */ 4763 /* Description: Right output gain adjustment */ 4764 4765 /* Bits 6..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */ 4766 #define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */ 4767 #define PDM_GAINR_GAINR_Msk (0x7FUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */ 4768 #define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */ 4769 #define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */ 4770 #define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */ 4771 4772 /* Register: PDM_RATIO */ 4773 /* Description: Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. */ 4774 4775 /* Bit 0 : Selects the ratio between PDM_CLK and output sample rate */ 4776 #define PDM_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */ 4777 #define PDM_RATIO_RATIO_Msk (0x1UL << PDM_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */ 4778 #define PDM_RATIO_RATIO_Ratio64 (0UL) /*!< Ratio of 64 */ 4779 #define PDM_RATIO_RATIO_Ratio80 (1UL) /*!< Ratio of 80 */ 4780 4781 /* Register: PDM_PSEL_CLK */ 4782 /* Description: Pin number configuration for PDM CLK signal */ 4783 4784 /* Bit 31 : Connection */ 4785 #define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 4786 #define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 4787 #define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */ 4788 #define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */ 4789 4790 /* Bits 4..0 : Pin number */ 4791 #define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */ 4792 #define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */ 4793 4794 /* Register: PDM_PSEL_DIN */ 4795 /* Description: Pin number configuration for PDM DIN signal */ 4796 4797 /* Bit 31 : Connection */ 4798 #define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 4799 #define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 4800 #define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */ 4801 #define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */ 4802 4803 /* Bits 4..0 : Pin number */ 4804 #define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */ 4805 #define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */ 4806 4807 /* Register: PDM_SAMPLE_PTR */ 4808 /* Description: RAM address pointer to write samples to with EasyDMA */ 4809 4810 /* Bits 31..0 : Address to write PDM samples to over DMA */ 4811 #define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */ 4812 #define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */ 4813 4814 /* Register: PDM_SAMPLE_MAXCNT */ 4815 /* Description: Number of samples to allocate memory for in EasyDMA mode */ 4816 4817 /* Bits 14..0 : Length of DMA RAM allocation in number of samples */ 4818 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */ 4819 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */ 4820 4821 4822 /* Peripheral: POWER */ 4823 /* Description: Power control 0 */ 4824 4825 /* Register: POWER_TASKS_PWMREQSTART */ 4826 /* Description: Request forcing PWM mode in external DC/DC voltage regulator. (Drives FPWM_DCDC pin high or low depending on a setting in UICR). */ 4827 4828 /* Bit 0 : Request forcing PWM mode in external DC/DC voltage regulator. (Drives FPWM_DCDC pin high or low depending on a setting in UICR). */ 4829 #define POWER_TASKS_PWMREQSTART_TASKS_PWMREQSTART_Pos (0UL) /*!< Position of TASKS_PWMREQSTART field. */ 4830 #define POWER_TASKS_PWMREQSTART_TASKS_PWMREQSTART_Msk (0x1UL << POWER_TASKS_PWMREQSTART_TASKS_PWMREQSTART_Pos) /*!< Bit mask of TASKS_PWMREQSTART field. */ 4831 #define POWER_TASKS_PWMREQSTART_TASKS_PWMREQSTART_Trigger (1UL) /*!< Trigger task */ 4832 4833 /* Register: POWER_TASKS_PWMREQSTOP */ 4834 /* Description: Stop requesting forcing PWM mode in external DC/DC voltage regulator */ 4835 4836 /* Bit 0 : Stop requesting forcing PWM mode in external DC/DC voltage regulator */ 4837 #define POWER_TASKS_PWMREQSTOP_TASKS_PWMREQSTOP_Pos (0UL) /*!< Position of TASKS_PWMREQSTOP field. */ 4838 #define POWER_TASKS_PWMREQSTOP_TASKS_PWMREQSTOP_Msk (0x1UL << POWER_TASKS_PWMREQSTOP_TASKS_PWMREQSTOP_Pos) /*!< Bit mask of TASKS_PWMREQSTOP field. */ 4839 #define POWER_TASKS_PWMREQSTOP_TASKS_PWMREQSTOP_Trigger (1UL) /*!< Trigger task */ 4840 4841 /* Register: POWER_TASKS_CONSTLAT */ 4842 /* Description: Enable constant latency mode. */ 4843 4844 /* Bit 0 : Enable constant latency mode. */ 4845 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */ 4846 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */ 4847 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */ 4848 4849 /* Register: POWER_TASKS_LOWPWR */ 4850 /* Description: Enable low power mode (variable latency) */ 4851 4852 /* Bit 0 : Enable low power mode (variable latency) */ 4853 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */ 4854 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */ 4855 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */ 4856 4857 /* Register: POWER_SUBSCRIBE_PWMREQSTART */ 4858 /* Description: Subscribe configuration for task PWMREQSTART */ 4859 4860 /* Bit 31 : */ 4861 #define POWER_SUBSCRIBE_PWMREQSTART_EN_Pos (31UL) /*!< Position of EN field. */ 4862 #define POWER_SUBSCRIBE_PWMREQSTART_EN_Msk (0x1UL << POWER_SUBSCRIBE_PWMREQSTART_EN_Pos) /*!< Bit mask of EN field. */ 4863 #define POWER_SUBSCRIBE_PWMREQSTART_EN_Disabled (0UL) /*!< Disable subscription */ 4864 #define POWER_SUBSCRIBE_PWMREQSTART_EN_Enabled (1UL) /*!< Enable subscription */ 4865 4866 /* Bits 7..0 : DPPI channel that task PWMREQSTART will subscribe to */ 4867 #define POWER_SUBSCRIBE_PWMREQSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4868 #define POWER_SUBSCRIBE_PWMREQSTART_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_PWMREQSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4869 4870 /* Register: POWER_SUBSCRIBE_PWMREQSTOP */ 4871 /* Description: Subscribe configuration for task PWMREQSTOP */ 4872 4873 /* Bit 31 : */ 4874 #define POWER_SUBSCRIBE_PWMREQSTOP_EN_Pos (31UL) /*!< Position of EN field. */ 4875 #define POWER_SUBSCRIBE_PWMREQSTOP_EN_Msk (0x1UL << POWER_SUBSCRIBE_PWMREQSTOP_EN_Pos) /*!< Bit mask of EN field. */ 4876 #define POWER_SUBSCRIBE_PWMREQSTOP_EN_Disabled (0UL) /*!< Disable subscription */ 4877 #define POWER_SUBSCRIBE_PWMREQSTOP_EN_Enabled (1UL) /*!< Enable subscription */ 4878 4879 /* Bits 7..0 : DPPI channel that task PWMREQSTOP will subscribe to */ 4880 #define POWER_SUBSCRIBE_PWMREQSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4881 #define POWER_SUBSCRIBE_PWMREQSTOP_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_PWMREQSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4882 4883 /* Register: POWER_SUBSCRIBE_CONSTLAT */ 4884 /* Description: Subscribe configuration for task CONSTLAT */ 4885 4886 /* Bit 31 : */ 4887 #define POWER_SUBSCRIBE_CONSTLAT_EN_Pos (31UL) /*!< Position of EN field. */ 4888 #define POWER_SUBSCRIBE_CONSTLAT_EN_Msk (0x1UL << POWER_SUBSCRIBE_CONSTLAT_EN_Pos) /*!< Bit mask of EN field. */ 4889 #define POWER_SUBSCRIBE_CONSTLAT_EN_Disabled (0UL) /*!< Disable subscription */ 4890 #define POWER_SUBSCRIBE_CONSTLAT_EN_Enabled (1UL) /*!< Enable subscription */ 4891 4892 /* Bits 7..0 : DPPI channel that task CONSTLAT will subscribe to */ 4893 #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4894 #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4895 4896 /* Register: POWER_SUBSCRIBE_LOWPWR */ 4897 /* Description: Subscribe configuration for task LOWPWR */ 4898 4899 /* Bit 31 : */ 4900 #define POWER_SUBSCRIBE_LOWPWR_EN_Pos (31UL) /*!< Position of EN field. */ 4901 #define POWER_SUBSCRIBE_LOWPWR_EN_Msk (0x1UL << POWER_SUBSCRIBE_LOWPWR_EN_Pos) /*!< Bit mask of EN field. */ 4902 #define POWER_SUBSCRIBE_LOWPWR_EN_Disabled (0UL) /*!< Disable subscription */ 4903 #define POWER_SUBSCRIBE_LOWPWR_EN_Enabled (1UL) /*!< Enable subscription */ 4904 4905 /* Bits 7..0 : DPPI channel that task LOWPWR will subscribe to */ 4906 #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4907 #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4908 4909 /* Register: POWER_EVENTS_POFWARN */ 4910 /* Description: Power failure warning */ 4911 4912 /* Bit 0 : Power failure warning */ 4913 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */ 4914 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */ 4915 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0UL) /*!< Event not generated */ 4916 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (1UL) /*!< Event generated */ 4917 4918 /* Register: POWER_EVENTS_SLEEPENTER */ 4919 /* Description: CPU entered WFI/WFE sleep */ 4920 4921 /* Bit 0 : CPU entered WFI/WFE sleep */ 4922 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */ 4923 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */ 4924 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0UL) /*!< Event not generated */ 4925 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (1UL) /*!< Event generated */ 4926 4927 /* Register: POWER_EVENTS_SLEEPEXIT */ 4928 /* Description: CPU exited WFI/WFE sleep */ 4929 4930 /* Bit 0 : CPU exited WFI/WFE sleep */ 4931 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */ 4932 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */ 4933 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0UL) /*!< Event not generated */ 4934 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (1UL) /*!< Event generated */ 4935 4936 /* Register: POWER_PUBLISH_POFWARN */ 4937 /* Description: Publish configuration for event POFWARN */ 4938 4939 /* Bit 31 : */ 4940 #define POWER_PUBLISH_POFWARN_EN_Pos (31UL) /*!< Position of EN field. */ 4941 #define POWER_PUBLISH_POFWARN_EN_Msk (0x1UL << POWER_PUBLISH_POFWARN_EN_Pos) /*!< Bit mask of EN field. */ 4942 #define POWER_PUBLISH_POFWARN_EN_Disabled (0UL) /*!< Disable publishing */ 4943 #define POWER_PUBLISH_POFWARN_EN_Enabled (1UL) /*!< Enable publishing */ 4944 4945 /* Bits 7..0 : DPPI channel that event POFWARN will publish to */ 4946 #define POWER_PUBLISH_POFWARN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4947 #define POWER_PUBLISH_POFWARN_CHIDX_Msk (0xFFUL << POWER_PUBLISH_POFWARN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4948 4949 /* Register: POWER_PUBLISH_SLEEPENTER */ 4950 /* Description: Publish configuration for event SLEEPENTER */ 4951 4952 /* Bit 31 : */ 4953 #define POWER_PUBLISH_SLEEPENTER_EN_Pos (31UL) /*!< Position of EN field. */ 4954 #define POWER_PUBLISH_SLEEPENTER_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPENTER_EN_Pos) /*!< Bit mask of EN field. */ 4955 #define POWER_PUBLISH_SLEEPENTER_EN_Disabled (0UL) /*!< Disable publishing */ 4956 #define POWER_PUBLISH_SLEEPENTER_EN_Enabled (1UL) /*!< Enable publishing */ 4957 4958 /* Bits 7..0 : DPPI channel that event SLEEPENTER will publish to */ 4959 #define POWER_PUBLISH_SLEEPENTER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4960 #define POWER_PUBLISH_SLEEPENTER_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPENTER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4961 4962 /* Register: POWER_PUBLISH_SLEEPEXIT */ 4963 /* Description: Publish configuration for event SLEEPEXIT */ 4964 4965 /* Bit 31 : */ 4966 #define POWER_PUBLISH_SLEEPEXIT_EN_Pos (31UL) /*!< Position of EN field. */ 4967 #define POWER_PUBLISH_SLEEPEXIT_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPEXIT_EN_Pos) /*!< Bit mask of EN field. */ 4968 #define POWER_PUBLISH_SLEEPEXIT_EN_Disabled (0UL) /*!< Disable publishing */ 4969 #define POWER_PUBLISH_SLEEPEXIT_EN_Enabled (1UL) /*!< Enable publishing */ 4970 4971 /* Bits 7..0 : DPPI channel that event SLEEPEXIT will publish to */ 4972 #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4973 #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4974 4975 /* Register: POWER_INTEN */ 4976 /* Description: Enable or disable interrupt */ 4977 4978 /* Bit 6 : Enable or disable interrupt for event SLEEPEXIT */ 4979 #define POWER_INTEN_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ 4980 #define POWER_INTEN_SLEEPEXIT_Msk (0x1UL << POWER_INTEN_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ 4981 #define POWER_INTEN_SLEEPEXIT_Disabled (0UL) /*!< Disable */ 4982 #define POWER_INTEN_SLEEPEXIT_Enabled (1UL) /*!< Enable */ 4983 4984 /* Bit 5 : Enable or disable interrupt for event SLEEPENTER */ 4985 #define POWER_INTEN_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ 4986 #define POWER_INTEN_SLEEPENTER_Msk (0x1UL << POWER_INTEN_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ 4987 #define POWER_INTEN_SLEEPENTER_Disabled (0UL) /*!< Disable */ 4988 #define POWER_INTEN_SLEEPENTER_Enabled (1UL) /*!< Enable */ 4989 4990 /* Bit 2 : Enable or disable interrupt for event POFWARN */ 4991 #define POWER_INTEN_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ 4992 #define POWER_INTEN_POFWARN_Msk (0x1UL << POWER_INTEN_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ 4993 #define POWER_INTEN_POFWARN_Disabled (0UL) /*!< Disable */ 4994 #define POWER_INTEN_POFWARN_Enabled (1UL) /*!< Enable */ 4995 4996 /* Register: POWER_INTENSET */ 4997 /* Description: Enable interrupt */ 4998 4999 /* Bit 6 : Write '1' to enable interrupt for event SLEEPEXIT */ 5000 #define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ 5001 #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ 5002 #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ 5003 #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ 5004 #define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */ 5005 5006 /* Bit 5 : Write '1' to enable interrupt for event SLEEPENTER */ 5007 #define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ 5008 #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ 5009 #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ 5010 #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ 5011 #define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */ 5012 5013 /* Bit 2 : Write '1' to enable interrupt for event POFWARN */ 5014 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ 5015 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ 5016 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */ 5017 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */ 5018 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */ 5019 5020 /* Register: POWER_INTENCLR */ 5021 /* Description: Disable interrupt */ 5022 5023 /* Bit 6 : Write '1' to disable interrupt for event SLEEPEXIT */ 5024 #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ 5025 #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ 5026 #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ 5027 #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ 5028 #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */ 5029 5030 /* Bit 5 : Write '1' to disable interrupt for event SLEEPENTER */ 5031 #define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ 5032 #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ 5033 #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ 5034 #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ 5035 #define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */ 5036 5037 /* Bit 2 : Write '1' to disable interrupt for event POFWARN */ 5038 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ 5039 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ 5040 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */ 5041 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */ 5042 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */ 5043 5044 /* Register: POWER_RESETREAS */ 5045 /* Description: Reset reason */ 5046 5047 /* Bit 18 : Reset triggered through CTRL-AP */ 5048 #define POWER_RESETREAS_CTRLAP_Pos (18UL) /*!< Position of CTRLAP field. */ 5049 #define POWER_RESETREAS_CTRLAP_Msk (0x1UL << POWER_RESETREAS_CTRLAP_Pos) /*!< Bit mask of CTRLAP field. */ 5050 #define POWER_RESETREAS_CTRLAP_NotDetected (0UL) /*!< Not detected */ 5051 #define POWER_RESETREAS_CTRLAP_Detected (1UL) /*!< Detected */ 5052 5053 /* Bit 17 : Reset from CPU lock-up detected */ 5054 #define POWER_RESETREAS_LOCKUP_Pos (17UL) /*!< Position of LOCKUP field. */ 5055 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */ 5056 #define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */ 5057 #define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */ 5058 5059 /* Bit 16 : Reset from AIRCR.SYSRESETREQ detected */ 5060 #define POWER_RESETREAS_SREQ_Pos (16UL) /*!< Position of SREQ field. */ 5061 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */ 5062 #define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */ 5063 #define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */ 5064 5065 /* Bit 4 : Reset due to wakeup from System OFF mode, when wakeup is triggered by entering debug interface mode */ 5066 #define POWER_RESETREAS_DIF_Pos (4UL) /*!< Position of DIF field. */ 5067 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */ 5068 #define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */ 5069 #define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */ 5070 5071 /* Bit 2 : Reset due to wakeup from System OFF mode, when wakeup is triggered by DETECT signal from GPIO */ 5072 #define POWER_RESETREAS_OFF_Pos (2UL) /*!< Position of OFF field. */ 5073 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */ 5074 #define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */ 5075 #define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */ 5076 5077 /* Bit 1 : Reset from global watchdog detected */ 5078 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */ 5079 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */ 5080 #define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */ 5081 #define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */ 5082 5083 /* Bit 0 : Reset from pin reset detected */ 5084 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ 5085 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ 5086 #define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */ 5087 #define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */ 5088 5089 /* Register: POWER_POWERSTATUS */ 5090 /* Description: Modem domain power status */ 5091 5092 /* Bit 0 : LTE modem domain status */ 5093 #define POWER_POWERSTATUS_LTEMODEM_Pos (0UL) /*!< Position of LTEMODEM field. */ 5094 #define POWER_POWERSTATUS_LTEMODEM_Msk (0x1UL << POWER_POWERSTATUS_LTEMODEM_Pos) /*!< Bit mask of LTEMODEM field. */ 5095 #define POWER_POWERSTATUS_LTEMODEM_OFF (0UL) /*!< LTE modem domain is powered off */ 5096 #define POWER_POWERSTATUS_LTEMODEM_ON (1UL) /*!< LTE modem domain is powered on */ 5097 5098 /* Register: POWER_GPREGRET */ 5099 /* Description: Description collection: General purpose retention register */ 5100 5101 /* Bits 7..0 : General purpose retention register */ 5102 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ 5103 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ 5104 5105 /* Register: POWER_LTEMODEM_STARTN */ 5106 /* Description: Start LTE modem */ 5107 5108 /* Bit 0 : Start LTE modem */ 5109 #define POWER_LTEMODEM_STARTN_STARTN_Pos (0UL) /*!< Position of STARTN field. */ 5110 #define POWER_LTEMODEM_STARTN_STARTN_Msk (0x1UL << POWER_LTEMODEM_STARTN_STARTN_Pos) /*!< Bit mask of STARTN field. */ 5111 #define POWER_LTEMODEM_STARTN_STARTN_Start (0UL) /*!< Start LTE modem */ 5112 #define POWER_LTEMODEM_STARTN_STARTN_Hold (1UL) /*!< Hold LTE modem disabled */ 5113 5114 /* Register: POWER_LTEMODEM_FORCEOFF */ 5115 /* Description: Force off LTE modem */ 5116 5117 /* Bit 0 : Force off LTE modem */ 5118 #define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */ 5119 #define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Msk (0x1UL << POWER_LTEMODEM_FORCEOFF_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */ 5120 #define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Release (0UL) /*!< Release force off */ 5121 #define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Hold (1UL) /*!< Hold force off active */ 5122 5123 5124 /* Peripheral: PWM */ 5125 /* Description: Pulse width modulation unit 0 */ 5126 5127 /* Register: PWM_TASKS_STOP */ 5128 /* Description: Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */ 5129 5130 /* Bit 0 : Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */ 5131 #define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 5132 #define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 5133 #define PWM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 5134 5135 /* Register: PWM_TASKS_SEQSTART */ 5136 /* Description: Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ 5137 5138 /* Bit 0 : Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ 5139 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos (0UL) /*!< Position of TASKS_SEQSTART field. */ 5140 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Msk (0x1UL << PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos) /*!< Bit mask of TASKS_SEQSTART field. */ 5141 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Trigger (1UL) /*!< Trigger task */ 5142 5143 /* Register: PWM_TASKS_NEXTSTEP */ 5144 /* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */ 5145 5146 /* Bit 0 : Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */ 5147 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL) /*!< Position of TASKS_NEXTSTEP field. */ 5148 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos) /*!< Bit mask of TASKS_NEXTSTEP field. */ 5149 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (1UL) /*!< Trigger task */ 5150 5151 /* Register: PWM_SUBSCRIBE_STOP */ 5152 /* Description: Subscribe configuration for task STOP */ 5153 5154 /* Bit 31 : */ 5155 #define PWM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 5156 #define PWM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PWM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 5157 #define PWM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ 5158 #define PWM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ 5159 5160 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 5161 #define PWM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5162 #define PWM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5163 5164 /* Register: PWM_SUBSCRIBE_SEQSTART */ 5165 /* Description: Description collection: Subscribe configuration for task SEQSTART[n] */ 5166 5167 /* Bit 31 : */ 5168 #define PWM_SUBSCRIBE_SEQSTART_EN_Pos (31UL) /*!< Position of EN field. */ 5169 #define PWM_SUBSCRIBE_SEQSTART_EN_Msk (0x1UL << PWM_SUBSCRIBE_SEQSTART_EN_Pos) /*!< Bit mask of EN field. */ 5170 #define PWM_SUBSCRIBE_SEQSTART_EN_Disabled (0UL) /*!< Disable subscription */ 5171 #define PWM_SUBSCRIBE_SEQSTART_EN_Enabled (1UL) /*!< Enable subscription */ 5172 5173 /* Bits 7..0 : DPPI channel that task SEQSTART[n] will subscribe to */ 5174 #define PWM_SUBSCRIBE_SEQSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5175 #define PWM_SUBSCRIBE_SEQSTART_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_SEQSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5176 5177 /* Register: PWM_SUBSCRIBE_NEXTSTEP */ 5178 /* Description: Subscribe configuration for task NEXTSTEP */ 5179 5180 /* Bit 31 : */ 5181 #define PWM_SUBSCRIBE_NEXTSTEP_EN_Pos (31UL) /*!< Position of EN field. */ 5182 #define PWM_SUBSCRIBE_NEXTSTEP_EN_Msk (0x1UL << PWM_SUBSCRIBE_NEXTSTEP_EN_Pos) /*!< Bit mask of EN field. */ 5183 #define PWM_SUBSCRIBE_NEXTSTEP_EN_Disabled (0UL) /*!< Disable subscription */ 5184 #define PWM_SUBSCRIBE_NEXTSTEP_EN_Enabled (1UL) /*!< Enable subscription */ 5185 5186 /* Bits 7..0 : DPPI channel that task NEXTSTEP will subscribe to */ 5187 #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5188 #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5189 5190 /* Register: PWM_EVENTS_STOPPED */ 5191 /* Description: Response to STOP task, emitted when PWM pulses are no longer generated */ 5192 5193 /* Bit 0 : Response to STOP task, emitted when PWM pulses are no longer generated */ 5194 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ 5195 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ 5196 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ 5197 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ 5198 5199 /* Register: PWM_EVENTS_SEQSTARTED */ 5200 /* Description: Description collection: First PWM period started on sequence n */ 5201 5202 /* Bit 0 : First PWM period started on sequence n */ 5203 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field. */ 5204 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of EVENTS_SEQSTARTED field. */ 5205 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_NotGenerated (0UL) /*!< Event not generated */ 5206 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (1UL) /*!< Event generated */ 5207 5208 /* Register: PWM_EVENTS_SEQEND */ 5209 /* Description: Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ 5210 5211 /* Bit 0 : Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ 5212 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL) /*!< Position of EVENTS_SEQEND field. */ 5213 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos) /*!< Bit mask of EVENTS_SEQEND field. */ 5214 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_NotGenerated (0UL) /*!< Event not generated */ 5215 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (1UL) /*!< Event generated */ 5216 5217 /* Register: PWM_EVENTS_PWMPERIODEND */ 5218 /* Description: Emitted at the end of each PWM period */ 5219 5220 /* Bit 0 : Emitted at the end of each PWM period */ 5221 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field. */ 5222 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit mask of EVENTS_PWMPERIODEND field. */ 5223 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0UL) /*!< Event not generated */ 5224 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (1UL) /*!< Event generated */ 5225 5226 /* Register: PWM_EVENTS_LOOPSDONE */ 5227 /* Description: Concatenated sequences have been played the amount of times defined in LOOP.CNT */ 5228 5229 /* Bit 0 : Concatenated sequences have been played the amount of times defined in LOOP.CNT */ 5230 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL) /*!< Position of EVENTS_LOOPSDONE field. */ 5231 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos) /*!< Bit mask of EVENTS_LOOPSDONE field. */ 5232 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_NotGenerated (0UL) /*!< Event not generated */ 5233 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (1UL) /*!< Event generated */ 5234 5235 /* Register: PWM_PUBLISH_STOPPED */ 5236 /* Description: Publish configuration for event STOPPED */ 5237 5238 /* Bit 31 : */ 5239 #define PWM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ 5240 #define PWM_PUBLISH_STOPPED_EN_Msk (0x1UL << PWM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ 5241 #define PWM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ 5242 #define PWM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ 5243 5244 /* Bits 7..0 : DPPI channel that event STOPPED will publish to */ 5245 #define PWM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5246 #define PWM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << PWM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5247 5248 /* Register: PWM_PUBLISH_SEQSTARTED */ 5249 /* Description: Description collection: Publish configuration for event SEQSTARTED[n] */ 5250 5251 /* Bit 31 : */ 5252 #define PWM_PUBLISH_SEQSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ 5253 #define PWM_PUBLISH_SEQSTARTED_EN_Msk (0x1UL << PWM_PUBLISH_SEQSTARTED_EN_Pos) /*!< Bit mask of EN field. */ 5254 #define PWM_PUBLISH_SEQSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ 5255 #define PWM_PUBLISH_SEQSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ 5256 5257 /* Bits 7..0 : DPPI channel that event SEQSTARTED[n] will publish to */ 5258 #define PWM_PUBLISH_SEQSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5259 #define PWM_PUBLISH_SEQSTARTED_CHIDX_Msk (0xFFUL << PWM_PUBLISH_SEQSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5260 5261 /* Register: PWM_PUBLISH_SEQEND */ 5262 /* Description: Description collection: Publish configuration for event SEQEND[n] */ 5263 5264 /* Bit 31 : */ 5265 #define PWM_PUBLISH_SEQEND_EN_Pos (31UL) /*!< Position of EN field. */ 5266 #define PWM_PUBLISH_SEQEND_EN_Msk (0x1UL << PWM_PUBLISH_SEQEND_EN_Pos) /*!< Bit mask of EN field. */ 5267 #define PWM_PUBLISH_SEQEND_EN_Disabled (0UL) /*!< Disable publishing */ 5268 #define PWM_PUBLISH_SEQEND_EN_Enabled (1UL) /*!< Enable publishing */ 5269 5270 /* Bits 7..0 : DPPI channel that event SEQEND[n] will publish to */ 5271 #define PWM_PUBLISH_SEQEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5272 #define PWM_PUBLISH_SEQEND_CHIDX_Msk (0xFFUL << PWM_PUBLISH_SEQEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5273 5274 /* Register: PWM_PUBLISH_PWMPERIODEND */ 5275 /* Description: Publish configuration for event PWMPERIODEND */ 5276 5277 /* Bit 31 : */ 5278 #define PWM_PUBLISH_PWMPERIODEND_EN_Pos (31UL) /*!< Position of EN field. */ 5279 #define PWM_PUBLISH_PWMPERIODEND_EN_Msk (0x1UL << PWM_PUBLISH_PWMPERIODEND_EN_Pos) /*!< Bit mask of EN field. */ 5280 #define PWM_PUBLISH_PWMPERIODEND_EN_Disabled (0UL) /*!< Disable publishing */ 5281 #define PWM_PUBLISH_PWMPERIODEND_EN_Enabled (1UL) /*!< Enable publishing */ 5282 5283 /* Bits 7..0 : DPPI channel that event PWMPERIODEND will publish to */ 5284 #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5285 #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Msk (0xFFUL << PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5286 5287 /* Register: PWM_PUBLISH_LOOPSDONE */ 5288 /* Description: Publish configuration for event LOOPSDONE */ 5289 5290 /* Bit 31 : */ 5291 #define PWM_PUBLISH_LOOPSDONE_EN_Pos (31UL) /*!< Position of EN field. */ 5292 #define PWM_PUBLISH_LOOPSDONE_EN_Msk (0x1UL << PWM_PUBLISH_LOOPSDONE_EN_Pos) /*!< Bit mask of EN field. */ 5293 #define PWM_PUBLISH_LOOPSDONE_EN_Disabled (0UL) /*!< Disable publishing */ 5294 #define PWM_PUBLISH_LOOPSDONE_EN_Enabled (1UL) /*!< Enable publishing */ 5295 5296 /* Bits 7..0 : DPPI channel that event LOOPSDONE will publish to */ 5297 #define PWM_PUBLISH_LOOPSDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5298 #define PWM_PUBLISH_LOOPSDONE_CHIDX_Msk (0xFFUL << PWM_PUBLISH_LOOPSDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5299 5300 /* Register: PWM_SHORTS */ 5301 /* Description: Shortcuts between local events and tasks */ 5302 5303 /* Bit 4 : Shortcut between event LOOPSDONE and task STOP */ 5304 #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */ 5305 #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */ 5306 #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */ 5307 #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */ 5308 5309 /* Bit 3 : Shortcut between event LOOPSDONE and task SEQSTART[1] */ 5310 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */ 5311 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */ 5312 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */ 5313 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */ 5314 5315 /* Bit 2 : Shortcut between event LOOPSDONE and task SEQSTART[0] */ 5316 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */ 5317 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */ 5318 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */ 5319 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */ 5320 5321 /* Bit 1 : Shortcut between event SEQEND[1] and task STOP */ 5322 #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */ 5323 #define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */ 5324 #define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */ 5325 #define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */ 5326 5327 /* Bit 0 : Shortcut between event SEQEND[0] and task STOP */ 5328 #define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */ 5329 #define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */ 5330 #define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */ 5331 #define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */ 5332 5333 /* Register: PWM_INTEN */ 5334 /* Description: Enable or disable interrupt */ 5335 5336 /* Bit 7 : Enable or disable interrupt for event LOOPSDONE */ 5337 #define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ 5338 #define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ 5339 #define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */ 5340 #define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */ 5341 5342 /* Bit 6 : Enable or disable interrupt for event PWMPERIODEND */ 5343 #define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ 5344 #define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ 5345 #define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */ 5346 #define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */ 5347 5348 /* Bit 5 : Enable or disable interrupt for event SEQEND[1] */ 5349 #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ 5350 #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ 5351 #define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */ 5352 #define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */ 5353 5354 /* Bit 4 : Enable or disable interrupt for event SEQEND[0] */ 5355 #define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ 5356 #define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ 5357 #define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */ 5358 #define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */ 5359 5360 /* Bit 3 : Enable or disable interrupt for event SEQSTARTED[1] */ 5361 #define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ 5362 #define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ 5363 #define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */ 5364 #define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */ 5365 5366 /* Bit 2 : Enable or disable interrupt for event SEQSTARTED[0] */ 5367 #define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ 5368 #define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ 5369 #define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */ 5370 #define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */ 5371 5372 /* Bit 1 : Enable or disable interrupt for event STOPPED */ 5373 #define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 5374 #define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 5375 #define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ 5376 #define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ 5377 5378 /* Register: PWM_INTENSET */ 5379 /* Description: Enable interrupt */ 5380 5381 /* Bit 7 : Write '1' to enable interrupt for event LOOPSDONE */ 5382 #define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ 5383 #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ 5384 #define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ 5385 #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ 5386 #define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */ 5387 5388 /* Bit 6 : Write '1' to enable interrupt for event PWMPERIODEND */ 5389 #define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ 5390 #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ 5391 #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ 5392 #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ 5393 #define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */ 5394 5395 /* Bit 5 : Write '1' to enable interrupt for event SEQEND[1] */ 5396 #define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ 5397 #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ 5398 #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ 5399 #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ 5400 #define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */ 5401 5402 /* Bit 4 : Write '1' to enable interrupt for event SEQEND[0] */ 5403 #define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ 5404 #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ 5405 #define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ 5406 #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ 5407 #define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */ 5408 5409 /* Bit 3 : Write '1' to enable interrupt for event SEQSTARTED[1] */ 5410 #define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ 5411 #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ 5412 #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ 5413 #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ 5414 #define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */ 5415 5416 /* Bit 2 : Write '1' to enable interrupt for event SEQSTARTED[0] */ 5417 #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ 5418 #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ 5419 #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ 5420 #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ 5421 #define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */ 5422 5423 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */ 5424 #define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 5425 #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 5426 #define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 5427 #define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 5428 #define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ 5429 5430 /* Register: PWM_INTENCLR */ 5431 /* Description: Disable interrupt */ 5432 5433 /* Bit 7 : Write '1' to disable interrupt for event LOOPSDONE */ 5434 #define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ 5435 #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ 5436 #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ 5437 #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ 5438 #define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */ 5439 5440 /* Bit 6 : Write '1' to disable interrupt for event PWMPERIODEND */ 5441 #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ 5442 #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ 5443 #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ 5444 #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ 5445 #define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */ 5446 5447 /* Bit 5 : Write '1' to disable interrupt for event SEQEND[1] */ 5448 #define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ 5449 #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ 5450 #define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ 5451 #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ 5452 #define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */ 5453 5454 /* Bit 4 : Write '1' to disable interrupt for event SEQEND[0] */ 5455 #define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ 5456 #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ 5457 #define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ 5458 #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ 5459 #define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */ 5460 5461 /* Bit 3 : Write '1' to disable interrupt for event SEQSTARTED[1] */ 5462 #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ 5463 #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ 5464 #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ 5465 #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ 5466 #define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */ 5467 5468 /* Bit 2 : Write '1' to disable interrupt for event SEQSTARTED[0] */ 5469 #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ 5470 #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ 5471 #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ 5472 #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ 5473 #define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */ 5474 5475 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */ 5476 #define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 5477 #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 5478 #define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 5479 #define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 5480 #define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ 5481 5482 /* Register: PWM_ENABLE */ 5483 /* Description: PWM module enable register */ 5484 5485 /* Bit 0 : Enable or disable PWM module */ 5486 #define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 5487 #define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 5488 #define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */ 5489 #define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ 5490 5491 /* Register: PWM_MODE */ 5492 /* Description: Selects operating mode of the wave counter */ 5493 5494 /* Bit 0 : Selects up mode or up-and-down mode for the counter */ 5495 #define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */ 5496 #define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */ 5497 #define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter, edge-aligned PWM duty cycle */ 5498 #define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter, center-aligned PWM duty cycle */ 5499 5500 /* Register: PWM_COUNTERTOP */ 5501 /* Description: Value up to which the pulse generator counter counts */ 5502 5503 /* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. */ 5504 #define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */ 5505 #define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */ 5506 5507 /* Register: PWM_PRESCALER */ 5508 /* Description: Configuration for PWM_CLK */ 5509 5510 /* Bits 2..0 : Prescaler of PWM_CLK */ 5511 #define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ 5512 #define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ 5513 #define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16 MHz) */ 5514 #define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 (8 MHz) */ 5515 #define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 (4 MHz) */ 5516 #define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 (2 MHz) */ 5517 #define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 (1 MHz) */ 5518 #define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by 32 (500 kHz) */ 5519 #define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by 64 (250 kHz) */ 5520 #define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 (125 kHz) */ 5521 5522 /* Register: PWM_DECODER */ 5523 /* Description: Configuration of the decoder */ 5524 5525 /* Bit 8 : Selects source for advancing the active sequence */ 5526 #define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */ 5527 #define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */ 5528 #define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */ 5529 #define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */ 5530 5531 /* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */ 5532 #define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */ 5533 #define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */ 5534 #define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */ 5535 #define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */ 5536 #define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */ 5537 #define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */ 5538 5539 /* Register: PWM_LOOP */ 5540 /* Description: Number of playbacks of a loop */ 5541 5542 /* Bits 15..0 : Number of playbacks of pattern cycles */ 5543 #define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */ 5544 #define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */ 5545 #define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */ 5546 5547 /* Register: PWM_SEQ_PTR */ 5548 /* Description: Description cluster: Beginning address in RAM of this sequence */ 5549 5550 /* Bits 31..0 : Beginning address in RAM of this sequence */ 5551 #define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 5552 #define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 5553 5554 /* Register: PWM_SEQ_CNT */ 5555 /* Description: Description cluster: Number of values (duty cycles) in this sequence */ 5556 5557 /* Bits 14..0 : Number of values (duty cycles) in this sequence */ 5558 #define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ 5559 #define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ 5560 #define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */ 5561 5562 /* Register: PWM_SEQ_REFRESH */ 5563 /* Description: Description cluster: Number of additional PWM periods between samples loaded into compare register */ 5564 5565 /* Bits 23..0 : Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */ 5566 #define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */ 5567 #define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */ 5568 #define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */ 5569 5570 /* Register: PWM_SEQ_ENDDELAY */ 5571 /* Description: Description cluster: Time added after the sequence */ 5572 5573 /* Bits 23..0 : Time added after the sequence in PWM periods */ 5574 #define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */ 5575 #define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */ 5576 5577 /* Register: PWM_PSEL_OUT */ 5578 /* Description: Description collection: Output pin select for PWM channel n */ 5579 5580 /* Bit 31 : Connection */ 5581 #define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 5582 #define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 5583 #define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */ 5584 #define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */ 5585 5586 /* Bits 4..0 : Pin number */ 5587 #define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */ 5588 #define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */ 5589 5590 5591 /* Peripheral: REGULATORS */ 5592 /* Description: Voltage regulators control 0 */ 5593 5594 /* Register: REGULATORS_SYSTEMOFF */ 5595 /* Description: System OFF register */ 5596 5597 /* Bit 0 : Enable System OFF mode */ 5598 #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */ 5599 #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << REGULATORS_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */ 5600 #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Enable (1UL) /*!< Enable System OFF mode */ 5601 5602 /* Register: REGULATORS_EXTPOFCON */ 5603 /* Description: External power failure warning configuration */ 5604 5605 /* Bit 0 : Enable or disable external power failure warning */ 5606 #define REGULATORS_EXTPOFCON_POF_Pos (0UL) /*!< Position of POF field. */ 5607 #define REGULATORS_EXTPOFCON_POF_Msk (0x1UL << REGULATORS_EXTPOFCON_POF_Pos) /*!< Bit mask of POF field. */ 5608 #define REGULATORS_EXTPOFCON_POF_Disabled (0UL) /*!< Disable */ 5609 #define REGULATORS_EXTPOFCON_POF_Enabled (1UL) /*!< Enable */ 5610 5611 /* Register: REGULATORS_DCDCEN */ 5612 /* Description: Enable DC/DC mode of the main voltage regulator. */ 5613 5614 /* Bit 0 : Enable DC/DC converter */ 5615 #define REGULATORS_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ 5616 #define REGULATORS_DCDCEN_DCDCEN_Msk (0x1UL << REGULATORS_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */ 5617 #define REGULATORS_DCDCEN_DCDCEN_Disabled (0UL) /*!< DC/DC mode is disabled */ 5618 #define REGULATORS_DCDCEN_DCDCEN_Enabled (1UL) /*!< DC/DC mode is enabled */ 5619 5620 5621 /* Peripheral: RTC */ 5622 /* Description: Real-time counter 0 */ 5623 5624 /* Register: RTC_TASKS_START */ 5625 /* Description: Start RTC counter */ 5626 5627 /* Bit 0 : Start RTC counter */ 5628 #define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 5629 #define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 5630 #define RTC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ 5631 5632 /* Register: RTC_TASKS_STOP */ 5633 /* Description: Stop RTC counter */ 5634 5635 /* Bit 0 : Stop RTC counter */ 5636 #define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 5637 #define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 5638 #define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 5639 5640 /* Register: RTC_TASKS_CLEAR */ 5641 /* Description: Clear RTC counter */ 5642 5643 /* Bit 0 : Clear RTC counter */ 5644 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ 5645 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ 5646 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */ 5647 5648 /* Register: RTC_TASKS_TRIGOVRFLW */ 5649 /* Description: Set counter to 0xFFFFF0 */ 5650 5651 /* Bit 0 : Set counter to 0xFFFFF0 */ 5652 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */ 5653 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */ 5654 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL) /*!< Trigger task */ 5655 5656 /* Register: RTC_SUBSCRIBE_START */ 5657 /* Description: Subscribe configuration for task START */ 5658 5659 /* Bit 31 : */ 5660 #define RTC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ 5661 #define RTC_SUBSCRIBE_START_EN_Msk (0x1UL << RTC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ 5662 #define RTC_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ 5663 #define RTC_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ 5664 5665 /* Bits 7..0 : DPPI channel that task START will subscribe to */ 5666 #define RTC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5667 #define RTC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5668 5669 /* Register: RTC_SUBSCRIBE_STOP */ 5670 /* Description: Subscribe configuration for task STOP */ 5671 5672 /* Bit 31 : */ 5673 #define RTC_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 5674 #define RTC_SUBSCRIBE_STOP_EN_Msk (0x1UL << RTC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 5675 #define RTC_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ 5676 #define RTC_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ 5677 5678 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 5679 #define RTC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5680 #define RTC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5681 5682 /* Register: RTC_SUBSCRIBE_CLEAR */ 5683 /* Description: Subscribe configuration for task CLEAR */ 5684 5685 /* Bit 31 : */ 5686 #define RTC_SUBSCRIBE_CLEAR_EN_Pos (31UL) /*!< Position of EN field. */ 5687 #define RTC_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << RTC_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field. */ 5688 #define RTC_SUBSCRIBE_CLEAR_EN_Disabled (0UL) /*!< Disable subscription */ 5689 #define RTC_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */ 5690 5691 /* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */ 5692 #define RTC_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5693 #define RTC_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5694 5695 /* Register: RTC_SUBSCRIBE_TRIGOVRFLW */ 5696 /* Description: Subscribe configuration for task TRIGOVRFLW */ 5697 5698 /* Bit 31 : */ 5699 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos (31UL) /*!< Position of EN field. */ 5700 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Msk (0x1UL << RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos) /*!< Bit mask of EN field. */ 5701 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Disabled (0UL) /*!< Disable subscription */ 5702 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Enabled (1UL) /*!< Enable subscription */ 5703 5704 /* Bits 7..0 : DPPI channel that task TRIGOVRFLW will subscribe to */ 5705 #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5706 #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5707 5708 /* Register: RTC_EVENTS_TICK */ 5709 /* Description: Event on counter increment */ 5710 5711 /* Bit 0 : Event on counter increment */ 5712 #define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */ 5713 #define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */ 5714 #define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0UL) /*!< Event not generated */ 5715 #define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL) /*!< Event generated */ 5716 5717 /* Register: RTC_EVENTS_OVRFLW */ 5718 /* Description: Event on counter overflow */ 5719 5720 /* Bit 0 : Event on counter overflow */ 5721 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */ 5722 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */ 5723 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0UL) /*!< Event not generated */ 5724 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL) /*!< Event generated */ 5725 5726 /* Register: RTC_EVENTS_COMPARE */ 5727 /* Description: Description collection: Compare event on CC[n] match */ 5728 5729 /* Bit 0 : Compare event on CC[n] match */ 5730 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ 5731 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ 5732 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */ 5733 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */ 5734 5735 /* Register: RTC_PUBLISH_TICK */ 5736 /* Description: Publish configuration for event TICK */ 5737 5738 /* Bit 31 : */ 5739 #define RTC_PUBLISH_TICK_EN_Pos (31UL) /*!< Position of EN field. */ 5740 #define RTC_PUBLISH_TICK_EN_Msk (0x1UL << RTC_PUBLISH_TICK_EN_Pos) /*!< Bit mask of EN field. */ 5741 #define RTC_PUBLISH_TICK_EN_Disabled (0UL) /*!< Disable publishing */ 5742 #define RTC_PUBLISH_TICK_EN_Enabled (1UL) /*!< Enable publishing */ 5743 5744 /* Bits 7..0 : DPPI channel that event TICK will publish to */ 5745 #define RTC_PUBLISH_TICK_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5746 #define RTC_PUBLISH_TICK_CHIDX_Msk (0xFFUL << RTC_PUBLISH_TICK_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5747 5748 /* Register: RTC_PUBLISH_OVRFLW */ 5749 /* Description: Publish configuration for event OVRFLW */ 5750 5751 /* Bit 31 : */ 5752 #define RTC_PUBLISH_OVRFLW_EN_Pos (31UL) /*!< Position of EN field. */ 5753 #define RTC_PUBLISH_OVRFLW_EN_Msk (0x1UL << RTC_PUBLISH_OVRFLW_EN_Pos) /*!< Bit mask of EN field. */ 5754 #define RTC_PUBLISH_OVRFLW_EN_Disabled (0UL) /*!< Disable publishing */ 5755 #define RTC_PUBLISH_OVRFLW_EN_Enabled (1UL) /*!< Enable publishing */ 5756 5757 /* Bits 7..0 : DPPI channel that event OVRFLW will publish to */ 5758 #define RTC_PUBLISH_OVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5759 #define RTC_PUBLISH_OVRFLW_CHIDX_Msk (0xFFUL << RTC_PUBLISH_OVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5760 5761 /* Register: RTC_PUBLISH_COMPARE */ 5762 /* Description: Description collection: Publish configuration for event COMPARE[n] */ 5763 5764 /* Bit 31 : */ 5765 #define RTC_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */ 5766 #define RTC_PUBLISH_COMPARE_EN_Msk (0x1UL << RTC_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */ 5767 #define RTC_PUBLISH_COMPARE_EN_Disabled (0UL) /*!< Disable publishing */ 5768 #define RTC_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */ 5769 5770 /* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to */ 5771 #define RTC_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5772 #define RTC_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << RTC_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5773 5774 /* Register: RTC_INTENSET */ 5775 /* Description: Enable interrupt */ 5776 5777 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */ 5778 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 5779 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 5780 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 5781 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 5782 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ 5783 5784 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */ 5785 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 5786 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 5787 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ 5788 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ 5789 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ 5790 5791 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */ 5792 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 5793 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 5794 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ 5795 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ 5796 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ 5797 5798 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ 5799 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 5800 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 5801 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 5802 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 5803 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ 5804 5805 /* Bit 1 : Write '1' to enable interrupt for event OVRFLW */ 5806 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 5807 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 5808 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ 5809 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ 5810 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */ 5811 5812 /* Bit 0 : Write '1' to enable interrupt for event TICK */ 5813 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ 5814 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ 5815 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ 5816 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ 5817 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */ 5818 5819 /* Register: RTC_INTENCLR */ 5820 /* Description: Disable interrupt */ 5821 5822 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */ 5823 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 5824 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 5825 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 5826 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 5827 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ 5828 5829 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */ 5830 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 5831 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 5832 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ 5833 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ 5834 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ 5835 5836 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */ 5837 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 5838 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 5839 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ 5840 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ 5841 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ 5842 5843 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ 5844 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 5845 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 5846 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 5847 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 5848 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ 5849 5850 /* Bit 1 : Write '1' to disable interrupt for event OVRFLW */ 5851 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 5852 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 5853 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ 5854 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ 5855 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ 5856 5857 /* Bit 0 : Write '1' to disable interrupt for event TICK */ 5858 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ 5859 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ 5860 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ 5861 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ 5862 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */ 5863 5864 /* Register: RTC_EVTEN */ 5865 /* Description: Enable or disable event routing */ 5866 5867 /* Bit 19 : Enable or disable event routing for event COMPARE[3] */ 5868 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 5869 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 5870 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */ 5871 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */ 5872 5873 /* Bit 18 : Enable or disable event routing for event COMPARE[2] */ 5874 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 5875 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 5876 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */ 5877 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */ 5878 5879 /* Bit 17 : Enable or disable event routing for event COMPARE[1] */ 5880 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 5881 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 5882 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */ 5883 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */ 5884 5885 /* Bit 16 : Enable or disable event routing for event COMPARE[0] */ 5886 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 5887 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 5888 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */ 5889 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */ 5890 5891 /* Bit 1 : Enable or disable event routing for event OVRFLW */ 5892 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 5893 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 5894 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */ 5895 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */ 5896 5897 /* Bit 0 : Enable or disable event routing for event TICK */ 5898 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ 5899 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ 5900 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */ 5901 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */ 5902 5903 /* Register: RTC_EVTENSET */ 5904 /* Description: Enable event routing */ 5905 5906 /* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */ 5907 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 5908 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 5909 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 5910 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 5911 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */ 5912 5913 /* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */ 5914 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 5915 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 5916 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ 5917 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ 5918 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */ 5919 5920 /* Bit 17 : Write '1' to enable event routing for event COMPARE[1] */ 5921 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 5922 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 5923 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ 5924 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ 5925 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */ 5926 5927 /* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */ 5928 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 5929 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 5930 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 5931 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 5932 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */ 5933 5934 /* Bit 1 : Write '1' to enable event routing for event OVRFLW */ 5935 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 5936 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 5937 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ 5938 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ 5939 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */ 5940 5941 /* Bit 0 : Write '1' to enable event routing for event TICK */ 5942 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ 5943 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ 5944 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ 5945 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ 5946 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */ 5947 5948 /* Register: RTC_EVTENCLR */ 5949 /* Description: Disable event routing */ 5950 5951 /* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */ 5952 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 5953 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 5954 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 5955 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 5956 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ 5957 5958 /* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */ 5959 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 5960 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 5961 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ 5962 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ 5963 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ 5964 5965 /* Bit 17 : Write '1' to disable event routing for event COMPARE[1] */ 5966 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 5967 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 5968 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ 5969 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ 5970 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ 5971 5972 /* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */ 5973 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 5974 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 5975 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 5976 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 5977 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ 5978 5979 /* Bit 1 : Write '1' to disable event routing for event OVRFLW */ 5980 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 5981 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 5982 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ 5983 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ 5984 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ 5985 5986 /* Bit 0 : Write '1' to disable event routing for event TICK */ 5987 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ 5988 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ 5989 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ 5990 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ 5991 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */ 5992 5993 /* Register: RTC_COUNTER */ 5994 /* Description: Current counter value */ 5995 5996 /* Bits 23..0 : Counter value */ 5997 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */ 5998 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ 5999 6000 /* Register: RTC_PRESCALER */ 6001 /* Description: 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. */ 6002 6003 /* Bits 11..0 : Prescaler value */ 6004 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ 6005 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ 6006 6007 /* Register: RTC_CC */ 6008 /* Description: Description collection: Compare register n */ 6009 6010 /* Bits 23..0 : Compare value */ 6011 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ 6012 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */ 6013 6014 6015 /* Peripheral: SAADC */ 6016 /* Description: Analog to Digital Converter 0 */ 6017 6018 /* Register: SAADC_TASKS_START */ 6019 /* Description: Start the ADC and prepare the result buffer in RAM */ 6020 6021 /* Bit 0 : Start the ADC and prepare the result buffer in RAM */ 6022 #define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 6023 #define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 6024 #define SAADC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ 6025 6026 /* Register: SAADC_TASKS_SAMPLE */ 6027 /* Description: Take one ADC sample, if scan is enabled all channels are sampled */ 6028 6029 /* Bit 0 : Take one ADC sample, if scan is enabled all channels are sampled */ 6030 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ 6031 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ 6032 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */ 6033 6034 /* Register: SAADC_TASKS_STOP */ 6035 /* Description: Stop the ADC and terminate any on-going conversion */ 6036 6037 /* Bit 0 : Stop the ADC and terminate any on-going conversion */ 6038 #define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 6039 #define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 6040 #define SAADC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 6041 6042 /* Register: SAADC_TASKS_CALIBRATEOFFSET */ 6043 /* Description: Starts offset auto-calibration */ 6044 6045 /* Bit 0 : Starts offset auto-calibration */ 6046 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field. */ 6047 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) /*!< Bit mask of TASKS_CALIBRATEOFFSET field. */ 6048 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (1UL) /*!< Trigger task */ 6049 6050 /* Register: SAADC_SUBSCRIBE_START */ 6051 /* Description: Subscribe configuration for task START */ 6052 6053 /* Bit 31 : */ 6054 #define SAADC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ 6055 #define SAADC_SUBSCRIBE_START_EN_Msk (0x1UL << SAADC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ 6056 #define SAADC_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ 6057 #define SAADC_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ 6058 6059 /* Bits 7..0 : DPPI channel that task START will subscribe to */ 6060 #define SAADC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 6061 #define SAADC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 6062 6063 /* Register: SAADC_SUBSCRIBE_SAMPLE */ 6064 /* Description: Subscribe configuration for task SAMPLE */ 6065 6066 /* Bit 31 : */ 6067 #define SAADC_SUBSCRIBE_SAMPLE_EN_Pos (31UL) /*!< Position of EN field. */ 6068 #define SAADC_SUBSCRIBE_SAMPLE_EN_Msk (0x1UL << SAADC_SUBSCRIBE_SAMPLE_EN_Pos) /*!< Bit mask of EN field. */ 6069 #define SAADC_SUBSCRIBE_SAMPLE_EN_Disabled (0UL) /*!< Disable subscription */ 6070 #define SAADC_SUBSCRIBE_SAMPLE_EN_Enabled (1UL) /*!< Enable subscription */ 6071 6072 /* Bits 7..0 : DPPI channel that task SAMPLE will subscribe to */ 6073 #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 6074 #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 6075 6076 /* Register: SAADC_SUBSCRIBE_STOP */ 6077 /* Description: Subscribe configuration for task STOP */ 6078 6079 /* Bit 31 : */ 6080 #define SAADC_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 6081 #define SAADC_SUBSCRIBE_STOP_EN_Msk (0x1UL << SAADC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 6082 #define SAADC_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ 6083 #define SAADC_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ 6084 6085 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 6086 #define SAADC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 6087 #define SAADC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 6088 6089 /* Register: SAADC_SUBSCRIBE_CALIBRATEOFFSET */ 6090 /* Description: Subscribe configuration for task CALIBRATEOFFSET */ 6091 6092 /* Bit 31 : */ 6093 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos (31UL) /*!< Position of EN field. */ 6094 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Msk (0x1UL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos) /*!< Bit mask of EN field. */ 6095 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Disabled (0UL) /*!< Disable subscription */ 6096 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Enabled (1UL) /*!< Enable subscription */ 6097 6098 /* Bits 7..0 : DPPI channel that task CALIBRATEOFFSET will subscribe to */ 6099 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 6100 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 6101 6102 /* Register: SAADC_EVENTS_STARTED */ 6103 /* Description: The ADC has started */ 6104 6105 /* Bit 0 : The ADC has started */ 6106 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ 6107 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ 6108 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ 6109 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ 6110 6111 /* Register: SAADC_EVENTS_END */ 6112 /* Description: The ADC has filled up the Result buffer */ 6113 6114 /* Bit 0 : The ADC has filled up the Result buffer */ 6115 #define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ 6116 #define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ 6117 #define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ 6118 #define SAADC_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ 6119 6120 /* Register: SAADC_EVENTS_DONE */ 6121 /* Description: A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */ 6122 6123 /* Bit 0 : A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */ 6124 #define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ 6125 #define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ 6126 #define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */ 6127 #define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */ 6128 6129 /* Register: SAADC_EVENTS_RESULTDONE */ 6130 /* Description: A result is ready to get transferred to RAM. */ 6131 6132 /* Bit 0 : A result is ready to get transferred to RAM. */ 6133 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */ 6134 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask of EVENTS_RESULTDONE field. */ 6135 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0UL) /*!< Event not generated */ 6136 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (1UL) /*!< Event generated */ 6137 6138 /* Register: SAADC_EVENTS_CALIBRATEDONE */ 6139 /* Description: Calibration is complete */ 6140 6141 /* Bit 0 : Calibration is complete */ 6142 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field. */ 6143 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) /*!< Bit mask of EVENTS_CALIBRATEDONE field. */ 6144 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0UL) /*!< Event not generated */ 6145 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (1UL) /*!< Event generated */ 6146 6147 /* Register: SAADC_EVENTS_STOPPED */ 6148 /* Description: The ADC has stopped */ 6149 6150 /* Bit 0 : The ADC has stopped */ 6151 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ 6152 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ 6153 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ 6154 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ 6155 6156 /* Register: SAADC_EVENTS_CH_LIMITH */ 6157 /* Description: Description cluster: Last results is equal or above CH[n].LIMIT.HIGH */ 6158 6159 /* Bit 0 : Last results is equal or above CH[n].LIMIT.HIGH */ 6160 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */ 6161 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */ 6162 #define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0UL) /*!< Event not generated */ 6163 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (1UL) /*!< Event generated */ 6164 6165 /* Register: SAADC_EVENTS_CH_LIMITL */ 6166 /* Description: Description cluster: Last results is equal or below CH[n].LIMIT.LOW */ 6167 6168 /* Bit 0 : Last results is equal or below CH[n].LIMIT.LOW */ 6169 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */ 6170 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field. */ 6171 #define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0UL) /*!< Event not generated */ 6172 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (1UL) /*!< Event generated */ 6173 6174 /* Register: SAADC_PUBLISH_STARTED */ 6175 /* Description: Publish configuration for event STARTED */ 6176 6177 /* Bit 31 : */ 6178 #define SAADC_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */ 6179 #define SAADC_PUBLISH_STARTED_EN_Msk (0x1UL << SAADC_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */ 6180 #define SAADC_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */ 6181 #define SAADC_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */ 6182 6183 /* Bits 7..0 : DPPI channel that event STARTED will publish to */ 6184 #define SAADC_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 6185 #define SAADC_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 6186 6187 /* Register: SAADC_PUBLISH_END */ 6188 /* Description: Publish configuration for event END */ 6189 6190 /* Bit 31 : */ 6191 #define SAADC_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ 6192 #define SAADC_PUBLISH_END_EN_Msk (0x1UL << SAADC_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ 6193 #define SAADC_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */ 6194 #define SAADC_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */ 6195 6196 /* Bits 7..0 : DPPI channel that event END will publish to */ 6197 #define SAADC_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 6198 #define SAADC_PUBLISH_END_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 6199 6200 /* Register: SAADC_PUBLISH_DONE */ 6201 /* Description: Publish configuration for event DONE */ 6202 6203 /* Bit 31 : */ 6204 #define SAADC_PUBLISH_DONE_EN_Pos (31UL) /*!< Position of EN field. */ 6205 #define SAADC_PUBLISH_DONE_EN_Msk (0x1UL << SAADC_PUBLISH_DONE_EN_Pos) /*!< Bit mask of EN field. */ 6206 #define SAADC_PUBLISH_DONE_EN_Disabled (0UL) /*!< Disable publishing */ 6207 #define SAADC_PUBLISH_DONE_EN_Enabled (1UL) /*!< Enable publishing */ 6208 6209 /* Bits 7..0 : DPPI channel that event DONE will publish to */ 6210 #define SAADC_PUBLISH_DONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 6211 #define SAADC_PUBLISH_DONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_DONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 6212 6213 /* Register: SAADC_PUBLISH_RESULTDONE */ 6214 /* Description: Publish configuration for event RESULTDONE */ 6215 6216 /* Bit 31 : */ 6217 #define SAADC_PUBLISH_RESULTDONE_EN_Pos (31UL) /*!< Position of EN field. */ 6218 #define SAADC_PUBLISH_RESULTDONE_EN_Msk (0x1UL << SAADC_PUBLISH_RESULTDONE_EN_Pos) /*!< Bit mask of EN field. */ 6219 #define SAADC_PUBLISH_RESULTDONE_EN_Disabled (0UL) /*!< Disable publishing */ 6220 #define SAADC_PUBLISH_RESULTDONE_EN_Enabled (1UL) /*!< Enable publishing */ 6221 6222 /* Bits 7..0 : DPPI channel that event RESULTDONE will publish to */ 6223 #define SAADC_PUBLISH_RESULTDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 6224 #define SAADC_PUBLISH_RESULTDONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_RESULTDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 6225 6226 /* Register: SAADC_PUBLISH_CALIBRATEDONE */ 6227 /* Description: Publish configuration for event CALIBRATEDONE */ 6228 6229 /* Bit 31 : */ 6230 #define SAADC_PUBLISH_CALIBRATEDONE_EN_Pos (31UL) /*!< Position of EN field. */ 6231 #define SAADC_PUBLISH_CALIBRATEDONE_EN_Msk (0x1UL << SAADC_PUBLISH_CALIBRATEDONE_EN_Pos) /*!< Bit mask of EN field. */ 6232 #define SAADC_PUBLISH_CALIBRATEDONE_EN_Disabled (0UL) /*!< Disable publishing */ 6233 #define SAADC_PUBLISH_CALIBRATEDONE_EN_Enabled (1UL) /*!< Enable publishing */ 6234 6235 /* Bits 7..0 : DPPI channel that event CALIBRATEDONE will publish to */ 6236 #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 6237 #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 6238 6239 /* Register: SAADC_PUBLISH_STOPPED */ 6240 /* Description: Publish configuration for event STOPPED */ 6241 6242 /* Bit 31 : */ 6243 #define SAADC_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ 6244 #define SAADC_PUBLISH_STOPPED_EN_Msk (0x1UL << SAADC_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ 6245 #define SAADC_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ 6246 #define SAADC_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ 6247 6248 /* Bits 7..0 : DPPI channel that event STOPPED will publish to */ 6249 #define SAADC_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 6250 #define SAADC_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 6251 6252 /* Register: SAADC_PUBLISH_CH_LIMITH */ 6253 /* Description: Description cluster: Publish configuration for event CH[n].LIMITH */ 6254 6255 /* Bit 31 : */ 6256 #define SAADC_PUBLISH_CH_LIMITH_EN_Pos (31UL) /*!< Position of EN field. */ 6257 #define SAADC_PUBLISH_CH_LIMITH_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITH_EN_Pos) /*!< Bit mask of EN field. */ 6258 #define SAADC_PUBLISH_CH_LIMITH_EN_Disabled (0UL) /*!< Disable publishing */ 6259 #define SAADC_PUBLISH_CH_LIMITH_EN_Enabled (1UL) /*!< Enable publishing */ 6260 6261 /* Bits 7..0 : DPPI channel that event CH[n].LIMITH will publish to */ 6262 #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 6263 #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 6264 6265 /* Register: SAADC_PUBLISH_CH_LIMITL */ 6266 /* Description: Description cluster: Publish configuration for event CH[n].LIMITL */ 6267 6268 /* Bit 31 : */ 6269 #define SAADC_PUBLISH_CH_LIMITL_EN_Pos (31UL) /*!< Position of EN field. */ 6270 #define SAADC_PUBLISH_CH_LIMITL_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITL_EN_Pos) /*!< Bit mask of EN field. */ 6271 #define SAADC_PUBLISH_CH_LIMITL_EN_Disabled (0UL) /*!< Disable publishing */ 6272 #define SAADC_PUBLISH_CH_LIMITL_EN_Enabled (1UL) /*!< Enable publishing */ 6273 6274 /* Bits 7..0 : DPPI channel that event CH[n].LIMITL will publish to */ 6275 #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 6276 #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 6277 6278 /* Register: SAADC_INTEN */ 6279 /* Description: Enable or disable interrupt */ 6280 6281 /* Bit 21 : Enable or disable interrupt for event CH7LIMITL */ 6282 #define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ 6283 #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ 6284 #define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */ 6285 #define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */ 6286 6287 /* Bit 20 : Enable or disable interrupt for event CH7LIMITH */ 6288 #define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ 6289 #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ 6290 #define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */ 6291 #define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */ 6292 6293 /* Bit 19 : Enable or disable interrupt for event CH6LIMITL */ 6294 #define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ 6295 #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ 6296 #define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */ 6297 #define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */ 6298 6299 /* Bit 18 : Enable or disable interrupt for event CH6LIMITH */ 6300 #define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ 6301 #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ 6302 #define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */ 6303 #define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */ 6304 6305 /* Bit 17 : Enable or disable interrupt for event CH5LIMITL */ 6306 #define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ 6307 #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ 6308 #define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */ 6309 #define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */ 6310 6311 /* Bit 16 : Enable or disable interrupt for event CH5LIMITH */ 6312 #define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ 6313 #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ 6314 #define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */ 6315 #define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */ 6316 6317 /* Bit 15 : Enable or disable interrupt for event CH4LIMITL */ 6318 #define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ 6319 #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ 6320 #define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */ 6321 #define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */ 6322 6323 /* Bit 14 : Enable or disable interrupt for event CH4LIMITH */ 6324 #define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ 6325 #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ 6326 #define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */ 6327 #define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */ 6328 6329 /* Bit 13 : Enable or disable interrupt for event CH3LIMITL */ 6330 #define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ 6331 #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ 6332 #define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */ 6333 #define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */ 6334 6335 /* Bit 12 : Enable or disable interrupt for event CH3LIMITH */ 6336 #define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ 6337 #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ 6338 #define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */ 6339 #define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */ 6340 6341 /* Bit 11 : Enable or disable interrupt for event CH2LIMITL */ 6342 #define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ 6343 #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ 6344 #define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */ 6345 #define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */ 6346 6347 /* Bit 10 : Enable or disable interrupt for event CH2LIMITH */ 6348 #define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ 6349 #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ 6350 #define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */ 6351 #define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */ 6352 6353 /* Bit 9 : Enable or disable interrupt for event CH1LIMITL */ 6354 #define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ 6355 #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ 6356 #define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */ 6357 #define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */ 6358 6359 /* Bit 8 : Enable or disable interrupt for event CH1LIMITH */ 6360 #define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ 6361 #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ 6362 #define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */ 6363 #define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */ 6364 6365 /* Bit 7 : Enable or disable interrupt for event CH0LIMITL */ 6366 #define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ 6367 #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ 6368 #define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */ 6369 #define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */ 6370 6371 /* Bit 6 : Enable or disable interrupt for event CH0LIMITH */ 6372 #define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ 6373 #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ 6374 #define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */ 6375 #define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */ 6376 6377 /* Bit 5 : Enable or disable interrupt for event STOPPED */ 6378 #define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ 6379 #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 6380 #define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ 6381 #define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ 6382 6383 /* Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */ 6384 #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ 6385 #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ 6386 #define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */ 6387 #define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */ 6388 6389 /* Bit 3 : Enable or disable interrupt for event RESULTDONE */ 6390 #define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ 6391 #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ 6392 #define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */ 6393 #define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */ 6394 6395 /* Bit 2 : Enable or disable interrupt for event DONE */ 6396 #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */ 6397 #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */ 6398 #define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */ 6399 #define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */ 6400 6401 /* Bit 1 : Enable or disable interrupt for event END */ 6402 #define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */ 6403 #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */ 6404 #define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */ 6405 #define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */ 6406 6407 /* Bit 0 : Enable or disable interrupt for event STARTED */ 6408 #define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ 6409 #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ 6410 #define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */ 6411 #define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */ 6412 6413 /* Register: SAADC_INTENSET */ 6414 /* Description: Enable interrupt */ 6415 6416 /* Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */ 6417 #define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ 6418 #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ 6419 #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6420 #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6421 #define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */ 6422 6423 /* Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */ 6424 #define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ 6425 #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ 6426 #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6427 #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6428 #define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */ 6429 6430 /* Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */ 6431 #define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ 6432 #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ 6433 #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6434 #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6435 #define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */ 6436 6437 /* Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */ 6438 #define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ 6439 #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ 6440 #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6441 #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6442 #define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */ 6443 6444 /* Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */ 6445 #define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ 6446 #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ 6447 #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6448 #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6449 #define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */ 6450 6451 /* Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */ 6452 #define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ 6453 #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ 6454 #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6455 #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6456 #define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */ 6457 6458 /* Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */ 6459 #define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ 6460 #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ 6461 #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6462 #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6463 #define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */ 6464 6465 /* Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */ 6466 #define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ 6467 #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ 6468 #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6469 #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6470 #define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */ 6471 6472 /* Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */ 6473 #define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ 6474 #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ 6475 #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6476 #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6477 #define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */ 6478 6479 /* Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */ 6480 #define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ 6481 #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ 6482 #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6483 #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6484 #define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */ 6485 6486 /* Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */ 6487 #define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ 6488 #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ 6489 #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6490 #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6491 #define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */ 6492 6493 /* Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */ 6494 #define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ 6495 #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ 6496 #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6497 #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6498 #define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */ 6499 6500 /* Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */ 6501 #define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ 6502 #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ 6503 #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6504 #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6505 #define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */ 6506 6507 /* Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */ 6508 #define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ 6509 #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ 6510 #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6511 #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6512 #define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */ 6513 6514 /* Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */ 6515 #define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ 6516 #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ 6517 #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6518 #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6519 #define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */ 6520 6521 /* Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */ 6522 #define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ 6523 #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ 6524 #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6525 #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6526 #define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */ 6527 6528 /* Bit 5 : Write '1' to enable interrupt for event STOPPED */ 6529 #define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ 6530 #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 6531 #define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 6532 #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 6533 #define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ 6534 6535 /* Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */ 6536 #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ 6537 #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ 6538 #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ 6539 #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ 6540 #define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */ 6541 6542 /* Bit 3 : Write '1' to enable interrupt for event RESULTDONE */ 6543 #define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ 6544 #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ 6545 #define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ 6546 #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ 6547 #define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */ 6548 6549 /* Bit 2 : Write '1' to enable interrupt for event DONE */ 6550 #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */ 6551 #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ 6552 #define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ 6553 #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ 6554 #define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */ 6555 6556 /* Bit 1 : Write '1' to enable interrupt for event END */ 6557 #define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */ 6558 #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ 6559 #define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ 6560 #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ 6561 #define SAADC_INTENSET_END_Set (1UL) /*!< Enable */ 6562 6563 /* Bit 0 : Write '1' to enable interrupt for event STARTED */ 6564 #define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ 6565 #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ 6566 #define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ 6567 #define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ 6568 #define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */ 6569 6570 /* Register: SAADC_INTENCLR */ 6571 /* Description: Disable interrupt */ 6572 6573 /* Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */ 6574 #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ 6575 #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ 6576 #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6577 #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6578 #define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */ 6579 6580 /* Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */ 6581 #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ 6582 #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ 6583 #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6584 #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6585 #define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */ 6586 6587 /* Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */ 6588 #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ 6589 #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ 6590 #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6591 #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6592 #define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */ 6593 6594 /* Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */ 6595 #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ 6596 #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ 6597 #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6598 #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6599 #define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */ 6600 6601 /* Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */ 6602 #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ 6603 #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ 6604 #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6605 #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6606 #define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */ 6607 6608 /* Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */ 6609 #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ 6610 #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ 6611 #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6612 #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6613 #define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */ 6614 6615 /* Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */ 6616 #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ 6617 #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ 6618 #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6619 #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6620 #define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */ 6621 6622 /* Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */ 6623 #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ 6624 #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ 6625 #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6626 #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6627 #define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */ 6628 6629 /* Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */ 6630 #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ 6631 #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ 6632 #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6633 #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6634 #define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */ 6635 6636 /* Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */ 6637 #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ 6638 #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ 6639 #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6640 #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6641 #define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */ 6642 6643 /* Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */ 6644 #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ 6645 #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ 6646 #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6647 #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6648 #define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */ 6649 6650 /* Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */ 6651 #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ 6652 #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ 6653 #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6654 #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6655 #define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */ 6656 6657 /* Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */ 6658 #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ 6659 #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ 6660 #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6661 #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6662 #define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */ 6663 6664 /* Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */ 6665 #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ 6666 #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ 6667 #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6668 #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6669 #define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */ 6670 6671 /* Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */ 6672 #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ 6673 #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ 6674 #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6675 #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6676 #define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */ 6677 6678 /* Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */ 6679 #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ 6680 #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ 6681 #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6682 #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6683 #define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */ 6684 6685 /* Bit 5 : Write '1' to disable interrupt for event STOPPED */ 6686 #define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ 6687 #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 6688 #define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 6689 #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 6690 #define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ 6691 6692 /* Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */ 6693 #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ 6694 #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ 6695 #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ 6696 #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ 6697 #define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */ 6698 6699 /* Bit 3 : Write '1' to disable interrupt for event RESULTDONE */ 6700 #define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ 6701 #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ 6702 #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ 6703 #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ 6704 #define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */ 6705 6706 /* Bit 2 : Write '1' to disable interrupt for event DONE */ 6707 #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */ 6708 #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ 6709 #define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ 6710 #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ 6711 #define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */ 6712 6713 /* Bit 1 : Write '1' to disable interrupt for event END */ 6714 #define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ 6715 #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 6716 #define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ 6717 #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ 6718 #define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */ 6719 6720 /* Bit 0 : Write '1' to disable interrupt for event STARTED */ 6721 #define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ 6722 #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ 6723 #define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ 6724 #define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ 6725 #define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ 6726 6727 /* Register: SAADC_STATUS */ 6728 /* Description: Status */ 6729 6730 /* Bit 0 : Status */ 6731 #define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 6732 #define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ 6733 #define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */ 6734 #define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Single conversion in progress. */ 6735 6736 /* Register: SAADC_ENABLE */ 6737 /* Description: Enable or disable ADC */ 6738 6739 /* Bit 0 : Enable or disable ADC */ 6740 #define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 6741 #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 6742 #define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */ 6743 #define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */ 6744 6745 /* Register: SAADC_CH_PSELP */ 6746 /* Description: Description cluster: Input positive pin selection for CH[n] */ 6747 6748 /* Bits 4..0 : Analog positive input channel */ 6749 #define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */ 6750 #define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */ 6751 #define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */ 6752 #define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */ 6753 #define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */ 6754 #define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */ 6755 #define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */ 6756 #define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */ 6757 #define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */ 6758 #define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */ 6759 #define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */ 6760 #define SAADC_CH_PSELP_PSELP_VDDGPIO (9UL) /*!< VDD_GPIO */ 6761 6762 /* Register: SAADC_CH_PSELN */ 6763 /* Description: Description cluster: Input negative pin selection for CH[n] */ 6764 6765 /* Bits 4..0 : Analog negative input, enables differential channel */ 6766 #define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */ 6767 #define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */ 6768 #define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */ 6769 #define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */ 6770 #define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */ 6771 #define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */ 6772 #define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */ 6773 #define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */ 6774 #define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */ 6775 #define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */ 6776 #define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */ 6777 #define SAADC_CH_PSELN_PSELN_VDD_GPIO (9UL) /*!< VDD_GPIO */ 6778 6779 /* Register: SAADC_CH_CONFIG */ 6780 /* Description: Description cluster: Input configuration for CH[n] */ 6781 6782 /* Bit 24 : Enable burst mode */ 6783 #define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */ 6784 #define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */ 6785 #define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */ 6786 #define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */ 6787 6788 /* Bit 20 : Enable differential mode */ 6789 #define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */ 6790 #define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ 6791 #define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */ 6792 #define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */ 6793 6794 /* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */ 6795 #define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */ 6796 #define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */ 6797 #define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */ 6798 #define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */ 6799 #define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */ 6800 #define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */ 6801 #define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */ 6802 #define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */ 6803 6804 /* Bit 12 : Reference control */ 6805 #define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */ 6806 #define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ 6807 #define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */ 6808 #define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD_GPIO/4 as reference */ 6809 6810 /* Bits 10..8 : Gain control */ 6811 #define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */ 6812 #define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */ 6813 #define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */ 6814 #define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */ 6815 #define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */ 6816 #define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */ 6817 #define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */ 6818 #define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */ 6819 #define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */ 6820 #define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */ 6821 6822 /* Bits 5..4 : Negative channel resistor control */ 6823 #define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */ 6824 #define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */ 6825 #define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */ 6826 #define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */ 6827 #define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD_GPIO */ 6828 #define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD_GPIO/2 */ 6829 6830 /* Bits 1..0 : Positive channel resistor control */ 6831 #define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */ 6832 #define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */ 6833 #define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */ 6834 #define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */ 6835 #define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD_GPIO */ 6836 #define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD_GPIO/2 */ 6837 6838 /* Register: SAADC_CH_LIMIT */ 6839 /* Description: Description cluster: High/low limits for event monitoring a channel */ 6840 6841 /* Bits 31..16 : High level limit */ 6842 #define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */ 6843 #define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */ 6844 6845 /* Bits 15..0 : Low level limit */ 6846 #define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */ 6847 #define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */ 6848 6849 /* Register: SAADC_RESOLUTION */ 6850 /* Description: Resolution configuration */ 6851 6852 /* Bits 2..0 : Set the resolution */ 6853 #define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */ 6854 #define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */ 6855 #define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */ 6856 #define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */ 6857 #define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */ 6858 #define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */ 6859 6860 /* Register: SAADC_OVERSAMPLE */ 6861 /* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */ 6862 6863 /* Bits 3..0 : Oversample control */ 6864 #define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */ 6865 #define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */ 6866 #define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */ 6867 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */ 6868 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */ 6869 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */ 6870 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */ 6871 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */ 6872 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */ 6873 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */ 6874 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */ 6875 6876 /* Register: SAADC_SAMPLERATE */ 6877 /* Description: Controls normal or continuous sample rate */ 6878 6879 /* Bit 12 : Select mode for sample rate control */ 6880 #define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */ 6881 #define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */ 6882 #define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */ 6883 #define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */ 6884 6885 /* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */ 6886 #define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */ 6887 #define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */ 6888 6889 /* Register: SAADC_RESULT_PTR */ 6890 /* Description: Data pointer */ 6891 6892 /* Bits 31..0 : Data pointer */ 6893 #define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 6894 #define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 6895 6896 /* Register: SAADC_RESULT_MAXCNT */ 6897 /* Description: Maximum number of buffer words to transfer */ 6898 6899 /* Bits 14..0 : Maximum number of buffer words to transfer */ 6900 #define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 6901 #define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 6902 6903 /* Register: SAADC_RESULT_AMOUNT */ 6904 /* Description: Number of buffer words transferred since last START */ 6905 6906 /* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */ 6907 #define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 6908 #define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 6909 6910 6911 /* Peripheral: SPIM */ 6912 /* Description: Serial Peripheral Interface Master with EasyDMA 0 */ 6913 6914 /* Register: SPIM_TASKS_START */ 6915 /* Description: Start SPI transaction */ 6916 6917 /* Bit 0 : Start SPI transaction */ 6918 #define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 6919 #define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 6920 #define SPIM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ 6921 6922 /* Register: SPIM_TASKS_STOP */ 6923 /* Description: Stop SPI transaction */ 6924 6925 /* Bit 0 : Stop SPI transaction */ 6926 #define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 6927 #define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 6928 #define SPIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 6929 6930 /* Register: SPIM_TASKS_SUSPEND */ 6931 /* Description: Suspend SPI transaction */ 6932 6933 /* Bit 0 : Suspend SPI transaction */ 6934 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ 6935 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ 6936 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ 6937 6938 /* Register: SPIM_TASKS_RESUME */ 6939 /* Description: Resume SPI transaction */ 6940 6941 /* Bit 0 : Resume SPI transaction */ 6942 #define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ 6943 #define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ 6944 #define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ 6945 6946 /* Register: SPIM_SUBSCRIBE_START */ 6947 /* Description: Subscribe configuration for task START */ 6948 6949 /* Bit 31 : */ 6950 #define SPIM_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ 6951 #define SPIM_SUBSCRIBE_START_EN_Msk (0x1UL << SPIM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ 6952 #define SPIM_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ 6953 #define SPIM_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ 6954 6955 /* Bits 7..0 : DPPI channel that task START will subscribe to */ 6956 #define SPIM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 6957 #define SPIM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 6958 6959 /* Register: SPIM_SUBSCRIBE_STOP */ 6960 /* Description: Subscribe configuration for task STOP */ 6961 6962 /* Bit 31 : */ 6963 #define SPIM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 6964 #define SPIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << SPIM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 6965 #define SPIM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ 6966 #define SPIM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ 6967 6968 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 6969 #define SPIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 6970 #define SPIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 6971 6972 /* Register: SPIM_SUBSCRIBE_SUSPEND */ 6973 /* Description: Subscribe configuration for task SUSPEND */ 6974 6975 /* Bit 31 : */ 6976 #define SPIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */ 6977 #define SPIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << SPIM_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */ 6978 #define SPIM_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */ 6979 #define SPIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */ 6980 6981 /* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */ 6982 #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 6983 #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 6984 6985 /* Register: SPIM_SUBSCRIBE_RESUME */ 6986 /* Description: Subscribe configuration for task RESUME */ 6987 6988 /* Bit 31 : */ 6989 #define SPIM_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */ 6990 #define SPIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << SPIM_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */ 6991 #define SPIM_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */ 6992 #define SPIM_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */ 6993 6994 /* Bits 7..0 : DPPI channel that task RESUME will subscribe to */ 6995 #define SPIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 6996 #define SPIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 6997 6998 /* Register: SPIM_EVENTS_STOPPED */ 6999 /* Description: SPI transaction has stopped */ 7000 7001 /* Bit 0 : SPI transaction has stopped */ 7002 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ 7003 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ 7004 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ 7005 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ 7006 7007 /* Register: SPIM_EVENTS_ENDRX */ 7008 /* Description: End of RXD buffer reached */ 7009 7010 /* Bit 0 : End of RXD buffer reached */ 7011 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ 7012 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ 7013 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ 7014 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ 7015 7016 /* Register: SPIM_EVENTS_END */ 7017 /* Description: End of RXD buffer and TXD buffer reached */ 7018 7019 /* Bit 0 : End of RXD buffer and TXD buffer reached */ 7020 #define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ 7021 #define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ 7022 #define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ 7023 #define SPIM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ 7024 7025 /* Register: SPIM_EVENTS_ENDTX */ 7026 /* Description: End of TXD buffer reached */ 7027 7028 /* Bit 0 : End of TXD buffer reached */ 7029 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ 7030 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ 7031 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */ 7032 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */ 7033 7034 /* Register: SPIM_EVENTS_STARTED */ 7035 /* Description: Transaction started */ 7036 7037 /* Bit 0 : Transaction started */ 7038 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ 7039 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ 7040 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ 7041 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ 7042 7043 /* Register: SPIM_PUBLISH_STOPPED */ 7044 /* Description: Publish configuration for event STOPPED */ 7045 7046 /* Bit 31 : */ 7047 #define SPIM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ 7048 #define SPIM_PUBLISH_STOPPED_EN_Msk (0x1UL << SPIM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ 7049 #define SPIM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ 7050 #define SPIM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ 7051 7052 /* Bits 7..0 : DPPI channel that event STOPPED will publish to */ 7053 #define SPIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 7054 #define SPIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 7055 7056 /* Register: SPIM_PUBLISH_ENDRX */ 7057 /* Description: Publish configuration for event ENDRX */ 7058 7059 /* Bit 31 : */ 7060 #define SPIM_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */ 7061 #define SPIM_PUBLISH_ENDRX_EN_Msk (0x1UL << SPIM_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */ 7062 #define SPIM_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */ 7063 #define SPIM_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */ 7064 7065 /* Bits 7..0 : DPPI channel that event ENDRX will publish to */ 7066 #define SPIM_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 7067 #define SPIM_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 7068 7069 /* Register: SPIM_PUBLISH_END */ 7070 /* Description: Publish configuration for event END */ 7071 7072 /* Bit 31 : */ 7073 #define SPIM_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ 7074 #define SPIM_PUBLISH_END_EN_Msk (0x1UL << SPIM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ 7075 #define SPIM_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */ 7076 #define SPIM_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */ 7077 7078 /* Bits 7..0 : DPPI channel that event END will publish to */ 7079 #define SPIM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 7080 #define SPIM_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 7081 7082 /* Register: SPIM_PUBLISH_ENDTX */ 7083 /* Description: Publish configuration for event ENDTX */ 7084 7085 /* Bit 31 : */ 7086 #define SPIM_PUBLISH_ENDTX_EN_Pos (31UL) /*!< Position of EN field. */ 7087 #define SPIM_PUBLISH_ENDTX_EN_Msk (0x1UL << SPIM_PUBLISH_ENDTX_EN_Pos) /*!< Bit mask of EN field. */ 7088 #define SPIM_PUBLISH_ENDTX_EN_Disabled (0UL) /*!< Disable publishing */ 7089 #define SPIM_PUBLISH_ENDTX_EN_Enabled (1UL) /*!< Enable publishing */ 7090 7091 /* Bits 7..0 : DPPI channel that event ENDTX will publish to */ 7092 #define SPIM_PUBLISH_ENDTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 7093 #define SPIM_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 7094 7095 /* Register: SPIM_PUBLISH_STARTED */ 7096 /* Description: Publish configuration for event STARTED */ 7097 7098 /* Bit 31 : */ 7099 #define SPIM_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */ 7100 #define SPIM_PUBLISH_STARTED_EN_Msk (0x1UL << SPIM_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */ 7101 #define SPIM_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */ 7102 #define SPIM_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */ 7103 7104 /* Bits 7..0 : DPPI channel that event STARTED will publish to */ 7105 #define SPIM_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 7106 #define SPIM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 7107 7108 /* Register: SPIM_SHORTS */ 7109 /* Description: Shortcuts between local events and tasks */ 7110 7111 /* Bit 17 : Shortcut between event END and task START */ 7112 #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ 7113 #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ 7114 #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ 7115 #define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ 7116 7117 /* Register: SPIM_INTENSET */ 7118 /* Description: Enable interrupt */ 7119 7120 /* Bit 19 : Write '1' to enable interrupt for event STARTED */ 7121 #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ 7122 #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ 7123 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ 7124 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ 7125 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */ 7126 7127 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */ 7128 #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ 7129 #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 7130 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ 7131 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ 7132 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */ 7133 7134 /* Bit 6 : Write '1' to enable interrupt for event END */ 7135 #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ 7136 #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ 7137 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ 7138 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ 7139 #define SPIM_INTENSET_END_Set (1UL) /*!< Enable */ 7140 7141 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */ 7142 #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 7143 #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 7144 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ 7145 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ 7146 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */ 7147 7148 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */ 7149 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 7150 #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 7151 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 7152 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 7153 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ 7154 7155 /* Register: SPIM_INTENCLR */ 7156 /* Description: Disable interrupt */ 7157 7158 /* Bit 19 : Write '1' to disable interrupt for event STARTED */ 7159 #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ 7160 #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ 7161 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ 7162 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ 7163 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ 7164 7165 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */ 7166 #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ 7167 #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 7168 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ 7169 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ 7170 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ 7171 7172 /* Bit 6 : Write '1' to disable interrupt for event END */ 7173 #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ 7174 #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 7175 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ 7176 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ 7177 #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */ 7178 7179 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */ 7180 #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 7181 #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 7182 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ 7183 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ 7184 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ 7185 7186 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */ 7187 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 7188 #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 7189 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 7190 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 7191 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ 7192 7193 /* Register: SPIM_ENABLE */ 7194 /* Description: Enable SPIM */ 7195 7196 /* Bits 3..0 : Enable or disable SPIM */ 7197 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 7198 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 7199 #define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */ 7200 #define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */ 7201 7202 /* Register: SPIM_PSEL_SCK */ 7203 /* Description: Pin select for SCK */ 7204 7205 /* Bit 31 : Connection */ 7206 #define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 7207 #define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 7208 #define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ 7209 #define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ 7210 7211 /* Bits 4..0 : Pin number */ 7212 #define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ 7213 #define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ 7214 7215 /* Register: SPIM_PSEL_MOSI */ 7216 /* Description: Pin select for MOSI signal */ 7217 7218 /* Bit 31 : Connection */ 7219 #define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 7220 #define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 7221 #define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ 7222 #define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ 7223 7224 /* Bits 4..0 : Pin number */ 7225 #define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ 7226 #define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ 7227 7228 /* Register: SPIM_PSEL_MISO */ 7229 /* Description: Pin select for MISO signal */ 7230 7231 /* Bit 31 : Connection */ 7232 #define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 7233 #define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 7234 #define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ 7235 #define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ 7236 7237 /* Bits 4..0 : Pin number */ 7238 #define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ 7239 #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ 7240 7241 /* Register: SPIM_FREQUENCY */ 7242 /* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */ 7243 7244 /* Bits 31..0 : SPI master data rate */ 7245 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 7246 #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 7247 #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */ 7248 #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ 7249 #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */ 7250 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */ 7251 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */ 7252 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */ 7253 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */ 7254 7255 /* Register: SPIM_RXD_PTR */ 7256 /* Description: Data pointer */ 7257 7258 /* Bits 31..0 : Data pointer */ 7259 #define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 7260 #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 7261 7262 /* Register: SPIM_RXD_MAXCNT */ 7263 /* Description: Maximum number of bytes in receive buffer */ 7264 7265 /* Bits 12..0 : Maximum number of bytes in receive buffer */ 7266 #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 7267 #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 7268 7269 /* Register: SPIM_RXD_AMOUNT */ 7270 /* Description: Number of bytes transferred in the last transaction */ 7271 7272 /* Bits 12..0 : Number of bytes transferred in the last transaction */ 7273 #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 7274 #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 7275 7276 /* Register: SPIM_RXD_LIST */ 7277 /* Description: EasyDMA list type */ 7278 7279 /* Bits 1..0 : List type */ 7280 #define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 7281 #define SPIM_RXD_LIST_LIST_Msk (0x3UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 7282 #define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ 7283 #define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ 7284 7285 /* Register: SPIM_TXD_PTR */ 7286 /* Description: Data pointer */ 7287 7288 /* Bits 31..0 : Data pointer */ 7289 #define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 7290 #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 7291 7292 /* Register: SPIM_TXD_MAXCNT */ 7293 /* Description: Maximum number of bytes in transmit buffer */ 7294 7295 /* Bits 12..0 : Maximum number of bytes in transmit buffer */ 7296 #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 7297 #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 7298 7299 /* Register: SPIM_TXD_AMOUNT */ 7300 /* Description: Number of bytes transferred in the last transaction */ 7301 7302 /* Bits 12..0 : Number of bytes transferred in the last transaction */ 7303 #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 7304 #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 7305 7306 /* Register: SPIM_TXD_LIST */ 7307 /* Description: EasyDMA list type */ 7308 7309 /* Bits 1..0 : List type */ 7310 #define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 7311 #define SPIM_TXD_LIST_LIST_Msk (0x3UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 7312 #define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ 7313 #define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ 7314 7315 /* Register: SPIM_CONFIG */ 7316 /* Description: Configuration register */ 7317 7318 /* Bit 2 : Serial clock (SCK) polarity */ 7319 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ 7320 #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ 7321 #define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ 7322 #define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ 7323 7324 /* Bit 1 : Serial clock (SCK) phase */ 7325 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ 7326 #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ 7327 #define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ 7328 #define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ 7329 7330 /* Bit 0 : Bit order */ 7331 #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ 7332 #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ 7333 #define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ 7334 #define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ 7335 7336 /* Register: SPIM_ORC */ 7337 /* Description: Over-read character. Character clocked out in case an over-read of the TXD buffer. */ 7338 7339 /* Bits 7..0 : Over-read character. Character clocked out in case an over-read of the TXD buffer. */ 7340 #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ 7341 #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ 7342 7343 7344 /* Peripheral: SPIS */ 7345 /* Description: SPI Slave 0 */ 7346 7347 /* Register: SPIS_TASKS_ACQUIRE */ 7348 /* Description: Acquire SPI semaphore */ 7349 7350 /* Bit 0 : Acquire SPI semaphore */ 7351 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */ 7352 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */ 7353 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (1UL) /*!< Trigger task */ 7354 7355 /* Register: SPIS_TASKS_RELEASE */ 7356 /* Description: Release SPI semaphore, enabling the SPI slave to acquire it */ 7357 7358 /* Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */ 7359 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */ 7360 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */ 7361 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (1UL) /*!< Trigger task */ 7362 7363 /* Register: SPIS_SUBSCRIBE_ACQUIRE */ 7364 /* Description: Subscribe configuration for task ACQUIRE */ 7365 7366 /* Bit 31 : */ 7367 #define SPIS_SUBSCRIBE_ACQUIRE_EN_Pos (31UL) /*!< Position of EN field. */ 7368 #define SPIS_SUBSCRIBE_ACQUIRE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_ACQUIRE_EN_Pos) /*!< Bit mask of EN field. */ 7369 #define SPIS_SUBSCRIBE_ACQUIRE_EN_Disabled (0UL) /*!< Disable subscription */ 7370 #define SPIS_SUBSCRIBE_ACQUIRE_EN_Enabled (1UL) /*!< Enable subscription */ 7371 7372 /* Bits 7..0 : DPPI channel that task ACQUIRE will subscribe to */ 7373 #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 7374 #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 7375 7376 /* Register: SPIS_SUBSCRIBE_RELEASE */ 7377 /* Description: Subscribe configuration for task RELEASE */ 7378 7379 /* Bit 31 : */ 7380 #define SPIS_SUBSCRIBE_RELEASE_EN_Pos (31UL) /*!< Position of EN field. */ 7381 #define SPIS_SUBSCRIBE_RELEASE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_RELEASE_EN_Pos) /*!< Bit mask of EN field. */ 7382 #define SPIS_SUBSCRIBE_RELEASE_EN_Disabled (0UL) /*!< Disable subscription */ 7383 #define SPIS_SUBSCRIBE_RELEASE_EN_Enabled (1UL) /*!< Enable subscription */ 7384 7385 /* Bits 7..0 : DPPI channel that task RELEASE will subscribe to */ 7386 #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 7387 #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 7388 7389 /* Register: SPIS_EVENTS_END */ 7390 /* Description: Granted transaction completed */ 7391 7392 /* Bit 0 : Granted transaction completed */ 7393 #define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ 7394 #define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ 7395 #define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ 7396 #define SPIS_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ 7397 7398 /* Register: SPIS_EVENTS_ENDRX */ 7399 /* Description: End of RXD buffer reached */ 7400 7401 /* Bit 0 : End of RXD buffer reached */ 7402 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ 7403 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ 7404 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ 7405 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ 7406 7407 /* Register: SPIS_EVENTS_ACQUIRED */ 7408 /* Description: Semaphore acquired */ 7409 7410 /* Bit 0 : Semaphore acquired */ 7411 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */ 7412 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */ 7413 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0UL) /*!< Event not generated */ 7414 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (1UL) /*!< Event generated */ 7415 7416 /* Register: SPIS_PUBLISH_END */ 7417 /* Description: Publish configuration for event END */ 7418 7419 /* Bit 31 : */ 7420 #define SPIS_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ 7421 #define SPIS_PUBLISH_END_EN_Msk (0x1UL << SPIS_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ 7422 #define SPIS_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */ 7423 #define SPIS_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */ 7424 7425 /* Bits 7..0 : DPPI channel that event END will publish to */ 7426 #define SPIS_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 7427 #define SPIS_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 7428 7429 /* Register: SPIS_PUBLISH_ENDRX */ 7430 /* Description: Publish configuration for event ENDRX */ 7431 7432 /* Bit 31 : */ 7433 #define SPIS_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */ 7434 #define SPIS_PUBLISH_ENDRX_EN_Msk (0x1UL << SPIS_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */ 7435 #define SPIS_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */ 7436 #define SPIS_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */ 7437 7438 /* Bits 7..0 : DPPI channel that event ENDRX will publish to */ 7439 #define SPIS_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 7440 #define SPIS_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 7441 7442 /* Register: SPIS_PUBLISH_ACQUIRED */ 7443 /* Description: Publish configuration for event ACQUIRED */ 7444 7445 /* Bit 31 : */ 7446 #define SPIS_PUBLISH_ACQUIRED_EN_Pos (31UL) /*!< Position of EN field. */ 7447 #define SPIS_PUBLISH_ACQUIRED_EN_Msk (0x1UL << SPIS_PUBLISH_ACQUIRED_EN_Pos) /*!< Bit mask of EN field. */ 7448 #define SPIS_PUBLISH_ACQUIRED_EN_Disabled (0UL) /*!< Disable publishing */ 7449 #define SPIS_PUBLISH_ACQUIRED_EN_Enabled (1UL) /*!< Enable publishing */ 7450 7451 /* Bits 7..0 : DPPI channel that event ACQUIRED will publish to */ 7452 #define SPIS_PUBLISH_ACQUIRED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 7453 #define SPIS_PUBLISH_ACQUIRED_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ACQUIRED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 7454 7455 /* Register: SPIS_SHORTS */ 7456 /* Description: Shortcuts between local events and tasks */ 7457 7458 /* Bit 2 : Shortcut between event END and task ACQUIRE */ 7459 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ 7460 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ 7461 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */ 7462 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */ 7463 7464 /* Register: SPIS_INTENSET */ 7465 /* Description: Enable interrupt */ 7466 7467 /* Bit 10 : Write '1' to enable interrupt for event ACQUIRED */ 7468 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ 7469 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ 7470 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ 7471 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ 7472 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */ 7473 7474 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */ 7475 #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 7476 #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 7477 #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ 7478 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ 7479 #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */ 7480 7481 /* Bit 1 : Write '1' to enable interrupt for event END */ 7482 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ 7483 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ 7484 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ 7485 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ 7486 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable */ 7487 7488 /* Register: SPIS_INTENCLR */ 7489 /* Description: Disable interrupt */ 7490 7491 /* Bit 10 : Write '1' to disable interrupt for event ACQUIRED */ 7492 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ 7493 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ 7494 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ 7495 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ 7496 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */ 7497 7498 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */ 7499 #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 7500 #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 7501 #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ 7502 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ 7503 #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ 7504 7505 /* Bit 1 : Write '1' to disable interrupt for event END */ 7506 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ 7507 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 7508 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ 7509 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ 7510 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */ 7511 7512 /* Register: SPIS_SEMSTAT */ 7513 /* Description: Semaphore status register */ 7514 7515 /* Bits 1..0 : Semaphore status */ 7516 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */ 7517 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */ 7518 #define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */ 7519 #define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */ 7520 #define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */ 7521 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */ 7522 7523 /* Register: SPIS_STATUS */ 7524 /* Description: Status from last transaction */ 7525 7526 /* Bit 1 : RX buffer overflow detected, and prevented */ 7527 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */ 7528 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ 7529 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */ 7530 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */ 7531 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */ 7532 7533 /* Bit 0 : TX buffer over-read detected, and prevented */ 7534 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */ 7535 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ 7536 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */ 7537 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */ 7538 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */ 7539 7540 /* Register: SPIS_ENABLE */ 7541 /* Description: Enable SPI slave */ 7542 7543 /* Bits 3..0 : Enable or disable SPI slave */ 7544 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 7545 #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 7546 #define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */ 7547 #define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */ 7548 7549 /* Register: SPIS_PSEL_SCK */ 7550 /* Description: Pin select for SCK */ 7551 7552 /* Bit 31 : Connection */ 7553 #define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 7554 #define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 7555 #define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ 7556 #define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ 7557 7558 /* Bits 4..0 : Pin number */ 7559 #define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ 7560 #define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ 7561 7562 /* Register: SPIS_PSEL_MISO */ 7563 /* Description: Pin select for MISO signal */ 7564 7565 /* Bit 31 : Connection */ 7566 #define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 7567 #define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 7568 #define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ 7569 #define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ 7570 7571 /* Bits 4..0 : Pin number */ 7572 #define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ 7573 #define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ 7574 7575 /* Register: SPIS_PSEL_MOSI */ 7576 /* Description: Pin select for MOSI signal */ 7577 7578 /* Bit 31 : Connection */ 7579 #define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 7580 #define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 7581 #define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ 7582 #define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ 7583 7584 /* Bits 4..0 : Pin number */ 7585 #define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ 7586 #define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ 7587 7588 /* Register: SPIS_PSEL_CSN */ 7589 /* Description: Pin select for CSN signal */ 7590 7591 /* Bit 31 : Connection */ 7592 #define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 7593 #define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 7594 #define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */ 7595 #define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */ 7596 7597 /* Bits 4..0 : Pin number */ 7598 #define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */ 7599 #define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */ 7600 7601 /* Register: SPIS_RXD_PTR */ 7602 /* Description: RXD data pointer */ 7603 7604 /* Bits 31..0 : RXD data pointer */ 7605 #define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 7606 #define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 7607 7608 /* Register: SPIS_RXD_MAXCNT */ 7609 /* Description: Maximum number of bytes in receive buffer */ 7610 7611 /* Bits 12..0 : Maximum number of bytes in receive buffer */ 7612 #define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 7613 #define SPIS_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 7614 7615 /* Register: SPIS_RXD_AMOUNT */ 7616 /* Description: Number of bytes received in last granted transaction */ 7617 7618 /* Bits 12..0 : Number of bytes received in the last granted transaction */ 7619 #define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 7620 #define SPIS_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 7621 7622 /* Register: SPIS_RXD_LIST */ 7623 /* Description: EasyDMA list type */ 7624 7625 /* Bits 1..0 : List type */ 7626 #define SPIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 7627 #define SPIS_RXD_LIST_LIST_Msk (0x3UL << SPIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 7628 #define SPIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ 7629 #define SPIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ 7630 7631 /* Register: SPIS_TXD_PTR */ 7632 /* Description: TXD data pointer */ 7633 7634 /* Bits 31..0 : TXD data pointer */ 7635 #define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 7636 #define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 7637 7638 /* Register: SPIS_TXD_MAXCNT */ 7639 /* Description: Maximum number of bytes in transmit buffer */ 7640 7641 /* Bits 12..0 : Maximum number of bytes in transmit buffer */ 7642 #define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 7643 #define SPIS_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 7644 7645 /* Register: SPIS_TXD_AMOUNT */ 7646 /* Description: Number of bytes transmitted in last granted transaction */ 7647 7648 /* Bits 12..0 : Number of bytes transmitted in last granted transaction */ 7649 #define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 7650 #define SPIS_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 7651 7652 /* Register: SPIS_TXD_LIST */ 7653 /* Description: EasyDMA list type */ 7654 7655 /* Bits 1..0 : List type */ 7656 #define SPIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 7657 #define SPIS_TXD_LIST_LIST_Msk (0x3UL << SPIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 7658 #define SPIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ 7659 #define SPIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ 7660 7661 /* Register: SPIS_CONFIG */ 7662 /* Description: Configuration register */ 7663 7664 /* Bit 2 : Serial clock (SCK) polarity */ 7665 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ 7666 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ 7667 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ 7668 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ 7669 7670 /* Bit 1 : Serial clock (SCK) phase */ 7671 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ 7672 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ 7673 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ 7674 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ 7675 7676 /* Bit 0 : Bit order */ 7677 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ 7678 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ 7679 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ 7680 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ 7681 7682 /* Register: SPIS_DEF */ 7683 /* Description: Default character. Character clocked out in case of an ignored transaction. */ 7684 7685 /* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */ 7686 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */ 7687 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */ 7688 7689 /* Register: SPIS_ORC */ 7690 /* Description: Over-read character */ 7691 7692 /* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */ 7693 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ 7694 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ 7695 7696 7697 /* Peripheral: SPU */ 7698 /* Description: System protection unit */ 7699 7700 /* Register: SPU_EVENTS_RAMACCERR */ 7701 /* Description: A security violation has been detected for the RAM memory space */ 7702 7703 /* Bit 0 : A security violation has been detected for the RAM memory space */ 7704 #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Pos (0UL) /*!< Position of EVENTS_RAMACCERR field. */ 7705 #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Msk (0x1UL << SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Pos) /*!< Bit mask of EVENTS_RAMACCERR field. */ 7706 #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_NotGenerated (0UL) /*!< Event not generated */ 7707 #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Generated (1UL) /*!< Event generated */ 7708 7709 /* Register: SPU_EVENTS_FLASHACCERR */ 7710 /* Description: A security violation has been detected for the flash memory space */ 7711 7712 /* Bit 0 : A security violation has been detected for the flash memory space */ 7713 #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Pos (0UL) /*!< Position of EVENTS_FLASHACCERR field. */ 7714 #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Msk (0x1UL << SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Pos) /*!< Bit mask of EVENTS_FLASHACCERR field. */ 7715 #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_NotGenerated (0UL) /*!< Event not generated */ 7716 #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Generated (1UL) /*!< Event generated */ 7717 7718 /* Register: SPU_EVENTS_PERIPHACCERR */ 7719 /* Description: A security violation has been detected on one or several peripherals */ 7720 7721 /* Bit 0 : A security violation has been detected on one or several peripherals */ 7722 #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos (0UL) /*!< Position of EVENTS_PERIPHACCERR field. */ 7723 #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Msk (0x1UL << SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos) /*!< Bit mask of EVENTS_PERIPHACCERR field. */ 7724 #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_NotGenerated (0UL) /*!< Event not generated */ 7725 #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Generated (1UL) /*!< Event generated */ 7726 7727 /* Register: SPU_PUBLISH_RAMACCERR */ 7728 /* Description: Publish configuration for event RAMACCERR */ 7729 7730 /* Bit 31 : */ 7731 #define SPU_PUBLISH_RAMACCERR_EN_Pos (31UL) /*!< Position of EN field. */ 7732 #define SPU_PUBLISH_RAMACCERR_EN_Msk (0x1UL << SPU_PUBLISH_RAMACCERR_EN_Pos) /*!< Bit mask of EN field. */ 7733 #define SPU_PUBLISH_RAMACCERR_EN_Disabled (0UL) /*!< Disable publishing */ 7734 #define SPU_PUBLISH_RAMACCERR_EN_Enabled (1UL) /*!< Enable publishing */ 7735 7736 /* Bits 7..0 : DPPI channel that event RAMACCERR will publish to */ 7737 #define SPU_PUBLISH_RAMACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 7738 #define SPU_PUBLISH_RAMACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_RAMACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 7739 7740 /* Register: SPU_PUBLISH_FLASHACCERR */ 7741 /* Description: Publish configuration for event FLASHACCERR */ 7742 7743 /* Bit 31 : */ 7744 #define SPU_PUBLISH_FLASHACCERR_EN_Pos (31UL) /*!< Position of EN field. */ 7745 #define SPU_PUBLISH_FLASHACCERR_EN_Msk (0x1UL << SPU_PUBLISH_FLASHACCERR_EN_Pos) /*!< Bit mask of EN field. */ 7746 #define SPU_PUBLISH_FLASHACCERR_EN_Disabled (0UL) /*!< Disable publishing */ 7747 #define SPU_PUBLISH_FLASHACCERR_EN_Enabled (1UL) /*!< Enable publishing */ 7748 7749 /* Bits 7..0 : DPPI channel that event FLASHACCERR will publish to */ 7750 #define SPU_PUBLISH_FLASHACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 7751 #define SPU_PUBLISH_FLASHACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_FLASHACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 7752 7753 /* Register: SPU_PUBLISH_PERIPHACCERR */ 7754 /* Description: Publish configuration for event PERIPHACCERR */ 7755 7756 /* Bit 31 : */ 7757 #define SPU_PUBLISH_PERIPHACCERR_EN_Pos (31UL) /*!< Position of EN field. */ 7758 #define SPU_PUBLISH_PERIPHACCERR_EN_Msk (0x1UL << SPU_PUBLISH_PERIPHACCERR_EN_Pos) /*!< Bit mask of EN field. */ 7759 #define SPU_PUBLISH_PERIPHACCERR_EN_Disabled (0UL) /*!< Disable publishing */ 7760 #define SPU_PUBLISH_PERIPHACCERR_EN_Enabled (1UL) /*!< Enable publishing */ 7761 7762 /* Bits 7..0 : DPPI channel that event PERIPHACCERR will publish to */ 7763 #define SPU_PUBLISH_PERIPHACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 7764 #define SPU_PUBLISH_PERIPHACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_PERIPHACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 7765 7766 /* Register: SPU_INTEN */ 7767 /* Description: Enable or disable interrupt */ 7768 7769 /* Bit 2 : Enable or disable interrupt for event PERIPHACCERR */ 7770 #define SPU_INTEN_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */ 7771 #define SPU_INTEN_PERIPHACCERR_Msk (0x1UL << SPU_INTEN_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */ 7772 #define SPU_INTEN_PERIPHACCERR_Disabled (0UL) /*!< Disable */ 7773 #define SPU_INTEN_PERIPHACCERR_Enabled (1UL) /*!< Enable */ 7774 7775 /* Bit 1 : Enable or disable interrupt for event FLASHACCERR */ 7776 #define SPU_INTEN_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */ 7777 #define SPU_INTEN_FLASHACCERR_Msk (0x1UL << SPU_INTEN_FLASHACCERR_Pos) /*!< Bit mask of FLASHACCERR field. */ 7778 #define SPU_INTEN_FLASHACCERR_Disabled (0UL) /*!< Disable */ 7779 #define SPU_INTEN_FLASHACCERR_Enabled (1UL) /*!< Enable */ 7780 7781 /* Bit 0 : Enable or disable interrupt for event RAMACCERR */ 7782 #define SPU_INTEN_RAMACCERR_Pos (0UL) /*!< Position of RAMACCERR field. */ 7783 #define SPU_INTEN_RAMACCERR_Msk (0x1UL << SPU_INTEN_RAMACCERR_Pos) /*!< Bit mask of RAMACCERR field. */ 7784 #define SPU_INTEN_RAMACCERR_Disabled (0UL) /*!< Disable */ 7785 #define SPU_INTEN_RAMACCERR_Enabled (1UL) /*!< Enable */ 7786 7787 /* Register: SPU_INTENSET */ 7788 /* Description: Enable interrupt */ 7789 7790 /* Bit 2 : Write '1' to enable interrupt for event PERIPHACCERR */ 7791 #define SPU_INTENSET_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */ 7792 #define SPU_INTENSET_PERIPHACCERR_Msk (0x1UL << SPU_INTENSET_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */ 7793 #define SPU_INTENSET_PERIPHACCERR_Disabled (0UL) /*!< Read: Disabled */ 7794 #define SPU_INTENSET_PERIPHACCERR_Enabled (1UL) /*!< Read: Enabled */ 7795 #define SPU_INTENSET_PERIPHACCERR_Set (1UL) /*!< Enable */ 7796 7797 /* Bit 1 : Write '1' to enable interrupt for event FLASHACCERR */ 7798 #define SPU_INTENSET_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */ 7799 #define SPU_INTENSET_FLASHACCERR_Msk (0x1UL << SPU_INTENSET_FLASHACCERR_Pos) /*!< Bit mask of FLASHACCERR field. */ 7800 #define SPU_INTENSET_FLASHACCERR_Disabled (0UL) /*!< Read: Disabled */ 7801 #define SPU_INTENSET_FLASHACCERR_Enabled (1UL) /*!< Read: Enabled */ 7802 #define SPU_INTENSET_FLASHACCERR_Set (1UL) /*!< Enable */ 7803 7804 /* Bit 0 : Write '1' to enable interrupt for event RAMACCERR */ 7805 #define SPU_INTENSET_RAMACCERR_Pos (0UL) /*!< Position of RAMACCERR field. */ 7806 #define SPU_INTENSET_RAMACCERR_Msk (0x1UL << SPU_INTENSET_RAMACCERR_Pos) /*!< Bit mask of RAMACCERR field. */ 7807 #define SPU_INTENSET_RAMACCERR_Disabled (0UL) /*!< Read: Disabled */ 7808 #define SPU_INTENSET_RAMACCERR_Enabled (1UL) /*!< Read: Enabled */ 7809 #define SPU_INTENSET_RAMACCERR_Set (1UL) /*!< Enable */ 7810 7811 /* Register: SPU_INTENCLR */ 7812 /* Description: Disable interrupt */ 7813 7814 /* Bit 2 : Write '1' to disable interrupt for event PERIPHACCERR */ 7815 #define SPU_INTENCLR_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */ 7816 #define SPU_INTENCLR_PERIPHACCERR_Msk (0x1UL << SPU_INTENCLR_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */ 7817 #define SPU_INTENCLR_PERIPHACCERR_Disabled (0UL) /*!< Read: Disabled */ 7818 #define SPU_INTENCLR_PERIPHACCERR_Enabled (1UL) /*!< Read: Enabled */ 7819 #define SPU_INTENCLR_PERIPHACCERR_Clear (1UL) /*!< Disable */ 7820 7821 /* Bit 1 : Write '1' to disable interrupt for event FLASHACCERR */ 7822 #define SPU_INTENCLR_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */ 7823 #define SPU_INTENCLR_FLASHACCERR_Msk (0x1UL << SPU_INTENCLR_FLASHACCERR_Pos) /*!< Bit mask of FLASHACCERR field. */ 7824 #define SPU_INTENCLR_FLASHACCERR_Disabled (0UL) /*!< Read: Disabled */ 7825 #define SPU_INTENCLR_FLASHACCERR_Enabled (1UL) /*!< Read: Enabled */ 7826 #define SPU_INTENCLR_FLASHACCERR_Clear (1UL) /*!< Disable */ 7827 7828 /* Bit 0 : Write '1' to disable interrupt for event RAMACCERR */ 7829 #define SPU_INTENCLR_RAMACCERR_Pos (0UL) /*!< Position of RAMACCERR field. */ 7830 #define SPU_INTENCLR_RAMACCERR_Msk (0x1UL << SPU_INTENCLR_RAMACCERR_Pos) /*!< Bit mask of RAMACCERR field. */ 7831 #define SPU_INTENCLR_RAMACCERR_Disabled (0UL) /*!< Read: Disabled */ 7832 #define SPU_INTENCLR_RAMACCERR_Enabled (1UL) /*!< Read: Enabled */ 7833 #define SPU_INTENCLR_RAMACCERR_Clear (1UL) /*!< Disable */ 7834 7835 /* Register: SPU_CAP */ 7836 /* Description: Show implemented features for the current device */ 7837 7838 /* Bit 0 : Show ARM TrustZone status */ 7839 #define SPU_CAP_TZM_Pos (0UL) /*!< Position of TZM field. */ 7840 #define SPU_CAP_TZM_Msk (0x1UL << SPU_CAP_TZM_Pos) /*!< Bit mask of TZM field. */ 7841 #define SPU_CAP_TZM_NotAvailable (0UL) /*!< ARM TrustZone support not available */ 7842 #define SPU_CAP_TZM_Enabled (1UL) /*!< ARM TrustZone support is available */ 7843 7844 /* Register: SPU_EXTDOMAIN_PERM */ 7845 /* Description: Description cluster: Access for bus access generated from the external domain n List capabilities of the external domain n */ 7846 7847 /* Bit 8 : */ 7848 #define SPU_EXTDOMAIN_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */ 7849 #define SPU_EXTDOMAIN_PERM_LOCK_Msk (0x1UL << SPU_EXTDOMAIN_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */ 7850 #define SPU_EXTDOMAIN_PERM_LOCK_Unlocked (0UL) /*!< This register can be updated */ 7851 #define SPU_EXTDOMAIN_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */ 7852 7853 /* Bit 4 : Peripheral security mapping */ 7854 #define SPU_EXTDOMAIN_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ 7855 #define SPU_EXTDOMAIN_PERM_SECATTR_Msk (0x1UL << SPU_EXTDOMAIN_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ 7856 #define SPU_EXTDOMAIN_PERM_SECATTR_NonSecure (0UL) /*!< Bus accesses from this domain have the non-secure attribute set */ 7857 #define SPU_EXTDOMAIN_PERM_SECATTR_Secure (1UL) /*!< Bus accesses from this domain have secure attribute set */ 7858 7859 /* Bits 1..0 : Define configuration capabilities for TrustZone Cortex-M secure attribute */ 7860 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Pos (0UL) /*!< Position of SECUREMAPPING field. */ 7861 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Msk (0x3UL << SPU_EXTDOMAIN_PERM_SECUREMAPPING_Pos) /*!< Bit mask of SECUREMAPPING field. */ 7862 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_NonSecure (0UL) /*!< The bus access from this external domain always have the non-secure attribute set */ 7863 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Secure (1UL) /*!< The bus access from this external domain always have the secure attribute set */ 7864 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_UserSelectable (2UL) /*!< Non-secure or secure attribute for bus access from this domain is defined by the EXTDOMAIN[n].PERM register */ 7865 7866 /* Register: SPU_DPPI_PERM */ 7867 /* Description: Description cluster: Select between secure and non-secure attribute for the DPPI channels. */ 7868 7869 /* Bit 15 : Select secure attribute. */ 7870 #define SPU_DPPI_PERM_CHANNEL15_Pos (15UL) /*!< Position of CHANNEL15 field. */ 7871 #define SPU_DPPI_PERM_CHANNEL15_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL15_Pos) /*!< Bit mask of CHANNEL15 field. */ 7872 #define SPU_DPPI_PERM_CHANNEL15_NonSecure (0UL) /*!< Channel15 has its non-secure attribute set */ 7873 #define SPU_DPPI_PERM_CHANNEL15_Secure (1UL) /*!< Channel15 has its secure attribute set */ 7874 7875 /* Bit 14 : Select secure attribute. */ 7876 #define SPU_DPPI_PERM_CHANNEL14_Pos (14UL) /*!< Position of CHANNEL14 field. */ 7877 #define SPU_DPPI_PERM_CHANNEL14_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL14_Pos) /*!< Bit mask of CHANNEL14 field. */ 7878 #define SPU_DPPI_PERM_CHANNEL14_NonSecure (0UL) /*!< Channel14 has its non-secure attribute set */ 7879 #define SPU_DPPI_PERM_CHANNEL14_Secure (1UL) /*!< Channel14 has its secure attribute set */ 7880 7881 /* Bit 13 : Select secure attribute. */ 7882 #define SPU_DPPI_PERM_CHANNEL13_Pos (13UL) /*!< Position of CHANNEL13 field. */ 7883 #define SPU_DPPI_PERM_CHANNEL13_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL13_Pos) /*!< Bit mask of CHANNEL13 field. */ 7884 #define SPU_DPPI_PERM_CHANNEL13_NonSecure (0UL) /*!< Channel13 has its non-secure attribute set */ 7885 #define SPU_DPPI_PERM_CHANNEL13_Secure (1UL) /*!< Channel13 has its secure attribute set */ 7886 7887 /* Bit 12 : Select secure attribute. */ 7888 #define SPU_DPPI_PERM_CHANNEL12_Pos (12UL) /*!< Position of CHANNEL12 field. */ 7889 #define SPU_DPPI_PERM_CHANNEL12_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL12_Pos) /*!< Bit mask of CHANNEL12 field. */ 7890 #define SPU_DPPI_PERM_CHANNEL12_NonSecure (0UL) /*!< Channel12 has its non-secure attribute set */ 7891 #define SPU_DPPI_PERM_CHANNEL12_Secure (1UL) /*!< Channel12 has its secure attribute set */ 7892 7893 /* Bit 11 : Select secure attribute. */ 7894 #define SPU_DPPI_PERM_CHANNEL11_Pos (11UL) /*!< Position of CHANNEL11 field. */ 7895 #define SPU_DPPI_PERM_CHANNEL11_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL11_Pos) /*!< Bit mask of CHANNEL11 field. */ 7896 #define SPU_DPPI_PERM_CHANNEL11_NonSecure (0UL) /*!< Channel11 has its non-secure attribute set */ 7897 #define SPU_DPPI_PERM_CHANNEL11_Secure (1UL) /*!< Channel11 has its secure attribute set */ 7898 7899 /* Bit 10 : Select secure attribute. */ 7900 #define SPU_DPPI_PERM_CHANNEL10_Pos (10UL) /*!< Position of CHANNEL10 field. */ 7901 #define SPU_DPPI_PERM_CHANNEL10_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL10_Pos) /*!< Bit mask of CHANNEL10 field. */ 7902 #define SPU_DPPI_PERM_CHANNEL10_NonSecure (0UL) /*!< Channel10 has its non-secure attribute set */ 7903 #define SPU_DPPI_PERM_CHANNEL10_Secure (1UL) /*!< Channel10 has its secure attribute set */ 7904 7905 /* Bit 9 : Select secure attribute. */ 7906 #define SPU_DPPI_PERM_CHANNEL9_Pos (9UL) /*!< Position of CHANNEL9 field. */ 7907 #define SPU_DPPI_PERM_CHANNEL9_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL9_Pos) /*!< Bit mask of CHANNEL9 field. */ 7908 #define SPU_DPPI_PERM_CHANNEL9_NonSecure (0UL) /*!< Channel9 has its non-secure attribute set */ 7909 #define SPU_DPPI_PERM_CHANNEL9_Secure (1UL) /*!< Channel9 has its secure attribute set */ 7910 7911 /* Bit 8 : Select secure attribute. */ 7912 #define SPU_DPPI_PERM_CHANNEL8_Pos (8UL) /*!< Position of CHANNEL8 field. */ 7913 #define SPU_DPPI_PERM_CHANNEL8_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL8_Pos) /*!< Bit mask of CHANNEL8 field. */ 7914 #define SPU_DPPI_PERM_CHANNEL8_NonSecure (0UL) /*!< Channel8 has its non-secure attribute set */ 7915 #define SPU_DPPI_PERM_CHANNEL8_Secure (1UL) /*!< Channel8 has its secure attribute set */ 7916 7917 /* Bit 7 : Select secure attribute. */ 7918 #define SPU_DPPI_PERM_CHANNEL7_Pos (7UL) /*!< Position of CHANNEL7 field. */ 7919 #define SPU_DPPI_PERM_CHANNEL7_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL7_Pos) /*!< Bit mask of CHANNEL7 field. */ 7920 #define SPU_DPPI_PERM_CHANNEL7_NonSecure (0UL) /*!< Channel7 has its non-secure attribute set */ 7921 #define SPU_DPPI_PERM_CHANNEL7_Secure (1UL) /*!< Channel7 has its secure attribute set */ 7922 7923 /* Bit 6 : Select secure attribute. */ 7924 #define SPU_DPPI_PERM_CHANNEL6_Pos (6UL) /*!< Position of CHANNEL6 field. */ 7925 #define SPU_DPPI_PERM_CHANNEL6_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL6_Pos) /*!< Bit mask of CHANNEL6 field. */ 7926 #define SPU_DPPI_PERM_CHANNEL6_NonSecure (0UL) /*!< Channel6 has its non-secure attribute set */ 7927 #define SPU_DPPI_PERM_CHANNEL6_Secure (1UL) /*!< Channel6 has its secure attribute set */ 7928 7929 /* Bit 5 : Select secure attribute. */ 7930 #define SPU_DPPI_PERM_CHANNEL5_Pos (5UL) /*!< Position of CHANNEL5 field. */ 7931 #define SPU_DPPI_PERM_CHANNEL5_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL5_Pos) /*!< Bit mask of CHANNEL5 field. */ 7932 #define SPU_DPPI_PERM_CHANNEL5_NonSecure (0UL) /*!< Channel5 has its non-secure attribute set */ 7933 #define SPU_DPPI_PERM_CHANNEL5_Secure (1UL) /*!< Channel5 has its secure attribute set */ 7934 7935 /* Bit 4 : Select secure attribute. */ 7936 #define SPU_DPPI_PERM_CHANNEL4_Pos (4UL) /*!< Position of CHANNEL4 field. */ 7937 #define SPU_DPPI_PERM_CHANNEL4_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL4_Pos) /*!< Bit mask of CHANNEL4 field. */ 7938 #define SPU_DPPI_PERM_CHANNEL4_NonSecure (0UL) /*!< Channel4 has its non-secure attribute set */ 7939 #define SPU_DPPI_PERM_CHANNEL4_Secure (1UL) /*!< Channel4 has its secure attribute set */ 7940 7941 /* Bit 3 : Select secure attribute. */ 7942 #define SPU_DPPI_PERM_CHANNEL3_Pos (3UL) /*!< Position of CHANNEL3 field. */ 7943 #define SPU_DPPI_PERM_CHANNEL3_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL3_Pos) /*!< Bit mask of CHANNEL3 field. */ 7944 #define SPU_DPPI_PERM_CHANNEL3_NonSecure (0UL) /*!< Channel3 has its non-secure attribute set */ 7945 #define SPU_DPPI_PERM_CHANNEL3_Secure (1UL) /*!< Channel3 has its secure attribute set */ 7946 7947 /* Bit 2 : Select secure attribute. */ 7948 #define SPU_DPPI_PERM_CHANNEL2_Pos (2UL) /*!< Position of CHANNEL2 field. */ 7949 #define SPU_DPPI_PERM_CHANNEL2_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL2_Pos) /*!< Bit mask of CHANNEL2 field. */ 7950 #define SPU_DPPI_PERM_CHANNEL2_NonSecure (0UL) /*!< Channel2 has its non-secure attribute set */ 7951 #define SPU_DPPI_PERM_CHANNEL2_Secure (1UL) /*!< Channel2 has its secure attribute set */ 7952 7953 /* Bit 1 : Select secure attribute. */ 7954 #define SPU_DPPI_PERM_CHANNEL1_Pos (1UL) /*!< Position of CHANNEL1 field. */ 7955 #define SPU_DPPI_PERM_CHANNEL1_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL1_Pos) /*!< Bit mask of CHANNEL1 field. */ 7956 #define SPU_DPPI_PERM_CHANNEL1_NonSecure (0UL) /*!< Channel1 has its non-secure attribute set */ 7957 #define SPU_DPPI_PERM_CHANNEL1_Secure (1UL) /*!< Channel1 has its secure attribute set */ 7958 7959 /* Bit 0 : Select secure attribute. */ 7960 #define SPU_DPPI_PERM_CHANNEL0_Pos (0UL) /*!< Position of CHANNEL0 field. */ 7961 #define SPU_DPPI_PERM_CHANNEL0_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL0_Pos) /*!< Bit mask of CHANNEL0 field. */ 7962 #define SPU_DPPI_PERM_CHANNEL0_NonSecure (0UL) /*!< Channel0 has its non-secure attribute set */ 7963 #define SPU_DPPI_PERM_CHANNEL0_Secure (1UL) /*!< Channel0 has its secure attribute set */ 7964 7965 /* Register: SPU_DPPI_LOCK */ 7966 /* Description: Description cluster: Prevent further modification of the corresponding PERM register */ 7967 7968 /* Bit 0 : */ 7969 #define SPU_DPPI_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */ 7970 #define SPU_DPPI_LOCK_LOCK_Msk (0x1UL << SPU_DPPI_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */ 7971 #define SPU_DPPI_LOCK_LOCK_Unlocked (0UL) /*!< DPPI[n].PERM register content can be changed */ 7972 #define SPU_DPPI_LOCK_LOCK_Locked (1UL) /*!< DPPI[n].PERM register can't be changed until next reset */ 7973 7974 /* Register: SPU_GPIOPORT_PERM */ 7975 /* Description: Description cluster: Select between secure and non-secure attribute for pins 0 to 31 of port n. */ 7976 7977 /* Bit 31 : Select secure attribute attribute for PIN 31. */ 7978 #define SPU_GPIOPORT_PERM_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 7979 #define SPU_GPIOPORT_PERM_PIN31_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 7980 #define SPU_GPIOPORT_PERM_PIN31_NonSecure (0UL) /*!< Pin 31 has its non-secure attribute set */ 7981 #define SPU_GPIOPORT_PERM_PIN31_Secure (1UL) /*!< Pin 31 has its secure attribute set */ 7982 7983 /* Bit 30 : Select secure attribute attribute for PIN 30. */ 7984 #define SPU_GPIOPORT_PERM_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 7985 #define SPU_GPIOPORT_PERM_PIN30_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 7986 #define SPU_GPIOPORT_PERM_PIN30_NonSecure (0UL) /*!< Pin 30 has its non-secure attribute set */ 7987 #define SPU_GPIOPORT_PERM_PIN30_Secure (1UL) /*!< Pin 30 has its secure attribute set */ 7988 7989 /* Bit 29 : Select secure attribute attribute for PIN 29. */ 7990 #define SPU_GPIOPORT_PERM_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 7991 #define SPU_GPIOPORT_PERM_PIN29_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 7992 #define SPU_GPIOPORT_PERM_PIN29_NonSecure (0UL) /*!< Pin 29 has its non-secure attribute set */ 7993 #define SPU_GPIOPORT_PERM_PIN29_Secure (1UL) /*!< Pin 29 has its secure attribute set */ 7994 7995 /* Bit 28 : Select secure attribute attribute for PIN 28. */ 7996 #define SPU_GPIOPORT_PERM_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 7997 #define SPU_GPIOPORT_PERM_PIN28_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 7998 #define SPU_GPIOPORT_PERM_PIN28_NonSecure (0UL) /*!< Pin 28 has its non-secure attribute set */ 7999 #define SPU_GPIOPORT_PERM_PIN28_Secure (1UL) /*!< Pin 28 has its secure attribute set */ 8000 8001 /* Bit 27 : Select secure attribute attribute for PIN 27. */ 8002 #define SPU_GPIOPORT_PERM_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 8003 #define SPU_GPIOPORT_PERM_PIN27_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 8004 #define SPU_GPIOPORT_PERM_PIN27_NonSecure (0UL) /*!< Pin 27 has its non-secure attribute set */ 8005 #define SPU_GPIOPORT_PERM_PIN27_Secure (1UL) /*!< Pin 27 has its secure attribute set */ 8006 8007 /* Bit 26 : Select secure attribute attribute for PIN 26. */ 8008 #define SPU_GPIOPORT_PERM_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 8009 #define SPU_GPIOPORT_PERM_PIN26_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 8010 #define SPU_GPIOPORT_PERM_PIN26_NonSecure (0UL) /*!< Pin 26 has its non-secure attribute set */ 8011 #define SPU_GPIOPORT_PERM_PIN26_Secure (1UL) /*!< Pin 26 has its secure attribute set */ 8012 8013 /* Bit 25 : Select secure attribute attribute for PIN 25. */ 8014 #define SPU_GPIOPORT_PERM_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 8015 #define SPU_GPIOPORT_PERM_PIN25_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 8016 #define SPU_GPIOPORT_PERM_PIN25_NonSecure (0UL) /*!< Pin 25 has its non-secure attribute set */ 8017 #define SPU_GPIOPORT_PERM_PIN25_Secure (1UL) /*!< Pin 25 has its secure attribute set */ 8018 8019 /* Bit 24 : Select secure attribute attribute for PIN 24. */ 8020 #define SPU_GPIOPORT_PERM_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 8021 #define SPU_GPIOPORT_PERM_PIN24_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 8022 #define SPU_GPIOPORT_PERM_PIN24_NonSecure (0UL) /*!< Pin 24 has its non-secure attribute set */ 8023 #define SPU_GPIOPORT_PERM_PIN24_Secure (1UL) /*!< Pin 24 has its secure attribute set */ 8024 8025 /* Bit 23 : Select secure attribute attribute for PIN 23. */ 8026 #define SPU_GPIOPORT_PERM_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 8027 #define SPU_GPIOPORT_PERM_PIN23_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 8028 #define SPU_GPIOPORT_PERM_PIN23_NonSecure (0UL) /*!< Pin 23 has its non-secure attribute set */ 8029 #define SPU_GPIOPORT_PERM_PIN23_Secure (1UL) /*!< Pin 23 has its secure attribute set */ 8030 8031 /* Bit 22 : Select secure attribute attribute for PIN 22. */ 8032 #define SPU_GPIOPORT_PERM_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 8033 #define SPU_GPIOPORT_PERM_PIN22_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 8034 #define SPU_GPIOPORT_PERM_PIN22_NonSecure (0UL) /*!< Pin 22 has its non-secure attribute set */ 8035 #define SPU_GPIOPORT_PERM_PIN22_Secure (1UL) /*!< Pin 22 has its secure attribute set */ 8036 8037 /* Bit 21 : Select secure attribute attribute for PIN 21. */ 8038 #define SPU_GPIOPORT_PERM_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 8039 #define SPU_GPIOPORT_PERM_PIN21_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 8040 #define SPU_GPIOPORT_PERM_PIN21_NonSecure (0UL) /*!< Pin 21 has its non-secure attribute set */ 8041 #define SPU_GPIOPORT_PERM_PIN21_Secure (1UL) /*!< Pin 21 has its secure attribute set */ 8042 8043 /* Bit 20 : Select secure attribute attribute for PIN 20. */ 8044 #define SPU_GPIOPORT_PERM_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 8045 #define SPU_GPIOPORT_PERM_PIN20_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 8046 #define SPU_GPIOPORT_PERM_PIN20_NonSecure (0UL) /*!< Pin 20 has its non-secure attribute set */ 8047 #define SPU_GPIOPORT_PERM_PIN20_Secure (1UL) /*!< Pin 20 has its secure attribute set */ 8048 8049 /* Bit 19 : Select secure attribute attribute for PIN 19. */ 8050 #define SPU_GPIOPORT_PERM_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 8051 #define SPU_GPIOPORT_PERM_PIN19_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 8052 #define SPU_GPIOPORT_PERM_PIN19_NonSecure (0UL) /*!< Pin 19 has its non-secure attribute set */ 8053 #define SPU_GPIOPORT_PERM_PIN19_Secure (1UL) /*!< Pin 19 has its secure attribute set */ 8054 8055 /* Bit 18 : Select secure attribute attribute for PIN 18. */ 8056 #define SPU_GPIOPORT_PERM_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 8057 #define SPU_GPIOPORT_PERM_PIN18_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 8058 #define SPU_GPIOPORT_PERM_PIN18_NonSecure (0UL) /*!< Pin 18 has its non-secure attribute set */ 8059 #define SPU_GPIOPORT_PERM_PIN18_Secure (1UL) /*!< Pin 18 has its secure attribute set */ 8060 8061 /* Bit 17 : Select secure attribute attribute for PIN 17. */ 8062 #define SPU_GPIOPORT_PERM_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 8063 #define SPU_GPIOPORT_PERM_PIN17_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 8064 #define SPU_GPIOPORT_PERM_PIN17_NonSecure (0UL) /*!< Pin 17 has its non-secure attribute set */ 8065 #define SPU_GPIOPORT_PERM_PIN17_Secure (1UL) /*!< Pin 17 has its secure attribute set */ 8066 8067 /* Bit 16 : Select secure attribute attribute for PIN 16. */ 8068 #define SPU_GPIOPORT_PERM_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 8069 #define SPU_GPIOPORT_PERM_PIN16_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 8070 #define SPU_GPIOPORT_PERM_PIN16_NonSecure (0UL) /*!< Pin 16 has its non-secure attribute set */ 8071 #define SPU_GPIOPORT_PERM_PIN16_Secure (1UL) /*!< Pin 16 has its secure attribute set */ 8072 8073 /* Bit 15 : Select secure attribute attribute for PIN 15. */ 8074 #define SPU_GPIOPORT_PERM_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 8075 #define SPU_GPIOPORT_PERM_PIN15_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 8076 #define SPU_GPIOPORT_PERM_PIN15_NonSecure (0UL) /*!< Pin 15 has its non-secure attribute set */ 8077 #define SPU_GPIOPORT_PERM_PIN15_Secure (1UL) /*!< Pin 15 has its secure attribute set */ 8078 8079 /* Bit 14 : Select secure attribute attribute for PIN 14. */ 8080 #define SPU_GPIOPORT_PERM_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 8081 #define SPU_GPIOPORT_PERM_PIN14_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 8082 #define SPU_GPIOPORT_PERM_PIN14_NonSecure (0UL) /*!< Pin 14 has its non-secure attribute set */ 8083 #define SPU_GPIOPORT_PERM_PIN14_Secure (1UL) /*!< Pin 14 has its secure attribute set */ 8084 8085 /* Bit 13 : Select secure attribute attribute for PIN 13. */ 8086 #define SPU_GPIOPORT_PERM_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 8087 #define SPU_GPIOPORT_PERM_PIN13_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 8088 #define SPU_GPIOPORT_PERM_PIN13_NonSecure (0UL) /*!< Pin 13 has its non-secure attribute set */ 8089 #define SPU_GPIOPORT_PERM_PIN13_Secure (1UL) /*!< Pin 13 has its secure attribute set */ 8090 8091 /* Bit 12 : Select secure attribute attribute for PIN 12. */ 8092 #define SPU_GPIOPORT_PERM_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 8093 #define SPU_GPIOPORT_PERM_PIN12_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 8094 #define SPU_GPIOPORT_PERM_PIN12_NonSecure (0UL) /*!< Pin 12 has its non-secure attribute set */ 8095 #define SPU_GPIOPORT_PERM_PIN12_Secure (1UL) /*!< Pin 12 has its secure attribute set */ 8096 8097 /* Bit 11 : Select secure attribute attribute for PIN 11. */ 8098 #define SPU_GPIOPORT_PERM_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 8099 #define SPU_GPIOPORT_PERM_PIN11_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 8100 #define SPU_GPIOPORT_PERM_PIN11_NonSecure (0UL) /*!< Pin 11 has its non-secure attribute set */ 8101 #define SPU_GPIOPORT_PERM_PIN11_Secure (1UL) /*!< Pin 11 has its secure attribute set */ 8102 8103 /* Bit 10 : Select secure attribute attribute for PIN 10. */ 8104 #define SPU_GPIOPORT_PERM_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 8105 #define SPU_GPIOPORT_PERM_PIN10_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 8106 #define SPU_GPIOPORT_PERM_PIN10_NonSecure (0UL) /*!< Pin 10 has its non-secure attribute set */ 8107 #define SPU_GPIOPORT_PERM_PIN10_Secure (1UL) /*!< Pin 10 has its secure attribute set */ 8108 8109 /* Bit 9 : Select secure attribute attribute for PIN 9. */ 8110 #define SPU_GPIOPORT_PERM_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 8111 #define SPU_GPIOPORT_PERM_PIN9_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 8112 #define SPU_GPIOPORT_PERM_PIN9_NonSecure (0UL) /*!< Pin 9 has its non-secure attribute set */ 8113 #define SPU_GPIOPORT_PERM_PIN9_Secure (1UL) /*!< Pin 9 has its secure attribute set */ 8114 8115 /* Bit 8 : Select secure attribute attribute for PIN 8. */ 8116 #define SPU_GPIOPORT_PERM_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 8117 #define SPU_GPIOPORT_PERM_PIN8_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 8118 #define SPU_GPIOPORT_PERM_PIN8_NonSecure (0UL) /*!< Pin 8 has its non-secure attribute set */ 8119 #define SPU_GPIOPORT_PERM_PIN8_Secure (1UL) /*!< Pin 8 has its secure attribute set */ 8120 8121 /* Bit 7 : Select secure attribute attribute for PIN 7. */ 8122 #define SPU_GPIOPORT_PERM_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 8123 #define SPU_GPIOPORT_PERM_PIN7_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 8124 #define SPU_GPIOPORT_PERM_PIN7_NonSecure (0UL) /*!< Pin 7 has its non-secure attribute set */ 8125 #define SPU_GPIOPORT_PERM_PIN7_Secure (1UL) /*!< Pin 7 has its secure attribute set */ 8126 8127 /* Bit 6 : Select secure attribute attribute for PIN 6. */ 8128 #define SPU_GPIOPORT_PERM_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 8129 #define SPU_GPIOPORT_PERM_PIN6_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 8130 #define SPU_GPIOPORT_PERM_PIN6_NonSecure (0UL) /*!< Pin 6 has its non-secure attribute set */ 8131 #define SPU_GPIOPORT_PERM_PIN6_Secure (1UL) /*!< Pin 6 has its secure attribute set */ 8132 8133 /* Bit 5 : Select secure attribute attribute for PIN 5. */ 8134 #define SPU_GPIOPORT_PERM_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 8135 #define SPU_GPIOPORT_PERM_PIN5_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 8136 #define SPU_GPIOPORT_PERM_PIN5_NonSecure (0UL) /*!< Pin 5 has its non-secure attribute set */ 8137 #define SPU_GPIOPORT_PERM_PIN5_Secure (1UL) /*!< Pin 5 has its secure attribute set */ 8138 8139 /* Bit 4 : Select secure attribute attribute for PIN 4. */ 8140 #define SPU_GPIOPORT_PERM_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 8141 #define SPU_GPIOPORT_PERM_PIN4_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 8142 #define SPU_GPIOPORT_PERM_PIN4_NonSecure (0UL) /*!< Pin 4 has its non-secure attribute set */ 8143 #define SPU_GPIOPORT_PERM_PIN4_Secure (1UL) /*!< Pin 4 has its secure attribute set */ 8144 8145 /* Bit 3 : Select secure attribute attribute for PIN 3. */ 8146 #define SPU_GPIOPORT_PERM_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 8147 #define SPU_GPIOPORT_PERM_PIN3_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 8148 #define SPU_GPIOPORT_PERM_PIN3_NonSecure (0UL) /*!< Pin 3 has its non-secure attribute set */ 8149 #define SPU_GPIOPORT_PERM_PIN3_Secure (1UL) /*!< Pin 3 has its secure attribute set */ 8150 8151 /* Bit 2 : Select secure attribute attribute for PIN 2. */ 8152 #define SPU_GPIOPORT_PERM_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 8153 #define SPU_GPIOPORT_PERM_PIN2_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 8154 #define SPU_GPIOPORT_PERM_PIN2_NonSecure (0UL) /*!< Pin 2 has its non-secure attribute set */ 8155 #define SPU_GPIOPORT_PERM_PIN2_Secure (1UL) /*!< Pin 2 has its secure attribute set */ 8156 8157 /* Bit 1 : Select secure attribute attribute for PIN 1. */ 8158 #define SPU_GPIOPORT_PERM_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 8159 #define SPU_GPIOPORT_PERM_PIN1_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 8160 #define SPU_GPIOPORT_PERM_PIN1_NonSecure (0UL) /*!< Pin 1 has its non-secure attribute set */ 8161 #define SPU_GPIOPORT_PERM_PIN1_Secure (1UL) /*!< Pin 1 has its secure attribute set */ 8162 8163 /* Bit 0 : Select secure attribute attribute for PIN 0. */ 8164 #define SPU_GPIOPORT_PERM_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 8165 #define SPU_GPIOPORT_PERM_PIN0_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 8166 #define SPU_GPIOPORT_PERM_PIN0_NonSecure (0UL) /*!< Pin 0 has its non-secure attribute set */ 8167 #define SPU_GPIOPORT_PERM_PIN0_Secure (1UL) /*!< Pin 0 has its secure attribute set */ 8168 8169 /* Register: SPU_GPIOPORT_LOCK */ 8170 /* Description: Description cluster: Prevent further modification of the corresponding PERM register */ 8171 8172 /* Bit 0 : */ 8173 #define SPU_GPIOPORT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */ 8174 #define SPU_GPIOPORT_LOCK_LOCK_Msk (0x1UL << SPU_GPIOPORT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */ 8175 #define SPU_GPIOPORT_LOCK_LOCK_Unlocked (0UL) /*!< GPIOPORT[n].PERM register content can be changed */ 8176 #define SPU_GPIOPORT_LOCK_LOCK_Locked (1UL) /*!< GPIOPORT[n].PERM register can't be changed until next reset */ 8177 8178 /* Register: SPU_FLASHNSC_REGION */ 8179 /* Description: Description cluster: Define which flash region can contain the non-secure callable (NSC) region n */ 8180 8181 /* Bit 8 : */ 8182 #define SPU_FLASHNSC_REGION_LOCK_Pos (8UL) /*!< Position of LOCK field. */ 8183 #define SPU_FLASHNSC_REGION_LOCK_Msk (0x1UL << SPU_FLASHNSC_REGION_LOCK_Pos) /*!< Bit mask of LOCK field. */ 8184 #define SPU_FLASHNSC_REGION_LOCK_Unlocked (0UL) /*!< This register can be updated */ 8185 #define SPU_FLASHNSC_REGION_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */ 8186 8187 /* Bits 4..0 : Region number */ 8188 #define SPU_FLASHNSC_REGION_REGION_Pos (0UL) /*!< Position of REGION field. */ 8189 #define SPU_FLASHNSC_REGION_REGION_Msk (0x1FUL << SPU_FLASHNSC_REGION_REGION_Pos) /*!< Bit mask of REGION field. */ 8190 8191 /* Register: SPU_FLASHNSC_SIZE */ 8192 /* Description: Description cluster: Define the size of the non-secure callable (NSC) region n */ 8193 8194 /* Bit 8 : */ 8195 #define SPU_FLASHNSC_SIZE_LOCK_Pos (8UL) /*!< Position of LOCK field. */ 8196 #define SPU_FLASHNSC_SIZE_LOCK_Msk (0x1UL << SPU_FLASHNSC_SIZE_LOCK_Pos) /*!< Bit mask of LOCK field. */ 8197 #define SPU_FLASHNSC_SIZE_LOCK_Unlocked (0UL) /*!< This register can be updated */ 8198 #define SPU_FLASHNSC_SIZE_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */ 8199 8200 /* Bits 3..0 : Size of the non-secure callable (NSC) region n */ 8201 #define SPU_FLASHNSC_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ 8202 #define SPU_FLASHNSC_SIZE_SIZE_Msk (0xFUL << SPU_FLASHNSC_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */ 8203 #define SPU_FLASHNSC_SIZE_SIZE_Disabled (0UL) /*!< The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. */ 8204 #define SPU_FLASHNSC_SIZE_SIZE_32 (1UL) /*!< The region n is defined as non-secure callable with a 32-byte size */ 8205 #define SPU_FLASHNSC_SIZE_SIZE_64 (2UL) /*!< The region n is defined as non-secure callable with a 64-byte size */ 8206 #define SPU_FLASHNSC_SIZE_SIZE_128 (3UL) /*!< The region n is defined as non-secure callable with a 128-byte size */ 8207 #define SPU_FLASHNSC_SIZE_SIZE_256 (4UL) /*!< The region n is defined as non-secure callable with a 256-byte size */ 8208 #define SPU_FLASHNSC_SIZE_SIZE_512 (5UL) /*!< The region n is defined as non-secure callable with a 512-byte size */ 8209 #define SPU_FLASHNSC_SIZE_SIZE_1024 (6UL) /*!< The region n is defined as non-secure callable with a 1024-byte size */ 8210 #define SPU_FLASHNSC_SIZE_SIZE_2048 (7UL) /*!< The region n is defined as non-secure callable with a 2048-byte size */ 8211 #define SPU_FLASHNSC_SIZE_SIZE_4096 (8UL) /*!< The region n is defined as non-secure callable with a 4096-byte size */ 8212 8213 /* Register: SPU_RAMNSC_REGION */ 8214 /* Description: Description cluster: Define which RAM region can contain the non-secure callable (NSC) region n */ 8215 8216 /* Bit 8 : */ 8217 #define SPU_RAMNSC_REGION_LOCK_Pos (8UL) /*!< Position of LOCK field. */ 8218 #define SPU_RAMNSC_REGION_LOCK_Msk (0x1UL << SPU_RAMNSC_REGION_LOCK_Pos) /*!< Bit mask of LOCK field. */ 8219 #define SPU_RAMNSC_REGION_LOCK_Unlocked (0UL) /*!< This register can be updated */ 8220 #define SPU_RAMNSC_REGION_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */ 8221 8222 /* Bits 4..0 : Region number */ 8223 #define SPU_RAMNSC_REGION_REGION_Pos (0UL) /*!< Position of REGION field. */ 8224 #define SPU_RAMNSC_REGION_REGION_Msk (0x1FUL << SPU_RAMNSC_REGION_REGION_Pos) /*!< Bit mask of REGION field. */ 8225 8226 /* Register: SPU_RAMNSC_SIZE */ 8227 /* Description: Description cluster: Define the size of the non-secure callable (NSC) region n */ 8228 8229 /* Bit 8 : */ 8230 #define SPU_RAMNSC_SIZE_LOCK_Pos (8UL) /*!< Position of LOCK field. */ 8231 #define SPU_RAMNSC_SIZE_LOCK_Msk (0x1UL << SPU_RAMNSC_SIZE_LOCK_Pos) /*!< Bit mask of LOCK field. */ 8232 #define SPU_RAMNSC_SIZE_LOCK_Unlocked (0UL) /*!< This register can be updated */ 8233 #define SPU_RAMNSC_SIZE_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */ 8234 8235 /* Bits 3..0 : Size of the non-secure callable (NSC) region n */ 8236 #define SPU_RAMNSC_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ 8237 #define SPU_RAMNSC_SIZE_SIZE_Msk (0xFUL << SPU_RAMNSC_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */ 8238 #define SPU_RAMNSC_SIZE_SIZE_Disabled (0UL) /*!< The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. */ 8239 #define SPU_RAMNSC_SIZE_SIZE_32 (1UL) /*!< The region n is defined as non-secure callable with a 32-byte size */ 8240 #define SPU_RAMNSC_SIZE_SIZE_64 (2UL) /*!< The region n is defined as non-secure callable with a 64-byte size */ 8241 #define SPU_RAMNSC_SIZE_SIZE_128 (3UL) /*!< The region n is defined as non-secure callable with a 128-byte size */ 8242 #define SPU_RAMNSC_SIZE_SIZE_256 (4UL) /*!< The region n is defined as non-secure callable with a 256-byte size */ 8243 #define SPU_RAMNSC_SIZE_SIZE_512 (5UL) /*!< The region n is defined as non-secure callable with a 512-byte size */ 8244 #define SPU_RAMNSC_SIZE_SIZE_1024 (6UL) /*!< The region n is defined as non-secure callable with a 1024-byte size */ 8245 #define SPU_RAMNSC_SIZE_SIZE_2048 (7UL) /*!< The region n is defined as non-secure callable with a 2048-byte size */ 8246 #define SPU_RAMNSC_SIZE_SIZE_4096 (8UL) /*!< The region n is defined as non-secure callable with a 4096-byte size */ 8247 8248 /* Register: SPU_FLASHREGION_PERM */ 8249 /* Description: Description cluster: Access permissions for flash region n */ 8250 8251 /* Bit 8 : */ 8252 #define SPU_FLASHREGION_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */ 8253 #define SPU_FLASHREGION_PERM_LOCK_Msk (0x1UL << SPU_FLASHREGION_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */ 8254 #define SPU_FLASHREGION_PERM_LOCK_Unlocked (0UL) /*!< This register can be updated */ 8255 #define SPU_FLASHREGION_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */ 8256 8257 /* Bit 4 : Security attribute for flash region n */ 8258 #define SPU_FLASHREGION_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ 8259 #define SPU_FLASHREGION_PERM_SECATTR_Msk (0x1UL << SPU_FLASHREGION_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ 8260 #define SPU_FLASHREGION_PERM_SECATTR_Non_Secure (0UL) /*!< Flash region n security attribute is non-secure */ 8261 #define SPU_FLASHREGION_PERM_SECATTR_Secure (1UL) /*!< Flash region n security attribute is secure */ 8262 8263 /* Bit 2 : Configure read permissions for flash region n */ 8264 #define SPU_FLASHREGION_PERM_READ_Pos (2UL) /*!< Position of READ field. */ 8265 #define SPU_FLASHREGION_PERM_READ_Msk (0x1UL << SPU_FLASHREGION_PERM_READ_Pos) /*!< Bit mask of READ field. */ 8266 #define SPU_FLASHREGION_PERM_READ_Disable (0UL) /*!< Block read operation from flash region n */ 8267 #define SPU_FLASHREGION_PERM_READ_Enable (1UL) /*!< Allow read operation from flash region n */ 8268 8269 /* Bit 1 : Configure write permission for flash region n */ 8270 #define SPU_FLASHREGION_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */ 8271 #define SPU_FLASHREGION_PERM_WRITE_Msk (0x1UL << SPU_FLASHREGION_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */ 8272 #define SPU_FLASHREGION_PERM_WRITE_Disable (0UL) /*!< Block write operation to region n */ 8273 #define SPU_FLASHREGION_PERM_WRITE_Enable (1UL) /*!< Allow write operation to region n */ 8274 8275 /* Bit 0 : Configure instruction fetch permissions from flash region n */ 8276 #define SPU_FLASHREGION_PERM_EXECUTE_Pos (0UL) /*!< Position of EXECUTE field. */ 8277 #define SPU_FLASHREGION_PERM_EXECUTE_Msk (0x1UL << SPU_FLASHREGION_PERM_EXECUTE_Pos) /*!< Bit mask of EXECUTE field. */ 8278 #define SPU_FLASHREGION_PERM_EXECUTE_Disable (0UL) /*!< Block instruction fetches from flash region n */ 8279 #define SPU_FLASHREGION_PERM_EXECUTE_Enable (1UL) /*!< Allow instruction fetches from flash region n */ 8280 8281 /* Register: SPU_RAMREGION_PERM */ 8282 /* Description: Description cluster: Access permissions for RAM region n */ 8283 8284 /* Bit 8 : */ 8285 #define SPU_RAMREGION_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */ 8286 #define SPU_RAMREGION_PERM_LOCK_Msk (0x1UL << SPU_RAMREGION_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */ 8287 #define SPU_RAMREGION_PERM_LOCK_Unlocked (0UL) /*!< This register can be updated */ 8288 #define SPU_RAMREGION_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */ 8289 8290 /* Bit 4 : Security attribute for RAM region n */ 8291 #define SPU_RAMREGION_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ 8292 #define SPU_RAMREGION_PERM_SECATTR_Msk (0x1UL << SPU_RAMREGION_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ 8293 #define SPU_RAMREGION_PERM_SECATTR_Non_Secure (0UL) /*!< RAM region n security attribute is non-secure */ 8294 #define SPU_RAMREGION_PERM_SECATTR_Secure (1UL) /*!< RAM region n security attribute is secure */ 8295 8296 /* Bit 2 : Configure read permissions for RAM region n */ 8297 #define SPU_RAMREGION_PERM_READ_Pos (2UL) /*!< Position of READ field. */ 8298 #define SPU_RAMREGION_PERM_READ_Msk (0x1UL << SPU_RAMREGION_PERM_READ_Pos) /*!< Bit mask of READ field. */ 8299 #define SPU_RAMREGION_PERM_READ_Disable (0UL) /*!< Block read operation from RAM region n */ 8300 #define SPU_RAMREGION_PERM_READ_Enable (1UL) /*!< Allow read operation from RAM region n */ 8301 8302 /* Bit 1 : Configure write permission for RAM region n */ 8303 #define SPU_RAMREGION_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */ 8304 #define SPU_RAMREGION_PERM_WRITE_Msk (0x1UL << SPU_RAMREGION_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */ 8305 #define SPU_RAMREGION_PERM_WRITE_Disable (0UL) /*!< Block write operation to RAM region n */ 8306 #define SPU_RAMREGION_PERM_WRITE_Enable (1UL) /*!< Allow write operation to RAM region n */ 8307 8308 /* Bit 0 : Configure instruction fetch permissions from RAM region n */ 8309 #define SPU_RAMREGION_PERM_EXECUTE_Pos (0UL) /*!< Position of EXECUTE field. */ 8310 #define SPU_RAMREGION_PERM_EXECUTE_Msk (0x1UL << SPU_RAMREGION_PERM_EXECUTE_Pos) /*!< Bit mask of EXECUTE field. */ 8311 #define SPU_RAMREGION_PERM_EXECUTE_Disable (0UL) /*!< Block instruction fetches from RAM region n */ 8312 #define SPU_RAMREGION_PERM_EXECUTE_Enable (1UL) /*!< Allow instruction fetches from RAM region n */ 8313 8314 /* Register: SPU_PERIPHID_PERM */ 8315 /* Description: Description cluster: List capabilities and access permissions for the peripheral with ID n */ 8316 8317 /* Bit 31 : Indicate if a peripheral is present with ID n */ 8318 #define SPU_PERIPHID_PERM_PRESENT_Pos (31UL) /*!< Position of PRESENT field. */ 8319 #define SPU_PERIPHID_PERM_PRESENT_Msk (0x1UL << SPU_PERIPHID_PERM_PRESENT_Pos) /*!< Bit mask of PRESENT field. */ 8320 #define SPU_PERIPHID_PERM_PRESENT_NotPresent (0UL) /*!< Peripheral is not present */ 8321 #define SPU_PERIPHID_PERM_PRESENT_IsPresent (1UL) /*!< Peripheral is present */ 8322 8323 /* Bit 8 : */ 8324 #define SPU_PERIPHID_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */ 8325 #define SPU_PERIPHID_PERM_LOCK_Msk (0x1UL << SPU_PERIPHID_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */ 8326 #define SPU_PERIPHID_PERM_LOCK_Unlocked (0UL) /*!< This register can be updated */ 8327 #define SPU_PERIPHID_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */ 8328 8329 /* Bit 5 : Security attribution for the DMA transfer */ 8330 #define SPU_PERIPHID_PERM_DMASEC_Pos (5UL) /*!< Position of DMASEC field. */ 8331 #define SPU_PERIPHID_PERM_DMASEC_Msk (0x1UL << SPU_PERIPHID_PERM_DMASEC_Pos) /*!< Bit mask of DMASEC field. */ 8332 #define SPU_PERIPHID_PERM_DMASEC_NonSecure (0UL) /*!< DMA transfers initiated by this peripheral have the non-secure attribute set */ 8333 #define SPU_PERIPHID_PERM_DMASEC_Secure (1UL) /*!< DMA transfers initiated by this peripheral have the secure attribute set */ 8334 8335 /* Bit 4 : Peripheral security mapping */ 8336 #define SPU_PERIPHID_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ 8337 #define SPU_PERIPHID_PERM_SECATTR_Msk (0x1UL << SPU_PERIPHID_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ 8338 #define SPU_PERIPHID_PERM_SECATTR_NonSecure (0UL) /*!< If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure peripheral address space. If SECUREMAPPING == Split: Peripheral is mapped in non-secure and secure peripheral address space. */ 8339 #define SPU_PERIPHID_PERM_SECATTR_Secure (1UL) /*!< Peripheral is mapped in secure peripheral address space */ 8340 8341 /* Bits 3..2 : Indicate if the peripheral has DMA capabilities and if DMA transfer can be assigned to a different security attribute than the peripheral itself */ 8342 #define SPU_PERIPHID_PERM_DMA_Pos (2UL) /*!< Position of DMA field. */ 8343 #define SPU_PERIPHID_PERM_DMA_Msk (0x3UL << SPU_PERIPHID_PERM_DMA_Pos) /*!< Bit mask of DMA field. */ 8344 #define SPU_PERIPHID_PERM_DMA_NoDMA (0UL) /*!< Peripheral has no DMA capability */ 8345 #define SPU_PERIPHID_PERM_DMA_NoSeparateAttribute (1UL) /*!< Peripheral has DMA and DMA transfers always have the same security attribute as assigned to the peripheral */ 8346 #define SPU_PERIPHID_PERM_DMA_SeparateAttribute (2UL) /*!< Peripheral has DMA and DMA transfers can have a different security attribute than the one assigned to the peripheral */ 8347 8348 /* Bits 1..0 : Define configuration capabilities for TrustZone Cortex-M secure attribute */ 8349 #define SPU_PERIPHID_PERM_SECUREMAPPING_Pos (0UL) /*!< Position of SECUREMAPPING field. */ 8350 #define SPU_PERIPHID_PERM_SECUREMAPPING_Msk (0x3UL << SPU_PERIPHID_PERM_SECUREMAPPING_Pos) /*!< Bit mask of SECUREMAPPING field. */ 8351 #define SPU_PERIPHID_PERM_SECUREMAPPING_NonSecure (0UL) /*!< This peripheral is always accessible as a non-secure peripheral */ 8352 #define SPU_PERIPHID_PERM_SECUREMAPPING_Secure (1UL) /*!< This peripheral is always accessible as a secure peripheral */ 8353 #define SPU_PERIPHID_PERM_SECUREMAPPING_UserSelectable (2UL) /*!< Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register */ 8354 #define SPU_PERIPHID_PERM_SECUREMAPPING_Split (3UL) /*!< This peripheral implements the split security mechanism. Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register. */ 8355 8356 8357 /* Peripheral: TAD */ 8358 /* Description: Trace and debug control */ 8359 8360 /* Register: TAD_TASKS_CLOCKSTART */ 8361 /* Description: Start all trace and debug clocks. */ 8362 8363 /* Bit 0 : Start all trace and debug clocks. */ 8364 #define TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Pos (0UL) /*!< Position of TASKS_CLOCKSTART field. */ 8365 #define TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Msk (0x1UL << TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Pos) /*!< Bit mask of TASKS_CLOCKSTART field. */ 8366 #define TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Trigger (1UL) /*!< Trigger task */ 8367 8368 /* Register: TAD_TASKS_CLOCKSTOP */ 8369 /* Description: Stop all trace and debug clocks. */ 8370 8371 /* Bit 0 : Stop all trace and debug clocks. */ 8372 #define TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Pos (0UL) /*!< Position of TASKS_CLOCKSTOP field. */ 8373 #define TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Msk (0x1UL << TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Pos) /*!< Bit mask of TASKS_CLOCKSTOP field. */ 8374 #define TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Trigger (1UL) /*!< Trigger task */ 8375 8376 /* Register: TAD_ENABLE */ 8377 /* Description: Enable debug domain and aquire selected GPIOs */ 8378 8379 /* Bit 0 : */ 8380 #define TAD_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 8381 #define TAD_ENABLE_ENABLE_Msk (0x1UL << TAD_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 8382 #define TAD_ENABLE_ENABLE_DISABLED (0UL) /*!< Disable debug domain and release selected GPIOs */ 8383 #define TAD_ENABLE_ENABLE_ENABLED (1UL) /*!< Enable debug domain and aquire selected GPIOs */ 8384 8385 /* Register: TAD_PSEL_TRACECLK */ 8386 /* Description: Pin configuration for TRACECLK */ 8387 8388 /* Bit 31 : Connection */ 8389 #define TAD_PSEL_TRACECLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 8390 #define TAD_PSEL_TRACECLK_CONNECT_Msk (0x1UL << TAD_PSEL_TRACECLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 8391 #define TAD_PSEL_TRACECLK_CONNECT_Connected (0UL) /*!< Connect */ 8392 #define TAD_PSEL_TRACECLK_CONNECT_Disconnected (1UL) /*!< Disconnect */ 8393 8394 /* Bits 4..0 : Pin number */ 8395 #define TAD_PSEL_TRACECLK_PIN_Pos (0UL) /*!< Position of PIN field. */ 8396 #define TAD_PSEL_TRACECLK_PIN_Msk (0x1FUL << TAD_PSEL_TRACECLK_PIN_Pos) /*!< Bit mask of PIN field. */ 8397 #define TAD_PSEL_TRACECLK_PIN_Traceclk (21UL) /*!< TRACECLK pin */ 8398 8399 /* Register: TAD_PSEL_TRACEDATA0 */ 8400 /* Description: Pin configuration for TRACEDATA[0] */ 8401 8402 /* Bit 31 : Connection */ 8403 #define TAD_PSEL_TRACEDATA0_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 8404 #define TAD_PSEL_TRACEDATA0_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA0_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 8405 #define TAD_PSEL_TRACEDATA0_CONNECT_Connected (0UL) /*!< Connect */ 8406 #define TAD_PSEL_TRACEDATA0_CONNECT_Disconnected (1UL) /*!< Disconnect */ 8407 8408 /* Bits 4..0 : Pin number */ 8409 #define TAD_PSEL_TRACEDATA0_PIN_Pos (0UL) /*!< Position of PIN field. */ 8410 #define TAD_PSEL_TRACEDATA0_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA0_PIN_Pos) /*!< Bit mask of PIN field. */ 8411 #define TAD_PSEL_TRACEDATA0_PIN_Tracedata0 (22UL) /*!< TRACEDATA0 pin */ 8412 8413 /* Register: TAD_PSEL_TRACEDATA1 */ 8414 /* Description: Pin configuration for TRACEDATA[1] */ 8415 8416 /* Bit 31 : Connection */ 8417 #define TAD_PSEL_TRACEDATA1_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 8418 #define TAD_PSEL_TRACEDATA1_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA1_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 8419 #define TAD_PSEL_TRACEDATA1_CONNECT_Connected (0UL) /*!< Connect */ 8420 #define TAD_PSEL_TRACEDATA1_CONNECT_Disconnected (1UL) /*!< Disconnect */ 8421 8422 /* Bits 4..0 : Pin number */ 8423 #define TAD_PSEL_TRACEDATA1_PIN_Pos (0UL) /*!< Position of PIN field. */ 8424 #define TAD_PSEL_TRACEDATA1_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA1_PIN_Pos) /*!< Bit mask of PIN field. */ 8425 #define TAD_PSEL_TRACEDATA1_PIN_Tracedata1 (23UL) /*!< TRACEDATA1 pin */ 8426 8427 /* Register: TAD_PSEL_TRACEDATA2 */ 8428 /* Description: Pin configuration for TRACEDATA[2] */ 8429 8430 /* Bit 31 : Connection */ 8431 #define TAD_PSEL_TRACEDATA2_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 8432 #define TAD_PSEL_TRACEDATA2_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA2_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 8433 #define TAD_PSEL_TRACEDATA2_CONNECT_Connected (0UL) /*!< Connect */ 8434 #define TAD_PSEL_TRACEDATA2_CONNECT_Disconnected (1UL) /*!< Disconnect */ 8435 8436 /* Bits 4..0 : Pin number */ 8437 #define TAD_PSEL_TRACEDATA2_PIN_Pos (0UL) /*!< Position of PIN field. */ 8438 #define TAD_PSEL_TRACEDATA2_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA2_PIN_Pos) /*!< Bit mask of PIN field. */ 8439 #define TAD_PSEL_TRACEDATA2_PIN_Tracedata2 (24UL) /*!< TRACEDATA2 pin */ 8440 8441 /* Register: TAD_PSEL_TRACEDATA3 */ 8442 /* Description: Pin configuration for TRACEDATA[3] */ 8443 8444 /* Bit 31 : Connection */ 8445 #define TAD_PSEL_TRACEDATA3_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 8446 #define TAD_PSEL_TRACEDATA3_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA3_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 8447 #define TAD_PSEL_TRACEDATA3_CONNECT_Connected (0UL) /*!< Connect */ 8448 #define TAD_PSEL_TRACEDATA3_CONNECT_Disconnected (1UL) /*!< Disconnect */ 8449 8450 /* Bits 4..0 : Pin number */ 8451 #define TAD_PSEL_TRACEDATA3_PIN_Pos (0UL) /*!< Position of PIN field. */ 8452 #define TAD_PSEL_TRACEDATA3_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA3_PIN_Pos) /*!< Bit mask of PIN field. */ 8453 #define TAD_PSEL_TRACEDATA3_PIN_Tracedata3 (25UL) /*!< TRACEDATA3 pin */ 8454 8455 /* Register: TAD_TRACEPORTSPEED */ 8456 /* Description: Clocking options for the Trace Port debug interface Reset behavior is the same as debug components */ 8457 8458 /* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock. */ 8459 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */ 8460 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Msk (0x3UL << TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */ 8461 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz (0UL) /*!< Trace Port clock is: 32MHz */ 8462 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_16MHz (1UL) /*!< Trace Port clock is: 16MHz */ 8463 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_8MHz (2UL) /*!< Trace Port clock is: 8MHz */ 8464 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_4MHz (3UL) /*!< Trace Port clock is: 4MHz */ 8465 8466 8467 /* Peripheral: TIMER */ 8468 /* Description: Timer/Counter 0 */ 8469 8470 /* Register: TIMER_TASKS_START */ 8471 /* Description: Start Timer */ 8472 8473 /* Bit 0 : Start Timer */ 8474 #define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 8475 #define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 8476 #define TIMER_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ 8477 8478 /* Register: TIMER_TASKS_STOP */ 8479 /* Description: Stop Timer */ 8480 8481 /* Bit 0 : Stop Timer */ 8482 #define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 8483 #define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 8484 #define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 8485 8486 /* Register: TIMER_TASKS_COUNT */ 8487 /* Description: Increment Timer (Counter mode only) */ 8488 8489 /* Bit 0 : Increment Timer (Counter mode only) */ 8490 #define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */ 8491 #define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */ 8492 #define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL) /*!< Trigger task */ 8493 8494 /* Register: TIMER_TASKS_CLEAR */ 8495 /* Description: Clear time */ 8496 8497 /* Bit 0 : Clear time */ 8498 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ 8499 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ 8500 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */ 8501 8502 /* Register: TIMER_TASKS_SHUTDOWN */ 8503 /* Description: Deprecated register - Shut down timer */ 8504 8505 /* Bit 0 : Deprecated field - Shut down timer */ 8506 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */ 8507 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */ 8508 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL) /*!< Trigger task */ 8509 8510 /* Register: TIMER_TASKS_CAPTURE */ 8511 /* Description: Description collection: Capture Timer value to CC[n] register */ 8512 8513 /* Bit 0 : Capture Timer value to CC[n] register */ 8514 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */ 8515 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */ 8516 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */ 8517 8518 /* Register: TIMER_SUBSCRIBE_START */ 8519 /* Description: Subscribe configuration for task START */ 8520 8521 /* Bit 31 : */ 8522 #define TIMER_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ 8523 #define TIMER_SUBSCRIBE_START_EN_Msk (0x1UL << TIMER_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ 8524 #define TIMER_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ 8525 #define TIMER_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ 8526 8527 /* Bits 7..0 : DPPI channel that task START will subscribe to */ 8528 #define TIMER_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 8529 #define TIMER_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 8530 8531 /* Register: TIMER_SUBSCRIBE_STOP */ 8532 /* Description: Subscribe configuration for task STOP */ 8533 8534 /* Bit 31 : */ 8535 #define TIMER_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 8536 #define TIMER_SUBSCRIBE_STOP_EN_Msk (0x1UL << TIMER_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 8537 #define TIMER_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ 8538 #define TIMER_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ 8539 8540 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 8541 #define TIMER_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 8542 #define TIMER_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 8543 8544 /* Register: TIMER_SUBSCRIBE_COUNT */ 8545 /* Description: Subscribe configuration for task COUNT */ 8546 8547 /* Bit 31 : */ 8548 #define TIMER_SUBSCRIBE_COUNT_EN_Pos (31UL) /*!< Position of EN field. */ 8549 #define TIMER_SUBSCRIBE_COUNT_EN_Msk (0x1UL << TIMER_SUBSCRIBE_COUNT_EN_Pos) /*!< Bit mask of EN field. */ 8550 #define TIMER_SUBSCRIBE_COUNT_EN_Disabled (0UL) /*!< Disable subscription */ 8551 #define TIMER_SUBSCRIBE_COUNT_EN_Enabled (1UL) /*!< Enable subscription */ 8552 8553 /* Bits 7..0 : DPPI channel that task COUNT will subscribe to */ 8554 #define TIMER_SUBSCRIBE_COUNT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 8555 #define TIMER_SUBSCRIBE_COUNT_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_COUNT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 8556 8557 /* Register: TIMER_SUBSCRIBE_CLEAR */ 8558 /* Description: Subscribe configuration for task CLEAR */ 8559 8560 /* Bit 31 : */ 8561 #define TIMER_SUBSCRIBE_CLEAR_EN_Pos (31UL) /*!< Position of EN field. */ 8562 #define TIMER_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field. */ 8563 #define TIMER_SUBSCRIBE_CLEAR_EN_Disabled (0UL) /*!< Disable subscription */ 8564 #define TIMER_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */ 8565 8566 /* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */ 8567 #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 8568 #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 8569 8570 /* Register: TIMER_SUBSCRIBE_SHUTDOWN */ 8571 /* Description: Deprecated register - Subscribe configuration for task SHUTDOWN */ 8572 8573 /* Bit 31 : */ 8574 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos (31UL) /*!< Position of EN field. */ 8575 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Msk (0x1UL << TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos) /*!< Bit mask of EN field. */ 8576 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Disabled (0UL) /*!< Disable subscription */ 8577 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Enabled (1UL) /*!< Enable subscription */ 8578 8579 /* Bits 7..0 : DPPI channel that task SHUTDOWN will subscribe to */ 8580 #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 8581 #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 8582 8583 /* Register: TIMER_SUBSCRIBE_CAPTURE */ 8584 /* Description: Description collection: Subscribe configuration for task CAPTURE[n] */ 8585 8586 /* Bit 31 : */ 8587 #define TIMER_SUBSCRIBE_CAPTURE_EN_Pos (31UL) /*!< Position of EN field. */ 8588 #define TIMER_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CAPTURE_EN_Pos) /*!< Bit mask of EN field. */ 8589 #define TIMER_SUBSCRIBE_CAPTURE_EN_Disabled (0UL) /*!< Disable subscription */ 8590 #define TIMER_SUBSCRIBE_CAPTURE_EN_Enabled (1UL) /*!< Enable subscription */ 8591 8592 /* Bits 7..0 : DPPI channel that task CAPTURE[n] will subscribe to */ 8593 #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 8594 #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 8595 8596 /* Register: TIMER_EVENTS_COMPARE */ 8597 /* Description: Description collection: Compare event on CC[n] match */ 8598 8599 /* Bit 0 : Compare event on CC[n] match */ 8600 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ 8601 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ 8602 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */ 8603 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */ 8604 8605 /* Register: TIMER_PUBLISH_COMPARE */ 8606 /* Description: Description collection: Publish configuration for event COMPARE[n] */ 8607 8608 /* Bit 31 : */ 8609 #define TIMER_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */ 8610 #define TIMER_PUBLISH_COMPARE_EN_Msk (0x1UL << TIMER_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */ 8611 #define TIMER_PUBLISH_COMPARE_EN_Disabled (0UL) /*!< Disable publishing */ 8612 #define TIMER_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */ 8613 8614 /* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to */ 8615 #define TIMER_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 8616 #define TIMER_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << TIMER_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 8617 8618 /* Register: TIMER_SHORTS */ 8619 /* Description: Shortcuts between local events and tasks */ 8620 8621 /* Bit 13 : Shortcut between event COMPARE[5] and task STOP */ 8622 #define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */ 8623 #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */ 8624 #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */ 8625 #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */ 8626 8627 /* Bit 12 : Shortcut between event COMPARE[4] and task STOP */ 8628 #define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */ 8629 #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */ 8630 #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */ 8631 #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */ 8632 8633 /* Bit 11 : Shortcut between event COMPARE[3] and task STOP */ 8634 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ 8635 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ 8636 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */ 8637 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */ 8638 8639 /* Bit 10 : Shortcut between event COMPARE[2] and task STOP */ 8640 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ 8641 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ 8642 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */ 8643 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */ 8644 8645 /* Bit 9 : Shortcut between event COMPARE[1] and task STOP */ 8646 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ 8647 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ 8648 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */ 8649 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */ 8650 8651 /* Bit 8 : Shortcut between event COMPARE[0] and task STOP */ 8652 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ 8653 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ 8654 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */ 8655 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */ 8656 8657 /* Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */ 8658 #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */ 8659 #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */ 8660 #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 8661 #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 8662 8663 /* Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */ 8664 #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */ 8665 #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */ 8666 #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 8667 #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 8668 8669 /* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */ 8670 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ 8671 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ 8672 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 8673 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 8674 8675 /* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */ 8676 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ 8677 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ 8678 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 8679 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 8680 8681 /* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */ 8682 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ 8683 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ 8684 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 8685 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 8686 8687 /* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */ 8688 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ 8689 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ 8690 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 8691 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 8692 8693 /* Register: TIMER_INTENSET */ 8694 /* Description: Enable interrupt */ 8695 8696 /* Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */ 8697 #define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ 8698 #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ 8699 #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ 8700 #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ 8701 #define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */ 8702 8703 /* Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */ 8704 #define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ 8705 #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ 8706 #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ 8707 #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ 8708 #define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */ 8709 8710 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */ 8711 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 8712 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 8713 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 8714 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 8715 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ 8716 8717 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */ 8718 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 8719 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 8720 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ 8721 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ 8722 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ 8723 8724 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */ 8725 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 8726 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 8727 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ 8728 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ 8729 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ 8730 8731 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ 8732 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 8733 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 8734 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 8735 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 8736 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ 8737 8738 /* Register: TIMER_INTENCLR */ 8739 /* Description: Disable interrupt */ 8740 8741 /* Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */ 8742 #define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ 8743 #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ 8744 #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ 8745 #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ 8746 #define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */ 8747 8748 /* Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */ 8749 #define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ 8750 #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ 8751 #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ 8752 #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ 8753 #define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */ 8754 8755 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */ 8756 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 8757 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 8758 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 8759 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 8760 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ 8761 8762 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */ 8763 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 8764 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 8765 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ 8766 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ 8767 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ 8768 8769 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */ 8770 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 8771 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 8772 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ 8773 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ 8774 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ 8775 8776 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ 8777 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 8778 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 8779 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 8780 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 8781 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ 8782 8783 /* Register: TIMER_MODE */ 8784 /* Description: Timer mode selection */ 8785 8786 /* Bits 1..0 : Timer mode */ 8787 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ 8788 #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ 8789 #define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */ 8790 #define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator - Select Counter mode */ 8791 #define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */ 8792 8793 /* Register: TIMER_BITMODE */ 8794 /* Description: Configure the number of bits used by the TIMER */ 8795 8796 /* Bits 1..0 : Timer bit width */ 8797 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */ 8798 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */ 8799 #define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */ 8800 #define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */ 8801 #define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */ 8802 #define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */ 8803 8804 /* Register: TIMER_PRESCALER */ 8805 /* Description: Timer prescaler register */ 8806 8807 /* Bits 3..0 : Prescaler value */ 8808 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ 8809 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ 8810 8811 /* Register: TIMER_ONESHOTEN */ 8812 /* Description: Description collection: Enable one-shot operation for Capture/Compare channel n */ 8813 8814 /* Bit 0 : Enable one-shot operation */ 8815 #define TIMER_ONESHOTEN_ONESHOTEN_Pos (0UL) /*!< Position of ONESHOTEN field. */ 8816 #define TIMER_ONESHOTEN_ONESHOTEN_Msk (0x1UL << TIMER_ONESHOTEN_ONESHOTEN_Pos) /*!< Bit mask of ONESHOTEN field. */ 8817 #define TIMER_ONESHOTEN_ONESHOTEN_Disable (0UL) /*!< Disable one-shot operation */ 8818 #define TIMER_ONESHOTEN_ONESHOTEN_Enable (1UL) /*!< Enable one-shot operation */ 8819 8820 /* Register: TIMER_CC */ 8821 /* Description: Description collection: Capture/Compare register n */ 8822 8823 /* Bits 31..0 : Capture/Compare value */ 8824 #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */ 8825 #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */ 8826 8827 8828 /* Peripheral: TWIM */ 8829 /* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */ 8830 8831 /* Register: TWIM_TASKS_STARTRX */ 8832 /* Description: Start TWI receive sequence */ 8833 8834 /* Bit 0 : Start TWI receive sequence */ 8835 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ 8836 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ 8837 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ 8838 8839 /* Register: TWIM_TASKS_STARTTX */ 8840 /* Description: Start TWI transmit sequence */ 8841 8842 /* Bit 0 : Start TWI transmit sequence */ 8843 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ 8844 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ 8845 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ 8846 8847 /* Register: TWIM_TASKS_STOP */ 8848 /* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */ 8849 8850 /* Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */ 8851 #define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 8852 #define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 8853 #define TWIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 8854 8855 /* Register: TWIM_TASKS_SUSPEND */ 8856 /* Description: Suspend TWI transaction */ 8857 8858 /* Bit 0 : Suspend TWI transaction */ 8859 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ 8860 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ 8861 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ 8862 8863 /* Register: TWIM_TASKS_RESUME */ 8864 /* Description: Resume TWI transaction */ 8865 8866 /* Bit 0 : Resume TWI transaction */ 8867 #define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ 8868 #define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ 8869 #define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ 8870 8871 /* Register: TWIM_SUBSCRIBE_STARTRX */ 8872 /* Description: Subscribe configuration for task STARTRX */ 8873 8874 /* Bit 31 : */ 8875 #define TWIM_SUBSCRIBE_STARTRX_EN_Pos (31UL) /*!< Position of EN field. */ 8876 #define TWIM_SUBSCRIBE_STARTRX_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STARTRX_EN_Pos) /*!< Bit mask of EN field. */ 8877 #define TWIM_SUBSCRIBE_STARTRX_EN_Disabled (0UL) /*!< Disable subscription */ 8878 #define TWIM_SUBSCRIBE_STARTRX_EN_Enabled (1UL) /*!< Enable subscription */ 8879 8880 /* Bits 7..0 : DPPI channel that task STARTRX will subscribe to */ 8881 #define TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 8882 #define TWIM_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 8883 8884 /* Register: TWIM_SUBSCRIBE_STARTTX */ 8885 /* Description: Subscribe configuration for task STARTTX */ 8886 8887 /* Bit 31 : */ 8888 #define TWIM_SUBSCRIBE_STARTTX_EN_Pos (31UL) /*!< Position of EN field. */ 8889 #define TWIM_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STARTTX_EN_Pos) /*!< Bit mask of EN field. */ 8890 #define TWIM_SUBSCRIBE_STARTTX_EN_Disabled (0UL) /*!< Disable subscription */ 8891 #define TWIM_SUBSCRIBE_STARTTX_EN_Enabled (1UL) /*!< Enable subscription */ 8892 8893 /* Bits 7..0 : DPPI channel that task STARTTX will subscribe to */ 8894 #define TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 8895 #define TWIM_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 8896 8897 /* Register: TWIM_SUBSCRIBE_STOP */ 8898 /* Description: Subscribe configuration for task STOP */ 8899 8900 /* Bit 31 : */ 8901 #define TWIM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 8902 #define TWIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 8903 #define TWIM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ 8904 #define TWIM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ 8905 8906 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 8907 #define TWIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 8908 #define TWIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 8909 8910 /* Register: TWIM_SUBSCRIBE_SUSPEND */ 8911 /* Description: Subscribe configuration for task SUSPEND */ 8912 8913 /* Bit 31 : */ 8914 #define TWIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */ 8915 #define TWIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIM_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */ 8916 #define TWIM_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */ 8917 #define TWIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */ 8918 8919 /* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */ 8920 #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 8921 #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 8922 8923 /* Register: TWIM_SUBSCRIBE_RESUME */ 8924 /* Description: Subscribe configuration for task RESUME */ 8925 8926 /* Bit 31 : */ 8927 #define TWIM_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */ 8928 #define TWIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIM_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */ 8929 #define TWIM_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */ 8930 #define TWIM_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */ 8931 8932 /* Bits 7..0 : DPPI channel that task RESUME will subscribe to */ 8933 #define TWIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 8934 #define TWIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 8935 8936 /* Register: TWIM_EVENTS_STOPPED */ 8937 /* Description: TWI stopped */ 8938 8939 /* Bit 0 : TWI stopped */ 8940 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ 8941 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ 8942 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ 8943 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ 8944 8945 /* Register: TWIM_EVENTS_ERROR */ 8946 /* Description: TWI error */ 8947 8948 /* Bit 0 : TWI error */ 8949 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ 8950 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ 8951 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ 8952 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ 8953 8954 /* Register: TWIM_EVENTS_SUSPENDED */ 8955 /* Description: SUSPEND task has been issued, TWI traffic is now suspended. */ 8956 8957 /* Bit 0 : SUSPEND task has been issued, TWI traffic is now suspended. */ 8958 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ 8959 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ 8960 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */ 8961 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */ 8962 8963 /* Register: TWIM_EVENTS_RXSTARTED */ 8964 /* Description: Receive sequence started */ 8965 8966 /* Bit 0 : Receive sequence started */ 8967 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ 8968 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ 8969 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ 8970 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ 8971 8972 /* Register: TWIM_EVENTS_TXSTARTED */ 8973 /* Description: Transmit sequence started */ 8974 8975 /* Bit 0 : Transmit sequence started */ 8976 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ 8977 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ 8978 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ 8979 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ 8980 8981 /* Register: TWIM_EVENTS_LASTRX */ 8982 /* Description: Byte boundary, starting to receive the last byte */ 8983 8984 /* Bit 0 : Byte boundary, starting to receive the last byte */ 8985 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */ 8986 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */ 8987 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0UL) /*!< Event not generated */ 8988 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (1UL) /*!< Event generated */ 8989 8990 /* Register: TWIM_EVENTS_LASTTX */ 8991 /* Description: Byte boundary, starting to transmit the last byte */ 8992 8993 /* Bit 0 : Byte boundary, starting to transmit the last byte */ 8994 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */ 8995 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */ 8996 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0UL) /*!< Event not generated */ 8997 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (1UL) /*!< Event generated */ 8998 8999 /* Register: TWIM_PUBLISH_STOPPED */ 9000 /* Description: Publish configuration for event STOPPED */ 9001 9002 /* Bit 31 : */ 9003 #define TWIM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ 9004 #define TWIM_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ 9005 #define TWIM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ 9006 #define TWIM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ 9007 9008 /* Bits 7..0 : DPPI channel that event STOPPED will publish to */ 9009 #define TWIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9010 #define TWIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9011 9012 /* Register: TWIM_PUBLISH_ERROR */ 9013 /* Description: Publish configuration for event ERROR */ 9014 9015 /* Bit 31 : */ 9016 #define TWIM_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */ 9017 #define TWIM_PUBLISH_ERROR_EN_Msk (0x1UL << TWIM_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */ 9018 #define TWIM_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */ 9019 #define TWIM_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */ 9020 9021 /* Bits 7..0 : DPPI channel that event ERROR will publish to */ 9022 #define TWIM_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9023 #define TWIM_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9024 9025 /* Register: TWIM_PUBLISH_SUSPENDED */ 9026 /* Description: Publish configuration for event SUSPENDED */ 9027 9028 /* Bit 31 : */ 9029 #define TWIM_PUBLISH_SUSPENDED_EN_Pos (31UL) /*!< Position of EN field. */ 9030 #define TWIM_PUBLISH_SUSPENDED_EN_Msk (0x1UL << TWIM_PUBLISH_SUSPENDED_EN_Pos) /*!< Bit mask of EN field. */ 9031 #define TWIM_PUBLISH_SUSPENDED_EN_Disabled (0UL) /*!< Disable publishing */ 9032 #define TWIM_PUBLISH_SUSPENDED_EN_Enabled (1UL) /*!< Enable publishing */ 9033 9034 /* Bits 7..0 : DPPI channel that event SUSPENDED will publish to */ 9035 #define TWIM_PUBLISH_SUSPENDED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9036 #define TWIM_PUBLISH_SUSPENDED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_SUSPENDED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9037 9038 /* Register: TWIM_PUBLISH_RXSTARTED */ 9039 /* Description: Publish configuration for event RXSTARTED */ 9040 9041 /* Bit 31 : */ 9042 #define TWIM_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ 9043 #define TWIM_PUBLISH_RXSTARTED_EN_Msk (0x1UL << TWIM_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */ 9044 #define TWIM_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ 9045 #define TWIM_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ 9046 9047 /* Bits 7..0 : DPPI channel that event RXSTARTED will publish to */ 9048 #define TWIM_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9049 #define TWIM_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9050 9051 /* Register: TWIM_PUBLISH_TXSTARTED */ 9052 /* Description: Publish configuration for event TXSTARTED */ 9053 9054 /* Bit 31 : */ 9055 #define TWIM_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ 9056 #define TWIM_PUBLISH_TXSTARTED_EN_Msk (0x1UL << TWIM_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */ 9057 #define TWIM_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ 9058 #define TWIM_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ 9059 9060 /* Bits 7..0 : DPPI channel that event TXSTARTED will publish to */ 9061 #define TWIM_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9062 #define TWIM_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9063 9064 /* Register: TWIM_PUBLISH_LASTRX */ 9065 /* Description: Publish configuration for event LASTRX */ 9066 9067 /* Bit 31 : */ 9068 #define TWIM_PUBLISH_LASTRX_EN_Pos (31UL) /*!< Position of EN field. */ 9069 #define TWIM_PUBLISH_LASTRX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTRX_EN_Pos) /*!< Bit mask of EN field. */ 9070 #define TWIM_PUBLISH_LASTRX_EN_Disabled (0UL) /*!< Disable publishing */ 9071 #define TWIM_PUBLISH_LASTRX_EN_Enabled (1UL) /*!< Enable publishing */ 9072 9073 /* Bits 7..0 : DPPI channel that event LASTRX will publish to */ 9074 #define TWIM_PUBLISH_LASTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9075 #define TWIM_PUBLISH_LASTRX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9076 9077 /* Register: TWIM_PUBLISH_LASTTX */ 9078 /* Description: Publish configuration for event LASTTX */ 9079 9080 /* Bit 31 : */ 9081 #define TWIM_PUBLISH_LASTTX_EN_Pos (31UL) /*!< Position of EN field. */ 9082 #define TWIM_PUBLISH_LASTTX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTTX_EN_Pos) /*!< Bit mask of EN field. */ 9083 #define TWIM_PUBLISH_LASTTX_EN_Disabled (0UL) /*!< Disable publishing */ 9084 #define TWIM_PUBLISH_LASTTX_EN_Enabled (1UL) /*!< Enable publishing */ 9085 9086 /* Bits 7..0 : DPPI channel that event LASTTX will publish to */ 9087 #define TWIM_PUBLISH_LASTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9088 #define TWIM_PUBLISH_LASTTX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9089 9090 /* Register: TWIM_SHORTS */ 9091 /* Description: Shortcuts between local events and tasks */ 9092 9093 /* Bit 12 : Shortcut between event LASTRX and task STOP */ 9094 #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */ 9095 #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */ 9096 #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */ 9097 #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */ 9098 9099 /* Bit 10 : Shortcut between event LASTRX and task STARTTX */ 9100 #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */ 9101 #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */ 9102 #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */ 9103 #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */ 9104 9105 /* Bit 9 : Shortcut between event LASTTX and task STOP */ 9106 #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */ 9107 #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */ 9108 #define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */ 9109 #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */ 9110 9111 /* Bit 8 : Shortcut between event LASTTX and task SUSPEND */ 9112 #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */ 9113 #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */ 9114 #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ 9115 #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ 9116 9117 /* Bit 7 : Shortcut between event LASTTX and task STARTRX */ 9118 #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */ 9119 #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */ 9120 #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ 9121 #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ 9122 9123 /* Register: TWIM_INTEN */ 9124 /* Description: Enable or disable interrupt */ 9125 9126 /* Bit 24 : Enable or disable interrupt for event LASTTX */ 9127 #define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ 9128 #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ 9129 #define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */ 9130 #define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */ 9131 9132 /* Bit 23 : Enable or disable interrupt for event LASTRX */ 9133 #define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ 9134 #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ 9135 #define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */ 9136 #define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */ 9137 9138 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */ 9139 #define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 9140 #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 9141 #define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ 9142 #define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ 9143 9144 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */ 9145 #define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 9146 #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 9147 #define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ 9148 #define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ 9149 9150 /* Bit 18 : Enable or disable interrupt for event SUSPENDED */ 9151 #define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ 9152 #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ 9153 #define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */ 9154 #define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */ 9155 9156 /* Bit 9 : Enable or disable interrupt for event ERROR */ 9157 #define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 9158 #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ 9159 #define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */ 9160 #define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */ 9161 9162 /* Bit 1 : Enable or disable interrupt for event STOPPED */ 9163 #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 9164 #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 9165 #define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ 9166 #define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ 9167 9168 /* Register: TWIM_INTENSET */ 9169 /* Description: Enable interrupt */ 9170 9171 /* Bit 24 : Write '1' to enable interrupt for event LASTTX */ 9172 #define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ 9173 #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ 9174 #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */ 9175 #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */ 9176 #define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */ 9177 9178 /* Bit 23 : Write '1' to enable interrupt for event LASTRX */ 9179 #define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ 9180 #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ 9181 #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */ 9182 #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */ 9183 #define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */ 9184 9185 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ 9186 #define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 9187 #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 9188 #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 9189 #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 9190 #define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ 9191 9192 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ 9193 #define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 9194 #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 9195 #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 9196 #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 9197 #define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ 9198 9199 /* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */ 9200 #define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ 9201 #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ 9202 #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ 9203 #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ 9204 #define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ 9205 9206 /* Bit 9 : Write '1' to enable interrupt for event ERROR */ 9207 #define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 9208 #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 9209 #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ 9210 #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ 9211 #define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */ 9212 9213 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */ 9214 #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 9215 #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 9216 #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 9217 #define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 9218 #define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ 9219 9220 /* Register: TWIM_INTENCLR */ 9221 /* Description: Disable interrupt */ 9222 9223 /* Bit 24 : Write '1' to disable interrupt for event LASTTX */ 9224 #define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ 9225 #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ 9226 #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */ 9227 #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */ 9228 #define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */ 9229 9230 /* Bit 23 : Write '1' to disable interrupt for event LASTRX */ 9231 #define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ 9232 #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ 9233 #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */ 9234 #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */ 9235 #define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */ 9236 9237 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ 9238 #define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 9239 #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 9240 #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 9241 #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 9242 #define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ 9243 9244 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ 9245 #define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 9246 #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 9247 #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 9248 #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 9249 #define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ 9250 9251 /* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */ 9252 #define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ 9253 #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ 9254 #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ 9255 #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ 9256 #define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ 9257 9258 /* Bit 9 : Write '1' to disable interrupt for event ERROR */ 9259 #define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 9260 #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 9261 #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ 9262 #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ 9263 #define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ 9264 9265 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */ 9266 #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 9267 #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 9268 #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 9269 #define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 9270 #define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ 9271 9272 /* Register: TWIM_ERRORSRC */ 9273 /* Description: Error source */ 9274 9275 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */ 9276 #define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ 9277 #define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ 9278 #define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ 9279 #define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ 9280 9281 /* Bit 1 : NACK received after sending the address (write '1' to clear) */ 9282 #define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ 9283 #define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ 9284 #define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */ 9285 #define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */ 9286 9287 /* Bit 0 : Overrun error */ 9288 #define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ 9289 #define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ 9290 #define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */ 9291 #define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */ 9292 9293 /* Register: TWIM_ENABLE */ 9294 /* Description: Enable TWIM */ 9295 9296 /* Bits 3..0 : Enable or disable TWIM */ 9297 #define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 9298 #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 9299 #define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */ 9300 #define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */ 9301 9302 /* Register: TWIM_PSEL_SCL */ 9303 /* Description: Pin select for SCL signal */ 9304 9305 /* Bit 31 : Connection */ 9306 #define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 9307 #define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 9308 #define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ 9309 #define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ 9310 9311 /* Bits 4..0 : Pin number */ 9312 #define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ 9313 #define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ 9314 9315 /* Register: TWIM_PSEL_SDA */ 9316 /* Description: Pin select for SDA signal */ 9317 9318 /* Bit 31 : Connection */ 9319 #define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 9320 #define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 9321 #define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ 9322 #define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ 9323 9324 /* Bits 4..0 : Pin number */ 9325 #define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ 9326 #define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ 9327 9328 /* Register: TWIM_FREQUENCY */ 9329 /* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */ 9330 9331 /* Bits 31..0 : TWI master clock frequency */ 9332 #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 9333 #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 9334 #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ 9335 #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ 9336 #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */ 9337 9338 /* Register: TWIM_RXD_PTR */ 9339 /* Description: Data pointer */ 9340 9341 /* Bits 31..0 : Data pointer */ 9342 #define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 9343 #define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 9344 9345 /* Register: TWIM_RXD_MAXCNT */ 9346 /* Description: Maximum number of bytes in receive buffer */ 9347 9348 /* Bits 12..0 : Maximum number of bytes in receive buffer */ 9349 #define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 9350 #define TWIM_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 9351 9352 /* Register: TWIM_RXD_AMOUNT */ 9353 /* Description: Number of bytes transferred in the last transaction */ 9354 9355 /* Bits 12..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ 9356 #define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 9357 #define TWIM_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 9358 9359 /* Register: TWIM_RXD_LIST */ 9360 /* Description: EasyDMA list type */ 9361 9362 /* Bits 1..0 : List type */ 9363 #define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 9364 #define TWIM_RXD_LIST_LIST_Msk (0x3UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 9365 #define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ 9366 #define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ 9367 9368 /* Register: TWIM_TXD_PTR */ 9369 /* Description: Data pointer */ 9370 9371 /* Bits 31..0 : Data pointer */ 9372 #define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 9373 #define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 9374 9375 /* Register: TWIM_TXD_MAXCNT */ 9376 /* Description: Maximum number of bytes in transmit buffer */ 9377 9378 /* Bits 12..0 : Maximum number of bytes in transmit buffer */ 9379 #define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 9380 #define TWIM_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 9381 9382 /* Register: TWIM_TXD_AMOUNT */ 9383 /* Description: Number of bytes transferred in the last transaction */ 9384 9385 /* Bits 12..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ 9386 #define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 9387 #define TWIM_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 9388 9389 /* Register: TWIM_TXD_LIST */ 9390 /* Description: EasyDMA list type */ 9391 9392 /* Bits 1..0 : List type */ 9393 #define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 9394 #define TWIM_TXD_LIST_LIST_Msk (0x3UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 9395 #define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ 9396 #define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ 9397 9398 /* Register: TWIM_ADDRESS */ 9399 /* Description: Address used in the TWI transfer */ 9400 9401 /* Bits 6..0 : Address used in the TWI transfer */ 9402 #define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ 9403 #define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ 9404 9405 9406 /* Peripheral: TWIS */ 9407 /* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */ 9408 9409 /* Register: TWIS_TASKS_STOP */ 9410 /* Description: Stop TWI transaction */ 9411 9412 /* Bit 0 : Stop TWI transaction */ 9413 #define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 9414 #define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 9415 #define TWIS_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 9416 9417 /* Register: TWIS_TASKS_SUSPEND */ 9418 /* Description: Suspend TWI transaction */ 9419 9420 /* Bit 0 : Suspend TWI transaction */ 9421 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ 9422 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ 9423 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ 9424 9425 /* Register: TWIS_TASKS_RESUME */ 9426 /* Description: Resume TWI transaction */ 9427 9428 /* Bit 0 : Resume TWI transaction */ 9429 #define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ 9430 #define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ 9431 #define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ 9432 9433 /* Register: TWIS_TASKS_PREPARERX */ 9434 /* Description: Prepare the TWI slave to respond to a write command */ 9435 9436 /* Bit 0 : Prepare the TWI slave to respond to a write command */ 9437 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */ 9438 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */ 9439 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (1UL) /*!< Trigger task */ 9440 9441 /* Register: TWIS_TASKS_PREPARETX */ 9442 /* Description: Prepare the TWI slave to respond to a read command */ 9443 9444 /* Bit 0 : Prepare the TWI slave to respond to a read command */ 9445 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */ 9446 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */ 9447 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (1UL) /*!< Trigger task */ 9448 9449 /* Register: TWIS_SUBSCRIBE_STOP */ 9450 /* Description: Subscribe configuration for task STOP */ 9451 9452 /* Bit 31 : */ 9453 #define TWIS_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 9454 #define TWIS_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIS_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 9455 #define TWIS_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ 9456 #define TWIS_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ 9457 9458 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 9459 #define TWIS_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9460 #define TWIS_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9461 9462 /* Register: TWIS_SUBSCRIBE_SUSPEND */ 9463 /* Description: Subscribe configuration for task SUSPEND */ 9464 9465 /* Bit 31 : */ 9466 #define TWIS_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */ 9467 #define TWIS_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIS_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */ 9468 #define TWIS_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */ 9469 #define TWIS_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */ 9470 9471 /* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */ 9472 #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9473 #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9474 9475 /* Register: TWIS_SUBSCRIBE_RESUME */ 9476 /* Description: Subscribe configuration for task RESUME */ 9477 9478 /* Bit 31 : */ 9479 #define TWIS_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */ 9480 #define TWIS_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIS_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */ 9481 #define TWIS_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */ 9482 #define TWIS_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */ 9483 9484 /* Bits 7..0 : DPPI channel that task RESUME will subscribe to */ 9485 #define TWIS_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9486 #define TWIS_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9487 9488 /* Register: TWIS_SUBSCRIBE_PREPARERX */ 9489 /* Description: Subscribe configuration for task PREPARERX */ 9490 9491 /* Bit 31 : */ 9492 #define TWIS_SUBSCRIBE_PREPARERX_EN_Pos (31UL) /*!< Position of EN field. */ 9493 #define TWIS_SUBSCRIBE_PREPARERX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARERX_EN_Pos) /*!< Bit mask of EN field. */ 9494 #define TWIS_SUBSCRIBE_PREPARERX_EN_Disabled (0UL) /*!< Disable subscription */ 9495 #define TWIS_SUBSCRIBE_PREPARERX_EN_Enabled (1UL) /*!< Enable subscription */ 9496 9497 /* Bits 7..0 : DPPI channel that task PREPARERX will subscribe to */ 9498 #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9499 #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9500 9501 /* Register: TWIS_SUBSCRIBE_PREPARETX */ 9502 /* Description: Subscribe configuration for task PREPARETX */ 9503 9504 /* Bit 31 : */ 9505 #define TWIS_SUBSCRIBE_PREPARETX_EN_Pos (31UL) /*!< Position of EN field. */ 9506 #define TWIS_SUBSCRIBE_PREPARETX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARETX_EN_Pos) /*!< Bit mask of EN field. */ 9507 #define TWIS_SUBSCRIBE_PREPARETX_EN_Disabled (0UL) /*!< Disable subscription */ 9508 #define TWIS_SUBSCRIBE_PREPARETX_EN_Enabled (1UL) /*!< Enable subscription */ 9509 9510 /* Bits 7..0 : DPPI channel that task PREPARETX will subscribe to */ 9511 #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9512 #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9513 9514 /* Register: TWIS_EVENTS_STOPPED */ 9515 /* Description: TWI stopped */ 9516 9517 /* Bit 0 : TWI stopped */ 9518 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ 9519 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ 9520 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ 9521 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ 9522 9523 /* Register: TWIS_EVENTS_ERROR */ 9524 /* Description: TWI error */ 9525 9526 /* Bit 0 : TWI error */ 9527 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ 9528 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ 9529 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ 9530 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ 9531 9532 /* Register: TWIS_EVENTS_RXSTARTED */ 9533 /* Description: Receive sequence started */ 9534 9535 /* Bit 0 : Receive sequence started */ 9536 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ 9537 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ 9538 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ 9539 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ 9540 9541 /* Register: TWIS_EVENTS_TXSTARTED */ 9542 /* Description: Transmit sequence started */ 9543 9544 /* Bit 0 : Transmit sequence started */ 9545 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ 9546 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ 9547 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ 9548 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ 9549 9550 /* Register: TWIS_EVENTS_WRITE */ 9551 /* Description: Write command received */ 9552 9553 /* Bit 0 : Write command received */ 9554 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */ 9555 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */ 9556 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0UL) /*!< Event not generated */ 9557 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (1UL) /*!< Event generated */ 9558 9559 /* Register: TWIS_EVENTS_READ */ 9560 /* Description: Read command received */ 9561 9562 /* Bit 0 : Read command received */ 9563 #define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */ 9564 #define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */ 9565 #define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0UL) /*!< Event not generated */ 9566 #define TWIS_EVENTS_READ_EVENTS_READ_Generated (1UL) /*!< Event generated */ 9567 9568 /* Register: TWIS_PUBLISH_STOPPED */ 9569 /* Description: Publish configuration for event STOPPED */ 9570 9571 /* Bit 31 : */ 9572 #define TWIS_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ 9573 #define TWIS_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIS_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ 9574 #define TWIS_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ 9575 #define TWIS_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ 9576 9577 /* Bits 7..0 : DPPI channel that event STOPPED will publish to */ 9578 #define TWIS_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9579 #define TWIS_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9580 9581 /* Register: TWIS_PUBLISH_ERROR */ 9582 /* Description: Publish configuration for event ERROR */ 9583 9584 /* Bit 31 : */ 9585 #define TWIS_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */ 9586 #define TWIS_PUBLISH_ERROR_EN_Msk (0x1UL << TWIS_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */ 9587 #define TWIS_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */ 9588 #define TWIS_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */ 9589 9590 /* Bits 7..0 : DPPI channel that event ERROR will publish to */ 9591 #define TWIS_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9592 #define TWIS_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9593 9594 /* Register: TWIS_PUBLISH_RXSTARTED */ 9595 /* Description: Publish configuration for event RXSTARTED */ 9596 9597 /* Bit 31 : */ 9598 #define TWIS_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ 9599 #define TWIS_PUBLISH_RXSTARTED_EN_Msk (0x1UL << TWIS_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */ 9600 #define TWIS_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ 9601 #define TWIS_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ 9602 9603 /* Bits 7..0 : DPPI channel that event RXSTARTED will publish to */ 9604 #define TWIS_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9605 #define TWIS_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9606 9607 /* Register: TWIS_PUBLISH_TXSTARTED */ 9608 /* Description: Publish configuration for event TXSTARTED */ 9609 9610 /* Bit 31 : */ 9611 #define TWIS_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ 9612 #define TWIS_PUBLISH_TXSTARTED_EN_Msk (0x1UL << TWIS_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */ 9613 #define TWIS_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ 9614 #define TWIS_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ 9615 9616 /* Bits 7..0 : DPPI channel that event TXSTARTED will publish to */ 9617 #define TWIS_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9618 #define TWIS_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9619 9620 /* Register: TWIS_PUBLISH_WRITE */ 9621 /* Description: Publish configuration for event WRITE */ 9622 9623 /* Bit 31 : */ 9624 #define TWIS_PUBLISH_WRITE_EN_Pos (31UL) /*!< Position of EN field. */ 9625 #define TWIS_PUBLISH_WRITE_EN_Msk (0x1UL << TWIS_PUBLISH_WRITE_EN_Pos) /*!< Bit mask of EN field. */ 9626 #define TWIS_PUBLISH_WRITE_EN_Disabled (0UL) /*!< Disable publishing */ 9627 #define TWIS_PUBLISH_WRITE_EN_Enabled (1UL) /*!< Enable publishing */ 9628 9629 /* Bits 7..0 : DPPI channel that event WRITE will publish to */ 9630 #define TWIS_PUBLISH_WRITE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9631 #define TWIS_PUBLISH_WRITE_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_WRITE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9632 9633 /* Register: TWIS_PUBLISH_READ */ 9634 /* Description: Publish configuration for event READ */ 9635 9636 /* Bit 31 : */ 9637 #define TWIS_PUBLISH_READ_EN_Pos (31UL) /*!< Position of EN field. */ 9638 #define TWIS_PUBLISH_READ_EN_Msk (0x1UL << TWIS_PUBLISH_READ_EN_Pos) /*!< Bit mask of EN field. */ 9639 #define TWIS_PUBLISH_READ_EN_Disabled (0UL) /*!< Disable publishing */ 9640 #define TWIS_PUBLISH_READ_EN_Enabled (1UL) /*!< Enable publishing */ 9641 9642 /* Bits 7..0 : DPPI channel that event READ will publish to */ 9643 #define TWIS_PUBLISH_READ_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9644 #define TWIS_PUBLISH_READ_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_READ_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9645 9646 /* Register: TWIS_SHORTS */ 9647 /* Description: Shortcuts between local events and tasks */ 9648 9649 /* Bit 14 : Shortcut between event READ and task SUSPEND */ 9650 #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */ 9651 #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */ 9652 #define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ 9653 #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ 9654 9655 /* Bit 13 : Shortcut between event WRITE and task SUSPEND */ 9656 #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */ 9657 #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */ 9658 #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ 9659 #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ 9660 9661 /* Register: TWIS_INTEN */ 9662 /* Description: Enable or disable interrupt */ 9663 9664 /* Bit 26 : Enable or disable interrupt for event READ */ 9665 #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */ 9666 #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */ 9667 #define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */ 9668 #define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */ 9669 9670 /* Bit 25 : Enable or disable interrupt for event WRITE */ 9671 #define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */ 9672 #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */ 9673 #define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */ 9674 #define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */ 9675 9676 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */ 9677 #define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 9678 #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 9679 #define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ 9680 #define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ 9681 9682 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */ 9683 #define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 9684 #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 9685 #define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ 9686 #define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ 9687 9688 /* Bit 9 : Enable or disable interrupt for event ERROR */ 9689 #define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 9690 #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ 9691 #define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */ 9692 #define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */ 9693 9694 /* Bit 1 : Enable or disable interrupt for event STOPPED */ 9695 #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 9696 #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 9697 #define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ 9698 #define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ 9699 9700 /* Register: TWIS_INTENSET */ 9701 /* Description: Enable interrupt */ 9702 9703 /* Bit 26 : Write '1' to enable interrupt for event READ */ 9704 #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */ 9705 #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */ 9706 #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */ 9707 #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */ 9708 #define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */ 9709 9710 /* Bit 25 : Write '1' to enable interrupt for event WRITE */ 9711 #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */ 9712 #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */ 9713 #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */ 9714 #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */ 9715 #define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */ 9716 9717 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ 9718 #define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 9719 #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 9720 #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 9721 #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 9722 #define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ 9723 9724 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ 9725 #define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 9726 #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 9727 #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 9728 #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 9729 #define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ 9730 9731 /* Bit 9 : Write '1' to enable interrupt for event ERROR */ 9732 #define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 9733 #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 9734 #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ 9735 #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ 9736 #define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */ 9737 9738 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */ 9739 #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 9740 #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 9741 #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 9742 #define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 9743 #define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */ 9744 9745 /* Register: TWIS_INTENCLR */ 9746 /* Description: Disable interrupt */ 9747 9748 /* Bit 26 : Write '1' to disable interrupt for event READ */ 9749 #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */ 9750 #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */ 9751 #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */ 9752 #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */ 9753 #define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */ 9754 9755 /* Bit 25 : Write '1' to disable interrupt for event WRITE */ 9756 #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */ 9757 #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */ 9758 #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */ 9759 #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */ 9760 #define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */ 9761 9762 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ 9763 #define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 9764 #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 9765 #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 9766 #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 9767 #define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ 9768 9769 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ 9770 #define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 9771 #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 9772 #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 9773 #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 9774 #define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ 9775 9776 /* Bit 9 : Write '1' to disable interrupt for event ERROR */ 9777 #define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 9778 #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 9779 #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ 9780 #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ 9781 #define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ 9782 9783 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */ 9784 #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 9785 #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 9786 #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 9787 #define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 9788 #define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ 9789 9790 /* Register: TWIS_ERRORSRC */ 9791 /* Description: Error source */ 9792 9793 /* Bit 3 : TX buffer over-read detected, and prevented */ 9794 #define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */ 9795 #define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ 9796 #define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */ 9797 #define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */ 9798 9799 /* Bit 2 : NACK sent after receiving a data byte */ 9800 #define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ 9801 #define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ 9802 #define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ 9803 #define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ 9804 9805 /* Bit 0 : RX buffer overflow detected, and prevented */ 9806 #define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */ 9807 #define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ 9808 #define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */ 9809 #define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */ 9810 9811 /* Register: TWIS_MATCH */ 9812 /* Description: Status register indicating which address had a match */ 9813 9814 /* Bit 0 : Indication of which address in {ADDRESS} that matched the incoming address */ 9815 #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ 9816 #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ 9817 9818 /* Register: TWIS_ENABLE */ 9819 /* Description: Enable TWIS */ 9820 9821 /* Bits 3..0 : Enable or disable TWIS */ 9822 #define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 9823 #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 9824 #define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */ 9825 #define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */ 9826 9827 /* Register: TWIS_PSEL_SCL */ 9828 /* Description: Pin select for SCL signal */ 9829 9830 /* Bit 31 : Connection */ 9831 #define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 9832 #define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 9833 #define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ 9834 #define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ 9835 9836 /* Bits 4..0 : Pin number */ 9837 #define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ 9838 #define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ 9839 9840 /* Register: TWIS_PSEL_SDA */ 9841 /* Description: Pin select for SDA signal */ 9842 9843 /* Bit 31 : Connection */ 9844 #define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 9845 #define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 9846 #define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ 9847 #define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ 9848 9849 /* Bits 4..0 : Pin number */ 9850 #define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ 9851 #define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ 9852 9853 /* Register: TWIS_RXD_PTR */ 9854 /* Description: RXD Data pointer */ 9855 9856 /* Bits 31..0 : RXD Data pointer */ 9857 #define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 9858 #define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 9859 9860 /* Register: TWIS_RXD_MAXCNT */ 9861 /* Description: Maximum number of bytes in RXD buffer */ 9862 9863 /* Bits 12..0 : Maximum number of bytes in RXD buffer */ 9864 #define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 9865 #define TWIS_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 9866 9867 /* Register: TWIS_RXD_AMOUNT */ 9868 /* Description: Number of bytes transferred in the last RXD transaction */ 9869 9870 /* Bits 12..0 : Number of bytes transferred in the last RXD transaction */ 9871 #define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 9872 #define TWIS_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 9873 9874 /* Register: TWIS_RXD_LIST */ 9875 /* Description: EasyDMA list type */ 9876 9877 /* Bits 1..0 : List type */ 9878 #define TWIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 9879 #define TWIS_RXD_LIST_LIST_Msk (0x3UL << TWIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 9880 #define TWIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ 9881 #define TWIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ 9882 9883 /* Register: TWIS_TXD_PTR */ 9884 /* Description: TXD Data pointer */ 9885 9886 /* Bits 31..0 : TXD Data pointer */ 9887 #define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 9888 #define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 9889 9890 /* Register: TWIS_TXD_MAXCNT */ 9891 /* Description: Maximum number of bytes in TXD buffer */ 9892 9893 /* Bits 12..0 : Maximum number of bytes in TXD buffer */ 9894 #define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 9895 #define TWIS_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 9896 9897 /* Register: TWIS_TXD_AMOUNT */ 9898 /* Description: Number of bytes transferred in the last TXD transaction */ 9899 9900 /* Bits 12..0 : Number of bytes transferred in the last TXD transaction */ 9901 #define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 9902 #define TWIS_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 9903 9904 /* Register: TWIS_TXD_LIST */ 9905 /* Description: EasyDMA list type */ 9906 9907 /* Bits 1..0 : List type */ 9908 #define TWIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 9909 #define TWIS_TXD_LIST_LIST_Msk (0x3UL << TWIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 9910 #define TWIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ 9911 #define TWIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ 9912 9913 /* Register: TWIS_ADDRESS */ 9914 /* Description: Description collection: TWI slave address n */ 9915 9916 /* Bits 6..0 : TWI slave address */ 9917 #define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ 9918 #define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ 9919 9920 /* Register: TWIS_CONFIG */ 9921 /* Description: Configuration register for the address match mechanism */ 9922 9923 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */ 9924 #define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */ 9925 #define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */ 9926 #define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */ 9927 #define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */ 9928 9929 /* Bit 0 : Enable or disable address matching on ADDRESS[0] */ 9930 #define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */ 9931 #define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */ 9932 #define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */ 9933 #define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */ 9934 9935 /* Register: TWIS_ORC */ 9936 /* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */ 9937 9938 /* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */ 9939 #define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ 9940 #define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ 9941 9942 9943 /* Peripheral: UARTE */ 9944 /* Description: UART with EasyDMA 0 */ 9945 9946 /* Register: UARTE_TASKS_STARTRX */ 9947 /* Description: Start UART receiver */ 9948 9949 /* Bit 0 : Start UART receiver */ 9950 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ 9951 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ 9952 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ 9953 9954 /* Register: UARTE_TASKS_STOPRX */ 9955 /* Description: Stop UART receiver */ 9956 9957 /* Bit 0 : Stop UART receiver */ 9958 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */ 9959 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */ 9960 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */ 9961 9962 /* Register: UARTE_TASKS_STARTTX */ 9963 /* Description: Start UART transmitter */ 9964 9965 /* Bit 0 : Start UART transmitter */ 9966 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ 9967 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ 9968 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ 9969 9970 /* Register: UARTE_TASKS_STOPTX */ 9971 /* Description: Stop UART transmitter */ 9972 9973 /* Bit 0 : Stop UART transmitter */ 9974 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */ 9975 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */ 9976 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */ 9977 9978 /* Register: UARTE_TASKS_FLUSHRX */ 9979 /* Description: Flush RX FIFO into RX buffer */ 9980 9981 /* Bit 0 : Flush RX FIFO into RX buffer */ 9982 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */ 9983 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */ 9984 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (1UL) /*!< Trigger task */ 9985 9986 /* Register: UARTE_SUBSCRIBE_STARTRX */ 9987 /* Description: Subscribe configuration for task STARTRX */ 9988 9989 /* Bit 31 : */ 9990 #define UARTE_SUBSCRIBE_STARTRX_EN_Pos (31UL) /*!< Position of EN field. */ 9991 #define UARTE_SUBSCRIBE_STARTRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STARTRX_EN_Pos) /*!< Bit mask of EN field. */ 9992 #define UARTE_SUBSCRIBE_STARTRX_EN_Disabled (0UL) /*!< Disable subscription */ 9993 #define UARTE_SUBSCRIBE_STARTRX_EN_Enabled (1UL) /*!< Enable subscription */ 9994 9995 /* Bits 7..0 : DPPI channel that task STARTRX will subscribe to */ 9996 #define UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9997 #define UARTE_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9998 9999 /* Register: UARTE_SUBSCRIBE_STOPRX */ 10000 /* Description: Subscribe configuration for task STOPRX */ 10001 10002 /* Bit 31 : */ 10003 #define UARTE_SUBSCRIBE_STOPRX_EN_Pos (31UL) /*!< Position of EN field. */ 10004 #define UARTE_SUBSCRIBE_STOPRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STOPRX_EN_Pos) /*!< Bit mask of EN field. */ 10005 #define UARTE_SUBSCRIBE_STOPRX_EN_Disabled (0UL) /*!< Disable subscription */ 10006 #define UARTE_SUBSCRIBE_STOPRX_EN_Enabled (1UL) /*!< Enable subscription */ 10007 10008 /* Bits 7..0 : DPPI channel that task STOPRX will subscribe to */ 10009 #define UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 10010 #define UARTE_SUBSCRIBE_STOPRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 10011 10012 /* Register: UARTE_SUBSCRIBE_STARTTX */ 10013 /* Description: Subscribe configuration for task STARTTX */ 10014 10015 /* Bit 31 : */ 10016 #define UARTE_SUBSCRIBE_STARTTX_EN_Pos (31UL) /*!< Position of EN field. */ 10017 #define UARTE_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STARTTX_EN_Pos) /*!< Bit mask of EN field. */ 10018 #define UARTE_SUBSCRIBE_STARTTX_EN_Disabled (0UL) /*!< Disable subscription */ 10019 #define UARTE_SUBSCRIBE_STARTTX_EN_Enabled (1UL) /*!< Enable subscription */ 10020 10021 /* Bits 7..0 : DPPI channel that task STARTTX will subscribe to */ 10022 #define UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 10023 #define UARTE_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 10024 10025 /* Register: UARTE_SUBSCRIBE_STOPTX */ 10026 /* Description: Subscribe configuration for task STOPTX */ 10027 10028 /* Bit 31 : */ 10029 #define UARTE_SUBSCRIBE_STOPTX_EN_Pos (31UL) /*!< Position of EN field. */ 10030 #define UARTE_SUBSCRIBE_STOPTX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STOPTX_EN_Pos) /*!< Bit mask of EN field. */ 10031 #define UARTE_SUBSCRIBE_STOPTX_EN_Disabled (0UL) /*!< Disable subscription */ 10032 #define UARTE_SUBSCRIBE_STOPTX_EN_Enabled (1UL) /*!< Enable subscription */ 10033 10034 /* Bits 7..0 : DPPI channel that task STOPTX will subscribe to */ 10035 #define UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 10036 #define UARTE_SUBSCRIBE_STOPTX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 10037 10038 /* Register: UARTE_SUBSCRIBE_FLUSHRX */ 10039 /* Description: Subscribe configuration for task FLUSHRX */ 10040 10041 /* Bit 31 : */ 10042 #define UARTE_SUBSCRIBE_FLUSHRX_EN_Pos (31UL) /*!< Position of EN field. */ 10043 #define UARTE_SUBSCRIBE_FLUSHRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_FLUSHRX_EN_Pos) /*!< Bit mask of EN field. */ 10044 #define UARTE_SUBSCRIBE_FLUSHRX_EN_Disabled (0UL) /*!< Disable subscription */ 10045 #define UARTE_SUBSCRIBE_FLUSHRX_EN_Enabled (1UL) /*!< Enable subscription */ 10046 10047 /* Bits 7..0 : DPPI channel that task FLUSHRX will subscribe to */ 10048 #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 10049 #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 10050 10051 /* Register: UARTE_EVENTS_CTS */ 10052 /* Description: CTS is activated (set low). Clear To Send. */ 10053 10054 /* Bit 0 : CTS is activated (set low). Clear To Send. */ 10055 #define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */ 10056 #define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */ 10057 #define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */ 10058 #define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */ 10059 10060 /* Register: UARTE_EVENTS_NCTS */ 10061 /* Description: CTS is deactivated (set high). Not Clear To Send. */ 10062 10063 /* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */ 10064 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */ 10065 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */ 10066 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */ 10067 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */ 10068 10069 /* Register: UARTE_EVENTS_RXDRDY */ 10070 /* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */ 10071 10072 /* Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */ 10073 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */ 10074 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */ 10075 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */ 10076 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */ 10077 10078 /* Register: UARTE_EVENTS_ENDRX */ 10079 /* Description: Receive buffer is filled up */ 10080 10081 /* Bit 0 : Receive buffer is filled up */ 10082 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ 10083 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ 10084 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ 10085 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ 10086 10087 /* Register: UARTE_EVENTS_TXDRDY */ 10088 /* Description: Data sent from TXD */ 10089 10090 /* Bit 0 : Data sent from TXD */ 10091 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */ 10092 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */ 10093 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */ 10094 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */ 10095 10096 /* Register: UARTE_EVENTS_ENDTX */ 10097 /* Description: Last TX byte transmitted */ 10098 10099 /* Bit 0 : Last TX byte transmitted */ 10100 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ 10101 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ 10102 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */ 10103 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */ 10104 10105 /* Register: UARTE_EVENTS_ERROR */ 10106 /* Description: Error detected */ 10107 10108 /* Bit 0 : Error detected */ 10109 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ 10110 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ 10111 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ 10112 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ 10113 10114 /* Register: UARTE_EVENTS_RXTO */ 10115 /* Description: Receiver timeout */ 10116 10117 /* Bit 0 : Receiver timeout */ 10118 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */ 10119 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */ 10120 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */ 10121 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */ 10122 10123 /* Register: UARTE_EVENTS_RXSTARTED */ 10124 /* Description: UART receiver has started */ 10125 10126 /* Bit 0 : UART receiver has started */ 10127 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ 10128 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ 10129 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ 10130 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ 10131 10132 /* Register: UARTE_EVENTS_TXSTARTED */ 10133 /* Description: UART transmitter has started */ 10134 10135 /* Bit 0 : UART transmitter has started */ 10136 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ 10137 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ 10138 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ 10139 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ 10140 10141 /* Register: UARTE_EVENTS_TXSTOPPED */ 10142 /* Description: Transmitter stopped */ 10143 10144 /* Bit 0 : Transmitter stopped */ 10145 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */ 10146 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */ 10147 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0UL) /*!< Event not generated */ 10148 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (1UL) /*!< Event generated */ 10149 10150 /* Register: UARTE_PUBLISH_CTS */ 10151 /* Description: Publish configuration for event CTS */ 10152 10153 /* Bit 31 : */ 10154 #define UARTE_PUBLISH_CTS_EN_Pos (31UL) /*!< Position of EN field. */ 10155 #define UARTE_PUBLISH_CTS_EN_Msk (0x1UL << UARTE_PUBLISH_CTS_EN_Pos) /*!< Bit mask of EN field. */ 10156 #define UARTE_PUBLISH_CTS_EN_Disabled (0UL) /*!< Disable publishing */ 10157 #define UARTE_PUBLISH_CTS_EN_Enabled (1UL) /*!< Enable publishing */ 10158 10159 /* Bits 7..0 : DPPI channel that event CTS will publish to */ 10160 #define UARTE_PUBLISH_CTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 10161 #define UARTE_PUBLISH_CTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_CTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 10162 10163 /* Register: UARTE_PUBLISH_NCTS */ 10164 /* Description: Publish configuration for event NCTS */ 10165 10166 /* Bit 31 : */ 10167 #define UARTE_PUBLISH_NCTS_EN_Pos (31UL) /*!< Position of EN field. */ 10168 #define UARTE_PUBLISH_NCTS_EN_Msk (0x1UL << UARTE_PUBLISH_NCTS_EN_Pos) /*!< Bit mask of EN field. */ 10169 #define UARTE_PUBLISH_NCTS_EN_Disabled (0UL) /*!< Disable publishing */ 10170 #define UARTE_PUBLISH_NCTS_EN_Enabled (1UL) /*!< Enable publishing */ 10171 10172 /* Bits 7..0 : DPPI channel that event NCTS will publish to */ 10173 #define UARTE_PUBLISH_NCTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 10174 #define UARTE_PUBLISH_NCTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_NCTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 10175 10176 /* Register: UARTE_PUBLISH_RXDRDY */ 10177 /* Description: Publish configuration for event RXDRDY */ 10178 10179 /* Bit 31 : */ 10180 #define UARTE_PUBLISH_RXDRDY_EN_Pos (31UL) /*!< Position of EN field. */ 10181 #define UARTE_PUBLISH_RXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_RXDRDY_EN_Pos) /*!< Bit mask of EN field. */ 10182 #define UARTE_PUBLISH_RXDRDY_EN_Disabled (0UL) /*!< Disable publishing */ 10183 #define UARTE_PUBLISH_RXDRDY_EN_Enabled (1UL) /*!< Enable publishing */ 10184 10185 /* Bits 7..0 : DPPI channel that event RXDRDY will publish to */ 10186 #define UARTE_PUBLISH_RXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 10187 #define UARTE_PUBLISH_RXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 10188 10189 /* Register: UARTE_PUBLISH_ENDRX */ 10190 /* Description: Publish configuration for event ENDRX */ 10191 10192 /* Bit 31 : */ 10193 #define UARTE_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */ 10194 #define UARTE_PUBLISH_ENDRX_EN_Msk (0x1UL << UARTE_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */ 10195 #define UARTE_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */ 10196 #define UARTE_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */ 10197 10198 /* Bits 7..0 : DPPI channel that event ENDRX will publish to */ 10199 #define UARTE_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 10200 #define UARTE_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 10201 10202 /* Register: UARTE_PUBLISH_TXDRDY */ 10203 /* Description: Publish configuration for event TXDRDY */ 10204 10205 /* Bit 31 : */ 10206 #define UARTE_PUBLISH_TXDRDY_EN_Pos (31UL) /*!< Position of EN field. */ 10207 #define UARTE_PUBLISH_TXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_TXDRDY_EN_Pos) /*!< Bit mask of EN field. */ 10208 #define UARTE_PUBLISH_TXDRDY_EN_Disabled (0UL) /*!< Disable publishing */ 10209 #define UARTE_PUBLISH_TXDRDY_EN_Enabled (1UL) /*!< Enable publishing */ 10210 10211 /* Bits 7..0 : DPPI channel that event TXDRDY will publish to */ 10212 #define UARTE_PUBLISH_TXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 10213 #define UARTE_PUBLISH_TXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 10214 10215 /* Register: UARTE_PUBLISH_ENDTX */ 10216 /* Description: Publish configuration for event ENDTX */ 10217 10218 /* Bit 31 : */ 10219 #define UARTE_PUBLISH_ENDTX_EN_Pos (31UL) /*!< Position of EN field. */ 10220 #define UARTE_PUBLISH_ENDTX_EN_Msk (0x1UL << UARTE_PUBLISH_ENDTX_EN_Pos) /*!< Bit mask of EN field. */ 10221 #define UARTE_PUBLISH_ENDTX_EN_Disabled (0UL) /*!< Disable publishing */ 10222 #define UARTE_PUBLISH_ENDTX_EN_Enabled (1UL) /*!< Enable publishing */ 10223 10224 /* Bits 7..0 : DPPI channel that event ENDTX will publish to */ 10225 #define UARTE_PUBLISH_ENDTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 10226 #define UARTE_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 10227 10228 /* Register: UARTE_PUBLISH_ERROR */ 10229 /* Description: Publish configuration for event ERROR */ 10230 10231 /* Bit 31 : */ 10232 #define UARTE_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */ 10233 #define UARTE_PUBLISH_ERROR_EN_Msk (0x1UL << UARTE_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */ 10234 #define UARTE_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */ 10235 #define UARTE_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */ 10236 10237 /* Bits 7..0 : DPPI channel that event ERROR will publish to */ 10238 #define UARTE_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 10239 #define UARTE_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 10240 10241 /* Register: UARTE_PUBLISH_RXTO */ 10242 /* Description: Publish configuration for event RXTO */ 10243 10244 /* Bit 31 : */ 10245 #define UARTE_PUBLISH_RXTO_EN_Pos (31UL) /*!< Position of EN field. */ 10246 #define UARTE_PUBLISH_RXTO_EN_Msk (0x1UL << UARTE_PUBLISH_RXTO_EN_Pos) /*!< Bit mask of EN field. */ 10247 #define UARTE_PUBLISH_RXTO_EN_Disabled (0UL) /*!< Disable publishing */ 10248 #define UARTE_PUBLISH_RXTO_EN_Enabled (1UL) /*!< Enable publishing */ 10249 10250 /* Bits 7..0 : DPPI channel that event RXTO will publish to */ 10251 #define UARTE_PUBLISH_RXTO_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 10252 #define UARTE_PUBLISH_RXTO_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXTO_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 10253 10254 /* Register: UARTE_PUBLISH_RXSTARTED */ 10255 /* Description: Publish configuration for event RXSTARTED */ 10256 10257 /* Bit 31 : */ 10258 #define UARTE_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ 10259 #define UARTE_PUBLISH_RXSTARTED_EN_Msk (0x1UL << UARTE_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */ 10260 #define UARTE_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ 10261 #define UARTE_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ 10262 10263 /* Bits 7..0 : DPPI channel that event RXSTARTED will publish to */ 10264 #define UARTE_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 10265 #define UARTE_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 10266 10267 /* Register: UARTE_PUBLISH_TXSTARTED */ 10268 /* Description: Publish configuration for event TXSTARTED */ 10269 10270 /* Bit 31 : */ 10271 #define UARTE_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ 10272 #define UARTE_PUBLISH_TXSTARTED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */ 10273 #define UARTE_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ 10274 #define UARTE_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ 10275 10276 /* Bits 7..0 : DPPI channel that event TXSTARTED will publish to */ 10277 #define UARTE_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 10278 #define UARTE_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 10279 10280 /* Register: UARTE_PUBLISH_TXSTOPPED */ 10281 /* Description: Publish configuration for event TXSTOPPED */ 10282 10283 /* Bit 31 : */ 10284 #define UARTE_PUBLISH_TXSTOPPED_EN_Pos (31UL) /*!< Position of EN field. */ 10285 #define UARTE_PUBLISH_TXSTOPPED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTOPPED_EN_Pos) /*!< Bit mask of EN field. */ 10286 #define UARTE_PUBLISH_TXSTOPPED_EN_Disabled (0UL) /*!< Disable publishing */ 10287 #define UARTE_PUBLISH_TXSTOPPED_EN_Enabled (1UL) /*!< Enable publishing */ 10288 10289 /* Bits 7..0 : DPPI channel that event TXSTOPPED will publish to */ 10290 #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 10291 #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 10292 10293 /* Register: UARTE_SHORTS */ 10294 /* Description: Shortcuts between local events and tasks */ 10295 10296 /* Bit 6 : Shortcut between event ENDRX and task STOPRX */ 10297 #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */ 10298 #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */ 10299 #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */ 10300 #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */ 10301 10302 /* Bit 5 : Shortcut between event ENDRX and task STARTRX */ 10303 #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */ 10304 #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */ 10305 #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ 10306 #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ 10307 10308 /* Register: UARTE_INTEN */ 10309 /* Description: Enable or disable interrupt */ 10310 10311 /* Bit 22 : Enable or disable interrupt for event TXSTOPPED */ 10312 #define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ 10313 #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ 10314 #define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */ 10315 #define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */ 10316 10317 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */ 10318 #define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 10319 #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 10320 #define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ 10321 #define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ 10322 10323 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */ 10324 #define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 10325 #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 10326 #define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ 10327 #define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ 10328 10329 /* Bit 17 : Enable or disable interrupt for event RXTO */ 10330 #define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */ 10331 #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */ 10332 #define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */ 10333 #define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */ 10334 10335 /* Bit 9 : Enable or disable interrupt for event ERROR */ 10336 #define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 10337 #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ 10338 #define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */ 10339 #define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */ 10340 10341 /* Bit 8 : Enable or disable interrupt for event ENDTX */ 10342 #define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ 10343 #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 10344 #define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ 10345 #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ 10346 10347 /* Bit 7 : Enable or disable interrupt for event TXDRDY */ 10348 #define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ 10349 #define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ 10350 #define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */ 10351 #define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */ 10352 10353 /* Bit 4 : Enable or disable interrupt for event ENDRX */ 10354 #define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 10355 #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 10356 #define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ 10357 #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ 10358 10359 /* Bit 2 : Enable or disable interrupt for event RXDRDY */ 10360 #define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ 10361 #define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ 10362 #define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */ 10363 #define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */ 10364 10365 /* Bit 1 : Enable or disable interrupt for event NCTS */ 10366 #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */ 10367 #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */ 10368 #define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */ 10369 #define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */ 10370 10371 /* Bit 0 : Enable or disable interrupt for event CTS */ 10372 #define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */ 10373 #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */ 10374 #define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */ 10375 #define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */ 10376 10377 /* Register: UARTE_INTENSET */ 10378 /* Description: Enable interrupt */ 10379 10380 /* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */ 10381 #define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ 10382 #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ 10383 #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ 10384 #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ 10385 #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */ 10386 10387 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ 10388 #define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 10389 #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 10390 #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 10391 #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 10392 #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ 10393 10394 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ 10395 #define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 10396 #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 10397 #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 10398 #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 10399 #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ 10400 10401 /* Bit 17 : Write '1' to enable interrupt for event RXTO */ 10402 #define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ 10403 #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ 10404 #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ 10405 #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ 10406 #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */ 10407 10408 /* Bit 9 : Write '1' to enable interrupt for event ERROR */ 10409 #define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 10410 #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 10411 #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ 10412 #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ 10413 #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */ 10414 10415 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */ 10416 #define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ 10417 #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 10418 #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ 10419 #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ 10420 #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */ 10421 10422 /* Bit 7 : Write '1' to enable interrupt for event TXDRDY */ 10423 #define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ 10424 #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ 10425 #define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ 10426 #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ 10427 #define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ 10428 10429 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */ 10430 #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 10431 #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 10432 #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ 10433 #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ 10434 #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */ 10435 10436 /* Bit 2 : Write '1' to enable interrupt for event RXDRDY */ 10437 #define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ 10438 #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ 10439 #define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ 10440 #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ 10441 #define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ 10442 10443 /* Bit 1 : Write '1' to enable interrupt for event NCTS */ 10444 #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ 10445 #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ 10446 #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ 10447 #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ 10448 #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */ 10449 10450 /* Bit 0 : Write '1' to enable interrupt for event CTS */ 10451 #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ 10452 #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ 10453 #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ 10454 #define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */ 10455 #define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */ 10456 10457 /* Register: UARTE_INTENCLR */ 10458 /* Description: Disable interrupt */ 10459 10460 /* Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */ 10461 #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ 10462 #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ 10463 #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ 10464 #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ 10465 #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */ 10466 10467 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ 10468 #define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 10469 #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 10470 #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 10471 #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 10472 #define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ 10473 10474 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ 10475 #define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 10476 #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 10477 #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 10478 #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 10479 #define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ 10480 10481 /* Bit 17 : Write '1' to disable interrupt for event RXTO */ 10482 #define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ 10483 #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ 10484 #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ 10485 #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ 10486 #define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ 10487 10488 /* Bit 9 : Write '1' to disable interrupt for event ERROR */ 10489 #define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 10490 #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 10491 #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ 10492 #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ 10493 #define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ 10494 10495 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */ 10496 #define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ 10497 #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 10498 #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ 10499 #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ 10500 #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ 10501 10502 /* Bit 7 : Write '1' to disable interrupt for event TXDRDY */ 10503 #define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ 10504 #define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ 10505 #define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ 10506 #define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ 10507 #define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ 10508 10509 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */ 10510 #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 10511 #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 10512 #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ 10513 #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ 10514 #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ 10515 10516 /* Bit 2 : Write '1' to disable interrupt for event RXDRDY */ 10517 #define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ 10518 #define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ 10519 #define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ 10520 #define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ 10521 #define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ 10522 10523 /* Bit 1 : Write '1' to disable interrupt for event NCTS */ 10524 #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ 10525 #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ 10526 #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ 10527 #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ 10528 #define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ 10529 10530 /* Bit 0 : Write '1' to disable interrupt for event CTS */ 10531 #define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ 10532 #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ 10533 #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ 10534 #define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */ 10535 #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */ 10536 10537 /* Register: UARTE_ERRORSRC */ 10538 /* Description: Error source This register is read/write one to clear. */ 10539 10540 /* Bit 3 : Break condition */ 10541 #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ 10542 #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ 10543 #define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ 10544 #define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ 10545 10546 /* Bit 2 : Framing error occurred */ 10547 #define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ 10548 #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ 10549 #define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ 10550 #define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ 10551 10552 /* Bit 1 : Parity error */ 10553 #define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ 10554 #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ 10555 #define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ 10556 #define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ 10557 10558 /* Bit 0 : Overrun error */ 10559 #define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ 10560 #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ 10561 #define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ 10562 #define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ 10563 10564 /* Register: UARTE_ENABLE */ 10565 /* Description: Enable UART */ 10566 10567 /* Bits 3..0 : Enable or disable UARTE */ 10568 #define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 10569 #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 10570 #define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */ 10571 #define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */ 10572 10573 /* Register: UARTE_PSEL_RTS */ 10574 /* Description: Pin select for RTS signal */ 10575 10576 /* Bit 31 : Connection */ 10577 #define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 10578 #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 10579 #define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */ 10580 #define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ 10581 10582 /* Bits 4..0 : Pin number */ 10583 #define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */ 10584 #define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */ 10585 10586 /* Register: UARTE_PSEL_TXD */ 10587 /* Description: Pin select for TXD signal */ 10588 10589 /* Bit 31 : Connection */ 10590 #define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 10591 #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 10592 #define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */ 10593 #define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ 10594 10595 /* Bits 4..0 : Pin number */ 10596 #define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */ 10597 #define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */ 10598 10599 /* Register: UARTE_PSEL_CTS */ 10600 /* Description: Pin select for CTS signal */ 10601 10602 /* Bit 31 : Connection */ 10603 #define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 10604 #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 10605 #define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */ 10606 #define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ 10607 10608 /* Bits 4..0 : Pin number */ 10609 #define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */ 10610 #define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */ 10611 10612 /* Register: UARTE_PSEL_RXD */ 10613 /* Description: Pin select for RXD signal */ 10614 10615 /* Bit 31 : Connection */ 10616 #define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 10617 #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 10618 #define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */ 10619 #define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ 10620 10621 /* Bits 4..0 : Pin number */ 10622 #define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */ 10623 #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */ 10624 10625 /* Register: UARTE_BAUDRATE */ 10626 /* Description: Baud rate. Accuracy depends on the HFCLK source selected. */ 10627 10628 /* Bits 31..0 : Baud rate */ 10629 #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ 10630 #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ 10631 #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ 10632 #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ 10633 #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ 10634 #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ 10635 #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */ 10636 #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ 10637 #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */ 10638 #define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ 10639 #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */ 10640 #define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ 10641 #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */ 10642 #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ 10643 #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */ 10644 #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */ 10645 #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ 10646 #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */ 10647 #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */ 10648 #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud */ 10649 10650 /* Register: UARTE_RXD_PTR */ 10651 /* Description: Data pointer */ 10652 10653 /* Bits 31..0 : Data pointer */ 10654 #define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 10655 #define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 10656 10657 /* Register: UARTE_RXD_MAXCNT */ 10658 /* Description: Maximum number of bytes in receive buffer */ 10659 10660 /* Bits 12..0 : Maximum number of bytes in receive buffer */ 10661 #define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 10662 #define UARTE_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 10663 10664 /* Register: UARTE_RXD_AMOUNT */ 10665 /* Description: Number of bytes transferred in the last transaction */ 10666 10667 /* Bits 12..0 : Number of bytes transferred in the last transaction */ 10668 #define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 10669 #define UARTE_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 10670 10671 /* Register: UARTE_TXD_PTR */ 10672 /* Description: Data pointer */ 10673 10674 /* Bits 31..0 : Data pointer */ 10675 #define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 10676 #define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 10677 10678 /* Register: UARTE_TXD_MAXCNT */ 10679 /* Description: Maximum number of bytes in transmit buffer */ 10680 10681 /* Bits 12..0 : Maximum number of bytes in transmit buffer */ 10682 #define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 10683 #define UARTE_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 10684 10685 /* Register: UARTE_TXD_AMOUNT */ 10686 /* Description: Number of bytes transferred in the last transaction */ 10687 10688 /* Bits 12..0 : Number of bytes transferred in the last transaction */ 10689 #define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 10690 #define UARTE_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 10691 10692 /* Register: UARTE_CONFIG */ 10693 /* Description: Configuration of parity and hardware flow control */ 10694 10695 /* Bit 4 : Stop bits */ 10696 #define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */ 10697 #define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */ 10698 #define UARTE_CONFIG_STOP_One (0UL) /*!< One stop bit */ 10699 #define UARTE_CONFIG_STOP_Two (1UL) /*!< Two stop bits */ 10700 10701 /* Bits 3..1 : Parity */ 10702 #define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ 10703 #define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ 10704 #define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ 10705 #define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include even parity bit */ 10706 10707 /* Bit 0 : Hardware flow control */ 10708 #define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ 10709 #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ 10710 #define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ 10711 #define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ 10712 10713 10714 /* Peripheral: UICR */ 10715 /* Description: User information configuration registers User information configuration registers */ 10716 10717 /* Register: UICR_APPROTECT */ 10718 /* Description: Access port protection */ 10719 10720 /* Bits 31..0 : Blocks debugger read/write access to all CPU registers and 10721 memory mapped addresses */ 10722 #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ 10723 #define UICR_APPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ 10724 #define UICR_APPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */ 10725 #define UICR_APPROTECT_PALL_HwUnprotected (0x50FA50FAUL) /*!< HwUnprotected */ 10726 10727 /* Register: UICR_XOSC32M */ 10728 /* Description: Oscillator control */ 10729 10730 /* Bits 5..0 : Pierce current DAC control signals */ 10731 #define UICR_XOSC32M_CTRL_Pos (0UL) /*!< Position of CTRL field. */ 10732 #define UICR_XOSC32M_CTRL_Msk (0x3FUL << UICR_XOSC32M_CTRL_Pos) /*!< Bit mask of CTRL field. */ 10733 10734 /* Register: UICR_HFXOSRC */ 10735 /* Description: HFXO clock source selection */ 10736 10737 /* Bit 0 : HFXO clock source selection */ 10738 #define UICR_HFXOSRC_HFXOSRC_Pos (0UL) /*!< Position of HFXOSRC field. */ 10739 #define UICR_HFXOSRC_HFXOSRC_Msk (0x1UL << UICR_HFXOSRC_HFXOSRC_Pos) /*!< Bit mask of HFXOSRC field. */ 10740 #define UICR_HFXOSRC_HFXOSRC_TCXO (0UL) /*!< 32 MHz temperature compensated crystal oscillator (TCXO) */ 10741 #define UICR_HFXOSRC_HFXOSRC_XTAL (1UL) /*!< 32 MHz crystal oscillator */ 10742 10743 /* Register: UICR_HFXOCNT */ 10744 /* Description: HFXO startup counter */ 10745 10746 /* Bits 7..0 : HFXO startup counter. Total debounce time = HFXOCNT*64 us + 0.5 us */ 10747 #define UICR_HFXOCNT_HFXOCNT_Pos (0UL) /*!< Position of HFXOCNT field. */ 10748 #define UICR_HFXOCNT_HFXOCNT_Msk (0xFFUL << UICR_HFXOCNT_HFXOCNT_Pos) /*!< Bit mask of HFXOCNT field. */ 10749 #define UICR_HFXOCNT_HFXOCNT_MinDebounceTime (0UL) /*!< Min debounce time = (0*64 us + 0.5 us) */ 10750 #define UICR_HFXOCNT_HFXOCNT_MaxDebounceTime (255UL) /*!< Max debounce time = (255*64 us + 0.5 us) */ 10751 10752 /* Register: UICR_APPNVMCPOFGUARD */ 10753 /* Description: Enable blocking NVM WRITE and aborting NVM ERASE for Application NVM in POFWARN condition . */ 10754 10755 /* Bit 0 : Enable blocking NVM WRITE and aborting NVM ERASE in POFWARN condition */ 10756 #define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Pos (0UL) /*!< Position of NVMCPOFGUARDEN field. */ 10757 #define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Msk (0x1UL << UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Pos) /*!< Bit mask of NVMCPOFGUARDEN field. */ 10758 #define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Disabled (0UL) /*!< NVM WRITE and NVM ERASE are not blocked in POFWARN condition */ 10759 #define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Enabled (1UL) /*!< NVM WRITE and NVM ERASE are blocked in POFWARN condition */ 10760 10761 /* Register: UICR_PMICCONF */ 10762 /* Description: Polarity of PMIC polarity configuration signals. */ 10763 10764 /* Bit 0 : Polarity of PMIC_FPWM signal. */ 10765 #define UICR_PMICCONF_PMICFPWMPOL_Pos (0UL) /*!< Position of PMICFPWMPOL field. */ 10766 #define UICR_PMICCONF_PMICFPWMPOL_Msk (0x1UL << UICR_PMICCONF_PMICFPWMPOL_Pos) /*!< Bit mask of PMICFPWMPOL field. */ 10767 #define UICR_PMICCONF_PMICFPWMPOL_ActiveLow (0UL) /*!< PMIC_FPWM output signal is active-low */ 10768 #define UICR_PMICCONF_PMICFPWMPOL_ActiveHigh (1UL) /*!< PMIC_FPWM output signal is active-high */ 10769 10770 /* Register: UICR_SECUREAPPROTECT */ 10771 /* Description: Secure access port protection */ 10772 10773 /* Bits 31..0 : Blocks debugger read/write access to all secure CPU registers and secure 10774 memory mapped addresses */ 10775 #define UICR_SECUREAPPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ 10776 #define UICR_SECUREAPPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_SECUREAPPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ 10777 #define UICR_SECUREAPPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */ 10778 #define UICR_SECUREAPPROTECT_PALL_HwUnprotected (0x50FA50FAUL) /*!< HwUnprotected */ 10779 10780 /* Register: UICR_ERASEPROTECT */ 10781 /* Description: Erase protection */ 10782 10783 /* Bits 31..0 : Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality */ 10784 #define UICR_ERASEPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ 10785 #define UICR_ERASEPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_ERASEPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ 10786 #define UICR_ERASEPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */ 10787 #define UICR_ERASEPROTECT_PALL_Unprotected (0xFFFFFFFFUL) /*!< Unprotected */ 10788 10789 /* Register: UICR_OTP */ 10790 /* Description: Description collection: One time programmable memory */ 10791 10792 /* Bits 31..16 : Upper half word */ 10793 #define UICR_OTP_UPPER_Pos (16UL) /*!< Position of UPPER field. */ 10794 #define UICR_OTP_UPPER_Msk (0xFFFFUL << UICR_OTP_UPPER_Pos) /*!< Bit mask of UPPER field. */ 10795 10796 /* Bits 15..0 : Lower half word */ 10797 #define UICR_OTP_LOWER_Pos (0UL) /*!< Position of LOWER field. */ 10798 #define UICR_OTP_LOWER_Msk (0xFFFFUL << UICR_OTP_LOWER_Pos) /*!< Bit mask of LOWER field. */ 10799 10800 /* Register: UICR_KEYSLOT_CONFIG_DEST */ 10801 /* Description: Description cluster: Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE[0-3]) 10802 will be pushed by KMU. Note that this address must match that of a peripherals 10803 APB mapped write-only key registers, else the KMU can push this key value into 10804 an address range which the CPU can potentially read. */ 10805 10806 /* Bits 31..0 : Secure APB destination address */ 10807 #define UICR_KEYSLOT_CONFIG_DEST_DEST_Pos (0UL) /*!< Position of DEST field. */ 10808 #define UICR_KEYSLOT_CONFIG_DEST_DEST_Msk (0xFFFFFFFFUL << UICR_KEYSLOT_CONFIG_DEST_DEST_Pos) /*!< Bit mask of DEST field. */ 10809 10810 /* Register: UICR_KEYSLOT_CONFIG_PERM */ 10811 /* Description: Description cluster: Define permissions for the key slot. Bits 0-15 and 16-31 can only be written when equal to 0xFFFF. */ 10812 10813 /* Bit 16 : Revocation state for the key slot */ 10814 #define UICR_KEYSLOT_CONFIG_PERM_STATE_Pos (16UL) /*!< Position of STATE field. */ 10815 #define UICR_KEYSLOT_CONFIG_PERM_STATE_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_STATE_Pos) /*!< Bit mask of STATE field. */ 10816 #define UICR_KEYSLOT_CONFIG_PERM_STATE_Revoked (0UL) /*!< Key value registers can no longer be read or pushed */ 10817 #define UICR_KEYSLOT_CONFIG_PERM_STATE_Active (1UL) /*!< Key value registers are readable (if enabled) and can be pushed (if enabled) */ 10818 10819 /* Bit 2 : Push permission for key slot */ 10820 #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Pos (2UL) /*!< Position of PUSH field. */ 10821 #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_PUSH_Pos) /*!< Bit mask of PUSH field. */ 10822 #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Disabled (0UL) /*!< Disable pushing of key value registers over secure APB, but can be read if field READ is Enabled */ 10823 #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Enabled (1UL) /*!< Enable pushing of key value registers over secure APB. Register KEYSLOT.CONFIGn.DEST must contain a valid destination address! */ 10824 10825 /* Bit 1 : Read permission for key slot */ 10826 #define UICR_KEYSLOT_CONFIG_PERM_READ_Pos (1UL) /*!< Position of READ field. */ 10827 #define UICR_KEYSLOT_CONFIG_PERM_READ_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_READ_Pos) /*!< Bit mask of READ field. */ 10828 #define UICR_KEYSLOT_CONFIG_PERM_READ_Disabled (0UL) /*!< Disable read from key value registers */ 10829 #define UICR_KEYSLOT_CONFIG_PERM_READ_Enabled (1UL) /*!< Enable read from key value registers */ 10830 10831 /* Bit 0 : Write permission for key slot */ 10832 #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Pos (0UL) /*!< Position of WRITE field. */ 10833 #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */ 10834 #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Disabled (0UL) /*!< Disable write to the key value registers */ 10835 #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Enabled (1UL) /*!< Enable write to the key value registers */ 10836 10837 /* Register: UICR_KEYSLOT_KEY_VALUE */ 10838 /* Description: Description collection: Define bits [31+o*32:0+o*32] of value assigned to KMU key slot. */ 10839 10840 /* Bits 31..0 : Define bits [31+o*32:0+o*32] of value assigned to KMU key slot */ 10841 #define UICR_KEYSLOT_KEY_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ 10842 #define UICR_KEYSLOT_KEY_VALUE_VALUE_Msk (0xFFFFFFFFUL << UICR_KEYSLOT_KEY_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ 10843 10844 10845 /* Peripheral: VMC */ 10846 /* Description: Volatile Memory controller 0 */ 10847 10848 /* Register: VMC_RAM_POWER */ 10849 /* Description: Description cluster: RAMn power control register */ 10850 10851 /* Bit 19 : Keep retention on RAM section S3 of RAM n when RAM section is switched off */ 10852 #define VMC_RAM_POWER_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */ 10853 #define VMC_RAM_POWER_S3RETENTION_Msk (0x1UL << VMC_RAM_POWER_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */ 10854 #define VMC_RAM_POWER_S3RETENTION_Off (0UL) /*!< Off */ 10855 #define VMC_RAM_POWER_S3RETENTION_On (1UL) /*!< On */ 10856 10857 /* Bit 18 : Keep retention on RAM section S2 of RAM n when RAM section is switched off */ 10858 #define VMC_RAM_POWER_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */ 10859 #define VMC_RAM_POWER_S2RETENTION_Msk (0x1UL << VMC_RAM_POWER_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */ 10860 #define VMC_RAM_POWER_S2RETENTION_Off (0UL) /*!< Off */ 10861 #define VMC_RAM_POWER_S2RETENTION_On (1UL) /*!< On */ 10862 10863 /* Bit 17 : Keep retention on RAM section S1 of RAM n when RAM section is switched off */ 10864 #define VMC_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ 10865 #define VMC_RAM_POWER_S1RETENTION_Msk (0x1UL << VMC_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ 10866 #define VMC_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */ 10867 #define VMC_RAM_POWER_S1RETENTION_On (1UL) /*!< On */ 10868 10869 /* Bit 16 : Keep retention on RAM section S0 of RAM n when RAM section is switched off */ 10870 #define VMC_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ 10871 #define VMC_RAM_POWER_S0RETENTION_Msk (0x1UL << VMC_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ 10872 #define VMC_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */ 10873 #define VMC_RAM_POWER_S0RETENTION_On (1UL) /*!< On */ 10874 10875 /* Bit 3 : Keep RAM section S3 of RAM n on or off in System ON mode */ 10876 #define VMC_RAM_POWER_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */ 10877 #define VMC_RAM_POWER_S3POWER_Msk (0x1UL << VMC_RAM_POWER_S3POWER_Pos) /*!< Bit mask of S3POWER field. */ 10878 #define VMC_RAM_POWER_S3POWER_Off (0UL) /*!< Off */ 10879 #define VMC_RAM_POWER_S3POWER_On (1UL) /*!< On */ 10880 10881 /* Bit 2 : Keep RAM section S2 of RAM n on or off in System ON mode */ 10882 #define VMC_RAM_POWER_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */ 10883 #define VMC_RAM_POWER_S2POWER_Msk (0x1UL << VMC_RAM_POWER_S2POWER_Pos) /*!< Bit mask of S2POWER field. */ 10884 #define VMC_RAM_POWER_S2POWER_Off (0UL) /*!< Off */ 10885 #define VMC_RAM_POWER_S2POWER_On (1UL) /*!< On */ 10886 10887 /* Bit 1 : Keep RAM section S1 of RAM n on or off in System ON mode */ 10888 #define VMC_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ 10889 #define VMC_RAM_POWER_S1POWER_Msk (0x1UL << VMC_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ 10890 #define VMC_RAM_POWER_S1POWER_Off (0UL) /*!< Off */ 10891 #define VMC_RAM_POWER_S1POWER_On (1UL) /*!< On */ 10892 10893 /* Bit 0 : Keep RAM section S0 of RAM n on or off in System ON mode */ 10894 #define VMC_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ 10895 #define VMC_RAM_POWER_S0POWER_Msk (0x1UL << VMC_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ 10896 #define VMC_RAM_POWER_S0POWER_Off (0UL) /*!< Off */ 10897 #define VMC_RAM_POWER_S0POWER_On (1UL) /*!< On */ 10898 10899 /* Register: VMC_RAM_POWERSET */ 10900 /* Description: Description cluster: RAMn power control set register */ 10901 10902 /* Bit 19 : Keep retention on RAM section S3 of RAM n when RAM section is switched off */ 10903 #define VMC_RAM_POWERSET_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */ 10904 #define VMC_RAM_POWERSET_S3RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */ 10905 #define VMC_RAM_POWERSET_S3RETENTION_On (1UL) /*!< On */ 10906 10907 /* Bit 18 : Keep retention on RAM section S2 of RAM n when RAM section is switched off */ 10908 #define VMC_RAM_POWERSET_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */ 10909 #define VMC_RAM_POWERSET_S2RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */ 10910 #define VMC_RAM_POWERSET_S2RETENTION_On (1UL) /*!< On */ 10911 10912 /* Bit 17 : Keep retention on RAM section S1 of RAM n when RAM section is switched off */ 10913 #define VMC_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ 10914 #define VMC_RAM_POWERSET_S1RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ 10915 #define VMC_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */ 10916 10917 /* Bit 16 : Keep retention on RAM section S0 of RAM n when RAM section is switched off */ 10918 #define VMC_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ 10919 #define VMC_RAM_POWERSET_S0RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ 10920 #define VMC_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */ 10921 10922 /* Bit 3 : Keep RAM section S3 of RAM n on or off in System ON mode */ 10923 #define VMC_RAM_POWERSET_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */ 10924 #define VMC_RAM_POWERSET_S3POWER_Msk (0x1UL << VMC_RAM_POWERSET_S3POWER_Pos) /*!< Bit mask of S3POWER field. */ 10925 #define VMC_RAM_POWERSET_S3POWER_On (1UL) /*!< On */ 10926 10927 /* Bit 2 : Keep RAM section S2 of RAM n on or off in System ON mode */ 10928 #define VMC_RAM_POWERSET_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */ 10929 #define VMC_RAM_POWERSET_S2POWER_Msk (0x1UL << VMC_RAM_POWERSET_S2POWER_Pos) /*!< Bit mask of S2POWER field. */ 10930 #define VMC_RAM_POWERSET_S2POWER_On (1UL) /*!< On */ 10931 10932 /* Bit 1 : Keep RAM section S1 of RAM n on or off in System ON mode */ 10933 #define VMC_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ 10934 #define VMC_RAM_POWERSET_S1POWER_Msk (0x1UL << VMC_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ 10935 #define VMC_RAM_POWERSET_S1POWER_On (1UL) /*!< On */ 10936 10937 /* Bit 0 : Keep RAM section S0 of RAM n on or off in System ON mode */ 10938 #define VMC_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ 10939 #define VMC_RAM_POWERSET_S0POWER_Msk (0x1UL << VMC_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ 10940 #define VMC_RAM_POWERSET_S0POWER_On (1UL) /*!< On */ 10941 10942 /* Register: VMC_RAM_POWERCLR */ 10943 /* Description: Description cluster: RAMn power control clear register */ 10944 10945 /* Bit 19 : Keep retention on RAM section S3 of RAM n when RAM section is switched off */ 10946 #define VMC_RAM_POWERCLR_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */ 10947 #define VMC_RAM_POWERCLR_S3RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */ 10948 #define VMC_RAM_POWERCLR_S3RETENTION_Off (1UL) /*!< Off */ 10949 10950 /* Bit 18 : Keep retention on RAM section S2 of RAM n when RAM section is switched off */ 10951 #define VMC_RAM_POWERCLR_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */ 10952 #define VMC_RAM_POWERCLR_S2RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */ 10953 #define VMC_RAM_POWERCLR_S2RETENTION_Off (1UL) /*!< Off */ 10954 10955 /* Bit 17 : Keep retention on RAM section S1 of RAM n when RAM section is switched off */ 10956 #define VMC_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ 10957 #define VMC_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ 10958 #define VMC_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */ 10959 10960 /* Bit 16 : Keep retention on RAM section S0 of RAM n when RAM section is switched off */ 10961 #define VMC_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ 10962 #define VMC_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ 10963 #define VMC_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */ 10964 10965 /* Bit 3 : Keep RAM section S3 of RAM n on or off in System ON mode */ 10966 #define VMC_RAM_POWERCLR_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */ 10967 #define VMC_RAM_POWERCLR_S3POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S3POWER_Pos) /*!< Bit mask of S3POWER field. */ 10968 #define VMC_RAM_POWERCLR_S3POWER_Off (1UL) /*!< Off */ 10969 10970 /* Bit 2 : Keep RAM section S2 of RAM n on or off in System ON mode */ 10971 #define VMC_RAM_POWERCLR_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */ 10972 #define VMC_RAM_POWERCLR_S2POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S2POWER_Pos) /*!< Bit mask of S2POWER field. */ 10973 #define VMC_RAM_POWERCLR_S2POWER_Off (1UL) /*!< Off */ 10974 10975 /* Bit 1 : Keep RAM section S1 of RAM n on or off in System ON mode */ 10976 #define VMC_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ 10977 #define VMC_RAM_POWERCLR_S1POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ 10978 #define VMC_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */ 10979 10980 /* Bit 0 : Keep RAM section S0 of RAM n on or off in System ON mode */ 10981 #define VMC_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ 10982 #define VMC_RAM_POWERCLR_S0POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ 10983 #define VMC_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */ 10984 10985 10986 /* Peripheral: WDT */ 10987 /* Description: Watchdog Timer 0 */ 10988 10989 /* Register: WDT_TASKS_START */ 10990 /* Description: Start the watchdog */ 10991 10992 /* Bit 0 : Start the watchdog */ 10993 #define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 10994 #define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 10995 #define WDT_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ 10996 10997 /* Register: WDT_SUBSCRIBE_START */ 10998 /* Description: Subscribe configuration for task START */ 10999 11000 /* Bit 31 : */ 11001 #define WDT_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ 11002 #define WDT_SUBSCRIBE_START_EN_Msk (0x1UL << WDT_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ 11003 #define WDT_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ 11004 #define WDT_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ 11005 11006 /* Bits 7..0 : DPPI channel that task START will subscribe to */ 11007 #define WDT_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 11008 #define WDT_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << WDT_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 11009 11010 /* Register: WDT_EVENTS_TIMEOUT */ 11011 /* Description: Watchdog timeout */ 11012 11013 /* Bit 0 : Watchdog timeout */ 11014 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */ 11015 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */ 11016 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0UL) /*!< Event not generated */ 11017 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (1UL) /*!< Event generated */ 11018 11019 /* Register: WDT_PUBLISH_TIMEOUT */ 11020 /* Description: Publish configuration for event TIMEOUT */ 11021 11022 /* Bit 31 : */ 11023 #define WDT_PUBLISH_TIMEOUT_EN_Pos (31UL) /*!< Position of EN field. */ 11024 #define WDT_PUBLISH_TIMEOUT_EN_Msk (0x1UL << WDT_PUBLISH_TIMEOUT_EN_Pos) /*!< Bit mask of EN field. */ 11025 #define WDT_PUBLISH_TIMEOUT_EN_Disabled (0UL) /*!< Disable publishing */ 11026 #define WDT_PUBLISH_TIMEOUT_EN_Enabled (1UL) /*!< Enable publishing */ 11027 11028 /* Bits 7..0 : DPPI channel that event TIMEOUT will publish to */ 11029 #define WDT_PUBLISH_TIMEOUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 11030 #define WDT_PUBLISH_TIMEOUT_CHIDX_Msk (0xFFUL << WDT_PUBLISH_TIMEOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 11031 11032 /* Register: WDT_INTENSET */ 11033 /* Description: Enable interrupt */ 11034 11035 /* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */ 11036 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ 11037 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ 11038 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ 11039 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ 11040 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */ 11041 11042 /* Register: WDT_INTENCLR */ 11043 /* Description: Disable interrupt */ 11044 11045 /* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */ 11046 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ 11047 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ 11048 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ 11049 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ 11050 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */ 11051 11052 /* Register: WDT_RUNSTATUS */ 11053 /* Description: Run status */ 11054 11055 /* Bit 0 : Indicates whether or not the watchdog is running */ 11056 #define WDT_RUNSTATUS_RUNSTATUSWDT_Pos (0UL) /*!< Position of RUNSTATUSWDT field. */ 11057 #define WDT_RUNSTATUS_RUNSTATUSWDT_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUSWDT_Pos) /*!< Bit mask of RUNSTATUSWDT field. */ 11058 #define WDT_RUNSTATUS_RUNSTATUSWDT_NotRunning (0UL) /*!< Watchdog not running */ 11059 #define WDT_RUNSTATUS_RUNSTATUSWDT_Running (1UL) /*!< Watchdog is running */ 11060 11061 /* Register: WDT_REQSTATUS */ 11062 /* Description: Request status */ 11063 11064 /* Bit 7 : Request status for RR[7] register */ 11065 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */ 11066 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */ 11067 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */ 11068 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */ 11069 11070 /* Bit 6 : Request status for RR[6] register */ 11071 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */ 11072 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */ 11073 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */ 11074 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */ 11075 11076 /* Bit 5 : Request status for RR[5] register */ 11077 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */ 11078 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */ 11079 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */ 11080 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */ 11081 11082 /* Bit 4 : Request status for RR[4] register */ 11083 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */ 11084 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */ 11085 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */ 11086 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */ 11087 11088 /* Bit 3 : Request status for RR[3] register */ 11089 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */ 11090 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */ 11091 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */ 11092 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */ 11093 11094 /* Bit 2 : Request status for RR[2] register */ 11095 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */ 11096 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */ 11097 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */ 11098 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */ 11099 11100 /* Bit 1 : Request status for RR[1] register */ 11101 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */ 11102 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */ 11103 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */ 11104 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */ 11105 11106 /* Bit 0 : Request status for RR[0] register */ 11107 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */ 11108 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */ 11109 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */ 11110 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */ 11111 11112 /* Register: WDT_CRV */ 11113 /* Description: Counter reload value */ 11114 11115 /* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */ 11116 #define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */ 11117 #define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */ 11118 11119 /* Register: WDT_RREN */ 11120 /* Description: Enable register for reload request registers */ 11121 11122 /* Bit 7 : Enable or disable RR[7] register */ 11123 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */ 11124 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */ 11125 #define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */ 11126 #define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */ 11127 11128 /* Bit 6 : Enable or disable RR[6] register */ 11129 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */ 11130 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */ 11131 #define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */ 11132 #define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */ 11133 11134 /* Bit 5 : Enable or disable RR[5] register */ 11135 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */ 11136 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */ 11137 #define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */ 11138 #define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */ 11139 11140 /* Bit 4 : Enable or disable RR[4] register */ 11141 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */ 11142 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */ 11143 #define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */ 11144 #define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */ 11145 11146 /* Bit 3 : Enable or disable RR[3] register */ 11147 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */ 11148 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */ 11149 #define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */ 11150 #define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */ 11151 11152 /* Bit 2 : Enable or disable RR[2] register */ 11153 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */ 11154 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */ 11155 #define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */ 11156 #define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */ 11157 11158 /* Bit 1 : Enable or disable RR[1] register */ 11159 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */ 11160 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */ 11161 #define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */ 11162 #define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */ 11163 11164 /* Bit 0 : Enable or disable RR[0] register */ 11165 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */ 11166 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */ 11167 #define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */ 11168 #define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */ 11169 11170 /* Register: WDT_CONFIG */ 11171 /* Description: Configuration register */ 11172 11173 /* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */ 11174 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ 11175 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ 11176 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */ 11177 #define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */ 11178 11179 /* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */ 11180 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ 11181 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ 11182 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */ 11183 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */ 11184 11185 /* Register: WDT_RR */ 11186 /* Description: Description collection: Reload request n */ 11187 11188 /* Bits 31..0 : Reload request register */ 11189 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ 11190 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */ 11191 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */ 11192 11193 11194 /*lint --flb "Leave library region" */ 11195 #endif 11196
