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Searched defs:APLLDIV (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h26027 …__IO uint32_t APLLDIV; /**< Auxiliary PLL Divide Register, offset: 0x504… member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h26026 …__IO uint32_t APLLDIV; /**< Auxiliary PLL Divide Register, offset: 0x504… member