1 /* 2 * Copyright (c) 2018 TDK Invensense 3 * 4 * SPDX-License-Identifier: BSD 3-Clause 5 */ 6 7 #ifndef _INV_IMU_REGMAP_REV_A_H_ 8 #define _INV_IMU_REGMAP_REV_A_H_ 9 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 /** @file inv_imu_regmap_rev_a.h 15 * File exposing the device register map 16 */ 17 18 #include <stdint.h> 19 20 /* BANK0 */ 21 #define MCLK_RDY 0x10000 22 #define DEVICE_CONFIG 0x10001 23 #define SIGNAL_PATH_RESET 0x10002 24 #define DRIVE_CONFIG1 0x10003 25 #define DRIVE_CONFIG2 0x10004 26 #define DRIVE_CONFIG3 0x10005 27 #define INT_CONFIG 0x10006 28 #define TEMP_DATA1 0x10009 29 #define TEMP_DATA0 0x1000a 30 #define ACCEL_DATA_X1 0x1000b 31 #define ACCEL_DATA_X0 0x1000c 32 #define ACCEL_DATA_Y1 0x1000d 33 #define ACCEL_DATA_Y0 0x1000e 34 #define ACCEL_DATA_Z1 0x1000f 35 #define ACCEL_DATA_Z0 0x10010 36 #define GYRO_DATA_X1 0x10011 37 #define GYRO_DATA_X0 0x10012 38 #define GYRO_DATA_Y1 0x10013 39 #define GYRO_DATA_Y0 0x10014 40 #define GYRO_DATA_Z1 0x10015 41 #define GYRO_DATA_Z0 0x10016 42 #define TMST_FSYNCH 0x10017 43 #define TMST_FSYNCL 0x10018 44 #define APEX_DATA4 0x1001d 45 #define APEX_DATA5 0x1001e 46 #define PWR_MGMT0 0x1001f 47 #define GYRO_CONFIG0 0x10020 48 #define ACCEL_CONFIG0 0x10021 49 #define TEMP_CONFIG0 0x10022 50 #define GYRO_CONFIG1 0x10023 51 #define ACCEL_CONFIG1 0x10024 52 #define APEX_CONFIG0 0x10025 53 #define APEX_CONFIG1 0x10026 54 #define WOM_CONFIG 0x10027 55 #define FIFO_CONFIG1 0x10028 56 #define FIFO_CONFIG2 0x10029 57 #define FIFO_CONFIG3 0x1002a 58 #define INT_SOURCE0 0x1002b 59 #define INT_SOURCE1 0x1002c 60 #define INT_SOURCE3 0x1002d 61 #define INT_SOURCE4 0x1002e 62 #define FIFO_LOST_PKT0 0x1002f 63 #define FIFO_LOST_PKT1 0x10030 64 #define APEX_DATA0 0x10031 65 #define APEX_DATA1 0x10032 66 #define APEX_DATA2 0x10033 67 #define APEX_DATA3 0x10034 68 #define INTF_CONFIG0 0x10035 69 #define INTF_CONFIG1 0x10036 70 #define INT_STATUS_DRDY 0x10039 71 #define INT_STATUS 0x1003a 72 #define INT_STATUS2 0x1003b 73 #define INT_STATUS3 0x1003c 74 #define FIFO_COUNTH 0x1003d 75 #define FIFO_COUNTL 0x1003e 76 #define FIFO_DATA 0x1003f 77 #define WHO_AM_I 0x10075 78 #define BLK_SEL_W 0x10079 79 #define MADDR_W 0x1007a 80 #define M_W 0x1007b 81 #define BLK_SEL_R 0x1007c 82 #define MADDR_R 0x1007d 83 #define M_R 0x1007e 84 85 /* MREG1 */ 86 #define TMST_CONFIG1_MREG1 0x00 87 #define FIFO_CONFIG5_MREG1 0x01 88 #define FIFO_CONFIG6_MREG1 0x02 89 #define FSYNC_CONFIG_MREG1 0x03 90 #define INT_CONFIG0_MREG1 0x04 91 #define INT_CONFIG1_MREG1 0x05 92 #define SENSOR_CONFIG3_MREG1 0x06 93 #define ST_CONFIG_MREG1 0x13 94 #define SELFTEST_MREG1 0x14 95 #define INTF_CONFIG6_MREG1 0x23 96 #define INTF_CONFIG10_MREG1 0x25 97 #define INTF_CONFIG7_MREG1 0x28 98 #define OTP_CONFIG_MREG1 0x2b 99 #define INT_SOURCE6_MREG1 0x2f 100 #define INT_SOURCE7_MREG1 0x30 101 #define INT_SOURCE8_MREG1 0x31 102 #define INT_SOURCE9_MREG1 0x32 103 #define INT_SOURCE10_MREG1 0x33 104 #define APEX_CONFIG2_MREG1 0x44 105 #define APEX_CONFIG3_MREG1 0x45 106 #define APEX_CONFIG4_MREG1 0x46 107 #define APEX_CONFIG5_MREG1 0x47 108 #define APEX_CONFIG9_MREG1 0x48 109 #define APEX_CONFIG10_MREG1 0x49 110 #define APEX_CONFIG11_MREG1 0x4a 111 #define ACCEL_WOM_X_THR_MREG1 0x4b 112 #define ACCEL_WOM_Y_THR_MREG1 0x4c 113 #define ACCEL_WOM_Z_THR_MREG1 0x4d 114 #define OFFSET_USER0_MREG1 0x4e 115 #define OFFSET_USER1_MREG1 0x4f 116 #define OFFSET_USER2_MREG1 0x50 117 #define OFFSET_USER3_MREG1 0x51 118 #define OFFSET_USER4_MREG1 0x52 119 #define OFFSET_USER5_MREG1 0x53 120 #define OFFSET_USER6_MREG1 0x54 121 #define OFFSET_USER7_MREG1 0x55 122 #define OFFSET_USER8_MREG1 0x56 123 #define ST_STATUS1_MREG1 0x63 124 #define ST_STATUS2_MREG1 0x64 125 #define FDR_CONFIG_MREG1 0x66 126 #define APEX_CONFIG12_MREG1 0x67 127 128 /* MREG3 */ 129 #define XA_ST_DATA_MREG3 0x5000 130 #define YA_ST_DATA_MREG3 0x5001 131 #define ZA_ST_DATA_MREG3 0x5002 132 #define XG_ST_DATA_MREG3 0x5003 133 #define YG_ST_DATA_MREG3 0x5004 134 #define ZG_ST_DATA_MREG3 0x5005 135 136 /* MREG2 */ 137 #define OTP_CTRL7_MREG2 0x2806 138 139 140 /* --------------------------------------------------------------------------- 141 * register BANK0 142 * ---------------------------------------------------------------------------*/ 143 144 /* 145 * MCLK_RDY 146 * Register Name : MCLK_RDY 147 */ 148 149 /* 150 * mclk_rdy 151 * 0: Indicates internal clock is currently not running 152 * 1: Indicates internal clock is currently running 153 */ 154 #define MCLK_RDY_MCLK_RDY_POS 0x03 155 #define MCLK_RDY_MCLK_RDY_MASK (0x01 << MCLK_RDY_MCLK_RDY_POS) 156 157 /* 158 * DEVICE_CONFIG 159 * Register Name : DEVICE_CONFIG 160 */ 161 162 /* 163 * spi_ap_4wire 164 * 0: AP interface uses 3-wire SPI mode 165 * 1: AP interface uses 4-wire SPI mode 166 */ 167 #define DEVICE_CONFIG_SPI_AP_4WIRE_POS 0x02 168 #define DEVICE_CONFIG_SPI_AP_4WIRE_MASK (0x01 << DEVICE_CONFIG_SPI_AP_4WIRE_POS) 169 170 /* 171 * spi_mode 172 * SPI mode selection 173 * 174 * 0: Mode 0 and Mode 3 175 * 1: Mode 1 and Mode 2 176 * 177 * If device is operating in non-SPI mode, user is not allowed to change the power-on default setting of this register. Change of this register setting will not take effect till AP_CS = 1. 178 */ 179 #define DEVICE_CONFIG_SPI_MODE_POS 0x00 180 #define DEVICE_CONFIG_SPI_MODE_MASK 0x01 181 182 183 184 /* 185 * SIGNAL_PATH_RESET 186 * Register Name : SIGNAL_PATH_RESET 187 */ 188 189 /* 190 * soft_reset_device_config 191 * Software Reset (auto clear bit) 192 * 193 * 0: Software reset not enabled 194 * 1: Software reset enabled 195 */ 196 #define SIGNAL_PATH_RESET_SOFT_RESET_DEVICE_CONFIG_POS 0x04 197 #define SIGNAL_PATH_RESET_SOFT_RESET_DEVICE_CONFIG_MASK (0x01 << SIGNAL_PATH_RESET_SOFT_RESET_DEVICE_CONFIG_POS) 198 199 /* 200 * fifo_flush 201 * When set to 1, FIFO will get flushed. 202 * FIFO flush requires the following programming sequence: 203 * • Write FIFO_FLUSH =1 204 * • Wait for 1.5 µs 205 * • Read FIFO_FLUSH, it should now be 0 206 * Host can only program this register bit to 1. 207 */ 208 #define SIGNAL_PATH_RESET_FIFO_FLUSH_POS 0x02 209 #define SIGNAL_PATH_RESET_FIFO_FLUSH_MASK (0x01 << SIGNAL_PATH_RESET_FIFO_FLUSH_POS) 210 211 212 213 /* 214 * DRIVE_CONFIG1 215 * Register Name : DRIVE_CONFIG1 216 */ 217 218 /* 219 * i3c_ddr_slew_rate 220 * Controls slew rate for output pin 14 when device is in I3CSM DDR protocol. 221 * While in I3CSM operation, the device automatically switches to use I3C_DDR_SLEW_RATE after receiving ENTHDR0 ccc command from the host. The device automatically switches back to I3C_SDR_SLEW_RATE after the host issues HDR_EXIT pattern. 222 * 223 * 000: MIN: 20 ns; TYP: 40 ns; MAX: 60 ns 224 * 001: MIN: 12 ns; TYP: 24 ns; MAX: 36 ns 225 * 010: MIN: 6 ns; TYP: 12 ns; MAX: 19 ns 226 * 011: MIN: 4 ns; TYP: 8 ns; MAX: 14 ns 227 * 100: MIN: 2 ns; TYP: 4 ns; MAX: 8 ns 228 * 101: MAX: 2 ns 229 * 110: Reserved 230 * 111: Reserved 231 * 232 * This register field should not be programmed in I3C/DDR mode. 233 */ 234 #define DRIVE_CONFIG1_I3C_DDR_SLEW_RATE_POS 0x03 235 #define DRIVE_CONFIG1_I3C_DDR_SLEW_RATE_MASK (0x07 << DRIVE_CONFIG1_I3C_DDR_SLEW_RATE_POS) 236 237 /* 238 * i3c_sdr_slew_rate 239 * Controls slew rate for output pin 14 in I3CSM SDR protocol. 240 * After device reset, I2C_SLEW_RATE is used by default. If I3CSM feature is enabled, the device automatically switches to use I3C_SDR_SLEW_RATE after receiving 0x7E+W message (an I3CSM broadcast message). 241 * 242 * 000: MIN: 20 ns; TYP: 40 ns; MAX: 60 ns 243 * 001: MIN: 12 ns; TYP: 24 ns; MAX: 36 ns 244 * 010: MIN: 6 ns; TYP: 12 ns; MAX: 19 ns 245 * 011: MIN: 4 ns; TYP: 8 ns; MAX: 14 ns 246 * 100: MIN: 2 ns; TYP: 4 ns; MAX: 8 ns 247 * 101: MAX: 2 ns 248 * 110: Reserved 249 * 111: Reserved 250 * 251 * This register field should not be programmed in I3C/DDR mode 252 */ 253 #define DRIVE_CONFIG1_I3C_SDR_SLEW_RATE_POS 0x00 254 #define DRIVE_CONFIG1_I3C_SDR_SLEW_RATE_MASK 0x07 255 256 257 258 /* 259 * DRIVE_CONFIG2 260 * Register Name : DRIVE_CONFIG2 261 */ 262 263 /* 264 * i2c_slew_rate 265 * Controls slew rate for output pin 14 in I2C mode. 266 * After device reset, the I2C_SLEW_RATE is used by default. If the 1st write operation from host is an SPI transaction, the device automatically switches to SPI_SLEW_RATE. If I3CSM feature is enabled, the device automatically switches to I3C_SDR_SLEW_RATE after receiving 0x7E+W message (an I3C broadcast message). 267 * 268 * 000: MIN: 20 ns; TYP: 40 ns; MAX: 60 ns 269 * 001: MIN: 12 ns; TYP: 24 ns; MAX: 36 ns 270 * 010: MIN: 6 ns; TYP: 12 ns; MAX: 19 ns 271 * 011: MIN: 4 ns; TYP: 8 ns; MAX: 14 ns 272 * 100: MIN: 2 ns; TYP: 4 ns; MAX: 8 ns 273 * 101: MAX: 2 ns 274 * 110: Reserved 275 * 111: Reserved 276 * 277 * This register field should not be programmed in I3C/DDR mode 278 */ 279 #define DRIVE_CONFIG2_I2C_SLEW_RATE_POS 0x03 280 #define DRIVE_CONFIG2_I2C_SLEW_RATE_MASK (0x07 << DRIVE_CONFIG2_I2C_SLEW_RATE_POS) 281 282 /* 283 * all_slew_rate 284 * Configure drive strength for all output pins in all modes (SPI3, SPI4, I2C, I3CSM) excluding pin 14. 285 * 286 * 000: MIN: 20 ns; TYP: 40 ns; MAX: 60 ns 287 * 001: MIN: 12 ns; TYP: 24 ns; MAX: 36 ns 288 * 010: MIN: 6 ns; TYP: 12 ns; MAX: 19 ns 289 * 011: MIN: 4 ns; TYP: 8 ns; MAX: 14 ns 290 * 100: MIN: 2 ns; TYP: 4 ns; MAX: 8 ns 291 * 101: MAX: 2 ns 292 * 110: Reserved 293 * 111: Reserved 294 * 295 * This register field should not be programmed in I3C/DDR mode 296 */ 297 #define DRIVE_CONFIG2_ALL_SLEW_RATE_POS 0x00 298 #define DRIVE_CONFIG2_ALL_SLEW_RATE_MASK 0x07 299 300 301 302 /* 303 * DRIVE_CONFIG3 304 * Register Name : DRIVE_CONFIG3 305 */ 306 307 /* 308 * spi_slew_rate 309 * Controls slew rate for output pin 14 in SPI 3-wire mode. In SPI 4-wire mode this register controls the slew rate of pin 1 as it is used as an output in SPI 4-wire mode only. After chip reset, the I2C_SLEW_RATE is used by default for pin 14 pin. If the 1st write operation from the host is an SPI3/4 transaction, the device automatically switches to SPI_SLEW_RATE. 310 * 311 * 000: MIN: 20 ns; TYP: 40 ns; MAX: 60 ns 312 * 001: MIN: 12 ns; TYP: 24 ns; MAX: 36 ns 313 * 010: MIN: 6 ns; TYP: 12 ns; MAX: 19 ns 314 * 011: MIN: 4 ns; TYP: 8 ns; MAX: 14 ns 315 * 100: MIN: 2 ns; TYP: 4 ns; MAX: 8 ns 316 * 101: MAX: 2 ns 317 * 110: Reserved 318 * 111: Reserved 319 * 320 * This register field should not be programmed in I3C/DDR mode 321 */ 322 #define DRIVE_CONFIG3_SPI_SLEW_RATE_POS 0x00 323 #define DRIVE_CONFIG3_SPI_SLEW_RATE_MASK 0x07 324 325 326 327 /* 328 * INT_CONFIG 329 * Register Name : INT_CONFIG 330 */ 331 332 /* 333 * int2_mode 334 * Interrupt mode and drive circuit shall be configurable by register. 335 * Interrupt Mode 336 * 1: Latched Mode 337 * 0: Pulsed Mode 338 */ 339 #define INT_CONFIG_INT2_MODE_POS 0x05 340 #define INT_CONFIG_INT2_MODE_MASK (0x01 << INT_CONFIG_INT2_MODE_POS) 341 342 /* 343 * int2_drive_circuit 344 * Interrupt mode and drive circuit shall be configurable by register. 345 * Drive Circuit 346 * 1: Push-Pull 347 * 0: Open drain 348 */ 349 #define INT_CONFIG_INT2_DRIVE_CIRCUIT_POS 0x04 350 #define INT_CONFIG_INT2_DRIVE_CIRCUIT_MASK (0x01 << INT_CONFIG_INT2_DRIVE_CIRCUIT_POS) 351 352 /* 353 * int2_polarity 354 * Interrupt mode and drive circuit shall be configurable by register. 355 * Interrupt Polarity 356 * 1: Active High 357 * 0: Active Low 358 */ 359 #define INT_CONFIG_INT2_POLARITY_POS 0x03 360 #define INT_CONFIG_INT2_POLARITY_MASK (0x01 << INT_CONFIG_INT2_POLARITY_POS) 361 362 /* 363 * int1_mode 364 * Interrupt mode and drive circuit shall be configurable by register. 365 * Interrupt Mode 366 * 1: Latched Mode 367 * 0: Pulsed Mode 368 */ 369 #define INT_CONFIG_INT1_MODE_POS 0x02 370 #define INT_CONFIG_INT1_MODE_MASK (0x01 << INT_CONFIG_INT1_MODE_POS) 371 372 /* 373 * int1_drive_circuit 374 * Interrupt mode and drive circuit shall be configurable by register. 375 * Drive Circuit 376 * 1: Push-Pull 377 * 0: Open drain 378 */ 379 #define INT_CONFIG_INT1_DRIVE_CIRCUIT_POS 0x01 380 #define INT_CONFIG_INT1_DRIVE_CIRCUIT_MASK (0x01 << INT_CONFIG_INT1_DRIVE_CIRCUIT_POS) 381 382 /* 383 * int1_polarity 384 * Interrupt mode and drive circuit shall be configurable by register. 385 * Interrupt Polarity 386 * 1: Active High 387 * 0: Active Low 388 */ 389 #define INT_CONFIG_INT1_POLARITY_POS 0x00 390 #define INT_CONFIG_INT1_POLARITY_MASK 0x01 391 392 393 394 /* 395 * TEMP_DATA1 396 * Register Name : TEMP_DATA1 397 */ 398 399 /* 400 * temp_data 401 * Temperature data 402 */ 403 #define TEMP_DATA1_TEMP_DATA_POS 0x00 404 #define TEMP_DATA1_TEMP_DATA_MASK 0xff 405 406 407 408 /* 409 * TEMP_DATA0 410 * Register Name : TEMP_DATA0 411 */ 412 413 /* 414 * temp_data 415 * Temperature data 416 */ 417 #define TEMP_DATA0_TEMP_DATA_POS 0x00 418 #define TEMP_DATA0_TEMP_DATA_MASK 0xff 419 420 421 422 /* 423 * ACCEL_DATA_X1 424 * Register Name : ACCEL_DATA_X1 425 */ 426 427 /* 428 * accel_data_x 429 * Accel X axis data 430 */ 431 #define ACCEL_DATA_X1_ACCEL_DATA_X_POS 0x00 432 #define ACCEL_DATA_X1_ACCEL_DATA_X_MASK 0xff 433 434 435 436 /* 437 * ACCEL_DATA_X0 438 * Register Name : ACCEL_DATA_X0 439 */ 440 441 /* 442 * accel_data_x 443 * Accel X axis data 444 */ 445 #define ACCEL_DATA_X0_ACCEL_DATA_X_POS 0x00 446 #define ACCEL_DATA_X0_ACCEL_DATA_X_MASK 0xff 447 448 449 450 /* 451 * ACCEL_DATA_Y1 452 * Register Name : ACCEL_DATA_Y1 453 */ 454 455 /* 456 * accel_data_y 457 * Accel Y axis data 458 */ 459 #define ACCEL_DATA_Y1_ACCEL_DATA_Y_POS 0x00 460 #define ACCEL_DATA_Y1_ACCEL_DATA_Y_MASK 0xff 461 462 463 464 /* 465 * ACCEL_DATA_Y0 466 * Register Name : ACCEL_DATA_Y0 467 */ 468 469 /* 470 * accel_data_y 471 * Accel Y axis data 472 */ 473 #define ACCEL_DATA_Y0_ACCEL_DATA_Y_POS 0x00 474 #define ACCEL_DATA_Y0_ACCEL_DATA_Y_MASK 0xff 475 476 477 478 /* 479 * ACCEL_DATA_Z1 480 * Register Name : ACCEL_DATA_Z1 481 */ 482 483 /* 484 * accel_data_z 485 * Accel Z axis data 486 */ 487 #define ACCEL_DATA_Z1_ACCEL_DATA_Z_POS 0x00 488 #define ACCEL_DATA_Z1_ACCEL_DATA_Z_MASK 0xff 489 490 491 492 /* 493 * ACCEL_DATA_Z0 494 * Register Name : ACCEL_DATA_Z0 495 */ 496 497 /* 498 * accel_data_z 499 * Accel Z axis data 500 */ 501 #define ACCEL_DATA_Z0_ACCEL_DATA_Z_POS 0x00 502 #define ACCEL_DATA_Z0_ACCEL_DATA_Z_MASK 0xff 503 504 505 506 /* 507 * GYRO_DATA_X1 508 * Register Name : GYRO_DATA_X1 509 */ 510 511 /* 512 * gyro_data_x 513 * Gyro X axis data 514 */ 515 #define GYRO_DATA_X1_GYRO_DATA_X_POS 0x00 516 #define GYRO_DATA_X1_GYRO_DATA_X_MASK 0xff 517 518 519 520 /* 521 * GYRO_DATA_X0 522 * Register Name : GYRO_DATA_X0 523 */ 524 525 /* 526 * gyro_data_x 527 * Gyro X axis data 528 */ 529 #define GYRO_DATA_X0_GYRO_DATA_X_POS 0x00 530 #define GYRO_DATA_X0_GYRO_DATA_X_MASK 0xff 531 532 533 534 /* 535 * GYRO_DATA_Y1 536 * Register Name : GYRO_DATA_Y1 537 */ 538 539 /* 540 * gyro_data_y 541 * Gyro Y axis data 542 */ 543 #define GYRO_DATA_Y1_GYRO_DATA_Y_POS 0x00 544 #define GYRO_DATA_Y1_GYRO_DATA_Y_MASK 0xff 545 546 547 548 /* 549 * GYRO_DATA_Y0 550 * Register Name : GYRO_DATA_Y0 551 */ 552 553 /* 554 * gyro_data_y 555 * Gyro Y axis data 556 */ 557 #define GYRO_DATA_Y0_GYRO_DATA_Y_POS 0x00 558 #define GYRO_DATA_Y0_GYRO_DATA_Y_MASK 0xff 559 560 561 562 /* 563 * GYRO_DATA_Z1 564 * Register Name : GYRO_DATA_Z1 565 */ 566 567 /* 568 * gyro_data_z 569 * Gyro Z axis data 570 */ 571 #define GYRO_DATA_Z1_GYRO_DATA_Z_POS 0x00 572 #define GYRO_DATA_Z1_GYRO_DATA_Z_MASK 0xff 573 574 575 576 /* 577 * GYRO_DATA_Z0 578 * Register Name : GYRO_DATA_Z0 579 */ 580 581 /* 582 * gyro_data_z 583 * Gyro Z axis data 584 */ 585 #define GYRO_DATA_Z0_GYRO_DATA_Z_POS 0x00 586 #define GYRO_DATA_Z0_GYRO_DATA_Z_MASK 0xff 587 588 589 590 /* 591 * TMST_FSYNCH 592 * Register Name : TMST_FSYNCH 593 */ 594 595 /* 596 * tmst_fsync_data 597 * Stores the time delta from the rising edge of FSYNC to the latest ODR until the UI Interface reads the FSYNC tag in the status register 598 */ 599 #define TMST_FSYNCH_TMST_FSYNC_DATA_POS 0x00 600 #define TMST_FSYNCH_TMST_FSYNC_DATA_MASK 0xff 601 602 603 604 /* 605 * TMST_FSYNCL 606 * Register Name : TMST_FSYNCL 607 */ 608 609 /* 610 * tmst_fsync_data 611 * Stores the time delta from the rising edge of FSYNC to the latest ODR until the UI Interface reads the FSYNC tag in the status register 612 */ 613 #define TMST_FSYNCL_TMST_FSYNC_DATA_POS 0x00 614 #define TMST_FSYNCL_TMST_FSYNC_DATA_MASK 0xff 615 616 617 618 /* 619 * APEX_DATA4 620 * Register Name : APEX_DATA4 621 */ 622 623 /* 624 * ff_dur 625 * Free Fall duration. The duration is given in number of samples and it can be converted to freefall distance by applying the following formula: 626 * ff_distance = 0.5*9.81*(ff_duration*dmp_odr_s)^2) 627 * Note: dmp_odr_s in the duration of DMP_ODR expressed in seconds. 628 */ 629 #define APEX_DATA4_FF_DUR_POS 0x00 630 #define APEX_DATA4_FF_DUR_MASK 0xff 631 632 633 634 /* 635 * APEX_DATA5 636 * Register Name : APEX_DATA5 637 */ 638 639 /* 640 * ff_dur 641 * Free Fall duration. The duration is given in number of samples and it can be converted to freefall distance by applying the following formula: 642 * ff_distance = 0.5*9.81*(ff_duration*dmp_odr_s)^2) 643 * Note: dmp_odr_s in the duration of DMP_ODR expressed in seconds. 644 */ 645 #define APEX_DATA5_FF_DUR_POS 0x00 646 #define APEX_DATA5_FF_DUR_MASK 0xff 647 648 649 650 /* 651 * PWR_MGMT0 652 * Register Name : PWR_MGMT0 653 */ 654 655 /* 656 * accel_lp_clk_sel 657 * 0: Accelerometer LP mode uses Wake Up oscillator clock. This is the lowest power consumption mode and it is the recommended setting. 658 * 1: Accelerometer LP mode uses RC oscillator clock. 659 * 660 * This field can be changed on-the-fly even if accel sensor is on. 661 */ 662 #define PWR_MGMT0_ACCEL_LP_CLK_SEL_POS 0x07 663 #define PWR_MGMT0_ACCEL_LP_CLK_SEL_MASK (0x01 << PWR_MGMT0_ACCEL_LP_CLK_SEL_POS) 664 665 /* 666 * idle 667 * If this bit is set to 1, the RC oscillator is powered on even if Accel and Gyro are powered off. 668 * Nominally this bit is set to 0, so when Accel and Gyro are powered off, 669 * the chip will go to OFF state , since the RC oscillator will also be powered off. 670 * 671 * This field can be changed on-the-fly even if a sensor is already on 672 */ 673 #define PWR_MGMT0_IDLE_POS 0x04 674 #define PWR_MGMT0_IDLE_MASK (0x01 << PWR_MGMT0_IDLE_POS) 675 676 /* 677 * gyro_mode 678 * 00: Turns gyroscope off 679 * 01: Places gyroscope in Standby Mode 680 * 10: Reserved 681 * 11: Places gyroscope in Low Noise (LN) Mode 682 * 683 * Gyroscope needs to be kept ON for a minimum of 45ms. When transitioning from OFF to any of the other modes, do not issue any register writes for 200 µs. 684 * 685 * This field can be changed on-the-fly even if gyro sensor is on 686 */ 687 #define PWR_MGMT0_GYRO_MODE_POS 0x02 688 #define PWR_MGMT0_GYRO_MODE_MASK (0x03 << PWR_MGMT0_GYRO_MODE_POS) 689 690 /* 691 * accel_mode 692 * 00: Turns accelerometer off 693 * 01: Turns accelerometer off 694 * 10: Places accelerometer in Low Power (LP) Mode 695 * 11: Places accelerometer in Low Noise (LN) Mode 696 * 697 * When selecting LP Mode please refer to ACCEL_LP_CLK_SEL setting, bit[7] of this register. 698 * 699 * Before entering LP mode and during LP Mode the following combinations of ODR and averaging are not permitted: 700 * 1) ODR=1600 Hz or ODR=800 Hz: any averaging. 701 * 2) ODR=400 Hz: averaging=16x, 32x or 64x. 702 * 3) ODR=200 Hz: averaging=64x. 703 * 704 * When transitioning from OFF to any of the other modes, do not issue any register writes for 200 µs. 705 * 706 * This field can be changed on-the-fly even if accel sensor is on 707 */ 708 #define PWR_MGMT0_ACCEL_MODE_POS 0x00 709 #define PWR_MGMT0_ACCEL_MODE_MASK 0x03 710 711 712 713 /* 714 * GYRO_CONFIG0 715 * Register Name : GYRO_CONFIG0 716 */ 717 718 /* 719 * gyro_ui_fs_sel 720 * Full scale select for gyroscope UI interface output 721 * 722 * 00: ±2000 dps 723 * 01: ±1000 dps 724 * 10: ±500 dps 725 * 11: ±250 dps 726 * 727 * This field can be changed on-the-fly even if gyro sensor is on 728 */ 729 #define GYRO_CONFIG0_GYRO_UI_FS_SEL_POS 0x05 730 #define GYRO_CONFIG0_GYRO_UI_FS_SEL_MASK (0x03 << GYRO_CONFIG0_GYRO_UI_FS_SEL_POS) 731 732 /* 733 * gyro_odr 734 * Gyroscope ODR selection for UI interface output 735 * 736 * 0000: Reserved 737 * 0001: Reserved 738 * 0010: Reserved 739 * 0011: Reserved 740 * 0100: Reserved 741 * 0101: 1.6k Hz 742 * 0110: 800 Hz 743 * 0111: 400 Hz 744 * 1000: 200 Hz 745 * 1001: 100 Hz 746 * 1010: 50 Hz 747 * 1011: 25 Hz 748 * 1100: 12.5 Hz 749 * 1101: Reserved 750 * 1110: Reserved 751 * 1111: Reserved 752 * 753 * This field can be changed on-the-fly even if gyro sensor is on 754 */ 755 #define GYRO_CONFIG0_GYRO_ODR_POS 0x00 756 #define GYRO_CONFIG0_GYRO_ODR_MASK 0x0f 757 758 759 760 /* 761 * ACCEL_CONFIG0 762 * Register Name : ACCEL_CONFIG0 763 */ 764 765 /* 766 * accel_ui_fs_sel 767 * Full scale select for accelerometer UI interface output 768 * 769 * 00: ±16g 770 * 01: ±8g 771 * 10: ±4g 772 * 11: ±2g 773 * 774 * This field can be changed on-the-fly even if accel sensor is on 775 */ 776 #define ACCEL_CONFIG0_ACCEL_UI_FS_SEL_POS 0x05 777 #define ACCEL_CONFIG0_ACCEL_UI_FS_SEL_MASK (0x03 << ACCEL_CONFIG0_ACCEL_UI_FS_SEL_POS) 778 779 /* 780 * accel_odr 781 * Accelerometer ODR selection for UI interface output 782 * 783 * 0000: Reserved 784 * 0001: Reserved 785 * 0010: Reserved 786 * 0011: Reserved 787 * 0100: Reserved 788 * 0101: 1.6 kHz (LN mode) 789 * 0110: 800 Hz (LN mode) 790 * 0111: 400 Hz (LP or LN mode) 791 * 1000: 200 Hz (LP or LN mode) 792 * 1001: 100 Hz (LP or LN mode) 793 * 1010: 50 Hz (LP or LN mode) 794 * 1011: 25 Hz (LP or LN mode) 795 * 1100: 12.5 Hz (LP or LN mode) 796 * 1101: 6.25 Hz (LP mode) 797 * 1110: 3.125 Hz (LP mode) 798 * 1111: 1.5625 Hz (LP mode) 799 * 800 * This field can be changed on-the-fly when accel sensor is on 801 */ 802 #define ACCEL_CONFIG0_ACCEL_ODR_POS 0x00 803 #define ACCEL_CONFIG0_ACCEL_ODR_MASK 0x0f 804 805 806 807 /* 808 * TEMP_CONFIG0 809 * Register Name : TEMP_CONFIG0 810 */ 811 812 /* 813 * temp_filt_bw 814 * Sets the bandwidth of the temperature signal DLPF 815 * 816 * 000: DLPF bypassed 817 * 001: DLPF BW = 180 Hz 818 * 010: DLPF BW = 72 Hz 819 * 011: DLPF BW = 34 Hz 820 * 100: DLPF BW = 16 Hz 821 * 101: DLPF BW = 8 Hz 822 * 110: DLPF BW = 4 Hz 823 * 111: DLPF BW = 4 Hz 824 * 825 * This field can be changed on-the-fly even if sensor is on 826 */ 827 #define TEMP_CONFIG0_TEMP_FILT_BW_POS 0x04 828 #define TEMP_CONFIG0_TEMP_FILT_BW_MASK (0x07 << TEMP_CONFIG0_TEMP_FILT_BW_POS) 829 830 831 832 /* 833 * GYRO_CONFIG1 834 * Register Name : GYRO_CONFIG1 835 */ 836 837 /* 838 * gyro_ui_filt_bw 839 * Selects GYRO UI low pass filter bandwidth 840 * 841 * 000: Low pass filter bypassed 842 * 001: 180 Hz 843 * 010: 121 Hz 844 * 011: 73 Hz 845 * 100: 53 Hz 846 * 101: 34 Hz 847 * 110: 25 Hz 848 * 111: 16 Hz 849 * 850 * This field can be changed on-the-fly even if gyro sensor is on 851 */ 852 #define GYRO_CONFIG1_GYRO_UI_FILT_BW_POS 0x00 853 #define GYRO_CONFIG1_GYRO_UI_FILT_BW_MASK 0x07 854 855 856 857 /* 858 * ACCEL_CONFIG1 859 * Register Name : ACCEL_CONFIG1 860 */ 861 862 /* 863 * accel_ui_avg 864 * Selects averaging filter setting to create accelerometer output in accelerometer low power mode (LPM) 865 * 866 * 000: 2x average 867 * 001: 4x average 868 * 010: 8x average 869 * 011: 16x average 870 * 100: 32x average 871 * 101: 64x average 872 * 110: 64x average 873 * 111: 64x average 874 * 875 * This field cannot be changed when the accel sensor is in LPM 876 */ 877 #define ACCEL_CONFIG1_ACCEL_UI_AVG_POS 0x04 878 #define ACCEL_CONFIG1_ACCEL_UI_AVG_MASK (0x07 << ACCEL_CONFIG1_ACCEL_UI_AVG_POS) 879 880 /* 881 * accel_ui_filt_bw 882 * Selects ACCEL UI low pass filter bandwidth 883 * 884 * 000: Low pass filter bypassed 885 * 001: 180 Hz 886 * 010: 121 Hz 887 * 011: 73 Hz 888 * 100: 53 Hz 889 * 101: 34 Hz 890 * 110: 25 Hz 891 * 111: 16 Hz 892 * 893 * This field can be changed on-the-fly even if accel sensor is on 894 */ 895 #define ACCEL_CONFIG1_ACCEL_UI_FILT_BW_POS 0x00 896 #define ACCEL_CONFIG1_ACCEL_UI_FILT_BW_MASK 0x07 897 898 899 900 /* 901 * APEX_CONFIG0 902 * Register Name : APEX_CONFIG0 903 */ 904 905 /* 906 * dmp_power_save_en 907 * When this bit is set to 1, power saving is enabled for DMP algorithms 908 */ 909 #define APEX_CONFIG0_DMP_POWER_SAVE_EN_POS 0x03 910 #define APEX_CONFIG0_DMP_POWER_SAVE_EN_MASK (0x01 << APEX_CONFIG0_DMP_POWER_SAVE_EN_POS) 911 912 /* 913 * dmp_init_en 914 * When this bit is set to 1, DMP runs DMP SW initialization procedure. Bit is reset by hardware when the procedure is finished. All other APEX features are ignored as long as DMP_INIT_EN is set. 915 * 916 * This field can be changed on-the-fly even if accel sensor is on. 917 */ 918 #define APEX_CONFIG0_DMP_INIT_EN_POS 0x02 919 #define APEX_CONFIG0_DMP_INIT_EN_MASK (0x01 << APEX_CONFIG0_DMP_INIT_EN_POS) 920 921 /* 922 * dmp_mem_reset_en 923 * When this bit is set to 1, it clears DMP SRAM for APEX operation or Self-test operation. 924 */ 925 #define APEX_CONFIG0_DMP_MEM_RESET_EN_POS 0x00 926 #define APEX_CONFIG0_DMP_MEM_RESET_EN_MASK 0x03 927 928 929 930 /* 931 * APEX_CONFIG1 932 * Register Name : APEX_CONFIG1 933 */ 934 935 /* 936 * smd_enable 937 * 0: Significant Motion Detection not enabled 938 * 1: Significant Motion Detection enabled 939 * 940 * This field can be changed on-the-fly even if accel sensor is on 941 */ 942 #define APEX_CONFIG1_SMD_ENABLE_POS 0x06 943 #define APEX_CONFIG1_SMD_ENABLE_MASK (0x01 << APEX_CONFIG1_SMD_ENABLE_POS) 944 945 /* 946 * ff_enable 947 * 0: Freefall Detection not enabled 948 * 1: Freefall Detection enabled 949 * 950 * This field can be changed on-the-fly even if accel sensor is on 951 */ 952 #define APEX_CONFIG1_FF_ENABLE_POS 0x05 953 #define APEX_CONFIG1_FF_ENABLE_MASK (0x01 << APEX_CONFIG1_FF_ENABLE_POS) 954 955 /* 956 * tilt_enable 957 * 0: Tilt Detection not enabled 958 * 1: Tilt Detection enabled 959 * 960 * This field can be changed on-the-fly even if accel sensor is on 961 */ 962 #define APEX_CONFIG1_TILT_ENABLE_POS 0x04 963 #define APEX_CONFIG1_TILT_ENABLE_MASK (0x01 << APEX_CONFIG1_TILT_ENABLE_POS) 964 965 /* 966 * ped_enable 967 * 0: Pedometer not enabled 968 * 1: Pedometer enabled 969 * 970 * This field can be changed on-the-fly even if accel sensor is on 971 */ 972 #define APEX_CONFIG1_PED_ENABLE_POS 0x03 973 #define APEX_CONFIG1_PED_ENABLE_MASK (0x01 << APEX_CONFIG1_PED_ENABLE_POS) 974 975 /* 976 * dmp_odr 977 * 00: 25 Hz 978 * 01: 400 Hz 979 * 10: 50 Hz 980 * 11: 100 Hz 981 * 982 * The ACCEL_ODR field must be configured to an ODR equal or greater to the DMP_ODR field, for correct device operation. 983 * 984 * This field can be changed on-the-fly even if accel sensor is on 985 */ 986 #define APEX_CONFIG1_DMP_ODR_POS 0x00 987 #define APEX_CONFIG1_DMP_ODR_MASK 0x03 988 989 990 991 /* 992 * WOM_CONFIG 993 * Register Name : WOM_CONFIG 994 */ 995 996 /* 997 * wom_int_dur 998 * Selects Wake on Motion interrupt assertion from among the following options 999 * 1000 * 00: WoM interrupt asserted at first overthreshold event 1001 * 01: WoM interrupt asserted at second overthreshold event 1002 * 10: WoM interrupt asserted at third overthreshold event 1003 * 11: WoM interrupt asserted at fourth overthreshold event 1004 * 1005 * This field can be changed on-the-fly even if accel sensor is on, but it cannot be changed if WOM_EN is already enabled 1006 */ 1007 #define WOM_CONFIG_WOM_INT_DUR_POS 0x03 1008 #define WOM_CONFIG_WOM_INT_DUR_MASK (0x03 << WOM_CONFIG_WOM_INT_DUR_POS) 1009 1010 /* 1011 * wom_int_mode 1012 * 0: Set WoM interrupt on the OR of all enabled accelerometer thresholds 1013 * 1: Set WoM interrupt on the AND of all enabled accelerometer thresholds 1014 * 1015 * This field can be changed on-the-fly even if accel sensor is on, but it cannot be changed if WOM_EN is already enabled 1016 */ 1017 #define WOM_CONFIG_WOM_INT_MODE_POS 0x02 1018 #define WOM_CONFIG_WOM_INT_MODE_MASK (0x01 << WOM_CONFIG_WOM_INT_MODE_POS) 1019 1020 /* 1021 * wom_mode 1022 * 0 - Initial sample is stored. Future samples are compared to initial sample 1023 * 1 - Compare current sample to previous sample 1024 * 1025 * This field can be changed on-the-fly even if accel sensor is already on, but it cannot be changed if wom_en is already enabled. 1026 */ 1027 #define WOM_CONFIG_WOM_MODE_POS 0x01 1028 #define WOM_CONFIG_WOM_MODE_MASK (0x01 << WOM_CONFIG_WOM_MODE_POS) 1029 1030 /* 1031 * wom_en 1032 * 1: enable wake-on-motion detection. 1033 * 0: disable wake-on-motion detection. 1034 * 1035 * This field can be changed on-the-fly even if accel sensor is already on. 1036 */ 1037 #define WOM_CONFIG_WOM_EN_POS 0x00 1038 #define WOM_CONFIG_WOM_EN_MASK 0x01 1039 1040 1041 1042 /* 1043 * FIFO_CONFIG1 1044 * Register Name : FIFO_CONFIG1 1045 */ 1046 1047 /* 1048 * fifo_mode 1049 * FIFO mode control 1050 * 1051 * 0: Stream-to-FIFO Mode 1052 * 1: STOP-on-FULL Mode 1053 */ 1054 #define FIFO_CONFIG1_FIFO_MODE_POS 0x01 1055 #define FIFO_CONFIG1_FIFO_MODE_MASK (0x01 << FIFO_CONFIG1_FIFO_MODE_POS) 1056 1057 /* 1058 * fifo_bypass 1059 * FIFO bypass control 1060 * 0: FIFO is not bypassed 1061 * 1: FIFO is bypassed 1062 */ 1063 #define FIFO_CONFIG1_FIFO_BYPASS_POS 0x00 1064 #define FIFO_CONFIG1_FIFO_BYPASS_MASK 0x01 1065 1066 1067 1068 /* 1069 * FIFO_CONFIG2 1070 * Register Name : FIFO_CONFIG2 1071 */ 1072 1073 /* 1074 * fifo_wm 1075 * FIFO watermark. Generate interrupt when the FIFO reaches or exceeds FIFO_WM size in bytes or records according to FIFO_COUNT_FORMAT setting. FIFO_WM_EN must be zero before writing this register. Interrupt only fires once. This register should be set to non-zero value, before choosing this interrupt source. 1076 * 1077 * This field should be changed when FIFO is empty to avoid spurious interrupts. 1078 */ 1079 #define FIFO_CONFIG2_FIFO_WM_POS 0x00 1080 #define FIFO_CONFIG2_FIFO_WM_MASK 0xff 1081 1082 1083 1084 /* 1085 * FIFO_CONFIG3 1086 * Register Name : FIFO_CONFIG3 1087 */ 1088 1089 /* 1090 * fifo_wm 1091 * FIFO watermark. Generate interrupt when the FIFO reaches or exceeds FIFO_WM size in bytes or records according to FIFO_COUNT_FORMAT setting. FIFO_WM_EN must be zero before writing this register. Interrupt only fires once. This register should be set to non-zero value, before choosing this interrupt source. 1092 * 1093 * This field should be changed when FIFO is empty to avoid spurious interrupts. 1094 */ 1095 #define FIFO_CONFIG3_FIFO_WM_POS 0x00 1096 #define FIFO_CONFIG3_FIFO_WM_MASK 0x0f 1097 1098 1099 1100 /* 1101 * INT_SOURCE0 1102 * Register Name : INT_SOURCE0 1103 */ 1104 1105 /* 1106 * st_int1_en 1107 * 0: Self-Test Done interrupt not routed to INT1 1108 * 1: Self-Test Done interrupt routed to INT1 1109 */ 1110 #define INT_SOURCE0_ST_INT1_EN_POS 0x07 1111 #define INT_SOURCE0_ST_INT1_EN_MASK (0x01 << INT_SOURCE0_ST_INT1_EN_POS) 1112 1113 /* 1114 * fsync_int1_en 1115 * 0: FSYNC interrupt not routed to INT1 1116 * 1: FSYNC interrupt routed to INT1 1117 */ 1118 #define INT_SOURCE0_FSYNC_INT1_EN_POS 0x06 1119 #define INT_SOURCE0_FSYNC_INT1_EN_MASK (0x01 << INT_SOURCE0_FSYNC_INT1_EN_POS) 1120 1121 /* 1122 * pll_rdy_int1_en 1123 * 0: PLL ready interrupt not routed to INT1 1124 * 1: PLL ready interrupt routed to INT1 1125 */ 1126 #define INT_SOURCE0_PLL_RDY_INT1_EN_POS 0x05 1127 #define INT_SOURCE0_PLL_RDY_INT1_EN_MASK (0x01 << INT_SOURCE0_PLL_RDY_INT1_EN_POS) 1128 1129 /* 1130 * reset_done_int1_en 1131 * 0: Reset done interrupt not routed to INT1 1132 * 1: Reset done interrupt routed to INT1 1133 */ 1134 #define INT_SOURCE0_RESET_DONE_INT1_EN_POS 0x04 1135 #define INT_SOURCE0_RESET_DONE_INT1_EN_MASK (0x01 << INT_SOURCE0_RESET_DONE_INT1_EN_POS) 1136 1137 /* 1138 * drdy_int1_en 1139 * 0: Data Ready interrupt not routed to INT1 1140 * 1: Data Ready interrupt routed to INT1 1141 */ 1142 #define INT_SOURCE0_DRDY_INT1_EN_POS 0x03 1143 #define INT_SOURCE0_DRDY_INT1_EN_MASK (0x01 << INT_SOURCE0_DRDY_INT1_EN_POS) 1144 1145 /* 1146 * fifo_ths_int1_en 1147 * 0: FIFO threshold interrupt not routed to INT1 1148 * 1: FIFO threshold interrupt routed to INT1 1149 */ 1150 #define INT_SOURCE0_FIFO_THS_INT1_EN_POS 0x02 1151 #define INT_SOURCE0_FIFO_THS_INT1_EN_MASK (0x01 << INT_SOURCE0_FIFO_THS_INT1_EN_POS) 1152 1153 /* 1154 * fifo_full_int1_en 1155 * 0: FIFO full interrupt not routed to INT1 1156 * 1: FIFO full interrupt routed to INT1 1157 * To avoid FIFO FULL interrupts while reading FIFO, this bit should be disabled while reading FIFO 1158 */ 1159 #define INT_SOURCE0_FIFO_FULL_INT1_EN_POS 0x01 1160 #define INT_SOURCE0_FIFO_FULL_INT1_EN_MASK (0x01 << INT_SOURCE0_FIFO_FULL_INT1_EN_POS) 1161 1162 /* 1163 * agc_rdy_int1_en 1164 * 0: UI AGC ready interrupt not routed to INT1 1165 * 1: UI AGC ready interrupt routed to INT1 1166 */ 1167 #define INT_SOURCE0_AGC_RDY_INT1_EN_POS 0x00 1168 #define INT_SOURCE0_AGC_RDY_INT1_EN_MASK 0x01 1169 1170 1171 1172 /* 1173 * INT_SOURCE1 1174 * Register Name : INT_SOURCE1 1175 */ 1176 1177 /* 1178 * i3c_protocol_error_int1_en 1179 * 0: I3CSM protocol error interrupt not routed to INT1 1180 * 1: I3CSM protocol error interrupt routed to INT1 1181 */ 1182 #define INT_SOURCE1_I3C_PROTOCOL_ERROR_INT1_EN_POS 0x06 1183 #define INT_SOURCE1_I3C_PROTOCOL_ERROR_INT1_EN_MASK (0x01 << INT_SOURCE1_I3C_PROTOCOL_ERROR_INT1_EN_POS) 1184 1185 /* 1186 * smd_int1_en 1187 * 0: SMD interrupt not routed to INT1 1188 * 1: SMD interrupt routed to INT1 1189 */ 1190 #define INT_SOURCE1_SMD_INT1_EN_POS 0x03 1191 #define INT_SOURCE1_SMD_INT1_EN_MASK (0x01 << INT_SOURCE1_SMD_INT1_EN_POS) 1192 1193 /* 1194 * wom_z_int1_en 1195 * 0: Z-axis WOM interrupt not routed to INT1 1196 * 1: Z-axis WOM interrupt routed to INT1 1197 */ 1198 #define INT_SOURCE1_WOM_Z_INT1_EN_POS 0x02 1199 #define INT_SOURCE1_WOM_Z_INT1_EN_MASK (0x01 << INT_SOURCE1_WOM_Z_INT1_EN_POS) 1200 1201 /* 1202 * wom_y_int1_en 1203 * 0: Y-axis WOM interrupt not routed to INT1 1204 * 1: Y-axis WOM interrupt routed to INT1 1205 */ 1206 #define INT_SOURCE1_WOM_Y_INT1_EN_POS 0x01 1207 #define INT_SOURCE1_WOM_Y_INT1_EN_MASK (0x01 << INT_SOURCE1_WOM_Y_INT1_EN_POS) 1208 1209 /* 1210 * wom_x_int1_en 1211 * 0: X-axis WOM interrupt not routed to INT1 1212 * 1: X-axis WOM interrupt routed to INT1 1213 */ 1214 #define INT_SOURCE1_WOM_X_INT1_EN_POS 0x00 1215 #define INT_SOURCE1_WOM_X_INT1_EN_MASK 0x01 1216 1217 1218 1219 /* 1220 * INT_SOURCE3 1221 * Register Name : INT_SOURCE3 1222 */ 1223 1224 /* 1225 * st_int2_en 1226 * 0: Self-Test Done interrupt not routed to INT2 1227 * 1: Self-Test Done interrupt routed to INT2 1228 */ 1229 #define INT_SOURCE3_ST_INT2_EN_POS 0x07 1230 #define INT_SOURCE3_ST_INT2_EN_MASK (0x01 << INT_SOURCE3_ST_INT2_EN_POS) 1231 1232 /* 1233 * fsync_int2_en 1234 * 0: FSYNC interrupt not routed to INT2 1235 * 1: FSYNC interrupt routed to INT2 1236 */ 1237 #define INT_SOURCE3_FSYNC_INT2_EN_POS 0x06 1238 #define INT_SOURCE3_FSYNC_INT2_EN_MASK (0x01 << INT_SOURCE3_FSYNC_INT2_EN_POS) 1239 1240 /* 1241 * pll_rdy_int2_en 1242 * 0: PLL ready interrupt not routed to INT2 1243 * 1: PLL ready interrupt routed to INT2 1244 */ 1245 #define INT_SOURCE3_PLL_RDY_INT2_EN_POS 0x05 1246 #define INT_SOURCE3_PLL_RDY_INT2_EN_MASK (0x01 << INT_SOURCE3_PLL_RDY_INT2_EN_POS) 1247 1248 /* 1249 * reset_done_int2_en 1250 * 0: Reset done interrupt not routed to INT2 1251 * 1: Reset done interrupt routed to INT2 1252 */ 1253 #define INT_SOURCE3_RESET_DONE_INT2_EN_POS 0x04 1254 #define INT_SOURCE3_RESET_DONE_INT2_EN_MASK (0x01 << INT_SOURCE3_RESET_DONE_INT2_EN_POS) 1255 1256 /* 1257 * drdy_int2_en 1258 * 0: Data Ready interrupt not routed to INT2 1259 * 1: Data Ready interrupt routed to INT2 1260 */ 1261 #define INT_SOURCE3_DRDY_INT2_EN_POS 0x03 1262 #define INT_SOURCE3_DRDY_INT2_EN_MASK (0x01 << INT_SOURCE3_DRDY_INT2_EN_POS) 1263 1264 /* 1265 * fifo_ths_int2_en 1266 * 0: FIFO threshold interrupt not routed to INT2 1267 * 1: FIFO threshold interrupt routed to INT2 1268 */ 1269 #define INT_SOURCE3_FIFO_THS_INT2_EN_POS 0x02 1270 #define INT_SOURCE3_FIFO_THS_INT2_EN_MASK (0x01 << INT_SOURCE3_FIFO_THS_INT2_EN_POS) 1271 1272 /* 1273 * fifo_full_int2_en 1274 * 0: FIFO full interrupt not routed to INT2 1275 * 1: FIFO full interrupt routed to INT2 1276 */ 1277 #define INT_SOURCE3_FIFO_FULL_INT2_EN_POS 0x01 1278 #define INT_SOURCE3_FIFO_FULL_INT2_EN_MASK (0x01 << INT_SOURCE3_FIFO_FULL_INT2_EN_POS) 1279 1280 /* 1281 * agc_rdy_int2_en 1282 * 0: AGC ready interrupt not routed to INT2 1283 * 1: AGC ready interrupt routed to INT2 1284 */ 1285 #define INT_SOURCE3_AGC_RDY_INT2_EN_POS 0x00 1286 #define INT_SOURCE3_AGC_RDY_INT2_EN_MASK 0x01 1287 1288 1289 1290 /* 1291 * INT_SOURCE4 1292 * Register Name : INT_SOURCE4 1293 */ 1294 1295 /* 1296 * i3c_protocol_error_int2_en 1297 * 0: I3CSM protocol error interrupt not routed to INT2 1298 * 1: I3CSM protocol error interrupt routed to INT2 1299 */ 1300 #define INT_SOURCE4_I3C_PROTOCOL_ERROR_INT2_EN_POS 0x06 1301 #define INT_SOURCE4_I3C_PROTOCOL_ERROR_INT2_EN_MASK (0x01 << INT_SOURCE4_I3C_PROTOCOL_ERROR_INT2_EN_POS) 1302 1303 /* 1304 * smd_int2_en 1305 * 0: SMD interrupt not routed to INT2 1306 * 1: SMD interrupt routed to INT2 1307 */ 1308 #define INT_SOURCE4_SMD_INT2_EN_POS 0x03 1309 #define INT_SOURCE4_SMD_INT2_EN_MASK (0x01 << INT_SOURCE4_SMD_INT2_EN_POS) 1310 1311 /* 1312 * wom_z_int2_en 1313 * 0: Z-axis WOM interrupt not routed to INT2 1314 * 1: Z-axis WOM interrupt routed to INT2 1315 */ 1316 #define INT_SOURCE4_WOM_Z_INT2_EN_POS 0x02 1317 #define INT_SOURCE4_WOM_Z_INT2_EN_MASK (0x01 << INT_SOURCE4_WOM_Z_INT2_EN_POS) 1318 1319 /* 1320 * wom_y_int2_en 1321 * 0: Y-axis WOM interrupt not routed to INT2 1322 * 1: Y-axis WOM interrupt routed to INT2 1323 */ 1324 #define INT_SOURCE4_WOM_Y_INT2_EN_POS 0x01 1325 #define INT_SOURCE4_WOM_Y_INT2_EN_MASK (0x01 << INT_SOURCE4_WOM_Y_INT2_EN_POS) 1326 1327 /* 1328 * wom_x_int2_en 1329 * 0: X-axis WOM interrupt not routed to INT2 1330 * 1: X-axis WOM interrupt routed to INT2 1331 */ 1332 #define INT_SOURCE4_WOM_X_INT2_EN_POS 0x00 1333 #define INT_SOURCE4_WOM_X_INT2_EN_MASK 0x01 1334 1335 1336 1337 /* 1338 * FIFO_LOST_PKT0 1339 * Register Name : FIFO_LOST_PKT0 1340 */ 1341 1342 /* 1343 * fifo_lost_pkt_cnt 1344 * Stores the number of packets lost in the FIFO 1345 */ 1346 #define FIFO_LOST_PKT0_FIFO_LOST_PKT_CNT_POS 0x00 1347 #define FIFO_LOST_PKT0_FIFO_LOST_PKT_CNT_MASK 0xff 1348 1349 1350 1351 /* 1352 * FIFO_LOST_PKT1 1353 * Register Name : FIFO_LOST_PKT1 1354 */ 1355 1356 /* 1357 * fifo_lost_pkt_cnt 1358 * Stores the number of packets lost in the FIFO 1359 */ 1360 #define FIFO_LOST_PKT1_FIFO_LOST_PKT_CNT_POS 0x00 1361 #define FIFO_LOST_PKT1_FIFO_LOST_PKT_CNT_MASK 0xff 1362 1363 1364 1365 /* 1366 * APEX_DATA0 1367 * Register Name : APEX_DATA0 1368 */ 1369 1370 /* 1371 * step_cnt 1372 * This status register indicates number of step taken. 1373 */ 1374 #define APEX_DATA0_STEP_CNT_POS 0x00 1375 #define APEX_DATA0_STEP_CNT_MASK 0xff 1376 1377 1378 1379 /* 1380 * APEX_DATA1 1381 * Register Name : APEX_DATA1 1382 */ 1383 1384 /* 1385 * step_cnt 1386 * This status register indicates number of step taken. 1387 */ 1388 #define APEX_DATA1_STEP_CNT_POS 0x00 1389 #define APEX_DATA1_STEP_CNT_MASK 0xff 1390 1391 1392 1393 /* 1394 * APEX_DATA2 1395 * Register Name : APEX_DATA2 1396 */ 1397 1398 /* 1399 * step_cadence 1400 * Pedometer step cadence.Walk/run cadency in number of samples. Format is u6.2. 1401 * E.g, At 50Hz and 2Hz walk frequency, the cadency is 25 samples. The register will output 100. 1402 */ 1403 #define APEX_DATA2_STEP_CADENCE_POS 0x00 1404 #define APEX_DATA2_STEP_CADENCE_MASK 0xff 1405 1406 1407 1408 /* 1409 * APEX_DATA3 1410 * Register Name : APEX_DATA3 1411 */ 1412 1413 /* 1414 * dmp_idle 1415 * 0: Indicates DMP is running 1416 * 1: Indicates DMP is idle 1417 */ 1418 #define APEX_DATA3_DMP_IDLE_POS 0x02 1419 #define APEX_DATA3_DMP_IDLE_MASK (0x01 << APEX_DATA3_DMP_IDLE_POS) 1420 1421 /* 1422 * activity_class 1423 * Pedometer Output: Detected activity 1424 * 1425 * 00: Unknown 1426 * 01: Walk 1427 * 10: Run 1428 * 11: Reserved 1429 */ 1430 #define APEX_DATA3_ACTIVITY_CLASS_POS 0x00 1431 #define APEX_DATA3_ACTIVITY_CLASS_MASK 0x03 1432 1433 1434 1435 /* 1436 * INTF_CONFIG0 1437 * Register Name : INTF_CONFIG0 1438 */ 1439 1440 /* 1441 * fifo_count_format 1442 * 0: FIFO count is reported in bytes 1443 * 1: FIFO count is reported in records (1 record = 16 bytes for header + gyro + accel + temp sensor data + time stamp, or 8 bytes for header + gyro/accel + temp sensor data) 1444 */ 1445 #define INTF_CONFIG0_FIFO_COUNT_FORMAT_POS 0x06 1446 #define INTF_CONFIG0_FIFO_COUNT_FORMAT_MASK (0x01 << INTF_CONFIG0_FIFO_COUNT_FORMAT_POS) 1447 1448 /* 1449 * fifo_count_endian 1450 * This bit applies to both fifo_count and lost_pkt_count 1451 * 0 : Little Endian (The LSByte data is read first, followed by MSByte data). 1452 * 1 : Big Endian (The MSByte data is read first, followed by LSByte data). 1453 */ 1454 #define INTF_CONFIG0_FIFO_COUNT_ENDIAN_POS 0x05 1455 #define INTF_CONFIG0_FIFO_COUNT_ENDIAN_MASK (0x01 << INTF_CONFIG0_FIFO_COUNT_ENDIAN_POS) 1456 1457 /* 1458 * sensor_data_endian 1459 * This bit applies to sensor data to AP, and fifo data. 1460 * 0 : Little Endian (The LSByte data is read first, followed by MSByte data). 1461 * 1 : Big Endian (The MSByte data is read first, followed by LSByte data). 1462 */ 1463 #define INTF_CONFIG0_SENSOR_DATA_ENDIAN_POS 0x04 1464 #define INTF_CONFIG0_SENSOR_DATA_ENDIAN_MASK (0x01 << INTF_CONFIG0_SENSOR_DATA_ENDIAN_POS) 1465 1466 /* 1467 * INTF_CONFIG1 1468 * Register Name : INTF_CONFIG1 1469 */ 1470 1471 /* 1472 * i3c_sdr_en 1473 * 0: I3CSM SDR mode not enabled 1474 * 1: I3CSM SDR mode enabled 1475 * 1476 * Device will be in pure I2C mode if {I3C_SDR_EN, I3C_DDR_EN} = 00 1477 */ 1478 #define INTF_CONFIG1_I3C_SDR_EN_POS 0x03 1479 #define INTF_CONFIG1_I3C_SDR_EN_MASK (0x01 << INTF_CONFIG1_I3C_SDR_EN_POS) 1480 1481 /* 1482 * i3c_ddr_en 1483 * 0: I3CSM DDR mode not enabled 1484 * 1: I3CSM DDR mode enabled 1485 * 1486 * This bit will not take effect unless I3C_SDR_EN = 1. 1487 */ 1488 #define INTF_CONFIG1_I3C_DDR_EN_POS 0x02 1489 #define INTF_CONFIG1_I3C_DDR_EN_MASK (0x01 << INTF_CONFIG1_I3C_DDR_EN_POS) 1490 1491 /* 1492 * clksel 1493 * 00 Alway select internal RC oscillator 1494 * 01 Select PLL when available, else select RC oscillator (default) 1495 * 10 (Reserved) 1496 * 11 Disable all clocks 1497 */ 1498 #define INTF_CONFIG1_CLKSEL_POS 0x00 1499 #define INTF_CONFIG1_CLKSEL_MASK 0x03 1500 1501 1502 1503 /* 1504 * INT_STATUS_DRDY 1505 * Register Name : INT_STATUS_DRDY 1506 */ 1507 1508 /* 1509 * data_rdy_int 1510 * This bit automatically sets to 1 when a Data Ready interrupt is generated. The bit clears to 0 after the register has been read. 1511 */ 1512 #define INT_STATUS_DRDY_DATA_RDY_INT_POS 0x00 1513 #define INT_STATUS_DRDY_DATA_RDY_INT_MASK 0x01 1514 1515 1516 1517 /* 1518 * INT_STATUS 1519 * Register Name : INT_STATUS 1520 */ 1521 1522 /* 1523 * st_int 1524 * This bit automatically sets to 1 when a Self Test done interrupt is generated. The bit clears to 0 after the register has been read. 1525 */ 1526 #define INT_STATUS_ST_INT_POS 0x07 1527 #define INT_STATUS_ST_INT_MASK (0x01 << INT_STATUS_ST_INT_POS) 1528 1529 /* 1530 * fsync_int 1531 * This bit automatically sets to 1 when an FSYNC interrupt is generated. The bit clears to 0 after the register has been read. 1532 */ 1533 #define INT_STATUS_FSYNC_INT_POS 0x06 1534 #define INT_STATUS_FSYNC_INT_MASK (0x01 << INT_STATUS_FSYNC_INT_POS) 1535 1536 /* 1537 * pll_rdy_int 1538 * This bit automatically sets to 1 when a PLL Ready interrupt is generated. The bit clears to 0 after the register has been read. 1539 */ 1540 #define INT_STATUS_PLL_RDY_INT_POS 0x05 1541 #define INT_STATUS_PLL_RDY_INT_MASK (0x01 << INT_STATUS_PLL_RDY_INT_POS) 1542 1543 /* 1544 * reset_done_int 1545 * This bit automatically sets to 1 when software reset is complete. The bit clears to 0 after the register has been read. 1546 */ 1547 #define INT_STATUS_RESET_DONE_INT_POS 0x04 1548 #define INT_STATUS_RESET_DONE_INT_MASK (0x01 << INT_STATUS_RESET_DONE_INT_POS) 1549 1550 /* 1551 * fifo_ths_int 1552 * This bit automatically sets to 1 when the FIFO buffer reaches the threshold value. The bit clears to 0 after the register has been read. 1553 */ 1554 #define INT_STATUS_FIFO_THS_INT_POS 0x02 1555 #define INT_STATUS_FIFO_THS_INT_MASK (0x01 << INT_STATUS_FIFO_THS_INT_POS) 1556 1557 /* 1558 * fifo_full_int 1559 * This bit automatically sets to 1 when the FIFO buffer is full. The bit clears to 0 after the register has been read. 1560 */ 1561 #define INT_STATUS_FIFO_FULL_INT_POS 0x01 1562 #define INT_STATUS_FIFO_FULL_INT_MASK (0x01 << INT_STATUS_FIFO_FULL_INT_POS) 1563 1564 /* 1565 * agc_rdy_int 1566 * This bit automatically sets to 1 when an AGC Ready interrupt is generated. The bit clears to 0 after the register has been read. 1567 */ 1568 #define INT_STATUS_AGC_RDY_INT_POS 0x00 1569 #define INT_STATUS_AGC_RDY_INT_MASK 0x01 1570 1571 1572 1573 /* 1574 * INT_STATUS2 1575 * Register Name : INT_STATUS2 1576 */ 1577 1578 /* 1579 * smd_int 1580 * Significant Motion Detection Interrupt, clears on read 1581 */ 1582 #define INT_STATUS2_SMD_INT_POS 0x03 1583 #define INT_STATUS2_SMD_INT_MASK (0x01 << INT_STATUS2_SMD_INT_POS) 1584 1585 /* 1586 * wom_x_int 1587 * Wake on Motion Interrupt on X-axis, clears on read 1588 */ 1589 #define INT_STATUS2_WOM_X_INT_POS 0x02 1590 #define INT_STATUS2_WOM_X_INT_MASK (0x01 << INT_STATUS2_WOM_X_INT_POS) 1591 1592 /* 1593 * wom_y_int 1594 * Wake on Motion Interrupt on Y-axis, clears on read 1595 */ 1596 #define INT_STATUS2_WOM_Y_INT_POS 0x01 1597 #define INT_STATUS2_WOM_Y_INT_MASK (0x01 << INT_STATUS2_WOM_Y_INT_POS) 1598 1599 /* 1600 * wom_z_int 1601 * Wake on Motion Interrupt on Z-axis, clears on read 1602 */ 1603 #define INT_STATUS2_WOM_Z_INT_POS 0x00 1604 #define INT_STATUS2_WOM_Z_INT_MASK 0x01 1605 1606 1607 1608 /* 1609 * INT_STATUS3 1610 * Register Name : INT_STATUS3 1611 */ 1612 1613 /* 1614 * step_det_int 1615 * Step Detection Interrupt, clears on read 1616 */ 1617 #define INT_STATUS3_STEP_DET_INT_POS 0x05 1618 #define INT_STATUS3_STEP_DET_INT_MASK (0x01 << INT_STATUS3_STEP_DET_INT_POS) 1619 1620 /* 1621 * step_cnt_ovf_int 1622 * Step Count Overflow Interrupt, clears on read 1623 */ 1624 #define INT_STATUS3_STEP_CNT_OVF_INT_POS 0x04 1625 #define INT_STATUS3_STEP_CNT_OVF_INT_MASK (0x01 << INT_STATUS3_STEP_CNT_OVF_INT_POS) 1626 1627 /* 1628 * tilt_det_int 1629 * Tilt Detection Interrupt, clears on read 1630 */ 1631 #define INT_STATUS3_TILT_DET_INT_POS 0x03 1632 #define INT_STATUS3_TILT_DET_INT_MASK (0x01 << INT_STATUS3_TILT_DET_INT_POS) 1633 1634 /* 1635 * ff_det_int 1636 * Freefall Interrupt, clears on read 1637 */ 1638 #define INT_STATUS3_FF_DET_INT_POS 0x02 1639 #define INT_STATUS3_FF_DET_INT_MASK (0x01 << INT_STATUS3_FF_DET_INT_POS) 1640 1641 /* 1642 * lowg_det_int 1643 * LowG Interrupt, clears on read 1644 */ 1645 #define INT_STATUS3_LOWG_DET_INT_POS 0x01 1646 #define INT_STATUS3_LOWG_DET_INT_MASK (0x01 << INT_STATUS3_LOWG_DET_INT_POS) 1647 1648 1649 1650 /* 1651 * FIFO_COUNTH 1652 * Register Name : FIFO_COUNTH 1653 */ 1654 1655 /* 1656 * fifo_count 1657 * Number of bytes in FIFO when fifo_count_format=0. 1658 * Number of records in FIFO when fifo_count_format=1. 1659 */ 1660 #define FIFO_COUNTH_FIFO_COUNT_POS 0x00 1661 #define FIFO_COUNTH_FIFO_COUNT_MASK 0xff 1662 1663 1664 1665 /* 1666 * FIFO_COUNTL 1667 * Register Name : FIFO_COUNTL 1668 */ 1669 1670 /* 1671 * fifo_count 1672 * Number of bytes in FIFO when fifo_count_format=0. 1673 * Number of records in FIFO when fifo_count_format=1. 1674 */ 1675 #define FIFO_COUNTL_FIFO_COUNT_POS 0x00 1676 #define FIFO_COUNTL_FIFO_COUNT_MASK 0xff 1677 1678 1679 1680 /* 1681 * FIFO_DATA 1682 * Register Name : FIFO_DATA 1683 */ 1684 1685 /* 1686 * fifo_data 1687 * FIFO data port 1688 */ 1689 #define FIFO_DATA_FIFO_DATA_POS 0x00 1690 #define FIFO_DATA_FIFO_DATA_MASK 0xff 1691 1692 1693 1694 /* 1695 * WHO_AM_I 1696 * Register Name : WHO_AM_I 1697 */ 1698 1699 /* 1700 * whoami 1701 * Register to indicate to user which device is being accessed 1702 */ 1703 #define WHO_AM_I_WHOAMI_POS 0x00 1704 #define WHO_AM_I_WHOAMI_MASK 0xff 1705 1706 1707 1708 /* 1709 * BLK_SEL_W 1710 * Register Name : BLK_SEL_W 1711 */ 1712 1713 /* 1714 * blk_sel_w 1715 * For write operation, select a 256-byte MCLK space, or 128-byte SCLK space. 1716 * Automatically reset when OTP copy operation is triggered. 1717 */ 1718 #define BLK_SEL_W_BLK_SEL_W_POS 0x00 1719 #define BLK_SEL_W_BLK_SEL_W_MASK 0xff 1720 1721 1722 1723 /* 1724 * MADDR_W 1725 * Register Name : MADDR_W 1726 */ 1727 1728 /* 1729 * maddr_w 1730 * For MREG write operation, the lower 8-bit address for accessing MCLK domain registers. 1731 */ 1732 #define MADDR_W_MADDR_W_POS 0x00 1733 #define MADDR_W_MADDR_W_MASK 0xff 1734 1735 1736 1737 /* 1738 * M_W 1739 * Register Name : M_W 1740 */ 1741 1742 /* 1743 * m_w 1744 * For MREG write operation, the write port for accessing MCLK domain registers. 1745 */ 1746 #define M_W_M_W_POS 0x00 1747 #define M_W_M_W_MASK 0xff 1748 1749 1750 1751 /* 1752 * BLK_SEL_R 1753 * Register Name : BLK_SEL_R 1754 */ 1755 1756 /* 1757 * blk_sel_r 1758 * For read operation, select a 256-byte MCLK space, or 128-byte SCLK space. 1759 * Automatically reset when OTP copy operation is triggered. 1760 */ 1761 #define BLK_SEL_R_BLK_SEL_R_POS 0x00 1762 #define BLK_SEL_R_BLK_SEL_R_MASK 0xff 1763 1764 1765 1766 /* 1767 * MADDR_R 1768 * Register Name : MADDR_R 1769 */ 1770 1771 /* 1772 * maddr_r 1773 * For MREG read operation, the lower 8-bit address for accessing MCLK domain registers. 1774 */ 1775 #define MADDR_R_MADDR_R_POS 0x00 1776 #define MADDR_R_MADDR_R_MASK 0xff 1777 1778 1779 1780 /* 1781 * M_R 1782 * Register Name : M_R 1783 */ 1784 1785 /* 1786 * m_r 1787 * For MREG read operation, the read port for accessing MCLK domain registers. 1788 */ 1789 #define M_R_M_R_POS 0x00 1790 #define M_R_M_R_MASK 0xff 1791 1792 1793 /* --------------------------------------------------------------------------- 1794 * register MREG1 1795 * ---------------------------------------------------------------------------*/ 1796 1797 /* 1798 * TMST_CONFIG1 1799 * Register Name : TMST_CONFIG1 1800 */ 1801 1802 /* 1803 * tmst_res 1804 * Time Stamp resolution; When set to 0 (default), time stamp resolution is 1 us. When set to 1, resolution is 16us 1805 */ 1806 #define TMST_CONFIG1_TMST_RES_POS 0x03 1807 #define TMST_CONFIG1_TMST_RES_MASK (0x01 << TMST_CONFIG1_TMST_RES_POS) 1808 1809 /* 1810 * tmst_delta_en 1811 * Time Stamp delta Enable : When set to 1, the Time stamp field contains the measurement of time since the last occurrence of ODR. 1812 */ 1813 #define TMST_CONFIG1_TMST_DELTA_EN_POS 0x02 1814 #define TMST_CONFIG1_TMST_DELTA_EN_MASK (0x01 << TMST_CONFIG1_TMST_DELTA_EN_POS) 1815 1816 /* 1817 * tmst_fsync_en 1818 * Time Stamp register Fsync Enable . When set to 1, the contents of the Timestamp feature of FSYNC is enabled. The user also needs to select fifo_tmst_fsync_en in order to propagate the timestamp value to the FIFO 1819 */ 1820 #define TMST_CONFIG1_TMST_FSYNC_EN_POS 0x01 1821 #define TMST_CONFIG1_TMST_FSYNC_EN_MASK (0x01 << TMST_CONFIG1_TMST_FSYNC_EN_POS) 1822 1823 /* 1824 * tmst_en 1825 * Time Stamp register Enable 1826 */ 1827 #define TMST_CONFIG1_TMST_EN_POS 0x00 1828 #define TMST_CONFIG1_TMST_EN_MASK 0x01 1829 1830 1831 1832 /* 1833 * FIFO_CONFIG5 1834 * Register Name : FIFO_CONFIG5 1835 */ 1836 1837 /* 1838 * fifo_wm_gt_th 1839 * 1: trigger FIFO-Watermark interrupt on every ODR(DMA Write) if FIFO_COUNT: =FIFO_WM 1840 * 1841 * 0: Trigger FIFO-Watermark interrupt when FIFO_COUNT == FIFO_WM 1842 */ 1843 #define FIFO_CONFIG5_FIFO_WM_GT_TH_POS 0x05 1844 #define FIFO_CONFIG5_FIFO_WM_GT_TH_MASK (0x01 << FIFO_CONFIG5_FIFO_WM_GT_TH_POS) 1845 1846 /* 1847 * fifo_resume_partial_rd 1848 * 0: FIFO is read in packets. If a partial packet is read, then the subsequent read will start from the beginning of the un-read packet. 1849 * 1: FIFO can be read partially. When read is resumed, FIFO bytes will continue from last read point. The SW driver is responsible for cascading previous read and present read and maintain frame boundaries. 1850 */ 1851 #define FIFO_CONFIG5_FIFO_RESUME_PARTIAL_RD_POS 0x04 1852 #define FIFO_CONFIG5_FIFO_RESUME_PARTIAL_RD_MASK (0x01 << FIFO_CONFIG5_FIFO_RESUME_PARTIAL_RD_POS) 1853 1854 /* 1855 * fifo_hires_en 1856 * Allows 20 bit resolution in the FIFO packet readout 1857 */ 1858 #define FIFO_CONFIG5_FIFO_HIRES_EN_POS 0x03 1859 #define FIFO_CONFIG5_FIFO_HIRES_EN_MASK (0x01 << FIFO_CONFIG5_FIFO_HIRES_EN_POS) 1860 1861 /* 1862 * fifo_tmst_fsync_en 1863 * Allows the TMST in the FIFO to be replaced by the FSYNC timestamp 1864 */ 1865 #define FIFO_CONFIG5_FIFO_TMST_FSYNC_EN_POS 0x02 1866 #define FIFO_CONFIG5_FIFO_TMST_FSYNC_EN_MASK (0x01 << FIFO_CONFIG5_FIFO_TMST_FSYNC_EN_POS) 1867 1868 /* 1869 * fifo_gyro_en 1870 * Enables Gyro Packets to go to FIFO 1871 */ 1872 #define FIFO_CONFIG5_FIFO_GYRO_EN_POS 0x01 1873 #define FIFO_CONFIG5_FIFO_GYRO_EN_MASK (0x01 << FIFO_CONFIG5_FIFO_GYRO_EN_POS) 1874 1875 /* 1876 * fifo_accel_en 1877 * Enable Accel Packets to go to FIFO 1878 */ 1879 #define FIFO_CONFIG5_FIFO_ACCEL_EN_POS 0x00 1880 #define FIFO_CONFIG5_FIFO_ACCEL_EN_MASK 0x01 1881 1882 1883 1884 /* 1885 * FIFO_CONFIG6 1886 * Register Name : FIFO_CONFIG6 1887 */ 1888 1889 /* 1890 * fifo_empty_indicator_dis 1891 * 0: xFF is sent out as FIFO data when FIFO is empty. 1892 * 1: The last FIFO data is sent out when FIFO is empty. 1893 */ 1894 #define FIFO_CONFIG6_FIFO_EMPTY_INDICATOR_DIS_POS 0x04 1895 #define FIFO_CONFIG6_FIFO_EMPTY_INDICATOR_DIS_MASK (0x01 << FIFO_CONFIG6_FIFO_EMPTY_INDICATOR_DIS_POS) 1896 1897 /* 1898 * rcosc_req_on_fifo_ths_dis 1899 * 0: When the FIFO is operating in ALP+WUOSC mode and the watermark (WM) interrupt is enabled, the FIFO wakes up the system oscillator (RCOSC) as soon as the watermark level is reached. The system oscillator remains enabled until a Host FIFO read operation happens. This will temporarily cause a small increase in the power consumption due to the enabling of the system oscillator. 1900 * 1: The system oscillator is not automatically woken-up by the FIFO/INT when the WM interrupt is triggered. The side effect is that the host can receive invalid packets until the system oscillator is off after it has been turned on for other reasons not related to a WM interrupt. 1901 * 1902 * The recommended setting of this bit is ‘1’ before entering and during all power modes excluding ALP with WUOSC. This is in order to avoid having to do a FIFO access/flush before entering sleep mode. During ALP with WUOSC it is recommended to set this bit to ‘0’. It is recommended to reset this bit back to ‘1’ before exiting ALP+WUOSC with a wait time of 1 ODR or higher. 1903 */ 1904 #define FIFO_CONFIG6_RCOSC_REQ_ON_FIFO_THS_DIS_POS 0x00 1905 #define FIFO_CONFIG6_RCOSC_REQ_ON_FIFO_THS_DIS_MASK 0x01 1906 1907 1908 1909 /* 1910 * FSYNC_CONFIG 1911 * Register Name : FSYNC_CONFIG 1912 */ 1913 1914 /* 1915 * fsync_ui_sel 1916 * this register was called (ext_sync_sel) 1917 * 0 Do not tag Fsync flag 1918 * 1 Tag Fsync flag to TEMP_OUT’s LSB 1919 * 2 Tag Fsync flag to GYRO_XOUT’s LSB 1920 * 3 Tag Fsync flag to GYRO_YOUT’s LSB 1921 * 4 Tag Fsync flag to GYRO_ZOUT’s LSB 1922 * 5 Tag Fsync flag to ACCEL_XOUT’s LSB 1923 * 6 Tag Fsync flag to ACCEL_YOUT’s LSB 1924 * 7 Tag Fsync flag to ACCEL_ZOUT’s LSB 1925 */ 1926 #define FSYNC_CONFIG_FSYNC_UI_SEL_POS 0x04 1927 #define FSYNC_CONFIG_FSYNC_UI_SEL_MASK (0x07 << FSYNC_CONFIG_FSYNC_UI_SEL_POS) 1928 1929 /* 1930 * fsync_ui_flag_clear_sel 1931 * 0 means the FSYNC flag is cleared when UI sensor reg is updated 1932 * 1 means the FSYNC flag is cleared when UI interface reads the sensor register LSB of FSYNC tagged axis 1933 */ 1934 #define FSYNC_CONFIG_FSYNC_UI_FLAG_CLEAR_SEL_POS 0x01 1935 #define FSYNC_CONFIG_FSYNC_UI_FLAG_CLEAR_SEL_MASK (0x01 << FSYNC_CONFIG_FSYNC_UI_FLAG_CLEAR_SEL_POS) 1936 1937 /* 1938 * fsync_polarity 1939 * 0: Start from Rising edge of FSYNC pulse to measure FSYNC interval 1940 * 1: Start from Falling edge of FSYNC pulse to measure FSYNC interval 1941 */ 1942 #define FSYNC_CONFIG_FSYNC_POLARITY_POS 0x00 1943 #define FSYNC_CONFIG_FSYNC_POLARITY_MASK 0x01 1944 1945 1946 1947 /* 1948 * INT_CONFIG0 1949 * Register Name : INT_CONFIG0 1950 */ 1951 1952 /* 1953 * ui_drdy_int_clear 1954 * Data Ready Interrupt Clear Option (latched mode) 1955 * 00: Clear on Status Bit Read 1956 * 01: Clear on Status Bit Read 1957 * 10: Clear on Sensor Register Read 1958 * 11: Clear on Status Bit Read OR on Sensor Register read 1959 */ 1960 #define INT_CONFIG0_UI_DRDY_INT_CLEAR_POS 0x04 1961 #define INT_CONFIG0_UI_DRDY_INT_CLEAR_MASK (0x03 << INT_CONFIG0_UI_DRDY_INT_CLEAR_POS) 1962 1963 /* 1964 * fifo_ths_int_clear 1965 * FIFO Threshold Interrupt Clear Option (latched mode) 1966 * 00: Clear on Status Bit Read 1967 * 01: Clear on Status Bit Read 1968 * 10: Clear on FIFO data 1Byte Read 1969 * 11: Clear on Status Bit Read OR on FIFO data 1 byte read 1970 */ 1971 #define INT_CONFIG0_FIFO_THS_INT_CLEAR_POS 0x02 1972 #define INT_CONFIG0_FIFO_THS_INT_CLEAR_MASK (0x03 << INT_CONFIG0_FIFO_THS_INT_CLEAR_POS) 1973 1974 /* 1975 * fifo_full_int_clear 1976 * FIFO Full Interrupt Clear Option (latched mode) 1977 * 00: Clear on Status Bit Read 1978 * 01: Clear on Status Bit Read 1979 * 10: Clear on FIFO data 1Byte Read 1980 * 11: Clear on Status Bit Read OR on FIFO data 1 byte read 1981 */ 1982 #define INT_CONFIG0_FIFO_FULL_INT_CLEAR_POS 0x00 1983 #define INT_CONFIG0_FIFO_FULL_INT_CLEAR_MASK 0x03 1984 1985 1986 1987 /* 1988 * INT_CONFIG1 1989 * Register Name : INT_CONFIG1 1990 */ 1991 1992 /* 1993 * int_tpulse_duration 1994 * 0 - (Default) Interrupt pulse duration is 100us 1995 * 1- Interrupt pulse duration is 8 us 1996 */ 1997 #define INT_CONFIG1_INT_TPULSE_DURATION_POS 0x06 1998 #define INT_CONFIG1_INT_TPULSE_DURATION_MASK (0x01 << INT_CONFIG1_INT_TPULSE_DURATION_POS) 1999 2000 /* 2001 * int_async_reset 2002 * 0: The interrupt pulse is reset as soon as the interrupt status register is read if the pulse is still active. 2003 * 1: The interrupt pulse remains high for the intended duration independent of when the interrupt status register is read. This is the default and recommended setting. In this case, when in ALP with the WUOSC clock, the clearing of the interrupt status register requires up to one ODR period after reading. 2004 */ 2005 #define INT_CONFIG1_INT_ASYNC_RESET_POS 0x04 2006 #define INT_CONFIG1_INT_ASYNC_RESET_MASK (0x01 << INT_CONFIG1_INT_ASYNC_RESET_POS) 2007 2008 2009 2010 /* 2011 * SENSOR_CONFIG3 2012 * Register Name : SENSOR_CONFIG3 2013 */ 2014 2015 /* 2016 * apex_disable 2017 * 1: Disable APEX features to extend FIFO size to 2.25 Kbytes 2018 */ 2019 #define SENSOR_CONFIG3_APEX_DISABLE_POS 0x06 2020 #define SENSOR_CONFIG3_APEX_DISABLE_MASK (0x01 << SENSOR_CONFIG3_APEX_DISABLE_POS) 2021 2022 /* 2023 * ST_CONFIG 2024 * Register Name : ST_CONFIG 2025 */ 2026 2027 /* 2028 * accel_st_reg 2029 * User must set this bit to 1 when enabling accelerometer self-test and clear it to 0 when self-test procedure has completed. 2030 */ 2031 #define ST_CONFIG_ACCEL_ST_REG_POS 0x07 2032 #define ST_CONFIG_ACCEL_ST_REG_MASK (0x01 << ST_CONFIG_ACCEL_ST_REG_POS) 2033 2034 /* 2035 * st_number_sample 2036 * This bit selects the number of sensor samples that should be used to process self-test 2037 * 0: 16 samples 2038 * 1: 200 samples 2039 */ 2040 #define ST_CONFIG_ST_NUMBER_SAMPLE_POS 0x06 2041 #define ST_CONFIG_ST_NUMBER_SAMPLE_MASK (0x01 << ST_CONFIG_ST_NUMBER_SAMPLE_POS) 2042 2043 /* 2044 * accel_st_lim 2045 * These bits control the tolerated ratio between self-test processed values and reference (fused) ones for accelerometer. 2046 * 0 : 5% 2047 * 1: 10% 2048 * 2: 15% 2049 * 3: 20% 2050 * 4: 25% 2051 * 5: 30% 2052 * 6: 40% 2053 * 7: 50% 2054 */ 2055 #define ST_CONFIG_ACCEL_ST_LIM_POS 0x03 2056 #define ST_CONFIG_ACCEL_ST_LIM_MASK (0x07 << ST_CONFIG_ACCEL_ST_LIM_POS) 2057 2058 /* 2059 * gyro_st_lim 2060 * These bits control the tolerated ratio between self-test processed values and reference (fused) ones for gyro. 2061 * 0 : 5% 2062 * 1: 10% 2063 * 2: 15% 2064 * 3: 20% 2065 * 4: 25% 2066 * 5: 30% 2067 * 6: 40% 2068 * 7: 50% 2069 */ 2070 #define ST_CONFIG_GYRO_ST_LIM_POS 0x00 2071 #define ST_CONFIG_GYRO_ST_LIM_MASK 0x07 2072 2073 2074 2075 /* 2076 * SELFTEST 2077 * Register Name : SELFTEST 2078 */ 2079 2080 /* 2081 * gyro_st_en 2082 * 1: enable gyro self test operation. Host needs to program this bit to 0 to move chip out of self test mode. If host programs this bit to 0 while st_busy = 1 and st_done =0, the current running self-test operation is terminated by host. 2083 */ 2084 #define SELFTEST_GYRO_ST_EN_POS 0x07 2085 #define SELFTEST_GYRO_ST_EN_MASK (0x01 << SELFTEST_GYRO_ST_EN_POS) 2086 2087 /* 2088 * accel_st_en 2089 * 1: enable accel self test operation. Host needs to program this bit to 0 to move chip out of self test mode. If host programs this bit to 0 while st_busy = 1 and st_done =0, the current running self-test operation is terminated by host. 2090 */ 2091 #define SELFTEST_ACCEL_ST_EN_POS 0x06 2092 #define SELFTEST_ACCEL_ST_EN_MASK (0x01 << SELFTEST_ACCEL_ST_EN_POS) 2093 2094 /* 2095 * en_gz_st 2096 * Enable Gyro Z-axis self test 2097 */ 2098 #define SELFTEST_EN_GZ_ST_POS 0x05 2099 #define SELFTEST_EN_GZ_ST_MASK (0x01 << SELFTEST_EN_GZ_ST_POS) 2100 2101 /* 2102 * en_gy_st 2103 * Enable Gyro Y-axis self test 2104 */ 2105 #define SELFTEST_EN_GY_ST_POS 0x04 2106 #define SELFTEST_EN_GY_ST_MASK (0x01 << SELFTEST_EN_GY_ST_POS) 2107 2108 /* 2109 * en_gx_st 2110 * Enable Gyro X-axis self test 2111 */ 2112 #define SELFTEST_EN_GX_ST_POS 0x03 2113 #define SELFTEST_EN_GX_ST_MASK (0x01 << SELFTEST_EN_GX_ST_POS) 2114 2115 /* 2116 * en_az_st 2117 * Enable Accel Z-axis self test 2118 */ 2119 #define SELFTEST_EN_AZ_ST_POS 0x02 2120 #define SELFTEST_EN_AZ_ST_MASK (0x01 << SELFTEST_EN_AZ_ST_POS) 2121 2122 /* 2123 * en_ay_st 2124 * Enable Accel Y-axis self test 2125 */ 2126 #define SELFTEST_EN_AY_ST_POS 0x01 2127 #define SELFTEST_EN_AY_ST_MASK (0x01 << SELFTEST_EN_AY_ST_POS) 2128 2129 /* 2130 * en_ax_st 2131 * Enable Accel X-axis self test 2132 */ 2133 #define SELFTEST_EN_AX_ST_POS 0x00 2134 #define SELFTEST_EN_AX_ST_MASK 0x01 2135 2136 2137 2138 /* 2139 * INTF_CONFIG6 2140 * Register Name : INTF_CONFIG6 2141 */ 2142 2143 /* 2144 * i3c_timeout_en 2145 * Value of 1 to enable i2c/i3c timeout function 2146 */ 2147 #define INTF_CONFIG6_I3C_TIMEOUT_EN_POS 0x04 2148 #define INTF_CONFIG6_I3C_TIMEOUT_EN_MASK (0x01 << INTF_CONFIG6_I3C_TIMEOUT_EN_POS) 2149 2150 /* 2151 * i3c_ibi_byte_en 2152 * I3C Enable IBI-payload function. 2153 */ 2154 #define INTF_CONFIG6_I3C_IBI_BYTE_EN_POS 0x03 2155 #define INTF_CONFIG6_I3C_IBI_BYTE_EN_MASK (0x01 << INTF_CONFIG6_I3C_IBI_BYTE_EN_POS) 2156 2157 /* 2158 * i3c_ibi_en 2159 * I3C Enable IBI function. 2160 */ 2161 #define INTF_CONFIG6_I3C_IBI_EN_POS 0x02 2162 #define INTF_CONFIG6_I3C_IBI_EN_MASK (0x01 << INTF_CONFIG6_I3C_IBI_EN_POS) 2163 2164 2165 2166 /* 2167 * INTF_CONFIG10 2168 * Register Name : INTF_CONFIG10 2169 */ 2170 2171 /* 2172 * asynctime0_dis 2173 * 1: Disable asynchronous timing control mode 0 operation. 2174 */ 2175 #define INTF_CONFIG10_ASYNCTIME0_DIS_POS 0x07 2176 #define INTF_CONFIG10_ASYNCTIME0_DIS_MASK (0x01 << INTF_CONFIG10_ASYNCTIME0_DIS_POS) 2177 2178 /* 2179 * INTF_CONFIG7 2180 * Register Name : INTF_CONFIG7 2181 */ 2182 2183 /* 2184 * i3c_ddr_wr_mode 2185 * This bit controls how I3C slave treats the 1st 2-byte data from 2186 * host in a DDR write operation. 2187 * 2188 * 0: (a) The 1st-byte in DDR-WR configures the starting register 2189 * address where the write operation should occur. 2190 * (b) The 2nd-byte in DDR-WR is ignored and dropped. 2191 * (c) The 3rd-byte in DDR-WR will be written into the register 2192 * with address specified by the 1st-byte. 2193 * Or, the next DDR-RD will be starting from the address 2194 * specified by the 1st-byte of previous DDR-WR. 2195 * 2196 * 1: (a) The 1st-byte in DDR-WR configures the starting register 2197 * address where the write operation should occur. 2198 * (b) The 2nd-byte in DDR-WR will be written into the register 2199 * with address specified by the 1st-byte. 2200 */ 2201 #define INTF_CONFIG7_I3C_DDR_WR_MODE_POS 0x03 2202 #define INTF_CONFIG7_I3C_DDR_WR_MODE_MASK (0x01 << INTF_CONFIG7_I3C_DDR_WR_MODE_POS) 2203 2204 /* 2205 * OTP_CONFIG 2206 * Register Name : OTP_CONFIG 2207 */ 2208 2209 /* 2210 * otp_copy_mode 2211 * 00: Reserved 2212 * 01: Enable copying OTP block to SRAM 2213 * 10: Reserved 2214 * 11: Enable copying self-test data from OTP memory to SRAM 2215 */ 2216 #define OTP_CONFIG_OTP_COPY_MODE_POS 0x02 2217 #define OTP_CONFIG_OTP_COPY_MODE_MASK (0x03 << OTP_CONFIG_OTP_COPY_MODE_POS) 2218 2219 /* 2220 * INT_SOURCE6 2221 * Register Name : INT_SOURCE6 2222 */ 2223 2224 /* 2225 * ff_int1_en 2226 * 0: Freefall interrupt not routed to INT1 2227 * 1: Freefall interrupt routed to INT1 2228 */ 2229 #define INT_SOURCE6_FF_INT1_EN_POS 0x07 2230 #define INT_SOURCE6_FF_INT1_EN_MASK (0x01 << INT_SOURCE6_FF_INT1_EN_POS) 2231 2232 /* 2233 * lowg_int1_en 2234 * 0: Low-g interrupt not routed to INT1 2235 * 1: Low-g interrupt routed to INT1 2236 */ 2237 #define INT_SOURCE6_LOWG_INT1_EN_POS 0x06 2238 #define INT_SOURCE6_LOWG_INT1_EN_MASK (0x01 << INT_SOURCE6_LOWG_INT1_EN_POS) 2239 2240 /* 2241 * step_det_int1_en 2242 * 0: Step detect interrupt not routed to INT1 2243 * 1: Step detect interrupt routed to INT1 2244 */ 2245 #define INT_SOURCE6_STEP_DET_INT1_EN_POS 0x05 2246 #define INT_SOURCE6_STEP_DET_INT1_EN_MASK (0x01 << INT_SOURCE6_STEP_DET_INT1_EN_POS) 2247 2248 /* 2249 * step_cnt_ofl_int1_en 2250 * 0: Step count overflow interrupt not routed to INT1 2251 * 1: Step count overflow interrupt routed to INT1 2252 */ 2253 #define INT_SOURCE6_STEP_CNT_OFL_INT1_EN_POS 0x04 2254 #define INT_SOURCE6_STEP_CNT_OFL_INT1_EN_MASK (0x01 << INT_SOURCE6_STEP_CNT_OFL_INT1_EN_POS) 2255 2256 /* 2257 * tilt_det_int1_en 2258 * 0: Tilt detect interrupt not routed to INT1 2259 * 1: Tile detect interrupt routed to INT1 2260 */ 2261 #define INT_SOURCE6_TILT_DET_INT1_EN_POS 0x03 2262 #define INT_SOURCE6_TILT_DET_INT1_EN_MASK (0x01 << INT_SOURCE6_TILT_DET_INT1_EN_POS) 2263 2264 2265 2266 /* 2267 * INT_SOURCE7 2268 * Register Name : INT_SOURCE7 2269 */ 2270 2271 /* 2272 * ff_int2_en 2273 * 0: Freefall interrupt not routed to INT2 2274 * 1: Freefall interrupt routed to INT2 2275 */ 2276 #define INT_SOURCE7_FF_INT2_EN_POS 0x07 2277 #define INT_SOURCE7_FF_INT2_EN_MASK (0x01 << INT_SOURCE7_FF_INT2_EN_POS) 2278 2279 /* 2280 * lowg_int2_en 2281 * 0: Low-g interrupt not routed to INT2 2282 * 1: Low-g interrupt routed to INT2 2283 */ 2284 #define INT_SOURCE7_LOWG_INT2_EN_POS 0x06 2285 #define INT_SOURCE7_LOWG_INT2_EN_MASK (0x01 << INT_SOURCE7_LOWG_INT2_EN_POS) 2286 2287 /* 2288 * step_det_int2_en 2289 * 0: Step detect interrupt not routed to INT2 2290 * 1: Step detect interrupt routed to INT2 2291 */ 2292 #define INT_SOURCE7_STEP_DET_INT2_EN_POS 0x05 2293 #define INT_SOURCE7_STEP_DET_INT2_EN_MASK (0x01 << INT_SOURCE7_STEP_DET_INT2_EN_POS) 2294 2295 /* 2296 * step_cnt_ofl_int2_en 2297 * 0: Step count overflow interrupt not routed to INT2 2298 * 1: Step count overflow interrupt routed to INT2 2299 */ 2300 #define INT_SOURCE7_STEP_CNT_OFL_INT2_EN_POS 0x04 2301 #define INT_SOURCE7_STEP_CNT_OFL_INT2_EN_MASK (0x01 << INT_SOURCE7_STEP_CNT_OFL_INT2_EN_POS) 2302 2303 /* 2304 * tilt_det_int2_en 2305 * 0: Tilt detect interrupt not routed to INT2 2306 * 1: Tile detect interrupt routed to INT2 2307 */ 2308 #define INT_SOURCE7_TILT_DET_INT2_EN_POS 0x03 2309 #define INT_SOURCE7_TILT_DET_INT2_EN_MASK (0x01 << INT_SOURCE7_TILT_DET_INT2_EN_POS) 2310 2311 2312 2313 /* 2314 * INT_SOURCE8 2315 * Register Name : INT_SOURCE8 2316 */ 2317 2318 /* 2319 * fsync_ibi_en 2320 * 0: FSYNC interrupt not routed to IBI 2321 * 1: FSYNC interrupt routed to IBI 2322 */ 2323 #define INT_SOURCE8_FSYNC_IBI_EN_POS 0x05 2324 #define INT_SOURCE8_FSYNC_IBI_EN_MASK (0x01 << INT_SOURCE8_FSYNC_IBI_EN_POS) 2325 2326 /* 2327 * pll_rdy_ibi_en 2328 * 0: PLL ready interrupt not routed to IBI 2329 * 1: PLL ready interrupt routed to IBI 2330 */ 2331 #define INT_SOURCE8_PLL_RDY_IBI_EN_POS 0x04 2332 #define INT_SOURCE8_PLL_RDY_IBI_EN_MASK (0x01 << INT_SOURCE8_PLL_RDY_IBI_EN_POS) 2333 2334 /* 2335 * ui_drdy_ibi_en 2336 * 0: UI data ready interrupt not routed to IBI 2337 * 1: UI data ready interrupt routed to IBI 2338 */ 2339 #define INT_SOURCE8_UI_DRDY_IBI_EN_POS 0x03 2340 #define INT_SOURCE8_UI_DRDY_IBI_EN_MASK (0x01 << INT_SOURCE8_UI_DRDY_IBI_EN_POS) 2341 2342 /* 2343 * fifo_ths_ibi_en 2344 * 0: FIFO threshold interrupt not routed to IBI 2345 * 1: FIFO threshold interrupt routed to IBI 2346 */ 2347 #define INT_SOURCE8_FIFO_THS_IBI_EN_POS 0x02 2348 #define INT_SOURCE8_FIFO_THS_IBI_EN_MASK (0x01 << INT_SOURCE8_FIFO_THS_IBI_EN_POS) 2349 2350 /* 2351 * fifo_full_ibi_en 2352 * 0: FIFO full interrupt not routed to IBI 2353 * 1: FIFO full interrupt routed to IBI 2354 */ 2355 #define INT_SOURCE8_FIFO_FULL_IBI_EN_POS 0x01 2356 #define INT_SOURCE8_FIFO_FULL_IBI_EN_MASK (0x01 << INT_SOURCE8_FIFO_FULL_IBI_EN_POS) 2357 2358 /* 2359 * agc_rdy_ibi_en 2360 * 0: AGC ready interrupt not routed to IBI 2361 * 1: AGC ready interrupt routed to IBI 2362 */ 2363 #define INT_SOURCE8_AGC_RDY_IBI_EN_POS 0x00 2364 #define INT_SOURCE8_AGC_RDY_IBI_EN_MASK 0x01 2365 2366 2367 2368 /* 2369 * INT_SOURCE9 2370 * Register Name : INT_SOURCE9 2371 */ 2372 2373 /* 2374 * i3c_protocol_error_ibi_en 2375 * 0: I3CSM protocol error interrupt not routed to IBI 2376 * 1: I3CSM protocol error interrupt routed to IBI 2377 */ 2378 #define INT_SOURCE9_I3C_PROTOCOL_ERROR_IBI_EN_POS 0x07 2379 #define INT_SOURCE9_I3C_PROTOCOL_ERROR_IBI_EN_MASK (0x01 << INT_SOURCE9_I3C_PROTOCOL_ERROR_IBI_EN_POS) 2380 2381 /* 2382 * ff_ibi_en 2383 * 0: Freefall interrupt not routed to IBI 2384 * 1: Freefall interrupt routed to IBI 2385 */ 2386 #define INT_SOURCE9_FF_IBI_EN_POS 0x06 2387 #define INT_SOURCE9_FF_IBI_EN_MASK (0x01 << INT_SOURCE9_FF_IBI_EN_POS) 2388 2389 /* 2390 * lowg_ibi_en 2391 * 0: Low-g interrupt not routed to IBI 2392 * 1: Low-g interrupt routed to IBI 2393 */ 2394 #define INT_SOURCE9_LOWG_IBI_EN_POS 0x05 2395 #define INT_SOURCE9_LOWG_IBI_EN_MASK (0x01 << INT_SOURCE9_LOWG_IBI_EN_POS) 2396 2397 /* 2398 * smd_ibi_en 2399 * 0: SMD interrupt not routed to IBI 2400 * 1: SMD interrupt routed to IBI 2401 */ 2402 #define INT_SOURCE9_SMD_IBI_EN_POS 0x04 2403 #define INT_SOURCE9_SMD_IBI_EN_MASK (0x01 << INT_SOURCE9_SMD_IBI_EN_POS) 2404 2405 /* 2406 * wom_z_ibi_en 2407 * 0: Z-axis WOM interrupt not routed to IBI 2408 * 1: Z-axis WOM interrupt routed to IBI 2409 */ 2410 #define INT_SOURCE9_WOM_Z_IBI_EN_POS 0x03 2411 #define INT_SOURCE9_WOM_Z_IBI_EN_MASK (0x01 << INT_SOURCE9_WOM_Z_IBI_EN_POS) 2412 2413 /* 2414 * wom_y_ibi_en 2415 * 0: Y-axis WOM interrupt not routed to IBI 2416 * 1: Y-axis WOM interrupt routed to IBI 2417 */ 2418 #define INT_SOURCE9_WOM_Y_IBI_EN_POS 0x02 2419 #define INT_SOURCE9_WOM_Y_IBI_EN_MASK (0x01 << INT_SOURCE9_WOM_Y_IBI_EN_POS) 2420 2421 /* 2422 * wom_x_ibi_en 2423 * 0: X-axis WOM interrupt not routed to IBI 2424 * 1: X-axis WOM interrupt routed to IBI 2425 */ 2426 #define INT_SOURCE9_WOM_X_IBI_EN_POS 0x01 2427 #define INT_SOURCE9_WOM_X_IBI_EN_MASK (0x01 << INT_SOURCE9_WOM_X_IBI_EN_POS) 2428 2429 /* 2430 * st_done_ibi_en 2431 * 0: Self-test done interrupt not routed to IBI 2432 * 1: Self-test done interrupt routed to IBI 2433 */ 2434 #define INT_SOURCE9_ST_DONE_IBI_EN_POS 0x00 2435 #define INT_SOURCE9_ST_DONE_IBI_EN_MASK 0x01 2436 2437 2438 2439 /* 2440 * INT_SOURCE10 2441 * Register Name : INT_SOURCE10 2442 */ 2443 2444 /* 2445 * step_det_ibi_en 2446 * 0: Step detect interrupt not routed to IBI 2447 * 1: Step detect interrupt routed to IBI 2448 */ 2449 #define INT_SOURCE10_STEP_DET_IBI_EN_POS 0x05 2450 #define INT_SOURCE10_STEP_DET_IBI_EN_MASK (0x01 << INT_SOURCE10_STEP_DET_IBI_EN_POS) 2451 2452 /* 2453 * step_cnt_ofl_ibi_en 2454 * 0: Step count overflow interrupt not routed to IBI 2455 * 1: Step count overflow interrupt routed to IBI 2456 */ 2457 #define INT_SOURCE10_STEP_CNT_OFL_IBI_EN_POS 0x04 2458 #define INT_SOURCE10_STEP_CNT_OFL_IBI_EN_MASK (0x01 << INT_SOURCE10_STEP_CNT_OFL_IBI_EN_POS) 2459 2460 /* 2461 * tilt_det_ibi_en 2462 * 0: Tilt detect interrupt not routed to IBI 2463 * 1: Tile detect interrupt routed to IBI 2464 */ 2465 #define INT_SOURCE10_TILT_DET_IBI_EN_POS 0x03 2466 #define INT_SOURCE10_TILT_DET_IBI_EN_MASK (0x01 << INT_SOURCE10_TILT_DET_IBI_EN_POS) 2467 2468 2469 2470 /* 2471 * APEX_CONFIG2 2472 * Register Name : APEX_CONFIG2 2473 */ 2474 2475 /* 2476 * low_energy_amp_th_sel 2477 * Threshold to select a valid step. Used to increase step detection for slow walk use case. 2478 * 2479 * 0000: 30 mg 2480 * 0001: 35 mg 2481 * 0010: 40 mg 2482 * 0011: 45 mg 2483 * 0100: 50 mg 2484 * 0101: 55 mg 2485 * 0110: 60 mg 2486 * 0111: 65 mg 2487 * 1000: 70 mg 2488 * 1001: 75 mg 2489 * 1010: 80 mg (default) 2490 * 1011: 85 mg 2491 * 1100: 90 mg 2492 * 1101: 95 mg 2493 * 1110: 100 mg 2494 * 1111: 105 mg 2495 */ 2496 #define APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS 0x04 2497 #define APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_MASK (0x0f << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS) 2498 2499 /* 2500 * dmp_power_save_time_sel 2501 * Duration of the period while the DMP stays awake after receiving a WOM event. 2502 * 2503 * 0000: 0 seconds 2504 * 0001: 4 seconds 2505 * 0010: 8 seconds (default) 2506 * 0011: 12 seconds 2507 * 0100: 16 seconds 2508 * 0101: 20 seconds 2509 * 0110: 24 seconds 2510 * 0111: 28 seconds 2511 * 1000: 32 seconds 2512 * 1001: 36 seconds 2513 * 1010: 40 seconds 2514 * 1011: 44 seconds 2515 * 1100: 48 seconds 2516 * 1101: 52 seconds 2517 * 1110: 56 seconds 2518 * 1111: 60 seconds 2519 */ 2520 #define APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_POS 0x00 2521 #define APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_MASK 0x0f 2522 2523 2524 2525 /* 2526 * APEX_CONFIG3 2527 * Register Name : APEX_CONFIG3 2528 */ 2529 2530 /* 2531 * ped_amp_th_sel 2532 * Threshold of step detection sensitivity. 2533 * 2534 * Low values increase detection sensitivity: reduce miss-detection. 2535 * High values reduce detection sensitivity: reduce false-positive. 2536 * 2537 * 0000: 30 mg 2538 * 0001: 34 mg 2539 * 0010: 38 mg 2540 * 0011: 42 mg 2541 * 0100: 46 mg 2542 * 0101: 50 mg 2543 * 0110: 54 mg 2544 * 0111: 58 mg 2545 * 1000: 62 mg (default) 2546 * 1001: 66 mg 2547 * 1010: 70 mg 2548 * 1011: 74 mg 2549 * 1100: 78 mg 2550 * 1101: 82 mg 2551 * 1110: 86 mg 2552 * 1111: 90 mg 2553 */ 2554 #define APEX_CONFIG3_PED_AMP_TH_SEL_POS 0x04 2555 #define APEX_CONFIG3_PED_AMP_TH_SEL_MASK (0x0f << APEX_CONFIG3_PED_AMP_TH_SEL_POS) 2556 2557 /* 2558 * ped_step_cnt_th_sel 2559 * Minimum number of steps that must be detected before step count is incremented. 2560 * 2561 * Low values reduce latency but increase false positives. 2562 * High values increase step count accuracy but increase latency. 2563 * 2564 * 0000: 0 steps 2565 * 0001: 1 step 2566 * 0010: 2 steps 2567 * 0011: 3 steps 2568 * 0100: 4 steps 2569 * 0101: 5 steps (default) 2570 * 0110: 6 steps 2571 * 0111: 7 steps 2572 * 1000: 8 steps 2573 * 1001: 9 steps 2574 * 1010: 10 steps 2575 * 1011: 11 steps 2576 * 1100: 12 steps 2577 * 1101: 13 steps 2578 * 1110: 14 steps 2579 * 1111: 15 steps 2580 */ 2581 #define APEX_CONFIG3_PED_STEP_CNT_TH_SEL_POS 0x00 2582 #define APEX_CONFIG3_PED_STEP_CNT_TH_SEL_MASK 0x0f 2583 2584 2585 2586 /* 2587 * APEX_CONFIG4 2588 * Register Name : APEX_CONFIG4 2589 */ 2590 2591 /* 2592 * ped_step_det_th_sel 2593 * Minimum number of steps that must be detected before step event is signaled. 2594 * 2595 * Low values reduce latency but increase false positives. 2596 * High values increase step event validity but increase latency. 2597 * 2598 * 000: 0 steps 2599 * 001: 1 step 2600 * 010: 2 steps (default) 2601 * 011: 3 steps 2602 * 100: 4 steps 2603 * 101: 5 steps 2604 * 110: 6 steps 2605 * 111: 7 steps 2606 */ 2607 #define APEX_CONFIG4_PED_STEP_DET_TH_SEL_POS 0x05 2608 #define APEX_CONFIG4_PED_STEP_DET_TH_SEL_MASK (0x07 << APEX_CONFIG4_PED_STEP_DET_TH_SEL_POS) 2609 2610 /* 2611 * ped_sb_timer_th_sel 2612 * Duration before algorithm considers that user has stopped taking steps. 2613 * 2614 * 000: 50 samples 2615 * 001: 75 sample 2616 * 010: 100 samples 2617 * 011: 125 samples 2618 * 100: 150 samples (default) 2619 * 101: 175 samples 2620 * 110: 200 samples 2621 * 111: 225 samples 2622 */ 2623 #define APEX_CONFIG4_PED_SB_TIMER_TH_SEL_POS 0x02 2624 #define APEX_CONFIG4_PED_SB_TIMER_TH_SEL_MASK (0x07 << APEX_CONFIG4_PED_SB_TIMER_TH_SEL_POS) 2625 2626 /* 2627 * ped_hi_en_th_sel 2628 * Threshold to classify acceleration signal as motion not due to steps. 2629 * 2630 * High values improve vibration rejection. 2631 * Low values improve detection. 2632 * 2633 * 00: 87.89 mg 2634 * 01: 104.49 mg (default) 2635 * 10: 132.81 mg 2636 * 11: 155.27 mg 2637 */ 2638 #define APEX_CONFIG4_PED_HI_EN_TH_SEL_POS 0x00 2639 #define APEX_CONFIG4_PED_HI_EN_TH_SEL_MASK 0x03 2640 2641 2642 2643 /* 2644 * APEX_CONFIG5 2645 * Register Name : APEX_CONFIG5 2646 */ 2647 2648 /* 2649 * tilt_wait_time_sel 2650 * Minimum duration for which the device should be tilted before signaling event. 2651 * 2652 * 00: 0s 2653 * 01: 2s 2654 * 10: 4s (default) 2655 * 11: 6s 2656 */ 2657 #define APEX_CONFIG5_TILT_WAIT_TIME_SEL_POS 0x06 2658 #define APEX_CONFIG5_TILT_WAIT_TIME_SEL_MASK (0x03 << APEX_CONFIG5_TILT_WAIT_TIME_SEL_POS) 2659 2660 /* 2661 * lowg_peak_th_hyst_sel 2662 * Hysteresis value added to the low-g threshold after exceeding it. 2663 * 2664 * 000: 31 mg (default) 2665 * 001: 63 mg 2666 * 010: 94 mg 2667 * 011: 125 mg 2668 * 100: 156 mg 2669 * 101: 188 mg 2670 * 110: 219 mg 2671 * 111: 250 mg 2672 */ 2673 #define APEX_CONFIG5_LOWG_PEAK_TH_HYST_SEL_POS 0x03 2674 #define APEX_CONFIG5_LOWG_PEAK_TH_HYST_SEL_MASK (0x07 << APEX_CONFIG5_LOWG_PEAK_TH_HYST_SEL_POS) 2675 2676 /* 2677 * highg_peak_th_hyst_sel 2678 * Hysteresis value subtracted from the high-g threshold after exceeding it. 2679 * 2680 * 000: 31 mg (default) 2681 * 001: 63 mg 2682 * 010: 94 mg 2683 * 011: 125 mg 2684 * 100: 156 mg 2685 * 101: 188 mg 2686 * 110: 219 mg 2687 * 111: 250 mg 2688 */ 2689 #define APEX_CONFIG5_HIGHG_PEAK_TH_HYST_SEL_POS 0x00 2690 #define APEX_CONFIG5_HIGHG_PEAK_TH_HYST_SEL_MASK 0x07 2691 2692 2693 2694 /* 2695 * APEX_CONFIG9 2696 * Register Name : APEX_CONFIG9 2697 */ 2698 2699 /* 2700 * ff_debounce_duration_sel 2701 * Period after a freefall is signaled during which a new freefall will not be detected. Prevents false detection due to bounces. 2702 * 2703 * 0000: 0 ms 2704 * 0001: 1250 ms 2705 * 0010: 1375 ms 2706 * 0011: 1500 ms 2707 * 0100: 1625 ms 2708 * 0101: 1750 ms 2709 * 0110: 1875 ms 2710 * 0111: 2000 ms 2711 * 1000: 2125 ms (default) 2712 * 1001: 2250 ms 2713 * 1010: 2375 ms 2714 * 1011: 2500 ms 2715 * 1100: 2625 ms 2716 * 1101: 2750 ms 2717 * 1110: 2875 ms 2718 * 1111: 3000 ms 2719 */ 2720 #define APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS 0x04 2721 #define APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_MASK (0x0f << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS) 2722 2723 /* 2724 * smd_sensitivity_sel 2725 * Parameter to tune SMD algorithm robustness to rejection, ranging from 0 to 4 (values higher than 4 are reserved). 2726 * 2727 * Low values increase detection rate but increase false positives. 2728 * High values reduce false positives but reduce detection rate (especially for transport use cases). 2729 * 2730 * Default value is 0. 2731 */ 2732 #define APEX_CONFIG9_SMD_SENSITIVITY_SEL_POS 0x01 2733 #define APEX_CONFIG9_SMD_SENSITIVITY_SEL_MASK (0x07 << APEX_CONFIG9_SMD_SENSITIVITY_SEL_POS) 2734 2735 /* 2736 * sensitivity_mode 2737 * Pedometer sensitivity mode 2738 * 0: Normal (default) 2739 * 1: Slow walk 2740 * 2741 * Slow walk mode improves slow walk detection (<1Hz) but the number of false positives may increase. 2742 */ 2743 #define APEX_CONFIG9_SENSITIVITY_MODE_POS 0x00 2744 #define APEX_CONFIG9_SENSITIVITY_MODE_MASK 0x01 2745 2746 2747 2748 /* 2749 * APEX_CONFIG10 2750 * Register Name : APEX_CONFIG10 2751 */ 2752 2753 /* 2754 * lowg_peak_th_sel 2755 * Threshold for accel values below which low-g state is detected. 2756 * 2757 * 00000: 31 mg (default) 2758 * 00001: 63 mg 2759 * 00010: 94 mg 2760 * 00011: 125 mg 2761 * 00100: 156 mg 2762 * 00101: 188 mg 2763 * 00110: 219 mg 2764 * 00111: 250 mg 2765 * 01000: 281 mg 2766 * 01001: 313 mg 2767 * 01010: 344 mg 2768 * 01011: 375 mg 2769 * 01100: 406 mg 2770 * 01101: 438 mg 2771 * 01110: 469 mg 2772 * 01111: 500 mg 2773 * 10000: 531 mg 2774 * 10001: 563 mg 2775 * 10010: 594 mg 2776 * 10011: 625 mg 2777 * 10100: 656 mg 2778 * 10101: 688 mg 2779 * 10110: 719 mg 2780 * 10111: 750 mg 2781 * 11000: 781 mg 2782 * 11001: 813 mg 2783 * 11010: 844 mg 2784 * 11011: 875 mg 2785 * 11100: 906 mg 2786 * 11101: 938 mg 2787 * 11110: 969 mg 2788 * 11111: 1000 mg 2789 */ 2790 #define APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS 0x03 2791 #define APEX_CONFIG10_LOWG_PEAK_TH_SEL_MASK (0x1f << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS) 2792 2793 /* 2794 * lowg_time_th_sel 2795 * Number of samples required to enter low-g state. 2796 * 2797 * 000: 1 sample (default) 2798 * 001: 2 samples 2799 * 010: 3 samples 2800 * 011: 4 samples 2801 * 100: 5 samples 2802 * 101: 6 samples 2803 * 110: 7 samples 2804 * 111: 8 samples 2805 */ 2806 #define APEX_CONFIG10_LOWG_TIME_TH_SEL_POS 0x00 2807 #define APEX_CONFIG10_LOWG_TIME_TH_SEL_MASK 0x07 2808 2809 2810 2811 /* 2812 * APEX_CONFIG11 2813 * Register Name : APEX_CONFIG11 2814 */ 2815 2816 /* 2817 * highg_peak_th_sel 2818 * Threshold for accel values above which high-g state is detected. 2819 * 2820 * 00000: 250 mg (default) 2821 * 00001: 500 mg 2822 * 00010: 750 mg 2823 * 00011: 1000 mg 2824 * 00100: 1250 mg 2825 * 00101: 1500 mg 2826 * 00110: 1750 mg 2827 * 00111: 2000 mg 2828 * 01000: 2250 mg 2829 * 01001: 2500 mg 2830 * 01010: 2750 mg 2831 * 01011: 3000 mg 2832 * 01100: 3250 mg 2833 * 01101: 3500 mg 2834 * 01110: 3750 mg 2835 * 01111: 4000 mg 2836 * 10000: 4250 mg 2837 * 10001: 4500 mg 2838 * 10010: 4750 mg 2839 * 10011: 5000 mg 2840 * 10100: 5250 mg 2841 * 10101: 5500 mg 2842 * 10110: 5750 mg 2843 * 10111: 6000 mg 2844 * 11000: 6250 mg 2845 * 11001: 6500 mg 2846 * 11010: 6750 mg 2847 * 11011: 7000 mg 2848 * 11100: 7250 mg 2849 * 11101: 7500 mg 2850 * 11110: 7750 mg 2851 * 11111: 8000 mg 2852 */ 2853 #define APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS 0x03 2854 #define APEX_CONFIG11_HIGHG_PEAK_TH_SEL_MASK (0x1f << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS) 2855 2856 /* 2857 * highg_time_th_sel 2858 * Number of samples required to enter high-g state. 2859 * 2860 * 000: 1 sample (default) 2861 * 001: 2 samples 2862 * 010: 3 samples 2863 * 011: 4 samples 2864 * 100: 5 samples 2865 * 101: 6 samples 2866 * 110: 7 samples 2867 * 111: 8 samples 2868 */ 2869 #define APEX_CONFIG11_HIGHG_TIME_TH_SEL_POS 0x00 2870 #define APEX_CONFIG11_HIGHG_TIME_TH_SEL_MASK 0x07 2871 2872 2873 2874 /* 2875 * ACCEL_WOM_X_THR 2876 * Register Name : ACCEL_WOM_X_THR 2877 */ 2878 2879 /* 2880 * wom_x_th 2881 * Threshold value for the Wake on Motion Interrupt for X-axis accelerometer 2882 * WoM thresholds are expressed in fixed “mg” independent of the selected Range [0g : 1g]; Resolution 1g/256=~3.9mg 2883 */ 2884 #define ACCEL_WOM_X_THR_WOM_X_TH_POS 0x00 2885 #define ACCEL_WOM_X_THR_WOM_X_TH_MASK 0xff 2886 2887 2888 2889 /* 2890 * ACCEL_WOM_Y_THR 2891 * Register Name : ACCEL_WOM_Y_THR 2892 */ 2893 2894 /* 2895 * wom_y_th 2896 * Threshold value for the Wake on Motion Interrupt for Y-axis accelerometer 2897 * WoM thresholds are expressed in fixed “mg” independent of the selected Range [0g : 1g]; Resolution 1g/256=~3.9mg 2898 */ 2899 #define ACCEL_WOM_Y_THR_WOM_Y_TH_POS 0x00 2900 #define ACCEL_WOM_Y_THR_WOM_Y_TH_MASK 0xff 2901 2902 2903 2904 /* 2905 * ACCEL_WOM_Z_THR 2906 * Register Name : ACCEL_WOM_Z_THR 2907 */ 2908 2909 /* 2910 * wom_z_th 2911 * Threshold value for the Wake on Motion Interrupt for Z-axis accelerometer 2912 * WoM thresholds are expressed in fixed “mg” independent of the selected Range [0g : 1g]; Resolution 1g/256=~3.9mg 2913 */ 2914 #define ACCEL_WOM_Z_THR_WOM_Z_TH_POS 0x00 2915 #define ACCEL_WOM_Z_THR_WOM_Z_TH_MASK 0xff 2916 2917 2918 2919 /* 2920 * OFFSET_USER0 2921 * Register Name : OFFSET_USER0 2922 */ 2923 2924 /* 2925 * gyro_x_offuser 2926 * Gyro offset programmed by user. Max value is +/-64 dps, resolution is 1/32 dps 2927 */ 2928 #define OFFSET_USER0_GYRO_X_OFFUSER_POS 0x00 2929 #define OFFSET_USER0_GYRO_X_OFFUSER_MASK 0xff 2930 2931 2932 2933 /* 2934 * OFFSET_USER1 2935 * Register Name : OFFSET_USER1 2936 */ 2937 2938 /* 2939 * gyro_x_offuser 2940 * Gyro offset programmed by user. Max value is +/-64 dps, resolution is 1/32 dps 2941 */ 2942 #define OFFSET_USER1_GYRO_X_OFFUSER_POS 0x00 2943 #define OFFSET_USER1_GYRO_X_OFFUSER_MASK 0x0f 2944 2945 /* 2946 * gyro_y_offuser 2947 * Gyro offset programmed by user. Max value is +/-64 dps, resolution is 1/32 dps 2948 */ 2949 #define OFFSET_USER1_GYRO_Y_OFFUSER_POS 0x04 2950 #define OFFSET_USER1_GYRO_Y_OFFUSER_MASK (0x0f << OFFSET_USER1_GYRO_Y_OFFUSER_POS) 2951 2952 2953 2954 /* 2955 * OFFSET_USER2 2956 * Register Name : OFFSET_USER2 2957 */ 2958 2959 /* 2960 * gyro_y_offuser 2961 * Gyro offset programmed by user. Max value is +/-64 dps, resolution is 1/32 dps 2962 */ 2963 #define OFFSET_USER2_GYRO_Y_OFFUSER_POS 0x00 2964 #define OFFSET_USER2_GYRO_Y_OFFUSER_MASK 0xff 2965 2966 2967 2968 /* 2969 * OFFSET_USER3 2970 * Register Name : OFFSET_USER3 2971 */ 2972 2973 /* 2974 * gyro_z_offuser 2975 * Gyro offset programmed by user. Max value is +/-64 dps, resolution is 1/32 dps 2976 */ 2977 #define OFFSET_USER3_GYRO_Z_OFFUSER_POS 0x00 2978 #define OFFSET_USER3_GYRO_Z_OFFUSER_MASK 0xff 2979 2980 2981 2982 /* 2983 * OFFSET_USER4 2984 * Register Name : OFFSET_USER4 2985 */ 2986 2987 /* 2988 * gyro_z_offuser 2989 * Gyro offset programmed by user. Max value is +/-64 dps, resolution is 1/32 dps 2990 */ 2991 #define OFFSET_USER4_GYRO_Z_OFFUSER_POS 0x00 2992 #define OFFSET_USER4_GYRO_Z_OFFUSER_MASK 0x0f 2993 2994 /* 2995 * accel_x_offuser 2996 * Accel offset programmed by user. Max value is +/-1 gee, resolution is 0.5 mgee 2997 */ 2998 #define OFFSET_USER4_ACCEL_X_OFFUSER_POS 0x04 2999 #define OFFSET_USER4_ACCEL_X_OFFUSER_MASK (0x0f << OFFSET_USER4_ACCEL_X_OFFUSER_POS) 3000 3001 3002 3003 /* 3004 * OFFSET_USER5 3005 * Register Name : OFFSET_USER5 3006 */ 3007 3008 /* 3009 * accel_x_offuser 3010 * Accel offset programmed by user. Max value is +/-1 gee, resolution is 0.5 mgee 3011 */ 3012 #define OFFSET_USER5_ACCEL_X_OFFUSER_POS 0x00 3013 #define OFFSET_USER5_ACCEL_X_OFFUSER_MASK 0xff 3014 3015 3016 3017 /* 3018 * OFFSET_USER6 3019 * Register Name : OFFSET_USER6 3020 */ 3021 3022 /* 3023 * accel_y_offuser 3024 * Accel offset programmed by user. Max value is +/-1 gee, resolution is 0.5 mgee 3025 */ 3026 #define OFFSET_USER6_ACCEL_Y_OFFUSER_POS 0x00 3027 #define OFFSET_USER6_ACCEL_Y_OFFUSER_MASK 0xff 3028 3029 3030 3031 /* 3032 * OFFSET_USER7 3033 * Register Name : OFFSET_USER7 3034 */ 3035 3036 /* 3037 * accel_y_offuser 3038 * Accel offset programmed by user. Max value is +/-1 gee, resolution is 0.5 mgee 3039 */ 3040 #define OFFSET_USER7_ACCEL_Y_OFFUSER_POS 0x00 3041 #define OFFSET_USER7_ACCEL_Y_OFFUSER_MASK 0x0f 3042 3043 /* 3044 * accel_z_offuser 3045 * Accel offset programmed by user. Max value is +/-1 gee, resolution is 0.5 mgee 3046 */ 3047 #define OFFSET_USER7_ACCEL_Z_OFFUSER_POS 0x04 3048 #define OFFSET_USER7_ACCEL_Z_OFFUSER_MASK (0x0f << OFFSET_USER7_ACCEL_Z_OFFUSER_POS) 3049 3050 3051 3052 /* 3053 * OFFSET_USER8 3054 * Register Name : OFFSET_USER8 3055 */ 3056 3057 /* 3058 * accel_z_offuser 3059 * Accel offset programmed by user. Max value is +/-1 gee, resolution is 0.5 mgee 3060 */ 3061 #define OFFSET_USER8_ACCEL_Z_OFFUSER_POS 0x00 3062 #define OFFSET_USER8_ACCEL_Z_OFFUSER_MASK 0xff 3063 3064 3065 3066 /* 3067 * ST_STATUS1 3068 * Register Name : ST_STATUS1 3069 */ 3070 3071 /* 3072 * accel_st_pass 3073 * 1: Accel self-test passed for all the 3 axes 3074 */ 3075 #define ST_STATUS1_ACCEL_ST_PASS_POS 0x05 3076 #define ST_STATUS1_ACCEL_ST_PASS_MASK (0x01 << ST_STATUS1_ACCEL_ST_PASS_POS) 3077 3078 /* 3079 * accel_st_done 3080 * 1: Accel self-test done for all the 3 axes 3081 */ 3082 #define ST_STATUS1_ACCEL_ST_DONE_POS 0x04 3083 #define ST_STATUS1_ACCEL_ST_DONE_MASK (0x01 << ST_STATUS1_ACCEL_ST_DONE_POS) 3084 3085 /* 3086 * az_st_pass 3087 * 1: Accel Z-axis self-test passed 3088 */ 3089 #define ST_STATUS1_AZ_ST_PASS_POS 0x03 3090 #define ST_STATUS1_AZ_ST_PASS_MASK (0x01 << ST_STATUS1_AZ_ST_PASS_POS) 3091 3092 /* 3093 * ay_st_pass 3094 * 1: Accel Y-axis self-test passed 3095 */ 3096 #define ST_STATUS1_AY_ST_PASS_POS 0x02 3097 #define ST_STATUS1_AY_ST_PASS_MASK (0x01 << ST_STATUS1_AY_ST_PASS_POS) 3098 3099 /* 3100 * ax_st_pass 3101 * 1: Accel X-axis self-test passed 3102 */ 3103 #define ST_STATUS1_AX_ST_PASS_POS 0x01 3104 #define ST_STATUS1_AX_ST_PASS_MASK (0x01 << ST_STATUS1_AX_ST_PASS_POS) 3105 3106 3107 3108 /* 3109 * ST_STATUS2 3110 * Register Name : ST_STATUS2 3111 */ 3112 3113 /* 3114 * st_incomplete 3115 * 1: Self-test is incomplete. 3116 * This bit is set to 1 if the self-test was aborted. 3117 * One possible cause of aborting the self-test may be the detection of significant movement in the gyro when the self-test for gyro and/or accel is being executed. 3118 */ 3119 #define ST_STATUS2_ST_INCOMPLETE_POS 0x06 3120 #define ST_STATUS2_ST_INCOMPLETE_MASK (0x01 << ST_STATUS2_ST_INCOMPLETE_POS) 3121 3122 /* 3123 * gyro_st_pass 3124 * 1: Gyro self-test passed for all the 3 axes 3125 */ 3126 #define ST_STATUS2_GYRO_ST_PASS_POS 0x05 3127 #define ST_STATUS2_GYRO_ST_PASS_MASK (0x01 << ST_STATUS2_GYRO_ST_PASS_POS) 3128 3129 /* 3130 * gyro_st_done 3131 * 1: Gyro self-test done for all the 3 axes 3132 */ 3133 #define ST_STATUS2_GYRO_ST_DONE_POS 0x04 3134 #define ST_STATUS2_GYRO_ST_DONE_MASK (0x01 << ST_STATUS2_GYRO_ST_DONE_POS) 3135 3136 /* 3137 * gz_st_pass 3138 * 1: Gyro Z-axis self-test passed 3139 */ 3140 #define ST_STATUS2_GZ_ST_PASS_POS 0x03 3141 #define ST_STATUS2_GZ_ST_PASS_MASK (0x01 << ST_STATUS2_GZ_ST_PASS_POS) 3142 3143 /* 3144 * gy_st_pass 3145 * 1: Gyro Y-axis self-test passed 3146 */ 3147 #define ST_STATUS2_GY_ST_PASS_POS 0x02 3148 #define ST_STATUS2_GY_ST_PASS_MASK (0x01 << ST_STATUS2_GY_ST_PASS_POS) 3149 3150 /* 3151 * gx_st_pass 3152 * 1: Gyro X-axis self-test passed 3153 */ 3154 #define ST_STATUS2_GX_ST_PASS_POS 0x01 3155 #define ST_STATUS2_GX_ST_PASS_MASK (0x01 << ST_STATUS2_GX_ST_PASS_POS) 3156 3157 3158 3159 /* 3160 * FDR_CONFIG 3161 * Register Name : FDR_CONFIG 3162 */ 3163 3164 /* 3165 * fdr_sel 3166 * [7:4] Reserved 3167 * [3:0] FIFO packet rate decimation factor. Sets the number of discarded FIFO packets. Valid range is 0 to 127. User must disable sensors when initializing FDR_SEL value or making changes to it. 3168 * 3169 * 0xxx: Decimation is disabled, all packets are sent to FIFO 3170 * 1000: 1 packet out of 2 is sent to FIFO 3171 * 1001: 1 packet out of 4 is sent to FIFO 3172 * 1010: 1 packet out of 8 is sent to FIFO 3173 * 1011: 1 packet out of 16 is sent to FIFO 3174 * 1100: 1 packet out of 32 is sent to FIFO 3175 * 1101: 1 packet out of 64 is sent to FIFO 3176 * 1110: 1 packet out of 128 is sent to FIFO 3177 * 1111: 1 packet out of 256 is sent to FIFO 3178 */ 3179 #define FDR_CONFIG_FDR_SEL_POS 0x00 3180 #define FDR_CONFIG_FDR_SEL_MASK 0xff 3181 3182 3183 3184 /* 3185 * APEX_CONFIG12 3186 * Register Name : APEX_CONFIG12 3187 */ 3188 3189 /* 3190 * ff_max_duration_sel 3191 * Maximum freefall length. Longer freefalls are ignored. 3192 * 3193 * 0000: 102 cm (default) 3194 * 0001: 120 cm 3195 * 0010: 139 cm 3196 * 0011: 159 cm 3197 * 0100: 181 cm 3198 * 0101: 204 cm 3199 * 0110: 228 cm 3200 * 0111: 254 cm 3201 * 1000: 281 cm 3202 * 1001: 310 cm 3203 * 1010: 339 cm 3204 * 1011: 371 cm 3205 * 1100: 403 cm 3206 * 1101: 438 cm 3207 * 1110: 473 cm 3208 * 1111: 510 cm 3209 */ 3210 #define APEX_CONFIG12_FF_MAX_DURATION_SEL_POS 0x04 3211 #define APEX_CONFIG12_FF_MAX_DURATION_SEL_MASK (0x0f << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS) 3212 3213 /* 3214 * ff_min_duration_sel 3215 * Minimum freefall length. Shorter freefalls are ignored. 3216 * 3217 * 0000: 10 cm (default) 3218 * 0001: 12 cm 3219 * 0010: 13 cm 3220 * 0011: 16 cm 3221 * 0100: 18 cm 3222 * 0101: 20 cm 3223 * 0110: 23 cm 3224 * 0111: 25 cm 3225 * 1000: 28 cm 3226 * 1001: 31 cm 3227 * 1010: 34 cm 3228 * 1011: 38 cm 3229 * 1100: 41 cm 3230 * 1101: 45 cm 3231 * 1110: 48 cm 3232 * 1111: 52 cm 3233 */ 3234 #define APEX_CONFIG12_FF_MIN_DURATION_SEL_POS 0x00 3235 #define APEX_CONFIG12_FF_MIN_DURATION_SEL_MASK 0x0f 3236 3237 3238 /* --------------------------------------------------------------------------- 3239 * register MREG3 3240 * ---------------------------------------------------------------------------*/ 3241 3242 /* 3243 * XA_ST_DATA 3244 * Register Name : XA_ST_DATA 3245 */ 3246 3247 /* 3248 * xa_st_data 3249 * Accel X-axis self test data converted to 8 bit code. 3250 */ 3251 #define XA_ST_DATA_XA_ST_DATA_POS 0x00 3252 #define XA_ST_DATA_XA_ST_DATA_MASK 0xff 3253 3254 3255 3256 /* 3257 * YA_ST_DATA 3258 * Register Name : YA_ST_DATA 3259 */ 3260 3261 /* 3262 * ya_st_data 3263 * Accel Y-axis self test data converted to 8 bit code. 3264 */ 3265 #define YA_ST_DATA_YA_ST_DATA_POS 0x00 3266 #define YA_ST_DATA_YA_ST_DATA_MASK 0xff 3267 3268 3269 3270 /* 3271 * ZA_ST_DATA 3272 * Register Name : ZA_ST_DATA 3273 */ 3274 3275 /* 3276 * za_st_data 3277 * Accel Z-axis self test data converted to 8 bit code. 3278 */ 3279 #define ZA_ST_DATA_ZA_ST_DATA_POS 0x00 3280 #define ZA_ST_DATA_ZA_ST_DATA_MASK 0xff 3281 3282 3283 3284 /* 3285 * XG_ST_DATA 3286 * Register Name : XG_ST_DATA 3287 */ 3288 3289 /* 3290 * xg_st_data 3291 * Gyro X-axis self test data converted to 8 bit code. 3292 */ 3293 #define XG_ST_DATA_XG_ST_DATA_POS 0x00 3294 #define XG_ST_DATA_XG_ST_DATA_MASK 0xff 3295 3296 3297 3298 /* 3299 * YG_ST_DATA 3300 * Register Name : YG_ST_DATA 3301 */ 3302 3303 /* 3304 * yg_st_data 3305 * Gyro Y-axis self test data converted to 8 bit code. 3306 */ 3307 #define YG_ST_DATA_YG_ST_DATA_POS 0x00 3308 #define YG_ST_DATA_YG_ST_DATA_MASK 0xff 3309 3310 3311 3312 /* 3313 * ZG_ST_DATA 3314 * Register Name : ZG_ST_DATA 3315 */ 3316 3317 /* 3318 * zg_st_data 3319 * Gyro Z-axis self test data converted to 8 bit code. 3320 */ 3321 #define ZG_ST_DATA_ZG_ST_DATA_POS 0x00 3322 #define ZG_ST_DATA_ZG_ST_DATA_MASK 0xff 3323 3324 3325 /* --------------------------------------------------------------------------- 3326 * register MREG2 3327 * ---------------------------------------------------------------------------*/ 3328 3329 /* 3330 * OTP_CTRL7 3331 * Register Name : OTP_CTRL7 3332 */ 3333 3334 /* 3335 * otp_reload 3336 * 1: to trigger OTP copy operation. This bit is cleared to 0 after OTP copy is done. 3337 * 3338 * With otp_copy_mode[1:0] = 2'b01, it takes 280us to complete the OTP reloading operation. 3339 * With otp_copy_mode[1:0] = 2'b11, it takes 20us to complete the OTP reloading operation. 3340 */ 3341 #define OTP_CTRL7_OTP_RELOAD_POS 0x03 3342 #define OTP_CTRL7_OTP_RELOAD_MASK (0x01 << OTP_CTRL7_OTP_RELOAD_POS) 3343 3344 /* 3345 * otp_pwr_down 3346 * 0: Power up OTP to copy from OTP to SRAM 3347 * 1: Power down OTP 3348 * 3349 * This bit is automatically set to 1 when OTP copy operation is complete. 3350 */ 3351 #define OTP_CTRL7_OTP_PWR_DOWN_POS 0x01 3352 #define OTP_CTRL7_OTP_PWR_DOWN_MASK (0x01 << OTP_CTRL7_OTP_PWR_DOWN_POS) 3353 3354 #ifdef __cplusplus 3355 } 3356 #endif 3357 3358 #endif /*#ifndef _INV_IMU_REGMAP_REV_A_H_*/
