1 /** 2 * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "soc/soc.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 /** APB_SARADC_CTRL_REG register 15 * register description 16 */ 17 #define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x0) 18 /** APB_SARADC_START_FORCE : R/W; bitpos: [0]; default: 0; 19 * Need add description 20 */ 21 #define APB_SARADC_START_FORCE (BIT(0)) 22 #define APB_SARADC_START_FORCE_M (APB_SARADC_START_FORCE_V << APB_SARADC_START_FORCE_S) 23 #define APB_SARADC_START_FORCE_V 0x00000001U 24 #define APB_SARADC_START_FORCE_S 0 25 /** APB_SARADC_START : R/W; bitpos: [1]; default: 0; 26 * Need add description 27 */ 28 #define APB_SARADC_START (BIT(1)) 29 #define APB_SARADC_START_M (APB_SARADC_START_V << APB_SARADC_START_S) 30 #define APB_SARADC_START_V 0x00000001U 31 #define APB_SARADC_START_S 1 32 /** APB_SARADC_SAR_CLK_GATED : R/W; bitpos: [6]; default: 1; 33 * Need add description 34 */ 35 #define APB_SARADC_SAR_CLK_GATED (BIT(6)) 36 #define APB_SARADC_SAR_CLK_GATED_M (APB_SARADC_SAR_CLK_GATED_V << APB_SARADC_SAR_CLK_GATED_S) 37 #define APB_SARADC_SAR_CLK_GATED_V 0x00000001U 38 #define APB_SARADC_SAR_CLK_GATED_S 6 39 /** APB_SARADC_SAR_CLK_DIV : R/W; bitpos: [14:7]; default: 4; 40 * SAR clock divider 41 */ 42 #define APB_SARADC_SAR_CLK_DIV 0x000000FFU 43 #define APB_SARADC_SAR_CLK_DIV_M (APB_SARADC_SAR_CLK_DIV_V << APB_SARADC_SAR_CLK_DIV_S) 44 #define APB_SARADC_SAR_CLK_DIV_V 0x000000FFU 45 #define APB_SARADC_SAR_CLK_DIV_S 7 46 /** APB_SARADC_SAR_PATT_LEN : R/W; bitpos: [17:15]; default: 7; 47 * 0 ~ 15 means length 1 ~ 16 48 */ 49 #define APB_SARADC_SAR_PATT_LEN 0x00000007U 50 #define APB_SARADC_SAR_PATT_LEN_M (APB_SARADC_SAR_PATT_LEN_V << APB_SARADC_SAR_PATT_LEN_S) 51 #define APB_SARADC_SAR_PATT_LEN_V 0x00000007U 52 #define APB_SARADC_SAR_PATT_LEN_S 15 53 /** APB_SARADC_SAR_PATT_P_CLEAR : R/W; bitpos: [23]; default: 0; 54 * clear the pointer of pattern table for DIG ADC1 CTRL 55 */ 56 #define APB_SARADC_SAR_PATT_P_CLEAR (BIT(23)) 57 #define APB_SARADC_SAR_PATT_P_CLEAR_M (APB_SARADC_SAR_PATT_P_CLEAR_V << APB_SARADC_SAR_PATT_P_CLEAR_S) 58 #define APB_SARADC_SAR_PATT_P_CLEAR_V 0x00000001U 59 #define APB_SARADC_SAR_PATT_P_CLEAR_S 23 60 /** APB_SARADC_XPD_SAR_FORCE : R/W; bitpos: [28:27]; default: 0; 61 * force option to xpd sar blocks 62 */ 63 #define APB_SARADC_XPD_SAR_FORCE 0x00000003U 64 #define APB_SARADC_XPD_SAR_FORCE_M (APB_SARADC_XPD_SAR_FORCE_V << APB_SARADC_XPD_SAR_FORCE_S) 65 #define APB_SARADC_XPD_SAR_FORCE_V 0x00000003U 66 #define APB_SARADC_XPD_SAR_FORCE_S 27 67 /** APB_SARADC_WAIT_ARB_CYCLE : R/W; bitpos: [31:30]; default: 1; 68 * wait arbit signal stable after sar_done 69 */ 70 #define APB_SARADC_WAIT_ARB_CYCLE 0x00000003U 71 #define APB_SARADC_WAIT_ARB_CYCLE_M (APB_SARADC_WAIT_ARB_CYCLE_V << APB_SARADC_WAIT_ARB_CYCLE_S) 72 #define APB_SARADC_WAIT_ARB_CYCLE_V 0x00000003U 73 #define APB_SARADC_WAIT_ARB_CYCLE_S 30 74 75 /** APB_SARADC_CTRL2_REG register 76 * register description 77 */ 78 #define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x4) 79 /** APB_SARADC_MEAS_NUM_LIMIT : R/W; bitpos: [0]; default: 0; 80 * Need add description 81 */ 82 #define APB_SARADC_MEAS_NUM_LIMIT (BIT(0)) 83 #define APB_SARADC_MEAS_NUM_LIMIT_M (APB_SARADC_MEAS_NUM_LIMIT_V << APB_SARADC_MEAS_NUM_LIMIT_S) 84 #define APB_SARADC_MEAS_NUM_LIMIT_V 0x00000001U 85 #define APB_SARADC_MEAS_NUM_LIMIT_S 0 86 /** APB_SARADC_MAX_MEAS_NUM : R/W; bitpos: [8:1]; default: 255; 87 * max conversion number 88 */ 89 #define APB_SARADC_MAX_MEAS_NUM 0x000000FFU 90 #define APB_SARADC_MAX_MEAS_NUM_M (APB_SARADC_MAX_MEAS_NUM_V << APB_SARADC_MAX_MEAS_NUM_S) 91 #define APB_SARADC_MAX_MEAS_NUM_V 0x000000FFU 92 #define APB_SARADC_MAX_MEAS_NUM_S 1 93 /** APB_SARADC_SAR1_INV : R/W; bitpos: [9]; default: 0; 94 * 1: data to DIG ADC1 CTRL is inverted, otherwise not 95 */ 96 #define APB_SARADC_SAR1_INV (BIT(9)) 97 #define APB_SARADC_SAR1_INV_M (APB_SARADC_SAR1_INV_V << APB_SARADC_SAR1_INV_S) 98 #define APB_SARADC_SAR1_INV_V 0x00000001U 99 #define APB_SARADC_SAR1_INV_S 9 100 /** APB_SARADC_SAR2_INV : R/W; bitpos: [10]; default: 0; 101 * 1: data to DIG ADC2 CTRL is inverted, otherwise not 102 */ 103 #define APB_SARADC_SAR2_INV (BIT(10)) 104 #define APB_SARADC_SAR2_INV_M (APB_SARADC_SAR2_INV_V << APB_SARADC_SAR2_INV_S) 105 #define APB_SARADC_SAR2_INV_V 0x00000001U 106 #define APB_SARADC_SAR2_INV_S 10 107 /** APB_SARADC_TIMER_TARGET : R/W; bitpos: [23:12]; default: 10; 108 * to set saradc timer target 109 */ 110 #define APB_SARADC_TIMER_TARGET 0x00000FFFU 111 #define APB_SARADC_TIMER_TARGET_M (APB_SARADC_TIMER_TARGET_V << APB_SARADC_TIMER_TARGET_S) 112 #define APB_SARADC_TIMER_TARGET_V 0x00000FFFU 113 #define APB_SARADC_TIMER_TARGET_S 12 114 /** APB_SARADC_TIMER_EN : R/W; bitpos: [24]; default: 0; 115 * to enable saradc timer trigger 116 */ 117 #define APB_SARADC_TIMER_EN (BIT(24)) 118 #define APB_SARADC_TIMER_EN_M (APB_SARADC_TIMER_EN_V << APB_SARADC_TIMER_EN_S) 119 #define APB_SARADC_TIMER_EN_V 0x00000001U 120 #define APB_SARADC_TIMER_EN_S 24 121 122 /** APB_SARADC_FILTER_CTRL1_REG register 123 * register description 124 */ 125 #define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x8) 126 /** APB_SARADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0; 127 * Need add description 128 */ 129 #define APB_SARADC_FILTER_FACTOR1 0x00000007U 130 #define APB_SARADC_FILTER_FACTOR1_M (APB_SARADC_FILTER_FACTOR1_V << APB_SARADC_FILTER_FACTOR1_S) 131 #define APB_SARADC_FILTER_FACTOR1_V 0x00000007U 132 #define APB_SARADC_FILTER_FACTOR1_S 26 133 /** APB_SARADC_FILTER_FACTOR0 : R/W; bitpos: [31:29]; default: 0; 134 * Need add description 135 */ 136 #define APB_SARADC_FILTER_FACTOR0 0x00000007U 137 #define APB_SARADC_FILTER_FACTOR0_M (APB_SARADC_FILTER_FACTOR0_V << APB_SARADC_FILTER_FACTOR0_S) 138 #define APB_SARADC_FILTER_FACTOR0_V 0x00000007U 139 #define APB_SARADC_FILTER_FACTOR0_S 29 140 141 /** APB_SARADC_FSM_WAIT_REG register 142 * register description 143 */ 144 #define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0xc) 145 /** APB_SARADC_XPD_WAIT : R/W; bitpos: [7:0]; default: 8; 146 * Need add description 147 */ 148 #define APB_SARADC_XPD_WAIT 0x000000FFU 149 #define APB_SARADC_XPD_WAIT_M (APB_SARADC_XPD_WAIT_V << APB_SARADC_XPD_WAIT_S) 150 #define APB_SARADC_XPD_WAIT_V 0x000000FFU 151 #define APB_SARADC_XPD_WAIT_S 0 152 /** APB_SARADC_RSTB_WAIT : R/W; bitpos: [15:8]; default: 8; 153 * Need add description 154 */ 155 #define APB_SARADC_RSTB_WAIT 0x000000FFU 156 #define APB_SARADC_RSTB_WAIT_M (APB_SARADC_RSTB_WAIT_V << APB_SARADC_RSTB_WAIT_S) 157 #define APB_SARADC_RSTB_WAIT_V 0x000000FFU 158 #define APB_SARADC_RSTB_WAIT_S 8 159 /** APB_SARADC_STANDBY_WAIT : R/W; bitpos: [23:16]; default: 255; 160 * Need add description 161 */ 162 #define APB_SARADC_STANDBY_WAIT 0x000000FFU 163 #define APB_SARADC_STANDBY_WAIT_M (APB_SARADC_STANDBY_WAIT_V << APB_SARADC_STANDBY_WAIT_S) 164 #define APB_SARADC_STANDBY_WAIT_V 0x000000FFU 165 #define APB_SARADC_STANDBY_WAIT_S 16 166 167 /** APB_SARADC_SAR1_STATUS_REG register 168 * register description 169 */ 170 #define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x10) 171 /** APB_SARADC_SAR1_STATUS : RO; bitpos: [31:0]; default: 0; 172 * Need add description 173 */ 174 #define APB_SARADC_SAR1_STATUS 0xFFFFFFFFU 175 #define APB_SARADC_SAR1_STATUS_M (APB_SARADC_SAR1_STATUS_V << APB_SARADC_SAR1_STATUS_S) 176 #define APB_SARADC_SAR1_STATUS_V 0xFFFFFFFFU 177 #define APB_SARADC_SAR1_STATUS_S 0 178 179 /** APB_SARADC_SAR2_STATUS_REG register 180 * register description 181 */ 182 #define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x14) 183 /** APB_SARADC_SAR2_STATUS : RO; bitpos: [31:0]; default: 0; 184 * Need add description 185 */ 186 #define APB_SARADC_SAR2_STATUS 0xFFFFFFFFU 187 #define APB_SARADC_SAR2_STATUS_M (APB_SARADC_SAR2_STATUS_V << APB_SARADC_SAR2_STATUS_S) 188 #define APB_SARADC_SAR2_STATUS_V 0xFFFFFFFFU 189 #define APB_SARADC_SAR2_STATUS_S 0 190 191 /** APB_SARADC_SAR_PATT_TAB1_REG register 192 * register description 193 */ 194 #define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x18) 195 /** APB_SARADC_SAR_PATT_TAB1 : R/W; bitpos: [23:0]; default: 16777215; 196 * item 0 ~ 3 for pattern table 1 (each item one byte) 197 */ 198 #define APB_SARADC_SAR_PATT_TAB1 0x00FFFFFFU 199 #define APB_SARADC_SAR_PATT_TAB1_M (APB_SARADC_SAR_PATT_TAB1_V << APB_SARADC_SAR_PATT_TAB1_S) 200 #define APB_SARADC_SAR_PATT_TAB1_V 0x00FFFFFFU 201 #define APB_SARADC_SAR_PATT_TAB1_S 0 202 203 /** APB_SARADC_SAR_PATT_TAB2_REG register 204 * register description 205 */ 206 #define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x1c) 207 /** APB_SARADC_SAR_PATT_TAB2 : R/W; bitpos: [23:0]; default: 16777215; 208 * Item 4 ~ 7 for pattern table 1 (each item one byte) 209 */ 210 #define APB_SARADC_SAR_PATT_TAB2 0x00FFFFFFU 211 #define APB_SARADC_SAR_PATT_TAB2_M (APB_SARADC_SAR_PATT_TAB2_V << APB_SARADC_SAR_PATT_TAB2_S) 212 #define APB_SARADC_SAR_PATT_TAB2_V 0x00FFFFFFU 213 #define APB_SARADC_SAR_PATT_TAB2_S 0 214 215 /** APB_SARADC_ONETIME_SAMPLE_REG register 216 * register description 217 */ 218 #define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x20) 219 /** APB_SARADC_ONETIME_ATTEN : R/W; bitpos: [24:23]; default: 0; 220 * Need add description 221 */ 222 #define APB_SARADC_ONETIME_ATTEN 0x00000003U 223 #define APB_SARADC_ONETIME_ATTEN_M (APB_SARADC_ONETIME_ATTEN_V << APB_SARADC_ONETIME_ATTEN_S) 224 #define APB_SARADC_ONETIME_ATTEN_V 0x00000003U 225 #define APB_SARADC_ONETIME_ATTEN_S 23 226 /** APB_SARADC_ONETIME_CHANNEL : R/W; bitpos: [28:25]; default: 13; 227 * Need add description 228 */ 229 #define APB_SARADC_ONETIME_CHANNEL 0x0000000FU 230 #define APB_SARADC_ONETIME_CHANNEL_M (APB_SARADC_ONETIME_CHANNEL_V << APB_SARADC_ONETIME_CHANNEL_S) 231 #define APB_SARADC_ONETIME_CHANNEL_V 0x0000000FU 232 #define APB_SARADC_ONETIME_CHANNEL_S 25 233 /** APB_SARADC_ONETIME_START : R/W; bitpos: [29]; default: 0; 234 * Need add description 235 */ 236 #define APB_SARADC_ONETIME_START (BIT(29)) 237 #define APB_SARADC_ONETIME_START_M (APB_SARADC_ONETIME_START_V << APB_SARADC_ONETIME_START_S) 238 #define APB_SARADC_ONETIME_START_V 0x00000001U 239 #define APB_SARADC_ONETIME_START_S 29 240 /** APB_SARADC2_ONETIME_SAMPLE : R/W; bitpos: [30]; default: 0; 241 * Need add description 242 */ 243 #define APB_SARADC2_ONETIME_SAMPLE (BIT(30)) 244 #define APB_SARADC2_ONETIME_SAMPLE_M (APB_SARADC2_ONETIME_SAMPLE_V << APB_SARADC2_ONETIME_SAMPLE_S) 245 #define APB_SARADC2_ONETIME_SAMPLE_V 0x00000001U 246 #define APB_SARADC2_ONETIME_SAMPLE_S 30 247 /** APB_SARADC1_ONETIME_SAMPLE : R/W; bitpos: [31]; default: 0; 248 * Need add description 249 */ 250 #define APB_SARADC1_ONETIME_SAMPLE (BIT(31)) 251 #define APB_SARADC1_ONETIME_SAMPLE_M (APB_SARADC1_ONETIME_SAMPLE_V << APB_SARADC1_ONETIME_SAMPLE_S) 252 #define APB_SARADC1_ONETIME_SAMPLE_V 0x00000001U 253 #define APB_SARADC1_ONETIME_SAMPLE_S 31 254 255 /** APB_SARADC_APB_ADC_ARB_CTRL_REG register 256 * register description 257 */ 258 #define APB_SARADC_APB_ADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x24) 259 /** APB_SARADC_ADC_ARB_APB_FORCE : R/W; bitpos: [2]; default: 0; 260 * adc2 arbiter force to enableapb controller 261 */ 262 #define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2)) 263 #define APB_SARADC_ADC_ARB_APB_FORCE_M (APB_SARADC_ADC_ARB_APB_FORCE_V << APB_SARADC_ADC_ARB_APB_FORCE_S) 264 #define APB_SARADC_ADC_ARB_APB_FORCE_V 0x00000001U 265 #define APB_SARADC_ADC_ARB_APB_FORCE_S 2 266 /** APB_SARADC_ADC_ARB_RTC_FORCE : R/W; bitpos: [3]; default: 0; 267 * adc2 arbiter force to enable rtc controller 268 */ 269 #define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3)) 270 #define APB_SARADC_ADC_ARB_RTC_FORCE_M (APB_SARADC_ADC_ARB_RTC_FORCE_V << APB_SARADC_ADC_ARB_RTC_FORCE_S) 271 #define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x00000001U 272 #define APB_SARADC_ADC_ARB_RTC_FORCE_S 3 273 /** APB_SARADC_ADC_ARB_WIFI_FORCE : R/W; bitpos: [4]; default: 0; 274 * adc2 arbiter force to enable wifi controller 275 */ 276 #define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4)) 277 #define APB_SARADC_ADC_ARB_WIFI_FORCE_M (APB_SARADC_ADC_ARB_WIFI_FORCE_V << APB_SARADC_ADC_ARB_WIFI_FORCE_S) 278 #define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x00000001U 279 #define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4 280 /** APB_SARADC_ADC_ARB_GRANT_FORCE : R/W; bitpos: [5]; default: 0; 281 * adc2 arbiter force grant 282 */ 283 #define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5)) 284 #define APB_SARADC_ADC_ARB_GRANT_FORCE_M (APB_SARADC_ADC_ARB_GRANT_FORCE_V << APB_SARADC_ADC_ARB_GRANT_FORCE_S) 285 #define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x00000001U 286 #define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5 287 /** APB_SARADC_ADC_ARB_APB_PRIORITY : R/W; bitpos: [7:6]; default: 0; 288 * Set adc2 arbiterapb priority 289 */ 290 #define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003U 291 #define APB_SARADC_ADC_ARB_APB_PRIORITY_M (APB_SARADC_ADC_ARB_APB_PRIORITY_V << APB_SARADC_ADC_ARB_APB_PRIORITY_S) 292 #define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x00000003U 293 #define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6 294 /** APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W; bitpos: [9:8]; default: 1; 295 * Set adc2 arbiter rtc priority 296 */ 297 #define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003U 298 #define APB_SARADC_ADC_ARB_RTC_PRIORITY_M (APB_SARADC_ADC_ARB_RTC_PRIORITY_V << APB_SARADC_ADC_ARB_RTC_PRIORITY_S) 299 #define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x00000003U 300 #define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8 301 /** APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W; bitpos: [11:10]; default: 2; 302 * Set adc2 arbiter wifi priority 303 */ 304 #define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003U 305 #define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M (APB_SARADC_ADC_ARB_WIFI_PRIORITY_V << APB_SARADC_ADC_ARB_WIFI_PRIORITY_S) 306 #define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x00000003U 307 #define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10 308 /** APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W; bitpos: [12]; default: 0; 309 * adc2 arbiter uses fixed priority 310 */ 311 #define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12)) 312 #define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (APB_SARADC_ADC_ARB_FIX_PRIORITY_V << APB_SARADC_ADC_ARB_FIX_PRIORITY_S) 313 #define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x00000001U 314 #define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12 315 316 /** APB_SARADC_FILTER_CTRL0_REG register 317 * register description 318 */ 319 #define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_SARADC_BASE + 0x28) 320 /** APB_SARADC_FILTER_CHANNEL1 : R/W; bitpos: [21:18]; default: 13; 321 * Need add description 322 */ 323 #define APB_SARADC_FILTER_CHANNEL1 0x0000000FU 324 #define APB_SARADC_FILTER_CHANNEL1_M (APB_SARADC_FILTER_CHANNEL1_V << APB_SARADC_FILTER_CHANNEL1_S) 325 #define APB_SARADC_FILTER_CHANNEL1_V 0x0000000FU 326 #define APB_SARADC_FILTER_CHANNEL1_S 18 327 /** APB_SARADC_FILTER_CHANNEL0 : R/W; bitpos: [25:22]; default: 13; 328 * apb_adc1_filter_factor 329 */ 330 #define APB_SARADC_FILTER_CHANNEL0 0x0000000FU 331 #define APB_SARADC_FILTER_CHANNEL0_M (APB_SARADC_FILTER_CHANNEL0_V << APB_SARADC_FILTER_CHANNEL0_S) 332 #define APB_SARADC_FILTER_CHANNEL0_V 0x0000000FU 333 #define APB_SARADC_FILTER_CHANNEL0_S 22 334 /** APB_SARADC_FILTER_RESET : R/W; bitpos: [31]; default: 0; 335 * enable apb_adc1_filter 336 */ 337 #define APB_SARADC_FILTER_RESET (BIT(31)) 338 #define APB_SARADC_FILTER_RESET_M (APB_SARADC_FILTER_RESET_V << APB_SARADC_FILTER_RESET_S) 339 #define APB_SARADC_FILTER_RESET_V 0x00000001U 340 #define APB_SARADC_FILTER_RESET_S 31 341 342 /** APB_SARADC1_DATA_STATUS_REG register 343 * register description 344 */ 345 #define APB_SARADC1_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x2c) 346 /** APB_SARADC1_DATA : RO; bitpos: [16:0]; default: 0; 347 * Need add description 348 */ 349 #define APB_SARADC1_DATA 0x0001FFFFU 350 #define APB_SARADC1_DATA_M (APB_SARADC1_DATA_V << APB_SARADC1_DATA_S) 351 #define APB_SARADC1_DATA_V 0x0001FFFFU 352 #define APB_SARADC1_DATA_S 0 353 354 /** APB_SARADC2_DATA_STATUS_REG register 355 * register description 356 */ 357 #define APB_SARADC2_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x30) 358 /** APB_SARADC2_DATA : RO; bitpos: [16:0]; default: 0; 359 * Need add description 360 */ 361 #define APB_SARADC2_DATA 0x0001FFFFU 362 #define APB_SARADC2_DATA_M (APB_SARADC2_DATA_V << APB_SARADC2_DATA_S) 363 #define APB_SARADC2_DATA_V 0x0001FFFFU 364 #define APB_SARADC2_DATA_S 0 365 366 /** APB_SARADC_THRES0_CTRL_REG register 367 * register description 368 */ 369 #define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x34) 370 /** APB_SARADC_THRES0_CHANNEL : R/W; bitpos: [3:0]; default: 13; 371 * Need add description 372 */ 373 #define APB_SARADC_THRES0_CHANNEL 0x0000000FU 374 #define APB_SARADC_THRES0_CHANNEL_M (APB_SARADC_THRES0_CHANNEL_V << APB_SARADC_THRES0_CHANNEL_S) 375 #define APB_SARADC_THRES0_CHANNEL_V 0x0000000FU 376 #define APB_SARADC_THRES0_CHANNEL_S 0 377 /** APB_SARADC_THRES0_HIGH : R/W; bitpos: [17:5]; default: 8191; 378 * saradc1's thres0 monitor thres 379 */ 380 #define APB_SARADC_THRES0_HIGH 0x00001FFFU 381 #define APB_SARADC_THRES0_HIGH_M (APB_SARADC_THRES0_HIGH_V << APB_SARADC_THRES0_HIGH_S) 382 #define APB_SARADC_THRES0_HIGH_V 0x00001FFFU 383 #define APB_SARADC_THRES0_HIGH_S 5 384 /** APB_SARADC_THRES0_LOW : R/W; bitpos: [30:18]; default: 0; 385 * saradc1's thres0 monitor thres 386 */ 387 #define APB_SARADC_THRES0_LOW 0x00001FFFU 388 #define APB_SARADC_THRES0_LOW_M (APB_SARADC_THRES0_LOW_V << APB_SARADC_THRES0_LOW_S) 389 #define APB_SARADC_THRES0_LOW_V 0x00001FFFU 390 #define APB_SARADC_THRES0_LOW_S 18 391 392 /** APB_SARADC_THRES1_CTRL_REG register 393 * register description 394 */ 395 #define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x38) 396 /** APB_SARADC_THRES1_CHANNEL : R/W; bitpos: [3:0]; default: 13; 397 * Need add description 398 */ 399 #define APB_SARADC_THRES1_CHANNEL 0x0000000FU 400 #define APB_SARADC_THRES1_CHANNEL_M (APB_SARADC_THRES1_CHANNEL_V << APB_SARADC_THRES1_CHANNEL_S) 401 #define APB_SARADC_THRES1_CHANNEL_V 0x0000000FU 402 #define APB_SARADC_THRES1_CHANNEL_S 0 403 /** APB_SARADC_THRES1_HIGH : R/W; bitpos: [17:5]; default: 8191; 404 * saradc1's thres0 monitor thres 405 */ 406 #define APB_SARADC_THRES1_HIGH 0x00001FFFU 407 #define APB_SARADC_THRES1_HIGH_M (APB_SARADC_THRES1_HIGH_V << APB_SARADC_THRES1_HIGH_S) 408 #define APB_SARADC_THRES1_HIGH_V 0x00001FFFU 409 #define APB_SARADC_THRES1_HIGH_S 5 410 /** APB_SARADC_THRES1_LOW : R/W; bitpos: [30:18]; default: 0; 411 * saradc1's thres0 monitor thres 412 */ 413 #define APB_SARADC_THRES1_LOW 0x00001FFFU 414 #define APB_SARADC_THRES1_LOW_M (APB_SARADC_THRES1_LOW_V << APB_SARADC_THRES1_LOW_S) 415 #define APB_SARADC_THRES1_LOW_V 0x00001FFFU 416 #define APB_SARADC_THRES1_LOW_S 18 417 418 /** APB_SARADC_THRES_CTRL_REG register 419 * register description 420 */ 421 #define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x3c) 422 /** APB_SARADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0; 423 * Need add description 424 */ 425 #define APB_SARADC_THRES_ALL_EN (BIT(27)) 426 #define APB_SARADC_THRES_ALL_EN_M (APB_SARADC_THRES_ALL_EN_V << APB_SARADC_THRES_ALL_EN_S) 427 #define APB_SARADC_THRES_ALL_EN_V 0x00000001U 428 #define APB_SARADC_THRES_ALL_EN_S 27 429 /** APB_SARADC_THRES3_EN : R/W; bitpos: [28]; default: 0; 430 * Need add description 431 */ 432 #define APB_SARADC_THRES3_EN (BIT(28)) 433 #define APB_SARADC_THRES3_EN_M (APB_SARADC_THRES3_EN_V << APB_SARADC_THRES3_EN_S) 434 #define APB_SARADC_THRES3_EN_V 0x00000001U 435 #define APB_SARADC_THRES3_EN_S 28 436 /** APB_SARADC_THRES2_EN : R/W; bitpos: [29]; default: 0; 437 * Need add description 438 */ 439 #define APB_SARADC_THRES2_EN (BIT(29)) 440 #define APB_SARADC_THRES2_EN_M (APB_SARADC_THRES2_EN_V << APB_SARADC_THRES2_EN_S) 441 #define APB_SARADC_THRES2_EN_V 0x00000001U 442 #define APB_SARADC_THRES2_EN_S 29 443 /** APB_SARADC_THRES1_EN : R/W; bitpos: [30]; default: 0; 444 * Need add description 445 */ 446 #define APB_SARADC_THRES1_EN (BIT(30)) 447 #define APB_SARADC_THRES1_EN_M (APB_SARADC_THRES1_EN_V << APB_SARADC_THRES1_EN_S) 448 #define APB_SARADC_THRES1_EN_V 0x00000001U 449 #define APB_SARADC_THRES1_EN_S 30 450 /** APB_SARADC_THRES0_EN : R/W; bitpos: [31]; default: 0; 451 * Need add description 452 */ 453 #define APB_SARADC_THRES0_EN (BIT(31)) 454 #define APB_SARADC_THRES0_EN_M (APB_SARADC_THRES0_EN_V << APB_SARADC_THRES0_EN_S) 455 #define APB_SARADC_THRES0_EN_V 0x00000001U 456 #define APB_SARADC_THRES0_EN_S 31 457 458 /** APB_SARADC_INT_ENA_REG register 459 * register description 460 */ 461 #define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x40) 462 /** APB_SARADC_THRES1_LOW_INT_ENA : R/W; bitpos: [26]; default: 0; 463 * Need add description 464 */ 465 #define APB_SARADC_THRES1_LOW_INT_ENA (BIT(26)) 466 #define APB_SARADC_THRES1_LOW_INT_ENA_M (APB_SARADC_THRES1_LOW_INT_ENA_V << APB_SARADC_THRES1_LOW_INT_ENA_S) 467 #define APB_SARADC_THRES1_LOW_INT_ENA_V 0x00000001U 468 #define APB_SARADC_THRES1_LOW_INT_ENA_S 26 469 /** APB_SARADC_THRES0_LOW_INT_ENA : R/W; bitpos: [27]; default: 0; 470 * Need add description 471 */ 472 #define APB_SARADC_THRES0_LOW_INT_ENA (BIT(27)) 473 #define APB_SARADC_THRES0_LOW_INT_ENA_M (APB_SARADC_THRES0_LOW_INT_ENA_V << APB_SARADC_THRES0_LOW_INT_ENA_S) 474 #define APB_SARADC_THRES0_LOW_INT_ENA_V 0x00000001U 475 #define APB_SARADC_THRES0_LOW_INT_ENA_S 27 476 /** APB_SARADC_THRES1_HIGH_INT_ENA : R/W; bitpos: [28]; default: 0; 477 * Need add description 478 */ 479 #define APB_SARADC_THRES1_HIGH_INT_ENA (BIT(28)) 480 #define APB_SARADC_THRES1_HIGH_INT_ENA_M (APB_SARADC_THRES1_HIGH_INT_ENA_V << APB_SARADC_THRES1_HIGH_INT_ENA_S) 481 #define APB_SARADC_THRES1_HIGH_INT_ENA_V 0x00000001U 482 #define APB_SARADC_THRES1_HIGH_INT_ENA_S 28 483 /** APB_SARADC_THRES0_HIGH_INT_ENA : R/W; bitpos: [29]; default: 0; 484 * Need add description 485 */ 486 #define APB_SARADC_THRES0_HIGH_INT_ENA (BIT(29)) 487 #define APB_SARADC_THRES0_HIGH_INT_ENA_M (APB_SARADC_THRES0_HIGH_INT_ENA_V << APB_SARADC_THRES0_HIGH_INT_ENA_S) 488 #define APB_SARADC_THRES0_HIGH_INT_ENA_V 0x00000001U 489 #define APB_SARADC_THRES0_HIGH_INT_ENA_S 29 490 /** APB_SARADC2_DONE_INT_ENA : R/W; bitpos: [30]; default: 0; 491 * Need add description 492 */ 493 #define APB_SARADC2_DONE_INT_ENA (BIT(30)) 494 #define APB_SARADC2_DONE_INT_ENA_M (APB_SARADC2_DONE_INT_ENA_V << APB_SARADC2_DONE_INT_ENA_S) 495 #define APB_SARADC2_DONE_INT_ENA_V 0x00000001U 496 #define APB_SARADC2_DONE_INT_ENA_S 30 497 /** APB_SARADC1_DONE_INT_ENA : R/W; bitpos: [31]; default: 0; 498 * Need add description 499 */ 500 #define APB_SARADC1_DONE_INT_ENA (BIT(31)) 501 #define APB_SARADC1_DONE_INT_ENA_M (APB_SARADC1_DONE_INT_ENA_V << APB_SARADC1_DONE_INT_ENA_S) 502 #define APB_SARADC1_DONE_INT_ENA_V 0x00000001U 503 #define APB_SARADC1_DONE_INT_ENA_S 31 504 505 /** APB_SARADC_INT_RAW_REG register 506 * register description 507 */ 508 #define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x44) 509 /** APB_SARADC_THRES1_LOW_INT_RAW : RO; bitpos: [26]; default: 0; 510 * Need add description 511 */ 512 #define APB_SARADC_THRES1_LOW_INT_RAW (BIT(26)) 513 #define APB_SARADC_THRES1_LOW_INT_RAW_M (APB_SARADC_THRES1_LOW_INT_RAW_V << APB_SARADC_THRES1_LOW_INT_RAW_S) 514 #define APB_SARADC_THRES1_LOW_INT_RAW_V 0x00000001U 515 #define APB_SARADC_THRES1_LOW_INT_RAW_S 26 516 /** APB_SARADC_THRES0_LOW_INT_RAW : RO; bitpos: [27]; default: 0; 517 * Need add description 518 */ 519 #define APB_SARADC_THRES0_LOW_INT_RAW (BIT(27)) 520 #define APB_SARADC_THRES0_LOW_INT_RAW_M (APB_SARADC_THRES0_LOW_INT_RAW_V << APB_SARADC_THRES0_LOW_INT_RAW_S) 521 #define APB_SARADC_THRES0_LOW_INT_RAW_V 0x00000001U 522 #define APB_SARADC_THRES0_LOW_INT_RAW_S 27 523 /** APB_SARADC_THRES1_HIGH_INT_RAW : RO; bitpos: [28]; default: 0; 524 * Need add description 525 */ 526 #define APB_SARADC_THRES1_HIGH_INT_RAW (BIT(28)) 527 #define APB_SARADC_THRES1_HIGH_INT_RAW_M (APB_SARADC_THRES1_HIGH_INT_RAW_V << APB_SARADC_THRES1_HIGH_INT_RAW_S) 528 #define APB_SARADC_THRES1_HIGH_INT_RAW_V 0x00000001U 529 #define APB_SARADC_THRES1_HIGH_INT_RAW_S 28 530 /** APB_SARADC_THRES0_HIGH_INT_RAW : RO; bitpos: [29]; default: 0; 531 * Need add description 532 */ 533 #define APB_SARADC_THRES0_HIGH_INT_RAW (BIT(29)) 534 #define APB_SARADC_THRES0_HIGH_INT_RAW_M (APB_SARADC_THRES0_HIGH_INT_RAW_V << APB_SARADC_THRES0_HIGH_INT_RAW_S) 535 #define APB_SARADC_THRES0_HIGH_INT_RAW_V 0x00000001U 536 #define APB_SARADC_THRES0_HIGH_INT_RAW_S 29 537 /** APB_SARADC2_DONE_INT_RAW : RO; bitpos: [30]; default: 0; 538 * Need add description 539 */ 540 #define APB_SARADC2_DONE_INT_RAW (BIT(30)) 541 #define APB_SARADC2_DONE_INT_RAW_M (APB_SARADC2_DONE_INT_RAW_V << APB_SARADC2_DONE_INT_RAW_S) 542 #define APB_SARADC2_DONE_INT_RAW_V 0x00000001U 543 #define APB_SARADC2_DONE_INT_RAW_S 30 544 /** APB_SARADC1_DONE_INT_RAW : RO; bitpos: [31]; default: 0; 545 * Need add description 546 */ 547 #define APB_SARADC1_DONE_INT_RAW (BIT(31)) 548 #define APB_SARADC1_DONE_INT_RAW_M (APB_SARADC1_DONE_INT_RAW_V << APB_SARADC1_DONE_INT_RAW_S) 549 #define APB_SARADC1_DONE_INT_RAW_V 0x00000001U 550 #define APB_SARADC1_DONE_INT_RAW_S 31 551 552 /** APB_SARADC_INT_ST_REG register 553 * register description 554 */ 555 #define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x48) 556 /** APB_SARADC_THRES1_LOW_INT_ST : RO; bitpos: [26]; default: 0; 557 * Need add description 558 */ 559 #define APB_SARADC_THRES1_LOW_INT_ST (BIT(26)) 560 #define APB_SARADC_THRES1_LOW_INT_ST_M (APB_SARADC_THRES1_LOW_INT_ST_V << APB_SARADC_THRES1_LOW_INT_ST_S) 561 #define APB_SARADC_THRES1_LOW_INT_ST_V 0x00000001U 562 #define APB_SARADC_THRES1_LOW_INT_ST_S 26 563 /** APB_SARADC_THRES0_LOW_INT_ST : RO; bitpos: [27]; default: 0; 564 * Need add description 565 */ 566 #define APB_SARADC_THRES0_LOW_INT_ST (BIT(27)) 567 #define APB_SARADC_THRES0_LOW_INT_ST_M (APB_SARADC_THRES0_LOW_INT_ST_V << APB_SARADC_THRES0_LOW_INT_ST_S) 568 #define APB_SARADC_THRES0_LOW_INT_ST_V 0x00000001U 569 #define APB_SARADC_THRES0_LOW_INT_ST_S 27 570 /** APB_SARADC_THRES1_HIGH_INT_ST : RO; bitpos: [28]; default: 0; 571 * Need add description 572 */ 573 #define APB_SARADC_THRES1_HIGH_INT_ST (BIT(28)) 574 #define APB_SARADC_THRES1_HIGH_INT_ST_M (APB_SARADC_THRES1_HIGH_INT_ST_V << APB_SARADC_THRES1_HIGH_INT_ST_S) 575 #define APB_SARADC_THRES1_HIGH_INT_ST_V 0x00000001U 576 #define APB_SARADC_THRES1_HIGH_INT_ST_S 28 577 /** APB_SARADC_THRES0_HIGH_INT_ST : RO; bitpos: [29]; default: 0; 578 * Need add description 579 */ 580 #define APB_SARADC_THRES0_HIGH_INT_ST (BIT(29)) 581 #define APB_SARADC_THRES0_HIGH_INT_ST_M (APB_SARADC_THRES0_HIGH_INT_ST_V << APB_SARADC_THRES0_HIGH_INT_ST_S) 582 #define APB_SARADC_THRES0_HIGH_INT_ST_V 0x00000001U 583 #define APB_SARADC_THRES0_HIGH_INT_ST_S 29 584 /** APB_SARADC2_DONE_INT_ST : RO; bitpos: [30]; default: 0; 585 * Need add description 586 */ 587 #define APB_SARADC2_DONE_INT_ST (BIT(30)) 588 #define APB_SARADC2_DONE_INT_ST_M (APB_SARADC2_DONE_INT_ST_V << APB_SARADC2_DONE_INT_ST_S) 589 #define APB_SARADC2_DONE_INT_ST_V 0x00000001U 590 #define APB_SARADC2_DONE_INT_ST_S 30 591 /** APB_SARADC1_DONE_INT_ST : RO; bitpos: [31]; default: 0; 592 * Need add description 593 */ 594 #define APB_SARADC1_DONE_INT_ST (BIT(31)) 595 #define APB_SARADC1_DONE_INT_ST_M (APB_SARADC1_DONE_INT_ST_V << APB_SARADC1_DONE_INT_ST_S) 596 #define APB_SARADC1_DONE_INT_ST_V 0x00000001U 597 #define APB_SARADC1_DONE_INT_ST_S 31 598 599 /** APB_SARADC_INT_CLR_REG register 600 * register description 601 */ 602 #define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x4c) 603 /** APB_SARADC_THRES1_LOW_INT_CLR : WO; bitpos: [26]; default: 0; 604 * Need add description 605 */ 606 #define APB_SARADC_THRES1_LOW_INT_CLR (BIT(26)) 607 #define APB_SARADC_THRES1_LOW_INT_CLR_M (APB_SARADC_THRES1_LOW_INT_CLR_V << APB_SARADC_THRES1_LOW_INT_CLR_S) 608 #define APB_SARADC_THRES1_LOW_INT_CLR_V 0x00000001U 609 #define APB_SARADC_THRES1_LOW_INT_CLR_S 26 610 /** APB_SARADC_THRES0_LOW_INT_CLR : WO; bitpos: [27]; default: 0; 611 * Need add description 612 */ 613 #define APB_SARADC_THRES0_LOW_INT_CLR (BIT(27)) 614 #define APB_SARADC_THRES0_LOW_INT_CLR_M (APB_SARADC_THRES0_LOW_INT_CLR_V << APB_SARADC_THRES0_LOW_INT_CLR_S) 615 #define APB_SARADC_THRES0_LOW_INT_CLR_V 0x00000001U 616 #define APB_SARADC_THRES0_LOW_INT_CLR_S 27 617 /** APB_SARADC_THRES1_HIGH_INT_CLR : WO; bitpos: [28]; default: 0; 618 * Need add description 619 */ 620 #define APB_SARADC_THRES1_HIGH_INT_CLR (BIT(28)) 621 #define APB_SARADC_THRES1_HIGH_INT_CLR_M (APB_SARADC_THRES1_HIGH_INT_CLR_V << APB_SARADC_THRES1_HIGH_INT_CLR_S) 622 #define APB_SARADC_THRES1_HIGH_INT_CLR_V 0x00000001U 623 #define APB_SARADC_THRES1_HIGH_INT_CLR_S 28 624 /** APB_SARADC_THRES0_HIGH_INT_CLR : WO; bitpos: [29]; default: 0; 625 * Need add description 626 */ 627 #define APB_SARADC_THRES0_HIGH_INT_CLR (BIT(29)) 628 #define APB_SARADC_THRES0_HIGH_INT_CLR_M (APB_SARADC_THRES0_HIGH_INT_CLR_V << APB_SARADC_THRES0_HIGH_INT_CLR_S) 629 #define APB_SARADC_THRES0_HIGH_INT_CLR_V 0x00000001U 630 #define APB_SARADC_THRES0_HIGH_INT_CLR_S 29 631 /** APB_SARADC2_DONE_INT_CLR : WO; bitpos: [30]; default: 0; 632 * Need add description 633 */ 634 #define APB_SARADC2_DONE_INT_CLR (BIT(30)) 635 #define APB_SARADC2_DONE_INT_CLR_M (APB_SARADC2_DONE_INT_CLR_V << APB_SARADC2_DONE_INT_CLR_S) 636 #define APB_SARADC2_DONE_INT_CLR_V 0x00000001U 637 #define APB_SARADC2_DONE_INT_CLR_S 30 638 /** APB_SARADC1_DONE_INT_CLR : WO; bitpos: [31]; default: 0; 639 * Need add description 640 */ 641 #define APB_SARADC1_DONE_INT_CLR (BIT(31)) 642 #define APB_SARADC1_DONE_INT_CLR_M (APB_SARADC1_DONE_INT_CLR_V << APB_SARADC1_DONE_INT_CLR_S) 643 #define APB_SARADC1_DONE_INT_CLR_V 0x00000001U 644 #define APB_SARADC1_DONE_INT_CLR_S 31 645 646 /** APB_SARADC_DMA_CONF_REG register 647 * register description 648 */ 649 #define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x50) 650 /** APB_SARADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255; 651 * the dma_in_suc_eof gen when sample cnt = spi_eof_num 652 */ 653 #define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFFU 654 #define APB_SARADC_APB_ADC_EOF_NUM_M (APB_SARADC_APB_ADC_EOF_NUM_V << APB_SARADC_APB_ADC_EOF_NUM_S) 655 #define APB_SARADC_APB_ADC_EOF_NUM_V 0x0000FFFFU 656 #define APB_SARADC_APB_ADC_EOF_NUM_S 0 657 /** APB_SARADC_APB_ADC_RESET_FSM : R/W; bitpos: [30]; default: 0; 658 * reset_apb_adc_state 659 */ 660 #define APB_SARADC_APB_ADC_RESET_FSM (BIT(30)) 661 #define APB_SARADC_APB_ADC_RESET_FSM_M (APB_SARADC_APB_ADC_RESET_FSM_V << APB_SARADC_APB_ADC_RESET_FSM_S) 662 #define APB_SARADC_APB_ADC_RESET_FSM_V 0x00000001U 663 #define APB_SARADC_APB_ADC_RESET_FSM_S 30 664 /** APB_SARADC_APB_ADC_TRANS : R/W; bitpos: [31]; default: 0; 665 * enable apb_adc use spi_dma 666 */ 667 #define APB_SARADC_APB_ADC_TRANS (BIT(31)) 668 #define APB_SARADC_APB_ADC_TRANS_M (APB_SARADC_APB_ADC_TRANS_V << APB_SARADC_APB_ADC_TRANS_S) 669 #define APB_SARADC_APB_ADC_TRANS_V 0x00000001U 670 #define APB_SARADC_APB_ADC_TRANS_S 31 671 672 /** APB_SARADC_APB_ADC_CLKM_CONF_REG register 673 * register description 674 */ 675 #define APB_SARADC_APB_ADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x54) 676 /** APB_SARADC_REG_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 4; 677 * Integral I2S clock divider value 678 */ 679 #define APB_SARADC_REG_CLKM_DIV_NUM 0x000000FFU 680 #define APB_SARADC_REG_CLKM_DIV_NUM_M (APB_SARADC_REG_CLKM_DIV_NUM_V << APB_SARADC_REG_CLKM_DIV_NUM_S) 681 #define APB_SARADC_REG_CLKM_DIV_NUM_V 0x000000FFU 682 #define APB_SARADC_REG_CLKM_DIV_NUM_S 0 683 /** APB_SARADC_REG_CLKM_DIV_B : R/W; bitpos: [13:8]; default: 0; 684 * Fractional clock divider numerator value 685 */ 686 #define APB_SARADC_REG_CLKM_DIV_B 0x0000003FU 687 #define APB_SARADC_REG_CLKM_DIV_B_M (APB_SARADC_REG_CLKM_DIV_B_V << APB_SARADC_REG_CLKM_DIV_B_S) 688 #define APB_SARADC_REG_CLKM_DIV_B_V 0x0000003FU 689 #define APB_SARADC_REG_CLKM_DIV_B_S 8 690 /** APB_SARADC_REG_CLKM_DIV_A : R/W; bitpos: [19:14]; default: 0; 691 * Fractional clock divider denominator value 692 */ 693 #define APB_SARADC_REG_CLKM_DIV_A 0x0000003FU 694 #define APB_SARADC_REG_CLKM_DIV_A_M (APB_SARADC_REG_CLKM_DIV_A_V << APB_SARADC_REG_CLKM_DIV_A_S) 695 #define APB_SARADC_REG_CLKM_DIV_A_V 0x0000003FU 696 #define APB_SARADC_REG_CLKM_DIV_A_S 14 697 /** APB_SARADC_CLK_EN : R/W; bitpos: [20]; default: 0; 698 * Need add description 699 */ 700 #define APB_SARADC_CLK_EN (BIT(20)) 701 #define APB_SARADC_CLK_EN_M (APB_SARADC_CLK_EN_V << APB_SARADC_CLK_EN_S) 702 #define APB_SARADC_CLK_EN_V 0x00000001U 703 #define APB_SARADC_CLK_EN_S 20 704 /** APB_SARADC_REG_CLK_SEL : R/W; bitpos: [22:21]; default: 0; 705 * Set this bit to enable clk_apll 706 */ 707 #define APB_SARADC_REG_CLK_SEL 0x00000003U 708 #define APB_SARADC_REG_CLK_SEL_M (APB_SARADC_REG_CLK_SEL_V << APB_SARADC_REG_CLK_SEL_S) 709 #define APB_SARADC_REG_CLK_SEL_V 0x00000003U 710 #define APB_SARADC_REG_CLK_SEL_S 21 711 712 /** APB_SARADC_APB_TSENS_CTRL_REG register 713 * register description 714 */ 715 #define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x58) 716 /** APB_SARADC_REG_TSENS_OUT : RO; bitpos: [7:0]; default: 0; 717 * Need add description 718 */ 719 #define APB_SARADC_REG_TSENS_OUT 0x000000FFU 720 #define APB_SARADC_REG_TSENS_OUT_M (APB_SARADC_REG_TSENS_OUT_V << APB_SARADC_REG_TSENS_OUT_S) 721 #define APB_SARADC_REG_TSENS_OUT_V 0x000000FFU 722 #define APB_SARADC_REG_TSENS_OUT_S 0 723 /** APB_SARADC_REG_TSENS_IN_INV : R/W; bitpos: [13]; default: 0; 724 * Need add description 725 */ 726 #define APB_SARADC_REG_TSENS_IN_INV (BIT(13)) 727 #define APB_SARADC_REG_TSENS_IN_INV_M (APB_SARADC_REG_TSENS_IN_INV_V << APB_SARADC_REG_TSENS_IN_INV_S) 728 #define APB_SARADC_REG_TSENS_IN_INV_V 0x00000001U 729 #define APB_SARADC_REG_TSENS_IN_INV_S 13 730 /** APB_SARADC_REG_TSENS_CLK_DIV : R/W; bitpos: [21:14]; default: 6; 731 * Need add description 732 */ 733 #define APB_SARADC_REG_TSENS_CLK_DIV 0x000000FFU 734 #define APB_SARADC_REG_TSENS_CLK_DIV_M (APB_SARADC_REG_TSENS_CLK_DIV_V << APB_SARADC_REG_TSENS_CLK_DIV_S) 735 #define APB_SARADC_REG_TSENS_CLK_DIV_V 0x000000FFU 736 #define APB_SARADC_REG_TSENS_CLK_DIV_S 14 737 /** APB_SARADC_REG_TSENS_PU : R/W; bitpos: [22]; default: 0; 738 * Need add description 739 */ 740 #define APB_SARADC_REG_TSENS_PU (BIT(22)) 741 #define APB_SARADC_REG_TSENS_PU_M (APB_SARADC_REG_TSENS_PU_V << APB_SARADC_REG_TSENS_PU_S) 742 #define APB_SARADC_REG_TSENS_PU_V 0x00000001U 743 #define APB_SARADC_REG_TSENS_PU_S 22 744 745 /** APB_SARADC_APB_TSENS_CTRL2_REG register 746 * register description 747 */ 748 #define APB_SARADC_APB_TSENS_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x5c) 749 /** APB_SARADC_REG_TSENS_XPD_WAIT : R/W; bitpos: [11:0]; default: 2; 750 * Need add description 751 */ 752 #define APB_SARADC_REG_TSENS_XPD_WAIT 0x00000FFFU 753 #define APB_SARADC_REG_TSENS_XPD_WAIT_M (APB_SARADC_REG_TSENS_XPD_WAIT_V << APB_SARADC_REG_TSENS_XPD_WAIT_S) 754 #define APB_SARADC_REG_TSENS_XPD_WAIT_V 0x00000FFFU 755 #define APB_SARADC_REG_TSENS_XPD_WAIT_S 0 756 /** APB_SARADC_REG_TSENS_XPD_FORCE : R/W; bitpos: [13:12]; default: 0; 757 * Need add description 758 */ 759 #define APB_SARADC_REG_TSENS_XPD_FORCE 0x00000003U 760 #define APB_SARADC_REG_TSENS_XPD_FORCE_M (APB_SARADC_REG_TSENS_XPD_FORCE_V << APB_SARADC_REG_TSENS_XPD_FORCE_S) 761 #define APB_SARADC_REG_TSENS_XPD_FORCE_V 0x00000003U 762 #define APB_SARADC_REG_TSENS_XPD_FORCE_S 12 763 /** APB_SARADC_REG_TSENS_CLK_INV : R/W; bitpos: [14]; default: 1; 764 * Need add description 765 */ 766 #define APB_SARADC_REG_TSENS_CLK_INV (BIT(14)) 767 #define APB_SARADC_REG_TSENS_CLK_INV_M (APB_SARADC_REG_TSENS_CLK_INV_V << APB_SARADC_REG_TSENS_CLK_INV_S) 768 #define APB_SARADC_REG_TSENS_CLK_INV_V 0x00000001U 769 #define APB_SARADC_REG_TSENS_CLK_INV_S 14 770 /** APB_SARADC_TSENS_CLK_SEL : R/W; bitpos: [15]; default: 0; 771 * Need add description 772 */ 773 #define APB_SARADC_TSENS_CLK_SEL (BIT(15)) 774 #define APB_SARADC_TSENS_CLK_SEL_M (APB_SARADC_TSENS_CLK_SEL_V << APB_SARADC_TSENS_CLK_SEL_S) 775 #define APB_SARADC_TSENS_CLK_SEL_V 0x00000001U 776 #define APB_SARADC_TSENS_CLK_SEL_S 15 777 778 /** APB_SARADC_CALI_REG register 779 * register description 780 */ 781 #define APB_SARADC_CALI_REG (DR_REG_APB_SARADC_BASE + 0x60) 782 /** APB_SARADC_CALI_CFG : R/W; bitpos: [16:0]; default: 32768; 783 * Need add description 784 */ 785 #define APB_SARADC_CALI_CFG 0x0001FFFFU 786 #define APB_SARADC_CALI_CFG_M (APB_SARADC_CALI_CFG_V << APB_SARADC_CALI_CFG_S) 787 #define APB_SARADC_CALI_CFG_V 0x0001FFFFU 788 #define APB_SARADC_CALI_CFG_S 0 789 790 /** APB_SARADC_APB_CTRL_DATE_REG register 791 * register description 792 */ 793 #define APB_SARADC_APB_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3fc) 794 /** APB_SARADC_DATE : R/W; bitpos: [31:0]; default: 34632208; 795 * Need add description 796 */ 797 #define APB_SARADC_DATE 0xFFFFFFFFU 798 #define APB_SARADC_DATE_M (APB_SARADC_DATE_V << APB_SARADC_DATE_S) 799 #define APB_SARADC_DATE_V 0xFFFFFFFFU 800 #define APB_SARADC_DATE_S 0 801 802 #ifdef __cplusplus 803 } 804 #endif 805