1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_MCLK_COMPONENT_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_MCLK_COMPONENT_FIXUP_H_ 9 10 /* -------- MCLK_INTENCLR : (MCLK Offset: 0x01) (R/W 8) Interrupt Enable Clear -------- */ 11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 typedef union { 13 struct { 14 uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ 15 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 16 } bit; /*!< Structure used for bit access */ 17 uint8_t reg; /*!< Type used for register access */ 18 } MCLK_INTENCLR_Type; 19 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 20 21 /* -------- MCLK_INTENSET : (MCLK Offset: 0x02) (R/W 8) Interrupt Enable Set -------- */ 22 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 23 typedef union { 24 struct { 25 uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ 26 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 27 } bit; /*!< Structure used for bit access */ 28 uint8_t reg; /*!< Type used for register access */ 29 } MCLK_INTENSET_Type; 30 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 31 32 /* -------- MCLK_INTFLAG : (MCLK Offset: 0x03) (R/W 8) Interrupt Flag Status and Clear -------- */ 33 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 typedef union { // __I to avoid read-modify-write on write-to-clear register 35 struct { 36 __I uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */ 37 __I uint8_t :7; /*!< bit: 1.. 7 Reserved */ 38 } bit; /*!< Structure used for bit access */ 39 uint8_t reg; /*!< Type used for register access */ 40 } MCLK_INTFLAG_Type; 41 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 42 43 /* -------- MCLK_HSDIV : (MCLK Offset: 0x04) ( R/ 8) HS Clock Division -------- */ 44 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 45 typedef union { 46 struct { 47 uint8_t DIV:8; /*!< bit: 0.. 7 CPU Clock Division Factor */ 48 } bit; /*!< Structure used for bit access */ 49 uint8_t reg; /*!< Type used for register access */ 50 } MCLK_HSDIV_Type; 51 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 52 53 /* -------- MCLK_CPUDIV : (MCLK Offset: 0x05) (R/W 8) CPU Clock Division -------- */ 54 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 55 typedef union { 56 struct { 57 uint8_t DIV:8; /*!< bit: 0.. 7 Low-Power Clock Division Factor */ 58 } bit; /*!< Structure used for bit access */ 59 uint8_t reg; /*!< Type used for register access */ 60 } MCLK_CPUDIV_Type; 61 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 62 63 /* -------- MCLK_AHBMASK : (MCLK Offset: 0x10) (R/W 32) AHB Mask -------- */ 64 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 65 typedef union { 66 struct { 67 uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */ 68 uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */ 69 uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */ 70 uint32_t HPB3_:1; /*!< bit: 3 HPB3 AHB Clock Mask */ 71 uint32_t DSU_:1; /*!< bit: 4 DSU AHB Clock Mask */ 72 uint32_t HMATRIX_:1; /*!< bit: 5 HMATRIX AHB Clock Mask */ 73 uint32_t NVMCTRL_:1; /*!< bit: 6 NVMCTRL AHB Clock Mask */ 74 uint32_t HSRAM_:1; /*!< bit: 7 HSRAM AHB Clock Mask */ 75 uint32_t CMCC_:1; /*!< bit: 8 CMCC AHB Clock Mask */ 76 uint32_t DMAC_:1; /*!< bit: 9 DMAC AHB Clock Mask */ 77 uint32_t USB_:1; /*!< bit: 10 USB AHB Clock Mask */ 78 uint32_t BKUPRAM_:1; /*!< bit: 11 BKUPRAM AHB Clock Mask */ 79 uint32_t PAC_:1; /*!< bit: 12 PAC AHB Clock Mask */ 80 uint32_t QSPI_:1; /*!< bit: 13 QSPI AHB Clock Mask */ 81 uint32_t GMAC_:1; /*!< bit: 14 GMAC AHB Clock Mask */ 82 uint32_t SDHC0_:1; /*!< bit: 15 SDHC0 AHB Clock Mask */ 83 uint32_t SDHC1_:1; /*!< bit: 16 SDHC1 AHB Clock Mask */ 84 uint32_t CAN0_:1; /*!< bit: 17 CAN0 AHB Clock Mask */ 85 uint32_t CAN1_:1; /*!< bit: 18 CAN1 AHB Clock Mask */ 86 uint32_t ICM_:1; /*!< bit: 19 ICM AHB Clock Mask */ 87 uint32_t PUKCC_:1; /*!< bit: 20 PUKCC AHB Clock Mask */ 88 uint32_t QSPI_2X_:1; /*!< bit: 21 QSPI_2X AHB Clock Mask */ 89 uint32_t NVMCTRL_SMEEPROM_:1; /*!< bit: 22 NVMCTRL_SMEEPROM AHB Clock Mask */ 90 uint32_t NVMCTRL_CACHE_:1; /*!< bit: 23 NVMCTRL_CACHE AHB Clock Mask */ 91 uint32_t :8; /*!< bit: 24..31 Reserved */ 92 } bit; /*!< Structure used for bit access */ 93 uint32_t reg; /*!< Type used for register access */ 94 } MCLK_AHBMASK_Type; 95 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 96 97 /* -------- MCLK_APBAMASK : (MCLK Offset: 0x14) (R/W 32) APBA Mask -------- */ 98 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 99 typedef union { 100 struct { 101 uint32_t PAC_:1; /*!< bit: 0 PAC APB Clock Enable */ 102 uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */ 103 uint32_t MCLK_:1; /*!< bit: 2 MCLK APB Clock Enable */ 104 uint32_t RSTC_:1; /*!< bit: 3 RSTC APB Clock Enable */ 105 uint32_t OSCCTRL_:1; /*!< bit: 4 OSCCTRL APB Clock Enable */ 106 uint32_t OSC32KCTRL_:1; /*!< bit: 5 OSC32KCTRL APB Clock Enable */ 107 uint32_t SUPC_:1; /*!< bit: 6 SUPC APB Clock Enable */ 108 uint32_t GCLK_:1; /*!< bit: 7 GCLK APB Clock Enable */ 109 uint32_t WDT_:1; /*!< bit: 8 WDT APB Clock Enable */ 110 uint32_t RTC_:1; /*!< bit: 9 RTC APB Clock Enable */ 111 uint32_t EIC_:1; /*!< bit: 10 EIC APB Clock Enable */ 112 uint32_t FREQM_:1; /*!< bit: 11 FREQM APB Clock Enable */ 113 uint32_t SERCOM0_:1; /*!< bit: 12 SERCOM0 APB Clock Enable */ 114 uint32_t SERCOM1_:1; /*!< bit: 13 SERCOM1 APB Clock Enable */ 115 uint32_t TC0_:1; /*!< bit: 14 TC0 APB Clock Enable */ 116 uint32_t TC1_:1; /*!< bit: 15 TC1 APB Clock Enable */ 117 uint32_t :16; /*!< bit: 16..31 Reserved */ 118 } bit; /*!< Structure used for bit access */ 119 uint32_t reg; /*!< Type used for register access */ 120 } MCLK_APBAMASK_Type; 121 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 122 123 #define MCLK_APBAMASK_EIC_BIT_MASK ((uint32_t)(0x1) << MCLK_APBAMASK_EIC_Pos) 124 125 /* -------- MCLK_APBBMASK : (MCLK Offset: 0x18) (R/W 32) APBB Mask -------- */ 126 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 127 typedef union { 128 struct { 129 uint32_t USB_:1; /*!< bit: 0 USB APB Clock Enable */ 130 uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */ 131 uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */ 132 uint32_t :1; /*!< bit: 3 Reserved */ 133 uint32_t PORT_:1; /*!< bit: 4 PORT APB Clock Enable */ 134 uint32_t :1; /*!< bit: 5 Reserved */ 135 uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */ 136 uint32_t EVSYS_:1; /*!< bit: 7 EVSYS APB Clock Enable */ 137 uint32_t :1; /*!< bit: 8 Reserved */ 138 uint32_t SERCOM2_:1; /*!< bit: 9 SERCOM2 APB Clock Enable */ 139 uint32_t SERCOM3_:1; /*!< bit: 10 SERCOM3 APB Clock Enable */ 140 uint32_t TCC0_:1; /*!< bit: 11 TCC0 APB Clock Enable */ 141 uint32_t TCC1_:1; /*!< bit: 12 TCC1 APB Clock Enable */ 142 uint32_t TC2_:1; /*!< bit: 13 TC2 APB Clock Enable */ 143 uint32_t TC3_:1; /*!< bit: 14 TC3 APB Clock Enable */ 144 uint32_t :1; /*!< bit: 15 Reserved */ 145 uint32_t RAMECC_:1; /*!< bit: 16 RAMECC APB Clock Enable */ 146 uint32_t :15; /*!< bit: 17..31 Reserved */ 147 } bit; /*!< Structure used for bit access */ 148 uint32_t reg; /*!< Type used for register access */ 149 } MCLK_APBBMASK_Type; 150 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 151 152 /* -------- MCLK_APBCMASK : (MCLK Offset: 0x1C) (R/W 32) APBC Mask -------- */ 153 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 154 typedef union { 155 struct { 156 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 157 uint32_t GMAC_:1; /*!< bit: 2 GMAC APB Clock Enable */ 158 uint32_t TCC2_:1; /*!< bit: 3 TCC2 APB Clock Enable */ 159 uint32_t TCC3_:1; /*!< bit: 4 TCC3 APB Clock Enable */ 160 uint32_t TC4_:1; /*!< bit: 5 TC4 APB Clock Enable */ 161 uint32_t TC5_:1; /*!< bit: 6 TC5 APB Clock Enable */ 162 uint32_t PDEC_:1; /*!< bit: 7 PDEC APB Clock Enable */ 163 uint32_t AC_:1; /*!< bit: 8 AC APB Clock Enable */ 164 uint32_t AES_:1; /*!< bit: 9 AES APB Clock Enable */ 165 uint32_t TRNG_:1; /*!< bit: 10 TRNG APB Clock Enable */ 166 uint32_t ICM_:1; /*!< bit: 11 ICM APB Clock Enable */ 167 uint32_t :1; /*!< bit: 12 Reserved */ 168 uint32_t QSPI_:1; /*!< bit: 13 QSPI APB Clock Enable */ 169 uint32_t CCL_:1; /*!< bit: 14 CCL APB Clock Enable */ 170 uint32_t :17; /*!< bit: 15..31 Reserved */ 171 } bit; /*!< Structure used for bit access */ 172 uint32_t reg; /*!< Type used for register access */ 173 } MCLK_APBCMASK_Type; 174 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 175 176 /* -------- MCLK_APBDMASK : (MCLK Offset: 0x20) (R/W 32) APBD Mask -------- */ 177 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 178 typedef union { 179 struct { 180 uint32_t SERCOM4_:1; /*!< bit: 0 SERCOM4 APB Clock Enable */ 181 uint32_t SERCOM5_:1; /*!< bit: 1 SERCOM5 APB Clock Enable */ 182 uint32_t SERCOM6_:1; /*!< bit: 2 SERCOM6 APB Clock Enable */ 183 uint32_t SERCOM7_:1; /*!< bit: 3 SERCOM7 APB Clock Enable */ 184 uint32_t TCC4_:1; /*!< bit: 4 TCC4 APB Clock Enable */ 185 uint32_t TC6_:1; /*!< bit: 5 TC6 APB Clock Enable */ 186 uint32_t TC7_:1; /*!< bit: 6 TC7 APB Clock Enable */ 187 uint32_t ADC0_:1; /*!< bit: 7 ADC0 APB Clock Enable */ 188 uint32_t ADC1_:1; /*!< bit: 8 ADC1 APB Clock Enable */ 189 uint32_t DAC_:1; /*!< bit: 9 DAC APB Clock Enable */ 190 uint32_t I2S_:1; /*!< bit: 10 I2S APB Clock Enable */ 191 uint32_t PCC_:1; /*!< bit: 11 PCC APB Clock Enable */ 192 uint32_t :20; /*!< bit: 12..31 Reserved */ 193 } bit; /*!< Structure used for bit access */ 194 uint32_t reg; /*!< Type used for register access */ 195 } MCLK_APBDMASK_Type; 196 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 197 198 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 199 typedef struct { 200 RoReg8 Reserved1[0x1]; 201 __IO MCLK_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x01 (R/W 8) Interrupt Enable Clear */ 202 __IO MCLK_INTENSET_Type INTENSET; /**< \brief Offset: 0x02 (R/W 8) Interrupt Enable Set */ 203 __IO MCLK_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x03 (R/W 8) Interrupt Flag Status and Clear */ 204 __I MCLK_HSDIV_Type HSDIV; /**< \brief Offset: 0x04 (R/ 8) HS Clock Division */ 205 __IO MCLK_CPUDIV_Type CPUDIV; /**< \brief Offset: 0x05 (R/W 8) CPU Clock Division */ 206 RoReg8 Reserved2[0xA]; 207 __IO MCLK_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x10 (R/W 32) AHB Mask */ 208 __IO MCLK_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x14 (R/W 32) APBA Mask */ 209 __IO MCLK_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x18 (R/W 32) APBB Mask */ 210 __IO MCLK_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x1C (R/W 32) APBC Mask */ 211 __IO MCLK_APBDMASK_Type APBDMASK; /**< \brief Offset: 0x20 (R/W 32) APBD Mask */ 212 } Mclk; 213 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 214 215 #endif /* _MICROCHIP_PIC32CXSG_MCLK_COMPONENT_FIXUP_H_ */ 216
