1 //***************************************************************************** 2 // 3 //! @file am_hal_pwrctrl_internal.h 4 //! 5 //! @brief Internal definitions for Power Control 6 //! 7 //! @addtogroup pwrctrl3 Pwrctrl - Power Control 8 //! @ingroup apollo3_hal 9 //! @{ 10 // 11 //***************************************************************************** 12 13 //***************************************************************************** 14 // 15 // Copyright (c) 2024, Ambiq Micro, Inc. 16 // All rights reserved. 17 // 18 // Redistribution and use in source and binary forms, with or without 19 // modification, are permitted provided that the following conditions are met: 20 // 21 // 1. Redistributions of source code must retain the above copyright notice, 22 // this list of conditions and the following disclaimer. 23 // 24 // 2. Redistributions in binary form must reproduce the above copyright 25 // notice, this list of conditions and the following disclaimer in the 26 // documentation and/or other materials provided with the distribution. 27 // 28 // 3. Neither the name of the copyright holder nor the names of its 29 // contributors may be used to endorse or promote products derived from this 30 // software without specific prior written permission. 31 // 32 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 33 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 36 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 37 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 38 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 39 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 40 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 41 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 42 // POSSIBILITY OF SUCH DAMAGE. 43 // 44 // This is part of revision release_sdk_3_2_0-dd5f40c14b of the AmbiqSuite Development Package. 45 // 46 //***************************************************************************** 47 48 #ifndef AM_HAL_PWRCTRL_INTERNAL_H 49 #define AM_HAL_PWRCTRL_INTERNAL_H 50 51 52 //***************************************************************************** 53 // 54 // Peripheral enable bits for am_hal_pwrctrl_periph_enable/disable() 55 // 56 //***************************************************************************** 57 #define AM_HAL_PWRCTRL_IOS (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOS, PWRCTRL_DEVPWREN_PWRIOS_EN)) 58 #define AM_HAL_PWRCTRL_IOM0 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM0, PWRCTRL_DEVPWREN_PWRIOM0_EN)) 59 #define AM_HAL_PWRCTRL_IOM1 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM1, PWRCTRL_DEVPWREN_PWRIOM1_EN)) 60 #define AM_HAL_PWRCTRL_IOM2 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM2, PWRCTRL_DEVPWREN_PWRIOM2_EN)) 61 #define AM_HAL_PWRCTRL_IOM3 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM3, PWRCTRL_DEVPWREN_PWRIOM3_EN)) 62 #define AM_HAL_PWRCTRL_IOM4 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM4, PWRCTRL_DEVPWREN_PWRIOM4_EN)) 63 #define AM_HAL_PWRCTRL_IOM5 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRIOM5, PWRCTRL_DEVPWREN_PWRIOM5_EN)) 64 #define AM_HAL_PWRCTRL_UART0 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRUART0, PWRCTRL_DEVPWREN_PWRUART0_EN)) 65 #define AM_HAL_PWRCTRL_UART1 (_VAL2FLD(PWRCTRL_DEVPWREN_PWRUART1, PWRCTRL_DEVPWREN_PWRUART1_EN)) 66 #define AM_HAL_PWRCTRL_ADC (_VAL2FLD(PWRCTRL_DEVPWREN_PWRADC, PWRCTRL_DEVPWREN_PWRADC_EN)) 67 #define AM_HAL_PWRCTRL_SCARD (_VAL2FLD(PWRCTRL_DEVPWREN_PWRSCARD, PWRCTRL_DEVPWREN_PWRSCARD_EN)) 68 #define AM_HAL_PWRCTRL_MSPI (_VAL2FLD(PWRCTRL_DEVPWREN_PWRMSPI, PWRCTRL_DEVPWREN_PWRMSPI_EN)) 69 #define AM_HAL_PWRCTRL_PDM (_VAL2FLD(PWRCTRL_DEVPWREN_PWRPDM, PWRCTRL_DEVPWREN_PWRPDM_EN)) 70 #define AM_HAL_PWRCTRL_BLEL (_VAL2FLD(PWRCTRL_DEVPWREN_PWRBLEL, PWRCTRL_DEVPWREN_PWRBLEL_EN)) 71 72 #define AM_HAL_PWRCTRL_DEVPWREN_MASK 0x00003FFF 73 #define AM_HAL_PWRCTRL_DEVPWRSTATUS_MASK 0x000003FC 74 75 //***************************************************************************** 76 // 77 // Memory enable values for all defined memory configurations. 78 // 79 //***************************************************************************** 80 #define AM_HAL_PWRCTRL_MEMEN_SRAM_8K_DTCM (_VAL2FLD(PWRCTRL_MEMPWREN_DTCM, PWRCTRL_MEMPWREN_DTCM_GROUP0DTCM0)) 81 #define AM_HAL_PWRCTRL_MEMEN_SRAM_32K_DTCM (_VAL2FLD(PWRCTRL_MEMPWREN_DTCM, PWRCTRL_MEMPWREN_DTCM_GROUP0)) 82 #define AM_HAL_PWRCTRL_MEMEN_SRAM_64K_DTCM (_VAL2FLD(PWRCTRL_MEMPWREN_DTCM, PWRCTRL_MEMPWREN_DTCM_ALL)) 83 #define AM_HAL_PWRCTRL_MEMEN_SRAM_96K \ 84 (AM_HAL_PWRCTRL_MEMEN_SRAM_64K_DTCM | \ 85 _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP0)) 86 #define AM_HAL_PWRCTRL_MEMEN_SRAM_128K \ 87 (AM_HAL_PWRCTRL_MEMEN_SRAM_96K | \ 88 _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP1)) 89 #define AM_HAL_PWRCTRL_MEMEN_SRAM_160K \ 90 (AM_HAL_PWRCTRL_MEMEN_SRAM_128K | \ 91 _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP2)) 92 #define AM_HAL_PWRCTRL_MEMEN_SRAM_192K \ 93 (AM_HAL_PWRCTRL_MEMEN_SRAM_160K | \ 94 _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP3)) 95 #define AM_HAL_PWRCTRL_MEMEN_SRAM_224K \ 96 (AM_HAL_PWRCTRL_MEMEN_SRAM_192K | \ 97 _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP4)) 98 #define AM_HAL_PWRCTRL_MEMEN_SRAM_256K \ 99 (AM_HAL_PWRCTRL_MEMEN_SRAM_224K | \ 100 _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP5)) 101 #define AM_HAL_PWRCTRL_MEMEN_SRAM_288K \ 102 (AM_HAL_PWRCTRL_MEMEN_SRAM_256K | \ 103 _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP6)) 104 #define AM_HAL_PWRCTRL_MEMEN_SRAM_320K \ 105 (AM_HAL_PWRCTRL_MEMEN_SRAM_288K | \ 106 _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP7)) 107 #define AM_HAL_PWRCTRL_MEMEN_SRAM_352K \ 108 (AM_HAL_PWRCTRL_MEMEN_SRAM_320K | \ 109 _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP8)) 110 #define AM_HAL_PWRCTRL_MEMEN_SRAM_384K \ 111 (AM_HAL_PWRCTRL_MEMEN_SRAM_352K | \ 112 _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_GROUP9)) 113 114 #define AM_HAL_PWRCTRL_MEMEN_SRAM_ALL (AM_HAL_PWRCTRL_MEMEN_SRAM_384K) 115 #define AM_HAL_PWRCTRL_MEMEN_FLASH_512K PWRCTRL_MEMPWREN_FLASH0_Msk 116 #define AM_HAL_PWRCTRL_MEMEN_FLASH_1M \ 117 (PWRCTRL_MEMPWREN_FLASH0_Msk | PWRCTRL_MEMPWREN_FLASH1_Msk) 118 #define AM_HAL_PWRCTRL_MEMEN_CACHE \ 119 (PWRCTRL_MEMPWREN_CACHEB0_Msk | PWRCTRL_MEMPWREN_CACHEB2_Msk) 120 #define AM_HAL_PWRCTRL_MEMEN_CACHE_DIS (~AM_HAL_PWRCTRL_MEMEN_CACHE) 121 122 // 123 // Power up all available memory devices (this is the default power up state) 124 // 125 #define AM_HAL_PWRCTRL_MEMEN_ALL \ 126 (_VAL2FLD(PWRCTRL_MEMPWREN_DTCM, PWRCTRL_MEMPWREN_DTCM_ALL) | \ 127 _VAL2FLD(PWRCTRL_MEMPWREN_SRAM, PWRCTRL_MEMPWREN_SRAM_ALL) | \ 128 _VAL2FLD(PWRCTRL_MEMPWREN_FLASH0, PWRCTRL_MEMPWREN_FLASH0_EN) | \ 129 _VAL2FLD(PWRCTRL_MEMPWREN_FLASH1, PWRCTRL_MEMPWREN_FLASH1_EN) | \ 130 _VAL2FLD(PWRCTRL_MEMPWREN_CACHEB0, PWRCTRL_MEMPWREN_CACHEB0_EN) | \ 131 _VAL2FLD(PWRCTRL_MEMPWREN_CACHEB2, PWRCTRL_MEMPWREN_CACHEB2_EN)) 132 133 //***************************************************************************** 134 // 135 // Memory deepsleep powerdown values for all defined memory configurations. 136 // 137 //***************************************************************************** 138 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_8K_DTCM (_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP, PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP0DTCM0)) 139 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_32K_DTCM (_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP, PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP0)) 140 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_64K_DTCM (_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP, PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_ALL)) 141 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_96K \ 142 (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_64K_DTCM | \ 143 _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP0)) 144 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_128K \ 145 (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_96K | \ 146 _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP1)) 147 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_160K \ 148 (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_128K | \ 149 _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP2)) 150 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_192K \ 151 (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_160K | \ 152 _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP3)) 153 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_224K \ 154 (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_192K | \ 155 _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP4)) 156 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_256K \ 157 (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_224K | \ 158 _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP5)) 159 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_288K \ 160 (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_256K | \ 161 _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP6)) 162 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_320K \ 163 (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_288K | \ 164 _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP7)) 165 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_352K \ 166 (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_320K | \ 167 _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP8)) 168 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_384K \ 169 (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_352K | \ 170 _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP9)) 171 172 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_ALL (AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_384K) 173 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_FLASH_512K PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_Msk 174 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_FLASH_1M \ 175 (PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_Msk | PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_Msk) 176 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_CACHE (PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_Msk) 177 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_CACHE_DIS (~AM_HAL_PWRCTRL_MEMPWDINSLEEP_CACHE) 178 179 // 180 // Power down all available memory devices 181 // 182 #define AM_HAL_PWRCTRL_MEMPWDINSLEEP_ALL \ 183 (_VAL2FLD(PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP, PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_ALL) | \ 184 _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP, PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_ALL) | \ 185 _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP, PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_EN) | \ 186 _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP, PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_EN) | \ 187 _VAL2FLD(PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP, PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_EN)) 188 189 //***************************************************************************** 190 // 191 // Memory status values for all defined memory configurations 192 // 193 //***************************************************************************** 194 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_8K_DTCM \ 195 (PWRCTRL_MEMPWRSTATUS_DTCM00_Msk) 196 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_32K_DTCM \ 197 (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_8K_DTCM | \ 198 PWRCTRL_MEMPWRSTATUS_DTCM01_Msk) 199 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_64K_DTCM \ 200 (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_32K_DTCM | \ 201 PWRCTRL_MEMPWRSTATUS_DTCM1_Msk) 202 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_96K \ 203 (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_64K_DTCM | \ 204 PWRCTRL_MEMPWRSTATUS_SRAM0_Msk) 205 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_128K \ 206 (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_96K | \ 207 PWRCTRL_MEMPWRSTATUS_SRAM1_Msk) 208 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_160K \ 209 (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_128K | \ 210 PWRCTRL_MEMPWRSTATUS_SRAM2_Msk) 211 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_192K \ 212 (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_160K | \ 213 PWRCTRL_MEMPWRSTATUS_SRAM3_Msk) 214 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_224K \ 215 (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_192K | \ 216 PWRCTRL_MEMPWRSTATUS_SRAM4_Msk) 217 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K \ 218 (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_224K | \ 219 PWRCTRL_MEMPWRSTATUS_SRAM5_Msk) 220 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_288K \ 221 (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K | \ 222 PWRCTRL_MEMPWRSTATUS_SRAM6_Msk) 223 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_320K \ 224 (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_288K | \ 225 PWRCTRL_MEMPWRSTATUS_SRAM7_Msk) 226 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_352K \ 227 (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_320K | \ 228 PWRCTRL_MEMPWRSTATUS_SRAM8_Msk) 229 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_384K \ 230 (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_352K | \ 231 PWRCTRL_MEMPWRSTATUS_SRAM9_Msk) 232 #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL \ 233 (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_384K) 234 #define AM_HAL_PWRCTRL_PWRONSTATUS_FLASH_512K \ 235 (PWRCTRL_MEMPWRSTATUS_FLASH0_Msk) 236 #define AM_HAL_PWRCTRL_PWRONSTATUS_FLASH_1M \ 237 (AM_HAL_PWRCTRL_PWRONSTATUS_FLASH_512K | \ 238 PWRCTRL_MEMPWRSTATUS_FLASH1_Msk) 239 #define AM_HAL_PWRCTRL_PWRONSTATUS_ALL \ 240 (AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_384K | \ 241 AM_HAL_PWRCTRL_PWRONSTATUS_FLASH_1M) 242 243 //***************************************************************************** 244 // 245 // Memory event values for all defined memory configurations 246 // 247 //***************************************************************************** 248 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_8K_DTCM \ 249 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_DTCMEN, \ 250 PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0DTCM0EN)) 251 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_32K_DTCM \ 252 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_DTCMEN, \ 253 PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0EN)) 254 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_64K_DTCM \ 255 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_DTCMEN, \ 256 PWRCTRL_MEMPWREVENTEN_DTCMEN_ALL)) 257 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_96K \ 258 ((_VAL2FLD(PWRCTRL_MEMPWREVENTEN_DTCMEN, \ 259 PWRCTRL_MEMPWREVENTEN_DTCMEN_ALL)) | \ 260 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ 261 PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP0EN))) 262 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_128K \ 263 (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_96K | \ 264 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ 265 PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP1EN))) 266 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_160K \ 267 (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_128K | \ 268 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ 269 PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP2EN))) 270 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_192K \ 271 (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_160K | \ 272 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ 273 PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP3EN))) 274 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_224K \ 275 (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_192K | \ 276 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ 277 PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP4EN))) 278 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_256K \ 279 (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_224K | \ 280 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ 281 PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP5EN))) 282 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_288K \ 283 (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_256K | \ 284 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ 285 PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP6EN))) 286 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_320K \ 287 (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_288K | \ 288 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ 289 PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP7EN))) 290 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_352K \ 291 (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_320K | \ 292 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ 293 PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP8EN))) 294 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_384K \ 295 (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_352K | \ 296 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_SRAMEN, \ 297 PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP9EN))) 298 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_FLASH_512K \ 299 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_FLASH0EN, \ 300 PWRCTRL_MEMPWREVENTEN_FLASH0EN_EN)) 301 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_FLASH_1M \ 302 (AM_HAL_PWRCTRL_MEMPWREVENTEN_FLASH_512K | \ 303 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_FLASH1EN, \ 304 PWRCTRL_MEMPWREVENTEN_FLASH1EN_EN))) 305 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_CACHE \ 306 ((_VAL2FLD(PWRCTRL_MEMPWREVENTEN_CACHEB0EN, \ 307 PWRCTRL_MEMPWREVENTEN_CACHEB0EN_EN)) | \ 308 (_VAL2FLD(PWRCTRL_MEMPWREVENTEN_CACHEB2EN, \ 309 PWRCTRL_MEMPWREVENTEN_CACHEB2EN_EN))) 310 #define AM_HAL_PWRCTRL_MEMPWREVENTEN_ALL \ 311 (AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_384K | \ 312 AM_HAL_PWRCTRL_MEMPWREVENTEN_FLASH_1M | \ 313 AM_HAL_PWRCTRL_MEMPWREVENTEN_CACHE) 314 315 //***************************************************************************** 316 // 317 // Memory region mask values for all defined memory configurations 318 // 319 //***************************************************************************** 320 #define AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK AM_HAL_PWRCTRL_MEMEN_SRAM_ALL 321 #define AM_HAL_PWRCTRL_MEM_REGION_FLASH_MASK AM_HAL_PWRCTRL_MEMEN_FLASH_1M 322 #define AM_HAL_PWRCTRL_MEM_REGION_CACHE_MASK AM_HAL_PWRCTRL_MEMEN_CACHE 323 #define AM_HAL_PWRCTRL_MEM_REGION_ALT_CACHE_MASK AM_HAL_PWRCTRL_PWRONSTATUS_CACHE 324 #define AM_HAL_PWRCTRL_MEM_REGION_ALL_MASK AM_HAL_PWRCTRL_MEMEN_ALL 325 #define AM_HAL_PWRCTRL_MEM_REGION_ALT_ALL_MASK AM_HAL_PWRCTRL_PWRONSTATUS_ALL 326 327 328 #endif // AM_HAL_PWRCTRL_INTERNAL_H 329 330 //***************************************************************************** 331 // 332 // End Doxygen group. 333 //! @} 334 // 335 //***************************************************************************** 336
