1 //***************************************************************************** 2 // 3 //! @file am_hal_i2s.h 4 //! 5 //! @brief HAL implementation for the Inter-IC Sound module. 6 //! 7 //! @addtogroup i2s4_4p I2S - Inter-IC Sound 8 //! @ingroup apollo4p_hal 9 //! @{ 10 // 11 //***************************************************************************** 12 13 //***************************************************************************** 14 // 15 // Copyright (c) 2023, Ambiq Micro, Inc. 16 // All rights reserved. 17 // 18 // Redistribution and use in source and binary forms, with or without 19 // modification, are permitted provided that the following conditions are met: 20 // 21 // 1. Redistributions of source code must retain the above copyright notice, 22 // this list of conditions and the following disclaimer. 23 // 24 // 2. Redistributions in binary form must reproduce the above copyright 25 // notice, this list of conditions and the following disclaimer in the 26 // documentation and/or other materials provided with the distribution. 27 // 28 // 3. Neither the name of the copyright holder nor the names of its 29 // contributors may be used to endorse or promote products derived from this 30 // software without specific prior written permission. 31 // 32 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 33 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 36 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 37 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 38 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 39 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 40 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 41 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 42 // POSSIBILITY OF SUCH DAMAGE. 43 // 44 // This is part of revision release_sdk_4_4_0-3c5977e664 of the AmbiqSuite Development Package. 45 // 46 //***************************************************************************** 47 #ifndef AM_HAL_I2S_H 48 #define AM_HAL_I2S_H 49 50 #ifdef __cplusplus 51 extern "C" 52 { 53 #endif 54 55 //***************************************************************************** 56 // 57 //! CMSIS-style macro for handling a variable I2S module number. 58 // 59 //***************************************************************************** 60 #define I2Sn(n) ((I2S0_Type*)(I2S0_BASE + (n * (I2S1_BASE - I2S0_BASE)))) 61 62 //***************************************************************************** 63 // 64 //! @name I2S Specific status codes 65 //! @{ 66 // 67 //***************************************************************************** 68 #define AM_HAL_I2S_POWER_ON AM_HAL_SYSCTRL_WAKE 69 #define AM_HAL_I2S_POWER_OFF AM_HAL_SYSCTRL_NORMALSLEEP 70 //! @} 71 72 // 73 //! The FIFO size for both the TX and RX FIFOs is 64 samples. 74 // 75 #define AM_HAL_I2S_FIFO_SIZE 64 76 77 //***************************************************************************** 78 // 79 //! I2S internal clock speed selection. 80 // 81 //***************************************************************************** 82 typedef enum 83 { 84 eAM_HAL_I2S_CLKSEL_HFRC2_48MHz = 0, 85 eAM_HAL_I2S_CLKSEL_HFRC2_24MHz, 86 eAM_HAL_I2S_CLKSEL_HFRC2_12MHz, 87 eAM_HAL_I2S_CLKSEL_HFRC2_6MHz, 88 eAM_HAL_I2S_CLKSEL_HFRC2_3MHz, 89 eAM_HAL_I2S_CLKSEL_HFRC2_1_5MHz, 90 eAM_HAL_I2S_CLKSEL_HFRC2_750KHz, 91 eAM_HAL_I2S_CLKSEL_HFRC2_375KHz, 92 93 eAM_HAL_I2S_CLKSEL_HFRC_24MHz, 94 eAM_HAL_I2S_CLKSEL_HFRC_12MHz, 95 eAM_HAL_I2S_CLKSEL_HFRC_6MHz, 96 eAM_HAL_I2S_CLKSEL_HFRC_3MHz, 97 eAM_HAL_I2S_CLKSEL_HFRC_1_5MHz, 98 eAM_HAL_I2S_CLKSEL_HFRC_750KHz, 99 eAM_HAL_I2S_CLKSEL_HFRC_375KHz, 100 101 eAM_HAL_I2S_CLKSEL_XTHS_EXTREF_CLK, 102 eAM_HAL_I2S_CLKSEL_XTHS_16MHz, 103 eAM_HAL_I2S_CLKSEL_XTHS_8MHz, 104 eAM_HAL_I2S_CLKSEL_XTHS_4MHz, 105 eAM_HAL_I2S_CLKSEL_XTHS_2MHz, 106 eAM_HAL_I2S_CLKSEL_XTHS_1MHz, 107 eAM_HAL_I2S_CLKSEL_XTHS_500KHz, 108 eAM_HAL_I2S_CLKSEL_MAX 109 } am_hal_i2s_clksel_e; 110 111 //***************************************************************************** 112 // 113 //! @name I2S interrupts macros 114 //! @{ 115 // 116 //***************************************************************************** 117 #define AM_HAL_I2S_INT_RXDMACPL I2S0_INTSTAT_RXDMACPL_Msk 118 #define AM_HAL_I2S_INT_TXDMACPL I2S0_INTSTAT_TXDMACPL_Msk 119 #define AM_HAL_I2S_INT_TXREQCNT I2S0_INTSTAT_TXREQCNT_Msk 120 #define AM_HAL_I2S_INT_RXREQCNT I2S0_INTSTAT_RXREQCNT_Msk 121 #define AM_HAL_I2S_INT_IPB I2S0_INTSTAT_IPB_Msk 122 123 #define AM_HAL_I2S_STAT_DMA_TX_ERR I2S0_TXDMASTAT_TXDMAERR_Msk 124 #define AM_HAL_I2S_STAT_DMA_RX_ERR I2S0_TXDMASTAT_TXDMAERR_Msk 125 126 #define AM_HAL_I2S_INT_IPBIRPT_TXDMA I2S0_IPBIRPT_TXDMAM_Msk 127 #define AM_HAL_I2S_INT_IPBIRPT_RXDMA I2S0_IPBIRPT_RXDMAM_Msk 128 #define AM_HAL_I2S_INT_IPBIRPT_TXE I2S0_IPBIRPT_TXEM_Msk 129 #define AM_HAL_I2S_INT_IPBIRPT_RXF I2S0_IPBIRPT_RXFM_Msk 130 #define AM_HAL_I2S_INT_IPBIRPT_TXFF I2S0_IPBIRPT_TXFFM_Msk 131 #define AM_HAL_I2S_INT_IPBIRPT_RXFF I2S0_IPBIRPT_RXFFM_Msk 132 133 // 134 //! @} 135 // 136 137 //***************************************************************************** 138 // 139 // General defines 140 // 141 //***************************************************************************** 142 143 //***************************************************************************** 144 // 145 //! @brief enumeration types for the I2S. 146 // 147 //***************************************************************************** 148 typedef enum 149 { 150 AM_HAL_I2S_REQ_INTSET = 0, 151 AM_HAL_I2S_REQ_INTCLR, 152 AM_HAL_I2S_REQ_TXFIFOCNT, 153 AM_HAL_I2S_REQ_READ_RXUPPERLIMIT, 154 AM_HAL_I2S_REQ_READ_TXLOWERLIMIT, 155 AM_HAL_I2S_REQ_WRITE_RXUPPERLIMIT, 156 AM_HAL_I2S_REQ_WRITE_TXLOWERLIMIT, 157 AM_HAL_I2S_REQ_MAX 158 } am_hal_i2s_request_e; 159 160 //***************************************************************************** 161 // 162 //! @brief enumeration types for the I2S clock selection. 163 // 164 //***************************************************************************** 165 typedef enum 166 { 167 //! no change to the clock selected by FSEL. 168 AM_HAL_I2S_CLKDIV_1 = 0, 169 170 //! frequency divide-by-3 of the clock selected by FSEL. 171 AM_HAL_I2S_CLKDIV_3 = 1 172 } am_hal_i2s_clk_div_e; 173 174 //***************************************************************************** 175 // 176 //! @name I2S Available word length/fsync period 177 //! @{ 178 // 179 //***************************************************************************** 180 #define AM_HAL_I2S_WORD_8BITS 8 181 #define AM_HAL_I2S_WORD_16BITS 16 182 #define AM_HAL_I2S_WORD_24BITS 24 183 #define AM_HAL_I2S_WORD_32BITS 32 184 #define AM_HAL_I2S_WORD_RESERVED 0 185 // 186 //! @} 187 // 188 189 //***************************************************************************** 190 // 191 //! I2S Channel Length 192 // 193 //***************************************************************************** 194 typedef enum 195 { 196 AM_HAL_I2S_FRAME_WDLEN_8BITS = I2S0_I2SDATACFG_WDLEN1_8b, 197 AM_HAL_I2S_FRAME_WDLEN_16BITS = I2S0_I2SDATACFG_WDLEN1_16b, 198 AM_HAL_I2S_FRAME_WDLEN_24BITS = I2S0_I2SDATACFG_WDLEN1_24b, 199 AM_HAL_I2S_FRAME_WDLEN_32BITS = I2S0_I2SDATACFG_WDLEN1_32b, 200 AM_HAL_I2S_FRAME_WDLEN_MAX, 201 } am_hal_i2s_channel_length_e; 202 203 //***************************************************************************** 204 // 205 //! I2S Sample Length 206 // 207 //***************************************************************************** 208 typedef enum 209 { 210 AM_HAL_I2S_SAMPLE_LENGTH_8BITS = I2S0_I2SDATACFG_SSZ1_8b, 211 AM_HAL_I2S_SAMPLE_LENGTH_16BITS = I2S0_I2SDATACFG_SSZ1_16b, 212 AM_HAL_I2S_SAMPLE_LENGTH_24BITS = I2S0_I2SDATACFG_SSZ1_24b, 213 AM_HAL_I2S_SAMPLE_LENGTH_32BITS = I2S0_I2SDATACFG_SSZ1_32b 214 } am_hal_i2s_sample_length_e; 215 216 // 217 //! Available frame size. 218 // 219 static const uint32_t ui32I2sWordLength[AM_HAL_I2S_FRAME_WDLEN_MAX] = 220 { 221 AM_HAL_I2S_WORD_8BITS, 222 AM_HAL_I2S_WORD_RESERVED, 223 AM_HAL_I2S_WORD_16BITS, 224 AM_HAL_I2S_WORD_RESERVED, 225 AM_HAL_I2S_WORD_24BITS, 226 AM_HAL_I2S_WORD_32BITS 227 }; 228 229 //***************************************************************************** 230 // 231 //! Specifies the data format of I2S sub frames 232 //! I2SDATACFG @0x00000040 233 //! 234 //! Read Phase Bit. 0: Single Phase frame; 1: Dual-Phase frame. 235 // 236 //***************************************************************************** 237 typedef enum 238 { 239 AM_HAL_I2S_DATA_PHASE_SINGLE, 240 AM_HAL_I2S_DATA_PHASE_DUAL 241 } am_hal_i2s_data_phase_e; 242 243 //***************************************************************************** 244 // 245 //! Audio sample justification. 0: Left-justified, 1: Right-justified 246 // 247 //***************************************************************************** 248 typedef enum 249 { 250 AM_HAL_I2S_DATA_JUSTIFIED_LEFT, 251 AM_HAL_I2S_DATA_JUSTIFIED_RIGHT 252 } am_hal_i2s_data_justified_e; 253 254 //***************************************************************************** 255 // 256 //! @name Specified polarity and clock configuration of the I2S IPB clocks and 257 //! IO signals 258 //! REGISTER OFFSET: 0x44 259 //! 260 //! @{ 261 // 262 typedef enum 263 { 264 AM_HAL_I2S_IO_MODE_SLAVE, 265 AM_HAL_I2S_IO_MODE_MASTER 266 } am_hal_i2s_io_mode_e; 267 268 typedef enum 269 { 270 AM_HAL_I2S_IO_SDATA_OUTPUT_DISABLE, 271 AM_HAL_I2S_IO_SDATA_OUTPUT_ENABLE 272 } am_hal_i2s_io_sdata_output_e; 273 274 typedef enum 275 { 276 AM_HAL_I2S_IO_RX_CPOL_RISING, 277 AM_HAL_I2S_IO_RX_CPOL_FALLING 278 } am_hal_i2s_io_rx_cpol_e; 279 280 typedef enum 281 { 282 AM_HAL_I2S_IO_TX_CPOL_FALLING, 283 AM_HAL_I2S_IO_TX_CPOL_RISING 284 } am_hal_i2s_io_tx_cpol_e; 285 286 typedef enum 287 { 288 AM_HAL_I2S_IO_FSYNC_CPOL_HIGH, 289 AM_HAL_I2S_IO_FSYNC_CPOL_LOW 290 } am_hal_i2s_io_fsync_cpol_e; 291 292 typedef enum 293 { 294 AM_HAL_I2S_XFER_RX, 295 AM_HAL_I2S_XFER_TX, 296 AM_HAL_I2S_XFER_RXTX 297 } am_hal_i2s_xfer_dir_e; 298 //! @} 299 300 //***************************************************************************** 301 // 302 //! @brief Configuration structure for the I2S/TDM Data format. 303 // 304 //***************************************************************************** 305 typedef struct 306 { 307 // 308 //! PH: Read Phase Bit. 0: Single Phase frame; 1: Dual-Phase frame. 309 // 310 am_hal_i2s_data_phase_e ePhase; 311 312 // 313 //! FRLEN1: Number of channels in phase 1: N+1 314 // 315 uint32_t ui32ChannelNumbersPhase1; 316 317 // 318 //! FRLEN2: Number of channels in phase 2: N+1 319 // 320 uint32_t ui32ChannelNumbersPhase2; 321 322 // 323 //! WDLEN1: channel length in bits for phase 1 324 //! 0: 8b,1: 12b, 2: 16b, 3: 20b, 4: 24b, 5: 32b. 325 // 326 am_hal_i2s_channel_length_e eChannelLenPhase1; 327 328 // 329 //! WDLEN2: channel length in bits for phase 2 330 // 331 am_hal_i2s_channel_length_e eChannelLenPhase2; 332 333 // 334 //! DATADLY: Receive data delay bit count. Valid values are 0-2 335 // 336 uint32_t eDataDelay; 337 338 // 339 //! SSZ1: Receive audio sample length for phase 1. 0: 8b, 1: 12b, 2: 16b, 3: 20b, 4: 24b, 5: 32b. 340 // 341 am_hal_i2s_sample_length_e eSampleLenPhase1; 342 343 // 344 //! SSZ2: Receive audio sample length for phase 2. 0: 8b, 1: 12b, 2: 16b, 3: 20b, 4: 24b, 5: 32b. 345 // 346 am_hal_i2s_sample_length_e eSampleLenPhase2; 347 348 // 349 //! JUST: Audio sample justification. 0: Left-justified, 1: Right-justified 350 // 351 am_hal_i2s_data_justified_e eDataJust; 352 } am_hal_i2s_data_format_t; 353 354 //***************************************************************************** 355 // 356 //! @brief Configuration structure for the I2S IPB clocks and IO signals. 357 // 358 //***************************************************************************** 359 typedef struct 360 { 361 // 362 //! MSL: Master/Slave configuration. 0: External clock. 1: Internal clock. 363 // 364 //am_hal_i2s_io_mode_e eMode; 365 366 // 367 //! OEN: Output enable for SDATA output 368 // 369 am_hal_i2s_io_sdata_output_e eOutput; 370 371 // 372 //! FPER: Frame period in units of sclk. (N+1) in length 373 // 374 uint32_t eFramecPeriod; 375 376 // 377 //! FWID: period of fsync/lr_clk in units of sclks 378 // 379 uint32_t eFsyncPeriod; 380 381 // 382 //! FSP: Polarity of fsync/lr_clk signal. 0: Active high. 1: Active low 383 // 384 am_hal_i2s_io_fsync_cpol_e eFyncCpol; 385 386 // 387 //! PRx/CLKP: Receive clock edge polarity bit. 0: rising edge. 1: falling edge. 388 // 389 am_hal_i2s_io_rx_cpol_e eRxCpol; 390 391 // 392 //! PRTX: Transmit clock edge polarity bit. 0: sdata starting from the falling edge. 1: sdata starting from the rising edge. 393 // 394 am_hal_i2s_io_tx_cpol_e eTxCpol; 395 } am_hal_i2s_io_signal_t; 396 397 //***************************************************************************** 398 // 399 //! DMA transfer structure 400 // 401 //***************************************************************************** 402 typedef struct 403 { 404 uint32_t ui32RxTargetAddr; 405 uint32_t ui32RxTargetAddrReverse; 406 uint32_t ui32RxTotalCount; 407 408 uint32_t ui32TxTargetAddr; 409 uint32_t ui32TxTargetAddrReverse; 410 uint32_t ui32TxTotalCount; 411 } am_hal_i2s_transfer_t; 412 413 //***************************************************************************** 414 // 415 //! @brief Configuration structure for the I2S. 416 // 417 //***************************************************************************** 418 typedef struct 419 { 420 // 421 //! User setting. 422 // 423 am_hal_i2s_io_mode_e eMode; 424 am_hal_i2s_xfer_dir_e eXfer; 425 426 am_hal_i2s_clksel_e eClock; 427 uint32_t eDiv3; 428 uint32_t eASRC; 429 430 // 431 //! I2S data format. 432 // 433 am_hal_i2s_data_format_t* eData; 434 435 // 436 //! I2S signal io. 437 // 438 am_hal_i2s_io_signal_t* eIO; 439 440 // 441 //! DMA transfer. 442 // 443 am_hal_i2s_transfer_t* eTransfer; 444 } am_hal_i2s_config_t; 445 446 //***************************************************************************** 447 // 448 // Functions 449 // 450 //***************************************************************************** 451 //***************************************************************************** 452 // 453 //! @brief initialize the I2S device controller 454 //! 455 //! @param ui32Module - the index to the I2S 456 //! @param ppHandle - pointer the handle of initialized I2S instance 457 //! 458 //! This function should be called firstly before we use any other I2S HAL driver 459 //! functions. 460 //! 461 //! @return status - generic or interface specific status. 462 // 463 //***************************************************************************** 464 extern uint32_t am_hal_i2s_initialize(uint32_t ui32Module, void **ppHandle); 465 466 //***************************************************************************** 467 // 468 //! @brief Uninitialize the I2S device controller 469 //! 470 //! @param pHandle - the handle of initialized I2S instance 471 //! 472 //! @return status - generic or interface specific status. 473 // 474 //***************************************************************************** 475 extern uint32_t am_hal_i2s_deinitialize(void *pHandle); 476 477 //***************************************************************************** 478 // 479 //! @brief I2S Power control function. function 480 //! 481 //! @param pHandle - handle for the I2S. 482 //! @param ePowerState - power state requested 483 //! @param bRetainState - boolean on whether to retain state 484 //! 485 //! This function allows advanced settings 486 //! 487 //! @return status - generic or interface specific status. 488 // 489 //***************************************************************************** 490 extern uint32_t am_hal_i2s_power_control(void *pHandle, am_hal_sysctrl_power_state_e ePowerState, bool bRetainState); 491 492 //***************************************************************************** 493 // 494 //! @brief I2S configuration function 495 //! 496 //! @param pHandle - handle for the module instance. 497 //! @param psConfig - pointer to the configuration structure. 498 //! 499 //! This function configures the I2S for operation. 500 //! 501 //! @return status - generic or interface specific status. 502 // 503 //***************************************************************************** 504 extern uint32_t am_hal_i2s_configure(void *pHandle, am_hal_i2s_config_t *psConfig); 505 506 //***************************************************************************** 507 // 508 //! @brief I2S enable function 509 //! 510 //! @param pHandle - handle for the module instance. 511 //! 512 //! This function enables the I2S operation. 513 //! 514 //! @return status - generic or interface specific status. 515 // 516 //***************************************************************************** 517 518 extern uint32_t am_hal_i2s_enable(void *pHandle); 519 520 //***************************************************************************** 521 // 522 //! @brief I2S disable function 523 //! 524 //! @param pHandle - handle for the module instance. 525 //! 526 //! This function disables the I2S operation. 527 //! 528 //! @return status - generic or interface specific status. 529 // 530 //***************************************************************************** 531 extern uint32_t am_hal_i2s_disable(void *pHandle); 532 533 //***************************************************************************** 534 // 535 //! @brief I2S Interrupt Service Routine 536 //! 537 //! @param pHandle - handle for the module instance. 538 //! @param ui32IntMask - uint32_t for interrupts to clear 539 //! @param psConfig - Pointer to the I2S Config 540 //! 541 //! @return AM_HAL_STATUS_SUCCESS 542 // 543 //***************************************************************************** 544 extern uint32_t am_hal_i2s_interrupt_service(void *pHandle, uint32_t ui32IntMask, am_hal_i2s_config_t* psConfig); 545 546 //***************************************************************************** 547 // 548 //! @brief I2S IPB Interrupt Service Routine 549 //! 550 //! This function is currently called internal to am_hal_i2s_interrupt_service 551 //! IRB -> full-duplex I2S (stereo TX + stereo RX) using shared CLK & FS 552 //! 553 //! @param pHandle - handle for the module instance. 554 //! 555 //! @return AM_HAL_STATUS_SUCCESS 556 // 557 //***************************************************************************** 558 extern uint32_t am_hal_i2s_ipb_interrupt_service(void *pHandle); 559 560 //***************************************************************************** 561 // 562 //! @brief I2S interrupt status function 563 //! 564 //! @param pHandle - handle for the interface. 565 //! @param pui32Status - pointer to status 566 //! @param bEnabledOnly - if I2S enabled 567 //! 568 //! This function returns the specific indicated interrupt status. 569 //! 570 //! @return status - generic or interface specific status. 571 // 572 //***************************************************************************** 573 extern uint32_t am_hal_i2s_interrupt_status_get(void *pHandle, uint32_t *pui32Status, bool bEnabledOnly); 574 575 //***************************************************************************** 576 // 577 //! @brief I2S interrupt clear 578 //! 579 //! @param pHandle - handle for the interface. 580 //! @param ui32IntMask - uint32_t for interrupts to clear 581 //! 582 //! This function clears the interrupts for the given peripheral. 583 //! 584 //! @return status - generic or interface specific status. 585 // 586 //***************************************************************************** 587 extern uint32_t am_hal_i2s_interrupt_clear(void *pHandle, uint32_t ui32IntMask); 588 589 //***************************************************************************** 590 // 591 //! @brief I2S disable interrupts function 592 //! 593 //! @param pHandle - handle for the interface. 594 //! @param ui32IntMask - I2S interrupt mask. 595 //! 596 //! This function disable the specific indicated interrupts. 597 //! 598 //! @return status - generic or interface specific status. 599 // 600 //***************************************************************************** 601 extern uint32_t am_hal_i2s_interrupt_disable(void *pHandle, uint32_t ui32IntMask); 602 603 //***************************************************************************** 604 // 605 //! @brief I2S DMA Complete 606 //! 607 //! Gets the DMA status(TXMDASTAT/RXDMASTAT) 608 //! 609 //! @param pHandle - handle for the interface. 610 //! @param pui32Status - Pointer to the DMA Status 611 //! @param xfer - Type of DMA Transfer 612 //! 613 //! @return AM_HAL_STATUS_SUCCESS 614 // 615 //***************************************************************************** 616 extern uint32_t am_hal_i2s_dma_status_get(void *pHandle, uint32_t *pui32Status, am_hal_i2s_xfer_dir_e xfer); 617 618 //***************************************************************************** 619 // 620 //! @brief I2S DMA Transaction Configuration 621 //! 622 //! Gets the DMA status(TXMDASTAT/RXDMASTAT) 623 //! 624 //! @param pHandle - handle for the interface. 625 //! @param psConfig - Pointer to the I2S Config 626 //! @param pTransferCfg - Pointer to the I2S Transaction Config 627 //! 628 //! @return AM_HAL_STATUS_SUCCESS 629 // 630 //***************************************************************************** 631 extern uint32_t am_hal_i2s_dma_configure(void *pHandle, am_hal_i2s_config_t* psConfig, am_hal_i2s_transfer_t *pTransferCfg); 632 633 //***************************************************************************** 634 // 635 //! @brief I2S DMA NonBlocking Transfer Start 636 //! 637 //! Gets the DMA status(TXMDASTAT/RXDMASTAT) 638 //! 639 //! @param pHandle - handle for the interface. 640 //! @param pConfig - Pointer to the I2S Config 641 //! 642 //! @return status - generic or interface specific status. 643 // 644 //***************************************************************************** 645 extern uint32_t am_hal_i2s_dma_transfer_start(void *pHandle, am_hal_i2s_config_t *pConfig); 646 647 //***************************************************************************** 648 // 649 //! @brief I2S DMA NonBlocking Transfer Continue 650 //! 651 //! Gets the DMA status(TXMDASTAT/RXDMASTAT) 652 //! 653 //! @param pHandle - handle for the interface. 654 //! @param psConfig - Pointer to the I2S Config 655 //! @param pTransferCfg - Pointer to the I2S Transaction Config 656 //! 657 //! @return status - generic or interface specific status. 658 // 659 //***************************************************************************** 660 extern uint32_t am_hal_i2s_dma_transfer_continue(void *pHandle, am_hal_i2s_config_t* psConfig, am_hal_i2s_transfer_t *pTransferCfg); 661 662 //***************************************************************************** 663 // 664 //! @brief I2S DMA Complete 665 //! 666 //! Complete DMA Transfer by writing the DMACFG register to 0 and clearing the 667 //! DMA TX/RX status register. 668 //! 669 //! @param pHandle - handle for the interface. 670 //! 671 //! @return AM_HAL_STATUS_SUCCESS 672 // 673 //***************************************************************************** 674 extern uint32_t am_hal_i2s_dma_transfer_complete(void *pHandle); 675 676 //***************************************************************************** 677 // 678 //! @brief I2S DMA Get Buffer 679 //! 680 //! @param pHandle - handle for the interface. 681 //! @param xfer - Type of DMA Transfer 682 //! 683 //! @return Pointer to the DMA Buffer 684 // 685 //***************************************************************************** 686 extern uint32_t am_hal_i2s_dma_get_buffer(void *pHandle, am_hal_i2s_xfer_dir_e xfer); 687 688 //***************************************************************************** 689 // 690 //! @brief I2S DMA Error Check 691 //! 692 //! @param pHandle - handle for the interface. 693 //! @param xfer - Type of DMA Transfer 694 //! 695 //! @return AM_HAL_STATUS_SUCCESS 696 // 697 //***************************************************************************** 698 extern uint32_t am_hal_i2s_dma_error(void *pHandle, am_hal_i2s_xfer_dir_e xfer); 699 700 //***************************************************************************** 701 // 702 //! @brief I2S DMA TX Buffer Empty Check 703 //! 704 //! @param pHandle - handle for the interface. 705 //! 706 //! @return true if empty, false is not empty 707 // 708 //***************************************************************************** 709 extern bool am_hal_i2s_tx_fifo_empty(void *pHandle); 710 711 #ifdef __cplusplus 712 } 713 #endif 714 715 #endif // AM_HAL_I2S_H 716 717 //***************************************************************************** 718 // 719 // End Doxygen group. 720 //! @} 721 // 722 //***************************************************************************** 723 724
