1 /** 2 ****************************************************************************** 3 * @file ais328dq_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * ais328dq_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef AIS328DQ_REGS_H 23 #define AIS328DQ_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup AIS328DQ 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup AIS328DQ_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> 0x31 if SA0=1 -> 0x33 **/ 172 #define AIS328DQ_I2C_ADD_L 0x31 173 #define AIS328DQ_I2C_ADD_H 0x33 174 175 /** Device Identification (Who am I) **/ 176 #define AIS328DQ_ID 0x32 177 178 /** 179 * @} 180 * 181 */ 182 183 /** 184 * @addtogroup AIS328DQ_Sensitivity 185 * @brief These macro are maintained for back compatibility. 186 * in order to convert data into engineering units please 187 * use functions: 188 * -> _from_fs2_to_mg(int16_t lsb); 189 * -> _from_fs4_to_mg(int16_t lsb); 190 * -> _from_fs8_to_mg(int16_t lsb); 191 * 192 * REMOVING the MACRO you are compliant with: 193 * MISRA-C 2012 [Dir 4.9] -> " avoid function-like macros " 194 * @{ 195 * 196 */ 197 198 #define AIS328DQ_FROM_FS_2g_TO_mg(lsb) (float_t)( (lsb >> 4 ) * 0.98f ) 199 #define AIS328DQ_FROM_FS_4g_TO_mg(lsb) (float_t)( (lsb >> 4 ) * 1.95f ) 200 #define AIS328DQ_FROM_FS_8g_TO_mg(lsb) (float_t)( (lsb >> 4 ) * 3.91f ) 201 202 /** 203 * @} 204 * 205 */ 206 207 #define AIS328DQ_WHO_AM_I 0x0FU 208 #define AIS328DQ_CTRL_REG1 0x20U 209 typedef struct 210 { 211 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 212 uint8_t xen : 1; 213 uint8_t yen : 1; 214 uint8_t zen : 1; 215 uint8_t dr : 2; 216 uint8_t pm : 3; 217 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 218 uint8_t pm : 3; 219 uint8_t dr : 2; 220 uint8_t zen : 1; 221 uint8_t yen : 1; 222 uint8_t xen : 1; 223 #endif /* DRV_BYTE_ORDER */ 224 } ais328dq_ctrl_reg1_t; 225 226 #define AIS328DQ_CTRL_REG2 0x21U 227 typedef struct 228 { 229 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 230 uint8_t hpcf : 2; 231 uint8_t hpen : 2; 232 uint8_t fds : 1; 233 uint8_t hpm : 2; 234 uint8_t boot : 1; 235 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 236 uint8_t boot : 1; 237 uint8_t hpm : 2; 238 uint8_t fds : 1; 239 uint8_t hpen : 2; 240 uint8_t hpcf : 2; 241 #endif /* DRV_BYTE_ORDER */ 242 } ais328dq_ctrl_reg2_t; 243 244 #define AIS328DQ_CTRL_REG3 0x22U 245 typedef struct 246 { 247 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 248 uint8_t i1_cfg : 2; 249 uint8_t lir1 : 1; 250 uint8_t i2_cfg : 2; 251 uint8_t lir2 : 1; 252 uint8_t pp_od : 1; 253 uint8_t ihl : 1; 254 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 255 uint8_t ihl : 1; 256 uint8_t pp_od : 1; 257 uint8_t lir2 : 1; 258 uint8_t i2_cfg : 2; 259 uint8_t lir1 : 1; 260 uint8_t i1_cfg : 2; 261 #endif /* DRV_BYTE_ORDER */ 262 } ais328dq_ctrl_reg3_t; 263 264 #define AIS328DQ_CTRL_REG4 0x23U 265 typedef struct 266 { 267 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 268 uint8_t sim : 1; 269 uint8_t st : 3; /* STsign + ST */ 270 uint8_t fs : 2; 271 uint8_t ble : 1; 272 uint8_t bdu : 1; 273 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 274 uint8_t bdu : 1; 275 uint8_t ble : 1; 276 uint8_t fs : 2; 277 uint8_t st : 3; /* STsign + ST */ 278 uint8_t sim : 1; 279 #endif /* DRV_BYTE_ORDER */ 280 } ais328dq_ctrl_reg4_t; 281 282 #define AIS328DQ_CTRL_REG5 0x24U 283 typedef struct 284 { 285 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 286 uint8_t turnon : 2; 287 uint8_t not_used_01 : 6; 288 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 289 uint8_t not_used_01 : 6; 290 uint8_t turnon : 2; 291 #endif /* DRV_BYTE_ORDER */ 292 } ais328dq_ctrl_reg5_t; 293 294 #define AIS328DQ_HP_FILTER_RESET 0x25U 295 #define AIS328DQ_REFERENCE 0x26U 296 #define AIS328DQ_STATUS_REG 0x27U 297 typedef struct 298 { 299 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 300 uint8_t xda : 1; 301 uint8_t yda : 1; 302 uint8_t zda : 1; 303 uint8_t zyxda : 1; 304 uint8_t _xor : 1; 305 uint8_t yor : 1; 306 uint8_t zor : 1; 307 uint8_t zyxor : 1; 308 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 309 uint8_t zyxor : 1; 310 uint8_t zor : 1; 311 uint8_t yor : 1; 312 uint8_t _xor : 1; 313 uint8_t zyxda : 1; 314 uint8_t zda : 1; 315 uint8_t yda : 1; 316 uint8_t xda : 1; 317 #endif /* DRV_BYTE_ORDER */ 318 } ais328dq_status_reg_t; 319 320 #define AIS328DQ_OUT_X_L 0x28U 321 #define AIS328DQ_OUT_X_H 0x29U 322 #define AIS328DQ_OUT_Y_L 0x2AU 323 #define AIS328DQ_OUT_Y_H 0x2BU 324 #define AIS328DQ_OUT_Z_L 0x2CU 325 #define AIS328DQ_OUT_Z_H 0x2DU 326 #define AIS328DQ_INT1_CFG 0x30U 327 typedef struct 328 { 329 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 330 uint8_t xlie : 1; 331 uint8_t xhie : 1; 332 uint8_t ylie : 1; 333 uint8_t yhie : 1; 334 uint8_t zlie : 1; 335 uint8_t zhie : 1; 336 uint8_t _6d : 1; 337 uint8_t aoi : 1; 338 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 339 uint8_t aoi : 1; 340 uint8_t _6d : 1; 341 uint8_t zhie : 1; 342 uint8_t zlie : 1; 343 uint8_t yhie : 1; 344 uint8_t ylie : 1; 345 uint8_t xhie : 1; 346 uint8_t xlie : 1; 347 #endif /* DRV_BYTE_ORDER */ 348 } ais328dq_int1_cfg_t; 349 350 #define AIS328DQ_INT1_SRC 0x31U 351 typedef struct 352 { 353 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 354 uint8_t xl : 1; 355 uint8_t xh : 1; 356 uint8_t yl : 1; 357 uint8_t yh : 1; 358 uint8_t zl : 1; 359 uint8_t zh : 1; 360 uint8_t ia : 1; 361 uint8_t not_used_01 : 1; 362 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 363 uint8_t not_used_01 : 1; 364 uint8_t ia : 1; 365 uint8_t zh : 1; 366 uint8_t zl : 1; 367 uint8_t yh : 1; 368 uint8_t yl : 1; 369 uint8_t xh : 1; 370 uint8_t xl : 1; 371 #endif /* DRV_BYTE_ORDER */ 372 } ais328dq_int1_src_t; 373 374 #define AIS328DQ_INT1_THS 0x32U 375 typedef struct 376 { 377 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 378 uint8_t ths : 7; 379 uint8_t not_used_01 : 1; 380 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 381 uint8_t not_used_01 : 1; 382 uint8_t ths : 7; 383 #endif /* DRV_BYTE_ORDER */ 384 } ais328dq_int1_ths_t; 385 386 #define AIS328DQ_INT1_DURATION 0x33U 387 typedef struct 388 { 389 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 390 uint8_t d : 7; 391 uint8_t not_used_01 : 1; 392 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 393 uint8_t not_used_01 : 1; 394 uint8_t d : 7; 395 #endif /* DRV_BYTE_ORDER */ 396 } ais328dq_int1_duration_t; 397 398 #define AIS328DQ_INT2_CFG 0x34U 399 typedef struct 400 { 401 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 402 uint8_t xlie : 1; 403 uint8_t xhie : 1; 404 uint8_t ylie : 1; 405 uint8_t yhie : 1; 406 uint8_t zlie : 1; 407 uint8_t zhie : 1; 408 uint8_t _6d : 1; 409 uint8_t aoi : 1; 410 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 411 uint8_t aoi : 1; 412 uint8_t _6d : 1; 413 uint8_t zhie : 1; 414 uint8_t zlie : 1; 415 uint8_t yhie : 1; 416 uint8_t ylie : 1; 417 uint8_t xhie : 1; 418 uint8_t xlie : 1; 419 #endif /* DRV_BYTE_ORDER */ 420 } ais328dq_int2_cfg_t; 421 422 #define AIS328DQ_INT2_SRC 0x35U 423 typedef struct 424 { 425 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 426 uint8_t xl : 1; 427 uint8_t xh : 1; 428 uint8_t yl : 1; 429 uint8_t yh : 1; 430 uint8_t zl : 1; 431 uint8_t zh : 1; 432 uint8_t ia : 1; 433 uint8_t not_used_01 : 1; 434 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 435 uint8_t not_used_01 : 1; 436 uint8_t ia : 1; 437 uint8_t zh : 1; 438 uint8_t zl : 1; 439 uint8_t yh : 1; 440 uint8_t yl : 1; 441 uint8_t xh : 1; 442 uint8_t xl : 1; 443 #endif /* DRV_BYTE_ORDER */ 444 } ais328dq_int2_src_t; 445 446 #define AIS328DQ_INT2_THS 0x36U 447 typedef struct 448 { 449 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 450 uint8_t ths : 7; 451 uint8_t not_used_01 : 1; 452 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 453 uint8_t not_used_01 : 1; 454 uint8_t ths : 7; 455 #endif /* DRV_BYTE_ORDER */ 456 } ais328dq_int2_ths_t; 457 458 #define AIS328DQ_INT2_DURATION 0x37U 459 typedef struct 460 { 461 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 462 uint8_t d : 7; 463 uint8_t not_used_01 : 1; 464 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 465 uint8_t not_used_01 : 1; 466 uint8_t d : 7; 467 #endif /* DRV_BYTE_ORDER */ 468 } ais328dq_int2_duration_t; 469 470 /** 471 * @defgroup AIS328DQ_Register_Union 472 * @brief This union group all the registers having a bit-field 473 * description. 474 * This union is useful but it's not needed by the driver. 475 * 476 * REMOVING this union you are compliant with: 477 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 478 * 479 * @{ 480 * 481 */ 482 typedef union 483 { 484 ais328dq_ctrl_reg1_t ctrl_reg1; 485 ais328dq_ctrl_reg2_t ctrl_reg2; 486 ais328dq_ctrl_reg3_t ctrl_reg3; 487 ais328dq_ctrl_reg4_t ctrl_reg4; 488 ais328dq_ctrl_reg5_t ctrl_reg5; 489 ais328dq_status_reg_t status_reg; 490 ais328dq_int1_cfg_t int1_cfg; 491 ais328dq_int1_src_t int1_src; 492 ais328dq_int1_ths_t int1_ths; 493 ais328dq_int1_duration_t int1_duration; 494 ais328dq_int2_cfg_t int2_cfg; 495 ais328dq_int2_src_t int2_src; 496 ais328dq_int2_ths_t int2_ths; 497 ais328dq_int2_duration_t int2_duration; 498 bitwise_t bitwise; 499 uint8_t byte; 500 } ais328dq_reg_t; 501 502 /** 503 * @} 504 * 505 */ 506 507 #ifndef __weak 508 #define __weak __attribute__((weak)) 509 #endif /* __weak */ 510 511 /* 512 * These are the basic platform dependent I/O routines to read 513 * and write device registers connected on a standard bus. 514 * The driver keeps offering a default implementation based on function 515 * pointers to read/write routines for backward compatibility. 516 * The __weak directive allows the final application to overwrite 517 * them with a custom implementation. 518 */ 519 520 int32_t ais328dq_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 521 uint8_t *data, 522 uint16_t len); 523 int32_t ais328dq_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 524 uint8_t *data, 525 uint16_t len); 526 527 float_t ais328dq_from_fs2_to_mg(int16_t lsb); 528 float_t ais328dq_from_fs4_to_mg(int16_t lsb); 529 float_t ais328dq_from_fs8_to_mg(int16_t lsb); 530 531 int32_t ais328dq_axis_x_data_set(const stmdev_ctx_t *ctx, uint8_t val); 532 int32_t ais328dq_axis_x_data_get(const stmdev_ctx_t *ctx, uint8_t *val); 533 534 int32_t ais328dq_axis_y_data_set(const stmdev_ctx_t *ctx, uint8_t val); 535 int32_t ais328dq_axis_y_data_get(const stmdev_ctx_t *ctx, uint8_t *val); 536 537 int32_t ais328dq_axis_z_data_set(const stmdev_ctx_t *ctx, uint8_t val); 538 int32_t ais328dq_axis_z_data_get(const stmdev_ctx_t *ctx, uint8_t *val); 539 540 typedef enum 541 { 542 AIS328DQ_ODR_OFF = 0x00, 543 AIS328DQ_ODR_Hz5 = 0x02, 544 AIS328DQ_ODR_1Hz = 0x03, 545 AIS328DQ_ODR_2Hz = 0x04, 546 AIS328DQ_ODR_5Hz = 0x05, 547 AIS328DQ_ODR_10Hz = 0x06, 548 AIS328DQ_ODR_50Hz = 0x01, 549 AIS328DQ_ODR_100Hz = 0x11, 550 AIS328DQ_ODR_400Hz = 0x21, 551 AIS328DQ_ODR_1kHz = 0x31, 552 } ais328dq_dr_t; 553 int32_t ais328dq_data_rate_set(const stmdev_ctx_t *ctx, ais328dq_dr_t val); 554 int32_t ais328dq_data_rate_get(const stmdev_ctx_t *ctx, ais328dq_dr_t *val); 555 556 typedef enum 557 { 558 AIS328DQ_NORMAL_MODE = 0, 559 AIS328DQ_REF_MODE_ENABLE = 1, 560 } ais328dq_hpm_t; 561 int32_t ais328dq_reference_mode_set(const stmdev_ctx_t *ctx, 562 ais328dq_hpm_t val); 563 int32_t ais328dq_reference_mode_get(const stmdev_ctx_t *ctx, 564 ais328dq_hpm_t *val); 565 566 typedef enum 567 { 568 AIS328DQ_2g = 0, 569 AIS328DQ_4g = 1, 570 AIS328DQ_8g = 3, 571 } ais328dq_fs_t; 572 int32_t ais328dq_full_scale_set(const stmdev_ctx_t *ctx, ais328dq_fs_t val); 573 int32_t ais328dq_full_scale_get(const stmdev_ctx_t *ctx, 574 ais328dq_fs_t *val); 575 576 int32_t ais328dq_block_data_update_set(const stmdev_ctx_t *ctx, 577 uint8_t val); 578 int32_t ais328dq_block_data_update_get(const stmdev_ctx_t *ctx, 579 uint8_t *val); 580 581 int32_t ais328dq_status_reg_get(const stmdev_ctx_t *ctx, 582 ais328dq_status_reg_t *val); 583 584 int32_t ais328dq_flag_data_ready_get(const stmdev_ctx_t *ctx, 585 uint8_t *val); 586 587 int32_t ais328dq_acceleration_raw_get(const stmdev_ctx_t *ctx, 588 int16_t *val); 589 590 int32_t ais328dq_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 591 592 int32_t ais328dq_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 593 int32_t ais328dq_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 594 595 typedef enum 596 { 597 AIS328DQ_ST_DISABLE = 0, 598 AIS328DQ_ST_POSITIVE = 1, 599 AIS328DQ_ST_NEGATIVE = 5, 600 } ais328dq_st_t; 601 int32_t ais328dq_self_test_set(const stmdev_ctx_t *ctx, ais328dq_st_t val); 602 int32_t ais328dq_self_test_get(const stmdev_ctx_t *ctx, ais328dq_st_t *val); 603 604 typedef enum 605 { 606 AIS328DQ_LSB_AT_LOW_ADD = 0, 607 AIS328DQ_MSB_AT_LOW_ADD = 1, 608 } ais328dq_ble_t; 609 int32_t ais328dq_data_format_set(const stmdev_ctx_t *ctx, 610 ais328dq_ble_t val); 611 int32_t ais328dq_data_format_get(const stmdev_ctx_t *ctx, 612 ais328dq_ble_t *val); 613 614 typedef enum 615 { 616 AIS328DQ_CUT_OFF_8Hz = 0, 617 AIS328DQ_CUT_OFF_16Hz = 1, 618 AIS328DQ_CUT_OFF_32Hz = 2, 619 AIS328DQ_CUT_OFF_64Hz = 3, 620 } ais328dq_hpcf_t; 621 int32_t ais328dq_hp_bandwidth_set(const stmdev_ctx_t *ctx, 622 ais328dq_hpcf_t val); 623 int32_t ais328dq_hp_bandwidth_get(const stmdev_ctx_t *ctx, 624 ais328dq_hpcf_t *val); 625 626 typedef enum 627 { 628 AIS328DQ_HP_DISABLE = 0, 629 AIS328DQ_HP_ON_OUT = 4, 630 AIS328DQ_HP_ON_INT1 = 1, 631 AIS328DQ_HP_ON_INT2 = 2, 632 AIS328DQ_HP_ON_INT1_INT2 = 3, 633 AIS328DQ_HP_ON_INT1_INT2_OUT = 7, 634 AIS328DQ_HP_ON_INT2_OUT = 6, 635 AIS328DQ_HP_ON_INT1_OUT = 5, 636 } ais328dq_hpen_t; 637 int32_t ais328dq_hp_path_set(const stmdev_ctx_t *ctx, ais328dq_hpen_t val); 638 int32_t ais328dq_hp_path_get(const stmdev_ctx_t *ctx, ais328dq_hpen_t *val); 639 640 int32_t ais328dq_hp_reset_get(stmdev_ctx_t *ctx); 641 642 int32_t ais328dq_hp_reference_value_set(const stmdev_ctx_t *ctx, 643 uint8_t val); 644 int32_t ais328dq_hp_reference_value_get(const stmdev_ctx_t *ctx, 645 uint8_t *val); 646 647 typedef enum 648 { 649 AIS328DQ_SPI_4_WIRE = 0, 650 AIS328DQ_SPI_3_WIRE = 1, 651 } ais328dq_sim_t; 652 int32_t ais328dq_spi_mode_set(const stmdev_ctx_t *ctx, ais328dq_sim_t val); 653 int32_t ais328dq_spi_mode_get(const stmdev_ctx_t *ctx, ais328dq_sim_t *val); 654 655 typedef enum 656 { 657 AIS328DQ_PAD1_INT1_SRC = 0, 658 AIS328DQ_PAD1_INT1_OR_INT2_SRC = 1, 659 AIS328DQ_PAD1_DRDY = 2, 660 AIS328DQ_PAD1_BOOT = 3, 661 } ais328dq_i1_cfg_t; 662 int32_t ais328dq_pin_int1_route_set(const stmdev_ctx_t *ctx, 663 ais328dq_i1_cfg_t val); 664 int32_t ais328dq_pin_int1_route_get(const stmdev_ctx_t *ctx, 665 ais328dq_i1_cfg_t *val); 666 667 typedef enum 668 { 669 AIS328DQ_INT1_PULSED = 0, 670 AIS328DQ_INT1_LATCHED = 1, 671 } ais328dq_lir1_t; 672 int32_t ais328dq_int1_notification_set(const stmdev_ctx_t *ctx, 673 ais328dq_lir1_t val); 674 int32_t ais328dq_int1_notification_get(const stmdev_ctx_t *ctx, 675 ais328dq_lir1_t *val); 676 677 typedef enum 678 { 679 AIS328DQ_PAD2_INT2_SRC = 0, 680 AIS328DQ_PAD2_INT1_OR_INT2_SRC = 1, 681 AIS328DQ_PAD2_DRDY = 2, 682 AIS328DQ_PAD2_BOOT = 3, 683 } ais328dq_i2_cfg_t; 684 int32_t ais328dq_pin_int2_route_set(const stmdev_ctx_t *ctx, 685 ais328dq_i2_cfg_t val); 686 int32_t ais328dq_pin_int2_route_get(const stmdev_ctx_t *ctx, 687 ais328dq_i2_cfg_t *val); 688 689 typedef enum 690 { 691 AIS328DQ_INT2_PULSED = 0, 692 AIS328DQ_INT2_LATCHED = 1, 693 } ais328dq_lir2_t; 694 int32_t ais328dq_int2_notification_set(const stmdev_ctx_t *ctx, 695 ais328dq_lir2_t val); 696 int32_t ais328dq_int2_notification_get(const stmdev_ctx_t *ctx, 697 ais328dq_lir2_t *val); 698 699 typedef enum 700 { 701 AIS328DQ_PUSH_PULL = 0, 702 AIS328DQ_OPEN_DRAIN = 1, 703 } ais328dq_pp_od_t; 704 int32_t ais328dq_pin_mode_set(const stmdev_ctx_t *ctx, 705 ais328dq_pp_od_t val); 706 int32_t ais328dq_pin_mode_get(const stmdev_ctx_t *ctx, 707 ais328dq_pp_od_t *val); 708 709 typedef enum 710 { 711 AIS328DQ_ACTIVE_HIGH = 0, 712 AIS328DQ_ACTIVE_LOW = 1, 713 } ais328dq_ihl_t; 714 int32_t ais328dq_pin_polarity_set(const stmdev_ctx_t *ctx, 715 ais328dq_ihl_t val); 716 int32_t ais328dq_pin_polarity_get(const stmdev_ctx_t *ctx, 717 ais328dq_ihl_t *val); 718 719 typedef struct 720 { 721 uint8_t int1_xlie : 1; 722 uint8_t int1_xhie : 1; 723 uint8_t int1_ylie : 1; 724 uint8_t int1_yhie : 1; 725 uint8_t int1_zlie : 1; 726 uint8_t int1_zhie : 1; 727 } ais328dq_int1_on_th_conf_t; 728 int32_t ais328dq_int1_on_threshold_conf_set(const stmdev_ctx_t *ctx, 729 ais328dq_int1_on_th_conf_t val); 730 int32_t ais328dq_int1_on_threshold_conf_get(const stmdev_ctx_t *ctx, 731 ais328dq_int1_on_th_conf_t *val); 732 733 typedef enum 734 { 735 AIS328DQ_INT1_ON_THRESHOLD_OR = 0, 736 AIS328DQ_INT1_ON_THRESHOLD_AND = 1, 737 } ais328dq_int1_aoi_t; 738 int32_t ais328dq_int1_on_threshold_mode_set(const stmdev_ctx_t *ctx, 739 ais328dq_int1_aoi_t val); 740 int32_t ais328dq_int1_on_threshold_mode_get(const stmdev_ctx_t *ctx, 741 ais328dq_int1_aoi_t *val); 742 743 int32_t ais328dq_int1_src_get(const stmdev_ctx_t *ctx, 744 ais328dq_int1_src_t *val); 745 746 int32_t ais328dq_int1_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 747 int32_t ais328dq_int1_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 748 749 int32_t ais328dq_int1_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 750 int32_t ais328dq_int1_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 751 752 typedef struct 753 { 754 uint8_t int2_xlie : 1; 755 uint8_t int2_xhie : 1; 756 uint8_t int2_ylie : 1; 757 uint8_t int2_yhie : 1; 758 uint8_t int2_zlie : 1; 759 uint8_t int2_zhie : 1; 760 } ais328dq_int2_on_th_conf_t; 761 int32_t ais328dq_int2_on_threshold_conf_set(const stmdev_ctx_t *ctx, 762 ais328dq_int2_on_th_conf_t val); 763 int32_t ais328dq_int2_on_threshold_conf_get(const stmdev_ctx_t *ctx, 764 ais328dq_int2_on_th_conf_t *val); 765 766 typedef enum 767 { 768 AIS328DQ_INT2_ON_THRESHOLD_OR = 0, 769 AIS328DQ_INT2_ON_THRESHOLD_AND = 1, 770 } ais328dq_int2_aoi_t; 771 int32_t ais328dq_int2_on_threshold_mode_set(const stmdev_ctx_t *ctx, 772 ais328dq_int2_aoi_t val); 773 int32_t ais328dq_int2_on_threshold_mode_get(const stmdev_ctx_t *ctx, 774 ais328dq_int2_aoi_t *val); 775 776 int32_t ais328dq_int2_src_get(const stmdev_ctx_t *ctx, 777 ais328dq_int2_src_t *val); 778 779 int32_t ais328dq_int2_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 780 int32_t ais328dq_int2_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 781 782 int32_t ais328dq_int2_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 783 int32_t ais328dq_int2_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 784 785 int32_t ais328dq_wkup_to_sleep_set(const stmdev_ctx_t *ctx, uint8_t val); 786 int32_t ais328dq_wkup_to_sleep_get(const stmdev_ctx_t *ctx, uint8_t *val); 787 788 typedef enum 789 { 790 AIS328DQ_6D_INT1_DISABLE = 0, 791 AIS328DQ_6D_INT1_MOVEMENT = 1, 792 AIS328DQ_6D_INT1_POSITION = 3, 793 } ais328dq_int1_6d_t; 794 int32_t ais328dq_int1_6d_mode_set(const stmdev_ctx_t *ctx, 795 ais328dq_int1_6d_t val); 796 int32_t ais328dq_int1_6d_mode_get(const stmdev_ctx_t *ctx, 797 ais328dq_int1_6d_t *val); 798 799 int32_t ais328dq_int1_6d_src_get(const stmdev_ctx_t *ctx, 800 ais328dq_int1_src_t *val); 801 802 int32_t ais328dq_int1_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 803 int32_t ais328dq_int1_6d_threshold_get(const stmdev_ctx_t *ctx, 804 uint8_t *val); 805 806 typedef enum 807 { 808 AIS328DQ_6D_INT2_DISABLE = 0, 809 AIS328DQ_6D_INT2_MOVEMENT = 1, 810 AIS328DQ_6D_INT2_POSITION = 3, 811 } ais328dq_int2_6d_t; 812 int32_t ais328dq_int2_6d_mode_set(const stmdev_ctx_t *ctx, 813 ais328dq_int2_6d_t val); 814 int32_t ais328dq_int2_6d_mode_get(const stmdev_ctx_t *ctx, 815 ais328dq_int2_6d_t *val); 816 817 int32_t ais328dq_int2_6d_src_get(const stmdev_ctx_t *ctx, 818 ais328dq_int2_src_t *val); 819 820 int32_t ais328dq_int2_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 821 int32_t ais328dq_int2_6d_threshold_get(const stmdev_ctx_t *ctx, 822 uint8_t *val); 823 824 /** 825 *@} 826 * 827 */ 828 829 #ifdef __cplusplus 830 } 831 #endif 832 833 #endif /* AIS328DQ_REGS_H */ 834 835 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 836
