1 /** 2 ****************************************************************************** 3 * @file ais2dw12_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * ais2dw12_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef AIS2DW12_REGS_H 23 #define AIS2DW12_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup AIS2DW12 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 /** 102 * @} 103 * 104 */ 105 106 #define PROPERTY_DISABLE (0U) 107 #define PROPERTY_ENABLE (1U) 108 109 /** @addtogroup Interfaces_Functions 110 * @brief This section provide a set of functions used to read and 111 * write a generic register of the device. 112 * MANDATORY: return 0 -> no Error. 113 * @{ 114 * 115 */ 116 117 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 118 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 119 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 120 121 typedef struct 122 { 123 /** Component mandatory fields **/ 124 stmdev_write_ptr write_reg; 125 stmdev_read_ptr read_reg; 126 /** Component optional fields **/ 127 stmdev_mdelay_ptr mdelay; 128 /** Customizable optional pointer **/ 129 void *handle; 130 } stmdev_ctx_t; 131 132 /** 133 * @} 134 * 135 */ 136 137 #endif /* MEMS_SHARED_TYPES */ 138 139 #ifndef MEMS_UCF_SHARED_TYPES 140 #define MEMS_UCF_SHARED_TYPES 141 142 /** @defgroup Generic address-data structure definition 143 * @brief This structure is useful to load a predefined configuration 144 * of a sensor. 145 * You can create a sensor configuration by your own or using 146 * Unico / Unicleo tools available on STMicroelectronics 147 * web site. 148 * 149 * @{ 150 * 151 */ 152 153 typedef struct 154 { 155 uint8_t address; 156 uint8_t data; 157 } ucf_line_t; 158 159 /** 160 * @} 161 * 162 */ 163 164 #endif /* MEMS_UCF_SHARED_TYPES */ 165 166 /** 167 * @} 168 * 169 */ 170 171 /** @defgroup AIS2DW12_Infos 172 * @{ 173 * 174 */ 175 176 /** I2C Device Address 8 bit format if SA0=0 -> 31 if SA0=1 -> 33 **/ 177 #define AIS2DW12_I2C_ADD_L 0x31U 178 #define AIS2DW12_I2C_ADD_H 0x33U 179 180 /** Device Identification (Who am I) **/ 181 #define AIS2DW12_ID 0x44U 182 183 /** 184 * @} 185 * 186 */ 187 188 #define AIS2DW12_OUT_T_L 0x0DU 189 #define AIS2DW12_OUT_T_H 0x0EU 190 #define AIS2DW12_WHO_AM_I 0x0FU 191 #define AIS2DW12_CTRL1 0x20U 192 typedef struct 193 { 194 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 195 uint8_t pw_mode : 2; 196 uint8_t op_mode : 2; 197 uint8_t odr : 4; 198 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 199 uint8_t odr : 4; 200 uint8_t op_mode : 2; 201 uint8_t pw_mode : 2; 202 #endif /* DRV_BYTE_ORDER*/ 203 } ais2dw12_ctrl1_t; 204 205 #define AIS2DW12_CTRL2 0x21U 206 typedef struct 207 { 208 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 209 uint8_t sim : 1; 210 uint8_t i2c_disable : 1; 211 uint8_t if_add_inc : 1; 212 uint8_t bdu : 1; 213 uint8_t cs_pu_disc : 1; 214 uint8_t not_used_01 : 1; 215 uint8_t soft_reset : 1; 216 uint8_t boot : 1; 217 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 218 uint8_t boot : 1; 219 uint8_t soft_reset : 1; 220 uint8_t not_used_01 : 1; 221 uint8_t cs_pu_disc : 1; 222 uint8_t bdu : 1; 223 uint8_t if_add_inc : 1; 224 uint8_t i2c_disable : 1; 225 uint8_t sim : 1; 226 #endif /* DRV_BYTE_ORDER */ 227 } ais2dw12_ctrl2_t; 228 229 #define AIS2DW12_CTRL3 0x22U 230 typedef struct 231 { 232 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 233 uint8_t slp_mode : 234 2; /* slp_mode_sel + slp_mode_1 */ 235 uint8_t not_used_01 : 1; 236 uint8_t h_lactive : 1; 237 uint8_t lir : 1; 238 uint8_t pp_od : 1; 239 uint8_t st : 2; 240 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 241 uint8_t st : 2; 242 uint8_t pp_od : 1; 243 uint8_t lir : 1; 244 uint8_t h_lactive : 1; 245 uint8_t not_used_01 : 1; 246 uint8_t slp_mode : 247 2; /* slp_mode_sel + slp_mode_1 */ 248 #endif /* DRV_BYTE_ORDER */ 249 } ais2dw12_ctrl3_t; 250 251 #define AIS2DW12_CTRL4_INT1 0x23U 252 typedef struct 253 { 254 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 255 uint8_t int1_drdy : 1; 256 uint8_t int1_fth : 1; 257 uint8_t int1_diff5 : 1; 258 uint8_t not_used_01 : 1; 259 uint8_t int1_ff : 1; 260 uint8_t int1_wu : 1; 261 uint8_t not_used_02 : 1; 262 uint8_t int1_6d : 1; 263 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 264 uint8_t int1_6d : 1; 265 uint8_t not_used_02 : 1; 266 uint8_t int1_wu : 1; 267 uint8_t int1_ff : 1; 268 uint8_t not_used_01 : 1; 269 uint8_t int1_diff5 : 1; 270 uint8_t int1_fth : 1; 271 uint8_t int1_drdy : 1; 272 #endif /* DRV_BYTE_ORDER */ 273 } ais2dw12_ctrl4_int1_t; 274 275 #define AIS2DW12_CTRL5_INT2 0x24U 276 typedef struct 277 { 278 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 279 uint8_t int2_drdy : 1; 280 uint8_t int2_fth : 1; 281 uint8_t int2_diff5 : 1; 282 uint8_t int2_ovr : 1; 283 uint8_t int2_drdy_t : 1; 284 uint8_t int2_boot : 1; 285 uint8_t int2_sleep_chg : 1; 286 uint8_t int2_sleep_state : 1; 287 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 288 uint8_t int2_sleep_state : 1; 289 uint8_t int2_sleep_chg : 1; 290 uint8_t int2_boot : 1; 291 uint8_t int2_drdy_t : 1; 292 uint8_t int2_ovr : 1; 293 uint8_t int2_diff5 : 1; 294 uint8_t int2_fth : 1; 295 uint8_t int2_drdy : 1; 296 #endif /* DRV_BYTE_ORDER */ 297 } ais2dw12_ctrl5_int2_t; 298 299 #define AIS2DW12_CTRL6 0x25U 300 typedef struct 301 { 302 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 303 uint8_t not_used_01 : 3; 304 uint8_t fds : 1; 305 uint8_t fs : 2; 306 uint8_t bw_filt : 2; 307 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 308 uint8_t bw_filt : 2; 309 uint8_t fs : 2; 310 uint8_t fds : 1; 311 uint8_t not_used_01 : 3; 312 #endif /* DRV_BYTE_ORDER */ 313 } ais2dw12_ctrl6_t; 314 315 #define AIS2DW12_OUT_T 0x26U 316 #define AIS2DW12_STATUS 0x27U 317 typedef struct 318 { 319 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 320 uint8_t drdy : 1; 321 uint8_t ff_ia : 1; 322 uint8_t _6d_ia : 1; 323 uint8_t not_used_01 : 2; 324 uint8_t sleep_state : 1; 325 uint8_t wu_ia : 1; 326 uint8_t fifo_ths : 1; 327 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 328 uint8_t fifo_ths : 1; 329 uint8_t wu_ia : 1; 330 uint8_t sleep_state : 1; 331 uint8_t not_used_01 : 2; 332 uint8_t _6d_ia : 1; 333 uint8_t ff_ia : 1; 334 uint8_t drdy : 1; 335 #endif /* DRV_BYTE_ORDER */ 336 } ais2dw12_status_t; 337 338 #define AIS2DW12_OUT_X_L 0x28U 339 #define AIS2DW12_OUT_X_H 0x29U 340 #define AIS2DW12_OUT_Y_L 0x2AU 341 #define AIS2DW12_OUT_Y_H 0x2BU 342 #define AIS2DW12_OUT_Z_L 0x2CU 343 #define AIS2DW12_OUT_Z_H 0x2DU 344 #define AIS2DW12_FIFO_CTRL 0x2EU 345 typedef struct 346 { 347 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 348 uint8_t fth : 5; 349 uint8_t fmode : 3; 350 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 351 uint8_t fmode : 3; 352 uint8_t fth : 5; 353 #endif /* DRV_BYTE_ORDER */ 354 } ais2dw12_fifo_ctrl_t; 355 356 #define AIS2DW12_FIFO_SAMPLES 0x2FU 357 typedef struct 358 { 359 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 360 uint8_t diff : 6; 361 uint8_t fifo_ovr : 1; 362 uint8_t fifo_fth : 1; 363 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 364 uint8_t fifo_fth : 1; 365 uint8_t fifo_ovr : 1; 366 uint8_t diff : 6; 367 #endif /* DRV_BYTE_ORDER */ 368 } ais2dw12_fifo_samples_t; 369 370 #define AIS2DW12_SIXD_THS 0x30U 371 typedef struct 372 { 373 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 374 uint8_t not_used_01 : 5; 375 uint8_t _6d_ths : 2; 376 uint8_t _4d_en : 1; 377 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 378 uint8_t _4d_en : 1; 379 uint8_t _6d_ths : 2; 380 uint8_t not_used_01 : 5; 381 #endif /* DRV_BYTE_ORDER */ 382 } ais2dw12_sixd_ths_t; 383 384 #define AIS2DW12_WAKE_UP_THS 0x34U 385 typedef struct 386 { 387 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 388 uint8_t wk_ths : 6; 389 uint8_t sleep_on : 1; 390 uint8_t not_used_01 : 1; 391 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 392 uint8_t not_used_01 : 1; 393 uint8_t sleep_on : 1; 394 uint8_t wk_ths : 6; 395 #endif /* DRV_BYTE_ORDER */ 396 } ais2dw12_wake_up_ths_t; 397 398 #define AIS2DW12_WAKE_UP_DUR 0x35U 399 typedef struct 400 { 401 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 402 uint8_t sleep_dur : 4; 403 uint8_t stationary : 1; 404 uint8_t wake_dur : 2; 405 uint8_t ff_dur : 1; 406 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 407 uint8_t ff_dur : 1; 408 uint8_t wake_dur : 2; 409 uint8_t stationary : 1; 410 uint8_t sleep_dur : 4; 411 #endif /* DRV_BYTE_ORDER */ 412 } ais2dw12_wake_up_dur_t; 413 414 #define AIS2DW12_FREE_FALL 0x36U 415 typedef struct 416 { 417 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 418 uint8_t ff_ths : 3; 419 uint8_t ff_dur : 5; 420 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 421 uint8_t ff_dur : 5; 422 uint8_t ff_ths : 3; 423 #endif /* DRV_BYTE_ORDER */ 424 } ais2dw12_free_fall_t; 425 426 #define AIS2DW12_STATUS_DUP 0x37U 427 typedef struct 428 { 429 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 430 uint8_t drdy : 1; 431 uint8_t ff_ia : 1; 432 uint8_t _6d_ia : 1; 433 uint8_t not_used_01 : 2; 434 uint8_t sleep_state_ia : 1; 435 uint8_t drdy_t : 1; 436 uint8_t ovr : 1; 437 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 438 uint8_t ovr : 1; 439 uint8_t drdy_t : 1; 440 uint8_t sleep_state_ia : 1; 441 uint8_t not_used_01 : 2; 442 uint8_t _6d_ia : 1; 443 uint8_t ff_ia : 1; 444 uint8_t drdy : 1; 445 #endif /* DRV_BYTE_ORDER */ 446 } ais2dw12_status_dup_t; 447 448 #define AIS2DW12_WAKE_UP_SRC 0x38U 449 typedef struct 450 { 451 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 452 uint8_t z_wu : 1; 453 uint8_t y_wu : 1; 454 uint8_t x_wu : 1; 455 uint8_t wu_ia : 1; 456 uint8_t sleep_state_ia : 1; 457 uint8_t ff_ia : 1; 458 uint8_t not_used_01 : 2; 459 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 460 uint8_t not_used_01 : 2; 461 uint8_t ff_ia : 1; 462 uint8_t sleep_state_ia : 1; 463 uint8_t wu_ia : 1; 464 uint8_t x_wu : 1; 465 uint8_t y_wu : 1; 466 uint8_t z_wu : 1; 467 #endif /* DRV_BYTE_ORDER */ 468 } ais2dw12_wake_up_src_t; 469 470 #define AIS2DW12_SIXD_SRC 0x3AU 471 typedef struct 472 { 473 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 474 uint8_t xl : 1; 475 uint8_t xh : 1; 476 uint8_t yl : 1; 477 uint8_t yh : 1; 478 uint8_t zl : 1; 479 uint8_t zh : 1; 480 uint8_t _6d_ia : 1; 481 uint8_t not_used_01 : 1; 482 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 483 uint8_t not_used_01 : 1; 484 uint8_t _6d_ia : 1; 485 uint8_t zh : 1; 486 uint8_t zl : 1; 487 uint8_t yh : 1; 488 uint8_t yl : 1; 489 uint8_t xh : 1; 490 uint8_t xl : 1; 491 #endif /* DRV_BYTE_ORDER */ 492 } ais2dw12_sixd_src_t; 493 494 #define AIS2DW12_ALL_INT_SRC 0x3BU 495 typedef struct 496 { 497 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 498 uint8_t ff_ia : 1; 499 uint8_t wu_ia : 1; 500 uint8_t not_used_01 : 2; 501 uint8_t _6d_ia : 1; 502 uint8_t sleep_change_ia : 1; 503 uint8_t not_used_02 : 2; 504 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 505 uint8_t not_used_02 : 2; 506 uint8_t sleep_change_ia : 1; 507 uint8_t _6d_ia : 1; 508 uint8_t not_used_01 : 2; 509 uint8_t wu_ia : 1; 510 uint8_t ff_ia : 1; 511 #endif /* DRV_BYTE_ORDER */ 512 } ais2dw12_all_int_src_t; 513 514 #define AIS2DW12_X_OFS_USR 0x3CU 515 #define AIS2DW12_Y_OFS_USR 0x3DU 516 #define AIS2DW12_Z_OFS_USR 0x3EU 517 #define AIS2DW12_CTRL7 0x3FU 518 typedef struct 519 { 520 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 521 uint8_t lpass_on6d : 1; 522 uint8_t hp_ref_mode : 1; 523 uint8_t usr_off_w : 1; 524 uint8_t usr_off_on_wu : 1; 525 uint8_t usr_off_on_out : 1; 526 uint8_t interrupts_enable : 1; 527 uint8_t int2_on_int1 : 1; 528 uint8_t drdy_pulsed : 1; 529 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 530 uint8_t drdy_pulsed : 1; 531 uint8_t int2_on_int1 : 1; 532 uint8_t interrupts_enable : 1; 533 uint8_t usr_off_on_out : 1; 534 uint8_t usr_off_on_wu : 1; 535 uint8_t usr_off_w : 1; 536 uint8_t hp_ref_mode : 1; 537 uint8_t lpass_on6d : 1; 538 #endif /* DRV_BYTE_ORDER */ 539 } ais2dw12_ctrl7_t; 540 541 /** 542 * @defgroup AIS2DW12_Register_Union 543 * @brief This union group all the registers having a bit-field 544 * description. 545 * This union is useful but it's not needed by the driver. 546 * 547 * REMOVING this union you are compliant with: 548 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 549 * 550 * @{ 551 * 552 */ 553 typedef union 554 { 555 ais2dw12_ctrl1_t ctrl1; 556 ais2dw12_ctrl2_t ctrl2; 557 ais2dw12_ctrl3_t ctrl3; 558 ais2dw12_ctrl4_int1_t ctrl4_int1; 559 ais2dw12_ctrl5_int2_t ctrl5_int2; 560 ais2dw12_ctrl6_t ctrl6; 561 ais2dw12_status_t status; 562 ais2dw12_fifo_ctrl_t fifo_ctrl; 563 ais2dw12_fifo_samples_t fifo_samples; 564 ais2dw12_sixd_ths_t sixd_ths; 565 ais2dw12_wake_up_ths_t wake_up_ths; 566 ais2dw12_wake_up_dur_t wake_up_dur; 567 ais2dw12_free_fall_t free_fall; 568 ais2dw12_status_dup_t status_dup; 569 ais2dw12_wake_up_src_t wake_up_src; 570 ais2dw12_sixd_src_t sixd_src; 571 ais2dw12_all_int_src_t all_int_src; 572 ais2dw12_ctrl7_t ctrl7; 573 bitwise_t bitwise; 574 uint8_t byte; 575 } ais2dw12_reg_t; 576 577 /** 578 * @} 579 * 580 */ 581 582 #ifndef __weak 583 #define __weak __attribute__((weak)) 584 #endif /* __weak */ 585 586 /* 587 * These are the basic platform dependent I/O routines to read 588 * and write device registers connected on a standard bus. 589 * The driver keeps offering a default implementation based on function 590 * pointers to read/write routines for backward compatibility. 591 * The __weak directive allows the final application to overwrite 592 * them with a custom implementation. 593 */ 594 595 int32_t ais2dw12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 596 uint8_t *data, 597 uint16_t len); 598 int32_t ais2dw12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 599 uint8_t *data, 600 uint16_t len); 601 602 float_t ais2dw12_from_fs2_to_mg(int16_t lsb); 603 float_t ais2dw12_from_fs4_to_mg(int16_t lsb); 604 float_t ais2dw12_from_fs2_12bit_to_mg(int16_t lsb); 605 float_t ais2dw12_from_fs4_12bit_to_mg(int16_t lsb); 606 607 float_t ais2dw12_from_lsb_to_celsius(int16_t lsb); 608 609 typedef enum 610 { 611 AIS2DW12_PWR_MD_4 = 0x03, 612 AIS2DW12_PWR_MD_3 = 0x02, 613 AIS2DW12_PWR_MD_2 = 0x01, 614 AIS2DW12_PWR_MD_12bit = 0x00, 615 AIS2DW12_SINGLE_PWR_MD_4 = 0x0B, 616 AIS2DW12_SINGLE_PWR_MD_3 = 0x0A, 617 AIS2DW12_SINGLE_PWR_MD_2 = 0x09, 618 AIS2DW12_SINGLE_PWR_MD_12bit = 0x08, 619 } ais2dw12_mode_t; 620 int32_t ais2dw12_power_mode_set(const stmdev_ctx_t *ctx, 621 ais2dw12_mode_t val); 622 int32_t ais2dw12_power_mode_get(const stmdev_ctx_t *ctx, 623 ais2dw12_mode_t *val); 624 625 typedef enum 626 { 627 AIS2DW12_XL_ODR_OFF = 0x00, 628 AIS2DW12_XL_ODR_1Hz6 = 0x01, 629 AIS2DW12_XL_ODR_12Hz5 = 0x02, 630 AIS2DW12_XL_ODR_25Hz = 0x03, 631 AIS2DW12_XL_ODR_50Hz = 0x04, 632 AIS2DW12_XL_ODR_100Hz = 0x05, 633 AIS2DW12_XL_SET_SW_TRIG = 0x12, /* Use this only in SINGLE mode */ 634 AIS2DW12_XL_SET_PIN_TRIG = 0x22, /* Use this only in SINGLE mode */ 635 } ais2dw12_odr_t; 636 int32_t ais2dw12_data_rate_set(const stmdev_ctx_t *ctx, ais2dw12_odr_t val); 637 int32_t ais2dw12_data_rate_get(const stmdev_ctx_t *ctx, 638 ais2dw12_odr_t *val); 639 640 int32_t ais2dw12_block_data_update_set(const stmdev_ctx_t *ctx, 641 uint8_t val); 642 int32_t ais2dw12_block_data_update_get(const stmdev_ctx_t *ctx, 643 uint8_t *val); 644 645 typedef enum 646 { 647 AIS2DW12_2g = 0, 648 AIS2DW12_4g = 1, 649 } ais2dw12_fs_t; 650 int32_t ais2dw12_full_scale_set(const stmdev_ctx_t *ctx, ais2dw12_fs_t val); 651 int32_t ais2dw12_full_scale_get(const stmdev_ctx_t *ctx, 652 ais2dw12_fs_t *val); 653 654 int32_t ais2dw12_status_reg_get(const stmdev_ctx_t *ctx, 655 ais2dw12_status_t *val); 656 657 int32_t ais2dw12_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 658 659 typedef struct 660 { 661 ais2dw12_status_dup_t status_dup; 662 ais2dw12_wake_up_src_t wake_up_src; 663 ais2dw12_sixd_src_t sixd_src; 664 ais2dw12_all_int_src_t all_int_src; 665 } ais2dw12_all_sources_t; 666 int32_t ais2dw12_all_sources_get(const stmdev_ctx_t *ctx, 667 ais2dw12_all_sources_t *val); 668 669 int32_t ais2dw12_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff); 670 int32_t ais2dw12_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff); 671 672 int32_t ais2dw12_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff); 673 int32_t ais2dw12_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff); 674 675 int32_t ais2dw12_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff); 676 int32_t ais2dw12_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff); 677 678 typedef enum 679 { 680 AIS2DW12_LSb_977ug = 0, 681 AIS2DW12_LSb_15mg6 = 1, 682 } ais2dw12_usr_off_w_t; 683 int32_t ais2dw12_offset_weight_set(const stmdev_ctx_t *ctx, 684 ais2dw12_usr_off_w_t val); 685 int32_t ais2dw12_offset_weight_get(const stmdev_ctx_t *ctx, 686 ais2dw12_usr_off_w_t *val); 687 688 int32_t ais2dw12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 689 690 int32_t ais2dw12_acceleration_raw_get(const stmdev_ctx_t *ctx, 691 int16_t *val); 692 693 int32_t ais2dw12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 694 695 int32_t ais2dw12_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); 696 int32_t ais2dw12_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); 697 698 int32_t ais2dw12_reset_set(const stmdev_ctx_t *ctx, uint8_t val); 699 int32_t ais2dw12_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 700 701 int32_t ais2dw12_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 702 int32_t ais2dw12_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 703 704 typedef enum 705 { 706 AIS2DW12_XL_ST_DISABLE = 0, 707 AIS2DW12_XL_ST_POSITIVE = 1, 708 AIS2DW12_XL_ST_NEGATIVE = 2, 709 } ais2dw12_st_t; 710 int32_t ais2dw12_self_test_set(const stmdev_ctx_t *ctx, ais2dw12_st_t val); 711 int32_t ais2dw12_self_test_get(const stmdev_ctx_t *ctx, ais2dw12_st_t *val); 712 713 typedef enum 714 { 715 AIS2DW12_DRDY_LATCHED = 0, 716 AIS2DW12_DRDY_PULSED = 1, 717 } ais2dw12_drdy_pulsed_t; 718 int32_t ais2dw12_data_ready_mode_set(const stmdev_ctx_t *ctx, 719 ais2dw12_drdy_pulsed_t val); 720 int32_t ais2dw12_data_ready_mode_get(const stmdev_ctx_t *ctx, 721 ais2dw12_drdy_pulsed_t *val); 722 723 typedef enum 724 { 725 AIS2DW12_LPF_ON_OUT = 0x00, 726 AIS2DW12_USER_OFFSET_ON_OUT = 0x01, 727 AIS2DW12_HIGH_PASS_ON_OUT = 0x10, 728 } ais2dw12_fds_t; 729 int32_t ais2dw12_filter_path_set(const stmdev_ctx_t *ctx, 730 ais2dw12_fds_t val); 731 int32_t ais2dw12_filter_path_get(const stmdev_ctx_t *ctx, 732 ais2dw12_fds_t *val); 733 734 typedef enum 735 { 736 AIS2DW12_ODR_DIV_2 = 0, 737 AIS2DW12_ODR_DIV_4 = 1, 738 AIS2DW12_ODR_DIV_10 = 2, 739 AIS2DW12_ODR_DIV_20 = 3, 740 } ais2dw12_bw_filt_t; 741 int32_t ais2dw12_filter_bandwidth_set(const stmdev_ctx_t *ctx, 742 ais2dw12_bw_filt_t val); 743 int32_t ais2dw12_filter_bandwidth_get(const stmdev_ctx_t *ctx, 744 ais2dw12_bw_filt_t *val); 745 746 int32_t ais2dw12_reference_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 747 int32_t ais2dw12_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 748 749 typedef enum 750 { 751 AIS2DW12_SPI_4_WIRE = 0, 752 AIS2DW12_SPI_3_WIRE = 1, 753 } ais2dw12_sim_t; 754 int32_t ais2dw12_spi_mode_set(const stmdev_ctx_t *ctx, ais2dw12_sim_t val); 755 int32_t ais2dw12_spi_mode_get(const stmdev_ctx_t *ctx, ais2dw12_sim_t *val); 756 757 typedef enum 758 { 759 AIS2DW12_I2C_ENABLE = 0, 760 AIS2DW12_I2C_DISABLE = 1, 761 } ais2dw12_i2c_disable_t; 762 int32_t ais2dw12_i2c_interface_set(const stmdev_ctx_t *ctx, 763 ais2dw12_i2c_disable_t val); 764 int32_t ais2dw12_i2c_interface_get(const stmdev_ctx_t *ctx, 765 ais2dw12_i2c_disable_t *val); 766 767 typedef enum 768 { 769 AIS2DW12_PULL_UP_CONNECT = 0, 770 AIS2DW12_PULL_UP_DISCONNECT = 1, 771 } ais2dw12_cs_pu_disc_t; 772 int32_t ais2dw12_cs_mode_set(const stmdev_ctx_t *ctx, 773 ais2dw12_cs_pu_disc_t val); 774 int32_t ais2dw12_cs_mode_get(const stmdev_ctx_t *ctx, 775 ais2dw12_cs_pu_disc_t *val); 776 777 typedef enum 778 { 779 AIS2DW12_ACTIVE_HIGH = 0, 780 AIS2DW12_ACTIVE_LOW = 1, 781 } ais2dw12_h_lactive_t; 782 int32_t ais2dw12_pin_polarity_set(const stmdev_ctx_t *ctx, 783 ais2dw12_h_lactive_t val); 784 int32_t ais2dw12_pin_polarity_get(const stmdev_ctx_t *ctx, 785 ais2dw12_h_lactive_t *val); 786 787 typedef enum 788 { 789 AIS2DW12_INT_PULSED = 0, 790 AIS2DW12_INT_LATCHED = 1, 791 } ais2dw12_lir_t; 792 int32_t ais2dw12_int_notification_set(const stmdev_ctx_t *ctx, 793 ais2dw12_lir_t val); 794 int32_t ais2dw12_int_notification_get(const stmdev_ctx_t *ctx, 795 ais2dw12_lir_t *val); 796 797 typedef enum 798 { 799 AIS2DW12_PUSH_PULL = 0, 800 AIS2DW12_OPEN_DRAIN = 1, 801 } ais2dw12_pp_od_t; 802 int32_t ais2dw12_pin_mode_set(const stmdev_ctx_t *ctx, 803 ais2dw12_pp_od_t val); 804 int32_t ais2dw12_pin_mode_get(const stmdev_ctx_t *ctx, 805 ais2dw12_pp_od_t *val); 806 807 int32_t ais2dw12_pin_int1_route_set(const stmdev_ctx_t *ctx, 808 ais2dw12_ctrl4_int1_t *val); 809 int32_t ais2dw12_pin_int1_route_get(const stmdev_ctx_t *ctx, 810 ais2dw12_ctrl4_int1_t *val); 811 812 int32_t ais2dw12_pin_int2_route_set(const stmdev_ctx_t *ctx, 813 ais2dw12_ctrl5_int2_t *val); 814 int32_t ais2dw12_pin_int2_route_get(const stmdev_ctx_t *ctx, 815 ais2dw12_ctrl5_int2_t *val); 816 817 int32_t ais2dw12_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); 818 int32_t ais2dw12_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); 819 820 int32_t ais2dw12_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 821 int32_t ais2dw12_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 822 823 int32_t ais2dw12_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 824 int32_t ais2dw12_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 825 826 typedef enum 827 { 828 AIS2DW12_HP_FEED = 0, 829 AIS2DW12_USER_OFFSET_FEED = 1, 830 } ais2dw12_usr_off_on_wu_t; 831 int32_t ais2dw12_wkup_feed_data_set(const stmdev_ctx_t *ctx, 832 ais2dw12_usr_off_on_wu_t val); 833 int32_t ais2dw12_wkup_feed_data_get(const stmdev_ctx_t *ctx, 834 ais2dw12_usr_off_on_wu_t *val); 835 836 typedef enum 837 { 838 AIS2DW12_NO_DETECTION = 0, 839 AIS2DW12_DETECT_ACT_INACT = 1, 840 AIS2DW12_DETECT_STAT_MOTION = 3, 841 } ais2dw12_sleep_on_t; 842 int32_t ais2dw12_act_mode_set(const stmdev_ctx_t *ctx, 843 ais2dw12_sleep_on_t val); 844 int32_t ais2dw12_act_mode_get(const stmdev_ctx_t *ctx, 845 ais2dw12_sleep_on_t *val); 846 847 int32_t ais2dw12_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 848 int32_t ais2dw12_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 849 850 int32_t ais2dw12_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 851 int32_t ais2dw12_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 852 853 int32_t ais2dw12_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 854 int32_t ais2dw12_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 855 856 int32_t ais2dw12_6d_src_get(const stmdev_ctx_t *ctx, 857 ais2dw12_sixd_src_t *val); 858 859 typedef enum 860 { 861 AIS2DW12_ODR_DIV_2_FEED = 0, 862 AIS2DW12_LPF2_FEED = 1, 863 } ais2dw12_lpass_on6d_t; 864 int32_t ais2dw12_6d_feed_data_set(const stmdev_ctx_t *ctx, 865 ais2dw12_lpass_on6d_t val); 866 int32_t ais2dw12_6d_feed_data_get(const stmdev_ctx_t *ctx, 867 ais2dw12_lpass_on6d_t *val); 868 869 int32_t ais2dw12_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 870 int32_t ais2dw12_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 871 872 typedef enum 873 { 874 AIS2DW12_FF_TSH_5LSb_FS2g = 0, 875 AIS2DW12_FF_TSH_7LSb_FS2g = 1, 876 AIS2DW12_FF_TSH_8LSb_FS2g = 2, 877 AIS2DW12_FF_TSH_10LSb_FS2g = 3, 878 AIS2DW12_FF_TSH_11LSb_FS2g = 4, 879 AIS2DW12_FF_TSH_13LSb_FS2g = 5, 880 AIS2DW12_FF_TSH_15LSb_FS2g = 6, 881 AIS2DW12_FF_TSH_16LSb_FS2g = 7, 882 } ais2dw12_ff_ths_t; 883 int32_t ais2dw12_ff_threshold_set(const stmdev_ctx_t *ctx, 884 ais2dw12_ff_ths_t val); 885 int32_t ais2dw12_ff_threshold_get(const stmdev_ctx_t *ctx, 886 ais2dw12_ff_ths_t *val); 887 888 int32_t ais2dw12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); 889 int32_t ais2dw12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); 890 891 typedef enum 892 { 893 AIS2DW12_BYPASS_MODE = 0, 894 AIS2DW12_FIFO_MODE = 1, 895 AIS2DW12_STREAM_TO_FIFO_MODE = 3, 896 AIS2DW12_BYPASS_TO_STREAM_MODE = 4, 897 AIS2DW12_STREAM_MODE = 6, 898 } ais2dw12_fmode_t; 899 int32_t ais2dw12_fifo_mode_set(const stmdev_ctx_t *ctx, 900 ais2dw12_fmode_t val); 901 int32_t ais2dw12_fifo_mode_get(const stmdev_ctx_t *ctx, 902 ais2dw12_fmode_t *val); 903 904 int32_t ais2dw12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val); 905 906 int32_t ais2dw12_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 907 908 int32_t ais2dw12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 909 910 /** 911 * @} 912 * 913 */ 914 915 #ifdef __cplusplus 916 } 917 #endif 918 919 #endif /*AIS2DW12_REGS_H */ 920 921 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 922
