1 /*
2  * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <lib/utils_def.h>
8 #include <plat/common/common_def.h>
9 
10 #define PLATFORM_LINKER_FORMAT		"elf64-littleaarch64"
11 #define PLATFORM_LINKER_ARCH		aarch64
12 
13 #define PLATFORM_STACK_SIZE		0x800
14 #define CACHE_WRITEBACK_GRANULE		64
15 
16 #define PLAT_PRIMARY_CPU		U(0x0)
17 #define PLATFORM_MAX_CPU_PER_CLUSTER	U(4)
18 #define PLATFORM_CLUSTER_COUNT		U(1)
19 #define PLATFORM_CLUSTER0_CORE_COUNT	U(4)
20 #define PLATFORM_CLUSTER1_CORE_COUNT	U(0)
21 #define PLATFORM_CORE_COUNT		(PLATFORM_CLUSTER0_CORE_COUNT)
22 
23 #define IMX_PWR_LVL0			MPIDR_AFFLVL0
24 #define IMX_PWR_LVL1			MPIDR_AFFLVL1
25 #define IMX_PWR_LVL2			MPIDR_AFFLVL2
26 
27 #define PWR_DOMAIN_AT_MAX_LVL		U(1)
28 #define PLAT_MAX_PWR_LVL		U(2)
29 #define PLAT_MAX_OFF_STATE		U(4)
30 #define PLAT_MAX_RET_STATE		U(1)
31 
32 #define PLAT_WAIT_RET_STATE		PLAT_MAX_RET_STATE
33 #define PLAT_WAIT_OFF_STATE		U(2)
34 #define PLAT_STOP_OFF_STATE		U(3)
35 
36 #define BL31_BASE			U(0x910000)
37 #define BL31_SIZE			SZ_64K
38 #define BL31_LIMIT			(BL31_BASE + BL31_SIZE)
39 
40 /* non-secure uboot base */
41 #define PLAT_NS_IMAGE_OFFSET		U(0x40200000)
42 #define BL32_FDT_OVERLAY_ADDR		(PLAT_NS_IMAGE_OFFSET + 0x3000000)
43 
44 /* GICv3 base address */
45 #define PLAT_GICD_BASE			U(0x38800000)
46 #define PLAT_GICR_BASE			U(0x38880000)
47 
48 #define PLAT_VIRT_ADDR_SPACE_SIZE	(1ull << 32)
49 #define PLAT_PHY_ADDR_SPACE_SIZE	(1ull << 32)
50 
51 #ifdef SPD_trusty
52 #define MAX_XLAT_TABLES			5
53 #define MAX_MMAP_REGIONS		15
54 #else
55 #define MAX_XLAT_TABLES			4
56 #define MAX_MMAP_REGIONS		14
57 #endif
58 
59 #define HAB_RVT_BASE			U(0x00000880) /* HAB_RVT for i.MX8MQ */
60 
61 #define IMX_BOOT_UART_CLK_IN_HZ		25000000 /* Select 25Mhz oscillator */
62 #define PLAT_CRASH_UART_BASE		IMX_BOOT_UART_BASE
63 #define PLAT_CRASH_UART_CLK_IN_HZ	25000000
64 #define IMX_CONSOLE_BAUDRATE		115200
65 
66 #define IMX_AIPS_BASE			U(0x30200000)
67 #define IMX_AIPS_SIZE			U(0xC00000)
68 #define IMX_AIPS1_BASE			U(0x30200000)
69 #define IMX_AIPS3_ARB_BASE		U(0x30800000)
70 #define IMX_OCOTP_BASE			U(0x30350000)
71 #define IMX_ANAMIX_BASE			U(0x30360000)
72 #define IMX_CCM_BASE			U(0x30380000)
73 #define IMX_SRC_BASE			U(0x30390000)
74 #define IMX_GPC_BASE			U(0x303a0000)
75 #define IMX_RDC_BASE			U(0x303d0000)
76 #define IMX_CSU_BASE			U(0x303e0000)
77 #define IMX_WDOG_BASE			U(0x30280000)
78 #define IMX_SNVS_BASE			U(0x30370000)
79 #define IMX_NOC_BASE			U(0x32700000)
80 #define IMX_TZASC_BASE			U(0x32F80000)
81 #define IMX_CAAM_BASE			U(0x30900000)
82 #define IMX_IOMUX_GPR_BASE		U(0x30340000)
83 #define IMX_DDRC_BASE			U(0x3d400000)
84 #define IMX_DDRPHY_BASE			U(0x3c000000)
85 #define IMX_DDR_IPS_BASE		U(0x3d000000)
86 #define IMX_DDR_IPS_SIZE		U(0x1800000)
87 #define IMX_DRAM_BASE			U(0x40000000)
88 #define IMX_DRAM_SIZE			U(0xc0000000)
89 
90 #define IMX_ROM_BASE			U(0x00000000)
91 #define IMX_ROM_SIZE			U(0x20000)
92 
93 #define AIPSTZ1_BASE			U(0x301f0000)
94 #define AIPSTZ2_BASE			U(0x305f0000)
95 #define AIPSTZ3_BASE			U(0x309f0000)
96 #define AIPSTZ4_BASE			U(0x32df0000)
97 
98 #define GPV_BASE			U(0x32000000)
99 #define GPV_SIZE			U(0x800000)
100 #define IMX_GIC_BASE			PLAT_GICD_BASE
101 #define IMX_GIC_SIZE			U(0x200000)
102 
103 #define WDOG_WSR			U(0x2)
104 #define WDOG_WCR_WDZST			BIT(0)
105 #define WDOG_WCR_WDBG			BIT(1)
106 #define WDOG_WCR_WDE			BIT(2)
107 #define WDOG_WCR_WDT			BIT(3)
108 #define WDOG_WCR_SRS			BIT(4)
109 #define WDOG_WCR_WDA			BIT(5)
110 #define WDOG_WCR_SRE			BIT(6)
111 #define WDOG_WCR_WDW			BIT(7)
112 
113 #define SRC_A53RCR0			U(0x4)
114 #define SRC_A53RCR1			U(0x8)
115 #define SRC_OTG1PHY_SCR			U(0x20)
116 #define SRC_OTG2PHY_SCR			U(0x24)
117 #define SRC_GPR1_OFFSET			U(0x74)
118 #define SRC_GPR10_OFFSET		U(0x98)
119 #define SRC_GPR10_PERSIST_SECONDARY_BOOT	BIT(30)
120 
121 #define SNVS_LPCR			U(0x38)
122 #define SNVS_LPCR_SRTC_ENV		BIT(0)
123 #define SNVS_LPCR_DP_EN			BIT(5)
124 #define SNVS_LPCR_TOP			BIT(6)
125 
126 #define SAVED_DRAM_TIMING_BASE		U(0x40000000)
127 
128 #define HW_DRAM_PLL_CFG0		(IMX_ANAMIX_BASE + 0x60)
129 #define HW_DRAM_PLL_CFG1		(IMX_ANAMIX_BASE + 0x64)
130 #define HW_DRAM_PLL_CFG2		(IMX_ANAMIX_BASE + 0x68)
131 #define DRAM_PLL_CTRL			HW_DRAM_PLL_CFG0
132 
133 #define IOMUXC_GPR10			U(0x28)
134 #define GPR_TZASC_EN			BIT(0)
135 #define GPR_TZASC_EN_LOCK		BIT(16)
136 
137 #define OCRAM_S_BASE			U(0x00180000)
138 #define OCRAM_S_SIZE			U(0x8000)
139 #define OCRAM_S_LIMIT			(OCRAM_S_BASE + OCRAM_S_SIZE)
140 
141 #define COUNTER_FREQUENCY		8333333 /* 25MHz / 3 */
142 
143 #define IMX_WDOG_B_RESET
144