1 /* 2 * Copyright (c) 2018-2020 Arm Limited. All rights reserved. 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __CMSIS_DRIVER_CONFIG_H__ 18 #define __CMSIS_DRIVER_CONFIG_H__ 19 20 #include "device_cfg.h" 21 #include "device_definition.h" 22 #include "platform_description.h" 23 #include "RTE_Device.h" 24 #include "target_cfg.h" 25 26 #define UART0_DEV UART0_PL011_DEV_NS 27 #define UART1_DEV UART1_PL011_DEV_NS 28 29 #define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S 30 #define MPC_ISRAM1_DEV MPC_ISRAM1_DEV_S 31 #define MPC_ISRAM2_DEV MPC_ISRAM2_DEV_S 32 #define MPC_ISRAM3_DEV MPC_ISRAM3_DEV_S 33 #define MPC_CODE_SRAM_DEV MPC_CODE_SRAM_DEV_S 34 #define MPC_QSPI_DEV MPC_QSPI_DEV_S 35 #define MPC_EFLASH0_DEV MPC_EFLASH0_DEV_S 36 #define MPC_EFLASH1_DEV MPC_EFLASH1_DEV_S 37 38 #define AHB_PPC0_DEV AHB_PPC0_DEV_S 39 #define AHB_PPCEXP0_DEV AHB_PPCEXP0_DEV_S 40 #define AHB_PPCEXP1_DEV AHB_PPCEXP1_DEV_S 41 #define AHB_PPCEXP2_DEV AHB_PPCEXP2_DEV_S 42 #define AHB_PPCEXP3_DEV AHB_PPCEXP3_DEV_S 43 #define APB_PPC0_DEV APB_PPC0_DEV_S 44 #define APB_PPC1_DEV APB_PPC1_DEV_S 45 #define APB_PPCEXP0_DEV APB_PPCEXP0_DEV_S 46 #define APB_PPCEXP1_DEV APB_PPCEXP1_DEV_S 47 #define APB_PPCEXP2_DEV APB_PPCEXP2_DEV_S 48 #define APB_PPCEXP3_DEV APB_PPCEXP3_DEV_S 49 50 #define MUSCA_B1_SCC_DEV MUSCA_B1_SCC_DEV_S 51 52 #define EFLASH0_DEV GFC100_EFLASH0_DEV_S 53 #define FLASH0_DEV MT25QL_DEV_S 54 55 #endif /* __CMSIS_DRIVER_CONFIG_H__ */ 56
