1 /* 2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the 14 * distribution. 15 * 16 * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 #ifndef __HW_AES_H__ 35 #define __HW_AES_H__ 36 37 //***************************************************************************** 38 // 39 // The following are defines for the AES_P register offsets. 40 // 41 //***************************************************************************** 42 #define AES_O_KEY2_6 0x00000000 // XTS second key / CBC-MAC third 43 // key 44 #define AES_O_KEY2_7 0x00000004 // XTS second key (MSW for 256-bit 45 // key) / CBC-MAC third key (MSW) 46 #define AES_O_KEY2_4 0x00000008 // XTS / CCM second key / CBC-MAC 47 // third key (LSW) 48 #define AES_O_KEY2_5 0x0000000C // XTS second key (MSW for 192-bit 49 // key) / CBC-MAC third key 50 #define AES_O_KEY2_2 0x00000010 // XTS / CCM / CBC-MAC second key / 51 // Hash Key input 52 #define AES_O_KEY2_3 0x00000014 // XTS second key (MSW for 128-bit 53 // key) + CCM/CBC-MAC second key 54 // (MSW) / Hash Key input (MSW) 55 #define AES_O_KEY2_0 0x00000018 // XTS / CCM / CBC-MAC second key 56 // (LSW) / Hash Key input (LSW) 57 #define AES_O_KEY2_1 0x0000001C // XTS / CCM / CBC-MAC second key / 58 // Hash Key input 59 #define AES_O_KEY1_6 0x00000020 // Key (LSW for 256-bit key) 60 #define AES_O_KEY1_7 0x00000024 // Key (MSW for 256-bit key) 61 #define AES_O_KEY1_4 0x00000028 // Key (LSW for 192-bit key) 62 #define AES_O_KEY1_5 0x0000002C // Key (MSW for 192-bit key) 63 #define AES_O_KEY1_2 0x00000030 // Key 64 #define AES_O_KEY1_3 0x00000034 // Key (MSW for 128-bit key) 65 #define AES_O_KEY1_0 0x00000038 // Key (LSW for 128-bit key) 66 #define AES_O_KEY1_1 0x0000003C // Key 67 #define AES_O_IV_IN_0 0x00000040 // Initialization Vector input 68 // (LSW) 69 #define AES_O_IV_IN_1 0x00000044 // Initialization vector input 70 #define AES_O_IV_IN_2 0x00000048 // Initialization vector input 71 #define AES_O_IV_IN_3 0x0000004C // Initialization Vector input 72 // (MSW) 73 #define AES_O_CTRL 0x00000050 // register determines the mode of 74 // operation of the AES Engine 75 #define AES_O_C_LENGTH_0 0x00000054 // Crypto data length registers 76 // (LSW and MSW) store the 77 // cryptographic data length in 78 // bytes for all modes. Once 79 // processing with this context is 80 // started@@ this length decrements 81 // to zero. Data lengths up to (2^61 82 // – 1) bytes are allowed. For GCM@@ 83 // any value up to 2^36 - 32 bytes 84 // can be used. This is because a 85 // 32-bit counter mode is used; the 86 // maximum number of 128-bit blocks 87 // is 2^32 – 2@@ resulting in a 88 // maximum number of bytes of 2^36 - 89 // 32. A write to this register 90 // triggers the engine to start 91 // using this context. This is valid 92 // for all modes except GCM and CCM. 93 // Note that for the combined 94 // modes@@ this length does not 95 // include the authentication only 96 // data; the authentication length 97 // is specified in the 98 // AES_AUTH_LENGTH register below. 99 // All modes must have a length > 0. 100 // For the combined modes@@ it is 101 // allowed to have one of the 102 // lengths equal to zero. For the 103 // basic encryption modes 104 // (ECB/CBC/CTR/ICM/CFB128) it is 105 // allowed to program zero to the 106 // length field; in that case the 107 // length is assumed infinite. All 108 // data must be byte (8-bit) 109 // aligned; bit aligned data streams 110 // are not supported by the AES 111 // Engine. For a Host read 112 // operation@@ these registers 113 // return all-zeroes. 114 #define AES_O_C_LENGTH_1 0x00000058 // Crypto data length registers 115 // (LSW and MSW) store the 116 // cryptographic data length in 117 // bytes for all modes. Once 118 // processing with this context is 119 // started@@ this length decrements 120 // to zero. Data lengths up to (2^61 121 // – 1) bytes are allowed. For GCM@@ 122 // any value up to 2^36 - 32 bytes 123 // can be used. This is because a 124 // 32-bit counter mode is used; the 125 // maximum number of 128-bit blocks 126 // is 2^32 – 2@@ resulting in a 127 // maximum number of bytes of 2^36 - 128 // 32. A write to this register 129 // triggers the engine to start 130 // using this context. This is valid 131 // for all modes except GCM and CCM. 132 // Note that for the combined 133 // modes@@ this length does not 134 // include the authentication only 135 // data; the authentication length 136 // is specified in the 137 // AES_AUTH_LENGTH register below. 138 // All modes must have a length > 0. 139 // For the combined modes@@ it is 140 // allowed to have one of the 141 // lengths equal to zero. For the 142 // basic encryption modes 143 // (ECB/CBC/CTR/ICM/CFB128) it is 144 // allowed to program zero to the 145 // length field; in that case the 146 // length is assumed infinite. All 147 // data must be byte (8-bit) 148 // aligned; bit aligned data streams 149 // are not supported by the AES 150 // Engine. For a Host read 151 // operation@@ these registers 152 // return all-zeroes. 153 #define AES_O_AUTH_LENGTH 0x0000005C // AAD data length. The 154 // authentication length register 155 // store the authentication data 156 // length in bytes for combined 157 // modes only (GCM or CCM) Supported 158 // AAD-lengths for CCM are from 0 to 159 // (2^16 - 2^8) bytes. For GCM any 160 // value up to (2^32 - 1) bytes can 161 // be used. Once processing with 162 // this context is started@@ this 163 // length decrements to zero. A 164 // write to this register triggers 165 // the engine to start using this 166 // context for GCM and CCM. For XTS 167 // this register is optionally used 168 // to load ‘j’. Loading of ‘j’ is 169 // only required if ‘j’ != 0. ‘j’ is 170 // a 28-bit value and must be 171 // written to bits [31-4] of this 172 // register. ‘j’ represents the 173 // sequential number of the 128-bit 174 // block inside the data unit. For 175 // the first block in a unit@@ this 176 // value is zero. It is not required 177 // to provide a ‘j’ for each new 178 // data block within a unit. Note 179 // that it is possible to start with 180 // a ‘j’ unequal to zero; refer to 181 // Table 4 for more details. For a 182 // Host read operation@@ these 183 // registers return all-zeroes. 184 #define AES_O_DATA_IN_0 0x00000060 // Data register to read and write 185 // plaintext/ciphertext (MSW) 186 #define AES_O_DATA_IN_1 0x00000064 // Data register to read and write 187 // plaintext/ciphertext 188 #define AES_O_DATA_IN_2 0x00000068 // Data register to read and write 189 // plaintext/ciphertext 190 #define AES_O_DATA_IN_3 0x0000006C // Data register to read and write 191 // plaintext/ciphertext (LSW) 192 #define AES_O_TAG_OUT_0 0x00000070 193 #define AES_O_TAG_OUT_1 0x00000074 194 #define AES_O_TAG_OUT_2 0x00000078 195 #define AES_O_TAG_OUT_3 0x0000007C 196 #define AES_O_REVISION 0x00000080 // Register AES_REVISION 197 #define AES_O_SYSCONFIG 0x00000084 // Register AES_SYSCONFIG.This 198 // register configures the DMA 199 // signals and controls the IDLE and 200 // reset logic 201 #define AES_O_SYSSTATUS 0x00000088 202 #define AES_O_IRQSTATUS 0x0000008C // This register indicates the 203 // interrupt status. If one of the 204 // interrupt bits is set the 205 // interrupt output will be asserted 206 #define AES_O_IRQENABLE 0x00000090 // This register contains an enable 207 // bit for each unique interrupt 208 // generated by the module. It 209 // matches the layout of 210 // AES_IRQSTATUS register. An 211 // interrupt is enabled when the bit 212 // in this register is set to ‘1’. 213 // An interrupt that is enabled is 214 // propagated to the SINTREQUEST_x 215 // output. All interrupts need to be 216 // enabled explicitly by writing 217 // this register. 218 219 220 221 //****************************************************************************** 222 // 223 // The following are defines for the bit fields in the AES_O_KEY2_6 register. 224 // 225 //****************************************************************************** 226 #define AES_KEY2_6_KEY_M 0xFFFFFFFF // key data 227 #define AES_KEY2_6_KEY_S 0 228 //****************************************************************************** 229 // 230 // The following are defines for the bit fields in the AES_O_KEY2_7 register. 231 // 232 //****************************************************************************** 233 #define AES_KEY2_7_KEY_M 0xFFFFFFFF // key data 234 #define AES_KEY2_7_KEY_S 0 235 //****************************************************************************** 236 // 237 // The following are defines for the bit fields in the AES_O_KEY2_4 register. 238 // 239 //****************************************************************************** 240 #define AES_KEY2_4_KEY_M 0xFFFFFFFF // key data 241 #define AES_KEY2_4_KEY_S 0 242 //****************************************************************************** 243 // 244 // The following are defines for the bit fields in the AES_O_KEY2_5 register. 245 // 246 //****************************************************************************** 247 #define AES_KEY2_5_KEY_M 0xFFFFFFFF // key data 248 #define AES_KEY2_5_KEY_S 0 249 //****************************************************************************** 250 // 251 // The following are defines for the bit fields in the AES_O_KEY2_2 register. 252 // 253 //****************************************************************************** 254 #define AES_KEY2_2_KEY_M 0xFFFFFFFF // key data 255 #define AES_KEY2_2_KEY_S 0 256 //****************************************************************************** 257 // 258 // The following are defines for the bit fields in the AES_O_KEY2_3 register. 259 // 260 //****************************************************************************** 261 #define AES_KEY2_3_KEY_M 0xFFFFFFFF // key data 262 #define AES_KEY2_3_KEY_S 0 263 //****************************************************************************** 264 // 265 // The following are defines for the bit fields in the AES_O_KEY2_0 register. 266 // 267 //****************************************************************************** 268 #define AES_KEY2_0_KEY_M 0xFFFFFFFF // key data 269 #define AES_KEY2_0_KEY_S 0 270 //****************************************************************************** 271 // 272 // The following are defines for the bit fields in the AES_O_KEY2_1 register. 273 // 274 //****************************************************************************** 275 #define AES_KEY2_1_KEY_M 0xFFFFFFFF // key data 276 #define AES_KEY2_1_KEY_S 0 277 //****************************************************************************** 278 // 279 // The following are defines for the bit fields in the AES_O_KEY1_6 register. 280 // 281 //****************************************************************************** 282 #define AES_KEY1_6_KEY_M 0xFFFFFFFF // key data 283 #define AES_KEY1_6_KEY_S 0 284 //****************************************************************************** 285 // 286 // The following are defines for the bit fields in the AES_O_KEY1_7 register. 287 // 288 //****************************************************************************** 289 #define AES_KEY1_7_KEY_M 0xFFFFFFFF // key data 290 #define AES_KEY1_7_KEY_S 0 291 //****************************************************************************** 292 // 293 // The following are defines for the bit fields in the AES_O_KEY1_4 register. 294 // 295 //****************************************************************************** 296 #define AES_KEY1_4_KEY_M 0xFFFFFFFF // key data 297 #define AES_KEY1_4_KEY_S 0 298 //****************************************************************************** 299 // 300 // The following are defines for the bit fields in the AES_O_KEY1_5 register. 301 // 302 //****************************************************************************** 303 #define AES_KEY1_5_KEY_M 0xFFFFFFFF // key data 304 #define AES_KEY1_5_KEY_S 0 305 //****************************************************************************** 306 // 307 // The following are defines for the bit fields in the AES_O_KEY1_2 register. 308 // 309 //****************************************************************************** 310 #define AES_KEY1_2_KEY_M 0xFFFFFFFF // key data 311 #define AES_KEY1_2_KEY_S 0 312 //****************************************************************************** 313 // 314 // The following are defines for the bit fields in the AES_O_KEY1_3 register. 315 // 316 //****************************************************************************** 317 #define AES_KEY1_3_KEY_M 0xFFFFFFFF // key data 318 #define AES_KEY1_3_KEY_S 0 319 //****************************************************************************** 320 // 321 // The following are defines for the bit fields in the AES_O_KEY1_0 register. 322 // 323 //****************************************************************************** 324 #define AES_KEY1_0_KEY_M 0xFFFFFFFF // key data 325 #define AES_KEY1_0_KEY_S 0 326 //****************************************************************************** 327 // 328 // The following are defines for the bit fields in the AES_O_KEY1_1 register. 329 // 330 //****************************************************************************** 331 #define AES_KEY1_1_KEY_M 0xFFFFFFFF // key data 332 #define AES_KEY1_1_KEY_S 0 333 //****************************************************************************** 334 // 335 // The following are defines for the bit fields in the AES_O_IV_IN_0 register. 336 // 337 //****************************************************************************** 338 #define AES_IV_IN_0_DATA_M 0xFFFFFFFF // IV data 339 #define AES_IV_IN_0_DATA_S 0 340 //****************************************************************************** 341 // 342 // The following are defines for the bit fields in the AES_O_IV_IN_1 register. 343 // 344 //****************************************************************************** 345 #define AES_IV_IN_1_DATA_M 0xFFFFFFFF // IV data 346 #define AES_IV_IN_1_DATA_S 0 347 //****************************************************************************** 348 // 349 // The following are defines for the bit fields in the AES_O_IV_IN_2 register. 350 // 351 //****************************************************************************** 352 #define AES_IV_IN_2_DATA_M 0xFFFFFFFF // IV data 353 #define AES_IV_IN_2_DATA_S 0 354 //****************************************************************************** 355 // 356 // The following are defines for the bit fields in the AES_O_IV_IN_3 register. 357 // 358 //****************************************************************************** 359 #define AES_IV_IN_3_DATA_M 0xFFFFFFFF // IV data 360 #define AES_IV_IN_3_DATA_S 0 361 //****************************************************************************** 362 // 363 // The following are defines for the bit fields in the AES_O_CTRL register. 364 // 365 //****************************************************************************** 366 #define AES_CTRL_CONTEXT_READY \ 367 0x80000000 // If ‘1’@@ this read-only status 368 // bit indicates that the context 369 // data registers can be overwritten 370 // and the host is permitted to 371 // write the next context. 372 373 #define AES_CTRL_SVCTXTRDY \ 374 0x40000000 // If ‘1’@@ this read-only status 375 // bit indicates that an AES 376 // authentication TAG and/or IV 377 // block(s) is/are available for the 378 // host to retrieve. This bit is 379 // only asserted if the 380 // ‘save_context’ bit is set to ‘1’. 381 // The bit is mutual exclusive with 382 // the ‘context_ready’ bit. 383 384 #define AES_CTRL_SAVE_CONTEXT 0x20000000 // This bit is used to indicate 385 // that an authentication TAG or 386 // result IV needs to be stored as a 387 // result context. If this bit is 388 // set@@ context output DMA and/or 389 // interrupt will be asserted if the 390 // operation is finished and related 391 // signals are enabled. 392 #define AES_CTRL_CCM_M 0x01C00000 // Defines “M�? that indicated the 393 // length of the authentication 394 // field for CCM operations; the 395 // authentication field length 396 // equals two times (the value of 397 // CCM-M plus one). Note that the 398 // AES Engine always returns a 399 // 128-bit authentication field@@ of 400 // which the M least significant 401 // bytes are valid. All values are 402 // supported. 403 #define AES_CTRL_CCM_S 22 404 #define AES_CTRL_CCM_L_M 0x00380000 // Defines “L�? that indicated the 405 // width of the length field for CCM 406 // operations; the length field in 407 // bytes equals the value of CMM-L 408 // plus one. Supported values for L 409 // are (programmed value): 2 (1)@@ 4 410 // (3) and 8 (7). 411 #define AES_CTRL_CCM_L_S 19 412 #define AES_CTRL_CCM 0x00040000 // AES-CCM is selected@@ this is a 413 // combined mode@@ using AES for 414 // both authentication and 415 // encryption. No additional mode 416 // selection is required. 0 Other 417 // mode selected 1 ccm mode selected 418 #define AES_CTRL_GCM_M 0x00030000 // AES-GCM mode is selected.this is 419 // a combined mode@@ using the 420 // Galois field multiplier GF(2^128) 421 // for authentication and AES-CTR 422 // mode for encryption@@ the bits 423 // specify the GCM mode. 0x0 No 424 // operation 0x1 GHASH with H loaded 425 // and Y0-encrypted forced to zero 426 // 0x2 GHASH with H loaded and 427 // Y0-encrypted calculated 428 // internally 0x3 Autonomous GHASH 429 // (both H and Y0-encrypted 430 // calculated internally) 431 #define AES_CTRL_GCM_S 16 432 #define AES_CTRL_CBCMAC 0x00008000 // AES-CBC MAC is selected@@ the 433 // Direction bit must be set to ‘1’ 434 // for this mode. 0 Other mode 435 // selected 1 cbcmac mode selected 436 #define AES_CTRL_F9 0x00004000 // AES f9 mode is selected@@ the 437 // AES key size must be set to 438 // 128-bit for this mode. 0 Other 439 // mode selected 1 f9 selected 440 #define AES_CTRL_F8 0x00002000 // AES f8 mode is selected@@ the 441 // AES key size must be set to 442 // 128-bit for this mode. 0 Other 443 // mode selected 1 f8 selected 444 #define AES_CTRL_XTS_M 0x00001800 // AES-XTS operation is selected; 445 // the bits specify the XTS mode.01 446 // = Previous/intermediate tweak 447 // value and ‘j’ loaded (value is 448 // loaded via IV@@ j is loaded via 449 // the AAD length register) 0x0 No 450 // operation 0x1 451 // Previous/intermediate tweak value 452 // and ‘j’ loaded (value is loaded 453 // via IV@@ j is loaded via the AAD 454 // length register) 0x2 Key2@@ i and 455 // j loaded (i is loaded via IV@@ j 456 // is loaded via the AAD length 457 // register) 0x3 Key2 and i loaded@@ 458 // j=0 (i is loaded via IV) 459 #define AES_CTRL_XTS_S 11 460 #define AES_CTRL_CFB 0x00000400 // full block AES cipher feedback 461 // mode (CFB128) is selected. 0 462 // other mode selected 1 cfb 463 // selected 464 #define AES_CTRL_ICM 0x00000200 // AES integer counter mode (ICM) 465 // is selected@@ this is a counter 466 // mode with a 16-bit wide counter. 467 // 0 Other mode selected. 1 ICM mode 468 // selected 469 #define AES_CTRL_CTR_WIDTH_M 0x00000180 // Specifies the counter width for 470 // AES-CTR mode 0x0 Counter is 32 471 // bits 0x1 Counter is 64 bits 0x2 472 // Counter is 128 bits 0x3 Counter 473 // is 192 bits 474 #define AES_CTRL_CTR_WIDTH_S 7 475 #define AES_CTRL_CTR 0x00000040 // Tthis bit must also be set for 476 // GCM and CCM@@ when 477 // encryption/decryption is 478 // required. 0 Other mode selected 1 479 // Counter mode 480 #define AES_CTRL_MODE 0x00000020 // ecb/cbc mode 0 ecb mode 1 cbc 481 // mode 482 #define AES_CTRL_KEY_SIZE_M 0x00000018 // key size 0x0 reserved 0x1 Key is 483 // 128 bits. 0x2 Key is 192 bits 0x3 484 // Key is 256 485 #define AES_CTRL_KEY_SIZE_S 3 486 #define AES_CTRL_DIRECTION 0x00000004 // If set to ‘1’ an encrypt 487 // operation is performed. If set to 488 // ‘0’ a decrypt operation is 489 // performed. Read 0 decryption is 490 // selected Read 1 Encryption is 491 // selected 492 #define AES_CTRL_INPUT_READY 0x00000002 // If ‘1’@@ this read-only status 493 // bit indicates that the 16-byte 494 // input buffer is empty@@ and the 495 // host is permitted to write the 496 // next block of data. 497 #define AES_CTRL_OUTPUT_READY 0x00000001 // If ‘1’@@ this read-only status 498 // bit indicates that an AES output 499 // block is available for the host 500 // to retrieve. 501 //****************************************************************************** 502 // 503 // The following are defines for the bit fields in the 504 // AES_O_C_LENGTH_0 register. 505 // 506 //****************************************************************************** 507 //****************************************************************************** 508 // 509 // The following are defines for the bit fields in the 510 // AES_O_C_LENGTH_1 register. 511 // 512 //****************************************************************************** 513 #define AES_C_LENGTH_1_LENGTH_M \ 514 0x1FFFFFFF // Data length (MSW) length 515 // registers (LSW and MSW) store the 516 // cryptographic data length in 517 // bytes for all modes. Once 518 // processing with this context is 519 // started@@ this length decrements 520 // to zero. Data lengths up to (2^61 521 // – 1) bytes are allowed. For GCM@@ 522 // any value up to 2^36 - 32 bytes 523 // can be used. This is because a 524 // 32-bit counter mode is used; the 525 // maximum number of 128-bit blocks 526 // is 2^32 – 2@@ resulting in a 527 // maximum number of bytes of 2^36 - 528 // 32. A write to this register 529 // triggers the engine to start 530 // using this context. This is valid 531 // for all modes except GCM and CCM. 532 // Note that for the combined 533 // modes@@ this length does not 534 // include the authentication only 535 // data; the authentication length 536 // is specified in the 537 // AES_AUTH_LENGTH register below. 538 // All modes must have a length > 0. 539 // For the combined modes@@ it is 540 // allowed to have one of the 541 // lengths equal to zero. For the 542 // basic encryption modes 543 // (ECB/CBC/CTR/ICM/CFB128) it is 544 // allowed to program zero to the 545 // length field; in that case the 546 // length is assumed infinite. All 547 // data must be byte (8-bit) 548 // aligned; bit aligned data streams 549 // are not supported by the AES 550 // Engine. For a Host read 551 // operation@@ these registers 552 // return all-zeroes. 553 554 #define AES_C_LENGTH_1_LENGTH_S 0 555 //****************************************************************************** 556 // 557 // The following are defines for the bit fields in the 558 // AES_O_AUTH_LENGTH register. 559 // 560 //****************************************************************************** 561 #define AES_AUTH_LENGTH_AUTH_M \ 562 0xFFFFFFFF // data 563 564 #define AES_AUTH_LENGTH_AUTH_S 0 565 //****************************************************************************** 566 // 567 // The following are defines for the bit fields in the AES_O_DATA_IN_0 register. 568 // 569 //****************************************************************************** 570 #define AES_DATA_IN_0_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt 571 #define AES_DATA_IN_0_DATA_S 0 572 //****************************************************************************** 573 // 574 // The following are defines for the bit fields in the AES_O_DATA_IN_1 register. 575 // 576 //****************************************************************************** 577 #define AES_DATA_IN_1_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt 578 #define AES_DATA_IN_1_DATA_S 0 579 //****************************************************************************** 580 // 581 // The following are defines for the bit fields in the AES_O_DATA_IN_2 register. 582 // 583 //****************************************************************************** 584 #define AES_DATA_IN_2_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt 585 #define AES_DATA_IN_2_DATA_S 0 586 //****************************************************************************** 587 // 588 // The following are defines for the bit fields in the AES_O_DATA_IN_3 register. 589 // 590 //****************************************************************************** 591 #define AES_DATA_IN_3_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt 592 #define AES_DATA_IN_3_DATA_S 0 593 //****************************************************************************** 594 // 595 // The following are defines for the bit fields in the AES_O_TAG_OUT_0 register. 596 // 597 //****************************************************************************** 598 #define AES_TAG_OUT_0_HASH_M 0xFFFFFFFF // Hash result (MSW) 599 #define AES_TAG_OUT_0_HASH_S 0 600 //****************************************************************************** 601 // 602 // The following are defines for the bit fields in the AES_O_TAG_OUT_1 register. 603 // 604 //****************************************************************************** 605 #define AES_TAG_OUT_1_HASH_M 0xFFFFFFFF // Hash result (MSW) 606 #define AES_TAG_OUT_1_HASH_S 0 607 //****************************************************************************** 608 // 609 // The following are defines for the bit fields in the AES_O_TAG_OUT_2 register. 610 // 611 //****************************************************************************** 612 #define AES_TAG_OUT_2_HASH_M 0xFFFFFFFF // Hash result (MSW) 613 #define AES_TAG_OUT_2_HASH_S 0 614 //****************************************************************************** 615 // 616 // The following are defines for the bit fields in the AES_O_TAG_OUT_3 register. 617 // 618 //****************************************************************************** 619 #define AES_TAG_OUT_3_HASH_M 0xFFFFFFFF // Hash result (LSW) 620 #define AES_TAG_OUT_3_HASH_S 0 621 //****************************************************************************** 622 // 623 // The following are defines for the bit fields in the AES_O_REVISION register. 624 // 625 //****************************************************************************** 626 #define AES_REVISION_SCHEME_M 0xC0000000 627 #define AES_REVISION_SCHEME_S 30 628 #define AES_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software 629 // compatible module family. If 630 // there is no level of software 631 // compatibility a new Func number 632 // (and hence REVISION) should be 633 // assigned. 634 #define AES_REVISION_FUNC_S 16 635 #define AES_REVISION_R_RTL_M 0x0000F800 // RTL Version (R)@@ maintained by 636 // IP design owner. RTL follows a 637 // numbering such as X.Y.R.Z which 638 // are explained in this table. R 639 // changes ONLY when: (1) PDS 640 // uploads occur which may have been 641 // due to spec changes (2) Bug fixes 642 // occur (3) Resets to '0' when X or 643 // Y changes. Design team has an 644 // internal 'Z' (customer invisible) 645 // number which increments on every 646 // drop that happens due to DV and 647 // RTL updates. Z resets to 0 when R 648 // increments. 649 #define AES_REVISION_R_RTL_S 11 650 #define AES_REVISION_X_MAJOR_M \ 651 0x00000700 // Major Revision (X)@@ maintained 652 // by IP specification owner. X 653 // changes ONLY when: (1) There is a 654 // major feature addition. An 655 // example would be adding Master 656 // Mode to Utopia Level2. The Func 657 // field (or Class/Type in old PID 658 // format) will remain the same. X 659 // does NOT change due to: (1) Bug 660 // fixes (2) Change in feature 661 // parameters. 662 663 #define AES_REVISION_X_MAJOR_S 8 664 #define AES_REVISION_CUSTOM_M 0x000000C0 665 #define AES_REVISION_CUSTOM_S 6 666 #define AES_REVISION_Y_MINOR_M \ 667 0x0000003F // Minor Revision (Y)@@ maintained 668 // by IP specification owner. Y 669 // changes ONLY when: (1) Features 670 // are scaled (up or down). 671 // Flexibility exists in that this 672 // feature scalability may either be 673 // represented in the Y change or a 674 // specific register in the IP that 675 // indicates which features are 676 // exactly available. (2) When 677 // feature creeps from Is-Not list 678 // to Is list. But this may not be 679 // the case once it sees silicon; in 680 // which case X will change. Y does 681 // NOT change due to: (1) Bug fixes 682 // (2) Typos or clarifications (3) 683 // major functional/feature 684 // change/addition/deletion. Instead 685 // these changes may be reflected 686 // via R@@ S@@ X as applicable. Spec 687 // owner maintains a 688 // customer-invisible number 'S' 689 // which changes due to: (1) 690 // Typos/clarifications (2) Bug 691 // documentation. Note that this bug 692 // is not due to a spec change but 693 // due to implementation. 694 // Nevertheless@@ the spec tracks 695 // the IP bugs. An RTL release (say 696 // for silicon PG1.1) that occurs 697 // due to bug fix should document 698 // the corresponding spec number 699 // (X.Y.S) in its release notes. 700 701 #define AES_REVISION_Y_MINOR_S 0 702 //****************************************************************************** 703 // 704 // The following are defines for the bit fields in the AES_O_SYSCONFIG register. 705 // 706 //****************************************************************************** 707 #define AES_SYSCONFIG_MACONTEXT_OUT_ON_DATA_OUT \ 708 0x00000200 // If set to '1' the two context 709 // out requests 710 // (dma_req_context_out_en@@ Bit [8] 711 // above@@ and context_out interrupt 712 // enable@@ Bit [3] of AES_IRQENABLE 713 // register) are mapped on the 714 // corresponding data output request 715 // bit. In this case@@ the original 716 // ‘context out’ bit values are 717 // ignored. 718 719 #define AES_SYSCONFIG_DMA_REQ_CONTEXT_OUT_EN \ 720 0x00000100 // If set to ‘1’@@ the DMA context 721 // output request is enabled (for 722 // context data out@@ e.g. TAG for 723 // authentication modes). 0 Dma 724 // disabled 1 Dma enabled 725 726 #define AES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \ 727 0x00000080 // If set to ‘1’@@ the DMA context 728 // request is enabled. 0 Dma 729 // disabled 1 Dma enabled 730 731 #define AES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \ 732 0x00000040 // If set to ‘1’@@ the DMA output 733 // request is enabled. 0 Dma 734 // disabled 1 Dma enabled 735 736 #define AES_SYSCONFIG_DMA_REQ_DATA_IN_EN \ 737 0x00000020 // If set to ‘1’@@ the DMA input 738 // request is enabled. 0 Dma 739 // disabled 1 Dma enabled 740 741 //****************************************************************************** 742 // 743 // The following are defines for the bit fields in the AES_O_SYSSTATUS register. 744 // 745 //****************************************************************************** 746 #define AES_SYSSTATUS_RESETDONE \ 747 0x00000001 748 749 //****************************************************************************** 750 // 751 // The following are defines for the bit fields in the AES_O_IRQSTATUS register. 752 // 753 //****************************************************************************** 754 #define AES_IRQSTATUS_CONTEXT_OUT \ 755 0x00000008 // This bit indicates 756 // authentication tag (and IV) 757 // interrupt(s) is/are active and 758 // triggers the interrupt output. 759 760 #define AES_IRQSTATUS_DATA_OUT \ 761 0x00000004 // This bit indicates data output 762 // interrupt is active and triggers 763 // the interrupt output. 764 765 #define AES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input 766 // interrupt is active and triggers 767 // the interrupt output. 768 #define AES_IRQSTATUS_CONTEX_IN \ 769 0x00000001 // This bit indicates context 770 // interrupt is active and triggers 771 // the interrupt output. 772 773 //****************************************************************************** 774 // 775 // The following are defines for the bit fields in the AES_O_IRQENABLE register. 776 // 777 //****************************************************************************** 778 #define AES_IRQENABLE_CONTEXT_OUT \ 779 0x00000008 // This bit indicates 780 // authentication tag (and IV) 781 // interrupt(s) is/are active and 782 // triggers the interrupt output. 783 784 #define AES_IRQENABLE_DATA_OUT \ 785 0x00000004 // This bit indicates data output 786 // interrupt is active and triggers 787 // the interrupt output. 788 789 #define AES_IRQENABLE_DATA_IN 0x00000002 // This bit indicates data input 790 // interrupt is active and triggers 791 // the interrupt output. 792 #define AES_IRQENABLE_CONTEX_IN \ 793 0x00000001 // This bit indicates context 794 // interrupt is active and triggers 795 // the interrupt output. 796 797 798 799 800 #endif // __HW_AES_H__ 801
