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31
32 /*!****************************************************************************
33 * @file aes.h
34 *
35 * @brief AES module header for CC23X0R5 devices
36 *
37 * @anchor ti_devices_cc23x0r5_aes_overview
38 *
39 * This module provides the low-level functions used to access the LAES128
40 * crypto engine.
41 ******************************************************************************/
42
43 #ifndef __AES_H__
44 #define __AES_H__
45
46 #include <stdint.h>
47
48 #include "../inc/hw_types.h"
49 #include "../inc/hw_memmap.h"
50 #include "../inc/hw_aes.h"
51
52 #ifdef __cplusplus
53 extern "C" {
54 #endif
55
56 #define AES_BLOCK_SIZE 16U //!< Block size in number of bytes
57 #define AES_BLOCK_SIZE_WORDS (AES_BLOCK_SIZE / 4U)
58 #define AES_BLOCK_SIZE_MULTIPLE_MASK 0xFFFFFFF0U
59 #define AES_BLOCK_SIZE_MULTIPLE_LENGTH(len) ((len)&AES_BLOCK_SIZE_MULTIPLE_MASK)
60 #define AES_NON_BLOCK_SIZE_MULTIPLE_MASK 0x0000000FU
61 #define AES_NON_BLOCK_SIZE_MULTIPLE_LENGTH(len) ((len)&AES_NON_BLOCK_SIZE_MULTIPLE_MASK)
62 #define AES_GET_NUM_BLOCKS(len) ((len) >> 4)
63 #define AES_BLOCKS_TO_BYTES(numBlocks) ((numBlocks) << 4)
64
65 #define AES_DOUBLE_BLOCK_SIZE_MULTIPLE_MASK (size_t)(0xFFFFFFE0UL)
66
67 #define AES_IV_LENGTH_BYTES AES_BLOCK_SIZE
68 #define AES_TAG_LENGTH_BYTES AES_BLOCK_SIZE
69
70 #define AES_128_KEY_LENGTH_BYTES (128U / 8U)
71
72 #define IS_WORD_ALIGNED(ptr) (((uintptr_t)(ptr) << 30) == 0U)
73
74 #define AES_ICLR_ALL \
75 ((uint32_t)AES_ICLR_AESDONE | (uint32_t)AES_ICLR_AESSTART | (uint32_t)AES_ICLR_CHADONE | (uint32_t)AES_ICLR_CHBDONE)
76
77 typedef union
78 {
79 uint32_t words[4];
80 uint8_t bytes[16];
81 } AES_BlockWordAligned;
82
83 /*! @cond NODOC */
84
85 /*!
86 * @brief Process word-aligned data for CBC-MAC or CMAC
87 *
88 * @note \c input cannot be NULL. AUTOCFG.BUSHALT must be enabled.
89 *
90 * @param [in] input Pointer word-aligned input
91 * @param [in] numBlocks Number of 16-byte blocks of data to process
92 *
93 */
94 void AESProcessAlignedBlocksCMAC(const uint32_t *input, uint32_t numBlocks);
95
96 /*!
97 * @brief Process word-aligned data for CTR
98 *
99 * @note \c input and \c output cannot be NULL. AUTOCFG.BUSHALT must be enabled.
100 *
101 * @param [in] input Pointer word-aligned input
102 * @param [out] output Pointer word-aligned output
103 * @param [in] numBlocks Number of 16-byte blocks of data to process
104 *
105 */
106 void AESProcessAlignedBlocksCTR(const uint32_t *input, uint32_t *output, uint32_t numBlocks);
107
108 /*!
109 * @brief Process word-aligned data for ECB or CBC
110 *
111 * @note \c input and \c output cannot be NULL. AUTOCFG.BUSHALT must be enabled.
112 *
113 * @param [in] input Pointer word-aligned input
114 * @param [out] output Pointer word-aligned output
115 * @param [in] numBlocks Number of 16-byte blocks of data to process
116 *
117 */
118 void AESProcessAlignedBlocksECB(const uint32_t *input, uint32_t *output, uint32_t numBlocks);
119
120 /*!
121 * @brief Copy a 16-byte block of data
122 *
123 * Copies a 16-byte block of data from the memory location pointed to by
124 * \c src to the memory location pointed to by \c dst. If \c src and \c dst
125 * are both word-aligned, the memory contents will be copied in words for
126 * optimal performance. If either \c src or \c dst are not word-aligned,
127 * the memory contents will be copied byte-by-byte.
128 *
129 * @note \c src and \c dst cannot be NULL.
130 *
131 * @param [out] dst Pointer to the memory location to copy to
132 * @param [in] src Pointer to the memory location to copy from
133 *
134 */
135 void AESCopyBlock(void *dst, const void *src);
136
137 /*!
138 * @brief Write AES key
139 *
140 * Writes the given 128-bit key to the AES KEY0..KEY3 registers.
141 *
142 * @param [in] key Array containing the key material.
143 *
144 */
AESWriteKEY(const uint8_t key[16])145 __STATIC_INLINE void AESWriteKEY(const uint8_t key[16])
146 {
147 AESCopyBlock((void *)(AES_BASE + AES_O_KEY0), key);
148 }
149
150 /*!
151 * @brief Write AES Buffer registers
152 *
153 * Writes the given values to the AES BUF0..BUF3 registers.
154 *
155 * @param [in] buf Array containing the values to be written to the
156 * buffer registers.
157 *
158 */
AESWriteBUF(const uint8_t buf[16])159 __STATIC_INLINE void AESWriteBUF(const uint8_t buf[16])
160 {
161 AESCopyBlock((void *)(AES_BASE + AES_O_BUF0), buf);
162 }
163
164 /*!
165 * @brief Write AES Buffer registers
166 *
167 * Writes the given values to the AES BUF0..BUF3 registers.
168 *
169 * @param [in] buf Word-aligned array containing the values to be written to the
170 * buffer registers.
171 *
172 */
AESWriteBUF32(const uint32_t buf[4])173 __STATIC_INLINE void AESWriteBUF32(const uint32_t buf[4])
174 {
175 HWREG(AES_BASE + AES_O_BUF0) = buf[0];
176 HWREG(AES_BASE + AES_O_BUF1) = buf[1];
177 HWREG(AES_BASE + AES_O_BUF2) = buf[2];
178 HWREG(AES_BASE + AES_O_BUF3) = buf[3];
179 }
180
181 /*!
182 * @brief Read AES Buffer registers
183 *
184 * Reads the contents from the AES BUF0..BUF3 registers.
185 *
186 * @param [out] buf Array where the buffer contents will be written to.
187 *
188 */
AESReadBUF(uint8_t buf[16])189 __STATIC_INLINE void AESReadBUF(uint8_t buf[16])
190 {
191 AESCopyBlock(buf, (const void *)(AES_BASE + AES_O_BUF0));
192 }
193
194 /*!
195 * @brief Read AES Buffer registers
196 *
197 * Reads the contents from the AES BUF0..BUF3 registers.
198 *
199 * @param [out] buf Word-aligned array where the buffer contents will be written to.
200 *
201 */
AESReadBUF32(uint32_t buf[4])202 __STATIC_INLINE void AESReadBUF32(uint32_t buf[4])
203 {
204 buf[0] = HWREG(AES_BASE + AES_O_BUF0);
205 buf[1] = HWREG(AES_BASE + AES_O_BUF1);
206 buf[2] = HWREG(AES_BASE + AES_O_BUF2);
207 buf[3] = HWREG(AES_BASE + AES_O_BUF3);
208 }
209
210 /*!
211 * @brief Write AES Text Word XOR registers
212 *
213 * Writes the given values to the AES TXTX0..TXTX3 registers.
214 *
215 * @param [in] txtxor Array containing the values to be written to the
216 * TXTX registers.
217 *
218 */
AESWriteTXTXOR(const uint8_t txtxor[16])219 __STATIC_INLINE void AESWriteTXTXOR(const uint8_t txtxor[16])
220 {
221 AESCopyBlock((void *)(AES_BASE + AES_O_TXTX0), txtxor);
222 }
223
224 /*!
225 * @brief Write AES Text Word XOR registers
226 *
227 * Writes the given values to the AES TXTX0..TXTX3 registers.
228 *
229 * @param [in] txtxor Word-aligned array containing the values to be written to the
230 * TXTX registers.
231 *
232 */
AESWriteTXTXOR32(const uint32_t txtxor[4])233 __STATIC_INLINE void AESWriteTXTXOR32(const uint32_t txtxor[4])
234 {
235 HWREG(AES_BASE + AES_O_TXTX0) = txtxor[0];
236 HWREG(AES_BASE + AES_O_TXTX1) = txtxor[1];
237 HWREG(AES_BASE + AES_O_TXTX2) = txtxor[2];
238 HWREG(AES_BASE + AES_O_TXTX3) = txtxor[3];
239 }
240
241 /*!
242 * @brief Read Text Word XOR Buffer Word registers
243 *
244 * Reads the contents from the AES TXTXBUF0..TXTXBUF0 registers.
245 *
246 * @param [out] txtxbuf Array where the TXTXBUF register contents will be
247 * written to.
248 *
249 */
AESReadTXTXBUF(uint8_t txtxbuf[16])250 __STATIC_INLINE void AESReadTXTXBUF(uint8_t txtxbuf[16])
251 {
252 AESCopyBlock(txtxbuf, (const void *)(AES_BASE + AES_O_TXTXBUF0));
253 }
254
255 /*!
256 * @brief Write AES Text Word registers
257 *
258 * Writes the given values to the AES TXT0..TXT3 registers.
259 *
260 * @param [in] txt Array containing the values to be written to the
261 * TXT registers.
262 *
263 */
AESWriteTXT(const uint8_t txt[16])264 __STATIC_INLINE void AESWriteTXT(const uint8_t txt[16])
265 {
266 AESCopyBlock((void *)(AES_BASE + AES_O_TXT0), txt);
267 }
268
269 /*!
270 * @brief Write AES Text Word registers
271 *
272 * Writes the given values to the AES TXT0..TXT3 registers.
273 *
274 * @param [in] txt Word-aligned array containing the values to be written to the
275 * TXT registers.
276 *
277 */
AESWriteTXT32(const uint32_t txt[4])278 __STATIC_INLINE void AESWriteTXT32(const uint32_t txt[4])
279 {
280 HWREG(AES_BASE + AES_O_TXT0) = txt[0];
281 HWREG(AES_BASE + AES_O_TXT1) = txt[1];
282 HWREG(AES_BASE + AES_O_TXT2) = txt[2];
283 HWREG(AES_BASE + AES_O_TXT3) = txt[3];
284 }
285
286 /*!
287 * @brief Read AES Text Word registers
288 *
289 * Reads the contents of the AES TXT0..TXT3 registers.
290 *
291 * @param [out] txt Array where the values from the TXT registers
292 * will be written to.
293 *
294 */
AESReadTXT(uint8_t txt[16])295 __STATIC_INLINE void AESReadTXT(uint8_t txt[16])
296 {
297 AESCopyBlock(txt, (const void *)(AES_BASE + AES_O_TXT0));
298 }
299
300 /*!
301 * @brief Read AES Text Word registers
302 *
303 * Reads the contents of the AES TXT0..TXT3 registers.
304 *
305 * @param [out] txt Word-aligned array where the values from the TXT registers
306 * will be written to.
307 *
308 */
AESReadTXT32(uint32_t txt[4])309 __STATIC_INLINE void AESReadTXT32(uint32_t txt[4])
310 {
311 txt[0] = HWREG(AES_BASE + AES_O_TXT0);
312 txt[1] = HWREG(AES_BASE + AES_O_TXT1);
313 txt[2] = HWREG(AES_BASE + AES_O_TXT2);
314 txt[3] = HWREG(AES_BASE + AES_O_TXT3);
315 }
316
317 /*!
318 * @brief Write AES Tag
319 *
320 * Writes the given Tag to the crypto engine.
321 *
322 * @param [in] tag Array containing the Tag.
323 *
324 */
AESWriteTag(const uint8_t tag[16])325 __STATIC_INLINE void AESWriteTag(const uint8_t tag[16])
326 {
327 AESWriteTXT(tag);
328 }
329
330 /*!
331 * @brief Write AES Tag
332 *
333 * Writes the given Tag to the crypto engine.
334 *
335 * @param [in] tag Array containing the Tag.
336 *
337 */
AESWriteTag32(const uint32_t tag[4])338 __STATIC_INLINE void AESWriteTag32(const uint32_t tag[4])
339 {
340 AESWriteTXT32(tag);
341 }
342
343 /*!
344 * @brief Read AES Tag
345 *
346 * Reads the Tag from the crypto engine.
347 *
348 * @param [out] tag Array where the Tag will be written to.
349 *
350 */
AESReadTag(uint8_t tag[16])351 __STATIC_INLINE void AESReadTag(uint8_t tag[16])
352 {
353 AESReadTXT(tag);
354 }
355
356 /*!
357 * @brief Read AES Tag
358 *
359 * Reads the Tag from the crypto engine.
360 *
361 * @param [out] tag Word-aligned array where the Tag will be written to.
362 *
363 */
AESReadTag32(uint32_t tag[4])364 __STATIC_INLINE void AESReadTag32(uint32_t tag[4])
365 {
366 AESReadTXT32(tag);
367 }
368
369 /*!
370 * @brief Set AES AutoCfg
371 *
372 * Sets the configuration for automatic HW updates to TXT and BUF.
373 *
374 * @param [in] autoCfg Specifies what configuration to be set.
375 * - @ref AES_AUTOCFG_CHBDONECLR_M
376 * - @ref AES_AUTOCFG_CHADONECLR_M
377 * - @ref AES_AUTOCFG_ECBSTARTCLR_M
378 * - @ref AES_AUTOCFG_ECBDONECLR_M
379 * - @ref AES_AUTOCFG_BUSHALT_M
380 * - @ref AES_AUTOCFG_CTRSIZE_M
381 * - @ref AES_AUTOCFG_CTRALIGN_M
382 * - @ref AES_AUTOCFG_CTRENDIAN_M
383 * - @ref AES_AUTOCFG_TRGTXT_M
384 * - @ref AES_AUTOCFG_AESSRC_M
385 * - @ref AES_AUTOCFG_TRGAES_M
386 *
387 */
AESSetAUTOCFG(uint32_t autoCfg)388 __STATIC_INLINE void AESSetAUTOCFG(uint32_t autoCfg)
389 {
390 HWREG(AES_BASE + AES_O_AUTOCFG) = autoCfg;
391 }
392
393 /*!
394 * @brief Clear the ECB trigger mask in AUTOCFG
395 *
396 * Clears the ECB trigger mask in AUTOCFG
397 *
398 */
AESClearAUTOCFGTrigger(void)399 __STATIC_INLINE void AESClearAUTOCFGTrigger(void)
400 {
401 /* Read the current AUTOCFG value */
402 uint32_t autoCfg = HWREG(AES_BASE + AES_O_AUTOCFG);
403
404 /* Clear the TRGECB bits */
405 autoCfg &= (uint32_t)~AES_AUTOCFG_TRGAES_M;
406
407 HWREG(AES_BASE + AES_O_AUTOCFG) = autoCfg;
408 }
409
410 /*!
411 * @brief Clear the BUSHALT enable in AUTOCFG
412 *
413 * Clears the BUSHALT enable in AUTOCFG
414 *
415 */
AESClearAUTOCFGBusHalt(void)416 __STATIC_INLINE void AESClearAUTOCFGBusHalt(void)
417 {
418 /* Read the current AUTOCFG value */
419 uint32_t autoCfg = HWREG(AES_BASE + AES_O_AUTOCFG);
420
421 /* Clear the BUSHALT bit */
422 autoCfg &= (uint32_t)~AES_AUTOCFG_BUSHALT_M;
423
424 HWREG(AES_BASE + AES_O_AUTOCFG) = autoCfg;
425 }
426
427 /*!
428 * @brief Get AES Status
429 *
430 * Gets the state of the AES Accelerator.
431 *
432 * @return The state of the AES Accelerator:
433 * - @ref AES_STA_STATE_BUSY
434 * - @ref AES_STA_STATE_IDLE
435 */
AESGetStatus(void)436 __STATIC_INLINE uint32_t AESGetStatus(void)
437 {
438 return (HWREG(AES_BASE + AES_O_STA) & AES_STA_STATE_M);
439 }
440
441 /*!
442 * @brief Set AES Trigger
443 *
444 * Sets the operations to be manually triggered.
445 *
446 * @param [in] triggerMask Specifies which operations to be triggered.
447 * - @ref AES_TRG_DMACHA
448 * - @ref AES_TRG_DMACHB
449 * - @ref AES_TRG_AESOP_TXTXBUF
450 * - @ref AES_TRG_AESOP_BUF
451 * - @ref AES_TRG_AESOP_TXT
452 *
453 */
AESSetTrigger(uint32_t triggerMask)454 __STATIC_INLINE void AESSetTrigger(uint32_t triggerMask)
455 {
456 HWREG(AES_BASE + AES_O_TRG) = triggerMask;
457 }
458
459 /*!
460 * @brief Abort AES operation
461 *
462 * Aborts an ongoing AES operation.
463 *
464 * @note An abort will clear TXT, BUF, DMA, AUTOCFG registers.
465 *
466 */
AESAbort(void)467 __STATIC_INLINE void AESAbort(void)
468 {
469 HWREG(AES_BASE + AES_O_ABORT) = AES_ABORT_ABORTAES_SET;
470 }
471
472 /*!
473 * @brief Clear AES TXT registers
474 *
475 * Clears the contents of TXT registers, if STATE = IDLE.
476 * Else, the contents remain unchanged.
477 *
478 */
AESClearTXT(void)479 __STATIC_INLINE void AESClearTXT(void)
480 {
481 HWREG(AES_BASE + AES_O_CLR) = AES_CLR_TXT_M;
482 }
483
484 /*!
485 * @brief Clear AES BUF registers
486 *
487 * Clears the contents of BUF registers, if STATE = IDLE.
488 * Else, the contents remain unchanged.
489 *
490 */
AESClearBUF(void)491 __STATIC_INLINE void AESClearBUF(void)
492 {
493 HWREG(AES_BASE + AES_O_CLR) = AES_CLR_BUF_M;
494 }
495
496 /*!
497 * @brief Clear AES TXT & BUF registers
498 *
499 * Clears the contents of TXT and BUF registers, if STATE = IDLE.
500 * Else, the contents remain unchanged.
501 *
502
503 */
AESClearTXTAndBUF(void)504 __STATIC_INLINE void AESClearTXTAndBUF(void)
505 {
506 HWREG(AES_BASE + AES_O_CLR) = AES_CLR_TXT_M | AES_CLR_BUF_M;
507 }
508
509 /*!
510 * @brief Write AES IV
511 *
512 * Writes the given IV to the crypto engine.
513 *
514 * @param [in] iv Array containing the IV.
515 *
516 */
AESWriteIV(const uint8_t iv[16])517 __STATIC_INLINE void AESWriteIV(const uint8_t iv[16])
518 {
519 AESWriteTXT(iv);
520 }
521
522 /*!
523 * @brief Write AES IV
524 *
525 * Writes the given IV to the crypto engine.
526 *
527 * @param [in] iv Word-aligned array containing the IV.
528 *
529 */
AESWriteIV32(const uint32_t iv[4])530 __STATIC_INLINE void AESWriteIV32(const uint32_t iv[4])
531 {
532 AESWriteTXT32(iv);
533 }
534
535 /*!
536 * @brief Clear AES IV
537 *
538 * Clears the IV in crypto engine.
539 *
540 */
AESClearIV(void)541 __STATIC_INLINE void AESClearIV(void)
542 {
543 AESClearTXT();
544 }
545
546 /*!
547 * @brief Read AES IV
548 *
549 * Reads the IV from the crypto engine.
550 *
551 * @param [out] iv Array where the IV will be written to.
552 *
553 */
AESReadIV(uint8_t iv[16])554 __STATIC_INLINE void AESReadIV(uint8_t iv[16])
555 {
556 AESReadTXT(iv);
557 }
558
559 /*!
560 * @brief Read AES IV
561 *
562 * Reads the IV from the crypto engine.
563 *
564 * @param [out] iv Word-aligned array where the IV will be written to.
565 *
566 */
AESReadIV32(uint32_t iv[4])567 __STATIC_INLINE void AESReadIV32(uint32_t iv[4])
568 {
569 AESReadTXT32(iv);
570 }
571
572 /*!
573 * @brief Get AES Raw Interrupt Status
574 *
575 * Gets the current Raw Interrupt Status
576 *
577 * @return The Raw Interrupt Status:
578 * - @ref AES_RIS_CHBDONE_M
579 * - @ref AES_RIS_CHADONE_M
580 * - @ref AES_RIS_ECBSTART_M
581 * - @ref AES_RIS_ECBDONE_M
582 */
AESGetRawInterruptStatus(void)583 __STATIC_INLINE uint32_t AESGetRawInterruptStatus(void)
584 {
585 return HWREG(AES_BASE + AES_O_RIS);
586 }
587
588 /*!
589 * @brief Set AES Interrupt
590 *
591 * Sets one or more AES Interrupts.
592 *
593 * @param [in] intFlags Specifies which interrupt(s) to be set.
594 * - @ref AES_ISET_CHBDONE_M
595 * - @ref AES_ISET_CHADONE_M
596 * - @ref AES_ISET_ECBSTART_M
597 * - @ref AES_ISET_ECBDONE_M
598 *
599
600 */
AESSetInterrupt(uint32_t intFlags)601 __STATIC_INLINE void AESSetInterrupt(uint32_t intFlags)
602 {
603 HWREG(AES_BASE + AES_O_ISET) = intFlags;
604 }
605
606 /*!
607 * @brief Clear AES Interrupt
608 *
609 * Clears one or more AES Interrupts.
610 *
611 * @param [in] intFlags Specifies which interrupt(s) to be cleared.
612 * - @ref AES_ICLR_CHBDONE_M
613 * - @ref AES_ICLR_CHADONE_M
614 * - @ref AES_ICLR_AESSTART_M
615 * - @ref AES_ICLR_AESDONE_M
616 *
617 */
AESClearInterrupt(uint32_t intFlags)618 __STATIC_INLINE void AESClearInterrupt(uint32_t intFlags)
619 {
620 HWREG(AES_BASE + AES_O_ICLR) = intFlags;
621 }
622
623 /*!
624 * @brief Get AES Masked Interrupt Status
625 *
626 * Gets the Masked Interrupt Status.
627 *
628 * @return The Masked Interrupt Status.
629 * - @ref AES_MIS_CHBDONE_M
630 * - @ref AES_MIS_CHADONE_M
631 * - @ref AES_MIS_ECBSTART_M
632 * - @ref AES_MIS_ECBDONE_M
633 */
AESGetMaskedInterruptStatus(void)634 __STATIC_INLINE uint32_t AESGetMaskedInterruptStatus(void)
635 {
636 return HWREG(AES_BASE + AES_O_MIS);
637 }
638
639 /*!
640 * @brief Set AES IMASK
641 *
642 * Enables/disables interrupts.
643 *
644 * @param [in] intFlags Specifies which interrupts to be enabled/disabled.
645 * - @ref AES_IMASK_CHBDONE_M
646 * - @ref AES_IMASK_CHADONE_M
647 * - @ref AES_IMASK_ECBSTART_M
648 * - @ref AES_IMASK_ECBDONE_M
649 *
650 */
AESSetIMASK(uint32_t intFlags)651 __STATIC_INLINE void AESSetIMASK(uint32_t intFlags)
652 {
653 HWREG(AES_BASE + AES_O_IMASK) = intFlags;
654 }
655
656 /*!
657 * @brief Setup AES DMA
658 *
659 * Setup the DMA for the AES engine
660 *
661 * @param [in] dmaConfig Specifies the DMA configuration for done side-effects,
662 * addresses and triggers for DMA channel A & B.
663 * - @ref AES_DMA_DONEACT_M
664 * - @ref AES_DMA_ADRCHA_M
665 * - @ref AES_DMA_TRGCHA_M
666 * - @ref AES_DMA_ADRCHB_M
667 * - @ref AES_DMA_TRGCHB_M
668 *
669 */
AESSetupDMA(uint32_t dmaConfig)670 __STATIC_INLINE void AESSetupDMA(uint32_t dmaConfig)
671 {
672 HWREG(AES_BASE + AES_O_DMA) = dmaConfig;
673 }
674
675 /*!
676 * @brief Disable DMA
677 *
678 * Disables the DMA for the crypto engine
679 *
680 */
AESDisableDMA(void)681 __STATIC_INLINE void AESDisableDMA(void)
682 {
683 HWREG(AES_BASE + AES_O_DMA) = AES_DMA_DONEACT_DIS | AES_DMA_TRGCHB_DIS | AES_DMA_TRGCHA_DIS;
684 }
685
686 /*! @endcond */
687
688 #ifdef __cplusplus
689 }
690 #endif
691
692 #endif /* __AES_H__ */
693
