1 /* 2 * Copyright (c) 2018 Analog Devices Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_DRIVERS_SENSOR_ADXL372_ADXL372_H_ 8 #define ZEPHYR_DRIVERS_SENSOR_ADXL372_ADXL372_H_ 9 10 #include <zephyr/types.h> 11 #include <device.h> 12 #include <drivers/gpio.h> 13 #include <drivers/spi.h> 14 #include <drivers/i2c.h> 15 #include <sys/util.h> 16 17 /* 18 * ADXL372 registers definition 19 */ 20 #define ADXL372_DEVID 0x00u /* Analog Devices accelerometer ID */ 21 #define ADXL372_DEVID_MST 0x01u /* Analog Devices MEMS device ID */ 22 #define ADXL372_PARTID 0x02u /* Device ID */ 23 #define ADXL372_REVID 0x03u /* product revision ID*/ 24 #define ADXL372_STATUS_1 0x04u /* Status register 1 */ 25 #define ADXL372_STATUS_2 0x05u /* Status register 2 */ 26 #define ADXL372_FIFO_ENTRIES_2 0x06u /* Valid data samples in the FIFO */ 27 #define ADXL372_FIFO_ENTRIES_1 0x07u /* Valid data samples in the FIFO */ 28 #define ADXL372_X_DATA_H 0x08u /* X-axis acceleration data [11:4] */ 29 #define ADXL372_X_DATA_L 0x09u /* X-axis acceleration data [3:0] */ 30 #define ADXL372_Y_DATA_H 0x0Au /* Y-axis acceleration data [11:4] */ 31 #define ADXL372_Y_DATA_L 0x0Bu /* Y-axis acceleration data [3:0] */ 32 #define ADXL372_Z_DATA_H 0x0Cu /* Z-axis acceleration data [11:4] */ 33 #define ADXL372_Z_DATA_L 0x0Du /* Z-axis acceleration data [3:0] */ 34 #define ADXL372_X_MAXPEAK_H 0x15u /* X-axis MaxPeak acceleration data */ 35 #define ADXL372_X_MAXPEAK_L 0x16u /* X-axis MaxPeak acceleration data */ 36 #define ADXL372_Y_MAXPEAK_H 0x17u /* Y-axis MaxPeak acceleration data */ 37 #define ADXL372_Y_MAXPEAK_L 0x18u /* Y-axis MaxPeak acceleration data */ 38 #define ADXL372_Z_MAXPEAK_H 0x19u /* Z-axis MaxPeak acceleration data */ 39 #define ADXL372_Z_MAXPEAK_L 0x1Au /* Z-axis MaxPeak acceleration data */ 40 #define ADXL372_OFFSET_X 0x20u /* X axis offset */ 41 #define ADXL372_OFFSET_Y 0x21u /* Y axis offset */ 42 #define ADXL372_OFFSET_Z 0x22u /* Z axis offset */ 43 #define ADXL372_X_THRESH_ACT_H 0x23u /* X axis Activity Threshold [15:8] */ 44 #define ADXL372_X_THRESH_ACT_L 0x24u /* X axis Activity Threshold [7:0] */ 45 #define ADXL372_Y_THRESH_ACT_H 0x25u /* Y axis Activity Threshold [15:8] */ 46 #define ADXL372_Y_THRESH_ACT_L 0x26u /* Y axis Activity Threshold [7:0] */ 47 #define ADXL372_Z_THRESH_ACT_H 0x27u /* Z axis Activity Threshold [15:8] */ 48 #define ADXL372_Z_THRESH_ACT_L 0x28u /* Z axis Activity Threshold [7:0] */ 49 #define ADXL372_TIME_ACT 0x29u /* Activity Time */ 50 #define ADXL372_X_THRESH_INACT_H 0x2Au /* X axis Inactivity Threshold */ 51 #define ADXL372_X_THRESH_INACT_L 0x2Bu /* X axis Inactivity Threshold */ 52 #define ADXL372_Y_THRESH_INACT_H 0x2Cu /* Y axis Inactivity Threshold */ 53 #define ADXL372_Y_THRESH_INACT_L 0x2Du /* Y axis Inactivity Threshold */ 54 #define ADXL372_Z_THRESH_INACT_H 0x2Eu /* Z axis Inactivity Threshold */ 55 #define ADXL372_Z_THRESH_INACT_L 0x2Fu /* Z axis Inactivity Threshold */ 56 #define ADXL372_TIME_INACT_H 0x30u /* Inactivity Time [15:8] */ 57 #define ADXL372_TIME_INACT_L 0x31u /* Inactivity Time [7:0] */ 58 #define ADXL372_X_THRESH_ACT2_H 0x32u /* X axis Activity2 Threshold [15:8] */ 59 #define ADXL372_X_THRESH_ACT2_L 0x33u /* X axis Activity2 Threshold [7:0] */ 60 #define ADXL372_Y_THRESH_ACT2_H 0x34u /* Y axis Activity2 Threshold [15:8] */ 61 #define ADXL372_Y_THRESH_ACT2_L 0x35u /* Y axis Activity2 Threshold [7:0] */ 62 #define ADXL372_Z_THRESH_ACT2_H 0x36u /* Z axis Activity2 Threshold [15:8] */ 63 #define ADXL372_Z_THRESH_ACT2_L 0x37u /* Z axis Activity2 Threshold [7:0] */ 64 #define ADXL372_HPF 0x38u /* High Pass Filter */ 65 #define ADXL372_FIFO_SAMPLES 0x39u /* FIFO Samples */ 66 #define ADXL372_FIFO_CTL 0x3Au /* FIFO Control */ 67 #define ADXL372_INT1_MAP 0x3Bu /* Interrupt 1 mapping control */ 68 #define ADXL372_INT2_MAP 0x3Cu /* Interrupt 2 mapping control */ 69 #define ADXL372_TIMING 0x3Du /* Timing */ 70 #define ADXL372_MEASURE 0x3Eu /* Measure */ 71 #define ADXL372_POWER_CTL 0x3Fu /* Power control */ 72 #define ADXL372_SELF_TEST 0x40u /* Self Test */ 73 #define ADXL372_RESET 0x41u /* Reset */ 74 #define ADXL372_FIFO_DATA 0x42u /* FIFO Data */ 75 76 #define ADXL372_DEVID_VAL 0xADu /* Analog Devices accelerometer ID */ 77 #define ADXL372_MST_DEVID_VAL 0x1Du /* Analog Devices MEMS device ID */ 78 #define ADXL372_PARTID_VAL 0xFAu /* Device ID */ 79 #define ADXL372_REVID_VAL 0x02u /* product revision ID*/ 80 #define ADXL372_RESET_CODE 0x52u /* Writing code 0x52 resets the device */ 81 82 #define ADXL372_READ 0x01u 83 #define ADXL372_REG_READ(x) (((x & 0xFF) << 1) | ADXL372_READ) 84 #define ADXL372_REG_WRITE(x) ((x & 0xFF) << 1) 85 #define ADXL372_TO_I2C_REG(x) ((x) >> 1) 86 87 /* ADXL372_POWER_CTL */ 88 #define ADXL372_POWER_CTL_INSTANT_ON_TH_MSK BIT(5) 89 #define ADXL372_POWER_CTL_INSTANT_ON_TH_MODE(x) (((x) & 0x1) << 5) 90 #define ADXL372_POWER_CTL_FIL_SETTLE_MSK BIT(4) 91 #define ADXL372_POWER_CTL_FIL_SETTLE_MODE(x) (((x) & 0x1) << 4) 92 #define ADXL372_POWER_CTL_LPF_DIS_MSK BIT(3) 93 #define ADXL372_POWER_CTL_LPF_DIS_MODE(x) (((x) & 0x1) << 3) 94 #define ADXL372_POWER_CTL_HPF_DIS_MSK BIT(2) 95 #define ADXL372_POWER_CTL_HPF_DIS_MODE(x) (((x) & 0x1) << 2) 96 #define ADXL372_POWER_CTL_MODE_MSK GENMASK(1, 0) 97 #define ADXL372_POWER_CTL_MODE(x) (((x) & 0x3) << 0) 98 99 /* ADXL372_MEASURE */ 100 #define ADXL372_MEASURE_AUTOSLEEP_MSK BIT(6) 101 #define ADXL372_MEASURE_AUTOSLEEP_MODE(x) (((x) & 0x1) << 6) 102 #define ADXL372_MEASURE_LINKLOOP_MSK GENMASK(5, 4) 103 #define ADXL372_MEASURE_LINKLOOP_MODE(x) (((x) & 0x3) << 4) 104 #define ADXL372_MEASURE_LOW_NOISE_MSK BIT(3) 105 #define ADXL372_MEASURE_LOW_NOISE_MODE(x) (((x) & 0x1) << 3) 106 #define ADXL372_MEASURE_BANDWIDTH_MSK GENMASK(2, 0) 107 #define ADXL372_MEASURE_BANDWIDTH_MODE(x) (((x) & 0x7) << 0) 108 109 /* ADXL372_TIMING */ 110 #define ADXL372_TIMING_ODR_MSK GENMASK(7, 5) 111 #define ADXL372_TIMING_ODR_MODE(x) (((x) & 0x7) << 5) 112 #define ADXL372_TIMING_WAKE_UP_RATE_MSK GENMASK(4, 2) 113 #define ADXL372_TIMING_WAKE_UP_RATE_MODE(x) (((x) & 0x7) << 2) 114 #define ADXL372_TIMING_EXT_CLK_MSK BIT(1) 115 #define ADXL372_TIMING_EXT_CLK_MODE(x) (((x) & 0x1) << 1) 116 #define ADXL372_TIMING_EXT_SYNC_MSK BIT(0) 117 #define ADXL372_TIMING_EXT_SYNC_MODE(x) (((x) & 0x1) << 0) 118 119 /* ADXL372_FIFO_CTL */ 120 #define ADXL372_FIFO_CTL_FORMAT_MSK GENMASK(5, 3) 121 #define ADXL372_FIFO_CTL_FORMAT_MODE(x) (((x) & 0x7) << 3) 122 #define ADXL372_FIFO_CTL_MODE_MSK GENMASK(2, 1) 123 #define ADXL372_FIFO_CTL_MODE_MODE(x) (((x) & 0x3) << 1) 124 #define ADXL372_FIFO_CTL_SAMPLES_MSK BIT(0) 125 #define ADXL372_FIFO_CTL_SAMPLES_MODE(x) (((x) > 0xFF) ? 1 : 0) 126 127 /* ADXL372_STATUS_1 */ 128 #define ADXL372_STATUS_1_DATA_RDY(x) (((x) >> 0) & 0x1) 129 #define ADXL372_STATUS_1_FIFO_RDY(x) (((x) >> 1) & 0x1) 130 #define ADXL372_STATUS_1_FIFO_FULL(x) (((x) >> 2) & 0x1) 131 #define ADXL372_STATUS_1_FIFO_OVR(x) (((x) >> 3) & 0x1) 132 #define ADXL372_STATUS_1_USR_NVM_BUSY(x) (((x) >> 5) & 0x1) 133 #define ADXL372_STATUS_1_AWAKE(x) (((x) >> 6) & 0x1) 134 #define ADXL372_STATUS_1_ERR_USR_REGS(x) (((x) >> 7) & 0x1) 135 136 /* ADXL372_STATUS_2 */ 137 #define ADXL372_STATUS_2_INACT(x) (((x) >> 4) & 0x1) 138 #define ADXL372_STATUS_2_ACTIVITY(x) (((x) >> 5) & 0x1) 139 #define ADXL372_STATUS_2_ACTIVITY2(x) (((x) >> 6) & 0x1) 140 141 /* ADXL372_INT1_MAP */ 142 #define ADXL372_INT1_MAP_DATA_RDY_MSK BIT(0) 143 #define ADXL372_INT1_MAP_DATA_RDY_MODE(x) (((x) & 0x1) << 0) 144 #define ADXL372_INT1_MAP_FIFO_RDY_MSK BIT(1) 145 #define ADXL372_INT1_MAP_FIFO_RDY_MODE(x) (((x) & 0x1) << 1) 146 #define ADXL372_INT1_MAP_FIFO_FULL_MSK BIT(2) 147 #define ADXL372_INT1_MAP_FIFO_FULL_MODE(x) (((x) & 0x1) << 2) 148 #define ADXL372_INT1_MAP_FIFO_OVR_MSK BIT(3) 149 #define ADXL372_INT1_MAP_FIFO_OVR_MODE(x) (((x) & 0x1) << 3) 150 #define ADXL372_INT1_MAP_INACT_MSK BIT(4) 151 #define ADXL372_INT1_MAP_INACT_MODE(x) (((x) & 0x1) << 4) 152 #define ADXL372_INT1_MAP_ACT_MSK BIT(5) 153 #define ADXL372_INT1_MAP_ACT_MODE(x) (((x) & 0x1) << 5) 154 #define ADXL372_INT1_MAP_AWAKE_MSK BIT(6) 155 #define ADXL372_INT1_MAP_AWAKE_MODE(x) (((x) & 0x1) << 6) 156 #define ADXL372_INT1_MAP_LOW_MSK BIT(7) 157 #define ADXL372_INT1_MAP_LOW_MODE(x) (((x) & 0x1) << 7) 158 159 /* ADXL372_INT2_MAP */ 160 #define ADXL372_INT2_MAP_DATA_RDY_MSK BIT(0) 161 #define ADXL372_INT2_MAP_DATA_RDY_MODE(x) (((x) & 0x1) << 0) 162 #define ADXL372_INT2_MAP_FIFO_RDY_MSK BIT(1) 163 #define ADXL372_INT2_MAP_FIFO_RDY_MODE(x) (((x) & 0x1) << 1) 164 #define ADXL372_INT2_MAP_FIFO_FULL_MSK BIT(2) 165 #define ADXL372_INT2_MAP_FIFO_FULL_MODE(x) (((x) & 0x1) << 2) 166 #define ADXL372_INT2_MAP_FIFO_OVR_MSK BIT(3) 167 #define ADXL372_INT2_MAP_FIFO_OVR_MODE(x) (((x) & 0x1) << 3) 168 #define ADXL372_INT2_MAP_INACT_MSK BIT(4) 169 #define ADXL372_INT2_MAP_INACT_MODE(x) (((x) & 0x1) << 4) 170 #define ADXL372_INT2_MAP_ACT_MSK BIT(5) 171 #define ADXL372_INT2_MAP_ACT_MODE(x) (((x) & 0x1) << 5) 172 #define ADXL372_INT2_MAP_AWAKE_MSK BIT(6) 173 #define ADXL372_INT2_MAP_AWAKE_MODE(x) (((x) & 0x1) << 6) 174 #define ADXL372_INT2_MAP_LOW_MSK BIT(7) 175 #define ADXL372_INT2_MAP_LOW_MODE(x) (((x) & 0x1) << 7) 176 177 /* ADXL372_HPF */ 178 #define ADXL372_HPF_CORNER(x) (((x) & 0x3) << 0) 179 180 enum adxl372_axis { 181 ADXL372_X_AXIS, 182 ADXL372_Y_AXIS, 183 ADXL372_Z_AXIS 184 }; 185 186 enum adxl372_op_mode { 187 ADXL372_STANDBY, 188 ADXL372_WAKE_UP, 189 ADXL372_INSTANT_ON, 190 ADXL372_FULL_BW_MEASUREMENT 191 }; 192 193 enum adxl372_bandwidth { 194 ADXL372_BW_200HZ, 195 ADXL372_BW_400HZ, 196 ADXL372_BW_800HZ, 197 ADXL372_BW_1600HZ, 198 ADXL372_BW_3200HZ, 199 ADXL372_BW_LPF_DISABLED = 0xC, 200 }; 201 202 enum adxl372_hpf_corner { 203 ADXL372_HPF_CORNER_0, 204 ADXL372_HPF_CORNER_1, 205 ADXL372_HPF_CORNER_2, 206 ADXL372_HPF_CORNER_3, 207 ADXL372_HPF_DISABLED, 208 }; 209 210 enum adxl372_act_proc_mode { 211 ADXL372_DEFAULT, 212 ADXL372_LINKED, 213 ADXL372_LOOPED 214 }; 215 216 enum adxl372_odr { 217 ADXL372_ODR_400HZ, 218 ADXL372_ODR_800HZ, 219 ADXL372_ODR_1600HZ, 220 ADXL372_ODR_3200HZ, 221 ADXL372_ODR_6400HZ 222 }; 223 224 enum adxl372_instant_on_th_mode { 225 ADXL372_INSTANT_ON_LOW_TH, 226 ADXL372_INSTANT_ON_HIGH_TH 227 }; 228 229 enum adxl372_wakeup_rate { 230 ADXL372_WUR_52ms, 231 ADXL372_WUR_104ms, 232 ADXL372_WUR_208ms, 233 ADXL372_WUR_512ms, 234 ADXL372_WUR_2048ms, 235 ADXL372_WUR_4096ms, 236 ADXL372_WUR_8192ms, 237 ADXL372_WUR_24576ms 238 }; 239 240 enum adxl372_filter_settle { 241 ADXL372_FILTER_SETTLE_370, 242 ADXL372_FILTER_SETTLE_16 243 }; 244 245 enum adxl372_fifo_format { 246 ADXL372_XYZ_FIFO, 247 ADXL372_X_FIFO, 248 ADXL372_Y_FIFO, 249 ADXL372_XY_FIFO, 250 ADXL372_Z_FIFO, 251 ADXL372_XZ_FIFO, 252 ADXL372_YZ_FIFO, 253 ADXL372_XYZ_PEAK_FIFO, 254 }; 255 256 enum adxl372_fifo_mode { 257 ADXL372_FIFO_BYPASSED, 258 ADXL372_FIFO_STREAMED, 259 ADXL372_FIFO_TRIGGERED, 260 ADXL372_FIFO_OLD_SAVED 261 }; 262 263 struct adxl372_fifo_config { 264 enum adxl372_fifo_mode fifo_mode; 265 enum adxl372_fifo_format fifo_format; 266 uint16_t fifo_samples; 267 }; 268 269 struct adxl372_activity_threshold { 270 uint16_t thresh; 271 bool referenced; 272 bool enable; 273 }; 274 275 struct adxl372_xyz_accel_data { 276 int16_t x; 277 int16_t y; 278 int16_t z; 279 }; 280 281 struct adxl372_data { 282 struct adxl372_xyz_accel_data sample; 283 struct adxl372_fifo_config fifo_config; 284 285 #ifdef CONFIG_ADXL372_TRIGGER 286 struct gpio_callback gpio_cb; 287 288 sensor_trigger_handler_t th_handler; 289 struct sensor_trigger th_trigger; 290 sensor_trigger_handler_t drdy_handler; 291 struct sensor_trigger drdy_trigger; 292 const struct device *dev; 293 294 #if defined(CONFIG_ADXL372_TRIGGER_OWN_THREAD) 295 K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_ADXL372_THREAD_STACK_SIZE); 296 struct k_sem gpio_sem; 297 struct k_thread thread; 298 #elif defined(CONFIG_ADXL372_TRIGGER_GLOBAL_THREAD) 299 struct k_work work; 300 #endif 301 #endif /* CONFIG_ADXL372_TRIGGER */ 302 }; 303 304 struct adxl372_dev_config { 305 #ifdef CONFIG_ADXL372_I2C 306 struct i2c_dt_spec i2c; 307 #endif 308 #ifdef CONFIG_ADXL372_SPI 309 struct spi_dt_spec spi; 310 #endif /* CONFIG_ADXL372_SPI */ 311 #ifdef CONFIG_ADXL372_TRIGGER 312 struct gpio_dt_spec interrupt; 313 #endif 314 bool max_peak_detect_mode; 315 316 /* Device Settings */ 317 bool autosleep; 318 319 struct adxl372_activity_threshold activity_th; 320 struct adxl372_activity_threshold activity2_th; 321 struct adxl372_activity_threshold inactivity_th; 322 struct adxl372_fifo_config fifo_config; 323 324 enum adxl372_bandwidth bw; 325 enum adxl372_hpf_corner hpf; 326 enum adxl372_odr odr; 327 enum adxl372_wakeup_rate wur; 328 enum adxl372_act_proc_mode act_proc_mode; 329 enum adxl372_instant_on_th_mode th_mode; 330 enum adxl372_filter_settle filter_settle; 331 enum adxl372_op_mode op_mode; 332 333 uint16_t inactivity_time; 334 uint8_t activity_time; 335 uint8_t int1_config; 336 uint8_t int2_config; 337 }; 338 339 #ifdef CONFIG_ADXL372_TRIGGER 340 int adxl372_get_status(const struct device *dev, 341 uint8_t *status1, uint8_t *status2, uint16_t *fifo_entries); 342 343 int adxl372_reg_write_mask(const struct device *dev, 344 uint8_t reg_addr, uint32_t mask, uint8_t data); 345 346 int adxl372_trigger_set(const struct device *dev, 347 const struct sensor_trigger *trig, 348 sensor_trigger_handler_t handler); 349 350 int adxl372_init_interrupt(const struct device *dev); 351 #endif /* CONFIG_ADT7420_TRIGGER */ 352 353 #endif /* ZEPHYR_DRIVERS_SENSOR_ADXL372_ADXL372_H_ */ 354
