1 /* 2 * Copyright (c) 2018 Analog Devices Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_DRIVERS_SENSOR_ADXL372_ADXL372_H_ 8 #define ZEPHYR_DRIVERS_SENSOR_ADXL372_ADXL372_H_ 9 10 #include <zephyr/drivers/sensor.h> 11 #include <zephyr/types.h> 12 #include <zephyr/device.h> 13 #include <zephyr/drivers/gpio.h> 14 #include <zephyr/kernel.h> 15 #include <zephyr/sys/util.h> 16 17 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) 18 #include <zephyr/drivers/spi.h> 19 #endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) */ 20 21 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) 22 #include <zephyr/drivers/i2c.h> 23 #endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) */ 24 25 /* 26 * ADXL372 registers definition 27 */ 28 #define ADXL372_DEVID 0x00u /* Analog Devices accelerometer ID */ 29 #define ADXL372_DEVID_MST 0x01u /* Analog Devices MEMS device ID */ 30 #define ADXL372_PARTID 0x02u /* Device ID */ 31 #define ADXL372_REVID 0x03u /* product revision ID*/ 32 #define ADXL372_STATUS_1 0x04u /* Status register 1 */ 33 #define ADXL372_STATUS_2 0x05u /* Status register 2 */ 34 #define ADXL372_FIFO_ENTRIES_2 0x06u /* Valid data samples in the FIFO */ 35 #define ADXL372_FIFO_ENTRIES_1 0x07u /* Valid data samples in the FIFO */ 36 #define ADXL372_X_DATA_H 0x08u /* X-axis acceleration data [11:4] */ 37 #define ADXL372_X_DATA_L 0x09u /* X-axis acceleration data [3:0] */ 38 #define ADXL372_Y_DATA_H 0x0Au /* Y-axis acceleration data [11:4] */ 39 #define ADXL372_Y_DATA_L 0x0Bu /* Y-axis acceleration data [3:0] */ 40 #define ADXL372_Z_DATA_H 0x0Cu /* Z-axis acceleration data [11:4] */ 41 #define ADXL372_Z_DATA_L 0x0Du /* Z-axis acceleration data [3:0] */ 42 #define ADXL372_X_MAXPEAK_H 0x15u /* X-axis MaxPeak acceleration data */ 43 #define ADXL372_X_MAXPEAK_L 0x16u /* X-axis MaxPeak acceleration data */ 44 #define ADXL372_Y_MAXPEAK_H 0x17u /* Y-axis MaxPeak acceleration data */ 45 #define ADXL372_Y_MAXPEAK_L 0x18u /* Y-axis MaxPeak acceleration data */ 46 #define ADXL372_Z_MAXPEAK_H 0x19u /* Z-axis MaxPeak acceleration data */ 47 #define ADXL372_Z_MAXPEAK_L 0x1Au /* Z-axis MaxPeak acceleration data */ 48 #define ADXL372_OFFSET_X 0x20u /* X axis offset */ 49 #define ADXL372_OFFSET_Y 0x21u /* Y axis offset */ 50 #define ADXL372_OFFSET_Z 0x22u /* Z axis offset */ 51 #define ADXL372_X_THRESH_ACT_H 0x23u /* X axis Activity Threshold [15:8] */ 52 #define ADXL372_X_THRESH_ACT_L 0x24u /* X axis Activity Threshold [7:0] */ 53 #define ADXL372_Y_THRESH_ACT_H 0x25u /* Y axis Activity Threshold [15:8] */ 54 #define ADXL372_Y_THRESH_ACT_L 0x26u /* Y axis Activity Threshold [7:0] */ 55 #define ADXL372_Z_THRESH_ACT_H 0x27u /* Z axis Activity Threshold [15:8] */ 56 #define ADXL372_Z_THRESH_ACT_L 0x28u /* Z axis Activity Threshold [7:0] */ 57 #define ADXL372_TIME_ACT 0x29u /* Activity Time */ 58 #define ADXL372_X_THRESH_INACT_H 0x2Au /* X axis Inactivity Threshold */ 59 #define ADXL372_X_THRESH_INACT_L 0x2Bu /* X axis Inactivity Threshold */ 60 #define ADXL372_Y_THRESH_INACT_H 0x2Cu /* Y axis Inactivity Threshold */ 61 #define ADXL372_Y_THRESH_INACT_L 0x2Du /* Y axis Inactivity Threshold */ 62 #define ADXL372_Z_THRESH_INACT_H 0x2Eu /* Z axis Inactivity Threshold */ 63 #define ADXL372_Z_THRESH_INACT_L 0x2Fu /* Z axis Inactivity Threshold */ 64 #define ADXL372_TIME_INACT_H 0x30u /* Inactivity Time [15:8] */ 65 #define ADXL372_TIME_INACT_L 0x31u /* Inactivity Time [7:0] */ 66 #define ADXL372_X_THRESH_ACT2_H 0x32u /* X axis Activity2 Threshold [15:8] */ 67 #define ADXL372_X_THRESH_ACT2_L 0x33u /* X axis Activity2 Threshold [7:0] */ 68 #define ADXL372_Y_THRESH_ACT2_H 0x34u /* Y axis Activity2 Threshold [15:8] */ 69 #define ADXL372_Y_THRESH_ACT2_L 0x35u /* Y axis Activity2 Threshold [7:0] */ 70 #define ADXL372_Z_THRESH_ACT2_H 0x36u /* Z axis Activity2 Threshold [15:8] */ 71 #define ADXL372_Z_THRESH_ACT2_L 0x37u /* Z axis Activity2 Threshold [7:0] */ 72 #define ADXL372_HPF 0x38u /* High Pass Filter */ 73 #define ADXL372_FIFO_SAMPLES 0x39u /* FIFO Samples */ 74 #define ADXL372_FIFO_CTL 0x3Au /* FIFO Control */ 75 #define ADXL372_INT1_MAP 0x3Bu /* Interrupt 1 mapping control */ 76 #define ADXL372_INT2_MAP 0x3Cu /* Interrupt 2 mapping control */ 77 #define ADXL372_TIMING 0x3Du /* Timing */ 78 #define ADXL372_MEASURE 0x3Eu /* Measure */ 79 #define ADXL372_POWER_CTL 0x3Fu /* Power control */ 80 #define ADXL372_SELF_TEST 0x40u /* Self Test */ 81 #define ADXL372_RESET 0x41u /* Reset */ 82 #define ADXL372_FIFO_DATA 0x42u /* FIFO Data */ 83 84 #define ADXL372_DEVID_VAL 0xADu /* Analog Devices accelerometer ID */ 85 #define ADXL372_MST_DEVID_VAL 0x1Du /* Analog Devices MEMS device ID */ 86 #define ADXL372_PARTID_VAL 0xFAu /* Device ID */ 87 #define ADXL372_REVID_VAL 0x02u /* product revision ID*/ 88 #define ADXL372_RESET_CODE 0x52u /* Writing code 0x52 resets the device */ 89 90 #define ADXL372_READ 0x01u 91 #define ADXL372_REG_READ(x) (((x & 0xFF) << 1) | ADXL372_READ) 92 #define ADXL372_REG_WRITE(x) ((x & 0xFF) << 1) 93 #define ADXL372_TO_I2C_REG(x) ((x) >> 1) 94 95 /* ADXL372_POWER_CTL */ 96 #define ADXL372_POWER_CTL_INSTANT_ON_TH_MSK BIT(5) 97 #define ADXL372_POWER_CTL_INSTANT_ON_TH_MODE(x) (((x) & 0x1) << 5) 98 #define ADXL372_POWER_CTL_FIL_SETTLE_MSK BIT(4) 99 #define ADXL372_POWER_CTL_FIL_SETTLE_MODE(x) (((x) & 0x1) << 4) 100 #define ADXL372_POWER_CTL_LPF_DIS_MSK BIT(3) 101 #define ADXL372_POWER_CTL_LPF_DIS_MODE(x) (((x) & 0x1) << 3) 102 #define ADXL372_POWER_CTL_HPF_DIS_MSK BIT(2) 103 #define ADXL372_POWER_CTL_HPF_DIS_MODE(x) (((x) & 0x1) << 2) 104 #define ADXL372_POWER_CTL_MODE_MSK GENMASK(1, 0) 105 #define ADXL372_POWER_CTL_MODE(x) (((x) & 0x3) << 0) 106 107 /* ADXL372_MEASURE */ 108 #define ADXL372_MEASURE_AUTOSLEEP_MSK BIT(6) 109 #define ADXL372_MEASURE_AUTOSLEEP_MODE(x) (((x) & 0x1) << 6) 110 #define ADXL372_MEASURE_LINKLOOP_MSK GENMASK(5, 4) 111 #define ADXL372_MEASURE_LINKLOOP_MODE(x) (((x) & 0x3) << 4) 112 #define ADXL372_MEASURE_LOW_NOISE_MSK BIT(3) 113 #define ADXL372_MEASURE_LOW_NOISE_MODE(x) (((x) & 0x1) << 3) 114 #define ADXL372_MEASURE_BANDWIDTH_MSK GENMASK(2, 0) 115 #define ADXL372_MEASURE_BANDWIDTH_MODE(x) (((x) & 0x7) << 0) 116 117 /* ADXL372_TIMING */ 118 #define ADXL372_TIMING_ODR_MSK GENMASK(7, 5) 119 #define ADXL372_TIMING_ODR_MODE(x) (((x) & 0x7) << 5) 120 #define ADXL372_TIMING_WAKE_UP_RATE_MSK GENMASK(4, 2) 121 #define ADXL372_TIMING_WAKE_UP_RATE_MODE(x) (((x) & 0x7) << 2) 122 #define ADXL372_TIMING_EXT_CLK_MSK BIT(1) 123 #define ADXL372_TIMING_EXT_CLK_MODE(x) (((x) & 0x1) << 1) 124 #define ADXL372_TIMING_EXT_SYNC_MSK BIT(0) 125 #define ADXL372_TIMING_EXT_SYNC_MODE(x) (((x) & 0x1) << 0) 126 127 /* ADXL372_FIFO_CTL */ 128 #define ADXL372_FIFO_CTL_FORMAT_MSK GENMASK(5, 3) 129 #define ADXL372_FIFO_CTL_FORMAT_MODE(x) (((x) & 0x7) << 3) 130 #define ADXL372_FIFO_CTL_MODE_MSK GENMASK(2, 1) 131 #define ADXL372_FIFO_CTL_MODE_MODE(x) (((x) & 0x3) << 1) 132 #define ADXL372_FIFO_CTL_SAMPLES_MSK BIT(0) 133 #define ADXL372_FIFO_CTL_SAMPLES_MODE(x) (((x) > 0xFF) ? 1 : 0) 134 135 /* ADXL372_STATUS_1 */ 136 #define ADXL372_STATUS_1_DATA_RDY(x) (((x) >> 0) & 0x1) 137 #define ADXL372_STATUS_1_FIFO_RDY(x) (((x) >> 1) & 0x1) 138 #define ADXL372_STATUS_1_FIFO_FULL(x) (((x) >> 2) & 0x1) 139 #define ADXL372_STATUS_1_FIFO_OVR(x) (((x) >> 3) & 0x1) 140 #define ADXL372_STATUS_1_USR_NVM_BUSY(x) (((x) >> 5) & 0x1) 141 #define ADXL372_STATUS_1_AWAKE(x) (((x) >> 6) & 0x1) 142 #define ADXL372_STATUS_1_ERR_USR_REGS(x) (((x) >> 7) & 0x1) 143 144 /* ADXL372_STATUS_2 */ 145 #define ADXL372_STATUS_2_INACT(x) (((x) >> 4) & 0x1) 146 #define ADXL372_STATUS_2_ACTIVITY(x) (((x) >> 5) & 0x1) 147 #define ADXL372_STATUS_2_ACTIVITY2(x) (((x) >> 6) & 0x1) 148 149 /* ADXL372_INT1_MAP */ 150 #define ADXL372_INT1_MAP_DATA_RDY_MSK BIT(0) 151 #define ADXL372_INT1_MAP_DATA_RDY_MODE(x) (((x) & 0x1) << 0) 152 #define ADXL372_INT1_MAP_FIFO_RDY_MSK BIT(1) 153 #define ADXL372_INT1_MAP_FIFO_RDY_MODE(x) (((x) & 0x1) << 1) 154 #define ADXL372_INT1_MAP_FIFO_FULL_MSK BIT(2) 155 #define ADXL372_INT1_MAP_FIFO_FULL_MODE(x) (((x) & 0x1) << 2) 156 #define ADXL372_INT1_MAP_FIFO_OVR_MSK BIT(3) 157 #define ADXL372_INT1_MAP_FIFO_OVR_MODE(x) (((x) & 0x1) << 3) 158 #define ADXL372_INT1_MAP_INACT_MSK BIT(4) 159 #define ADXL372_INT1_MAP_INACT_MODE(x) (((x) & 0x1) << 4) 160 #define ADXL372_INT1_MAP_ACT_MSK BIT(5) 161 #define ADXL372_INT1_MAP_ACT_MODE(x) (((x) & 0x1) << 5) 162 #define ADXL372_INT1_MAP_AWAKE_MSK BIT(6) 163 #define ADXL372_INT1_MAP_AWAKE_MODE(x) (((x) & 0x1) << 6) 164 #define ADXL372_INT1_MAP_LOW_MSK BIT(7) 165 #define ADXL372_INT1_MAP_LOW_MODE(x) (((x) & 0x1) << 7) 166 167 /* ADXL372_INT2_MAP */ 168 #define ADXL372_INT2_MAP_DATA_RDY_MSK BIT(0) 169 #define ADXL372_INT2_MAP_DATA_RDY_MODE(x) (((x) & 0x1) << 0) 170 #define ADXL372_INT2_MAP_FIFO_RDY_MSK BIT(1) 171 #define ADXL372_INT2_MAP_FIFO_RDY_MODE(x) (((x) & 0x1) << 1) 172 #define ADXL372_INT2_MAP_FIFO_FULL_MSK BIT(2) 173 #define ADXL372_INT2_MAP_FIFO_FULL_MODE(x) (((x) & 0x1) << 2) 174 #define ADXL372_INT2_MAP_FIFO_OVR_MSK BIT(3) 175 #define ADXL372_INT2_MAP_FIFO_OVR_MODE(x) (((x) & 0x1) << 3) 176 #define ADXL372_INT2_MAP_INACT_MSK BIT(4) 177 #define ADXL372_INT2_MAP_INACT_MODE(x) (((x) & 0x1) << 4) 178 #define ADXL372_INT2_MAP_ACT_MSK BIT(5) 179 #define ADXL372_INT2_MAP_ACT_MODE(x) (((x) & 0x1) << 5) 180 #define ADXL372_INT2_MAP_AWAKE_MSK BIT(6) 181 #define ADXL372_INT2_MAP_AWAKE_MODE(x) (((x) & 0x1) << 6) 182 #define ADXL372_INT2_MAP_LOW_MSK BIT(7) 183 #define ADXL372_INT2_MAP_LOW_MODE(x) (((x) & 0x1) << 7) 184 185 /* ADXL372_HPF */ 186 #define ADXL372_HPF_CORNER(x) (((x) & 0x3) << 0) 187 188 enum adxl372_axis { 189 ADXL372_X_AXIS, 190 ADXL372_Y_AXIS, 191 ADXL372_Z_AXIS 192 }; 193 194 enum adxl372_op_mode { 195 ADXL372_STANDBY, 196 ADXL372_WAKE_UP, 197 ADXL372_INSTANT_ON, 198 ADXL372_FULL_BW_MEASUREMENT 199 }; 200 201 enum adxl372_bandwidth { 202 ADXL372_BW_200HZ, 203 ADXL372_BW_400HZ, 204 ADXL372_BW_800HZ, 205 ADXL372_BW_1600HZ, 206 ADXL372_BW_3200HZ, 207 ADXL372_BW_LPF_DISABLED = 0xC, 208 }; 209 210 enum adxl372_hpf_corner { 211 ADXL372_HPF_CORNER_0, 212 ADXL372_HPF_CORNER_1, 213 ADXL372_HPF_CORNER_2, 214 ADXL372_HPF_CORNER_3, 215 ADXL372_HPF_DISABLED, 216 }; 217 218 enum adxl372_act_proc_mode { 219 ADXL372_DEFAULT, 220 ADXL372_LINKED, 221 ADXL372_LOOPED 222 }; 223 224 enum adxl372_odr { 225 ADXL372_ODR_400HZ, 226 ADXL372_ODR_800HZ, 227 ADXL372_ODR_1600HZ, 228 ADXL372_ODR_3200HZ, 229 ADXL372_ODR_6400HZ 230 }; 231 232 enum adxl372_instant_on_th_mode { 233 ADXL372_INSTANT_ON_LOW_TH, 234 ADXL372_INSTANT_ON_HIGH_TH 235 }; 236 237 enum adxl372_wakeup_rate { 238 ADXL372_WUR_52ms, 239 ADXL372_WUR_104ms, 240 ADXL372_WUR_208ms, 241 ADXL372_WUR_512ms, 242 ADXL372_WUR_2048ms, 243 ADXL372_WUR_4096ms, 244 ADXL372_WUR_8192ms, 245 ADXL372_WUR_24576ms 246 }; 247 248 enum adxl372_filter_settle { 249 ADXL372_FILTER_SETTLE_370, 250 ADXL372_FILTER_SETTLE_16 251 }; 252 253 enum adxl372_fifo_format { 254 ADXL372_XYZ_FIFO, 255 ADXL372_X_FIFO, 256 ADXL372_Y_FIFO, 257 ADXL372_XY_FIFO, 258 ADXL372_Z_FIFO, 259 ADXL372_XZ_FIFO, 260 ADXL372_YZ_FIFO, 261 ADXL372_XYZ_PEAK_FIFO, 262 }; 263 264 enum adxl372_fifo_mode { 265 ADXL372_FIFO_BYPASSED, 266 ADXL372_FIFO_STREAMED, 267 ADXL372_FIFO_TRIGGERED, 268 ADXL372_FIFO_OLD_SAVED 269 }; 270 271 struct adxl372_fifo_config { 272 enum adxl372_fifo_mode fifo_mode; 273 enum adxl372_fifo_format fifo_format; 274 uint16_t fifo_samples; 275 }; 276 277 struct adxl372_activity_threshold { 278 uint16_t thresh; 279 bool referenced; 280 bool enable; 281 }; 282 283 struct adxl372_xyz_accel_data { 284 int16_t x; 285 int16_t y; 286 int16_t z; 287 }; 288 289 struct adxl372_transfer_function { 290 int (*read_reg_multiple)(const struct device *dev, uint8_t reg_addr, 291 uint8_t *value, uint16_t len); 292 int (*write_reg)(const struct device *dev, uint8_t reg_addr, 293 uint8_t value); 294 int (*read_reg)(const struct device *dev, uint8_t reg_addr, 295 uint8_t *value); 296 int (*write_reg_mask)(const struct device *dev, uint8_t reg_addr, 297 uint32_t mask, uint8_t value); 298 }; 299 300 struct adxl372_data { 301 struct adxl372_xyz_accel_data sample; 302 const struct adxl372_transfer_function *hw_tf; 303 struct adxl372_fifo_config fifo_config; 304 enum adxl372_act_proc_mode act_proc_mode; 305 #ifdef CONFIG_ADXL372_TRIGGER 306 struct gpio_callback gpio_cb; 307 308 sensor_trigger_handler_t th_handler; 309 const struct sensor_trigger *th_trigger; 310 sensor_trigger_handler_t drdy_handler; 311 const struct sensor_trigger *drdy_trigger; 312 const struct device *dev; 313 314 #if defined(CONFIG_ADXL372_TRIGGER_OWN_THREAD) 315 K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_ADXL372_THREAD_STACK_SIZE); 316 struct k_sem gpio_sem; 317 struct k_thread thread; 318 #elif defined(CONFIG_ADXL372_TRIGGER_GLOBAL_THREAD) 319 struct k_work work; 320 #endif 321 #endif /* CONFIG_ADXL372_TRIGGER */ 322 }; 323 324 struct adxl372_dev_config { 325 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) 326 struct i2c_dt_spec i2c; 327 #endif 328 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) 329 struct spi_dt_spec spi; 330 #endif 331 int (*bus_init)(const struct device *dev); 332 #ifdef CONFIG_ADXL372_TRIGGER 333 struct gpio_dt_spec interrupt; 334 #endif 335 336 enum adxl372_bandwidth bw; 337 enum adxl372_hpf_corner hpf; 338 enum adxl372_odr odr; 339 340 bool max_peak_detect_mode; 341 342 /* Device Settings */ 343 bool autosleep; 344 345 struct adxl372_activity_threshold activity_th; 346 struct adxl372_activity_threshold activity2_th; 347 struct adxl372_activity_threshold inactivity_th; 348 struct adxl372_fifo_config fifo_config; 349 350 enum adxl372_wakeup_rate wur; 351 enum adxl372_instant_on_th_mode th_mode; 352 enum adxl372_filter_settle filter_settle; 353 enum adxl372_op_mode op_mode; 354 355 uint16_t inactivity_time; 356 uint8_t activity_time; 357 uint8_t int1_config; 358 uint8_t int2_config; 359 }; 360 361 int adxl372_spi_init(const struct device *dev); 362 int adxl372_i2c_init(const struct device *dev); 363 364 #ifdef CONFIG_ADXL372_TRIGGER 365 int adxl372_get_status(const struct device *dev, 366 uint8_t *status1, uint8_t *status2, uint16_t *fifo_entries); 367 368 int adxl372_reg_write_mask(const struct device *dev, 369 uint8_t reg_addr, uint32_t mask, uint8_t data); 370 371 int adxl372_trigger_set(const struct device *dev, 372 const struct sensor_trigger *trig, 373 sensor_trigger_handler_t handler); 374 375 int adxl372_init_interrupt(const struct device *dev); 376 #endif /* CONFIG_ADT7420_TRIGGER */ 377 378 #endif /* ZEPHYR_DRIVERS_SENSOR_ADXL372_ADXL372_H_ */ 379
