1 /* 2 * Copyright (c) 2023 Analog Devices Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_DRIVERS_SENSOR_ADXL367_ADXL367_H_ 8 #define ZEPHYR_DRIVERS_SENSOR_ADXL367_ADXL367_H_ 9 10 #include <zephyr/drivers/sensor.h> 11 #include <zephyr/types.h> 12 #include <zephyr/device.h> 13 #include <zephyr/drivers/gpio.h> 14 #include <zephyr/kernel.h> 15 #include <zephyr/sys/util.h> 16 17 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) 18 #include <zephyr/drivers/spi.h> 19 #endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) */ 20 21 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) 22 #include <zephyr/drivers/i2c.h> 23 #endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) */ 24 25 /* 26 * ADXL367 registers definition 27 */ 28 #define ADXL367_DEVID 0x00u /* Analog Devices accelerometer ID */ 29 #define ADXL367_DEVID_MST 0x01u /* Analog Devices MEMS device ID */ 30 #define ADXL367_PART_ID 0x02u /* Device ID */ 31 #define ADXL367_REV_ID 0x03u /* product revision ID*/ 32 #define ADXL367_SERIAL_NR_3 0x04u /* Serial Number 3 */ 33 #define ADXL367_SERIAL_NR_2 0x05u /* Serial Number 2 */ 34 #define ADXL367_SERIAL_NR_1 0x06u /* Serial Number 1 */ 35 #define ADXL367_SERIAL_NR_0 0x07u /* Serial Number 0 */ 36 #define ADXL367_XDATA 0x08u /* X-axis acceleration data [13:6] */ 37 #define ADXL367_YDATA 0x09u /* Y-axis acceleration data [13:6] */ 38 #define ADXL367_ZDATA 0x0Au /* Z-axis acceleration data [13:6] */ 39 #define ADXL367_STATUS 0x0Bu /* Status */ 40 #define ADXL367_FIFO_ENTRIES_L 0x0Cu /* FIFO Entries Low */ 41 #define ADXL367_FIFO_ENTRIES_H 0x0Du /* FIFO Entries High */ 42 #define ADXL367_X_DATA_H 0x0Eu /* X-axis acceleration data [13:6] */ 43 #define ADXL367_X_DATA_L 0x0Fu /* X-axis acceleration data [5:0] */ 44 #define ADXL367_Y_DATA_H 0x10u /* Y-axis acceleration data [13:6] */ 45 #define ADXL367_Y_DATA_L 0x11u /* Y-axis acceleration data [5:0] */ 46 #define ADXL367_Z_DATA_H 0x12u /* Z-axis acceleration data [13:6] */ 47 #define ADXL367_Z_DATA_L 0x13u /* Z-axis acceleration data [5:0] */ 48 #define ADXL367_TEMP_H 0x14u /* Temperate data [13:6] */ 49 #define ADXL367_TEMP_L 0x15u /* Temperate data [5:0] */ 50 #define ADXL367_EX_ADC_H 0x16u /* Extended ADC data [13:6] */ 51 #define ADXL367_EX_ADC_L 0x17u /* Extended ADC data [5:0] */ 52 #define ADXL367_I2C_FIFO_DATA 0x18u /* I2C FIFO Data address */ 53 #define ADXL367_SOFT_RESET 0x1Fu /* Software reset register */ 54 #define ADXL367_THRESH_ACT_H 0x20u /* Activity Threshold [12:6] */ 55 #define ADXL367_THRESH_ACT_L 0x21u /* Activity Threshold [5:0] */ 56 #define ADXL367_TIME_ACT 0x22u /* Activity Time */ 57 #define ADXL367_THRESH_INACT_H 0x23u /* Inactivity Threshold [12:6] */ 58 #define ADXL367_THRESH_INACT_L 0x24u /* Inactivity Threshold [5:0] */ 59 #define ADXL367_TIME_INACT_H 0x25u /* Inactivity Time [12:6] */ 60 #define ADXL367_TIME_INACT_L 0x26u /* Inactivity Time [5:0] */ 61 #define ADXL367_ACT_INACT_CTL 0x27u /* Activity Inactivity Control */ 62 #define ADXL367_FIFO_CONTROL 0x28u /* FIFO Control */ 63 #define ADXL367_FIFO_SAMPLES 0x29u /* FIFO Samples */ 64 #define ADXL367_INTMAP1_LOWER 0x2Au /* Interrupt 1 mapping control lower */ 65 #define ADXL367_INTMAP2_LOWER 0x2Bu /* Interrupt 2 mapping control lower */ 66 #define ADXL367_FILTER_CTL 0x2Cu /* Filter Control register */ 67 #define ADXL367_POWER_CTL 0x2Du /* Power Control register */ 68 #define ADXL367_SELF_TEST 0x2Eu /* Self Test */ 69 #define ADXL367_TAP_THRESH 0x2Fu /* Tap Threshold */ 70 #define ADXL367_TAP_DUR 0x30u /* Tap Duration */ 71 #define ADXL367_TAP_LATENT 0x31u /* Tap Latency */ 72 #define ADXL367_TAP_WINDOW 0x32u /* Tap Window */ 73 #define ADXL367_X_OFFSET 0x33u /* X-axis offset */ 74 #define ADXL367_Y_OFFSET 0x34u /* Y-axis offset */ 75 #define ADXL367_Z_OFFSET 0x35u /* Z-axis offset */ 76 #define ADXL367_X_SENS 0x36u /* X-axis user sensitivity */ 77 #define ADXL367_Y_SENS 0x37u /* Y-axis user sensitivity */ 78 #define ADXL367_Z_SENS 0x38u /* Z-axis user sensitivity */ 79 #define ADXL367_TIMER_CTL 0x39u /* Timer Control */ 80 #define ADXL367_INTMAP1_UPPER 0x3Au /* Interrupt 1 mapping control upper */ 81 #define ADXL367_INTMAP2_UPPER 0x3Bu /* Interrupt 2 mapping control upper */ 82 #define ADXL367_ADC_CTL 0x3Cu /* ADC Control Register */ 83 #define ADXL367_TEMP_CTL 0x3Du /* Temperature Control Register */ 84 #define ADXL367_TEMP_ADC_OTH_H 0x3Eu /* Temperature ADC Over Threshold [12:6]*/ 85 #define ADXL367_TEMP_ADC_OTH_L 0x3Fu /* Temperature ADC Over Threshold [5:0]*/ 86 #define ADXL367_TEMP_ADC_UTH_H 0x40u /* Temperature ADC Under Threshold [12:6]*/ 87 #define ADXL367_TEMP_ADC_UTH_L 0x41u /* Temperature ADC Under Threshold [5:0]*/ 88 #define ADXL367_TEMP_ADC_TIMER 0x42u /* Temperature Activiy Inactivity Timer */ 89 #define ADXL367_AXIS_MASK 0x43u /* Axis Mask Register */ 90 #define ADXL367_STATUS_COPY 0x44u /* Status Copy Register */ 91 #define ADXL367_STATUS2 0x45u /* Status 2 Register */ 92 93 #define ADXL367_DEVID_VAL 0xADu /* Analog Devices accelerometer ID */ 94 #define ADXL367_MST_DEVID_VAL 0x1Du /* Analog Devices MEMS device ID */ 95 #define ADXL367_PARTID_VAL 0xF7u /* Device ID */ 96 #define ADXL367_REVID_VAL 0x03u /* product revision ID*/ 97 #define ADXL367_RESET_CODE 0x52u /* Writing code 0x52 resets the device */ 98 99 #define ADXL367_READ 0x01u 100 #define ADXL367_REG_READ(x) (((x & 0xFF) << 1) | ADXL367_READ) 101 #define ADXL367_REG_WRITE(x) ((x & 0xFF) << 1) 102 #define ADXL367_TO_REG(x) ((x) >> 1) 103 #define ADXL367_SPI_WRITE_REG 0x0Au 104 #define ADXL367_SPI_READ_REG 0x0Bu 105 106 #define ADXL367_ABSOLUTE 0x00 107 #define ADXL367_REFERENCED 0x01 108 109 /* ADXL367_POWER_CTL */ 110 #define ADXL367_POWER_CTL_EXT_CLK_MSK BIT(6) 111 #define ADXL367_POWER_CTL_NOISE_MSK GENMASK(5, 4) 112 #define ADXL367_POWER_CTL_WAKEUP_MSK BIT(3) 113 #define ADXL367_POWER_CTL_AUTOSLEEP_MSK BIT(2) 114 #define ADXL367_POWER_CTL_MEASURE_MSK GENMASK(1, 0) 115 116 /* ADXL367_ACT_INACT_CTL */ 117 #define ADXL367_ACT_INACT_CTL_LINKLOOP_MSK GENMASK(5, 4) 118 #define ADXL367_ACT_INACT_CTL_INACT_REF_MSK BIT(3) 119 #define ADXL367_ACT_INACT_CTL_INACT_EN_MSK BIT(2) 120 #define ADXL367_ACT_INACT_CTL_ACT_REF_MSK BIT(1) 121 #define ADXL367_ACT_INACT_CTL_ACT_EN_MSK BIT(0) 122 123 /* ADXL367_ACT_INACT_CTL_INACT_EN options */ 124 #define ADXL367_NO_INACTIVITY_DETECTION_ENABLED 0x0 125 #define ADXL367_INACTIVITY_ENABLE 0x1 126 #define ADXL367_NO_INACTIVITY_DETECTION_ENABLED_2 0x2 127 #define ADXL367_REFERENCED_INACTIVITY_ENABLE 0x3 128 129 /* ADXL367_ACT_INACT_CTL_ACT_EN options */ 130 #define ADXL367_NO_ACTIVITY_DETECTION 0x0 131 #define ADXL367_ACTIVITY_ENABLE 0x1 132 #define ADXL367_NO_ACTIVITY_DETECTION_2 0x2 133 #define ADXL367_REFERENCED_ACTIVITY_ENABLE 0x3 134 135 #define ADXL367_TEMP_OFFSET 1185 136 #define ADXL367_TEMP_25C 165 137 #define ADXL367_TEMP_SCALE 18518518LL 138 #define ADXL367_TEMP_SCALE_DIV 1000000000 139 140 #define ADXL367_THRESH_H_MSK GENMASK(6, 0) 141 #define ADXL367_THRESH_L_MSK GENMASK(7, 2) 142 143 /* ADXL367_REG_TEMP_CTL definitions. */ 144 #define ADXL367_TEMP_INACT_EN_MSK BIT(3) 145 #define ADXL367_TEMP_ACT_EN_MSK BIT(1) 146 #define ADXL367_TEMP_EN_MSK BIT(0) 147 148 /* ADXL367_SELF_TEST */ 149 #define ADXL367_SELF_TEST_ST_FORCE_MSK BIT(1) 150 #define ADXL367_SELF_TEST_ST_MSK BIT(0) 151 152 /* ADXL367_REG_FILTER_CTL definitions */ 153 #define ADXL367_FILTER_CTL_RANGE_MSK GENMASK(7, 6) 154 #define ADXL367_FILTER_I2C_HS BIT(5) 155 #define ADXL367_FILTER_CTL_RES BIT(4) 156 #define ADXL367_FILTER_CTL_EXT_SAMPLE BIT(3) 157 #define ADXL367_FILTER_CTL_ODR_MSK GENMASK(2, 0) 158 159 /* ADXL367_REG_FIFO_CONTROL */ 160 #define ADXL367_FIFO_CONTROL_FIFO_CHANNEL_MSK GENMASK(6, 3) 161 #define ADXL367_FIFO_CONTROL_FIFO_SAMPLES_MSK BIT(2) 162 #define ADXL367_FIFO_CONTROL_FIFO_MODE_MSK GENMASK(1, 0) 163 164 /* ADXL367_REG_ADC_CTL definitions. */ 165 #define ADXL367_FIFO_8_12BIT_MSK GENMASK(7, 6) 166 #define ADXL367_ADC_INACT_EN BIT(3) 167 #define ADXL367_ADC_ACT_EN BIT(1) 168 #define ADXL367_ADC_EN BIT(0) 169 170 /* ADXL367_REG_STATUS definitions */ 171 #define ADXL367_STATUS_ERR_USER_REGS BIT(7) 172 #define ADXL367_STATUS_AWAKE BIT(6) 173 #define ADXL367_STATUS_INACT BIT(5) 174 #define ADXL367_STATUS_ACT BIT(4) 175 #define ADXL367_STATUS_FIFO_OVERRUN BIT(3) 176 #define ADXL367_STATUS_FIFO_WATERMARK BIT(2) 177 #define ADXL367_STATUS_FIFO_RDY BIT(1) 178 #define ADXL367_STATUS_DATA_RDY BIT(0) 179 180 /* ADXL367_INTMAP_LOWER */ 181 #define ADXL367_INT_LOW BIT(7) 182 #define ADXL367_AWAKE_INT BIT(6) 183 #define ADXL367_INACT_INT BIT(5) 184 #define ADXL367_ACT_INT BIT(4) 185 #define ADXL367_FIFO_OVERRUN BIT(3) 186 #define ADXL367_FIFO_WATERMARK BIT(2) 187 #define ADXL367_FIFO_RDY BIT(1) 188 #define ADXL367_DATA_RDY BIT(0) 189 190 /* ADXL367_INTMAP_UPPER */ 191 #define ADXL367_ERR_FUSE BIT(7) 192 #define ADXL367_ERR_USER_REGS BIT(6) 193 #define ADXL367_KPALV_TIMER BIT(4) 194 #define ADXL367_TEMP_ADC_HI BIT(3) 195 #define ADXL367_TEMP_ADC_LOW BIT(2) 196 #define ADXL367_TAP_TWO BIT(1) 197 #define ADXL367_TAP_ONE BIT(0) 198 199 /* Min change = 90mg. Sensitivity = 4LSB / mg */ 200 #define ADXL367_SELF_TEST_MIN (90 * 100 / 25) 201 /* Max change = 270mg. Sensitivity = 4LSB / mg */ 202 #define ADXL367_SELF_TEST_MAX (270 * 100 / 25) 203 204 enum adxl367_axis { 205 ADXL367_X_AXIS, 206 ADXL367_Y_AXIS, 207 ADXL367_Z_AXIS 208 }; 209 210 enum adxl367_op_mode { 211 ADXL367_STANDBY = 0, 212 ADXL367_MEASURE = 2, 213 }; 214 215 enum adxl367_range { 216 ADXL367_2G_RANGE, 217 ADXL367_4G_RANGE, 218 ADXL367_8G_RANGE, 219 }; 220 221 enum adxl367_act_proc_mode { 222 ADXL367_DEFAULT = 0, 223 ADXL367_LINKED = 1, 224 ADXL367_LOOPED = 3, 225 }; 226 227 enum adxl367_odr { 228 ADXL367_ODR_12P5HZ, 229 ADXL367_ODR_25HZ, 230 ADXL367_ODR_50HZ, 231 ADXL367_ODR_100HZ, 232 ADXL367_ODR_200HZ, 233 ADXL367_ODR_400HZ, 234 }; 235 236 enum adxl367_fifo_format { 237 ADXL367_FIFO_FORMAT_XYZ, 238 ADXL367_FIFO_FORMAT_X, 239 ADXL367_FIFO_FORMAT_Y, 240 ADXL367_FIFO_FORMAT_Z, 241 ADXL367_FIFO_FORMAT_XYZT, 242 ADXL367_FIFO_FORMAT_XT, 243 ADXL367_FIFO_FORMAT_YT, 244 ADXL367_FIFO_FORMAT_ZT, 245 ADXL367_FIFO_FORMAT_XYZA, 246 ADXL367_FIFO_FORMAT_XA, 247 ADXL367_FIFO_FORMAT_YA, 248 ADXL367_FIFO_FORMAT_ZA 249 }; 250 251 enum adxl367_fifo_mode { 252 ADXL367_FIFO_DISABLED, 253 ADXL367_OLDEST_SAVED, 254 ADXL367_STREAM_MODE, 255 ADXL367_TRIGGERED_MODE 256 }; 257 258 enum adxl367_fifo_read_mode { 259 ADXL367_12B_CHID, 260 ADXL367_8B, 261 ADXL367_12B, 262 ADXL367_14B_CHID 263 }; 264 265 struct adxl367_fifo_config { 266 enum adxl367_fifo_mode fifo_mode; 267 enum adxl367_fifo_format fifo_format; 268 enum adxl367_fifo_read_mode fifo_read_mode; 269 uint16_t fifo_samples; 270 }; 271 272 struct adxl367_activity_threshold { 273 uint16_t value; 274 bool referenced; 275 bool enable; 276 }; 277 278 struct adxl367_xyz_accel_data { 279 int16_t x; 280 int16_t y; 281 int16_t z; 282 }; 283 284 struct adxl367_transfer_function { 285 int (*read_reg_multiple)(const struct device *dev, uint8_t reg_addr, 286 uint8_t *value, uint16_t len); 287 int (*write_reg)(const struct device *dev, uint8_t reg_addr, 288 uint8_t value); 289 int (*read_reg)(const struct device *dev, uint8_t reg_addr, 290 uint8_t *value); 291 int (*write_reg_mask)(const struct device *dev, uint8_t reg_addr, 292 uint32_t mask, uint8_t value); 293 }; 294 295 struct adxl367_data { 296 struct adxl367_xyz_accel_data sample; 297 int16_t temp_val; 298 const struct adxl367_transfer_function *hw_tf; 299 struct adxl367_fifo_config fifo_config; 300 enum adxl367_act_proc_mode act_proc_mode; 301 enum adxl367_range range; 302 #ifdef CONFIG_ADXL367_TRIGGER 303 struct gpio_callback gpio_cb; 304 305 sensor_trigger_handler_t th_handler; 306 const struct sensor_trigger *th_trigger; 307 sensor_trigger_handler_t drdy_handler; 308 const struct sensor_trigger *drdy_trigger; 309 const struct device *dev; 310 311 #if defined(CONFIG_ADXL367_TRIGGER_OWN_THREAD) 312 K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_ADXL367_THREAD_STACK_SIZE); 313 struct k_sem gpio_sem; 314 struct k_thread thread; 315 #elif defined(CONFIG_ADXL367_TRIGGER_GLOBAL_THREAD) 316 struct k_work work; 317 #endif 318 #endif /* CONFIG_ADXL367_TRIGGER */ 319 }; 320 321 struct adxl367_dev_config { 322 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) 323 struct i2c_dt_spec i2c; 324 #endif 325 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) 326 struct spi_dt_spec spi; 327 #endif 328 int (*bus_init)(const struct device *dev); 329 330 #ifdef CONFIG_ADXL367_TRIGGER 331 struct gpio_dt_spec interrupt; 332 #endif 333 334 enum adxl367_odr odr; 335 336 /* Device Settings */ 337 bool autosleep; 338 bool low_noise; 339 bool temp_en; 340 341 struct adxl367_activity_threshold activity_th; 342 struct adxl367_activity_threshold inactivity_th; 343 struct adxl367_fifo_config fifo_config; 344 345 enum adxl367_range range; 346 enum adxl367_op_mode op_mode; 347 348 uint16_t inactivity_time; 349 uint8_t activity_time; 350 }; 351 352 int adxl367_spi_init(const struct device *dev); 353 int adxl367_i2c_init(const struct device *dev); 354 int adxl367_trigger_set(const struct device *dev, 355 const struct sensor_trigger *trig, 356 sensor_trigger_handler_t handler); 357 358 int adxl367_init_interrupt(const struct device *dev); 359 360 #endif /* ZEPHYR_DRIVERS_SENSOR_ADXL367_ADXL367_H_ */ 361
