1 /* 2 * Copyright (c) 2017 IpTronix S.r.l. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_DRIVERS_SENSOR_ADXL362_ADXL362_H_ 8 #define ZEPHYR_DRIVERS_SENSOR_ADXL362_ADXL362_H_ 9 10 #include <zephyr/types.h> 11 #include <zephyr/device.h> 12 #include <zephyr/drivers/gpio.h> 13 #include <zephyr/drivers/spi.h> 14 #include <zephyr/drivers/sensor.h> 15 16 #define ADXL362_SLAVE_ID 1 17 18 /* ADXL362 communication commands */ 19 #define ADXL362_WRITE_REG 0x0A 20 #define ADXL362_READ_REG 0x0B 21 #define ADXL362_READ_FIFO 0x0D 22 23 /* Registers */ 24 #define ADXL362_REG_DEVID_AD 0x00 25 #define ADXL362_REG_DEVID_MST 0x01 26 #define ADXL362_REG_PARTID 0x02 27 #define ADXL362_REG_REVID 0x03 28 #define ADXL362_REG_XDATA 0x08 29 #define ADXL362_REG_YDATA 0x09 30 #define ADXL362_REG_ZDATA 0x0A 31 #define ADXL362_REG_STATUS 0x0B 32 #define ADXL362_REG_FIFO_L 0x0C 33 #define ADXL362_REG_FIFO_H 0x0D 34 #define ADXL362_REG_XDATA_L 0x0E 35 #define ADXL362_REG_XDATA_H 0x0F 36 #define ADXL362_REG_YDATA_L 0x10 37 #define ADXL362_REG_YDATA_H 0x11 38 #define ADXL362_REG_ZDATA_L 0x12 39 #define ADXL362_REG_ZDATA_H 0x13 40 #define ADXL362_REG_TEMP_L 0x14 41 #define ADXL362_REG_TEMP_H 0x15 42 #define ADXL362_REG_SOFT_RESET 0x1F 43 #define ADXL362_REG_THRESH_ACT_L 0x20 44 #define ADXL362_REG_THRESH_ACT_H 0x21 45 #define ADXL362_REG_TIME_ACT 0x22 46 #define ADXL362_REG_THRESH_INACT_L 0x23 47 #define ADXL362_REG_THRESH_INACT_H 0x24 48 #define ADXL362_REG_TIME_INACT_L 0x25 49 #define ADXL362_REG_TIME_INACT_H 0x26 50 #define ADXL362_REG_ACT_INACT_CTL 0x27 51 #define ADXL362_REG_FIFO_CTL 0x28 52 #define ADXL362_REG_FIFO_SAMPLES 0x29 53 #define ADXL362_REG_INTMAP1 0x2A 54 #define ADXL362_REG_INTMAP2 0x2B 55 #define ADXL362_REG_FILTER_CTL 0x2C 56 #define ADXL362_REG_POWER_CTL 0x2D 57 #define ADXL362_REG_SELF_TEST 0x2E 58 59 /* ADXL362_REG_STATUS definitions */ 60 #define ADXL362_STATUS_ERR_USER_REGS (1 << 7) 61 #define ADXL362_STATUS_AWAKE (1 << 6) 62 #define ADXL362_STATUS_INACT (1 << 5) 63 #define ADXL362_STATUS_ACT (1 << 4) 64 #define ADXL362_STATUS_FIFO_OVERRUN (1 << 3) 65 #define ADXL362_STATUS_FIFO_WATERMARK (1 << 2) 66 #define ADXL362_STATUS_FIFO_RDY (1 << 1) 67 #define ADXL362_STATUS_DATA_RDY (1 << 0) 68 69 /* ADXL362_REG_ACT_INACT_CTL definitions */ 70 #define ADXL362_ACT_INACT_CTL_LINKLOOP(x) (((x) & 0x3) << 4) 71 #define ADXL362_ACT_INACT_CTL_INACT_REF (1 << 3) 72 #define ADXL362_ACT_INACT_CTL_INACT_EN (1 << 2) 73 #define ADXL362_ACT_INACT_CTL_ACT_REF (1 << 1) 74 #define ADXL362_ACT_INACT_CTL_ACT_EN (1 << 0) 75 76 /* ADXL362_ACT_INACT_CTL_LINKLOOP(x) options */ 77 #define ADXL362_MODE_DEFAULT 0 78 #define ADXL362_MODE_LINK 1 79 #define ADXL362_MODE_LOOP 3 80 81 /* ADXL362_REG_FIFO_CTL */ 82 #define ADXL362_FIFO_CTL_AH (1 << 3) 83 #define ADXL362_FIFO_CTL_FIFO_TEMP (1 << 2) 84 #define ADXL362_FIFO_CTL_FIFO_MODE(x) (((x) & 0x3) << 0) 85 86 /* ADXL362_FIFO_CTL_FIFO_MODE(x) options */ 87 #define ADXL362_FIFO_DISABLE 0 88 #define ADXL362_FIFO_OLDEST_SAVED 1 89 #define ADXL362_FIFO_STREAM 2 90 #define ADXL362_FIFO_TRIGGERED 3 91 92 /* ADXL362_REG_INTMAP1 */ 93 #define ADXL362_INTMAP1_INT_LOW (1 << 7) 94 #define ADXL362_INTMAP1_AWAKE (1 << 6) 95 #define ADXL362_INTMAP1_INACT (1 << 5) 96 #define ADXL362_INTMAP1_ACT (1 << 4) 97 #define ADXL362_INTMAP1_FIFO_OVERRUN (1 << 3) 98 #define ADXL362_INTMAP1_FIFO_WATERMARK (1 << 2) 99 #define ADXL362_INTMAP1_FIFO_READY (1 << 1) 100 #define ADXL362_INTMAP1_DATA_READY (1 << 0) 101 102 /* ADXL362_REG_INTMAP2 definitions */ 103 #define ADXL362_INTMAP2_INT_LOW (1 << 7) 104 #define ADXL362_INTMAP2_AWAKE (1 << 6) 105 #define ADXL362_INTMAP2_INACT (1 << 5) 106 #define ADXL362_INTMAP2_ACT (1 << 4) 107 #define ADXL362_INTMAP2_FIFO_OVERRUN (1 << 3) 108 #define ADXL362_INTMAP2_FIFO_WATERMARK (1 << 2) 109 #define ADXL362_INTMAP2_FIFO_READY (1 << 1) 110 #define ADXL362_INTMAP2_DATA_READY (1 << 0) 111 112 /* ADXL362_REG_FILTER_CTL definitions */ 113 #define ADXL362_FILTER_CTL_RANGE(x) (((x) & 0x3) << 6) 114 #define ADXL362_FILTER_CTL_RES (1 << 5) 115 #define ADXL362_FILTER_CTL_HALF_BW (1 << 4) 116 #define ADXL362_FILTER_CTL_EXT_SAMPLE (1 << 3) 117 #define ADXL362_FILTER_CTL_ODR(x) (((x) & 0x7) << 0) 118 119 /* ADXL362_FILTER_CTL_RANGE(x) options */ 120 #define ADXL362_RANGE_2G 0 /* +/-2 g */ 121 #define ADXL362_RANGE_4G 1 /* +/-4 g */ 122 #define ADXL362_RANGE_8G 2 /* +/-8 g */ 123 124 /* ADXL362_FILTER_CTL_ODR(x) options */ 125 #define ADXL362_ODR_12_5_HZ 0 /* 12.5 Hz */ 126 #define ADXL362_ODR_25_HZ 1 /* 25 Hz */ 127 #define ADXL362_ODR_50_HZ 2 /* 50 Hz */ 128 #define ADXL362_ODR_100_HZ 3 /* 100 Hz */ 129 #define ADXL362_ODR_200_HZ 4 /* 200 Hz */ 130 #define ADXL362_ODR_400_HZ 5 /* 400 Hz */ 131 132 /* ADXL362_REG_POWER_CTL definitions */ 133 #define ADXL362_POWER_CTL_RES (1 << 7) 134 #define ADXL362_POWER_CTL_EXT_CLK (1 << 6) 135 #define ADXL362_POWER_CTL_LOW_NOISE(x) (((x) & 0x3) << 4) 136 #define ADXL362_POWER_CTL_WAKEUP (1 << 3) 137 #define ADXL362_POWER_CTL_AUTOSLEEP (1 << 2) 138 #define ADXL362_POWER_CTL_MEASURE(x) (((x) & 0x3) << 0) 139 140 /* ADXL362_POWER_CTL_LOW_NOISE(x) options */ 141 #define ADXL362_NOISE_MODE_NORMAL 0 142 #define ADXL362_NOISE_MODE_LOW 1 143 #define ADXL362_NOISE_MODE_ULTRALOW 2 144 145 /* ADXL362_POWER_CTL_MEASURE(x) options */ 146 #define ADXL362_MEASURE_STANDBY 0 147 #define ADXL362_MEASURE_ON 2 148 149 /* ADXL362_REG_SELF_TEST */ 150 #define ADXL362_SELF_TEST_ST (1 << 0) 151 152 /* ADXL362 device information */ 153 #define ADXL362_DEVICE_AD 0xAD 154 #define ADXL362_DEVICE_MST 0x1D 155 #define ADXL362_PART_ID 0xF2 156 157 /* ADXL362 Reset settings */ 158 #define ADXL362_RESET_KEY 0x52 159 160 /* ADXL362 Status check */ 161 #define ADXL362_STATUS_CHECK_DATA_READY(x) (((x) >> 0) & 0x1) 162 #define ADXL362_STATUS_CHECK_INACT(x) (((x) >> 5) & 0x1) 163 #define ADXL362_STATUS_CHECK_ACTIVITY(x) (((x) >> 4) & 0x1) 164 #define ADXL362_STATUS_CHECK_FIFO_OVR(x) (((x) >> 3) & 0x1) 165 #define ADXL362_STATUS_CHECK_FIFO_WTR(x) (((x) >> 2) & 0x1) 166 167 /* ADXL362 scale factors from specifications */ 168 #define ADXL362_ACCEL_2G_LSB_PER_G 1000 169 #define ADXL362_ACCEL_4G_LSB_PER_G 500 170 #define ADXL362_ACCEL_8G_LSB_PER_G 235 171 172 /* ADXL362 temperature sensor specifications */ 173 #define ADXL362_TEMP_MC_PER_LSB 65 174 #define ADXL362_TEMP_BIAS_LSB 350 175 #define ADXL362_TEMP_BIAS_TEST_CONDITION 25 176 177 /* ADXL362 check fifo sample header */ 178 #define ADXL362_FIFO_HDR_CHECK_ACCEL_X(x) ((((x) & 0xC000) >> 14) == 0x00) 179 #define ADXL362_FIFO_HDR_CHECK_ACCEL_Y(x) ((((x) & 0xC000) >> 14) == 0x01) 180 #define ADXL362_FIFO_HDR_CHECK_ACCEL_Z(x) ((((x) & 0xC000) >> 14) == 0x02) 181 #define ADXL362_FIFO_HDR_CHECK_TEMP(x) ((((x) & 0xC000) >> 14) == 0x03) 182 183 struct adxl362_config { 184 struct spi_dt_spec bus; 185 #if defined(CONFIG_ADXL362_TRIGGER) 186 struct gpio_dt_spec interrupt; 187 uint8_t int1_config; 188 uint8_t int2_config; 189 #endif 190 uint8_t power_ctl; 191 }; 192 193 struct adxl362_data { 194 union { 195 int16_t acc_xyz[3]; 196 struct { 197 int16_t acc_x; 198 int16_t acc_y; 199 int16_t acc_z; 200 }; 201 } __packed; 202 int16_t temp; 203 uint8_t selected_range; 204 uint8_t accel_odr; 205 206 uint8_t fifo_mode; 207 uint8_t en_temp_read; 208 uint16_t water_mark_lvl; 209 210 #if defined(CONFIG_ADXL362_TRIGGER) 211 const struct device *dev; 212 struct gpio_callback gpio_cb; 213 struct k_mutex trigger_mutex; 214 215 sensor_trigger_handler_t inact_handler; 216 const struct sensor_trigger *inact_trigger; 217 sensor_trigger_handler_t act_handler; 218 const struct sensor_trigger *act_trigger; 219 sensor_trigger_handler_t drdy_handler; 220 const struct sensor_trigger *drdy_trigger; 221 222 #if defined(CONFIG_ADXL362_TRIGGER_OWN_THREAD) 223 K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_ADXL362_THREAD_STACK_SIZE); 224 struct k_sem gpio_sem; 225 struct k_thread thread; 226 #elif defined(CONFIG_ADXL362_TRIGGER_GLOBAL_THREAD) 227 struct k_work work; 228 #endif 229 #endif /* CONFIG_ADXL362_TRIGGER */ 230 #ifdef CONFIG_ADXL362_STREAM 231 uint8_t status; 232 uint8_t fifo_ent[2]; 233 struct rtio_iodev_sqe *sqe; 234 struct rtio *rtio_ctx; 235 struct rtio_iodev *iodev; 236 uint64_t timestamp; 237 struct rtio *r_cb; 238 uint8_t fifo_full_irq: 1; 239 uint8_t fifo_wmark_irq: 1; 240 uint8_t res: 6; 241 #endif /* CONFIG_ADXL362_STREAM */ 242 }; 243 244 struct adxl362_sample_data { 245 #ifdef CONFIG_ADXL362_STREAM 246 uint8_t is_fifo: 1; 247 uint8_t res: 7; 248 #endif /*CONFIG_ADXL362_STREAM*/ 249 uint8_t selected_range; 250 int16_t acc_x; 251 int16_t acc_y; 252 int16_t acc_z; 253 int16_t temp; 254 }; 255 256 struct adxl362_fifo_data { 257 uint8_t is_fifo: 1; 258 uint8_t has_tmp: 1; 259 uint8_t selected_range: 3; 260 uint8_t accel_odr: 3; 261 uint8_t int_status; 262 uint16_t fifo_byte_count; 263 uint64_t timestamp; 264 } __attribute__((__packed__)); 265 266 BUILD_ASSERT(sizeof(struct adxl362_fifo_data) % 4 == 0, 267 "adxl362_fifo_data struct should be word aligned"); 268 269 #if defined(CONFIG_ADXL362_ACCEL_RANGE_RUNTIME) ||\ 270 defined(CONFIG_ADXL362_ACCEL_RANGE_2G) 271 # define ADXL362_DEFAULT_RANGE_ACC ADXL362_RANGE_2G 272 #elif defined(CONFIG_ADXL362_ACCEL_RANGE_4G) 273 # define ADXL362_DEFAULT_RANGE_ACC ADXL362_RANGE_4G 274 #else 275 # define ADXL362_DEFAULT_RANGE_ACC ADXL362_RANGE_8G 276 #endif 277 278 #if defined(CONFIG_ADXL362_ACCEL_ODR_RUNTIME) ||\ 279 defined(CONFIG_ADXL362_ACCEL_ODR_12_5) 280 # define ADXL362_DEFAULT_ODR_ACC ADXL362_ODR_12_5_HZ 281 #elif defined(CONFIG_ADXL362_ACCEL_ODR_25) 282 # define ADXL362_DEFAULT_ODR_ACC ADXL362_ODR_25_HZ 283 #elif defined(CONFIG_ADXL362_ACCEL_ODR_50) 284 # define ADXL362_DEFAULT_ODR_ACC ADXL362_ODR_50_HZ 285 #elif defined(CONFIG_ADXL362_ACCEL_ODR_100) 286 # define ADXL362_DEFAULT_ODR_ACC ADXL362_ODR_100_HZ 287 #elif defined(CONFIG_ADXL362_ACCEL_ODR_200) 288 # define ADXL362_DEFAULT_ODR_ACC ADXL362_ODR_200_HZ 289 #else 290 # define ADXL362_DEFAULT_ODR_ACC ADXL362_ODR_400_HZ 291 #endif 292 293 void adxl362_submit_stream(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe); 294 void adxl362_stream_irq_handler(const struct device *dev); 295 int adxl362_fifo_read(const struct device *dev, void *buff, size_t length); 296 297 #ifdef CONFIG_ADXL362_TRIGGER 298 int adxl362_reg_write_mask(const struct device *dev, 299 uint8_t reg_addr, uint8_t mask, uint8_t data); 300 301 int adxl362_get_status(const struct device *dev, uint8_t *status); 302 303 int adxl362_interrupt_activity_enable(const struct device *dev); 304 305 int adxl362_trigger_set(const struct device *dev, 306 const struct sensor_trigger *trig, 307 sensor_trigger_handler_t handler); 308 309 int adxl362_init_interrupt(const struct device *dev); 310 311 int adxl362_set_interrupt_mode(const struct device *dev, uint8_t mode); 312 313 int adxl362_clear_data_ready(const struct device *dev); 314 #endif /* CONFIG_ADT7420_TRIGGER */ 315 316 #ifdef CONFIG_SENSOR_ASYNC_API 317 int adxl362_rtio_fetch(const struct device *dev, 318 struct adxl362_sample_data *sample_data); 319 void adxl362_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe); 320 int adxl362_get_decoder(const struct device *dev, const struct sensor_decoder_api **decoder); 321 void adxl362_accel_convert(struct sensor_value *val, int accel, 322 int range); 323 void adxl362_temp_convert(struct sensor_value *val, int temp); 324 #endif /* CONFIG_SENSOR_ASYNC_API */ 325 326 #ifdef CONFIG_ADXL362_STREAM 327 int adxl362_fifo_setup(const struct device *dev, uint8_t mode, 328 uint16_t water_mark_lvl, uint8_t en_temp_read); 329 #endif /* CONFIG_ADXL362_STREAM */ 330 331 int adxl362_reg_access(const struct device *dev, uint8_t cmd, 332 uint8_t reg_addr, void *data, size_t length); 333 #endif /* ZEPHYR_DRIVERS_SENSOR_ADXL362_ADXL362_H_ */ 334
