1 /****************************************************************************** 2 * 3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 4 * Analog Devices, Inc.), 5 * Copyright (C) 2023-2024 Analog Devices, Inc. 6 * 7 * Licensed under the Apache License, Version 2.0 (the "License"); 8 * you may not use this file except in compliance with the License. 9 * You may obtain a copy of the License at 10 * 11 * http://www.apache.org/licenses/LICENSE-2.0 12 * 13 * Unless required by applicable law or agreed to in writing, software 14 * distributed under the License is distributed on an "AS IS" BASIS, 15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16 * See the License for the specific language governing permissions and 17 * limitations under the License. 18 * 19 ******************************************************************************/ 20 21 #ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_EMAC_EMAC_REVA_H_ 22 #define LIBRARIES_PERIPHDRIVERS_SOURCE_EMAC_EMAC_REVA_H_ 23 24 /* **** Includes **** */ 25 #include <stddef.h> 26 #include "emac.h" 27 #include "emac_reva_regs.h" 28 29 /* **** Definitions **** */ 30 #define MAX_SYS_EMAC_RX_BUFFER_SIZE 16384 31 #define MAX_SYS_EMAC_RX_RING_SIZE 128 32 #define MAX_SYS_EMAC_TX_RING_SIZE 16 33 #define EMAC_RX_BUFFER_SIZE 128 34 #define CONFIG_SYS_EMAC_TX_TIMEOUT 1000 /**! Transmission Timeout in Microseconds */ 35 #define CONFIG_SYS_EMAC_AUTONEG_TIMEOUT 500000 /**! Auto Negotiation Timeout in Microseconds */ 36 37 #define RXADDR_USED 0x00000001 38 #define RXADDR_WRAP 0x00000002 39 #define RXBUF_FRMLEN_MASK 0x00000fff 40 #define RXBUF_FRAME_START 0x00004000 41 #define RXBUF_FRAME_END 0x00008000 42 #define RXBUF_TYPEID_MATCH 0x00400000 43 #define RXBUF_ADDR4_MATCH 0x00800000 44 #define RXBUF_ADDR3_MATCH 0x01000000 45 #define RXBUF_ADDR2_MATCH 0x02000000 46 #define RXBUF_ADDR1_MATCH 0x04000000 47 #define RXBUF_BROADCAST 0x80000000 48 #define TXBUF_FRMLEN_MASK 0x000007ff 49 #define TXBUF_FRAME_END 0x00008000 50 #define TXBUF_NOCRC 0x00010000 51 #define TXBUF_EXHAUSTED 0x08000000 52 #define TXBUF_UNDERRUN 0x10000000 53 #define TXBUF_MAXRETRY 0x20000000 54 #define TXBUF_WRAP 0x40000000 55 #define TXBUF_USED 0x80000000 56 57 /* Definitions for MII-Compatible Transceivers */ 58 #define MII_BMCR 0x00 /**! Basic Mode Control Register */ 59 #define MII_BMSR 0x01 /**! Basic Mode Status Register */ 60 #define MII_PHYSID1 0x02 /**! PHYS ID 1 */ 61 #define MII_PHYSID2 0x03 /**! PHYS ID 2 */ 62 #define MII_ADVERTISE 0x04 /**! Advertisement Control Register */ 63 #define MII_LPA 0x05 /**! Link Partner Ability Register */ 64 65 /* Basic Mode Control Register */ 66 #define BMCR_ANRESTART 0x0200 /**! Auto Negotiation Restart */ 67 #define BMCR_ANENABLE 0x1000 /**! Enable Auto Negotiation */ 68 69 /* Basic Mode Status Register */ 70 #define BMSR_LSTATUS 0x0004 /**! Link Status */ 71 #define BMSR_ANEGCOMPLETE 0x0020 /**! Auto Negotiation Complete */ 72 73 /* Advertisement Control Register */ 74 #define ADVERTISE_CSMA 0x0001 75 #define ADVERTISE_10HALF 0x0020 76 #define ADVERTISE_10FULL 0x0040 77 #define ADVERTISE_100HALF 0x0080 78 #define ADVERTISE_100FULL 0x0100 79 #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | ADVERTISE_CSMA) 80 #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | ADVERTISE_100HALF | ADVERTISE_100FULL) 81 82 /* Link Partner Ability Register */ 83 #define LPA_10HALF 0x0020 84 #define LPA_10FULL 0x0040 85 #define LPA_100HALF 0x0080 86 #define LPA_100FULL 0x0100 87 #define LPA_100BASE4 0x0200 88 89 /* Constants for CLK */ 90 #define EMAC_CLK_DIV8 0 91 #define EMAC_CLK_DIV16 1 92 #define EMAC_CLK_DIV32 2 93 #define EMAC_CLK_DIV64 3 94 95 /* **** Macros **** */ 96 /* Bit Manipulation */ 97 #define EMAC_BIT(reg, name) (1 << MXC_F_EMAC_REVA_##reg##_##name##_POS) 98 #define EMAC_BF(reg, name, value) \ 99 (((value) & (MXC_F_EMAC_REVA_##reg##_##name >> MXC_F_EMAC_REVA_##reg##_##name##_POS)) \ 100 << MXC_F_EMAC_REVA_##reg##_##name##_POS) 101 #define EMAC_BFEXT(reg, name, value) \ 102 (((value) >> MXC_F_EMAC_REVA_##reg##_##name##_POS) & \ 103 (MXC_F_EMAC_REVA_##reg##_##name >> MXC_F_EMAC_REVA_##reg##_##name##_POS)) 104 105 /* Register Access */ 106 #define REG_READL(a) (*(volatile uint32_t *)(a)) 107 #define REG_WRITEL(v, a) (*(volatile uint32_t *)(a) = (v)) 108 #define EMAC_READL(port, reg) REG_READL(&(port)->regs->reg) 109 #define EMAC_WRITEL(port, reg, value) REG_WRITEL((value), &(port)->regs->reg) 110 111 /* Misc */ 112 #define barrier() asm volatile("" ::: "memory") 113 114 /** @brief Enumeration for the EMAC interrupt events */ 115 typedef enum { 116 MXC_EMAC_REVA_EVENT_MPS = 117 MXC_F_EMAC_REVA_INT_EN_MPS, /**! Management Packet Sent Interrupt */ 118 MXC_EMAC_REVA_EVENT_RXCMPL = 119 MXC_F_EMAC_REVA_INT_EN_RXCMPL, /**! Receive Complete Interrupt */ 120 MXC_EMAC_REVA_EVENT_RXUBR = 121 MXC_F_EMAC_REVA_INT_EN_RXUBR, /**! RX Used Bit Read Interrupt */ 122 MXC_EMAC_REVA_EVENT_TXUBR = 123 MXC_F_EMAC_REVA_INT_EN_TXUBR, /**! TX Used Bit Read Interrupt */ 124 MXC_EMAC_REVA_EVENT_TXUR = 125 MXC_F_EMAC_REVA_INT_EN_TXUR, /**! Ethernet Transmit Underrun Interrupt */ 126 MXC_EMAC_REVA_EVENT_RLE = 127 MXC_F_EMAC_REVA_INT_EN_RLE, /**! Retry Limit Exceeded Interrupt */ 128 MXC_EMAC_REVA_EVENT_TXERR = 129 MXC_F_EMAC_REVA_INT_EN_TXERR, /**! Transmit Buffers Exhausted In Mid-Frame Interrupt */ 130 MXC_EMAC_REVA_EVENT_TXCMPL = 131 MXC_F_EMAC_REVA_INT_EN_TXCMPL, /**! Transmit Complete Interrupt */ 132 MXC_EMAC_REVA_EVENT_LC = 133 MXC_F_EMAC_REVA_INT_EN_LC, /**! Link Change Interrupt */ 134 MXC_EMAC_REVA_EVENT_RXOR = 135 MXC_F_EMAC_REVA_INT_EN_RXOR, /**! Receive Overrun Interrupt */ 136 MXC_EMAC_REVA_EVENT_HRESPNO = 137 MXC_F_EMAC_REVA_INT_EN_HRESPNO, /**! HRESP Not OK Interrupt */ 138 MXC_EMAC_REVA_EVENT_PPR = 139 MXC_F_EMAC_REVA_INT_EN_PPR, /**! Pause Packet Received Interrupt */ 140 MXC_EMAC_REVA_EVENT_PTZ = 141 MXC_F_EMAC_REVA_INT_EN_PTZ /**! Pause Time Zero Interrupt */ 142 } mxc_emac_reva_events_t; 143 144 /* **** Structures **** */ 145 146 /** 147 * @brief The information needed for an EMAC buffer descriptor 148 * 149 */ 150 typedef struct { 151 unsigned int addr; 152 unsigned int ctrl; 153 } mxc_emac_reva_dma_desc_t; 154 155 /** 156 * @brief The information needed by the EMAC driver to operate 157 * 158 */ 159 typedef struct { 160 mxc_emac_reva_regs_t *regs; 161 unsigned int rx_tail; 162 unsigned int tx_head; 163 unsigned int tx_tail; 164 void *rx_buffer; 165 void *tx_buffer; 166 mxc_emac_reva_dma_desc_t *rx_ring; 167 mxc_emac_reva_dma_desc_t *tx_ring; 168 unsigned int rx_buffer_dma; 169 unsigned int rx_ring_dma; 170 unsigned int tx_ring_dma; 171 uint16_t phy_addr; 172 173 unsigned int first_init; 174 unsigned int rx_buffer_size; 175 unsigned int rx_ring_size; 176 unsigned int tx_ring_size; 177 mxc_emac_delay_func_t delay_us; 178 mxc_emac_cb_funcs_tbl_t cb_funcs; 179 } mxc_emac_reva_device_t; 180 181 /** 182 * @brief The basic configuration information to set up EMAC module 183 * 184 */ 185 typedef struct { 186 unsigned char *rx_buff; 187 unsigned char *rx_ring_buff; 188 unsigned char *tx_ring_buff; 189 unsigned int rx_buff_size; 190 unsigned int rx_ring_buff_size; 191 unsigned int tx_ring_buff_size; 192 uint16_t phy_addr; 193 unsigned int interrupt_mode; 194 unsigned int interrupt_events; 195 mxc_emac_delay_func_t delay_us; 196 mxc_emac_cb_funcs_tbl_t conf_cb_funcs; 197 } mxc_emac_reva_config_t; 198 199 /* **** Function Prototypes **** */ 200 /* ************************************************************************* */ 201 /* Control/Configuration Functions */ 202 /* ************************************************************************* */ 203 int MXC_EMAC_RevA_Init(mxc_emac_reva_config_t *config); 204 int MXC_EMAC_RevA_SetConfiguration(mxc_emac_reva_config_t *config); 205 int MXC_EMAC_RevA_SetHwAddr(unsigned char *enetaddr); 206 int MXC_EMAC_RevA_EnableInterruptEvents(unsigned int events); 207 int MXC_EMAC_RevA_DisableInterruptEvents(unsigned int events); 208 209 /* ************************************************************************* */ 210 /* Low-Level Functions */ 211 /* ************************************************************************* */ 212 int MXC_EMAC_RevA_Start(void); 213 int MXC_EMAC_RevA_Stop(void); 214 int MXC_EMAC_RevA_ReadLinkStatus(void); 215 216 /* ************************************************************************* */ 217 /* Transaction-Level Functions */ 218 /* ************************************************************************* */ 219 int MXC_EMAC_RevA_SendSync(const void *packet, unsigned int length); 220 int MXC_EMAC_RevA_SendAsync(const void *packet, unsigned int length); 221 int MXC_EMAC_RevA_Recv(void *rx_buff, unsigned int max_len); 222 void MXC_EMAC_RevA_IrqHandler(void); 223 224 #endif // LIBRARIES_PERIPHDRIVERS_SOURCE_EMAC_EMAC_REVA_H_ 225
