1 /* 2 * Copyright (c) 2023 PHOENIX CONTACT Electronics GmbH 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ETH_ADIN2111_PRIV_H__ 7 #define ETH_ADIN2111_PRIV_H__ 8 9 #include <stdint.h> 10 #include <stdbool.h> 11 #include <zephyr/kernel.h> 12 #include <zephyr/drivers/gpio.h> 13 #include <zephyr/drivers/spi.h> 14 #include <zephyr/net/net_if.h> 15 #include <ethernet/eth_stats.h> 16 17 /* SPI frequency maximum, based on clock cycle time */ 18 #define ADIN2111_SPI_MAX_FREQUENCY 25000000U 19 20 #define ADIN2111_PHYID 0x01U 21 /* PHY Identification Register Reset Value */ 22 #define ADIN2111_PHYID_RST_VAL 0x0283BCA1U 23 #define ADIN1110_PHYID_RST_VAL 0x0283BC91U 24 25 /* Reset Control and Status Register */ 26 #define ADIN2111_RESET 0x03U 27 /* MACPHY software reset */ 28 #define ADIN2111_RESET_SWRESET BIT(0) 29 30 /* Configuration Register 0 */ 31 #define ADIN2111_CONFIG0 0x04U 32 /* Configuration Synchronization */ 33 #define ADIN2111_CONFIG0_SYNC BIT(15) 34 /* Transmit Frame Check Sequence Validation Enable */ 35 #define ADIN2111_CONFIG0_TXFCSVE BIT(14) 36 /* Zero Align Receive Frame Enable */ 37 #define ADIN2111_CONFIG0_ZARFE BIT(12) 38 /* New packet received only after a new CS assertion */ 39 #define ADIN2111_CONFIG0_CSARFE BIT(13) 40 /* Transmit Cut Through Enable */ 41 #define ADIN2111_CONFIG0_TXCTE BIT(9) 42 /* Receive Cut Through Enable. Must be 0 for Generic SPI */ 43 #define ADIN2111_CONFIG0_RXCTE BIT(8) 44 45 /* Configuration Register 2 */ 46 #define ADIN2111_CONFIG2 0x06U 47 /* Forward Frames from Port 2 Not Matching a MAC Address to Port 1 */ 48 #define ADIN2111_CONFIG2_P2_FWD_UNK2P1 BIT(14) 49 /* Forward Frames from Port 1 Not Matching a MAC Address to Port 2 */ 50 #define ADIN2111_CONFIG2_P1_FWD_UNK2P2 BIT(13) 51 /* Forward Frames Not Matching Any MAC Address to the Host */ 52 #define ADIN2111_CONFIG2_P2_FWD_UNK2HOST BIT(12) 53 /* Enable Cut Through from Port to Port */ 54 #define ADIN2111_CONFIG2_PORT_CUT_THRU_EN BIT(11) 55 /* Enable CRC Append */ 56 #define ADIN2111_CONFIG2_CRC_APPEND BIT(5) 57 /* Forward Frames Not Matching Any MAC Address to the Host */ 58 #define ADIN2111_CONFIG2_P1_FWD_UNK2HOST BIT(2) 59 60 /* Status Register 0 */ 61 #define ADIN2111_STATUS0 0x08U 62 /* PHY Interrupt for Port 1 */ 63 #define ADIN2111_STATUS0_PHYINT BIT(7) 64 /** 65 * Reset Complete. 66 * The bit is set when the MACPHY reset is complete 67 * and ready for configuration. 68 */ 69 #define ADIN2111_STATUS0_RESETC BIT(6) 70 /* Value to completely clear status register 0 */ 71 #define ADIN2111_STATUS0_CLEAR 0x1F7FU 72 73 /* Status Register 1 */ 74 #define ADIN2111_STATUS1 0x09U 75 /* PHY Interrupt for Port 2 */ 76 #define ADIN2111_STATUS1_PHYINT BIT(19) 77 /* Port 2 RX FIFO Contains Data */ 78 #define ADIN2111_STATUS1_P2_RX_RDY BIT(17) 79 /* Indicates that a CRC error was detected */ 80 #define ADIN2111_STATUS1_SPI_ERR BIT(10) 81 /* Port 1 RX FIFO Contains Data */ 82 #define ADIN2111_STATUS1_P1_RX_RDY BIT(4) 83 /* Frame transmitted */ 84 #define ADIN2111_STATUS1_TX_RDY BIT(3) 85 /* Value to completely clear status register 1 */ 86 #define ADIN2111_STATUS1_CLEAR 0xFFF01F08U 87 88 /* Buffer Status Register */ 89 #define ADIN2111_BUFSTS 0x0BU 90 /* Rx chunks available */ 91 #define ADIN2111_BUFSTS_RCA_MASK GENMASK(7, 0) 92 /* Tx credits */ 93 #define ADIN2111_BUFSTS_TXC 8U 94 #define ADIN2111_BUFSTS_TXC_MASK GENMASK(15, 8) 95 96 /* Interrupt Mask Register 0 */ 97 #define ADIN2111_IMASK0 0x0CU 98 /* Physical Layer Interrupt Mask */ 99 #define ADIN2111_IMASK0_PHYINTM BIT(7) 100 101 /* Interrupt Mask Register 1 */ 102 #define ADIN2111_IMASK1 0x0DU 103 /* Mask Bit for P2_PHYINT */ 104 #define ADIN2111_IMASK1_P2_PHYINT_MASK BIT(19) 105 /*!< Mask Bit for P2_RX_RDY. Generic SPI only.*/ 106 #define ADIN2111_IMASK1_P2_RX_RDY_MASK BIT(17) 107 /*!< Mask Bit for SPI_ERR. Generic SPI only. */ 108 #define ADIN2111_IMASK1_SPI_ERR_MASK BIT(10) 109 /*!< Mask Bit for P1_RX_RDY. Generic SPI only.*/ 110 #define ADIN2111_IMASK1_P1_RX_RDY_MASK BIT(4) 111 /*!< Mask Bit for TX_FRM_DONE. Generic SPI only.*/ 112 #define ADIN2111_IMASK1_TX_RDY_MASK BIT(3) 113 114 /* MAC Tx Frame Size Register */ 115 #define ADIN2111_TX_FSIZE 0x30U 116 /* Tx FIFO Space Register */ 117 #define ADIN2111_TX_SPACE 0x32U 118 119 /* MAC Address Rule and DA Filter Upper 16 Bits Registers */ 120 #define ADIN2111_ADDR_FILT_UPR 0x50U 121 #define ADIN2111_ADDR_APPLY2PORT2 BIT(31) 122 #define ADIN2111_ADDR_APPLY2PORT1 BIT(30) 123 #define ADIN2111_ADDR_TO_OTHER_PORT BIT(17) 124 #define ADIN2111_ADDR_TO_HOST BIT(16) 125 126 /* MAC Address DA Filter Lower 32 Bits Registers */ 127 #define ADIN2111_ADDR_FILT_LWR 0x51U 128 /* Upper 16 Bits of the MAC Address Mask */ 129 #define ADIN2111_ADDR_MSK_UPR 0x70U 130 /* Lower 32 Bits of the MAC Address Mask */ 131 #define ADIN2111_ADDR_MSK_LWR 0x71U 132 133 /* P1 MAC Rx Frame Size Register */ 134 #define ADIN2111_P1_RX_FSIZE 0x90U 135 /* P1 MAC Receive Register */ 136 #define ADIN2111_P1_RX 0x91U 137 138 /* P2 MAC Rx Frame Size Register */ 139 #define ADIN2111_P2_RX_FSIZE 0xC0U 140 /* P2 MAC Receive Register */ 141 #define ADIN2111_P2_RX 0xC1U 142 143 /* MAC reset status */ 144 #define ADIN1110_MAC_RST_STATUS_REG 0x3BU 145 146 /* MAC reset */ 147 #define ADIN2111_SOFT_RST_REG 0x3CU 148 #define ADIN2111_SWRESET_KEY1 0x4F1CU 149 #define ADIN2111_SWRESET_KEY2 0xC1F4U 150 #define ADIN2111_SWRELEASE_KEY1 0x6F1AU 151 #define ADIN2111_SWRELEASE_KEY2 0xA1F6U 152 153 /* SPI header size in bytes */ 154 #define ADIN2111_SPI_HEADER_SIZE 2U 155 /* SPI header size for write transaction */ 156 #define ADIN2111_WRITE_HEADER_SIZE ADIN2111_SPI_HEADER_SIZE 157 /* SPI header size for read transaction (1 for TA) */ 158 #define ADIN2111_READ_HEADER_SIZE (ADIN2111_SPI_HEADER_SIZE + 1U) 159 160 /* SPI register write buffer size without CRC */ 161 #define ADIN2111_REG_WRITE_BUF_SIZE (ADIN2111_WRITE_HEADER_SIZE + sizeof(uint32_t)) 162 /* SPI register write buffer with appended CRC size (1 for header, 1 for register) */ 163 #define ADIN2111_REG_WRITE_BUF_SIZE_CRC (ADIN2111_REG_WRITE_BUF_SIZE + 2U) 164 165 /* SPI register read buffer size with TA without CRC */ 166 #define ADIN2111_REG_READ_BUF_SIZE (ADIN2111_READ_HEADER_SIZE + sizeof(uint32_t)) 167 /* SPI register read buffer with TA and appended CRC size (1 header, 1 for register) */ 168 #define ADIN2111_REG_READ_BUF_SIZE_CRC (ADIN2111_REG_READ_BUF_SIZE + 2U) 169 170 /* SPI read fifo cmd buffer size with TA without CRC */ 171 #define ADIN2111_FIFO_READ_CMD_BUF_SIZE (ADIN2111_READ_HEADER_SIZE) 172 /* SPI read fifo cmd buffer with TA and appended CRC size */ 173 #define ADIN2111_FIFO_READ_CMD_BUF_SIZE_CRC (ADIN2111_FIFO_READ_CMD_BUF_SIZE + 1U) 174 175 /* SPI Header for writing control transaction in half duplex mode */ 176 #define ADIN2111_WRITE_TXN_CTRL 0xA000U 177 /* SPI Header for writing control transaction with MAC TX register (!) in half duplex mode */ 178 #define ADIN2111_TXN_CTRL_TX_REG 0xA031U 179 /* SPI Header for reading control transaction in half duplex mode */ 180 #define ADIN2111_READ_TXN_CTRL 0x8000U 181 182 /* Frame header size in bytes */ 183 #define ADIN2111_FRAME_HEADER_SIZE 2U 184 #define ADIN2111_INTERNAL_HEADER_SIZE 2U 185 /* Number of buffer bytes in TxFIFO to provide frame margin upon writes */ 186 #define ADIN2111_TX_FIFO_BUFFER_MARGIN 4U 187 188 /* Manufacturer unique ID */ 189 #define ADIN2111_PHYID_OUI 0xa0ef 190 191 /* Open Alliance definitions */ 192 #define ADIN2111_OA_ALLOC_TIMEOUT K_MSEC(10) 193 /* Max setting to a max RCA of 255 68-bytes ckunks */ 194 #define ADIN2111_OA_BUF_SZ (255U * 64U) 195 196 #define ADIN2111_OA_CTL_LEN_PROT 16U 197 #define ADIN2111_OA_CTL_LEN 12U 198 #define ADIN2111_OA_CTL_MMS BIT(24) 199 #define ADIN2111_OA_CTL_WNR BIT(29) 200 201 #define ADIN2111_OA_DATA_HDR_DNC BIT(31) 202 #define ADIN2111_OA_DATA_HDR_NORX BIT(29) 203 #define ADIN2111_OA_DATA_HDR_VS 22U 204 #define ADIN2111_OA_DATA_HDR_DV BIT(21) 205 #define ADIN2111_OA_DATA_HDR_SV BIT(20) 206 #define ADIN2111_OA_DATA_HDR_EV BIT(14) 207 #define ADIN2111_OA_DATA_HDR_EBO 8U 208 209 #define ADIN2111_OA_DATA_FTR_SYNC BIT(29) 210 #define ADIN2111_OA_DATA_FTR_EBO 8U 211 #define ADIN2111_OA_DATA_FTR_DV BIT(21) 212 #define ADIN2111_OA_DATA_FTR_SV BIT(20) 213 #define ADIN2111_OA_DATA_FTR_EV BIT(14) 214 #define ADIN2111_OA_DATA_FTR_SWO 16U 215 #define ADIN2111_OA_DATA_FTR_SWO_MSK GENMASK(19, 16) 216 #define ADIN2111_OA_DATA_FTR_EBO 8U 217 #define ADIN2111_OA_DATA_FTR_EBO_MSK GENMASK(13, 8) 218 219 enum adin2111_chips_id { 220 ADIN2111_MAC = 0, 221 ADIN1110_MAC, 222 }; 223 224 struct adin2111_config { 225 enum adin2111_chips_id id; 226 struct spi_dt_spec spi; 227 struct gpio_dt_spec interrupt; 228 struct gpio_dt_spec reset; 229 }; 230 231 struct adin2111_data { 232 struct k_mutex lock; 233 struct k_sem offload_sem; 234 uint32_t imask0; 235 uint32_t imask1; 236 uint8_t *buf; 237 /* Port 0: PHY 1, Port 1: PHY 2 */ 238 const struct device *port[2]; 239 uint8_t *oa_tx_buf; 240 uint8_t *oa_rx_buf; 241 uint16_t ifaces_left_to_init; 242 uint16_t scur; 243 struct gpio_callback gpio_int_callback; 244 bool oa; 245 bool oa_prot; 246 uint8_t oa_cps; 247 K_KERNEL_STACK_MEMBER(rx_thread_stack, CONFIG_ETH_ADIN2111_IRQ_THREAD_STACK_SIZE); 248 struct k_thread rx_thread; 249 }; 250 251 struct adin2111_port_data { 252 struct net_if *iface; 253 uint8_t mac_addr[6]; 254 #if defined(CONFIG_NET_STATISTICS_ETHERNET) 255 struct net_stats_eth stats; 256 #endif /* CONFIG_NET_STATISTICS_ETHERNET */ 257 }; 258 259 struct adin2111_port_config { 260 const struct device *adin; 261 const struct device *phy; 262 const uint16_t port_idx; 263 const uint16_t phy_addr; 264 }; 265 266 #endif /* ETH_ADIN2111_PRIV_H__ */ 267
