1 /* 2 * Copyright (c) 2023 PHOENIX CONTACT Electronics GmbH 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ETH_ADIN2111_PRIV_H__ 7 #define ETH_ADIN2111_PRIV_H__ 8 9 #include <stdint.h> 10 #include <stdbool.h> 11 #include <zephyr/kernel.h> 12 #include <zephyr/drivers/gpio.h> 13 #include <zephyr/drivers/spi.h> 14 #include <zephyr/net/net_if.h> 15 #include <ethernet/eth_stats.h> 16 17 /* SPI frequency maximum, based on clock cycle time */ 18 #define ADIN2111_SPI_MAX_FREQUENCY 25000000U 19 20 #define ADIN2111_PHYID 0x01U 21 /* PHY Identification Register Reset Value */ 22 #define ADIN2111_PHYID_RST_VAL 0x0283BCA1U 23 #define ADIN1110_PHYID_RST_VAL 0x0283BC91U 24 25 /* Reset Control and Status Register */ 26 #define ADIN2111_RESET 0x03U 27 /* MACPHY software reset */ 28 #define ADIN2111_RESET_SWRESET BIT(0) 29 30 /* Configuration Register 0 */ 31 #define ADIN2111_CONFIG0 0x04U 32 /* Configuration Synchronization */ 33 #define ADIN2111_CONFIG0_SYNC BIT(15) 34 /* Transmit Frame Check Sequence Validation Enable */ 35 #define ADIN2111_CONFIG0_TXFCSVE BIT(14) 36 /* Transmit Cut Through Enable */ 37 #define ADIN2111_CONFIG0_TXCTE BIT(9) 38 /* Receive Cut Through Enable. Must be 0 for Generic SPI */ 39 #define ADIN2111_CONFIG0_RXCTE BIT(8) 40 41 /* Configuration Register 2 */ 42 #define ADIN2111_CONFIG2 0x06U 43 /* Forward Frames from Port 2 Not Matching a MAC Address to Port 1 */ 44 #define ADIN2111_CONFIG2_P2_FWD_UNK2P1 BIT(14) 45 /* Forward Frames from Port 1 Not Matching a MAC Address to Port 2 */ 46 #define ADIN2111_CONFIG2_P1_FWD_UNK2P2 BIT(13) 47 /* Enable Cut Through from Port to Port */ 48 #define ADIN2111_CONFIG2_PORT_CUT_THRU_EN BIT(11) 49 /* Enable CRC Append */ 50 #define ADIN2111_CONFIG2_CRC_APPEND BIT(5) 51 52 /* Status Register 0 */ 53 #define ADIN2111_STATUS0 0x08U 54 /* PHY Interrupt for Port 1 */ 55 #define ADIN2111_STATUS0_PHYINT BIT(7) 56 /** 57 * Reset Complete. 58 * The bit is set when the MACPHY reset is complete 59 * and ready for configuration. 60 */ 61 #define ADIN2111_STATUS0_RESETC BIT(6) 62 /* Value to completely clear status register 0 */ 63 #define ADIN2111_STATUS0_CLEAR 0x1F7FU 64 65 /* Status Register 1 */ 66 #define ADIN2111_STATUS1 0x09U 67 /* PHY Interrupt for Port 2 */ 68 #define ADIN2111_STATUS1_PHYINT BIT(19) 69 /* Port 2 RX FIFO Contains Data */ 70 #define ADIN2111_STATUS1_P2_RX_RDY BIT(17) 71 /* Indicates that a CRC error was detected */ 72 #define ADIN2111_STATUS1_SPI_ERR BIT(10) 73 /* Port 1 RX FIFO Contains Data */ 74 #define ADIN2111_STATUS1_P1_RX_RDY BIT(4) 75 /* Value to completely clear status register 1 */ 76 #define ADIN2111_STATUS1_CLEAR 0xFFF01F08U 77 78 79 /* Interrupt Mask Register 0 */ 80 #define ADIN2111_IMASK0 0x0CU 81 /* Physical Layer Interrupt Mask */ 82 #define ADIN2111_IMASK0_PHYINTM BIT(7) 83 84 /* Interrupt Mask Register 1 */ 85 #define ADIN2111_IMASK1 0x0DU 86 /* Mask Bit for P2_PHYINT */ 87 #define ADIN2111_IMASK1_P2_PHYINT_MASK BIT(19) 88 /*!< Mask Bit for P2_RX_RDY. Generic SPI only.*/ 89 #define ADIN2111_IMASK1_P2_RX_RDY_MASK BIT(17) 90 /*!< Mask Bit for SPI_ERR. Generic SPI only. */ 91 #define ADIN2111_IMASK1_SPI_ERR_MASK BIT(10) 92 /*!< Mask Bit for P1_RX_RDY. Generic SPI only.*/ 93 #define ADIN2111_IMASK1_P1_RX_RDY_MASK BIT(4) 94 /*!< Mask Bit for TX_FRM_DONE. Generic SPI only.*/ 95 #define ADIN2111_IMASK1_TX_RDY_MASK BIT(4) 96 97 /* MAC Tx Frame Size Register */ 98 #define ADIN2111_TX_FSIZE 0x30U 99 /* Tx FIFO Space Register */ 100 #define ADIN2111_TX_SPACE 0x32U 101 102 /* MAC Address Rule and DA Filter Upper 16 Bits Registers */ 103 #define ADIN2111_ADDR_FILT_UPR 0x50U 104 #define ADIN2111_ADDR_APPLY2PORT2 BIT(31) 105 #define ADIN2111_ADDR_APPLY2PORT1 BIT(30) 106 #define ADIN2111_ADDR_TO_OTHER_PORT BIT(17) 107 #define ADIN2111_ADDR_TO_HOST BIT(16) 108 109 /* MAC Address DA Filter Lower 32 Bits Registers */ 110 #define ADIN2111_ADDR_FILT_LWR 0x51U 111 /* Upper 16 Bits of the MAC Address Mask */ 112 #define ADIN2111_ADDR_MSK_UPR 0x70U 113 /* Lower 32 Bits of the MAC Address Mask */ 114 #define ADIN2111_ADDR_MSK_LWR 0x71U 115 116 /* P1 MAC Rx Frame Size Register */ 117 #define ADIN2111_P1_RX_FSIZE 0x90U 118 /* P1 MAC Receive Register */ 119 #define ADIN2111_P1_RX 0x91U 120 121 /* P2 MAC Rx Frame Size Register */ 122 #define ADIN2111_P2_RX_FSIZE 0xC0U 123 /* P2 MAC Receive Register */ 124 #define ADIN2111_P2_RX 0xC1U 125 126 /* SPI header size in bytes */ 127 #define ADIN2111_SPI_HEADER_SIZE 2U 128 /* SPI header size for write transaction */ 129 #define ADIN2111_WRITE_HEADER_SIZE ADIN2111_SPI_HEADER_SIZE 130 /* SPI header size for read transaction (1 for TA) */ 131 #define ADIN2111_READ_HEADER_SIZE (ADIN2111_SPI_HEADER_SIZE + 1U) 132 133 /* SPI register write buffer size without CRC */ 134 #define ADIN2111_REG_WRITE_BUF_SIZE (ADIN2111_WRITE_HEADER_SIZE + sizeof(uint32_t)) 135 /* SPI register write buffer with appended CRC size (1 for header, 1 for register) */ 136 #define ADIN2111_REG_WRITE_BUF_SIZE_CRC (ADIN2111_REG_WRITE_BUF_SIZE + 2U) 137 138 /* SPI register read buffer size with TA without CRC */ 139 #define ADIN2111_REG_READ_BUF_SIZE (ADIN2111_READ_HEADER_SIZE + sizeof(uint32_t)) 140 /* SPI register read buffer with TA and appended CRC size (1 header, 1 for register) */ 141 #define ADIN2111_REG_READ_BUF_SIZE_CRC (ADIN2111_REG_READ_BUF_SIZE + 2U) 142 143 /* SPI read fifo cmd buffer size with TA without CRC */ 144 #define ADIN2111_FIFO_READ_CMD_BUF_SIZE (ADIN2111_READ_HEADER_SIZE) 145 /* SPI read fifo cmd buffer with TA and appended CRC size */ 146 #define ADIN2111_FIFO_READ_CMD_BUF_SIZE_CRC (ADIN2111_FIFO_READ_CMD_BUF_SIZE + 1U) 147 148 /* SPI Header for writing control transaction in half duplex mode */ 149 #define ADIN2111_WRITE_TXN_CTRL 0xA000U 150 /* SPI Header for writing control transaction with MAC TX register (!) in half duplex mode */ 151 #define ADIN2111_TXN_CTRL_TX_REG 0xA031U 152 /* SPI Header for reading control transaction in half duplex mode */ 153 #define ADIN2111_READ_TXN_CTRL 0x8000U 154 155 /* Frame header size in bytes */ 156 #define ADIN2111_FRAME_HEADER_SIZE 2U 157 #define ADIN2111_INTERNAL_HEADER_SIZE 2U 158 /* Number of buffer bytes in TxFIFO to provide frame margin upon writes */ 159 #define ADIN2111_TX_FIFO_BUFFER_MARGIN 4U 160 161 enum adin2111_chips_id { 162 ADIN2111_MAC = 0, 163 ADIN1110_MAC, 164 }; 165 166 struct adin2111_config { 167 enum adin2111_chips_id id; 168 struct spi_dt_spec spi; 169 struct gpio_dt_spec interrupt; 170 struct gpio_dt_spec reset; 171 }; 172 173 struct adin2111_data { 174 /* Port 0: PHY 1, Port 1: PHY 2 */ 175 const struct device *port[2]; 176 struct gpio_callback gpio_int_callback; 177 struct k_sem offload_sem; 178 struct k_mutex lock; 179 uint32_t imask0; 180 uint32_t imask1; 181 uint16_t ifaces_left_to_init; 182 uint8_t *buf; 183 184 K_KERNEL_STACK_MEMBER(rx_thread_stack, CONFIG_ETH_ADIN2111_IRQ_THREAD_STACK_SIZE); 185 struct k_thread rx_thread; 186 }; 187 188 struct adin2111_port_data { 189 struct net_if *iface; 190 uint8_t mac_addr[6]; 191 #if defined(CONFIG_NET_STATISTICS_ETHERNET) 192 struct net_stats_eth stats; 193 #endif /* CONFIG_NET_STATISTICS_ETHERNET */ 194 }; 195 196 struct adin2111_port_config { 197 const struct device *adin; 198 const struct device *phy; 199 const uint16_t port_idx; 200 const uint16_t phy_addr; 201 }; 202 203 #endif /* ETH_ADIN2111_PRIV_H__ */ 204
