1 /* 2 * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #pragma once 8 #include "hal/adc_types.h" 9 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 /** 15 * @brief ADC resolution setting option. 16 * @note Only used in single read mode 17 */ 18 typedef enum { 19 #if CONFIG_IDF_TARGET_ESP32 20 ADC_WIDTH_BIT_9 = 9, /*!< ADC capture width is 9Bit. */ 21 ADC_WIDTH_BIT_10 = 10, /*!< ADC capture width is 10Bit. */ 22 ADC_WIDTH_BIT_11 = 11, /*!< ADC capture width is 11Bit. */ 23 ADC_WIDTH_BIT_12 = 12, /*!< ADC capture width is 12Bit. */ 24 #elif SOC_ADC_RTC_MAX_BITWIDTH == 12 25 ADC_WIDTH_BIT_12 = 12, /*!< ADC capture width is 12Bit. */ 26 #elif SOC_ADC_RTC_MAX_BITWIDTH == 13 27 ADC_WIDTH_BIT_13 = 13, /*!< ADC capture width is 13Bit. */ 28 #endif 29 ADC_WIDTH_MAX, 30 } adc_bits_width_t; 31 32 /** 33 * The default (max) bit width of the ADC of current version. You can also get the maximum bitwidth 34 * by `SOC_ADC_RTC_MAX_BITWIDTH` defined in soc_caps.h. 35 */ 36 #define ADC_WIDTH_BIT_DEFAULT (ADC_WIDTH_MAX-1) 37 38 #if CONFIG_IDF_TARGET_ESP32 39 typedef enum { 40 ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO36 */ 41 ADC1_CHANNEL_1, /*!< ADC1 channel 1 is GPIO37 */ 42 ADC1_CHANNEL_2, /*!< ADC1 channel 2 is GPIO38 */ 43 ADC1_CHANNEL_3, /*!< ADC1 channel 3 is GPIO39 */ 44 ADC1_CHANNEL_4, /*!< ADC1 channel 4 is GPIO32 */ 45 ADC1_CHANNEL_5, /*!< ADC1 channel 5 is GPIO33 */ 46 ADC1_CHANNEL_6, /*!< ADC1 channel 6 is GPIO34 */ 47 ADC1_CHANNEL_7, /*!< ADC1 channel 7 is GPIO35 */ 48 ADC1_CHANNEL_MAX, 49 } adc1_channel_t; 50 #elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 51 typedef enum { 52 ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO1 */ 53 ADC1_CHANNEL_1, /*!< ADC1 channel 1 is GPIO2 */ 54 ADC1_CHANNEL_2, /*!< ADC1 channel 2 is GPIO3 */ 55 ADC1_CHANNEL_3, /*!< ADC1 channel 3 is GPIO4 */ 56 ADC1_CHANNEL_4, /*!< ADC1 channel 4 is GPIO5 */ 57 ADC1_CHANNEL_5, /*!< ADC1 channel 5 is GPIO6 */ 58 ADC1_CHANNEL_6, /*!< ADC1 channel 6 is GPIO7 */ 59 ADC1_CHANNEL_7, /*!< ADC1 channel 7 is GPIO8 */ 60 ADC1_CHANNEL_8, /*!< ADC1 channel 8 is GPIO9 */ 61 ADC1_CHANNEL_9, /*!< ADC1 channel 9 is GPIO10 */ 62 ADC1_CHANNEL_MAX, 63 } adc1_channel_t; 64 #elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 65 typedef enum { 66 ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO0 */ 67 ADC1_CHANNEL_1, /*!< ADC1 channel 1 is GPIO1 */ 68 ADC1_CHANNEL_2, /*!< ADC1 channel 2 is GPIO2 */ 69 ADC1_CHANNEL_3, /*!< ADC1 channel 3 is GPIO3 */ 70 ADC1_CHANNEL_4, /*!< ADC1 channel 4 is GPIO4 */ 71 ADC1_CHANNEL_MAX, 72 } adc1_channel_t; 73 #elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 74 typedef enum { 75 ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO0 */ 76 ADC1_CHANNEL_1, /*!< ADC1 channel 1 is GPIO1 */ 77 ADC1_CHANNEL_2, /*!< ADC1 channel 2 is GPIO2 */ 78 ADC1_CHANNEL_3, /*!< ADC1 channel 3 is GPIO3 */ 79 ADC1_CHANNEL_4, /*!< ADC1 channel 4 is GPIO4 */ 80 ADC1_CHANNEL_5, /*!< ADC1 channel 5 is GPIO5 */ 81 ADC1_CHANNEL_6, /*!< ADC1 channel 6 is GPIO6 */ 82 ADC1_CHANNEL_MAX, 83 } adc1_channel_t; 84 #endif // CONFIG_IDF_TARGET_* 85 86 #if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 87 typedef enum { 88 ADC2_CHANNEL_0 = 0, /*!< ADC2 channel 0 is GPIO4 (ESP32), GPIO11 (ESP32-S2) */ 89 ADC2_CHANNEL_1, /*!< ADC2 channel 1 is GPIO0 (ESP32), GPIO12 (ESP32-S2) */ 90 ADC2_CHANNEL_2, /*!< ADC2 channel 2 is GPIO2 (ESP32), GPIO13 (ESP32-S2) */ 91 ADC2_CHANNEL_3, /*!< ADC2 channel 3 is GPIO15 (ESP32), GPIO14 (ESP32-S2) */ 92 ADC2_CHANNEL_4, /*!< ADC2 channel 4 is GPIO13 (ESP32), GPIO15 (ESP32-S2) */ 93 ADC2_CHANNEL_5, /*!< ADC2 channel 5 is GPIO12 (ESP32), GPIO16 (ESP32-S2) */ 94 ADC2_CHANNEL_6, /*!< ADC2 channel 6 is GPIO14 (ESP32), GPIO17 (ESP32-S2) */ 95 ADC2_CHANNEL_7, /*!< ADC2 channel 7 is GPIO27 (ESP32), GPIO18 (ESP32-S2) */ 96 ADC2_CHANNEL_8, /*!< ADC2 channel 8 is GPIO25 (ESP32), GPIO19 (ESP32-S2) */ 97 ADC2_CHANNEL_9, /*!< ADC2 channel 9 is GPIO26 (ESP32), GPIO20 (ESP32-S2) */ 98 ADC2_CHANNEL_MAX, 99 } adc2_channel_t; 100 #elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 101 // ESP32C6 has no ADC2 102 typedef enum { 103 ADC2_CHANNEL_0 = 0, /*!< ADC2 channel 0 is GPIO5 */ 104 ADC2_CHANNEL_MAX, 105 } adc2_channel_t; 106 #endif 107 108 #if SOC_ADC_DMA_SUPPORTED 109 /** 110 * @brief Digital ADC DMA read max timeout value, it may make the ``adc_digi_read_bytes`` block forever if the OS supports 111 */ 112 #define ADC_MAX_DELAY UINT32_MAX 113 114 /** 115 * @brief ADC DMA driver configuration 116 */ 117 typedef struct adc_digi_init_config_s { 118 uint32_t max_store_buf_size; ///< Max length of the converted data that driver can store before they are processed. 119 uint32_t conv_num_each_intr; ///< Bytes of data that can be converted in 1 interrupt. This should be in multiples of `SOC_ADC_DIGI_DATA_BYTES_PER_CONV`. 120 uint32_t adc1_chan_mask; ///< Channel list of ADC1 to be initialized. 121 uint32_t adc2_chan_mask; ///< Channel list of ADC2 to be initialized. 122 } adc_digi_init_config_t; 123 124 /** 125 * @brief ADC digital controller settings 126 */ 127 typedef struct { 128 bool conv_limit_en; ///< Suggest leaving it empty, this parameter has been deprecated 129 uint32_t conv_limit_num; ///< suggest leaving it empty, this parameter has been deprecated 130 uint32_t pattern_num; ///< Number of ADC channels that will be used 131 adc_digi_pattern_config_t *adc_pattern; ///< List of configs for each ADC channel that will be used 132 uint32_t sample_freq_hz; /*!< Please refer to `soc/soc_caps.h` to know the ADC sampling frequency range*/ 133 adc_digi_convert_mode_t conv_mode; ///< ADC DMA conversion mode, see `adc_digi_convert_mode_t`. 134 adc_digi_output_format_t format; ///< ADC DMA conversion output format, see `adc_digi_output_format_t`. 135 } adc_digi_configuration_t; 136 #endif // #if SOC_ADC_DMA_SUPPORTED 137 138 #ifdef __cplusplus 139 } 140 #endif 141
