1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
7 *
8 * o Redistributions of source code must retain the above copyright notice, this list
9 * of conditions and the following disclaimer.
10 *
11 * o Redistributions in binary form must reproduce the above copyright notice, this
12 * list of conditions and the following disclaimer in the documentation and/or
13 * other materials provided with the distribution.
14 *
15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include "adc_imx7d.h"
32
33 /*******************************************************************************
34 * Code
35 ******************************************************************************/
36
37 /*******************************************************************************
38 * ADC Module Initialization and Configuration functions.
39 ******************************************************************************/
40 /*FUNCTION**********************************************************************
41 *
42 * Function Name : ADC_Init
43 * Description : Initialize ADC to reset state and initialize with initialize
44 * structure.
45 *
46 *END**************************************************************************/
ADC_Init(ADC_Type * base,const adc_init_config_t * initConfig)47 void ADC_Init(ADC_Type* base, const adc_init_config_t* initConfig)
48 {
49 assert(initConfig);
50
51 /* Reset ADC register to its default value. */
52 ADC_Deinit(base);
53
54 /* Set ADC Module Sample Rate */
55 ADC_SetSampleRate(base, initConfig->sampleRate);
56
57 /* Enable ADC Build-in voltage level shifter */
58 if (initConfig->levelShifterEnable)
59 ADC_LevelShifterEnable(base);
60 else
61 ADC_LevelShifterDisable(base);
62
63 /* Wait until ADC module power-up completely. */
64 while((ADC_ADC_CFG_REG(base) & ADC_ADC_CFG_ADC_PD_OK_MASK));
65 }
66
67 /*FUNCTION**********************************************************************
68 *
69 * Function Name : ADC_Deinit
70 * Description : This function reset ADC module register content to its
71 * default value.
72 *
73 *END**************************************************************************/
ADC_Deinit(ADC_Type * base)74 void ADC_Deinit(ADC_Type* base)
75 {
76 /* Stop all continues conversions */
77 ADC_SetConvertCmd(base, adcLogicChA, false);
78 ADC_SetConvertCmd(base, adcLogicChB, false);
79 ADC_SetConvertCmd(base, adcLogicChC, false);
80 ADC_SetConvertCmd(base, adcLogicChD, false);
81
82 /* Reset ADC Module Register content to default value */
83 ADC_CH_A_CFG1_REG(base) = 0x0;
84 ADC_CH_A_CFG2_REG(base) = ADC_CH_A_CFG2_CHA_AUTO_DIS_MASK;
85 ADC_CH_B_CFG1_REG(base) = 0x0;
86 ADC_CH_B_CFG2_REG(base) = ADC_CH_B_CFG2_CHB_AUTO_DIS_MASK;
87 ADC_CH_C_CFG1_REG(base) = 0x0;
88 ADC_CH_C_CFG2_REG(base) = ADC_CH_C_CFG2_CHC_AUTO_DIS_MASK;
89 ADC_CH_D_CFG1_REG(base) = 0x0;
90 ADC_CH_D_CFG2_REG(base) = ADC_CH_D_CFG2_CHD_AUTO_DIS_MASK;
91 ADC_CH_SW_CFG_REG(base) = 0x0;
92 ADC_TIMER_UNIT_REG(base) = 0x0;
93 ADC_DMA_FIFO_REG(base) = ADC_DMA_FIFO_DMA_WM_LVL(0xF);
94 ADC_INT_SIG_EN_REG(base) = 0x0;
95 ADC_INT_EN_REG(base) = 0x0;
96 ADC_INT_STATUS_REG(base) = 0x0;
97 ADC_ADC_CFG_REG(base) = ADC_ADC_CFG_ADC_EN_MASK;
98 }
99
100 /*FUNCTION**********************************************************************
101 *
102 * Function Name : ADC_SetSampleRate
103 * Description : This function is used to set ADC module sample rate.
104 *
105 *END**************************************************************************/
ADC_SetSampleRate(ADC_Type * base,uint32_t sampleRate)106 void ADC_SetSampleRate(ADC_Type* base, uint32_t sampleRate)
107 {
108 uint8_t preDiv;
109 uint8_t coreTimerUnit;
110
111 assert((sampleRate <= 1000000) && (sampleRate >= 1563));
112
113 for (preDiv = 0 ; preDiv < 6; preDiv++)
114 {
115 uint32_t divider = 24000000 >> (2 + preDiv);
116 divider /= sampleRate * 6;
117 if(divider <= 32)
118 {
119 coreTimerUnit = divider - 1;
120 break;
121 }
122 }
123
124 if (0x6 == preDiv)
125 {
126 preDiv = 0x5;
127 coreTimerUnit = 0x1F;
128 }
129
130 ADC_TIMER_UNIT_REG(base) = 0x0;
131 ADC_TIMER_UNIT_REG(base) = ADC_TIMER_UNIT_PRE_DIV(preDiv) | ADC_TIMER_UNIT_CORE_TIMER_UNIT(coreTimerUnit);
132 }
133
134 /*******************************************************************************
135 * ADC Low power control functions.
136 ******************************************************************************/
137 /*FUNCTION**********************************************************************
138 *
139 * Function Name : ADC_SetClockDownCmd
140 * Description : This function is used to stop all digital part power.
141 *
142 *END**************************************************************************/
ADC_SetClockDownCmd(ADC_Type * base,bool clockDown)143 void ADC_SetClockDownCmd(ADC_Type* base, bool clockDown)
144 {
145 if (clockDown)
146 ADC_ADC_CFG_REG(base) |= ADC_ADC_CFG_ADC_CLK_DOWN_MASK;
147 else
148 ADC_ADC_CFG_REG(base) &= ~ADC_ADC_CFG_ADC_CLK_DOWN_MASK;
149 }
150
151 /*FUNCTION**********************************************************************
152 *
153 * Function Name : ADC_SetPowerDownCmd
154 * Description : This function is used to power down ADC analogue core.
155 * Before entering into stop-mode, power down ADC analogue
156 * core first.
157 *
158 *END**************************************************************************/
ADC_SetPowerDownCmd(ADC_Type * base,bool powerDown)159 void ADC_SetPowerDownCmd(ADC_Type* base, bool powerDown)
160 {
161 if (powerDown)
162 {
163 ADC_ADC_CFG_REG(base) |= ADC_ADC_CFG_ADC_PD_MASK;
164 /* Wait until power down action finish. */
165 while((ADC_ADC_CFG_REG(base) & ADC_ADC_CFG_ADC_PD_OK_MASK));
166 }
167 else
168 {
169 ADC_ADC_CFG_REG(base) &= ~ADC_ADC_CFG_ADC_PD_MASK;
170 }
171 }
172
173 /*******************************************************************************
174 * ADC Convert Channel Initialization and Configuration functions.
175 ******************************************************************************/
176
177 /*FUNCTION**********************************************************************
178 *
179 * Function Name : ADC_LogicChInit
180 * Description : Initialize ADC Logic channel with initialization structure.
181 *
182 *END**************************************************************************/
ADC_LogicChInit(ADC_Type * base,uint8_t logicCh,const adc_logic_ch_init_config_t * chInitConfig)183 void ADC_LogicChInit(ADC_Type* base, uint8_t logicCh, const adc_logic_ch_init_config_t* chInitConfig)
184 {
185 assert(chInitConfig);
186
187 /* Select input channel */
188 ADC_SelectInputCh(base, logicCh, chInitConfig->inputChannel);
189
190 /* Set Continuous Convert Rate. */
191 if (chInitConfig->coutinuousEnable)
192 ADC_SetConvertRate(base, logicCh, chInitConfig->convertRate);
193
194 /* Set Hardware average Number. */
195 if (chInitConfig->averageEnable)
196 {
197 ADC_SetAverageNum(base, logicCh, chInitConfig->averageNumber);
198 ADC_SetAverageCmd(base, logicCh, true);
199 }
200 }
201
202 /*FUNCTION**********************************************************************
203 *
204 * Function Name : ADC_LogicChDeinit
205 * Description : Reset target ADC logic channel registers to default value.
206 *
207 *END**************************************************************************/
ADC_LogicChDeinit(ADC_Type * base,uint8_t logicCh)208 void ADC_LogicChDeinit(ADC_Type* base, uint8_t logicCh)
209 {
210 assert(logicCh <= adcLogicChSW);
211
212 switch (logicCh)
213 {
214 case adcLogicChA:
215 ADC_CH_A_CFG1_REG(base) = 0x0;
216 ADC_CH_A_CFG2_REG(base) = 0x8000;
217 break;
218 case adcLogicChB:
219 ADC_CH_B_CFG1_REG(base) = 0x0;
220 ADC_CH_B_CFG2_REG(base) = 0x8000;
221 break;
222 case adcLogicChC:
223 ADC_CH_C_CFG1_REG(base) = 0x0;
224 ADC_CH_C_CFG2_REG(base) = 0x8000;
225 break;
226 case adcLogicChD:
227 ADC_CH_D_CFG1_REG(base) = 0x0;
228 ADC_CH_D_CFG2_REG(base) = 0x8000;
229 break;
230 case adcLogicChSW:
231 ADC_CH_SW_CFG_REG(base) = 0x0;
232 break;
233 default:
234 break;
235 }
236 }
237
238 /*FUNCTION**********************************************************************
239 *
240 * Function Name : ADC_SelectInputCh
241 * Description : Select input channel for target logic channel.
242 *
243 *END**************************************************************************/
ADC_SelectInputCh(ADC_Type * base,uint8_t logicCh,uint8_t inputCh)244 void ADC_SelectInputCh(ADC_Type* base, uint8_t logicCh, uint8_t inputCh)
245 {
246 assert(logicCh <= adcLogicChSW);
247
248 switch (logicCh)
249 {
250 case adcLogicChA:
251 ADC_CH_A_CFG1_REG(base) = (ADC_CH_A_CFG1_REG(base) & ~ADC_CH_A_CFG1_CHA_SEL_MASK) | \
252 ADC_CH_A_CFG1_CHA_SEL(inputCh);
253 break;
254 case adcLogicChB:
255 ADC_CH_B_CFG1_REG(base) = (ADC_CH_B_CFG1_REG(base) & ~ADC_CH_B_CFG1_CHB_SEL_MASK) | \
256 ADC_CH_B_CFG1_CHB_SEL(inputCh);
257 break;
258 case adcLogicChC:
259 ADC_CH_C_CFG1_REG(base) = (ADC_CH_C_CFG1_REG(base) & ~ADC_CH_C_CFG1_CHC_SEL_MASK) | \
260 ADC_CH_C_CFG1_CHC_SEL(inputCh);
261 break;
262 case adcLogicChD:
263 ADC_CH_D_CFG1_REG(base) = (ADC_CH_D_CFG1_REG(base) & ~ADC_CH_D_CFG1_CHD_SEL_MASK) | \
264 ADC_CH_D_CFG1_CHD_SEL(inputCh);
265 break;
266 case adcLogicChSW:
267 ADC_CH_SW_CFG_REG(base) = (ADC_CH_SW_CFG_REG(base) & ~ADC_CH_SW_CFG_CH_SW_SEL_MASK) | \
268 ADC_CH_SW_CFG_CH_SW_SEL(inputCh);
269 break;
270 default:
271 break;
272 }
273 }
274
275 /*FUNCTION**********************************************************************
276 *
277 * Function Name : ADC_SetConvertRate
278 * Description : Set ADC conversion rate of target logic channel.
279 *
280 *END**************************************************************************/
ADC_SetConvertRate(ADC_Type * base,uint8_t logicCh,uint32_t convertRate)281 void ADC_SetConvertRate(ADC_Type* base, uint8_t logicCh, uint32_t convertRate)
282 {
283 assert(logicCh <= adcLogicChD);
284
285 /* Calculate ADC module's current sample rate */
286 uint32_t sampleRate = (4000000 >> (2 + (ADC_TIMER_UNIT_REG(base) >> ADC_TIMER_UNIT_PRE_DIV_SHIFT))) / \
287 ((ADC_TIMER_UNIT_REG(base) & ADC_TIMER_UNIT_CORE_TIMER_UNIT_MASK) + 1);
288
289 uint32_t convertDiv = sampleRate / convertRate;
290 assert((sampleRate / convertRate) <= ADC_CH_A_CFG1_CHA_TIMER_MASK);
291
292 switch (logicCh)
293 {
294 case adcLogicChA:
295 ADC_CH_A_CFG1_REG(base) = (ADC_CH_A_CFG1_REG(base) & ~ADC_CH_A_CFG1_CHA_TIMER_MASK) | \
296 ADC_CH_A_CFG1_CHA_TIMER(convertDiv);
297 break;
298 case adcLogicChB:
299 ADC_CH_B_CFG1_REG(base) = (ADC_CH_B_CFG1_REG(base) & ~ADC_CH_B_CFG1_CHB_TIMER_MASK) | \
300 ADC_CH_B_CFG1_CHB_TIMER(convertDiv);
301 break;
302 case adcLogicChC:
303 ADC_CH_C_CFG1_REG(base) = (ADC_CH_C_CFG1_REG(base) & ~ADC_CH_C_CFG1_CHC_TIMER_MASK) | \
304 ADC_CH_C_CFG1_CHC_TIMER(convertDiv);
305 break;
306 case adcLogicChD:
307 ADC_CH_D_CFG1_REG(base) = (ADC_CH_D_CFG1_REG(base) & ~ADC_CH_D_CFG1_CHD_TIMER_MASK) | \
308 ADC_CH_D_CFG1_CHD_TIMER(convertDiv);
309 break;
310 default:
311 break;
312 }
313 }
314
315 /*FUNCTION**********************************************************************
316 *
317 * Function Name : ADC_SetAverageCmd
318 * Description : Set work state of hardware average feature of target
319 * logic channel.
320 *
321 *END**************************************************************************/
ADC_SetAverageCmd(ADC_Type * base,uint8_t logicCh,bool enable)322 void ADC_SetAverageCmd(ADC_Type* base, uint8_t logicCh, bool enable)
323 {
324 assert(logicCh <= adcLogicChSW);
325
326 if (enable)
327 {
328 switch (logicCh)
329 {
330 case adcLogicChA:
331 ADC_CH_A_CFG1_REG(base) |= ADC_CH_A_CFG1_CHA_AVG_EN_MASK;
332 break;
333 case adcLogicChB:
334 ADC_CH_B_CFG1_REG(base) |= ADC_CH_B_CFG1_CHB_AVG_EN_MASK;
335 break;
336 case adcLogicChC:
337 ADC_CH_C_CFG1_REG(base) |= ADC_CH_C_CFG1_CHC_AVG_EN_MASK;
338 break;
339 case adcLogicChD:
340 ADC_CH_D_CFG1_REG(base) |= ADC_CH_D_CFG1_CHD_AVG_EN_MASK;
341 break;
342 case adcLogicChSW:
343 ADC_CH_SW_CFG_REG(base) |= ADC_CH_SW_CFG_CH_SW_AVG_EN_MASK;
344 break;
345 default:
346 break;
347 }
348 }
349 else
350 {
351 switch (logicCh)
352 {
353 case adcLogicChA:
354 ADC_CH_A_CFG1_REG(base) &= ~ADC_CH_A_CFG1_CHA_AVG_EN_MASK;
355 break;
356 case adcLogicChB:
357 ADC_CH_B_CFG1_REG(base) &= ~ADC_CH_B_CFG1_CHB_AVG_EN_MASK;
358 break;
359 case adcLogicChC:
360 ADC_CH_C_CFG1_REG(base) &= ~ADC_CH_C_CFG1_CHC_AVG_EN_MASK;
361 break;
362 case adcLogicChD:
363 ADC_CH_D_CFG1_REG(base) &= ~ADC_CH_D_CFG1_CHD_AVG_EN_MASK;
364 break;
365 case adcLogicChSW:
366 ADC_CH_SW_CFG_REG(base) &= ~ADC_CH_SW_CFG_CH_SW_AVG_EN_MASK;
367 break;
368 default:
369 break;
370 }
371 }
372 }
373
374 /*FUNCTION**********************************************************************
375 *
376 * Function Name : ADC_SetAverageNum
377 * Description : Set hardware average number of target logic channel.
378 *
379 *END**************************************************************************/
ADC_SetAverageNum(ADC_Type * base,uint8_t logicCh,uint8_t avgNum)380 void ADC_SetAverageNum(ADC_Type* base, uint8_t logicCh, uint8_t avgNum)
381 {
382 assert(logicCh <= adcLogicChSW);
383 assert(avgNum <= adcAvgNum32);
384
385 switch (logicCh)
386 {
387 case adcLogicChA:
388 ADC_CH_A_CFG2_REG(base) = (ADC_CH_A_CFG2_REG(base) & ~ADC_CH_A_CFG2_CHA_AVG_NUMBER_MASK) | \
389 ADC_CH_A_CFG2_CHA_AVG_NUMBER(avgNum);
390 break;
391 case adcLogicChB:
392 ADC_CH_B_CFG2_REG(base) = (ADC_CH_B_CFG2_REG(base) & ~ADC_CH_B_CFG2_CHB_AVG_NUMBER_MASK) | \
393 ADC_CH_B_CFG2_CHB_AVG_NUMBER(avgNum);
394 break;
395 case adcLogicChC:
396 ADC_CH_C_CFG2_REG(base) = (ADC_CH_C_CFG2_REG(base) & ~ADC_CH_C_CFG2_CHC_AVG_NUMBER_MASK) | \
397 ADC_CH_C_CFG2_CHC_AVG_NUMBER(avgNum);
398 break;
399 case adcLogicChD:
400 ADC_CH_D_CFG2_REG(base) = (ADC_CH_D_CFG2_REG(base) & ~ADC_CH_D_CFG2_CHD_AVG_NUMBER_MASK) | \
401 ADC_CH_D_CFG2_CHD_AVG_NUMBER(avgNum);
402 break;
403 case adcLogicChSW:
404 ADC_CH_SW_CFG_REG(base) = (ADC_CH_SW_CFG_REG(base) & ~ADC_CH_SW_CFG_CH_SW_AVG_NUMBER_MASK) | \
405 ADC_CH_SW_CFG_CH_SW_AVG_NUMBER(avgNum);
406 break;
407 default:
408 break;
409 }
410 }
411
412 /*******************************************************************************
413 * ADC Conversion Control functions.
414 ******************************************************************************/
415 /*FUNCTION**********************************************************************
416 *
417 * Function Name : ADC_SetConvertCmd
418 * Description : Set continuous convert work mode of target logic channel.
419 *
420 *END**************************************************************************/
ADC_SetConvertCmd(ADC_Type * base,uint8_t logicCh,bool enable)421 void ADC_SetConvertCmd(ADC_Type* base, uint8_t logicCh, bool enable)
422 {
423 assert(logicCh <= adcLogicChD);
424
425 if (enable)
426 {
427 switch (logicCh)
428 {
429 case adcLogicChA:
430 ADC_CH_A_CFG1_REG(base) = (ADC_CH_A_CFG1_REG(base) & ~ADC_CH_A_CFG1_CHA_SINGLE_MASK) |
431 ADC_CH_A_CFG1_CHA_EN_MASK;
432 break;
433 case adcLogicChB:
434 ADC_CH_B_CFG1_REG(base) = (ADC_CH_B_CFG1_REG(base) & ~ADC_CH_B_CFG1_CHB_SINGLE_MASK) |
435 ADC_CH_B_CFG1_CHB_EN_MASK;
436 break;
437 case adcLogicChC:
438 ADC_CH_C_CFG1_REG(base) = (ADC_CH_C_CFG1_REG(base) & ~ADC_CH_C_CFG1_CHC_SINGLE_MASK) |
439 ADC_CH_C_CFG1_CHC_EN_MASK;
440 break;
441 case adcLogicChD:
442 ADC_CH_D_CFG1_REG(base) = (ADC_CH_D_CFG1_REG(base) & ~ADC_CH_D_CFG1_CHD_SINGLE_MASK) |
443 ADC_CH_D_CFG1_CHD_EN_MASK;
444 break;
445 default:
446 break;
447 }
448 }
449 else
450 {
451 switch (logicCh)
452 {
453 case adcLogicChA:
454 ADC_CH_A_CFG1_REG(base) &= ~ADC_CH_A_CFG1_CHA_EN_MASK;
455 break;
456 case adcLogicChB:
457 ADC_CH_B_CFG1_REG(base) &= ~ADC_CH_B_CFG1_CHB_EN_MASK;
458 break;
459 case adcLogicChC:
460 ADC_CH_C_CFG1_REG(base) &= ~ADC_CH_C_CFG1_CHC_EN_MASK;
461 break;
462 case adcLogicChD:
463 ADC_CH_D_CFG1_REG(base) &= ~ADC_CH_D_CFG1_CHD_EN_MASK;
464 break;
465 default:
466 break;
467 }
468 }
469 }
470
471 /*FUNCTION**********************************************************************
472 *
473 * Function Name : ADC_TriggerSingleConvert
474 * Description : Trigger single time convert on the target logic channel.
475 *
476 *END**************************************************************************/
ADC_TriggerSingleConvert(ADC_Type * base,uint8_t logicCh)477 void ADC_TriggerSingleConvert(ADC_Type* base, uint8_t logicCh)
478 {
479 assert(logicCh <= adcLogicChSW);
480
481 switch (logicCh)
482 {
483 case adcLogicChA:
484 ADC_CH_A_CFG1_REG(base) |= ADC_CH_A_CFG1_CHA_SINGLE_MASK | ADC_CH_A_CFG1_CHA_EN_MASK;
485 break;
486 case adcLogicChB:
487 ADC_CH_B_CFG1_REG(base) |= ADC_CH_B_CFG1_CHB_SINGLE_MASK | ADC_CH_B_CFG1_CHB_EN_MASK;
488 break;
489 case adcLogicChC:
490 ADC_CH_C_CFG1_REG(base) |= ADC_CH_C_CFG1_CHC_SINGLE_MASK | ADC_CH_C_CFG1_CHC_EN_MASK;
491 break;
492 case adcLogicChD:
493 ADC_CH_D_CFG1_REG(base) |= ADC_CH_D_CFG1_CHD_SINGLE_MASK | ADC_CH_D_CFG1_CHD_EN_MASK;
494 break;
495 case adcLogicChSW:
496 ADC_CH_SW_CFG_REG(base) |= ADC_CH_SW_CFG_START_CONV_MASK;
497 break;
498 default:
499 break;
500 }
501 }
502
503 /*FUNCTION**********************************************************************
504 *
505 * Function Name : ADC_StopConvert
506 * Description : Stop current convert on the target logic channel.
507 *
508 *END**************************************************************************/
ADC_StopConvert(ADC_Type * base,uint8_t logicCh)509 void ADC_StopConvert(ADC_Type* base, uint8_t logicCh)
510 {
511 assert(logicCh <= adcLogicChSW);
512
513 switch (logicCh)
514 {
515 case adcLogicChA:
516 ADC_CH_A_CFG1_REG(base) &= ~ADC_CH_A_CFG1_CHA_EN_MASK;
517 break;
518 case adcLogicChB:
519 ADC_CH_B_CFG1_REG(base) &= ~ADC_CH_B_CFG1_CHB_EN_MASK;
520 break;
521 case adcLogicChC:
522 ADC_CH_C_CFG1_REG(base) &= ~ADC_CH_C_CFG1_CHC_EN_MASK;
523 break;
524 case adcLogicChD:
525 ADC_CH_D_CFG1_REG(base) &= ~ADC_CH_D_CFG1_CHD_EN_MASK;
526 break;
527 case adcLogicChSW:
528 /* Wait until ADC conversion finish. */
529 while (ADC_CH_SW_CFG_REG(base) & ADC_CH_SW_CFG_START_CONV_MASK);
530 break;
531 default:
532 break;
533 }
534 }
535
536 /*FUNCTION**********************************************************************
537 *
538 * Function Name : ADC_GetConvertResult
539 * Description : Get 12-bit length right aligned convert result.
540 *
541 *END**************************************************************************/
ADC_GetConvertResult(ADC_Type * base,uint8_t logicCh)542 uint16_t ADC_GetConvertResult(ADC_Type* base, uint8_t logicCh)
543 {
544 assert(logicCh <= adcLogicChSW);
545
546 switch (logicCh)
547 {
548 case adcLogicChA:
549 return ADC_CHA_B_CNV_RSLT_REG(base) & ADC_CHA_B_CNV_RSLT_CHA_CNV_RSLT_MASK;
550 case adcLogicChB:
551 return ADC_CHA_B_CNV_RSLT_REG(base) >> ADC_CHA_B_CNV_RSLT_CHB_CNV_RSLT_SHIFT;
552 case adcLogicChC:
553 return ADC_CHC_D_CNV_RSLT_REG(base) & ADC_CHC_D_CNV_RSLT_CHC_CNV_RSLT_MASK;
554 case adcLogicChD:
555 return ADC_CHC_D_CNV_RSLT_REG(base) >> ADC_CHC_D_CNV_RSLT_CHD_CNV_RSLT_SHIFT;
556 case adcLogicChSW:
557 return ADC_CH_SW_CNV_RSLT_REG(base) & ADC_CH_SW_CNV_RSLT_CH_SW_CNV_RSLT_MASK;
558 default:
559 return 0;
560 }
561 }
562
563 /*******************************************************************************
564 * ADC Comparer Control functions.
565 ******************************************************************************/
566 /*FUNCTION**********************************************************************
567 *
568 * Function Name : ADC_SetCmpMode
569 * Description : Set the work mode of ADC module build-in comparer on target
570 * logic channel.
571 *
572 *END**************************************************************************/
ADC_SetCmpMode(ADC_Type * base,uint8_t logicCh,uint8_t cmpMode)573 void ADC_SetCmpMode(ADC_Type* base, uint8_t logicCh, uint8_t cmpMode)
574 {
575 assert(logicCh <= adcLogicChD);
576 assert(cmpMode <= adcCmpModeOutOffInterval);
577
578 switch (logicCh)
579 {
580 case adcLogicChA:
581 ADC_CH_A_CFG2_REG(base) = (ADC_CH_A_CFG2_REG(base) & ~ADC_CH_A_CFG2_CHA_CMP_MODE_MASK) | \
582 ADC_CH_A_CFG2_CHA_CMP_MODE(cmpMode);
583 break;
584 case adcLogicChB:
585 ADC_CH_B_CFG2_REG(base) = (ADC_CH_B_CFG2_REG(base) & ~ADC_CH_B_CFG2_CHB_CMP_MODE_MASK) | \
586 ADC_CH_B_CFG2_CHB_CMP_MODE(cmpMode);
587 break;
588 case adcLogicChC:
589 ADC_CH_C_CFG2_REG(base) = (ADC_CH_C_CFG2_REG(base) & ~ADC_CH_C_CFG2_CHC_CMP_MODE_MASK) | \
590 ADC_CH_C_CFG2_CHC_CMP_MODE(cmpMode);
591 break;
592 case adcLogicChD:
593 ADC_CH_D_CFG2_REG(base) = (ADC_CH_D_CFG2_REG(base) & ~ADC_CH_D_CFG2_CHD_CMP_MODE_MASK) | \
594 ADC_CH_D_CFG2_CHD_CMP_MODE(cmpMode);
595 break;
596 default:
597 break;
598 }
599 }
600
601 /*FUNCTION**********************************************************************
602 *
603 * Function Name : ADC_SetCmpHighThres
604 * Description : Set ADC module build-in comparer high threshold on target
605 * logic channel.
606 *
607 *END**************************************************************************/
ADC_SetCmpHighThres(ADC_Type * base,uint8_t logicCh,uint16_t threshold)608 void ADC_SetCmpHighThres(ADC_Type* base, uint8_t logicCh, uint16_t threshold)
609 {
610 assert(logicCh <= adcLogicChD);
611 assert(threshold <= 0xFFF);
612
613 switch (logicCh)
614 {
615 case adcLogicChA:
616 ADC_CH_A_CFG2_REG(base) = (ADC_CH_A_CFG2_REG(base) & ~ADC_CH_A_CFG2_CHA_HIGH_THRES_MASK) | \
617 ADC_CH_A_CFG2_CHA_HIGH_THRES(threshold);
618 break;
619 case adcLogicChB:
620 ADC_CH_B_CFG2_REG(base) = (ADC_CH_B_CFG2_REG(base) & ~ADC_CH_B_CFG2_CHB_HIGH_THRES_MASK) | \
621 ADC_CH_B_CFG2_CHB_HIGH_THRES(threshold);
622 break;
623 case adcLogicChC:
624 ADC_CH_C_CFG2_REG(base) = (ADC_CH_C_CFG2_REG(base) & ~ADC_CH_C_CFG2_CHC_HIGH_THRES_MASK) | \
625 ADC_CH_C_CFG2_CHC_HIGH_THRES(threshold);
626 break;
627 case adcLogicChD:
628 ADC_CH_D_CFG2_REG(base) = (ADC_CH_D_CFG2_REG(base) & ~ADC_CH_D_CFG2_CHD_HIGH_THRES_MASK) | \
629 ADC_CH_D_CFG2_CHD_HIGH_THRES(threshold);
630 break;
631 default:
632 break;
633 }
634 }
635
636 /*FUNCTION**********************************************************************
637 *
638 * Function Name : ADC_SetCmpLowThres
639 * Description : Set ADC module build-in comparer low threshold on target
640 * logic channel.
641 *
642 *END**************************************************************************/
ADC_SetCmpLowThres(ADC_Type * base,uint8_t logicCh,uint16_t threshold)643 void ADC_SetCmpLowThres(ADC_Type* base, uint8_t logicCh, uint16_t threshold)
644 {
645 assert(logicCh <= adcLogicChD);
646 assert(threshold <= 0xFFF);
647
648 switch (logicCh)
649 {
650 case adcLogicChA:
651 ADC_CH_A_CFG2_REG(base) = (ADC_CH_A_CFG2_REG(base) & ~ADC_CH_A_CFG2_CHA_LOW_THRES_MASK) | \
652 ADC_CH_A_CFG2_CHA_LOW_THRES(threshold);
653 break;
654 case adcLogicChB:
655 ADC_CH_B_CFG2_REG(base) = (ADC_CH_B_CFG2_REG(base) & ~ADC_CH_B_CFG2_CHB_LOW_THRES_MASK) | \
656 ADC_CH_B_CFG2_CHB_LOW_THRES(threshold);
657 break;
658 case adcLogicChC:
659 ADC_CH_C_CFG2_REG(base) = (ADC_CH_C_CFG2_REG(base) & ~ADC_CH_C_CFG2_CHC_LOW_THRES_MASK) | \
660 ADC_CH_B_CFG2_CHB_LOW_THRES(threshold);
661 break;
662 case adcLogicChD:
663 ADC_CH_D_CFG2_REG(base) = (ADC_CH_D_CFG2_REG(base) & ~ADC_CH_D_CFG2_CHD_LOW_THRES_MASK) | \
664 ADC_CH_D_CFG2_CHD_LOW_THRES(threshold);
665 break;
666 default:
667 break;
668 }
669 }
670
671 /*FUNCTION**********************************************************************
672 *
673 * Function Name : ADC_SetAutoDisableCmd
674 * Description : Set the working mode of ADC module auto disable feature on
675 * target logic channel.
676 *
677 *END**************************************************************************/
ADC_SetAutoDisableCmd(ADC_Type * base,uint8_t logicCh,bool enable)678 void ADC_SetAutoDisableCmd(ADC_Type* base, uint8_t logicCh, bool enable)
679 {
680 assert(logicCh <= adcLogicChD);
681
682 if (enable)
683 {
684 switch (logicCh)
685 {
686 case adcLogicChA:
687 ADC_CH_A_CFG2_REG(base) |= ADC_CH_A_CFG2_CHA_AUTO_DIS_MASK;
688 break;
689 case adcLogicChB:
690 ADC_CH_B_CFG2_REG(base) |= ADC_CH_B_CFG2_CHB_AUTO_DIS_MASK;
691 break;
692 case adcLogicChC:
693 ADC_CH_C_CFG2_REG(base) |= ADC_CH_C_CFG2_CHC_AUTO_DIS_MASK;
694 break;
695 case adcLogicChD:
696 ADC_CH_D_CFG2_REG(base) |= ADC_CH_D_CFG2_CHD_AUTO_DIS_MASK;
697 break;
698 default:
699 break;
700 }
701 }
702 else
703 {
704 switch (logicCh)
705 {
706 case adcLogicChA:
707 ADC_CH_A_CFG2_REG(base) &= ~ADC_CH_A_CFG2_CHA_AUTO_DIS_MASK;
708 break;
709 case adcLogicChB:
710 ADC_CH_B_CFG2_REG(base) &= ~ADC_CH_B_CFG2_CHB_AUTO_DIS_MASK;
711 break;
712 case adcLogicChC:
713 ADC_CH_C_CFG2_REG(base) &= ~ADC_CH_C_CFG2_CHC_AUTO_DIS_MASK;
714 break;
715 case adcLogicChD:
716 ADC_CH_D_CFG2_REG(base) &= ~ADC_CH_D_CFG2_CHD_AUTO_DIS_MASK;
717 break;
718 default:
719 break;
720 }
721 }
722 }
723
724 /*******************************************************************************
725 * Interrupt and Flag control functions.
726 ******************************************************************************/
727 /*FUNCTION**********************************************************************
728 *
729 * Function Name : ADC_SetIntCmd
730 * Description : Enables or disables ADC interrupt requests.
731 *
732 *END**************************************************************************/
ADC_SetIntCmd(ADC_Type * base,uint32_t intSource,bool enable)733 void ADC_SetIntCmd(ADC_Type* base, uint32_t intSource, bool enable)
734 {
735 if (enable)
736 ADC_INT_EN_REG(base) |= intSource;
737 else
738 ADC_INT_EN_REG(base) &= ~intSource;
739 }
740
741 /*FUNCTION**********************************************************************
742 *
743 * Function Name : ADC_SetIntSigCmd
744 * Description : Enables or disables ADC interrupt flag when interrupt
745 * condition met.
746 *
747 *END**************************************************************************/
ADC_SetIntSigCmd(ADC_Type * base,uint32_t intSignal,bool enable)748 void ADC_SetIntSigCmd(ADC_Type* base, uint32_t intSignal, bool enable)
749 {
750 if (enable)
751 ADC_INT_SIG_EN_REG(base) |= intSignal;
752 else
753 ADC_INT_SIG_EN_REG(base) &= ~intSignal;
754 }
755
756 /*******************************************************************************
757 * DMA & FIFO control functions.
758 ******************************************************************************/
759 /*FUNCTION**********************************************************************
760 *
761 * Function Name : ADC_SetDmaReset
762 * Description : Set the reset state of ADC internal DMA part.
763 *
764 *END**************************************************************************/
ADC_SetDmaReset(ADC_Type * base,bool active)765 void ADC_SetDmaReset(ADC_Type* base, bool active)
766 {
767 if (active)
768 ADC_DMA_FIFO_REG(base) |= ADC_DMA_FIFO_DMA_RST_MASK;
769 else
770 ADC_DMA_FIFO_REG(base) &= ~ADC_DMA_FIFO_DMA_RST_MASK;
771 }
772
773 /*FUNCTION**********************************************************************
774 *
775 * Function Name : ADC_SetDmaCmd
776 * Description : Set the work mode of ADC DMA part.
777 *
778 *END**************************************************************************/
ADC_SetDmaCmd(ADC_Type * base,bool enable)779 void ADC_SetDmaCmd(ADC_Type* base, bool enable)
780 {
781 if (enable)
782 ADC_DMA_FIFO_REG(base) |= ADC_DMA_FIFO_DMA_EN_MASK;
783 else
784 ADC_DMA_FIFO_REG(base) &= ~ADC_DMA_FIFO_DMA_EN_MASK;
785 }
786
787 /*FUNCTION**********************************************************************
788 *
789 * Function Name : ADC_SetDmaFifoCmd
790 * Description : Set the work mode of ADC DMA FIFO part.
791 *
792 *END**************************************************************************/
ADC_SetDmaFifoCmd(ADC_Type * base,bool enable)793 void ADC_SetDmaFifoCmd(ADC_Type* base, bool enable)
794 {
795 if (enable)
796 ADC_DMA_FIFO_REG(base) |= ADC_DMA_FIFO_DMA_FIFO_EN_MASK;
797 else
798 ADC_DMA_FIFO_REG(base) &= ~ADC_DMA_FIFO_DMA_FIFO_EN_MASK;
799 }
800
801 /*******************************************************************************
802 * EOF
803 ******************************************************************************/
804
