1 /* 2 * Copyright 2021-2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ADC_SAR_IP_HEADERWRAPPER_S32XX_H 8 #define ADC_SAR_IP_HEADERWRAPPER_S32XX_H 9 10 /** 11 * @file 12 * 13 * @addtogroup adc_sar_ip Adc Sar IPL 14 * @{ 15 */ 16 17 #ifdef __cplusplus 18 extern "C"{ 19 #endif 20 21 /* Important Note: This file cannot be used independently. 22 * It depends on platform header files to be included before including it */ 23 24 /*================================================================================================== 25 * SOURCE FILE VERSION INFORMATION 26 ==================================================================================================*/ 27 #define ADC_SAR_IP_VENDOR_ID_HEADERWRAPPER_S32XX 43 28 #define ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_HEADERWRAPPER_S32XX 4 29 #define ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_HEADERWRAPPER_S32XX 7 30 #define ADC_SAR_IP_AR_RELEASE_REVISION_VERSION_HEADERWRAPPER_S32XX 0 31 #define ADC_SAR_IP_SW_MAJOR_VERSION_HEADERWRAPPER_S32XX 2 32 #define ADC_SAR_IP_SW_MINOR_VERSION_HEADERWRAPPER_S32XX 0 33 #define ADC_SAR_IP_SW_PATCH_VERSION_HEADERWRAPPER_S32XX 0 34 35 /*================================================================================================== 36 * DEFINITIONS 37 ==================================================================================================*/ 38 39 #define ADC_SAR_IP_NUM_GROUP_CHAN (2U) 40 #define ADC_SAR_IP_CDR_COUNT (39U) 41 #define ADC_SAR_IP_INSTANCE_COUNT ADC_INSTANCE_COUNT 42 #define ADC_SAR_IP_THRHLR_COUNT (8U) 43 #define ADC_SAR_IP_CWSELR_COUNT (2U) 44 45 #define ADC_SAR_IP_MAX_RESOLUTION (12U) 46 #define ADC_SAR_IP_HAS_THRHLR_ARRAY (0U) 47 #define ADC_SAR_IP_HAS_CWSELR_UNROLLED (1U) 48 #define ADC_SAR_IP_CALIBRATION_USES_MCR (1U) 49 50 #define ADC_SAR_IP_PRESAMPLE_DVDD_EVAL (0U) 51 #define ADC_SAR_IP_PRESAMPLE_AVDD_EVAL (1U) 52 #define ADC_SAR_IP_PRESAMPLE_VREFL_EVAL (2U) 53 #define ADC_SAR_IP_PRESAMPLE_VREFH_EVAL (3U) 54 55 #define ADC_SAR_IP_HAS_CWSELR0 (1U) 56 #define ADC_SAR_IP_HAS_CWSELR1 (0U) 57 #define ADC_SAR_IP_HAS_CWSELR2 (0U) 58 #define ADC_SAR_IP_HAS_CWSELR3 (0U) 59 #define ADC_SAR_IP_HAS_CWSELR4 (1U) 60 #define ADC_SAR_IP_HAS_CWSELR5 (0U) 61 #define ADC_SAR_IP_HAS_CWSELR6 (0U) 62 #define ADC_SAR_IP_HAS_CWSELR7 (0U) 63 #define ADC_SAR_IP_HAS_CWSELR8 (0U) 64 #define ADC_SAR_IP_HAS_CWSELR9 (0U) 65 #define ADC_SAR_IP_HAS_CWSELR10 (0U) 66 #define ADC_SAR_IP_HAS_CWSELR11 (0U) 67 #define ADC_SAR_IP_HAS_ADCLKSEL (1U) 68 69 #define ADC_SAR_IP_MSR_ADCSTATUS_POWER_DOWN (1U) 70 #define ADC_SAR_IP_MSR_ADCSTATUS_IDLE (0U) 71 72 #define ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE (1U) 73 #define ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL (1U) 74 #define ADC_SAR_IP_HAS_CTU_TRIGGER_MODE (1U) 75 #define ADC_SAR_IP_HAS_CTU (1U) 76 #define ADC_SAR_IP_HAS_CLKSEL_EXTENDED (0U) 77 #define ADC_SAR_IP_W1C_ABORT (0U) 78 #define ADC_SAR_IP_HAS_TEMPSENSE_CHN (0U) 79 #define ADC_SAR_IP_SELFTEST_FULL_CLK (1U) 80 81 #define ADC_SAR_IP_HAS_SELFTEST_STCR1 (1U) 82 #define ADC_SAR_IP_HAS_SELFTEST_STCR3 (1U) 83 #define ADC_SAR_IP_HAS_BANDGAP_STATUS (0U) 84 #define ADC_SAR_IP_HAS_SELFTEST_USE_CH32 (0U) 85 86 #define ADC_SAR_IP_ABORTCHAIN_WORKAROUND (1U) 87 88 #if (ADC_SAR_IP_INSTANCE_COUNT == 2U) 89 /* 31-28 3-0 63-60 35-32 95-92 67-64 90 \_/ \_/ \_/ \_/ \_/ \_/ 91 |......| |......| |......| */ 92 #define FEATURE_ADC_CHN_AVAIL_BITMAP {{0x000000FFU, 0x00000079U}, /* 0 */ \ 93 {0x000000FFU, 0x00000079U}, /* 1 */ \ 94 } 95 /* Adc Channels are divided into 2 Groups. */ 96 /* This array shows max number of channels of each group. */ 97 /* There are some registers that relate to this one: CEOCFR, CIMR, DMAR, PSR, NCMR, JCMR,... */ 98 /* Should be same with ADC_CDRx_COUNT in header file (from Base) */ 99 #define FEATURE_ADC_MAX_CHN_COUNT {{8U, 8U}, /* 0 */ \ 100 {8U, 8U}, /* 1 */ \ 101 } 102 /* Number of group channels of each unit*/ 103 /* Unit 0 / 1 */ 104 #define FEATURE_ADC_MAX_GROUP_COUNT { 2U, 2U } 105 /* Bit0: DSDR is available 106 Bit1: PSCR is available 107 Bit2: CTU is available 108 Bit3: CTU trigger mode is available */ 109 #define FEATURE_ADC_FEAT_AVAIL_BITMAP {0x0000000EU, /* 0 */ \ 110 0x0000000EU, /* 1 */ \ 111 } 112 #else 113 /* 31-28 3-0 63-60 35-32 95-92 67-64 114 \_/ \_/ \_/ \_/ \_/ \_/ 115 |......| |......| |......| */ 116 #define FEATURE_ADC_CHN_AVAIL_BITMAP {{0x000000FFU, 0x00000079U}, /* 0 */ \ 117 } 118 /* Adc Channels are divided into 2 Groups. */ 119 /* This array shows max number of channels of each group. */ 120 /* There are some registers that relate to this one: CEOCFR, CIMR, DMAR, PSR, NCMR, JCMR,... */ 121 /* Should be same with ADC_CDRx_COUNT in header file (from Base) */ 122 #define FEATURE_ADC_MAX_CHN_COUNT {{8U, 8U}, /* 0 */ \ 123 } 124 /* Number of group channels of each unit*/ 125 /* Unit 0 */ 126 #define FEATURE_ADC_MAX_GROUP_COUNT { 2U } 127 /* Bit0: DSDR is available 128 Bit1: PSCR is available 129 Bit2: CTU is available 130 Bit3: CTU trigger mode is available */ 131 #define FEATURE_ADC_FEAT_AVAIL_BITMAP {0x0000000EU, /* 0 */ \ 132 } 133 #endif /* (ADC_SAR_IP_INSTANCE_COUNT == 2U) */ 134 135 /* Register access defines */ 136 #define REG_ACCESS(reg, index) (*(volatile uint32*)(&(((&(reg))[(index)])))) 137 #define REG_READ(reg, index) (*(volatile const uint32*)(&(((&(reg))[(index)])))) 138 139 #define CEOCFR(base, regIndex) REG_ACCESS((base)->CEOCFR0, (regIndex)) 140 #define CIMR(base, regIndex) REG_ACCESS((base)->CIMR0, (regIndex)) 141 #define DMAR(base, regIndex) REG_ACCESS((base)->DMAR0, (regIndex)) 142 #define PSR(base, regIndex) REG_ACCESS((base)->PSR0, (regIndex)) 143 #define CTR(base, regIndex) REG_ACCESS((base)->CTR0, (regIndex)) 144 #define NCMR(base, regIndex) REG_ACCESS((base)->NCMR0, (regIndex)) 145 #define JCMR(base, regIndex) REG_ACCESS((base)->JCMR0, (regIndex)) 146 #define CWSELR(base, regIndex) REG_ACCESS((base)->CWSELR, (regIndex)) 147 #define CWENR(base, regIndex) REG_ACCESS((base)->CWENR0, (regIndex)) 148 #define AWORR(base, regIndex) REG_ACCESS((base)->AWORR0, (regIndex)) 149 #define CDR(base, chanIndex) REG_READ((base)->PCDR[0U], (chanIndex)) 150 151 /* MCR */ 152 #define ADC_MCR_ADCLKSEL_MASK ADC_MCR_ADCLKSE_MASK 153 #define ADC_MCR_ADCLKSEL(x) ADC_MCR_ADCLKSE(x) 154 155 /* CTR */ 156 #define ADC_CTR_INPSAMP(x) ADC_CTR0_INPSAMP(x) 157 158 /* NCMR */ 159 #define ADC_NCMR_CH0(x) ADC_NCMR0_CH0(x) 160 161 /* CDR */ 162 #define ADC_CDR_CDATA_MASK ADC_PCDR_CDATA_MASK 163 #define ADC_CDR_CDATA_SHIFT ADC_PCDR_CDATA_SHIFT 164 #define ADC_CDR_RESULT_MASK ADC_PCDR_RESULT_MASK 165 #define ADC_CDR_RESULT(x) ADC_PCDR_RESULT(x) 166 #define ADC_CDR_OVERW_MASK ADC_PCDR_OVERW_MASK 167 #define ADC_CDR_OVERW_SHIFT ADC_PCDR_OVERW_SHIFT 168 #define ADC_CDR_VALID_MASK ADC_PCDR_VALID_MASK 169 170 /* USROFSGN - Offset and Gain User */ 171 #define ADC_USER_OFFSET_GAIN_REG USROFSGN 172 #define ADC_USER_OFFSET(x) ADC_USROFSGN_OFFSUSER(x) 173 #define ADC_USER_GAIN(x) ADC_USROFSGN_GAINUSER(x) 174 175 #ifdef __cplusplus 176 } 177 #endif 178 179 /** @} */ 180 181 #endif /* ADC_SAR_IP_HEADERWRAPPER_S32XX_H */ 182
