1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal_adc.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32U5xx_HAL_ADC_H 21 #define STM32U5xx_HAL_ADC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32u5xx_hal_def.h" 29 30 /* Include low level driver */ 31 #include "stm32u5xx_ll_adc.h" 32 33 /** @addtogroup STM32U5xx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup ADC 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup ADC_Exported_Types ADC Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief ADC group regular oversampling structure definition 48 */ 49 typedef struct 50 { 51 uint32_t Ratio; /*!< Configures the oversampling ratio. 52 In case of ADC1 or ADC2 (if available), this parameter can be in the 53 range from 0 to 1023 54 In case of ADC4, this parameter can be a value of 55 @ref ADC_HAL_EC_OVS_RATIO */ 56 57 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 58 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 59 60 uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. 61 This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */ 62 63 uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode. 64 The oversampling is either temporary stopped or reset upon an injected 65 sequence interruption. 66 If oversampling is enabled on both regular and injected groups, 67 this parameter is discarded and forced to setting 68 "ADC_REGOVERSAMPLING_RESUMED_MODE" 69 (the oversampling buffer is zeroed during injection sequence). 70 This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG 71 Note: This parameter is not applicable for ADC4 */ 72 73 } ADC_OversamplingTypeDef; 74 75 /** 76 * @brief Structure definition of ADC instance and ADC group regular. 77 * @note Parameters of this structure are shared within 2 scopes: 78 * - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign, 79 * ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff. 80 * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, 81 * NbrOfDiscConversion, ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, 82 * OversamplingMode, Oversampling, ConversionDataManagement. 83 * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. 84 * ADC state can be either: 85 * - For all parameters: ADC disabled 86 * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': 87 * ADC enabled without conversion on going on group regular. 88 * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going 89 * on groups regular and injected. 90 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 91 * without error reporting (as it can be the expected behavior in case of intended action to update another 92 * parameter (which fulfills the ADC state condition) on the fly). 93 */ 94 typedef struct 95 { 96 uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous 97 clock derived from system clock or PLL (Refer to reference manual for list of 98 clocks available)) and clock prescaler. 99 This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. 100 Note: The ADC clock configuration is common to all ADC instances. 101 Note: In case of usage of channels on injected group, ADC frequency should be 102 lower than AHB clock frequency /4 for resolution 12 or 10 bits, AHB clock 103 frequency /3 for resolution 8 bits, AHB clock frequency /2 for 104 resolution 6 bits. 105 Note: In case of synchronous clock mode based on HCLK/1, the configuration must 106 be enabled only if the system clock has a 50% duty clock cycle 107 (APB prescaler configured inside RCC must be bypassed and PCLK clock must 108 have 50% duty cycle). 109 Refer to reference manual for details. 110 Note: In case of usage of asynchronous clock, the selected clock must be 111 preliminarily enabled at RCC top level. 112 Note: This parameter can be modified only if all ADC instances are disabled. */ 113 114 uint32_t Resolution; /*!< Configure the ADC resolution. 115 This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ 116 117 uint32_t GainCompensation; /*!< Specify the ADC gain compensation coefficient to be applied to ADC raw 118 conversion data, based on following formula: 119 DATA = DATA(raw) * (gain compensation coef) / 4095 120 14 bit format, unsigned: 2 bits exponents / 14 bits mantissa 121 Gain step is 1/4095 = 0.000244 122 Gain range is 0.0000 to 3.999756 123 This parameter value can be 124 0 Gain compensation will be disabled and coefficient set to 0 125 1 -> 0x3FFF Gain compensation will be enabled and coefficient set to 126 specified value */ 127 128 uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected. 129 This parameter can be associated to parameter 'DiscontinuousConvMode' 130 to have main sequence subdivided in successive parts. 131 For ADC1 or ADC2 instances, this parameter could be enabled or disabled. 132 If disabled: Conversion is performed in single mode (one channel converted, 133 the one defined in rank 1). 134 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' 135 are discarded (equivalent to set to 1). 136 If enabled: Conversions are performed in sequence mode (multiple ranks defined 137 by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of 138 each channel in sequencer). 139 Scan direction is upward: from rank 1 to rank 'n'. 140 For ADC4 instance, this parameter could be "fully configurable" or 141 "not fully configurable": 142 - sequencer configured to fully configurable: 143 sequencer length and each rank affectation to a channel are configurable. 144 - Sequence length: Set number of ranks in the scan sequence. 145 - Sequence direction: Unless specified in parameters, sequencer 146 scan direction is forward (from rank 1 to rank n). 147 - sequencer configured to not fully configurable: 148 sequencer length and each rank affectation to a channel are fixed by 149 channel HW number. 150 - Sequence length: Number of ranks in the scan sequence is 151 defined by number of channels set in the sequence, 152 rank of each channel is fixed by channel HW number. 153 (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 154 - Sequence direction: Unless specified in parameters, sequencer 155 scan direction is forward (from lowest channel number to 156 highest channel number). 157 This parameter can be a value of @ref ADC_Scan_mode */ 158 159 uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). 160 Refer to reference manual for alignments formats versus resolutions. 161 This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */ 162 163 uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and 164 interruption: end of unitary conversion or end of sequence conversions. 165 This parameter can be a value of @ref ADC_EOCSelection. */ 166 167 FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when 168 the previous conversion (for ADC group regular) or previous sequence 169 (for ADC group injected) has been retrieved by user software, using function 170 HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue(). 171 This feature automatically adapts the frequency of ADC conversions triggers to 172 the speed of the system that reads the data. Moreover, this avoids risk 173 of overrun for low frequency applications. 174 This parameter can be set to ENABLE or DISABLE. 175 Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), 176 HAL_ADC_Start_DMA()) since these modes have to clear immediately 177 the EOC flag (by CPU to free the IRQ pending event or by DMA). 178 Auto wait will work but fort a very short time, discarding its intended 179 benefit (except specific case of high load of CPU or DMA transfers 180 which can justify usage of auto wait). 181 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 182 2. Later on, when ADC conversion data is needed: 183 use HAL_ADC_GetValue() to retrieve conversion result and trig another 184 conversion start. 185 (in case of usage of ADC group injected, use the equivalent functions 186 HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */ 187 188 uint32_t LowPowerAutoPowerOff; /*!< Select the auto-off low power mode: the ADC automatically powers-off after 189 a conversion and automatically wakes-up when a new conversion is triggered. 190 This feature can be combined with automatic wait mode ('LowPowerAutoWait'). 191 This parameter can be value of @ref ADC_HAL_LowPower_DPD. 192 Note: If activated, this feature also turns off the ADC dedicated 16 MHz 193 RC oscillator (HSI16). 194 Note: This parameter can be used for ADC4 only. */ 195 196 FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) 197 or continuous mode for ADC group regular, after the first ADC conversion start 198 trigger occurred (software start or external trigger). 199 This parameter can be set to ENABLE or DISABLE. */ 200 201 uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group 202 sequencer. 203 This parameter is dependent on ADC instance. 204 If ADC1 or ADC2 instances: 205 To use the regular group sequencer and convert several ranks, 206 parameter 'ScanConvMode' must be enabled. 207 This parameter must be a number between Min_Data = 1 and Max_Data = 16. 208 If ADC4 instance: 209 This parameter is dependent on ScanConvMode: 210 - sequencer configured to fully configurable: 211 Number of ranks in the scan sequence is configurable using this parameter. 212 Note: After the first call of 'HAL_ADC_Init()', each rank corresponding 213 to parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'. 214 Afterwards, when all needed sequencer ranks are set, parameter 215 'NbrOfConversion' can be updated without modifying configuration of 216 sequencer ranks (sequencer ranks above 'NbrOfConversion' are discarded). 217 - sequencer configured to not fully configurable: 218 Number of ranks in the scan sequence is defined by number of channels set in 219 the sequence. This parameter is discarded. 220 This parameter must be a number between Min_Data = 1 and Max_Data = 8. 221 Note: This parameter must be modified when no conversion is on going on 222 regular group (ADC disabled, or ADC enabled without continuous mode 223 or external trigger that could launch a conversion). */ 224 225 FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is 226 performed in Complete-sequence/Discontinuous-sequence 227 (main sequence subdivided in successive parts). 228 Discontinuous mode is used only if sequencer is enabled 229 (parameter 'ScanConvMode'). If sequencer is disabled, this parameter 230 is discarded. 231 Discontinuous mode can be enabled only if continuous mode is disabled. 232 If continuous mode is enabled, this parameter setting is discarded. 233 This parameter can be set to ENABLE or DISABLE. */ 234 235 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence 236 of ADC group regular (parameter NbrOfConversion) will be subdivided. 237 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. 238 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ 239 240 uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular 241 conversion start. 242 If set to ADC_SOFTWARE_START, external triggers are disabled and software 243 trigger is used instead. 244 This parameter can be a value of @ref ADC_regular_external_trigger_source. 245 Caution: external trigger source is common to all ADC instances. */ 246 247 uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular 248 conversion start. 249 If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. 250 This parameter can be a value of @ref ADC_regular_external_trigger_edge */ 251 252 uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA 253 (oneshot or circular), or stored in the DR register or 254 transferred to MDF register. 255 Note: In continuous mode, DMA must be configured in circular mode. 256 Otherwise an overrun will be triggered when DMA buffer maximum pointer 257 is reached. 258 This parameter can be a value of @ref ADC_ConversionDataManagement. 259 Note: This parameter must be modified when no conversion is on going on both 260 regular and injected groups (ADC disabled, or ADC enabled without 261 continuous mode or external trigger that could launch a conversion). */ 262 263 FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode 264 (DMA transfer stops when number of conversions is reached) or in 265 continuous mode (DMA transfer unlimited, whatever number of conversions). 266 This parameter can be set to ENABLE or DISABLE. 267 Note: In continuous mode, DMA must be configured in circular mode. 268 Otherwise an overrun will be triggered when DMA buffer maximum 269 pointer is reached. */ 270 271 uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). 272 This parameter applies to ADC group regular only. 273 This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. 274 Note: In case of overrun set to data preserved and usage with programming model 275 with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of 276 conversion flags, this induces the release of the preserved data. 277 If needed, this data can be saved in function HAL_ADC_ConvCpltCallback(), 278 placed in user program code (called before end of conversion flags clear). 279 Note: Error reporting with respect to the conversion mode: 280 - Usage with ADC conversion by polling for event or interruption: 281 Error is reported only if overrun is set to data preserved. 282 If overrun is set to data overwritten, user can willingly not read 283 all the converted data, this is not considered as an erroneous case. 284 - Usage with ADC conversion by DMA: Error is reported whatever overrun 285 setting (DMA is expected to process all data from data register). */ 286 287 uint32_t SamplingTimeCommon1; /*!< Set sampling time common to a group of channels. 288 Unit: ADC clock cycles. 289 This parameter is applied for ADC4. 290 Conversion time is the addition of sampling time and processing time 291 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 292 8.5 cycles at 8 bits). 293 Note: On this STM32 family, two different sampling time settings are available, 294 each channel can use one of these two settings. 295 On some other STM32 devices, this parameter in channel wise and 296 is located into ADC channel initialization structure. 297 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME 298 Note: In case of usage of internal measurement channels 299 (VrefInt/Vbat/TempSensor), sampling time constraints must be respected 300 (sampling time can be adjusted in function of ADC clock frequency and 301 sampling time setting). 302 Refer to device datasheet for timings values, parameters TS_vrefint, 303 TS_vbat, TS_temp (values rough order: few tens of microseconds). */ 304 305 uint32_t SamplingTimeCommon2; /*!< Set sampling time common to a group of channels, second common setting possible. 306 Unit: ADC clock cycles 307 This parameter is applied for ADC4. 308 Conversion time is the addition of sampling time and processing time (12.5 ADC 309 clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 310 8.5 cycles at 8 bits). 311 Note: On this STM32 family, two different sampling time settings are available, 312 each channel can use one of these two settings. 313 On some other STM32 devices, this parameter in channel wise and is located 314 into ADC channel initialization structure. 315 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME 316 Note: In case of usage of internal measurement channels 317 (VrefInt/Vbat/TempSensor), sampling time constraints must be respected 318 (sampling time can be adjusted in function of ADC clock frequency and 319 sampling time setting) 320 Refer to device datasheet for timings values, parameters TS_vrefint, 321 TS_vbat, TS_temp (values rough order: few tens of microseconds). */ 322 323 uint32_t LeftBitShift; /*!< Configures the left shifting applied to the final result with or without 324 oversampling. 325 This parameter can be a value of @ref ADCEx_Left_Bit_Shift */ 326 327 FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. 328 This parameter can be set to ENABLE or DISABLE. 329 Note: This parameter can be modified only if there is no conversion 330 is ongoing on ADC groups regular and injected */ 331 332 ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. 333 Caution: this setting overwrites the previous oversampling configuration 334 if oversampling is already enabled. */ 335 336 uint32_t TriggerFrequencyMode; /*!< Set ADC trigger frequency mode. 337 This parameter can be a value of @ref ADC_HAL_EC_REG_TRIGGER_FREQ. 338 Note: ADC trigger frequency mode must be set to low frequency when 339 a duration is exceeded before ADC conversion start trigger event 340 (between ADC enable and ADC conversion start trigger event 341 or between two ADC conversion start trigger event). 342 Duration value: Refer to device datasheet, parameter "tIdle". 343 Note: When ADC trigger frequency mode is set to low frequency, 344 some rearm cycles are inserted before performing ADC conversion 345 start, inducing a delay of 2 ADC clock cycles. */ 346 347 uint32_t VrefProtection; /*!< Select the Vref protection mode: specify VREF+ protection mode 348 when multiple ADCs are working simultaneously. 349 This parameter can be value of @ref ADC_HAL_VrefProt. 350 Note: This parameter can be used for ADC4 only. */ 351 352 } ADC_InitTypeDef; 353 354 /** 355 * @brief Structure definition of ADC channel for regular group 356 * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. 357 * ADC state can be either: 358 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff') 359 * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on 360 * going on regular group. 361 * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going 362 * on regular and injected groups. 363 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 364 * without error reporting (as it can be the expected behavior in case of intended action to update another 365 * parameter (which fulfills the ADC state condition) on the fly. 366 */ 367 typedef struct 368 { 369 uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. 370 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 371 Note: Depending on devices and ADC instances, some channels may not be 372 available on device package pins. Refer to device datasheet for 373 channels availability. */ 374 375 uint32_t Rank; /*!< Specify the rank in the regular group sequencer. 376 This parameter is depending on ADC instances. 377 If ADC1 or ADC2 instances, this parameter specify the rank in the sequencer. 378 Note: to disable a channel or change order of conversion sequencer, 379 rank containing a previous channel setting can be overwritten by 380 the new channel setting (or parameter number of conversions adjusted) 381 If ADC4 instance, this parameter allows to add or remove the channel from 382 the ADC regular group sequencer and specify its conversion rank. 383 This parameter is depending on ScanConvMode: 384 - sequencer configured to fully configurable: 385 Channels ordering into each rank of scan sequence: 386 whatever channel can be placed into whatever rank. 387 - sequencer configured to not fully configurable: 388 rank of each channel is fixed by channel HW number. 389 (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 390 Despite the channel rank is fixed, this parameter allow an additional 391 possibility: to remove the selected rank (selected channel) from sequencer. 392 This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS */ 393 394 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 395 Unit: ADC clock cycles 396 Conversion time is the addition of sampling time and processing time 397 (14.5 ADC clock cycles at ADC resolution 14 bits, 12.5 cycles at 12 bits, 398 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 399 For ADC1 and 2 (if available): This parameter can be a value of 400 @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME. 401 Caution: This parameter applies to a channel that can be used into regular 402 and/or injected group. It overwrites the last setting. 403 For ADC4: This parameter can be a value of @ref ADC_HAL_EC_SAMPLINGTIME_COMMON. 404 Note: On this STM32 family, two different sampling time settings are available 405 (refer to parameters "SamplingTimeCommon1" and "SamplingTimeCommon2"), 406 each channel can use one of these two settings. 407 Note: In case of usage of internal measurement channels 408 (VrefInt/Vbat/TempSensor), sampling time constraints must be respected 409 (sampling time can be adjusted in function of ADC clock frequency 410 and sampling time setting) 411 Refer to device datasheet for timings values. */ 412 413 uint32_t SingleDiff; /*!< Select single-ended or differential input. 414 In differential mode: Differential measurement is carried out between 415 the selected channel 'i' (positive input) and channel 416 'i+1' (negative input). 417 Only channel 'i' has to be configured, channel 'i+1' is 418 configured automatically. 419 This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING 420 Caution: This parameter applies to a channel that can be used in a regular 421 and/or injected group. It overwrites the last setting. 422 Note: Refer to Reference Manual to ensure the selected channel is available 423 in differential mode. 424 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' 425 is not usable separately. 426 Note: This parameter must be modified when ADC is disabled (before ADC start 427 conversion or after ADC stop conversion). 428 If ADC is enabled, this parameter setting is bypassed without error 429 reporting (as it can be the expected behavior in case of another 430 parameter update on the fly) */ 431 432 uint32_t OffsetNumber; /*!< Select the offset number 433 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB 434 Caution: Only one offset is allowed per channel. This parameter overwrites the 435 last setting. */ 436 437 uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data. 438 Offset value must be a positive number. 439 Depending of ADC resolution selected (14, 12, 10, 8 or 6 bits), this parameter 440 must be a number between Min_Data = 0x000 and Max_Data = 0x3FFF, 441 0xFFF, 0x3FF, 0xFF or 0x3F respectively. 442 Note: This parameter must be modified when no conversion is on going on without 443 both regular and injected groups (ADC disabled, or ADC enabled 444 continuous mode or external trigger that could launch a conversion). */ 445 446 FunctionalState OffsetRightShift; /*!< Define the Right-shift data after Offset correction. 447 This parameter is applied only for 14-bit or 8-bit resolution. 448 This parameter can be set to ENABLE or DISABLE.*/ 449 450 FunctionalState OffsetSignedSaturation; /*!< Specify whether the Signed saturation feature is used or not. 451 This parameter is only applied when OffsetSaturation is ENABLE. 452 This parameter is applied only for 14-bit or 8-bit resolution. 453 This parameter can be set to ENABLE or DISABLE. 454 Note: 455 - If OffsetSignedSaturation is set to DISABLE the unsigned 456 saturation feature is used */ 457 458 FunctionalState OffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow. 459 This parameter value can be ENABLE or DISABLE. 460 Note: 461 - This parameter must be modified when no conversion is on going on 462 both regular and injected groups (ADC disabled, or ADC enabled without 463 continuous mode or external trigger that could launch a conversion). 464 - Applicable for ADC1 */ 465 466 uint32_t OffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added 467 (positive sign) from or to the raw converted data. 468 This parameter can be a value of @ref ADCEx_OffsetSign. 469 Note: 470 - This parameter must be modified when no conversion is on going on 471 both regular and injected groups (ADC disabled, or ADC enabled without 472 continuous mode or external trigger that could launch a conversion). 473 - Applicable for ADC1 */ 474 475 476 } ADC_ChannelConfTypeDef; 477 478 /** 479 * @brief Structure definition of ADC analog watchdog 480 * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. 481 * ADC state can be either: 482 * - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC groups regular 483 * and injected. 484 */ 485 typedef struct 486 { 487 uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. 488 For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of 489 channels by setting parameter 'WatchdogMode'). 490 For Analog Watchdog 2 and 3: Several channels can be monitored 491 (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel) 492 This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ 493 494 uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. 495 For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or 496 all channels, ADC groups regular and-or injected. 497 For Analog Watchdog 2 and 3: Several channels can be monitored by applying 498 successively the AWD init structure. 499 For ADC1/ADC2, channels on ADC group regular and injected are not differentiated: 500 Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 501 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, value 502 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel. 503 This parameter can be a value of @ref ADC_analog_watchdog_mode. */ 504 505 uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. 506 For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' 507 is configured on single channel (only 1 channel can be monitored). 508 For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, 509 call successively the function HAL_ADC_AnalogWDGConfig() for each channel to 510 be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE'). 511 Note: 'ORING' channels is not supported. For Analog watchdog 2 and 3 and for 512 multiple channels monitoring it's mandatory to recall successively the 513 function HAL_ADC_AnalogWDGConfig() to add monitored channel for each call. 514 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ 515 516 FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. 517 This parameter can be set to ENABLE or DISABLE */ 518 519 uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. 520 Depending of ADC resolution selected (14, 12, 10, 8 or 6 bits), this parameter must 521 be a number between Min_Data = 0x000 and Max_Data = 0x3FFF, 0xFFF, 0x3FF, 522 0xFF or 0x3F respectively. 523 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: 524 - if ADC resolution is 12 bits the 4 LSB are ignored, 525 - if ADC resolution is 10 bits the 2 LSB are ignored. 526 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are impacted: 527 the comparison of analog watchdog thresholds is done on oversampling 528 intermediate computation (after ratio, before shift application): 529 intermediate register bitfield [32:7] (26 most significant bits). */ 530 531 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. 532 Depending of ADC resolution selected (14, 12, 10, 8 or 6 bits), this parameter 533 must be a number between Min_Data = 0x000 and Max_Data = 0x3FFF, 0xFFF, 0x3FF, 534 0xFF or 0x3F respectively. 535 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: 536 - if ADC resolution is 12 bits the 4 LSB are ignored, 537 - if ADC resolution is 10 bits the 2 LSB are ignored. 538 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 539 impacted: the comparison of analog watchdog thresholds is done on oversampling 540 intermediate computation (after ratio, before shift application): 541 intermediate register bitfield [32:7] (26 most significant bits). */ 542 543 uint32_t FilteringConfig; /*!< Specify whether filtering should be use and the number of samples to consider. 544 Before setting flag or raising interrupt, analog watchdog can wait to have several 545 consecutive out-of-window samples. This parameter allows to configure this number. 546 This parameter only applies to Analog watchdog 1. 547 For others, use value ADC_AWD_FILTERING_NONE. 548 Note: This parameter is applicable for ADC1/ADC2 on this device. 549 This parameter can be a value of @ref ADC_analog_watchdog_filtering_config. */ 550 551 } ADC_AnalogWDGConfTypeDef; 552 553 /** 554 * @brief ADC group injected contexts queue configuration 555 * @note Structure intended to be used only through structure "ADC_HandleTypeDef" 556 */ 557 typedef struct 558 { 559 uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each 560 HAL_ADCEx_InjectedConfigChannel() call to finally initialize 561 JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */ 562 563 uint32_t ChannelCount; /*!< Number of channels in the injected sequence */ 564 } ADC_InjectionConfigTypeDef; 565 566 /** @defgroup ADC_States ADC States 567 * @{ 568 */ 569 570 /** 571 * @brief HAL ADC state machine: ADC states definition (bitfields) 572 * @note ADC state machine is managed by bitfields, state must be compared 573 * with bit by bit. 574 * For example: 575 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " 576 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " 577 */ 578 /* States of ADC global scope */ 579 #define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ 580 #define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ 581 #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, 582 calibration) */ 583 #define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ 584 585 /* States of ADC errors */ 586 #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */ 587 #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */ 588 #define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */ 589 590 /* States of ADC group regular */ 591 #define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur 592 (either by continuous mode, external trigger, 593 low power auto power-on (if feature available), 594 multimode ADC master control (if feature available)) */ 595 #define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ 596 #define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ 597 #define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: 598 End Of Sampling flag raised */ 599 600 /* States of ADC group injected */ 601 #define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur 602 (either by auto-injection mode, external trigger, 603 low power auto power-on (if feature available), 604 multimode ADC master control (if feature available)) */ 605 #define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */ 606 607 /* States of ADC analog watchdogs */ 608 #define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ 609 #define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */ 610 #define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ 611 612 /* States of ADC multi-mode */ 613 #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another 614 ADC master (when feature available) */ 615 616 /** 617 * @} 618 */ 619 620 /** 621 * @brief ADC handle Structure definition 622 */ 623 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 624 typedef struct __ADC_HandleTypeDef 625 #else 626 typedef struct 627 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 628 { 629 ADC_TypeDef *Instance; /*!< Register base address */ 630 ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ 631 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 632 HAL_LockTypeDef Lock; /*!< ADC locking object */ 633 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ 634 __IO uint32_t ErrorCode; /*!< ADC Error code */ 635 ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */ 636 uint32_t ADCGroupRegularSequencerRanks; /*!< ADC group regular sequencer memorization 637 of ranks setting, used in mode "fully configurable" 638 (refer to parameter 'ScanConvMode') */ 639 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 640 void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ 641 void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ 642 void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ 643 void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ 644 void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ 645 void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue overflow callback */ 646 void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ 647 void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ 648 void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ 649 void (* CalibrationCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of calibration callback */ 650 void (* VoltageRegulatorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC voltage regulator (LDO) Ready callback */ 651 void (* ADCReadyCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Ready callback */ 652 void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ 653 void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ 654 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 655 } ADC_HandleTypeDef; 656 657 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 658 /** 659 * @brief HAL ADC Callback ID enumeration definition 660 */ 661 typedef enum 662 { 663 HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ 664 HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ 665 HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ 666 HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ 667 HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ 668 HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, /*!< ADC group injected context queue overflow callback ID */ 669 HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */ 670 HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */ 671 HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */ 672 HAL_ADC_END_OF_CALIBRATION_CB_ID = 0x09U, /*!< ADC end of calibration callback ID */ 673 HAL_ADC_VOLTAGE_REGULATOR_CB_ID = 0x0AU, /*!< ADC voltage regulator (LDO) Ready callback ID */ 674 HAL_ADC_ADC_READY_CB_ID = 0x0BU, /*!< ADC Ready callback ID */ 675 HAL_ADC_MSPINIT_CB_ID = 0x0CU, /*!< ADC Msp Init callback ID */ 676 HAL_ADC_MSPDEINIT_CB_ID = 0x0DU /*!< ADC Msp DeInit callback ID */ 677 } HAL_ADC_CallbackIDTypeDef; 678 679 /** 680 * @brief HAL ADC Callback pointer definition 681 */ 682 typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ 683 684 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 685 686 /** 687 * @} 688 */ 689 690 691 /* Exported constants --------------------------------------------------------*/ 692 693 /** @defgroup ADC_Exported_Constants ADC Exported Constants 694 * @{ 695 */ 696 697 /** @defgroup ADC_Error_Code ADC Error Code 698 * @{ 699 */ 700 #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ 701 #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking, 702 enable/disable, erroneous state, ...) */ 703 #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ 704 #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ 705 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 706 #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ 707 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 708 /** 709 * @} 710 */ 711 712 /** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source 713 * @{ 714 */ 715 #define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */ 716 #define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */ 717 #define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */ 718 #define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */ 719 #define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */ 720 #define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */ 721 #define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */ 722 #define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */ 723 #define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */ 724 #define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */ 725 #define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */ 726 #define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */ 727 /** 728 * @} 729 */ 730 731 /** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution 732 * @{ 733 */ 734 #define ADC_RESOLUTION_14B (LL_ADC_RESOLUTION_14B) /*!< ADC resolution 14 bits (ADC1, ADC2 only) */ 735 #define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */ 736 #define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */ 737 #define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */ 738 #define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits (ADC4 only) */ 739 740 /* Legacy literals */ 741 #define ADC4_RESOLUTION_12B ADC_RESOLUTION_12B 742 #define ADC4_RESOLUTION_10B ADC_RESOLUTION_10B 743 #define ADC4_RESOLUTION_8B ADC_RESOLUTION_8B 744 #define ADC4_RESOLUTION_6B ADC_RESOLUTION_6B 745 /** 746 * @} 747 */ 748 749 /** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment 750 * @{ 751 */ 752 #define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ 753 #define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ 754 /** 755 * @} 756 */ 757 758 /** @defgroup ADC_Scan_mode ADC sequencer scan mode 759 * @{ 760 */ 761 #define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */ 762 #define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */ 763 764 /** @defgroup ADC_Private_Constants ADC Private Constants 765 * @{ 766 */ 767 768 /* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */ 769 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC) 770 771 #define ADC4_SCAN_SEQ_FIXED_INT (0x80000000U) /* Internal definition to differentiate sequencer setting 772 fixed or configurable */ 773 774 #define ADC4_SCAN_DISABLE (0x00000000UL) /*!< Sequencer set to fully configurable: only the rank 1 is enabled (no scan sequence on several ranks) */ 775 #define ADC4_SCAN_ENABLE (ADC4_CFGR1_CHSELRMOD) /*!< Sequencer set to fully configurable: sequencer length and each rank affectation to a channel are configurable. */ 776 777 778 #define ADC_SCAN_SEQ_FIXED (ADC4_SCAN_SEQ_FIXED_INT) /*!< Sequencer set to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). Scan direction forward: from channel 0 to channel 18 */ 779 #define ADC_SCAN_SEQ_FIXED_BACKWARD (ADC4_SCAN_SEQ_FIXED_INT | ADC4_CFGR1_SCANDIR) /*!< Sequencer set to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). Scan direction backward: from channel 18 to channel 0 */ 780 781 #define ADC_SCAN_DIRECTION_FORWARD (ADC_SCAN_SEQ_FIXED) /* For compatibility with other STM32 devices */ 782 #define ADC_SCAN_DIRECTION_BACKWARD (ADC_SCAN_SEQ_FIXED_BACKWARD) /* For compatibility with other STM32 devices */ 783 784 /** 785 * @} 786 */ 787 788 /* Combination of all CHSELR bits: SQ2...SQ8 */ 789 #define ADC_CHSELR_SQ2_TO_SQ8 (ADC_CHSELR_SQ2 | ADC_CHSELR_SQ3 | ADC_CHSELR_SQ4 | ADC_CHSELR_SQ5\ 790 | ADC_CHSELR_SQ6 | ADC_CHSELR_SQ7 | ADC_CHSELR_SQ8) 791 /** 792 * @} 793 */ 794 795 /** @defgroup ADC_HAL_LowPower_DPD ADC low power and deep power down selection 796 * @{ 797 */ 798 #define ADC_LOW_POWER_NONE (0x00000000UL) /*!< Both Low Power Auto Off and Deep Power Down is disabled */ 799 #define ADC_LOW_POWER_AUTOFF (ADC4_PWRR_AUTOFF) /*!< Low Power Auto Off enabled and Deep Power Down is disabled */ 800 #define ADC_LOW_POWER_DPD (ADC4_PWRR_DPD) /*!< Low Power Auto Off disabled and Deep Power Down is enabled */ 801 #define ADC_LOW_POWER_AUTOFF_DPD (ADC4_PWRR_AUTOFF | ADC4_PWRR_DPD) /*!< Low Power Auto Off and Deep Power Down are enabled */ 802 /** 803 * @} 804 */ 805 806 /** @defgroup ADC_HAL_VrefProt ADC VREF+ protection mode selection 807 * @{ 808 */ 809 #define ADC_VREF_PPROT_NONE (0x00000000UL) /*!< No VREF protection is applied*/ 810 #define ADC_VREF_PPROT_VREFPROT (ADC4_PWRR_VREFPROT) /*!< VREF+ protection when multiple ADCs are working simultaneously and a clock divider is used.*/ 811 #define ADC_VREF_PPROT_VREFSECSMP (ADC4_PWRR_VREFSECSMP) /*!< VREF+ protection when multiple ADCs are working simultaneously and a clock divider of 1 is used.*/ 812 #define ADC_VREF_PPROT_VREF_VREFSECSMP (ADC4_PWRR_VREFPROT | ADC4_PWRR_VREFSECSMP) /*!< Both VREF+ protection when multiple ADCs are working simultaneously and VREF+ second sample protection.*/ 813 /** 814 * @} 815 */ 816 817 /** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source 818 * @{ 819 */ 820 /* ADC group regular trigger sources for all ADC instances */ 821 #define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */ 822 #define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 823 #define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 824 #define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 825 #define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 826 #define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */ 827 #define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 828 #define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11 event. Trigger edge set to rising edge (default setting). */ 829 #define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */ 830 #define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */ 831 #define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */ 832 #define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */ 833 #define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */ 834 #define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */ 835 #define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */ 836 #define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */ 837 #define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 838 #define ADC_EXTERNALTRIG_EXT_IT15 (LL_ADC_REG_TRIG_EXT_EXTI_LINE15) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 15 event. Trigger edge set to rising edge (default setting). */ 839 #define ADC_EXTERNALTRIG_LPTIM1_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 channel 1 event. Trigger edge set to rising edge (default setting). */ 840 #define ADC_EXTERNALTRIG_LPTIM2_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM2_CH1) /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 channel 1 event. Trigger edge set to rising edge (default setting). */ 841 #define ADC_EXTERNALTRIG_LPTIM3_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM3_CH1) /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 channel 1 event. Trigger edge set to rising edge (default setting). */ 842 #define ADC_EXTERNALTRIG_LPTIM4_OUT (LL_ADC_REG_TRIG_EXT_LPTIM4_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM4 OUT event. Trigger edge set to rising edge (default setting). */ 843 844 #define ADC4_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4_ADC4) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 845 #define ADC4_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2_ADC4) 846 #if defined(TIM2) 847 #define ADC4_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC4) 848 #endif /* TIM2 */ 849 #if defined(TIM15) 850 #define ADC4_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO_ADC4) 851 #endif /* TIM5 */ 852 #if defined(TIM6) 853 #define ADC4_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC4) 854 #endif /* TIM6 */ 855 856 #if defined(LPTIM1) 857 #define ADC4_EXTERNALTRIG_LPTIM1_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM1_CH1_ADC4) 858 #endif /* LPTIM1 */ 859 860 #if defined(LPTIM3) 861 #define ADC4_EXTERNALTRIG_LPTIM3_CH2 (LL_ADC_REG_TRIG_EXT_LPTIM3_CH2_ADC4) 862 #endif /* LPTIM3 */ 863 #define ADC4_EXTERNALTRIG_EXT_IT15 (LL_ADC_REG_TRIG_EXT_EXTI_LINE15_ADC4) 864 865 /** 866 * @} 867 */ 868 869 /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) 870 * @{ 871 */ 872 #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware trigger detection disabled */ 873 #define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion trigger polarity set to rising edge */ 874 #define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion trigger polarity set to falling edge */ 875 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ 876 /** 877 * @} 878 */ 879 880 /** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions 881 * @{ 882 */ 883 #define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */ 884 #define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */ 885 /** 886 * @} 887 */ 888 889 /** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data 890 * @{ 891 */ 892 #define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */ 893 #define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */ 894 /** 895 * @} 896 */ 897 898 /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks 899 * @{ 900 */ 901 #define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ 902 #define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ 903 #define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ 904 #define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ 905 #define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ 906 #define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ 907 #define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ 908 #define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ 909 #define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */ 910 #define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */ 911 #define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */ 912 #define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */ 913 #define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */ 914 #define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */ 915 #define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */ 916 #define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */ 917 /** 918 * @} 919 */ 920 921 /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks 922 * @{ 923 */ 924 #define ADC4_RANK_CHANNEL_NUMBER (0x00000001U) /*!< Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */ 925 #define ADC4_RANK_NONE (0x00000002U) /*!< Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Disable the selected rank (selected channel) from sequencer */ 926 927 #define ADC4_REGULAR_RANK_1 (LL_ADC_REG_RANK_1_ADC4) /*!< ADC group regular sequencer rank 1 */ 928 #define ADC4_REGULAR_RANK_2 (LL_ADC_REG_RANK_2_ADC4) /*!< ADC group regular sequencer rank 2 */ 929 #define ADC4_REGULAR_RANK_3 (LL_ADC_REG_RANK_3_ADC4) /*!< ADC group regular sequencer rank 3 */ 930 #define ADC4_REGULAR_RANK_4 (LL_ADC_REG_RANK_4_ADC4) /*!< ADC group regular sequencer rank 4 */ 931 #define ADC4_REGULAR_RANK_5 (LL_ADC_REG_RANK_5_ADC4) /*!< ADC group regular sequencer rank 5 */ 932 #define ADC4_REGULAR_RANK_6 (LL_ADC_REG_RANK_6_ADC4) /*!< ADC group regular sequencer rank 6 */ 933 #define ADC4_REGULAR_RANK_7 (LL_ADC_REG_RANK_7_ADC4) /*!< ADC group regular sequencer rank 7 */ 934 #define ADC4_REGULAR_RANK_8 (LL_ADC_REG_RANK_8_ADC4) /*!< ADC group regular sequencer rank 8 */ 935 936 /** 937 * @} 938 */ 939 /** @defgroup ADC_HAL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels 940 * @{ 941 */ 942 #define ADC4_SAMPLINGTIME_COMMON_1 (LL_ADC_SAMPLINGTIME_COMMON_1) /*!< Set sampling time common to a group of channels: sampling time nb 1 */ 943 #define ADC4_SAMPLINGTIME_COMMON_2 (LL_ADC_SAMPLINGTIME_COMMON_2) /*!< Set sampling time common to a group of channels: sampling time nb 2 */ 944 /** 945 * @} 946 */ 947 948 /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time 949 * @{ 950 */ 951 #define ADC_SAMPLETIME_5CYCLES (LL_ADC_SAMPLINGTIME_5CYCLES) /*!< Sampling time 5 ADC clock cycles */ 952 #define ADC_SAMPLETIME_6CYCLES (LL_ADC_SAMPLINGTIME_6CYCLES) /*!< Sampling time 6 ADC clock cycles */ 953 #define ADC_SAMPLETIME_12CYCLES (LL_ADC_SAMPLINGTIME_12CYCLES) /*!< Sampling time 12 ADC clock cycles */ 954 #define ADC_SAMPLETIME_20CYCLES (LL_ADC_SAMPLINGTIME_20CYCLES) /*!< Sampling time 20 ADC clock cycles */ 955 #define ADC_SAMPLETIME_36CYCLES (LL_ADC_SAMPLINGTIME_36CYCLES) /*!< Sampling time 36 ADC clock cycles */ 956 #define ADC_SAMPLETIME_68CYCLES (LL_ADC_SAMPLINGTIME_68CYCLES) /*!< Sampling time 68 ADC clock cycles */ 957 #define ADC_SAMPLETIME_391CYCLES (LL_ADC_SAMPLINGTIME_391CYCLES) /*!< Sampling time 391 ADC clock cycles */ 958 #define ADC_SAMPLETIME_814CYCLES (LL_ADC_SAMPLINGTIME_814CYCLES) /*!< Sampling time 814 ADC clock cycles */ 959 /** 960 * @} 961 */ 962 963 /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time 964 * @{ 965 */ 966 #define ADC4_SAMPLETIME_1CYCLE_5 (LL_ADC4_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycle */ 967 #define ADC4_SAMPLETIME_3CYCLES_5 (LL_ADC4_SAMPLINGTIME_3CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles */ 968 #define ADC4_SAMPLETIME_7CYCLES_5 (LL_ADC4_SAMPLINGTIME_7CYCLES_5) /*!< Sampling time 7.5 ADC clock cycles */ 969 #define ADC4_SAMPLETIME_12CYCLES_5 (LL_ADC4_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ 970 #define ADC4_SAMPLETIME_19CYCLES_5 (LL_ADC4_SAMPLINGTIME_19CYCLES_5) /*!< Sampling time 19.5 ADC clock cycles */ 971 #define ADC4_SAMPLETIME_39CYCLES_5 (LL_ADC4_SAMPLINGTIME_39CYCLES_5) /*!< Sampling time 39.5 ADC clock cycles */ 972 #define ADC4_SAMPLETIME_79CYCLES_5 (LL_ADC4_SAMPLINGTIME_79CYCLES_5) /*!< Sampling time 79.5 ADC clock cycles */ 973 #define ADC4_SAMPLETIME_814CYCLES_5 (LL_ADC4_SAMPLINGTIME_814CYCLES_5) /*!< Sampling time 814.5 ADC clock cycles */ 974 /** 975 * @} 976 */ 977 978 /** @defgroup ADCEx_Calibration_Mode ADC Extended Calibration mode offset mode or linear mode 979 * @{ 980 */ 981 #define ADC_CALIB_OFFSET (LL_ADC_CALIB_OFFSET) 982 #define ADC_CALIB_OFFSET_LINEARITY (LL_ADC_CALIB_OFFSET_LINEARITY) 983 /** 984 * @} 985 */ 986 987 /** @defgroup ADCEx_Calibration_Linearity_Index ADC indexes for linear calibration 988 * @{ 989 */ 990 #define ADC_CALIB_OFFSET_INDEX LL_ADC_CALIB_OFFSET_INDEX /*!< Offset Calibration Index */ 991 #define ADC_CALIB_LINEARITY_INDEX1 LL_ADC_CALIB_LINEARITY_INDEX1 /*!< Linearity Calibration Index 1*/ 992 #define ADC_CALIB_LINEARITY_INDEX2 LL_ADC_CALIB_LINEARITY_INDEX2 /*!< Linearity Calibration Index 1*/ 993 #define ADC_CALIB_LINEARITY_INDEX3 LL_ADC_CALIB_LINEARITY_INDEX3 /*!< Linearity Calibration Index 1*/ 994 #define ADC_CALIB_LINEARITY_INDEX4 LL_ADC_CALIB_LINEARITY_INDEX4 /*!< Linearity Calibration Index 1*/ 995 #define ADC_CALIB_LINEARITY_INDEX5 LL_ADC_CALIB_LINEARITY_INDEX5 /*!< Linearity Calibration Index 1*/ 996 #define ADC_CALIB_LINEARITY_INDEX6 LL_ADC_CALIB_LINEARITY_INDEX6 /*!< Linearity Calibration Index 1*/ 997 #define ADC_CALIB_LINEARITY_INDEX7 LL_ADC_CALIB_LINEARITY_INDEX7 /*!< Linearity Calibration Index 1*/ 998 #define ADC_CALIB_INTEROFFSET_INDEX LL_ADC_CALIB_INTEROFFSET_INDEX /*!< Linearity Calibration Index 1*/ 999 /** 1000 * @} 1001 */ 1002 1003 /** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number 1004 * @{ 1005 */ 1006 /* Note: VrefInt, TempSensor and Vbat internal channels are not available on */ 1007 /* all ADC instances (refer to Reference Manual). */ 1008 #define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ 1009 #define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ 1010 #define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ 1011 #define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ 1012 #define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ 1013 #define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ 1014 #define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ 1015 #define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ 1016 #define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ 1017 #define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ 1018 #define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ 1019 #define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ 1020 #define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ 1021 #define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ 1022 #define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ 1023 #define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ 1024 #define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ 1025 #define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ 1026 #define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ 1027 #define ADC_CHANNEL_19 (LL_ADC_CHANNEL_19) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */ 1028 #define ADC_CHANNEL_20 (LL_ADC_CHANNEL_20) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN20 */ 1029 #define ADC_CHANNEL_21 (LL_ADC_CHANNEL_21) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN21 */ 1030 #define ADC_CHANNEL_22 (LL_ADC_CHANNEL_22) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN22 */ 1031 #define ADC_CHANNEL_23 (LL_ADC_CHANNEL_23) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN23 */ 1032 #define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */ 1033 #define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< ADC internal channel connected to Temperature sensor. */ 1034 #define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. */ 1035 1036 #define ADC_CHANNEL_DAC1CH1_ADC4 (LL_ADC_CHANNEL_DAC1CH1_ADC4) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC4 */ 1037 #define ADC_CHANNEL_DAC1CH2_ADC4 (LL_ADC_CHANNEL_DAC1CH2_ADC4) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC4 */ 1038 1039 #define ADC4_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR_ADC4) /*!< ADC internal channel connected to Temperature sensor, channel specific to ADC4. */ 1040 #define ADC4_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT_ADC4) /*!< ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, channel specific to ADC4. */ 1041 1042 #define ADC_CHANNEL_VCORE (LL_ADC_CHANNEL_VCORE) /*!< ADC internal channel connected to Vcore, channel specific to ADC4. */ 1043 1044 /** 1045 * @} 1046 */ 1047 1048 /** @defgroup ADC_ConversionDataManagement ADC Conversion Data Management 1049 * @{ 1050 */ 1051 #define ADC_CONVERSIONDATA_DR ((uint32_t)0x00000000) /*!< Regular Conversion data stored in DR register only */ 1052 #define ADC_CONVERSIONDATA_MDF ((uint32_t)ADC_CFGR1_DMNGT_1) /*!< MDF mode selected */ 1053 #define ADC_CONVERSIONDATA_DMA_ONESHOT ((uint32_t)ADC_CFGR1_DMNGT_0) /*!< DMA one shot mode selected */ 1054 #define ADC_CONVERSIONDATA_DMA_CIRCULAR ((uint32_t)(ADC_CFGR1_DMNGT_0 | ADC_CFGR1_DMNGT_1)) /*!< DMA circular mode selected */ 1055 /** 1056 * @} 1057 */ 1058 /** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number 1059 * @{ 1060 */ 1061 #define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ 1062 #define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */ 1063 #define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */ 1064 /** 1065 * @} 1066 */ 1067 1068 /** @defgroup ADC_analog_watchdog_filtering_config ADC Analog Watchdog filtering configuration 1069 * @{ 1070 */ 1071 #define ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog watchdog no filtering, one out-of-window sample is needed to raise flag or interrupt */ 1072 #define ADC_AWD_FILTERING_2SAMPLES ((ADC_HTR_AWDFILT_0)) /*!< ADC analog watchdog 2 consecutives out-of-window samples are needed to raise flag or interrupt */ 1073 #define ADC_AWD_FILTERING_3SAMPLES ((ADC_HTR_AWDFILT_1)) /*!< ADC analog watchdog 3 consecutives out-of-window samples are needed to raise flag or interrupt */ 1074 #define ADC_AWD_FILTERING_4SAMPLES ((ADC_HTR_AWDFILT_1 | ADC_HTR_AWDFILT_0)) /*!< ADC analog watchdog 4 consecutives out-of-window samples are needed to raise flag or interrupt */ 1075 #define ADC_AWD_FILTERING_5SAMPLES ((ADC_HTR_AWDFILT_2)) /*!< ADC analog watchdog 5 consecutives out-of-window samples are needed to raise flag or interrupt */ 1076 #define ADC_AWD_FILTERING_6SAMPLES ((ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_0)) /*!< ADC analog watchdog 6 consecutives out-of-window samples are needed to raise flag or interrupt */ 1077 #define ADC_AWD_FILTERING_7SAMPLES ((ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_1)) /*!< ADC analog watchdog 7 consecutives out-of-window samples are needed to raise flag or interrupt */ 1078 #define ADC_AWD_FILTERING_8SAMPLES ((ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_1 | ADC_HTR_AWDFILT_0)) /*!< ADC analog watchdog 8 consecutives out-of-window samples are needed to raise flag or interrupt */ 1079 /** 1080 * @} 1081 */ 1082 1083 1084 1085 /** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode 1086 * @{ 1087 */ 1088 #define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */ 1089 #define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */ 1090 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR1_AWD1SGL | ADC_CFGR1_JAWD1EN) /*!< Analog watchdog applied to an injected group single channel */ 1091 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN | ADC_CFGR1_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */ 1092 #define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR1_AWD1EN) /*!< Analog watchdog applied to regular group all channels */ 1093 #define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR1_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */ 1094 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR1_AWD1EN | ADC_CFGR1_JAWD1EN) /*!< Analog watchdog applied to regular and injected groups all channels */ 1095 /** 1096 * @} 1097 */ 1098 1099 /** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio 1100 * @{ 1101 */ 1102 #define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 1103 #define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 1104 #define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 1105 #define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 1106 #define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 1107 #define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 1108 #define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 1109 #define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 1110 /** 1111 * @} 1112 */ 1113 /** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift 1114 * @{ 1115 */ 1116 #define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ 1117 #define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */ 1118 #define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */ 1119 #define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */ 1120 #define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */ 1121 #define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */ 1122 #define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */ 1123 #define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */ 1124 #define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */ 1125 #define ADC_RIGHTBITSHIFT_9 (LL_ADC_OVS_SHIFT_RIGHT_9) /*!< ADC oversampling shift of 9 (sum of the ADC conversions data is divided by 512 to result as the ADC oversampling conversion data) */ 1126 #define ADC_RIGHTBITSHIFT_10 (LL_ADC_OVS_SHIFT_RIGHT_10)/*!< ADC oversampling shift of 10 (sum of the ADC conversions data is divided by 1024 to result as the ADC oversampling conversion data) */ 1127 #define ADC_RIGHTBITSHIFT_11 (LL_ADC_OVS_SHIFT_RIGHT_11)/*!< ADC oversampling shift of 11 (sum of the ADC conversions data is divided by 2048 to result as the ADC oversampling conversion data) */ 1128 /** 1129 * @} 1130 */ 1131 1132 /** @defgroup ADCEx_Left_Bit_Shift ADC Extended Oversampling left Shift 1133 * @{ 1134 */ 1135 #define ADC_LEFTBITSHIFT_NONE (LL_ADC_LEFT_BIT_SHIFT_NONE) /*!< ADC No bit shift */ 1136 #define ADC_LEFTBITSHIFT_1 (LL_ADC_LEFT_BIT_SHIFT_1) /*!< ADC 1 bit shift */ 1137 #define ADC_LEFTBITSHIFT_2 (LL_ADC_LEFT_BIT_SHIFT_2) /*!< ADC 2 bits shift */ 1138 #define ADC_LEFTBITSHIFT_3 (LL_ADC_LEFT_BIT_SHIFT_3) /*!< ADC 3 bits shift */ 1139 #define ADC_LEFTBITSHIFT_4 (LL_ADC_LEFT_BIT_SHIFT_4) /*!< ADC 4 bits shift */ 1140 #define ADC_LEFTBITSHIFT_5 (LL_ADC_LEFT_BIT_SHIFT_5) /*!< ADC 5 bits shift */ 1141 #define ADC_LEFTBITSHIFT_6 (LL_ADC_LEFT_BIT_SHIFT_6) /*!< ADC 6 bits shift */ 1142 #define ADC_LEFTBITSHIFT_7 (LL_ADC_LEFT_BIT_SHIFT_7) /*!< ADC 7 bits shift */ 1143 #define ADC_LEFTBITSHIFT_8 (LL_ADC_LEFT_BIT_SHIFT_8) /*!< ADC 8 bits shift */ 1144 #define ADC_LEFTBITSHIFT_9 (LL_ADC_LEFT_BIT_SHIFT_9) /*!< ADC 9 bits shift */ 1145 #define ADC_LEFTBITSHIFT_10 (LL_ADC_LEFT_BIT_SHIFT_10) /*!< ADC 10 bits shift */ 1146 #define ADC_LEFTBITSHIFT_11 (LL_ADC_LEFT_BIT_SHIFT_11) /*!< ADC 11 bits shift */ 1147 #define ADC_LEFTBITSHIFT_12 (LL_ADC_LEFT_BIT_SHIFT_12) /*!< ADC 12 bits shift */ 1148 #define ADC_LEFTBITSHIFT_13 (LL_ADC_LEFT_BIT_SHIFT_13) /*!< ADC 13 bits shift */ 1149 #define ADC_LEFTBITSHIFT_14 (LL_ADC_LEFT_BIT_SHIFT_14) /*!< ADC 14 bits shift */ 1150 #define ADC_LEFTBITSHIFT_15 (LL_ADC_LEFT_BIT_SHIFT_15) /*!< ADC 15 bits shift */ 1151 /** 1152 * @} 1153 */ 1154 1155 /** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode 1156 * @{ 1157 */ 1158 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ 1159 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ 1160 /** 1161 * @} 1162 */ 1163 1164 /** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular 1165 * @{ 1166 */ 1167 #define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained during injection sequence */ 1168 #define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during injection sequence */ 1169 /** 1170 * @} 1171 */ 1172 1173 /** @defgroup ADC_HAL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode 1174 * @{ 1175 */ 1176 #define ADC_TRIGGER_FREQ_HIGH (LL_ADC_TRIGGER_FREQ_HIGH) /*!< ADC trigger frequency mode set to high frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */ 1177 #define ADC_TRIGGER_FREQ_LOW (LL_ADC_TRIGGER_FREQ_LOW) /*!< ADC trigger frequency mode set to low frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */ 1178 /** 1179 * @} 1180 */ 1181 1182 /** @defgroup ADC_Event_type ADC Event type 1183 * @{ 1184 */ 1185 #define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ 1186 #define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */ 1187 #define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */ 1188 #define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */ 1189 #define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ 1190 /** 1191 * @} 1192 */ 1193 #define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */ 1194 1195 /** @defgroup ADC_interrupts_definition ADC interrupts definition 1196 * @{ 1197 */ 1198 #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ 1199 #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ 1200 #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ 1201 #define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ 1202 #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ 1203 #define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */ 1204 #define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */ 1205 #define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ 1206 #define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */ 1207 #define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */ 1208 #define ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC End of Calibration interrupt source */ 1209 #define ADC_IT_LDORDY ADC_IER_LDORDYIE /*!< ADC Voltage Regulator (LDO) Ready interrupt source */ 1210 1211 #define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */ 1212 1213 /** 1214 * @} 1215 */ 1216 1217 /** @defgroup ADC_flags_definition ADC flags definition 1218 * @{ 1219 */ 1220 #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ 1221 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ 1222 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ 1223 #define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ 1224 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ 1225 #define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */ 1226 #define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */ 1227 #define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */ 1228 #define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ 1229 #define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ 1230 #define ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC End of Calibration flag */ 1231 #define ADC_FLAG_LDORDY ADC_ISR_LDORDY /*!< ADC Voltage Regulator (LDO) Ready flag */ 1232 1233 /** 1234 * @} 1235 */ 1236 1237 /** 1238 * @} 1239 */ 1240 1241 /* Private macro -------------------------------------------------------------*/ 1242 1243 /** @defgroup ADC_Private_Macros ADC Private Macros 1244 * @{ 1245 */ 1246 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 1247 /* code of final user. */ 1248 1249 /** 1250 * @brief Verify the ADC data conversion setting. 1251 * @param DATA : programmed DATA conversion mode. 1252 * @retval SET (DATA is a valid value) or RESET (DATA is invalid) 1253 */ 1254 #define IS_ADC_CONVERSIONDATAMGT(DATA) \ 1255 ((((DATA) == ADC_CONVERSIONDATA_DR)) || \ 1256 (((DATA) == ADC_CONVERSIONDATA_MDF)) || \ 1257 (((DATA) == ADC_CONVERSIONDATA_DMA_ONESHOT)) || \ 1258 (((DATA) == ADC_CONVERSIONDATA_DMA_CIRCULAR))) 1259 1260 /** 1261 * @brief Return resolution bits in CFGR register RES[1:0] field. 1262 * @param __HANDLE__ ADC handle 1263 * @retval Value of bitfield RES in CFGR register. 1264 */ 1265 #define ADC_GET_RESOLUTION(__HANDLE__) \ 1266 (LL_ADC_GetResolution((__HANDLE__)->Instance)) 1267 1268 /** 1269 * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE"). 1270 * @param __HANDLE__ ADC handle 1271 * @retval None 1272 */ 1273 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 1274 1275 /** 1276 * @brief Verification of ADC state: enabled or disabled. 1277 * @param __HANDLE__ ADC handle 1278 * @retval SET (ADC enabled) or RESET (ADC disabled) 1279 */ 1280 #define ADC_IS_ENABLE(__HANDLE__) \ 1281 (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ 1282 ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \ 1283 ) ? SET : RESET) 1284 1285 /** 1286 * @brief Enable ADC overrun mode. 1287 * @param _OVERRUN_MODE_ Overrun mode. 1288 * @retval Overrun bit setting to be programmed into CFGR register 1289 */ 1290 /* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */ 1291 /* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it */ 1292 /* as the default case to be compliant with other STM32 devices. */ 1293 #define ADC_CFGR_OVERRUN(_OVERRUN_MODE_) \ 1294 ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \ 1295 )? (ADC_CFGR1_OVRMOD) : (0x00000000UL) \ 1296 ) 1297 1298 /* Note: Scan mode set using this macro (instead of parameter direct set) */ 1299 /* due to different modes on other STM32 devices: */ 1300 /* if scan mode is disabled, sequencer is set to fully configurable */ 1301 /* with setting of only rank 1 enabled afterwards. */ 1302 #define ADC_SCAN_SEQ_MODE(_SCAN_MODE_) \ 1303 ( (((_SCAN_MODE_) & ADC4_SCAN_SEQ_FIXED_INT) != 0UL \ 1304 )? \ 1305 ((_SCAN_MODE_) & (~ADC4_SCAN_SEQ_FIXED_INT)) \ 1306 : \ 1307 (ADC4_CFGR1_CHSELRMOD) \ 1308 ) 1309 1310 /** 1311 * @brief Check if conversion is on going on regular group. 1312 * @param __HANDLE__ ADC handle 1313 * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going) 1314 */ 1315 #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ 1316 (LL_ADC_REG_IsConversionOngoing((__HANDLE__)->Instance)) 1317 1318 1319 /** 1320 * @brief Simultaneously clear and set specific bits of the handle State. 1321 * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 1322 * the first parameter is the ADC handle State, the second parameter is the 1323 * bit field to clear, the third and last parameter is the bit field to set. 1324 * @retval None 1325 */ 1326 #define ADC_STATE_CLR_SET MODIFY_REG 1327 1328 /** 1329 * @brief Verify that a given value is aligned with the ADC resolution range. 1330 * @param __ADCx__ ADC instance 1331 * @param __RESOLUTION__ ADC resolution (14, 12, 10, 8 or 6 bits). 1332 * @param __ADC_VALUE__ value checked against the resolution. 1333 * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) 1334 */ 1335 #define IS_ADC_RANGE(__ADCx__, __RESOLUTION__, __ADC_VALUE__) \ 1336 ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__ADCx__, __RESOLUTION__)) 1337 1338 /** 1339 * @brief Verify the length of the scheduled regular conversions group. 1340 * @param __LENGTH__ number of programmed conversions. 1341 * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) 1342 * or RESET (__LENGTH__ is null or too large) 1343 */ 1344 #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL))) 1345 1346 /** @defgroup ADC_regular_nb_conv_verification ADC4 Regular Conversion Number Verification 1347 * @{ 1348 */ 1349 #define IS_ADC4_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1UL) && ((LENGTH) <= 8UL)) 1350 /** 1351 * @} 1352 */ 1353 1354 /** 1355 * @brief Verify the number of scheduled regular conversions in discontinuous mode. 1356 * @param NUMBER number of scheduled regular conversions in discontinuous mode. 1357 * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) 1358 * or RESET (NUMBER is null or too large) 1359 */ 1360 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL))) 1361 1362 1363 /** 1364 * @brief Verify the ADC clock setting. 1365 * @param __ADC_CLOCK__ programmed ADC clock. 1366 * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid) 1367 */ 1368 #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \ 1369 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \ 1370 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \ 1371 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \ 1372 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \ 1373 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \ 1374 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \ 1375 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \ 1376 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \ 1377 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \ 1378 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \ 1379 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) ) 1380 1381 /** 1382 * @brief Verify the ADC resolution setting. 1383 * @param __RESOLUTION__ programmed ADC resolution. 1384 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 1385 */ 1386 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_14B) || \ 1387 ((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ 1388 ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ 1389 ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ 1390 ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) 1391 1392 /** 1393 * @brief Verify the ADC resolution setting when limited to 6 or 8 bits. 1394 * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits. 1395 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 1396 */ 1397 #define IS_ADC_RESOLUTION_8_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B)) 1398 1399 /** 1400 * @brief Verify the ADC resolution setting. 1401 * @param __RESOLUTION__ programmed ADC resolution. 1402 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 1403 */ 1404 #define IS_ADC4_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC4_RESOLUTION_12B) || \ 1405 ((__RESOLUTION__) == ADC4_RESOLUTION_10B) || \ 1406 ((__RESOLUTION__) == ADC4_RESOLUTION_8B) || \ 1407 ((__RESOLUTION__) == ADC4_RESOLUTION_6B) ) 1408 1409 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ 1410 ((ALIGN) == ADC_DATAALIGN_LEFT) ) 1411 1412 /** 1413 * @brief Verify the ADC gain compensation. 1414 * @param __GAIN_COMPENSATION__ programmed ADC gain compensation coefficient. 1415 * @retval SET (__GAIN_COMPENSATION__ is a valid value) or RESET (__GAIN_COMPENSATION__ is invalid) 1416 */ 1417 #define IS_ADC_GAIN_COMPENSATION(__GAIN_COMPENSATION__) ((__GAIN_COMPENSATION__) <= 16393UL) 1418 1419 /** 1420 * @brief Verify the ADC scan mode. 1421 * @param __SCAN_MODE__ programmed ADC scan mode. 1422 * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid) 1423 */ 1424 #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \ 1425 ((__SCAN_MODE__) == ADC_SCAN_ENABLE) ) 1426 1427 #define IS_ADC4_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC4_SCAN_DISABLE) || \ 1428 ((SCAN_MODE) == ADC4_SCAN_ENABLE) || \ 1429 ((SCAN_MODE) == ADC_SCAN_SEQ_FIXED) || \ 1430 ((SCAN_MODE) == ADC_SCAN_SEQ_FIXED_BACKWARD) ) 1431 1432 /** 1433 * @brief Verify the ADC edge trigger setting for regular group. 1434 * @param __EDGE__ programmed ADC edge trigger setting. 1435 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 1436 */ 1437 #define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 1438 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 1439 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 1440 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) 1441 1442 /** 1443 * @brief Verify the ADC regular conversions external trigger. 1444 * @param __REGTRIG__ programmed ADC regular conversions external trigger. 1445 * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid) 1446 */ 1447 #define IS_ADC_EXTTRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ 1448 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ 1449 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ 1450 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ 1451 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ 1452 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ 1453 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ 1454 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ 1455 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ 1456 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ 1457 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 1458 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ 1459 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ 1460 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ 1461 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ 1462 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ 1463 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT15) || \ 1464 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM1_CH1) || \ 1465 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM2_CH1) || \ 1466 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM3_CH1) || \ 1467 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM4_OUT) || \ 1468 ((__REGTRIG__) == ADC_SOFTWARE_START) ) 1469 1470 1471 #define IS_ADC4_EXTTRIG(REGTRIG) (((REGTRIG) == ADC4_EXTERNALTRIG_T1_TRGO2) || \ 1472 ((REGTRIG) == ADC4_EXTERNALTRIG_T1_CC4) || \ 1473 ((REGTRIG) == ADC4_EXTERNALTRIG_T2_TRGO) || \ 1474 ((REGTRIG) == ADC4_EXTERNALTRIG_T15_TRGO) || \ 1475 ((REGTRIG) == ADC4_EXTERNALTRIG_T6_TRGO) || \ 1476 ((REGTRIG) == ADC4_EXTERNALTRIG_LPTIM1_CH1) || \ 1477 ((REGTRIG) == ADC4_EXTERNALTRIG_LPTIM3_CH2) || \ 1478 ((REGTRIG) == ADC4_EXTERNALTRIG_EXT_IT15) || \ 1479 ((REGTRIG) == ADC_SOFTWARE_START) ) 1480 1481 /** 1482 * @brief Verify the ADC regular conversions check for converted data availability. 1483 * @param __EOC_SELECTION__ converted data availability check. 1484 * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid) 1485 */ 1486 #define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \ 1487 ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) ) 1488 1489 /** 1490 * @brief Verify the ADC regular conversions overrun handling. 1491 * @param __OVR__ ADC regular conversions overrun handling. 1492 * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid) 1493 */ 1494 #define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \ 1495 ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) ) 1496 1497 /** 1498 * @brief Verify the ADC conversions sampling time. 1499 * @param __TIME__ ADC conversions sampling time. 1500 * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid) 1501 */ 1502 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_5CYCLES) || \ 1503 ((__TIME__) == ADC_SAMPLETIME_6CYCLES) || \ 1504 ((__TIME__) == ADC_SAMPLETIME_12CYCLES) || \ 1505 ((__TIME__) == ADC_SAMPLETIME_20CYCLES) || \ 1506 ((__TIME__) == ADC_SAMPLETIME_36CYCLES) || \ 1507 ((__TIME__) == ADC_SAMPLETIME_68CYCLES) || \ 1508 ((__TIME__) == ADC_SAMPLETIME_391CYCLES) || \ 1509 ((__TIME__) == ADC_SAMPLETIME_814CYCLES) ) 1510 1511 #define IS_ADC4_SAMPLE_TIME(TIME) (((TIME) == ADC4_SAMPLETIME_1CYCLE_5) || \ 1512 ((TIME) == ADC4_SAMPLETIME_3CYCLES_5) || \ 1513 ((TIME) == ADC4_SAMPLETIME_7CYCLES_5) || \ 1514 ((TIME) == ADC4_SAMPLETIME_12CYCLES_5) || \ 1515 ((TIME) == ADC4_SAMPLETIME_19CYCLES_5) || \ 1516 ((TIME) == ADC4_SAMPLETIME_39CYCLES_5) || \ 1517 ((TIME) == ADC4_SAMPLETIME_79CYCLES_5) || \ 1518 ((TIME) == ADC4_SAMPLETIME_814CYCLES_5) ) 1519 1520 #define IS_ADC4_SAMPLE_TIME_COMMON(TIME) (((TIME) == ADC4_SAMPLINGTIME_COMMON_1) || \ 1521 ((TIME) == ADC4_SAMPLINGTIME_COMMON_2) ) 1522 /** 1523 * @brief Verify the ADC regular channel setting. 1524 * @param __CHANNEL__ programmed ADC regular channel. 1525 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 1526 */ 1527 #define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \ 1528 ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \ 1529 ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \ 1530 ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \ 1531 ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \ 1532 ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \ 1533 ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \ 1534 ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \ 1535 ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \ 1536 ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \ 1537 ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \ 1538 ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \ 1539 ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \ 1540 ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \ 1541 ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \ 1542 ((__CHANNEL__) == ADC_REGULAR_RANK_16) ) 1543 1544 1545 #define IS_ADC4_REGULAR_RANK(RANK) (((RANK) == ADC4_REGULAR_RANK_1 ) || \ 1546 ((RANK) == ADC4_REGULAR_RANK_2 ) || \ 1547 ((RANK) == ADC4_REGULAR_RANK_3 ) || \ 1548 ((RANK) == ADC4_REGULAR_RANK_4 ) || \ 1549 ((RANK) == ADC4_REGULAR_RANK_5 ) || \ 1550 ((RANK) == ADC4_REGULAR_RANK_6 ) || \ 1551 ((RANK) == ADC4_REGULAR_RANK_7 ) || \ 1552 ((RANK) == ADC4_REGULAR_RANK_8 ) ) 1553 1554 #define IS_ADC4_REGULAR_RANK_SEQ_FIXED(RANK) (((RANK) == ADC4_RANK_CHANNEL_NUMBER) || \ 1555 ((RANK) == ADC4_RANK_NONE) ) 1556 1557 1558 #define IS_ADC_TRIGGER_FREQ(TRIGGER_FREQ) (((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_HIGH) || \ 1559 ((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_LOW) ) 1560 1561 #define IS_ADC4_LOW_POWER(__LP_MODE__) (((__LP_MODE__) == ADC_LOW_POWER_NONE) || \ 1562 ((__LP_MODE__) == ADC_LOW_POWER_AUTOFF) || \ 1563 ((__LP_MODE__) == ADC_LOW_POWER_DPD) || \ 1564 ((__LP_MODE__) == ADC_LOW_POWER_AUTOFF_DPD) ) 1565 1566 #define IS_ADC4_VREF_PROT(__VREF_PROT__) (((__VREF_PROT__) == ADC_VREF_PPROT_NONE) || \ 1567 ((__VREF_PROT__) == ADC_VREF_PPROT_VREFPROT) || \ 1568 ((__VREF_PROT__) == ADC_VREF_PPROT_VREFSECSMP) || \ 1569 ((__VREF_PROT__) == ADC_VREF_PPROT_VREF_VREFSECSMP) ) 1570 1571 /** 1572 * @} 1573 */ 1574 1575 1576 /* Private constants ---------------------------------------------------------*/ 1577 1578 /** @defgroup ADC_Private_Constants ADC Private Constants 1579 * @{ 1580 */ 1581 1582 /* Fixed timeout values for ADC conversion (including sampling time) */ 1583 /* Maximum sampling time is 810.5 ADC clock cycle */ 1584 /* Maximum conversion time is 16.5 + Maximum sampling time */ 1585 /* or 16.5 + 810.5 = 827 ADC clock cycles */ 1586 /* Minimum ADC Clock frequency is 0.35 MHz */ 1587 /* Maximum conversion time is */ 1588 /* 653 / 0.14 MHz = 4.66 ms */ 1589 #define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */ 1590 1591 /* Delay for temperature sensor stabilization time. */ 1592 /* Maximum delay is 120us (refer device datasheet, parameter tSTART). */ 1593 /* Unit: us */ 1594 #define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US) 1595 1596 /* Delay for ADC voltage regulator startup time */ 1597 /* Maximum delay is 10 microseconds */ 1598 /* (refer device RM, parameter Tadcvreg_stup). */ 1599 #define ADC_STAB_DELAY_US ((uint32_t) 10) /*!< ADC voltage regulator startup time */ 1600 1601 /** 1602 * @} 1603 */ 1604 1605 /* Exported macro ------------------------------------------------------------*/ 1606 1607 /** @defgroup ADC_Exported_Macros ADC Exported Macros 1608 * @{ 1609 */ 1610 /* Macro for internal HAL driver usage, and possibly can be used into code of */ 1611 /* final user. */ 1612 1613 /** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags. 1614 * @{ 1615 */ 1616 1617 /** @brief Reset ADC handle state. 1618 * @param __HANDLE__ ADC handle 1619 * @retval None 1620 */ 1621 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1622 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1623 do{ \ 1624 (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ 1625 (__HANDLE__)->MspInitCallback = NULL; \ 1626 (__HANDLE__)->MspDeInitCallback = NULL; \ 1627 } while(0) 1628 #else 1629 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1630 ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 1631 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 1632 1633 /** 1634 * @brief Enable ADC interrupt. 1635 * @param __HANDLE__ ADC handle 1636 * @param __INTERRUPT__ ADC Interrupt 1637 * This parameter can be one of the following values: 1638 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1639 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1640 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1641 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1642 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1643 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1644 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1645 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1646 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1647 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1648 * @arg @ref ADC_IT_EOCAL ADC End of Calibration interrupt source 1649 * @arg @ref ADC_IT_LDORDY ADC Voltage Regulator (LDO) Ready interrupt source 1650 * @retval None 1651 */ 1652 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 1653 (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) 1654 1655 /** 1656 * @brief Disable ADC interrupt. 1657 * @param __HANDLE__ ADC handle 1658 * @param __INTERRUPT__ ADC Interrupt 1659 * This parameter can be one of the following values: 1660 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1661 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1662 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1663 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1664 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1665 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1666 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1667 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1668 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1669 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1670 * @arg @ref ADC_IT_EOCAL ADC End of Calibration interrupt source 1671 * @arg @ref ADC_IT_LDORDY ADC Voltage Regulator (LDO) Ready interrupt source 1672 * @retval None 1673 */ 1674 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 1675 (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) 1676 1677 /** @brief Checks if the specified ADC interrupt source is enabled or disabled. 1678 * @param __HANDLE__ ADC handle 1679 * @param __INTERRUPT__ ADC interrupt source to check 1680 * This parameter can be one of the following values: 1681 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1682 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1683 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1684 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1685 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1686 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1687 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1688 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1689 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1690 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1691 * @arg @ref ADC_IT_EOCAL ADC End of Calibration interrupt source 1692 * @arg @ref ADC_IT_LDORDY ADC Voltage Regulator (LDO) Ready interrupt source 1693 * @retval State of interruption (SET or RESET) 1694 */ 1695 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 1696 (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) 1697 1698 /** 1699 * @brief Check whether the specified ADC flag is set or not. 1700 * @param __HANDLE__ ADC handle 1701 * @param __FLAG__ ADC flag 1702 * This parameter can be one of the following values: 1703 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1704 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1705 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1706 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1707 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1708 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag 1709 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag 1710 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1711 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1712 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1713 * @arg @ref ADC_FLAG_EOCAL ADC End of Calibration flag 1714 * @arg @ref ADC_FLAG_LDORDY ADC Voltage Regulator (LDO) Ready flag 1715 * @retval State of flag (TRUE or FALSE). 1716 */ 1717 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ 1718 ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) 1719 1720 /** 1721 * @brief Clear the specified ADC flag. 1722 * @param __HANDLE__ ADC handle 1723 * @param __FLAG__ ADC flag 1724 * This parameter can be one of the following values: 1725 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1726 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1727 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1728 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1729 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1730 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag 1731 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag 1732 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1733 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1734 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1735 * @arg @ref ADC_FLAG_EOCAL ADC End of Calibration flag 1736 * @arg @ref ADC_FLAG_LDORDY ADC Voltage Regulator (LDO) Ready flag 1737 * @retval None 1738 */ 1739 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ 1740 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 1741 (((__HANDLE__)->Instance->ISR) = (__FLAG__)) 1742 1743 /** 1744 * @} 1745 */ 1746 1747 /** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro 1748 * @{ 1749 */ 1750 1751 /** 1752 * @brief Helper macro to get ADC channel number in decimal format 1753 * from literals ADC_CHANNEL_x. 1754 * @note Example: 1755 * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) 1756 * will return decimal number "4". 1757 * @note The input can be a value from functions where a channel 1758 * number is returned, either defined with number 1759 * or with bitfield (only one bit must be set). 1760 * @param __CHANNEL__ This parameter can be one of the following values: 1761 * @arg @ref ADC_CHANNEL_0 (3) 1762 * @arg @ref ADC_CHANNEL_1 (3) 1763 * @arg @ref ADC_CHANNEL_2 (3) 1764 * @arg @ref ADC_CHANNEL_3 (3) 1765 * @arg @ref ADC_CHANNEL_4 (3) 1766 * @arg @ref ADC_CHANNEL_5 (3) 1767 * @arg @ref ADC_CHANNEL_6 1768 * @arg @ref ADC_CHANNEL_7 1769 * @arg @ref ADC_CHANNEL_8 1770 * @arg @ref ADC_CHANNEL_9 1771 * @arg @ref ADC_CHANNEL_10 1772 * @arg @ref ADC_CHANNEL_11 1773 * @arg @ref ADC_CHANNEL_12 1774 * @arg @ref ADC_CHANNEL_13 1775 * @arg @ref ADC_CHANNEL_14 1776 * @arg @ref ADC_CHANNEL_15 1777 * @arg @ref ADC_CHANNEL_16 1778 * @arg @ref ADC_CHANNEL_17 1779 * @arg @ref ADC_CHANNEL_18 1780 * @arg @ref ADC_CHANNEL_VREFINT (1) 1781 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 1782 * @arg @ref ADC_CHANNEL_VBAT (1) 1783 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC4 (2) 1784 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC4 (2) 1785 * 1786 * (1) On STM32U5, parameter available only on ADC instance: ADC1.\n 1787 * (2) On STM32U5, parameter available only on ADC instance: ADC4.\n 1788 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). 1789 * Other channels are slow channels (conversion rate: refer to reference manual). 1790 * @retval Value between Min_Data=0 and Max_Data=18 1791 */ 1792 #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 1793 __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) 1794 1795 /** 1796 * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x 1797 * from number in decimal format. 1798 * @note Example: 1799 * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) 1800 * will return a data equivalent to "ADC_CHANNEL_4". 1801 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 1802 * @retval Returned value can be one of the following values: 1803 * @arg @ref ADC_CHANNEL_0 (3) 1804 * @arg @ref ADC_CHANNEL_1 (3) 1805 * @arg @ref ADC_CHANNEL_2 (3) 1806 * @arg @ref ADC_CHANNEL_3 (3) 1807 * @arg @ref ADC_CHANNEL_4 (3) 1808 * @arg @ref ADC_CHANNEL_5 (3) 1809 * @arg @ref ADC_CHANNEL_6 1810 * @arg @ref ADC_CHANNEL_7 1811 * @arg @ref ADC_CHANNEL_8 1812 * @arg @ref ADC_CHANNEL_9 1813 * @arg @ref ADC_CHANNEL_10 1814 * @arg @ref ADC_CHANNEL_11 1815 * @arg @ref ADC_CHANNEL_12 1816 * @arg @ref ADC_CHANNEL_13 1817 * @arg @ref ADC_CHANNEL_14 1818 * @arg @ref ADC_CHANNEL_15 1819 * @arg @ref ADC_CHANNEL_16 1820 * @arg @ref ADC_CHANNEL_17 1821 * @arg @ref ADC_CHANNEL_18 1822 * @arg @ref ADC_CHANNEL_VREFINT (1) 1823 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 1824 * @arg @ref ADC_CHANNEL_VBAT (1) 1825 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC4 (2) 1826 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC4 (2) 1827 * @arg @ref ADC4_CHANNEL_TEMPSENSOR (2) 1828 * @arg @ref ADC4_CHANNEL_VBAT (2) 1829 * @arg @ref ADC_CHANNEL_VCORE (2) 1830 * 1831 * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.\n 1832 * (2) On STM32U5, parameter available only on ADC instance: ADC4.\n 1833 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). 1834 * Other channels are slow channels (conversion rate: refer to reference manual).\n 1835 * (1, 2) For ADC channel read back from ADC register, 1836 * comparison with internal channel parameter to be done 1837 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 1838 */ 1839 #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 1840 __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) 1841 1842 /** 1843 * @brief Helper macro to determine whether the selected channel 1844 * corresponds to literal definitions of driver. 1845 * @note The different literal definitions of ADC channels are: 1846 * - ADC internal channel: 1847 * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ... 1848 * - ADC external channel (channel connected to a GPIO pin): 1849 * ADC_CHANNEL_1, ADC_CHANNEL_2, ... 1850 * @note The channel parameter must be a value defined from literal 1851 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1852 * ADC_CHANNEL_TEMPSENSOR, ...), 1853 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), 1854 * must not be a value from functions where a channel number is 1855 * returned from ADC registers, 1856 * because internal and external channels share the same channel 1857 * number in ADC registers. The differentiation is made only with 1858 * parameters definitions of driver. 1859 * @param __CHANNEL__ This parameter can be one of the following values: 1860 * @arg @ref ADC_CHANNEL_0 (3) 1861 * @arg @ref ADC_CHANNEL_1 (3) 1862 * @arg @ref ADC_CHANNEL_2 (3) 1863 * @arg @ref ADC_CHANNEL_3 (3) 1864 * @arg @ref ADC_CHANNEL_4 (3) 1865 * @arg @ref ADC_CHANNEL_5 (3) 1866 * @arg @ref ADC_CHANNEL_6 1867 * @arg @ref ADC_CHANNEL_7 1868 * @arg @ref ADC_CHANNEL_8 1869 * @arg @ref ADC_CHANNEL_9 1870 * @arg @ref ADC_CHANNEL_10 1871 * @arg @ref ADC_CHANNEL_11 1872 * @arg @ref ADC_CHANNEL_12 1873 * @arg @ref ADC_CHANNEL_13 1874 * @arg @ref ADC_CHANNEL_14 1875 * @arg @ref ADC_CHANNEL_15 1876 * @arg @ref ADC_CHANNEL_16 1877 * @arg @ref ADC_CHANNEL_17 1878 * @arg @ref ADC_CHANNEL_18 1879 * @arg @ref ADC_CHANNEL_VREFINT (1) 1880 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 1881 * @arg @ref ADC_CHANNEL_VBAT (1) 1882 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC4 (2) 1883 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC4 (2) 1884 * @arg @ref ADC4_CHANNEL_TEMPSENSOR (2) 1885 * @arg @ref ADC4_CHANNEL_VBAT (2) 1886 * @arg @ref ADC_CHANNEL_VCORE (2) 1887 * 1888 * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.\n 1889 * (2) On STM32U5, parameter available only on ADC instance: ADC4.\n 1890 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). 1891 * Other channels are slow channels (conversion rate: refer to reference manual). 1892 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel 1893 * (channel connected to a GPIO pin). 1894 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. 1895 */ 1896 #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ 1897 __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) 1898 1899 /** 1900 * @brief Helper macro to convert a channel defined from parameter 1901 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1902 * ADC_CHANNEL_TEMPSENSOR, ...), 1903 * to its equivalent parameter definition of a ADC external channel 1904 * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...). 1905 * @note The channel parameter can be, additionally to a value 1906 * defined from parameter definition of a ADC internal channel 1907 * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), 1908 * a value defined from parameter definition of 1909 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1910 * or a value from functions where a channel number is returned 1911 * from ADC registers. 1912 * @param __CHANNEL__ This parameter can be one of the following values: 1913 * @arg @ref ADC_CHANNEL_0 (3) 1914 * @arg @ref ADC_CHANNEL_1 (3) 1915 * @arg @ref ADC_CHANNEL_2 (3) 1916 * @arg @ref ADC_CHANNEL_3 (3) 1917 * @arg @ref ADC_CHANNEL_4 (3) 1918 * @arg @ref ADC_CHANNEL_5 (3) 1919 * @arg @ref ADC_CHANNEL_6 1920 * @arg @ref ADC_CHANNEL_7 1921 * @arg @ref ADC_CHANNEL_8 1922 * @arg @ref ADC_CHANNEL_9 1923 * @arg @ref ADC_CHANNEL_10 1924 * @arg @ref ADC_CHANNEL_11 1925 * @arg @ref ADC_CHANNEL_12 1926 * @arg @ref ADC_CHANNEL_13 1927 * @arg @ref ADC_CHANNEL_14 1928 * @arg @ref ADC_CHANNEL_15 1929 * @arg @ref ADC_CHANNEL_16 1930 * @arg @ref ADC_CHANNEL_17 1931 * @arg @ref ADC_CHANNEL_18 1932 * @arg @ref ADC_CHANNEL_VREFINT (1) 1933 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 1934 * @arg @ref ADC_CHANNEL_VBAT (1) 1935 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC4 (2) 1936 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC4 (2) 1937 * @arg @ref ADC4_CHANNEL_TEMPSENSOR (2) 1938 * @arg @ref ADC4_CHANNEL_VBAT (2) 1939 * @arg @ref ADC_CHANNEL_VCORE (2) 1940 * 1941 * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.\n 1942 * (2) On STM32U5, parameter available only on ADC instance: ADC4. 1943 * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). 1944 * Other channels are slow channels (conversion rate: refer to reference manual).\n 1945 * @retval Returned value can be one of the following values: 1946 * @arg @ref ADC_CHANNEL_0 1947 * @arg @ref ADC_CHANNEL_1 1948 * @arg @ref ADC_CHANNEL_2 1949 * @arg @ref ADC_CHANNEL_3 1950 * @arg @ref ADC_CHANNEL_4 1951 * @arg @ref ADC_CHANNEL_5 1952 * @arg @ref ADC_CHANNEL_6 1953 * @arg @ref ADC_CHANNEL_7 1954 * @arg @ref ADC_CHANNEL_8 1955 * @arg @ref ADC_CHANNEL_9 1956 * @arg @ref ADC_CHANNEL_10 1957 * @arg @ref ADC_CHANNEL_11 1958 * @arg @ref ADC_CHANNEL_12 1959 * @arg @ref ADC_CHANNEL_13 1960 * @arg @ref ADC_CHANNEL_14 1961 * @arg @ref ADC_CHANNEL_15 1962 * @arg @ref ADC_CHANNEL_16 1963 * @arg @ref ADC_CHANNEL_17 1964 * @arg @ref ADC_CHANNEL_18 1965 */ 1966 #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ 1967 __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) 1968 1969 /** 1970 * @brief Helper macro to determine whether the internal channel 1971 * selected is available on the ADC instance selected. 1972 * @note The channel parameter must be a value defined from parameter 1973 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1974 * ADC_CHANNEL_TEMPSENSOR, ...), 1975 * must not be a value defined from parameter definition of 1976 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1977 * or a value from functions where a channel number is 1978 * returned from ADC registers, 1979 * because internal and external channels share the same channel 1980 * number in ADC registers. The differentiation is made only with 1981 * parameters definitions of driver. 1982 * @param __ADC_INSTANCE__ ADC instance 1983 * @param __CHANNEL__ This parameter can be one of the following values: 1984 * @arg @ref ADC_CHANNEL_VREFINT (1) 1985 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 1986 * @arg @ref ADC_CHANNEL_VBAT (1) 1987 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC4 (2) 1988 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC4 (2) 1989 * @arg @ref ADC4_CHANNEL_TEMPSENSOR (2) 1990 * @arg @ref ADC4_CHANNEL_VBAT (2) 1991 * @arg @ref ADC_CHANNEL_VCORE (2) 1992 * 1993 * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.\n 1994 * (2) On STM32U5, parameter available only on ADC instance: ADC4.\n 1995 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. 1996 * Value "1" if the internal channel selected is available on the ADC instance selected. 1997 */ 1998 #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ 1999 __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) 2000 2001 #if defined(ADC_MULTIMODE_SUPPORT) 2002 /** 2003 * @brief Helper macro to get the ADC multimode conversion data of ADC master 2004 * or ADC slave from raw value with both ADC conversion data concatenated. 2005 * @note This macro is intended to be used when multimode transfer by DMA 2006 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). 2007 * In this case the transferred data need to processed with this macro 2008 * to separate the conversion data of ADC master and ADC slave. 2009 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: 2010 * @arg @ref LL_ADC_MULTI_MASTER 2011 * @arg @ref LL_ADC_MULTI_SLAVE 2012 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF 2013 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 2014 */ 2015 #define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ 2016 __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__)) 2017 #endif /* ADC_MULTIMODE_SUPPORT */ 2018 2019 /** 2020 * @brief Helper macro to select the ADC common instance 2021 * to which is belonging the selected ADC instance. 2022 * @note ADC common register instance can be used for: 2023 * - Set parameters common to several ADC instances 2024 * - Multimode (for devices with several ADC instances) 2025 * Refer to functions having argument "ADCxy_COMMON" as parameter. 2026 * @param __ADCx__ ADC instance 2027 * @retval ADC common register instance 2028 */ 2029 #define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ 2030 __LL_ADC_COMMON_INSTANCE((__ADCx__)) 2031 2032 /** 2033 * @brief Helper macro to check if all ADC instances sharing the same 2034 * ADC common instance are disabled. 2035 * @note This check is required by functions with setting conditioned to 2036 * ADC state: 2037 * All ADC instances of the ADC common group must be disabled. 2038 * Refer to functions having argument "ADCxy_COMMON" as parameter. 2039 * @note On devices with only 1 ADC common instance, parameter of this macro 2040 * is useless and can be ignored (parameter kept for compatibility 2041 * with devices featuring several ADC common instances). 2042 * @param __ADCXY_COMMON__ ADC common instance 2043 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 2044 * @retval Value "0" if all ADC instances sharing the same ADC common instance 2045 * are disabled. 2046 * Value "1" if at least one ADC instance sharing the same ADC common instance 2047 * is enabled. 2048 */ 2049 #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 2050 __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) 2051 2052 /** 2053 * @brief Helper macro to define the ADC conversion data full-scale digital 2054 * value corresponding to the selected ADC resolution. 2055 * @note ADC conversion data full-scale corresponds to voltage range 2056 * determined by analog voltage references Vref+ and Vref- 2057 * (refer to reference manual). 2058 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 2059 * @arg @ref ADC_RESOLUTION_14B 2060 * @arg @ref ADC_RESOLUTION_12B 2061 * @arg @ref ADC_RESOLUTION_10B 2062 * @arg @ref ADC_RESOLUTION_8B 2063 * @arg @ref ADC_RESOLUTION_6B 2064 * 2065 * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.\n 2066 * (2) On STM32U5, parameter available only on ADC instance: ADC4.\n 2067 * @retval ADC conversion data full-scale digital value 2068 */ 2069 #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 2070 __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) 2071 2072 /** 2073 * @brief Helper macro to convert the ADC conversion data from 2074 * a resolution to another resolution. 2075 * @param __ADCx__ ADC instance 2076 * @param __DATA__ ADC conversion data to be converted 2077 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted 2078 * This parameter can be one of the following values: 2079 * @arg @ref ADC_RESOLUTION_14B (1) 2080 * @arg @ref ADC_RESOLUTION_12B (1)(2) 2081 * @arg @ref ADC_RESOLUTION_10B (1)(2) 2082 * @arg @ref ADC_RESOLUTION_8B (1)(2) 2083 * @arg @ref ADC_RESOLUTION_6B (2) 2084 * 2085 * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.\n 2086 * (2) On STM32U5, parameter available only on ADC instance: ADC4.\n 2087 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion 2088 * This parameter can be one of the following values: 2089 * @arg @ref ADC_RESOLUTION_14B (1) 2090 * @arg @ref ADC_RESOLUTION_12B (1)(2) 2091 * @arg @ref ADC_RESOLUTION_10B (1)(2) 2092 * @arg @ref ADC_RESOLUTION_8B (1)(2) 2093 * @arg @ref ADC_RESOLUTION_6B (2) 2094 * 2095 * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.\n 2096 * (2) On STM32U5, parameter available only on ADC instance: ADC4.\n 2097 * @retval ADC conversion data to the requested resolution 2098 */ 2099 #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__ADCx__, __DATA__,\ 2100 __ADC_RESOLUTION_CURRENT__,\ 2101 __ADC_RESOLUTION_TARGET__) \ 2102 __LL_ADC_CONVERT_DATA_RESOLUTION((__ADCx__), (__DATA__),\ 2103 (__ADC_RESOLUTION_CURRENT__),\ 2104 (__ADC_RESOLUTION_TARGET__)) 2105 2106 /** 2107 * @brief Helper macro to calculate the voltage (unit: mVolt) 2108 * corresponding to a ADC conversion data (unit: digital value). 2109 * @note Analog reference voltage (Vref+) must be either known from 2110 * user board environment or can be calculated using ADC measurement 2111 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 2112 * @param __ADCx__ ADC instance 2113 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 2114 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) 2115 * (unit: digital value). 2116 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 2117 * @arg @ref ADC_RESOLUTION_14B (1) 2118 * @arg @ref ADC_RESOLUTION_12B (1)(2) 2119 * @arg @ref ADC_RESOLUTION_10B (1)(2) 2120 * @arg @ref ADC_RESOLUTION_8B (1)(2) 2121 * @arg @ref ADC_RESOLUTION_6B (2) 2122 * 2123 * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.\n 2124 * (2) On STM32U5, parameter available only on ADC instance: ADC4.\n 2125 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 2126 */ 2127 #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__ADCx__, __VREFANALOG_VOLTAGE__, \ 2128 __ADC_DATA__, \ 2129 __ADC_RESOLUTION__) \ 2130 __LL_ADC_CALC_DATA_TO_VOLTAGE((__ADCx__), (__VREFANALOG_VOLTAGE__), \ 2131 (__ADC_DATA__), \ 2132 (__ADC_RESOLUTION__)) 2133 2134 /** 2135 * @brief Helper macro to calculate analog reference voltage (Vref+) 2136 * (unit: mVolt) from ADC conversion data of internal voltage 2137 * reference VrefInt. 2138 * @note Computation is using VrefInt calibration value 2139 * stored in system memory for each device during production. 2140 * @note This voltage depends on user board environment: voltage level 2141 * connected to pin Vref+. 2142 * On devices with small package, the pin Vref+ is not present 2143 * and internally bonded to pin Vdda. 2144 * @note On this STM32 series, calibration data of internal voltage reference 2145 * VrefInt corresponds to a resolution of 12 bits, 2146 * this is the recommended ADC resolution to convert voltage of 2147 * internal voltage reference VrefInt. 2148 * Otherwise, this macro performs the processing to scale 2149 * ADC conversion data to 12 bits. 2150 * @param __ADCx__ ADC instance 2151 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) 2152 * of internal voltage reference VrefInt (unit: digital value). 2153 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 2154 * @arg @ref ADC_RESOLUTION_14B (1) 2155 * @arg @ref ADC_RESOLUTION_12B (1)(2) 2156 * @arg @ref ADC_RESOLUTION_10B (1)(2) 2157 * @arg @ref ADC_RESOLUTION_8B (1)(2) 2158 * @arg @ref ADC_RESOLUTION_6B (2) 2159 * 2160 * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.\n 2161 * (2) On STM32U5, parameter available only on ADC instance: ADC4.\n 2162 * @retval Analog reference voltage (unit: mV) 2163 */ 2164 #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__ADCx__, __VREFINT_ADC_DATA__, \ 2165 __ADC_RESOLUTION__) \ 2166 __LL_ADC_CALC_VREFANALOG_VOLTAGE((__ADCx__),(__VREFINT_ADC_DATA__), \ 2167 (__ADC_RESOLUTION__)) 2168 2169 /** 2170 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 2171 * from ADC conversion data of internal temperature sensor. 2172 * @note Computation is using temperature sensor calibration values 2173 * stored in system memory for each device during production. 2174 * @note Calculation formula: 2175 * Temperature = ((TS_ADC_DATA - TS_CAL1) 2176 * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) 2177 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP 2178 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 2179 * Avg_Slope = (TS_CAL2 - TS_CAL1) 2180 * / (TS_CAL2_TEMP - TS_CAL1_TEMP) 2181 * TS_CAL1 = equivalent TS_ADC_DATA at temperature 2182 * TEMP_DEGC_CAL1 (calibrated in factory) 2183 * TS_CAL2 = equivalent TS_ADC_DATA at temperature 2184 * TEMP_DEGC_CAL2 (calibrated in factory) 2185 * Caution: Calculation relevancy under reserve that calibration 2186 * parameters are correct (address and data). 2187 * To calculate temperature using temperature sensor 2188 * datasheet typical values (generic values less, therefore 2189 * less accurate than calibrated values), 2190 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). 2191 * @note As calculation input, the analog reference voltage (Vref+) must be 2192 * defined as it impacts the ADC LSB equivalent voltage. 2193 * @note Analog reference voltage (Vref+) must be either known from 2194 * user board environment or can be calculated using ADC measurement 2195 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 2196 * @note On this STM32 series, calibration data of temperature sensor 2197 * corresponds to a resolution of 12 bits, 2198 * this is the recommended ADC resolution to convert voltage of 2199 * temperature sensor. 2200 * Otherwise, this macro performs the processing to scale 2201 * ADC conversion data to 12 bits. 2202 * @param __ADCx__ ADC instance 2203 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 2204 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal 2205 * temperature sensor (unit: digital value). 2206 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature 2207 * sensor voltage has been measured. 2208 * This parameter can be one of the following values: 2209 * @arg @ref ADC_RESOLUTION_14B (1) 2210 * @arg @ref ADC_RESOLUTION_12B (1)(2) 2211 * @arg @ref ADC_RESOLUTION_10B (1)(2) 2212 * @arg @ref ADC_RESOLUTION_8B (1)(2) 2213 * @arg @ref ADC_RESOLUTION_6B (2) 2214 * 2215 * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.\n 2216 * (2) On STM32U5, parameter available only on ADC instance: ADC4.\n 2217 * @retval Temperature (unit: degree Celsius) 2218 */ 2219 #define __HAL_ADC_CALC_TEMPERATURE(__ADCx__, __VREFANALOG_VOLTAGE__,\ 2220 __TEMPSENSOR_ADC_DATA__,\ 2221 __ADC_RESOLUTION__) \ 2222 __LL_ADC_CALC_TEMPERATURE((__ADCx__), (__VREFANALOG_VOLTAGE__),\ 2223 (__TEMPSENSOR_ADC_DATA__),\ 2224 (__ADC_RESOLUTION__)) 2225 2226 /** 2227 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 2228 * from ADC conversion data of internal temperature sensor. 2229 * @note Computation is using temperature sensor typical values 2230 * (refer to device datasheet). 2231 * @note Calculation formula: 2232 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) 2233 * / Avg_Slope + CALx_TEMP 2234 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 2235 * (unit: digital value) 2236 * Avg_Slope = temperature sensor slope 2237 * (unit: uV/Degree Celsius) 2238 * TS_TYP_CALx_VOLT = temperature sensor digital value at 2239 * temperature CALx_TEMP (unit: mV) 2240 * Caution: Calculation relevancy under reserve the temperature sensor 2241 * of the current device has characteristics in line with 2242 * datasheet typical values. 2243 * If temperature sensor calibration values are available on 2244 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), 2245 * temperature calculation will be more accurate using 2246 * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). 2247 * @note As calculation input, the analog reference voltage (Vref+) must be 2248 * defined as it impacts the ADC LSB equivalent voltage. 2249 * @note Analog reference voltage (Vref+) must be either known from 2250 * user board environment or can be calculated using ADC measurement 2251 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 2252 * @note ADC measurement data must correspond to a resolution of 12bits 2253 * (full scale digital value 4095). If not the case, the data must be 2254 * preliminarily rescaled to an equivalent resolution of 12 bits. 2255 * @param __ADCx__ ADC instance 2256 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value 2257 * (unit: uV/DegCelsius). 2258 * On STM32U5, refer to device datasheet parameter "Avg_Slope". 2259 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value 2260 * (at temperature and Vref+ defined in parameters below) (unit: mV). 2261 * Refer to device datasheet parameter "V30" (corresponding to TS_CAL1). 2262 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage 2263 * (see parameter above) is corresponding (unit: mV) 2264 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) 2265 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). 2266 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. 2267 * This parameter can be one of the following values: 2268 * @arg @ref ADC_RESOLUTION_14B (1) 2269 * @arg @ref ADC_RESOLUTION_12B (1)(2) 2270 * @arg @ref ADC_RESOLUTION_10B (1)(2) 2271 * @arg @ref ADC_RESOLUTION_8B (1)(2) 2272 * @arg @ref ADC_RESOLUTION_6B (2) 2273 * 2274 * (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.\n 2275 * (2) On STM32U5, parameter available only on ADC instance: ADC4.\n 2276 * @retval Temperature (unit: degree Celsius) 2277 */ 2278 #define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__ADCx__, __TEMPSENSOR_TYP_AVGSLOPE__,\ 2279 __TEMPSENSOR_TYP_CALX_V__,\ 2280 __TEMPSENSOR_CALX_TEMP__,\ 2281 __VREFANALOG_VOLTAGE__,\ 2282 __TEMPSENSOR_ADC_DATA__,\ 2283 __ADC_RESOLUTION__) \ 2284 __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__ADCx__), (__TEMPSENSOR_TYP_AVGSLOPE__),\ 2285 (__TEMPSENSOR_TYP_CALX_V__),\ 2286 (__TEMPSENSOR_CALX_TEMP__),\ 2287 (__VREFANALOG_VOLTAGE__),\ 2288 (__TEMPSENSOR_ADC_DATA__),\ 2289 (__ADC_RESOLUTION__)) 2290 2291 /** 2292 * @} 2293 */ 2294 2295 /** 2296 * @} 2297 */ 2298 2299 /* Include ADC HAL Extended module */ 2300 #include "stm32u5xx_hal_adc_ex.h" 2301 2302 /* Exported functions --------------------------------------------------------*/ 2303 /** @addtogroup ADC_Exported_Functions 2304 * @{ 2305 */ 2306 2307 /** @addtogroup ADC_Exported_Functions_Group1 2308 * @brief Initialization and Configuration functions 2309 * @{ 2310 */ 2311 /* Initialization and de-initialization functions ****************************/ 2312 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); 2313 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 2314 void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); 2315 void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); 2316 2317 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 2318 /* Callbacks Register/UnRegister functions ***********************************/ 2319 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, 2320 pADC_CallbackTypeDef pCallback); 2321 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); 2322 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 2323 /** 2324 * @} 2325 */ 2326 2327 /** @addtogroup ADC_Exported_Functions_Group2 2328 * @brief IO operation functions 2329 * @{ 2330 */ 2331 /* IO operation functions *****************************************************/ 2332 2333 /* Blocking mode: Polling */ 2334 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); 2335 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); 2336 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 2337 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); 2338 2339 /* Non-blocking mode: Interruption */ 2340 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); 2341 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); 2342 2343 /* Non-blocking mode: DMA */ 2344 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, const uint32_t *pData, uint32_t Length); 2345 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); 2346 2347 /* ADC retrieve conversion value intended to be used with polling or interruption */ 2348 uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc); 2349 2350 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ 2351 void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); 2352 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); 2353 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); 2354 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); 2355 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 2356 void HAL_ADC_CalibrationCpltCallback(ADC_HandleTypeDef *hadc); 2357 void HAL_ADC_VoltageRegulatorCallback(ADC_HandleTypeDef *hadc); 2358 void HAL_ADC_ADCReadyCallback(ADC_HandleTypeDef *hadc); 2359 /** 2360 * @} 2361 */ 2362 2363 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions 2364 * @brief Peripheral Control functions 2365 * @{ 2366 */ 2367 /* Peripheral Control functions ***********************************************/ 2368 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *pConfig); 2369 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig); 2370 2371 /** 2372 * @} 2373 */ 2374 2375 /* Peripheral State functions *************************************************/ 2376 /** @addtogroup ADC_Exported_Functions_Group4 2377 * @{ 2378 */ 2379 uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc); 2380 uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc); 2381 2382 /** 2383 * @} 2384 */ 2385 2386 /** 2387 * @} 2388 */ 2389 2390 /* Private functions -----------------------------------------------------------*/ 2391 /** @addtogroup ADC_Private_Functions ADC Private Functions 2392 * @{ 2393 */ 2394 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup); 2395 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc); 2396 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc); 2397 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); 2398 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); 2399 void ADC_DMAError(DMA_HandleTypeDef *hdma); 2400 void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc); 2401 2402 /** 2403 * @} 2404 */ 2405 /** 2406 * @} 2407 */ 2408 /** 2409 * @} 2410 */ 2411 2412 #ifdef __cplusplus 2413 } 2414 #endif 2415 2416 2417 #endif /* STM32U5xx_HAL_ADC_H */ 2418
