1 /****************************************************************************** 2 * Filename: hw_adc_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_ADC_H__ 34 #define __HW_ADC_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // ADC component 40 // 41 //***************************************************************************** 42 // Interrupt mask 43 #define ADC_O_IMASK0 0x00000028U 44 45 // Raw interrupt status 46 #define ADC_O_RIS0 0x00000030U 47 48 // Masked interrupt status 49 #define ADC_O_MIS0 0x00000038U 50 51 // Interrupt set 52 #define ADC_O_ISET0 0x00000040U 53 54 // Interrupt clear 55 #define ADC_O_ICLR0 0x00000048U 56 57 // Interrupt mask 58 #define ADC_O_IMASK1 0x00000058U 59 60 // Raw interrupt status 61 #define ADC_O_RIS1 0x00000060U 62 63 // Masked interrupt status 64 #define ADC_O_MIS1 0x00000068U 65 66 // Interrupt set 67 #define ADC_O_ISET1 0x00000070U 68 69 // Interrupt clear 70 #define ADC_O_ICLR1 0x00000078U 71 72 // Interrupt mask 73 #define ADC_O_IMASK2 0x00000088U 74 75 // Raw interrupt status 76 #define ADC_O_RIS2 0x00000090U 77 78 // Masked interrupt status 79 #define ADC_O_MIS2 0x00000098U 80 81 // Interrupt set 82 #define ADC_O_ISET2 0x000000A0U 83 84 // Interrupt clear 85 #define ADC_O_ICLR2 0x000000A8U 86 87 // Control Register 0 88 #define ADC_O_CTL0 0x00000100U 89 90 // Control Register 1 91 #define ADC_O_CTL1 0x00000104U 92 93 // Control Register 2 94 #define ADC_O_CTL2 0x00000108U 95 96 // Control Register 3 97 #define ADC_O_CTL3 0x0000010CU 98 99 // Sample Time Compare 0 Register 100 #define ADC_O_SCOMP0 0x00000114U 101 102 // Sample Time Compare 1 Register 103 #define ADC_O_SCOMP1 0x00000118U 104 105 // Reference Buffer Configuration Register 106 #define ADC_O_REFCFG 0x0000011CU 107 108 // Window Comparator Low Threshold Register 109 #define ADC_O_WCLOW 0x00000148U 110 111 // Window Comparator High Threshold Register 112 #define ADC_O_WCHIGH 0x00000150U 113 114 // FIFO Data Register 115 #define ADC_O_FIFODATA 0x00000160U 116 117 // ASC Result Register 118 #define ADC_O_ASCRES 0x00000170U 119 120 // Conversion Memory Control Register 0 121 #define ADC_O_MEMCTL0 0x00000180U 122 123 // Conversion Memory Control Register 1 124 #define ADC_O_MEMCTL1 0x00000184U 125 126 // Conversion Memory Control Register 2 127 #define ADC_O_MEMCTL2 0x00000188U 128 129 // Conversion Memory Control Register 3 130 #define ADC_O_MEMCTL3 0x0000018CU 131 132 // Memory Result Register 0 133 #define ADC_O_MEMRES0 0x00000280U 134 135 // Memory Result Register 1 136 #define ADC_O_MEMRES1 0x00000284U 137 138 // Memory Result Register 2 139 #define ADC_O_MEMRES2 0x00000288U 140 141 // Memory Result Register 3 142 #define ADC_O_MEMRES3 0x0000028CU 143 144 // Status Register 145 #define ADC_O_STA 0x00000340U 146 147 // Internal. Only to be used through TI provided API. 148 #define ADC_O_TEST0 0x00000E00U 149 150 // Internal. Only to be used through TI provided API. 151 #define ADC_O_TEST2 0x00000E08U 152 153 // Internal. Only to be used through TI provided API. 154 #define ADC_O_TEST3 0x00000E0CU 155 156 // Internal. Only to be used through TI provided API. 157 #define ADC_O_TEST4 0x00000E10U 158 159 // Internal. Only to be used through TI provided API. 160 #define ADC_O_TEST5 0x00000E14U 161 162 // Internal. Only to be used through TI provided API. 163 #define ADC_O_TEST6 0x00000E18U 164 165 // Internal. Only to be used through TI provided API. 166 #define ADC_O_DEBUG1 0x00000E20U 167 168 // Internal. Only to be used through TI provided API. 169 #define ADC_O_DEBUG2 0x00000E24U 170 171 // Internal. Only to be used through TI provided API. 172 #define ADC_O_DEBUG3 0x00000E28U 173 174 // Internal. Only to be used through TI provided API. 175 #define ADC_O_DEBUG4 0x00000E2CU 176 177 //***************************************************************************** 178 // 179 // Register: ADC_O_IMASK0 180 // 181 //***************************************************************************** 182 // Field: [11] MEMRESIFG3 183 // 184 // MEMRES3 conversion result interrupt mask. 185 // ENUMs: 186 // EN Enable interrupt mask 187 // DIS Disable interrupt mask 188 #define ADC_IMASK0_MEMRESIFG3 0x00000800U 189 #define ADC_IMASK0_MEMRESIFG3_M 0x00000800U 190 #define ADC_IMASK0_MEMRESIFG3_S 11U 191 #define ADC_IMASK0_MEMRESIFG3_EN 0x00000800U 192 #define ADC_IMASK0_MEMRESIFG3_DIS 0x00000000U 193 194 // Field: [10] MEMRESIFG2 195 // 196 // MEMRES2 conversion result interrupt mask. 197 // ENUMs: 198 // EN Enable interrupt mask 199 // DIS Disable interrupt mask 200 #define ADC_IMASK0_MEMRESIFG2 0x00000400U 201 #define ADC_IMASK0_MEMRESIFG2_M 0x00000400U 202 #define ADC_IMASK0_MEMRESIFG2_S 10U 203 #define ADC_IMASK0_MEMRESIFG2_EN 0x00000400U 204 #define ADC_IMASK0_MEMRESIFG2_DIS 0x00000000U 205 206 // Field: [9] MEMRESIFG1 207 // 208 // MEMRES1 conversion result interrupt mask. 209 // ENUMs: 210 // EN Enable interrupt mask 211 // DIS Disable interrupt mask 212 #define ADC_IMASK0_MEMRESIFG1 0x00000200U 213 #define ADC_IMASK0_MEMRESIFG1_M 0x00000200U 214 #define ADC_IMASK0_MEMRESIFG1_S 9U 215 #define ADC_IMASK0_MEMRESIFG1_EN 0x00000200U 216 #define ADC_IMASK0_MEMRESIFG1_DIS 0x00000000U 217 218 // Field: [8] MEMRESIFG0 219 // 220 // MEMRES0 conversion result interrupt mask. 221 // ENUMs: 222 // EN Enable interrupt mask 223 // DIS Disable interrupt mask 224 #define ADC_IMASK0_MEMRESIFG0 0x00000100U 225 #define ADC_IMASK0_MEMRESIFG0_M 0x00000100U 226 #define ADC_IMASK0_MEMRESIFG0_S 8U 227 #define ADC_IMASK0_MEMRESIFG0_EN 0x00000100U 228 #define ADC_IMASK0_MEMRESIFG0_DIS 0x00000000U 229 230 // Field: [7] ASCDONE 231 // 232 // Mask for ASC done raw interrupt flag. 233 // ENUMs: 234 // EN Enable interrupt mask 235 // DIS Disable interrupt mask 236 #define ADC_IMASK0_ASCDONE 0x00000080U 237 #define ADC_IMASK0_ASCDONE_M 0x00000080U 238 #define ADC_IMASK0_ASCDONE_S 7U 239 #define ADC_IMASK0_ASCDONE_EN 0x00000080U 240 #define ADC_IMASK0_ASCDONE_DIS 0x00000000U 241 242 // Field: [6] UVIFG 243 // 244 // Conversion underflow interrupt mask. 245 // ENUMs: 246 // EN Enable interrupt mask 247 // DIS Disable interrupt mask 248 #define ADC_IMASK0_UVIFG 0x00000040U 249 #define ADC_IMASK0_UVIFG_M 0x00000040U 250 #define ADC_IMASK0_UVIFG_S 6U 251 #define ADC_IMASK0_UVIFG_EN 0x00000040U 252 #define ADC_IMASK0_UVIFG_DIS 0x00000000U 253 254 // Field: [5] DMADONE 255 // 256 // DMA done interrupt mask. 257 // ENUMs: 258 // EN Enable interrupt mask 259 // DIS Disable interrupt mask 260 #define ADC_IMASK0_DMADONE 0x00000020U 261 #define ADC_IMASK0_DMADONE_M 0x00000020U 262 #define ADC_IMASK0_DMADONE_S 5U 263 #define ADC_IMASK0_DMADONE_EN 0x00000020U 264 #define ADC_IMASK0_DMADONE_DIS 0x00000000U 265 266 // Field: [4] INIFG 267 // 268 // In-range comparator interrupt mask. 269 // ENUMs: 270 // EN Enable interrupt mask 271 // DIS Disable interrupt mask 272 #define ADC_IMASK0_INIFG 0x00000010U 273 #define ADC_IMASK0_INIFG_M 0x00000010U 274 #define ADC_IMASK0_INIFG_S 4U 275 #define ADC_IMASK0_INIFG_EN 0x00000010U 276 #define ADC_IMASK0_INIFG_DIS 0x00000000U 277 278 // Field: [3] LOWIFG 279 // 280 // Low threshold compare interrupt mask. 281 // ENUMs: 282 // EN Enable interrupt mask 283 // DIS Disable interrupt mask 284 #define ADC_IMASK0_LOWIFG 0x00000008U 285 #define ADC_IMASK0_LOWIFG_M 0x00000008U 286 #define ADC_IMASK0_LOWIFG_S 3U 287 #define ADC_IMASK0_LOWIFG_EN 0x00000008U 288 #define ADC_IMASK0_LOWIFG_DIS 0x00000000U 289 290 // Field: [2] HIGHIFG 291 // 292 // High threshold compare interrupt mask. 293 // ENUMs: 294 // EN Enable interrupt mask 295 // DIS Disable interrupt mask 296 #define ADC_IMASK0_HIGHIFG 0x00000004U 297 #define ADC_IMASK0_HIGHIFG_M 0x00000004U 298 #define ADC_IMASK0_HIGHIFG_S 2U 299 #define ADC_IMASK0_HIGHIFG_EN 0x00000004U 300 #define ADC_IMASK0_HIGHIFG_DIS 0x00000000U 301 302 // Field: [1] TOVIFG 303 // 304 // Sequence conversion time overflow interrupt mask. 305 // ENUMs: 306 // EN Enable interrupt mask 307 // DIS Disable interrupt mask 308 #define ADC_IMASK0_TOVIFG 0x00000002U 309 #define ADC_IMASK0_TOVIFG_M 0x00000002U 310 #define ADC_IMASK0_TOVIFG_S 1U 311 #define ADC_IMASK0_TOVIFG_EN 0x00000002U 312 #define ADC_IMASK0_TOVIFG_DIS 0x00000000U 313 314 // Field: [0] OVIFG 315 // 316 // Conversion overflow interrupt mask. 317 // ENUMs: 318 // EN Enable interrupt mask 319 // DIS Disable interrupt mask 320 #define ADC_IMASK0_OVIFG 0x00000001U 321 #define ADC_IMASK0_OVIFG_M 0x00000001U 322 #define ADC_IMASK0_OVIFG_S 0U 323 #define ADC_IMASK0_OVIFG_EN 0x00000001U 324 #define ADC_IMASK0_OVIFG_DIS 0x00000000U 325 326 //***************************************************************************** 327 // 328 // Register: ADC_O_RIS0 329 // 330 //***************************************************************************** 331 // Field: [11] MEMRESIFG3 332 // 333 // Raw interrupt status for MEMRES3. 334 // This bit is set to 1 when MEMRES3 is loaded with a new 335 // conversion result. 336 // Reading MEMRES3 register will clear this bit, or when the 337 // corresponding bit in ICLR0 is set to 1 338 // ENUMs: 339 // SET A new data is ready to be read. 340 // CLR No new data ready. 341 #define ADC_RIS0_MEMRESIFG3 0x00000800U 342 #define ADC_RIS0_MEMRESIFG3_M 0x00000800U 343 #define ADC_RIS0_MEMRESIFG3_S 11U 344 #define ADC_RIS0_MEMRESIFG3_SET 0x00000800U 345 #define ADC_RIS0_MEMRESIFG3_CLR 0x00000000U 346 347 // Field: [10] MEMRESIFG2 348 // 349 // Raw interrupt status for MEMRES2. 350 // This bit is set to 1 when MEMRES2 is loaded with a new 351 // conversion result. 352 // Reading MEMRES2 register will clear this bit, or when the 353 // corresponding bit in ICLR0 is set to 1 354 // ENUMs: 355 // SET A new data is ready to be read. 356 // CLR No new data ready. 357 #define ADC_RIS0_MEMRESIFG2 0x00000400U 358 #define ADC_RIS0_MEMRESIFG2_M 0x00000400U 359 #define ADC_RIS0_MEMRESIFG2_S 10U 360 #define ADC_RIS0_MEMRESIFG2_SET 0x00000400U 361 #define ADC_RIS0_MEMRESIFG2_CLR 0x00000000U 362 363 // Field: [9] MEMRESIFG1 364 // 365 // Raw interrupt status for MEMRES1. 366 // This bit is set to 1 when MEMRES1 is loaded with a new 367 // conversion result. 368 // Reading MEMRES1 register will clear this bit, or when the 369 // corresponding bit in ICLR0 is set to 1 370 // ENUMs: 371 // SET A new data is ready to be read. 372 // CLR No new data ready. 373 #define ADC_RIS0_MEMRESIFG1 0x00000200U 374 #define ADC_RIS0_MEMRESIFG1_M 0x00000200U 375 #define ADC_RIS0_MEMRESIFG1_S 9U 376 #define ADC_RIS0_MEMRESIFG1_SET 0x00000200U 377 #define ADC_RIS0_MEMRESIFG1_CLR 0x00000000U 378 379 // Field: [8] MEMRESIFG0 380 // 381 // Raw interrupt status for MEMRES0. 382 // This bit is set to 1 when MEMRES0 is loaded with a new 383 // conversion result. 384 // Reading MEMRES0 register will clear this bit, or when the 385 // corresponding bit in ICLR0 is set to 1 386 // ENUMs: 387 // SET A new data is ready to be read. 388 // CLR No new data ready. 389 #define ADC_RIS0_MEMRESIFG0 0x00000100U 390 #define ADC_RIS0_MEMRESIFG0_M 0x00000100U 391 #define ADC_RIS0_MEMRESIFG0_S 8U 392 #define ADC_RIS0_MEMRESIFG0_SET 0x00000100U 393 #define ADC_RIS0_MEMRESIFG0_CLR 0x00000000U 394 395 // Field: [7] ASCDONE 396 // 397 // Raw interrupt flag for ASC done. 398 // ENUMs: 399 // SET Interrupt is pending. 400 // CLR Interrupt is not pending. 401 #define ADC_RIS0_ASCDONE 0x00000080U 402 #define ADC_RIS0_ASCDONE_M 0x00000080U 403 #define ADC_RIS0_ASCDONE_S 7U 404 #define ADC_RIS0_ASCDONE_SET 0x00000080U 405 #define ADC_RIS0_ASCDONE_CLR 0x00000000U 406 407 // Field: [6] UVIFG 408 // 409 // Raw interrupt flag for MEMRESx underflow. 410 // ENUMs: 411 // SET Interrupt is pending. 412 // CLR Interrupt is not pending. 413 #define ADC_RIS0_UVIFG 0x00000040U 414 #define ADC_RIS0_UVIFG_M 0x00000040U 415 #define ADC_RIS0_UVIFG_S 6U 416 #define ADC_RIS0_UVIFG_SET 0x00000040U 417 #define ADC_RIS0_UVIFG_CLR 0x00000000U 418 419 // Field: [5] DMADONE 420 // 421 // Raw interrupt flag for DMADONE. 422 // ENUMs: 423 // SET Interrupt is pending. 424 // CLR Interrupt is not pending. 425 #define ADC_RIS0_DMADONE 0x00000020U 426 #define ADC_RIS0_DMADONE_M 0x00000020U 427 #define ADC_RIS0_DMADONE_S 5U 428 #define ADC_RIS0_DMADONE_SET 0x00000020U 429 #define ADC_RIS0_DMADONE_CLR 0x00000000U 430 431 // Field: [4] INIFG 432 // 433 // Raw interrupt status for In-range comparator. 434 // ENUMs: 435 // SET Interrupt is pending. 436 // CLR Interrupt is not pending. 437 #define ADC_RIS0_INIFG 0x00000010U 438 #define ADC_RIS0_INIFG_M 0x00000010U 439 #define ADC_RIS0_INIFG_S 4U 440 #define ADC_RIS0_INIFG_SET 0x00000010U 441 #define ADC_RIS0_INIFG_CLR 0x00000000U 442 443 // Field: [3] LOWIFG 444 // 445 // Raw interrupt flag for the MEMRESx result register being below than the 446 // WCLOWx threshold of the window comparator. 447 // ENUMs: 448 // SET Interrupt is pending. 449 // CLR Interrupt is not pending. 450 #define ADC_RIS0_LOWIFG 0x00000008U 451 #define ADC_RIS0_LOWIFG_M 0x00000008U 452 #define ADC_RIS0_LOWIFG_S 3U 453 #define ADC_RIS0_LOWIFG_SET 0x00000008U 454 #define ADC_RIS0_LOWIFG_CLR 0x00000000U 455 456 // Field: [2] HIGHIFG 457 // 458 // Raw interrupt flag for the MEMRESx result register being higher than the 459 // WCHIGHx threshold of the window comparator. 460 // ENUMs: 461 // SET Interrupt is pending. 462 // CLR Interrupt is not pending. 463 #define ADC_RIS0_HIGHIFG 0x00000004U 464 #define ADC_RIS0_HIGHIFG_M 0x00000004U 465 #define ADC_RIS0_HIGHIFG_S 2U 466 #define ADC_RIS0_HIGHIFG_SET 0x00000004U 467 #define ADC_RIS0_HIGHIFG_CLR 0x00000000U 468 469 // Field: [1] TOVIFG 470 // 471 // Raw interrupt flag for sequence conversion trigger overflow. 472 // ENUMs: 473 // SET Interrupt is pending. 474 // CLR Interrupt is not pending. 475 #define ADC_RIS0_TOVIFG 0x00000002U 476 #define ADC_RIS0_TOVIFG_M 0x00000002U 477 #define ADC_RIS0_TOVIFG_S 1U 478 #define ADC_RIS0_TOVIFG_SET 0x00000002U 479 #define ADC_RIS0_TOVIFG_CLR 0x00000000U 480 481 // Field: [0] OVIFG 482 // 483 // Raw interrupt flag for MEMRESx overflow. 484 // ENUMs: 485 // SET Interrupt is pending. 486 // CLR Interrupt is not pending. 487 #define ADC_RIS0_OVIFG 0x00000001U 488 #define ADC_RIS0_OVIFG_M 0x00000001U 489 #define ADC_RIS0_OVIFG_S 0U 490 #define ADC_RIS0_OVIFG_SET 0x00000001U 491 #define ADC_RIS0_OVIFG_CLR 0x00000000U 492 493 //***************************************************************************** 494 // 495 // Register: ADC_O_MIS0 496 // 497 //***************************************************************************** 498 // Field: [11] MEMRESIFG3 499 // 500 // Masked interrupt status for MEMRES3. 501 // ENUMs: 502 // SET A new data is ready to be read. 503 // CLR No new data ready. 504 #define ADC_MIS0_MEMRESIFG3 0x00000800U 505 #define ADC_MIS0_MEMRESIFG3_M 0x00000800U 506 #define ADC_MIS0_MEMRESIFG3_S 11U 507 #define ADC_MIS0_MEMRESIFG3_SET 0x00000800U 508 #define ADC_MIS0_MEMRESIFG3_CLR 0x00000000U 509 510 // Field: [10] MEMRESIFG2 511 // 512 // Masked interrupt status for MEMRES2. 513 // ENUMs: 514 // SET A new data is ready to be read. 515 // CLR No new data ready. 516 #define ADC_MIS0_MEMRESIFG2 0x00000400U 517 #define ADC_MIS0_MEMRESIFG2_M 0x00000400U 518 #define ADC_MIS0_MEMRESIFG2_S 10U 519 #define ADC_MIS0_MEMRESIFG2_SET 0x00000400U 520 #define ADC_MIS0_MEMRESIFG2_CLR 0x00000000U 521 522 // Field: [9] MEMRESIFG1 523 // 524 // Masked interrupt status for MEMRES1. 525 // ENUMs: 526 // SET A new data is ready to be read. 527 // CLR No new data ready. 528 #define ADC_MIS0_MEMRESIFG1 0x00000200U 529 #define ADC_MIS0_MEMRESIFG1_M 0x00000200U 530 #define ADC_MIS0_MEMRESIFG1_S 9U 531 #define ADC_MIS0_MEMRESIFG1_SET 0x00000200U 532 #define ADC_MIS0_MEMRESIFG1_CLR 0x00000000U 533 534 // Field: [8] MEMRESIFG0 535 // 536 // Masked interrupt status for MEMRES0. 537 // ENUMs: 538 // SET A new data is ready to be read. 539 // CLR No new data ready. 540 #define ADC_MIS0_MEMRESIFG0 0x00000100U 541 #define ADC_MIS0_MEMRESIFG0_M 0x00000100U 542 #define ADC_MIS0_MEMRESIFG0_S 8U 543 #define ADC_MIS0_MEMRESIFG0_SET 0x00000100U 544 #define ADC_MIS0_MEMRESIFG0_CLR 0x00000000U 545 546 // Field: [7] ASCDONE 547 // 548 // Masked interrupt status for ASC done. 549 // ENUMs: 550 // SET Interrupt is pending. 551 // CLR Interrupt is not pending. 552 #define ADC_MIS0_ASCDONE 0x00000080U 553 #define ADC_MIS0_ASCDONE_M 0x00000080U 554 #define ADC_MIS0_ASCDONE_S 7U 555 #define ADC_MIS0_ASCDONE_SET 0x00000080U 556 #define ADC_MIS0_ASCDONE_CLR 0x00000000U 557 558 // Field: [6] UVIFG 559 // 560 // Masked interrupt flag for MEMRESx underflow. 561 // ENUMs: 562 // SET Interrupt is pending. 563 // CLR Interrupt is not pending. 564 #define ADC_MIS0_UVIFG 0x00000040U 565 #define ADC_MIS0_UVIFG_M 0x00000040U 566 #define ADC_MIS0_UVIFG_S 6U 567 #define ADC_MIS0_UVIFG_SET 0x00000040U 568 #define ADC_MIS0_UVIFG_CLR 0x00000000U 569 570 // Field: [5] DMADONE 571 // 572 // Masked interrupt flag for DMADONE. 573 // ENUMs: 574 // SET Interrupt is pending. 575 // CLR Interrupt is not pending. 576 #define ADC_MIS0_DMADONE 0x00000020U 577 #define ADC_MIS0_DMADONE_M 0x00000020U 578 #define ADC_MIS0_DMADONE_S 5U 579 #define ADC_MIS0_DMADONE_SET 0x00000020U 580 #define ADC_MIS0_DMADONE_CLR 0x00000000U 581 582 // Field: [4] INIFG 583 // 584 // Mask INIFG in MIS0 register. 585 // ENUMs: 586 // SET Interrupt is pending. 587 // CLR Interrupt is not pending. 588 #define ADC_MIS0_INIFG 0x00000010U 589 #define ADC_MIS0_INIFG_M 0x00000010U 590 #define ADC_MIS0_INIFG_S 4U 591 #define ADC_MIS0_INIFG_SET 0x00000010U 592 #define ADC_MIS0_INIFG_CLR 0x00000000U 593 594 // Field: [3] LOWIFG 595 // 596 // Masked interrupt flag for the MEMRESx result register being below than the 597 // WCLOWx threshold of the window comparator. 598 // ENUMs: 599 // SET Interrupt is pending. 600 // CLR Interrupt is not pending. 601 #define ADC_MIS0_LOWIFG 0x00000008U 602 #define ADC_MIS0_LOWIFG_M 0x00000008U 603 #define ADC_MIS0_LOWIFG_S 3U 604 #define ADC_MIS0_LOWIFG_SET 0x00000008U 605 #define ADC_MIS0_LOWIFG_CLR 0x00000000U 606 607 // Field: [2] HIGHIFG 608 // 609 // Masked interrupt flag for the MEMRESx result register being higher than the 610 // WCHIGHx threshold of the window comparator. 611 // ENUMs: 612 // SET Interrupt is pending. 613 // CLR Interrupt is not pending. 614 #define ADC_MIS0_HIGHIFG 0x00000004U 615 #define ADC_MIS0_HIGHIFG_M 0x00000004U 616 #define ADC_MIS0_HIGHIFG_S 2U 617 #define ADC_MIS0_HIGHIFG_SET 0x00000004U 618 #define ADC_MIS0_HIGHIFG_CLR 0x00000000U 619 620 // Field: [1] TOVIFG 621 // 622 // Masked interrupt flag for sequence conversion timeout overflow. 623 // ENUMs: 624 // SET Interrupt is pending. 625 // CLR Interrupt is not pending. 626 #define ADC_MIS0_TOVIFG 0x00000002U 627 #define ADC_MIS0_TOVIFG_M 0x00000002U 628 #define ADC_MIS0_TOVIFG_S 1U 629 #define ADC_MIS0_TOVIFG_SET 0x00000002U 630 #define ADC_MIS0_TOVIFG_CLR 0x00000000U 631 632 // Field: [0] OVIFG 633 // 634 // Masked interrupt flag for MEMRESx overflow. 635 // ENUMs: 636 // SET Interrupt is pending. 637 // CLR Interrupt is not pending. 638 #define ADC_MIS0_OVIFG 0x00000001U 639 #define ADC_MIS0_OVIFG_M 0x00000001U 640 #define ADC_MIS0_OVIFG_S 0U 641 #define ADC_MIS0_OVIFG_SET 0x00000001U 642 #define ADC_MIS0_OVIFG_CLR 0x00000000U 643 644 //***************************************************************************** 645 // 646 // Register: ADC_O_ISET0 647 // 648 //***************************************************************************** 649 // Field: [11] MEMRESIFG3 650 // 651 // Set interrupt status for MEMRES3. 652 // ENUMs: 653 // SET A new data is ready to be read. 654 // NO_EFFECT No new data ready. 655 #define ADC_ISET0_MEMRESIFG3 0x00000800U 656 #define ADC_ISET0_MEMRESIFG3_M 0x00000800U 657 #define ADC_ISET0_MEMRESIFG3_S 11U 658 #define ADC_ISET0_MEMRESIFG3_SET 0x00000800U 659 #define ADC_ISET0_MEMRESIFG3_NO_EFFECT 0x00000000U 660 661 // Field: [10] MEMRESIFG2 662 // 663 // Set interrupt status for MEMRES2. 664 // ENUMs: 665 // SET A new data is ready to be read. 666 // NO_EFFECT No new data ready. 667 #define ADC_ISET0_MEMRESIFG2 0x00000400U 668 #define ADC_ISET0_MEMRESIFG2_M 0x00000400U 669 #define ADC_ISET0_MEMRESIFG2_S 10U 670 #define ADC_ISET0_MEMRESIFG2_SET 0x00000400U 671 #define ADC_ISET0_MEMRESIFG2_NO_EFFECT 0x00000000U 672 673 // Field: [9] MEMRESIFG1 674 // 675 // Set interrupt status for MEMRES1. 676 // ENUMs: 677 // SET A new data is ready to be read. 678 // NO_EFFECT No new data ready. 679 #define ADC_ISET0_MEMRESIFG1 0x00000200U 680 #define ADC_ISET0_MEMRESIFG1_M 0x00000200U 681 #define ADC_ISET0_MEMRESIFG1_S 9U 682 #define ADC_ISET0_MEMRESIFG1_SET 0x00000200U 683 #define ADC_ISET0_MEMRESIFG1_NO_EFFECT 0x00000000U 684 685 // Field: [8] MEMRESIFG0 686 // 687 // Set Interrupt status for MEMRES0. 688 // ENUMs: 689 // SET A new data is ready to be read. 690 // NO_EFFECT No new data ready. 691 #define ADC_ISET0_MEMRESIFG0 0x00000100U 692 #define ADC_ISET0_MEMRESIFG0_M 0x00000100U 693 #define ADC_ISET0_MEMRESIFG0_S 8U 694 #define ADC_ISET0_MEMRESIFG0_SET 0x00000100U 695 #define ADC_ISET0_MEMRESIFG0_NO_EFFECT 0x00000000U 696 697 // Field: [7] ASCDONE 698 // 699 // Set interrupt for ASC done. 700 // ENUMs: 701 // SET Interrupt is pending. 702 // NO_EFFECT Interrupt is not pending. 703 #define ADC_ISET0_ASCDONE 0x00000080U 704 #define ADC_ISET0_ASCDONE_M 0x00000080U 705 #define ADC_ISET0_ASCDONE_S 7U 706 #define ADC_ISET0_ASCDONE_SET 0x00000080U 707 #define ADC_ISET0_ASCDONE_NO_EFFECT 0x00000000U 708 709 // Field: [6] UVIFG 710 // 711 // Set interrupt for MEMRESx underflow. 712 // ENUMs: 713 // SET Interrupt is pending. 714 // NO_EFFECT Interrupt is not pending. 715 #define ADC_ISET0_UVIFG 0x00000040U 716 #define ADC_ISET0_UVIFG_M 0x00000040U 717 #define ADC_ISET0_UVIFG_S 6U 718 #define ADC_ISET0_UVIFG_SET 0x00000040U 719 #define ADC_ISET0_UVIFG_NO_EFFECT 0x00000000U 720 721 // Field: [5] DMADONE 722 // 723 // Set interrupt for DMADONE. 724 // ENUMs: 725 // SET Interrupt is pending. 726 // NO_EFFECT Interrupt is not pending. 727 #define ADC_ISET0_DMADONE 0x00000020U 728 #define ADC_ISET0_DMADONE_M 0x00000020U 729 #define ADC_ISET0_DMADONE_S 5U 730 #define ADC_ISET0_DMADONE_SET 0x00000020U 731 #define ADC_ISET0_DMADONE_NO_EFFECT 0x00000000U 732 733 // Field: [4] INIFG 734 // 735 // Set INIFG interrupt register. 736 // ENUMs: 737 // SET Interrupt is pending. 738 // NO_EFFECT Interrupt is not pending. 739 #define ADC_ISET0_INIFG 0x00000010U 740 #define ADC_ISET0_INIFG_M 0x00000010U 741 #define ADC_ISET0_INIFG_S 4U 742 #define ADC_ISET0_INIFG_SET 0x00000010U 743 #define ADC_ISET0_INIFG_NO_EFFECT 0x00000000U 744 745 // Field: [3] LOWIFG 746 // 747 // Set interrupt for MEMRESx result register being below than the WCLOWx 748 // threshold of the window comparator. 749 // ENUMs: 750 // SET Interrupt is pending. 751 // NO_EFFECT Interrupt is not pending. 752 #define ADC_ISET0_LOWIFG 0x00000008U 753 #define ADC_ISET0_LOWIFG_M 0x00000008U 754 #define ADC_ISET0_LOWIFG_S 3U 755 #define ADC_ISET0_LOWIFG_SET 0x00000008U 756 #define ADC_ISET0_LOWIFG_NO_EFFECT 0x00000000U 757 758 // Field: [2] HIGHIFG 759 // 760 // Set Interrupt for the MEMRESx result register being higher than the WCHIGHx 761 // threshold of the window comparator. 762 // ENUMs: 763 // SET Interrupt is pending. 764 // NO_EFFECT Interrupt is not pending. 765 #define ADC_ISET0_HIGHIFG 0x00000004U 766 #define ADC_ISET0_HIGHIFG_M 0x00000004U 767 #define ADC_ISET0_HIGHIFG_S 2U 768 #define ADC_ISET0_HIGHIFG_SET 0x00000004U 769 #define ADC_ISET0_HIGHIFG_NO_EFFECT 0x00000000U 770 771 // Field: [1] TOVIFG 772 // 773 // Set interrupt for sequence conversion timeout overflow. 774 // ENUMs: 775 // SET Interrupt is pending. 776 // NO_EFFECT Interrupt is not pending. 777 #define ADC_ISET0_TOVIFG 0x00000002U 778 #define ADC_ISET0_TOVIFG_M 0x00000002U 779 #define ADC_ISET0_TOVIFG_S 1U 780 #define ADC_ISET0_TOVIFG_SET 0x00000002U 781 #define ADC_ISET0_TOVIFG_NO_EFFECT 0x00000000U 782 783 // Field: [0] OVIFG 784 // 785 // Set Interrupt for MEMRESx overflow. 786 // ENUMs: 787 // SET Interrupt is pending. 788 // NO_EFFECT Interrupt is not pending. 789 #define ADC_ISET0_OVIFG 0x00000001U 790 #define ADC_ISET0_OVIFG_M 0x00000001U 791 #define ADC_ISET0_OVIFG_S 0U 792 #define ADC_ISET0_OVIFG_SET 0x00000001U 793 #define ADC_ISET0_OVIFG_NO_EFFECT 0x00000000U 794 795 //***************************************************************************** 796 // 797 // Register: ADC_O_ICLR0 798 // 799 //***************************************************************************** 800 // Field: [11] MEMRESIFG3 801 // 802 // Clear interrupt status for MEMRES3. 803 // ENUMs: 804 // CLR A new data is ready to be read. 805 // NO_EFFECT No new data ready. 806 #define ADC_ICLR0_MEMRESIFG3 0x00000800U 807 #define ADC_ICLR0_MEMRESIFG3_M 0x00000800U 808 #define ADC_ICLR0_MEMRESIFG3_S 11U 809 #define ADC_ICLR0_MEMRESIFG3_CLR 0x00000800U 810 #define ADC_ICLR0_MEMRESIFG3_NO_EFFECT 0x00000000U 811 812 // Field: [10] MEMRESIFG2 813 // 814 // Clear interrupt status for MEMRES2. 815 // ENUMs: 816 // CLR A new data is ready to be read. 817 // NO_EFFECT No new data ready. 818 #define ADC_ICLR0_MEMRESIFG2 0x00000400U 819 #define ADC_ICLR0_MEMRESIFG2_M 0x00000400U 820 #define ADC_ICLR0_MEMRESIFG2_S 10U 821 #define ADC_ICLR0_MEMRESIFG2_CLR 0x00000400U 822 #define ADC_ICLR0_MEMRESIFG2_NO_EFFECT 0x00000000U 823 824 // Field: [9] MEMRESIFG1 825 // 826 // Clear interrupt status for MEMRES1. 827 // ENUMs: 828 // CLR A new data is ready to be read. 829 // NO_EFFECT No new data ready. 830 #define ADC_ICLR0_MEMRESIFG1 0x00000200U 831 #define ADC_ICLR0_MEMRESIFG1_M 0x00000200U 832 #define ADC_ICLR0_MEMRESIFG1_S 9U 833 #define ADC_ICLR0_MEMRESIFG1_CLR 0x00000200U 834 #define ADC_ICLR0_MEMRESIFG1_NO_EFFECT 0x00000000U 835 836 // Field: [8] MEMRESIFG0 837 // 838 // Clear interrupt status for MEMRES0. 839 // ENUMs: 840 // CLR A new data is ready to be read. 841 // NO_EFFECT No new data ready. 842 #define ADC_ICLR0_MEMRESIFG0 0x00000100U 843 #define ADC_ICLR0_MEMRESIFG0_M 0x00000100U 844 #define ADC_ICLR0_MEMRESIFG0_S 8U 845 #define ADC_ICLR0_MEMRESIFG0_CLR 0x00000100U 846 #define ADC_ICLR0_MEMRESIFG0_NO_EFFECT 0x00000000U 847 848 // Field: [7] ASCDONE 849 // 850 // Clear ASC done flag in RIS. 851 // ENUMs: 852 // CLR Interrupt is pending. 853 // NO_EFFECT Interrupt is not pending. 854 #define ADC_ICLR0_ASCDONE 0x00000080U 855 #define ADC_ICLR0_ASCDONE_M 0x00000080U 856 #define ADC_ICLR0_ASCDONE_S 7U 857 #define ADC_ICLR0_ASCDONE_CLR 0x00000080U 858 #define ADC_ICLR0_ASCDONE_NO_EFFECT 0x00000000U 859 860 // Field: [6] UVIFG 861 // 862 // Clear interrupt flag for MEMRESx underflow. 863 // ENUMs: 864 // CLR Interrupt is pending. 865 // NO_EFFECT Interrupt is not pending. 866 #define ADC_ICLR0_UVIFG 0x00000040U 867 #define ADC_ICLR0_UVIFG_M 0x00000040U 868 #define ADC_ICLR0_UVIFG_S 6U 869 #define ADC_ICLR0_UVIFG_CLR 0x00000040U 870 #define ADC_ICLR0_UVIFG_NO_EFFECT 0x00000000U 871 872 // Field: [5] DMADONE 873 // 874 // Clear interrupt flag for DMADONE. 875 // ENUMs: 876 // CLR Interrupt is pending. 877 // NO_EFFECT Interrupt is not pending. 878 #define ADC_ICLR0_DMADONE 0x00000020U 879 #define ADC_ICLR0_DMADONE_M 0x00000020U 880 #define ADC_ICLR0_DMADONE_S 5U 881 #define ADC_ICLR0_DMADONE_CLR 0x00000020U 882 #define ADC_ICLR0_DMADONE_NO_EFFECT 0x00000000U 883 884 // Field: [4] INIFG 885 // 886 // Clear INIFG in MIS0 register. 887 // ENUMs: 888 // CLR Interrupt is pending. 889 // NO_EFFECT Interrupt is not pending. 890 #define ADC_ICLR0_INIFG 0x00000010U 891 #define ADC_ICLR0_INIFG_M 0x00000010U 892 #define ADC_ICLR0_INIFG_S 4U 893 #define ADC_ICLR0_INIFG_CLR 0x00000010U 894 #define ADC_ICLR0_INIFG_NO_EFFECT 0x00000000U 895 896 // Field: [3] LOWIFG 897 // 898 // Clear interrupt flag for the MEMRESx result register being below than the 899 // WCLOWx threshold of the window comparator. 900 // ENUMs: 901 // CLR Interrupt is pending. 902 // NO_EFFECT Interrupt is not pending. 903 #define ADC_ICLR0_LOWIFG 0x00000008U 904 #define ADC_ICLR0_LOWIFG_M 0x00000008U 905 #define ADC_ICLR0_LOWIFG_S 3U 906 #define ADC_ICLR0_LOWIFG_CLR 0x00000008U 907 #define ADC_ICLR0_LOWIFG_NO_EFFECT 0x00000000U 908 909 // Field: [2] HIGHIFG 910 // 911 // Clear interrupt flag for the MEMRESx result register being higher than the 912 // WCHIGHx threshold of the window comparator. 913 // ENUMs: 914 // CLR Interrupt is pending. 915 // NO_EFFECT Interrupt is not pending. 916 #define ADC_ICLR0_HIGHIFG 0x00000004U 917 #define ADC_ICLR0_HIGHIFG_M 0x00000004U 918 #define ADC_ICLR0_HIGHIFG_S 2U 919 #define ADC_ICLR0_HIGHIFG_CLR 0x00000004U 920 #define ADC_ICLR0_HIGHIFG_NO_EFFECT 0x00000000U 921 922 // Field: [1] TOVIFG 923 // 924 // Clear interrupt flag for sequence conversion timeout overflow. 925 // ENUMs: 926 // CLR Interrupt is pending. 927 // NO_EFFECT Interrupt is not pending. 928 #define ADC_ICLR0_TOVIFG 0x00000002U 929 #define ADC_ICLR0_TOVIFG_M 0x00000002U 930 #define ADC_ICLR0_TOVIFG_S 1U 931 #define ADC_ICLR0_TOVIFG_CLR 0x00000002U 932 #define ADC_ICLR0_TOVIFG_NO_EFFECT 0x00000000U 933 934 // Field: [0] OVIFG 935 // 936 // Clear interrupt flag for MEMRESx overflow. 937 // ENUMs: 938 // CLR Interrupt is pending. 939 // NO_EFFECT Interrupt is not pending. 940 #define ADC_ICLR0_OVIFG 0x00000001U 941 #define ADC_ICLR0_OVIFG_M 0x00000001U 942 #define ADC_ICLR0_OVIFG_S 0U 943 #define ADC_ICLR0_OVIFG_CLR 0x00000001U 944 #define ADC_ICLR0_OVIFG_NO_EFFECT 0x00000000U 945 946 //***************************************************************************** 947 // 948 // Register: ADC_O_IMASK1 949 // 950 //***************************************************************************** 951 // Field: [8] MEMRESIFG0 952 // 953 // MEMRES0 conversion result interrupt mask. 954 // ENUMs: 955 // SET A new data is ready to be read. 956 // CLR No new data ready. 957 #define ADC_IMASK1_MEMRESIFG0 0x00000100U 958 #define ADC_IMASK1_MEMRESIFG0_M 0x00000100U 959 #define ADC_IMASK1_MEMRESIFG0_S 8U 960 #define ADC_IMASK1_MEMRESIFG0_SET 0x00000100U 961 #define ADC_IMASK1_MEMRESIFG0_CLR 0x00000000U 962 963 // Field: [4] INIFG 964 // 965 // In-range comparator interrupt mask. 966 // ENUMs: 967 // SET Interrupt is pending. 968 // CLR Interrupt is not pending. 969 #define ADC_IMASK1_INIFG 0x00000010U 970 #define ADC_IMASK1_INIFG_M 0x00000010U 971 #define ADC_IMASK1_INIFG_S 4U 972 #define ADC_IMASK1_INIFG_SET 0x00000010U 973 #define ADC_IMASK1_INIFG_CLR 0x00000000U 974 975 // Field: [3] LOWIFG 976 // 977 // Low threshold compare interrupt mask. 978 // ENUMs: 979 // SET Interrupt is pending. 980 // CLR Interrupt is not pending. 981 #define ADC_IMASK1_LOWIFG 0x00000008U 982 #define ADC_IMASK1_LOWIFG_M 0x00000008U 983 #define ADC_IMASK1_LOWIFG_S 3U 984 #define ADC_IMASK1_LOWIFG_SET 0x00000008U 985 #define ADC_IMASK1_LOWIFG_CLR 0x00000000U 986 987 // Field: [2] HIGHIFG 988 // 989 // High threshold compare interrupt mask. 990 // ENUMs: 991 // SET Interrupt is pending. 992 // CLR Interrupt is not pending. 993 #define ADC_IMASK1_HIGHIFG 0x00000004U 994 #define ADC_IMASK1_HIGHIFG_M 0x00000004U 995 #define ADC_IMASK1_HIGHIFG_S 2U 996 #define ADC_IMASK1_HIGHIFG_SET 0x00000004U 997 #define ADC_IMASK1_HIGHIFG_CLR 0x00000000U 998 999 //***************************************************************************** 1000 // 1001 // Register: ADC_O_RIS1 1002 // 1003 //***************************************************************************** 1004 // Field: [8] MEMRESIFG0 1005 // 1006 // Raw interrupt status for MEMRES0. 1007 // This bit is set to 1 when MEMRES0 is loaded with a new 1008 // conversion result. 1009 // Reading MEMRES0 register will clear this bit, or when the 1010 // corresponding bit in ICLR1 is set to 1 1011 // ENUMs: 1012 // SET A new data is ready to be read. 1013 // CLR No new data ready. 1014 #define ADC_RIS1_MEMRESIFG0 0x00000100U 1015 #define ADC_RIS1_MEMRESIFG0_M 0x00000100U 1016 #define ADC_RIS1_MEMRESIFG0_S 8U 1017 #define ADC_RIS1_MEMRESIFG0_SET 0x00000100U 1018 #define ADC_RIS1_MEMRESIFG0_CLR 0x00000000U 1019 1020 // Field: [4] INIFG 1021 // 1022 // Raw interrupt status for In-range comparator. 1023 // ENUMs: 1024 // SET Interrupt is pending. 1025 // CLR Interrupt is not pending. 1026 #define ADC_RIS1_INIFG 0x00000010U 1027 #define ADC_RIS1_INIFG_M 0x00000010U 1028 #define ADC_RIS1_INIFG_S 4U 1029 #define ADC_RIS1_INIFG_SET 0x00000010U 1030 #define ADC_RIS1_INIFG_CLR 0x00000000U 1031 1032 // Field: [3] LOWIFG 1033 // 1034 // Raw interrupt flag for the MEMRESx result register being below than the 1035 // WCLOWx threshold of the window comparator. 1036 // ENUMs: 1037 // SET Interrupt is pending. 1038 // CLR Interrupt is not pending. 1039 #define ADC_RIS1_LOWIFG 0x00000008U 1040 #define ADC_RIS1_LOWIFG_M 0x00000008U 1041 #define ADC_RIS1_LOWIFG_S 3U 1042 #define ADC_RIS1_LOWIFG_SET 0x00000008U 1043 #define ADC_RIS1_LOWIFG_CLR 0x00000000U 1044 1045 // Field: [2] HIGHIFG 1046 // 1047 // Raw interrupt flag for the MEMRESx result register being higher than the 1048 // WCHIGHx threshold of the window comparator. 1049 // ENUMs: 1050 // SET Interrupt is pending. 1051 // CLR Interrupt is not pending. 1052 #define ADC_RIS1_HIGHIFG 0x00000004U 1053 #define ADC_RIS1_HIGHIFG_M 0x00000004U 1054 #define ADC_RIS1_HIGHIFG_S 2U 1055 #define ADC_RIS1_HIGHIFG_SET 0x00000004U 1056 #define ADC_RIS1_HIGHIFG_CLR 0x00000000U 1057 1058 //***************************************************************************** 1059 // 1060 // Register: ADC_O_MIS1 1061 // 1062 //***************************************************************************** 1063 // Field: [8] MEMRESIFG0 1064 // 1065 // Masked interrupt status for MEMRES0. 1066 // ENUMs: 1067 // SET A new data is ready to be read. 1068 // CLR No new data ready. 1069 #define ADC_MIS1_MEMRESIFG0 0x00000100U 1070 #define ADC_MIS1_MEMRESIFG0_M 0x00000100U 1071 #define ADC_MIS1_MEMRESIFG0_S 8U 1072 #define ADC_MIS1_MEMRESIFG0_SET 0x00000100U 1073 #define ADC_MIS1_MEMRESIFG0_CLR 0x00000000U 1074 1075 // Field: [4] INIFG 1076 // 1077 // Mask INIFG in MIS1 register. 1078 // ENUMs: 1079 // SET Interrupt is pending. 1080 // CLR Interrupt is not pending. 1081 #define ADC_MIS1_INIFG 0x00000010U 1082 #define ADC_MIS1_INIFG_M 0x00000010U 1083 #define ADC_MIS1_INIFG_S 4U 1084 #define ADC_MIS1_INIFG_SET 0x00000010U 1085 #define ADC_MIS1_INIFG_CLR 0x00000000U 1086 1087 // Field: [3] LOWIFG 1088 // 1089 // Masked interrupt flag for the MEMRESx result register being below than the 1090 // WCLOWx threshold of the window comparator. 1091 // ENUMs: 1092 // SET Interrupt is pending. 1093 // CLR Interrupt is not pending. 1094 #define ADC_MIS1_LOWIFG 0x00000008U 1095 #define ADC_MIS1_LOWIFG_M 0x00000008U 1096 #define ADC_MIS1_LOWIFG_S 3U 1097 #define ADC_MIS1_LOWIFG_SET 0x00000008U 1098 #define ADC_MIS1_LOWIFG_CLR 0x00000000U 1099 1100 // Field: [2] HIGHIFG 1101 // 1102 // Masked interrupt flag for the MEMRESx result register being higher than the 1103 // WCHIGHx threshold of the window comparator. 1104 // ENUMs: 1105 // SET Interrupt is pending. 1106 // CLR Interrupt is not pending. 1107 #define ADC_MIS1_HIGHIFG 0x00000004U 1108 #define ADC_MIS1_HIGHIFG_M 0x00000004U 1109 #define ADC_MIS1_HIGHIFG_S 2U 1110 #define ADC_MIS1_HIGHIFG_SET 0x00000004U 1111 #define ADC_MIS1_HIGHIFG_CLR 0x00000000U 1112 1113 //***************************************************************************** 1114 // 1115 // Register: ADC_O_ISET1 1116 // 1117 //***************************************************************************** 1118 // Field: [8] MEMRESIFG0 1119 // 1120 // Set Interrupt status for MEMRES0. 1121 // ENUMs: 1122 // SET A new data is ready to be read. 1123 // NO_EFFECT No new data ready. 1124 #define ADC_ISET1_MEMRESIFG0 0x00000100U 1125 #define ADC_ISET1_MEMRESIFG0_M 0x00000100U 1126 #define ADC_ISET1_MEMRESIFG0_S 8U 1127 #define ADC_ISET1_MEMRESIFG0_SET 0x00000100U 1128 #define ADC_ISET1_MEMRESIFG0_NO_EFFECT 0x00000000U 1129 1130 // Field: [4] INIFG 1131 // 1132 // Set INIFG interrupt register. 1133 // ENUMs: 1134 // SET Interrupt is pending. 1135 // NO_EFFECT Interrupt is not pending. 1136 #define ADC_ISET1_INIFG 0x00000010U 1137 #define ADC_ISET1_INIFG_M 0x00000010U 1138 #define ADC_ISET1_INIFG_S 4U 1139 #define ADC_ISET1_INIFG_SET 0x00000010U 1140 #define ADC_ISET1_INIFG_NO_EFFECT 0x00000000U 1141 1142 // Field: [3] LOWIFG 1143 // 1144 // Set interrupt for MEMRESx result register being below than the WCLOWx 1145 // threshold of the window comparator. 1146 // ENUMs: 1147 // SET Interrupt is pending. 1148 // NO_EFFECT Interrupt is not pending. 1149 #define ADC_ISET1_LOWIFG 0x00000008U 1150 #define ADC_ISET1_LOWIFG_M 0x00000008U 1151 #define ADC_ISET1_LOWIFG_S 3U 1152 #define ADC_ISET1_LOWIFG_SET 0x00000008U 1153 #define ADC_ISET1_LOWIFG_NO_EFFECT 0x00000000U 1154 1155 // Field: [2] HIGHIFG 1156 // 1157 // Set Interrupt for the MEMRESx result register being higher than the WCHIGHx 1158 // threshold of the window comparator. 1159 // ENUMs: 1160 // SET Interrupt is pending. 1161 // NO_EFFECT Interrupt is not pending. 1162 #define ADC_ISET1_HIGHIFG 0x00000004U 1163 #define ADC_ISET1_HIGHIFG_M 0x00000004U 1164 #define ADC_ISET1_HIGHIFG_S 2U 1165 #define ADC_ISET1_HIGHIFG_SET 0x00000004U 1166 #define ADC_ISET1_HIGHIFG_NO_EFFECT 0x00000000U 1167 1168 //***************************************************************************** 1169 // 1170 // Register: ADC_O_ICLR1 1171 // 1172 //***************************************************************************** 1173 // Field: [8] MEMRESIFG0 1174 // 1175 // Clear interrupt status for MEMRES0. 1176 // ENUMs: 1177 // CLR A new data is ready to be read. 1178 // NO_EFFECT No new data ready. 1179 #define ADC_ICLR1_MEMRESIFG0 0x00000100U 1180 #define ADC_ICLR1_MEMRESIFG0_M 0x00000100U 1181 #define ADC_ICLR1_MEMRESIFG0_S 8U 1182 #define ADC_ICLR1_MEMRESIFG0_CLR 0x00000100U 1183 #define ADC_ICLR1_MEMRESIFG0_NO_EFFECT 0x00000000U 1184 1185 // Field: [4] INIFG 1186 // 1187 // Clear INIFG in MIS1 register. 1188 // ENUMs: 1189 // CLR Interrupt is pending. 1190 // NO_EFFECT Interrupt is not pending. 1191 #define ADC_ICLR1_INIFG 0x00000010U 1192 #define ADC_ICLR1_INIFG_M 0x00000010U 1193 #define ADC_ICLR1_INIFG_S 4U 1194 #define ADC_ICLR1_INIFG_CLR 0x00000010U 1195 #define ADC_ICLR1_INIFG_NO_EFFECT 0x00000000U 1196 1197 // Field: [3] LOWIFG 1198 // 1199 // Clear interrupt flag for the MEMRESx result register being below than the 1200 // WCLOWx threshold of the window comparator. 1201 // ENUMs: 1202 // CLR Interrupt is pending. 1203 // NO_EFFECT Interrupt is not pending. 1204 #define ADC_ICLR1_LOWIFG 0x00000008U 1205 #define ADC_ICLR1_LOWIFG_M 0x00000008U 1206 #define ADC_ICLR1_LOWIFG_S 3U 1207 #define ADC_ICLR1_LOWIFG_CLR 0x00000008U 1208 #define ADC_ICLR1_LOWIFG_NO_EFFECT 0x00000000U 1209 1210 // Field: [2] HIGHIFG 1211 // 1212 // Clear interrupt flag for the MEMRESx result register being higher than the 1213 // WCHIGHx threshold of the window comparator. 1214 // ENUMs: 1215 // CLR Interrupt is pending. 1216 // NO_EFFECT Interrupt is not pending. 1217 #define ADC_ICLR1_HIGHIFG 0x00000004U 1218 #define ADC_ICLR1_HIGHIFG_M 0x00000004U 1219 #define ADC_ICLR1_HIGHIFG_S 2U 1220 #define ADC_ICLR1_HIGHIFG_CLR 0x00000004U 1221 #define ADC_ICLR1_HIGHIFG_NO_EFFECT 0x00000000U 1222 1223 //***************************************************************************** 1224 // 1225 // Register: ADC_O_IMASK2 1226 // 1227 //***************************************************************************** 1228 // Field: [11] MEMRESIFG3 1229 // 1230 // MEMRES3 conversion result interrupt mask. 1231 // ENUMs: 1232 // SET A new data is ready to be read. 1233 // CLR No new data ready. 1234 #define ADC_IMASK2_MEMRESIFG3 0x00000800U 1235 #define ADC_IMASK2_MEMRESIFG3_M 0x00000800U 1236 #define ADC_IMASK2_MEMRESIFG3_S 11U 1237 #define ADC_IMASK2_MEMRESIFG3_SET 0x00000800U 1238 #define ADC_IMASK2_MEMRESIFG3_CLR 0x00000000U 1239 1240 // Field: [10] MEMRESIFG2 1241 // 1242 // MEMRES2 conversion result interrupt mask. 1243 // ENUMs: 1244 // SET A new data is ready to be read. 1245 // CLR No new data ready. 1246 #define ADC_IMASK2_MEMRESIFG2 0x00000400U 1247 #define ADC_IMASK2_MEMRESIFG2_M 0x00000400U 1248 #define ADC_IMASK2_MEMRESIFG2_S 10U 1249 #define ADC_IMASK2_MEMRESIFG2_SET 0x00000400U 1250 #define ADC_IMASK2_MEMRESIFG2_CLR 0x00000000U 1251 1252 // Field: [9] MEMRESIFG1 1253 // 1254 // MEMRES1 conversion result interrupt mask. 1255 // ENUMs: 1256 // SET A new data is ready to be read. 1257 // CLR No new data ready. 1258 #define ADC_IMASK2_MEMRESIFG1 0x00000200U 1259 #define ADC_IMASK2_MEMRESIFG1_M 0x00000200U 1260 #define ADC_IMASK2_MEMRESIFG1_S 9U 1261 #define ADC_IMASK2_MEMRESIFG1_SET 0x00000200U 1262 #define ADC_IMASK2_MEMRESIFG1_CLR 0x00000000U 1263 1264 // Field: [8] MEMRESIFG0 1265 // 1266 // MEMRES0 conversion result interrupt mask. 1267 // ENUMs: 1268 // SET A new data is ready to be read. 1269 // CLR No new data ready. 1270 #define ADC_IMASK2_MEMRESIFG0 0x00000100U 1271 #define ADC_IMASK2_MEMRESIFG0_M 0x00000100U 1272 #define ADC_IMASK2_MEMRESIFG0_S 8U 1273 #define ADC_IMASK2_MEMRESIFG0_SET 0x00000100U 1274 #define ADC_IMASK2_MEMRESIFG0_CLR 0x00000000U 1275 1276 //***************************************************************************** 1277 // 1278 // Register: ADC_O_RIS2 1279 // 1280 //***************************************************************************** 1281 // Field: [11] MEMRESIFG3 1282 // 1283 // Raw interrupt status for MEMRES3. 1284 // This bit is set to 1 when MEMRES3 is loaded with a new 1285 // conversion result. 1286 // Reading MEMRES3 register will clear this bit, or when the 1287 // corresponding bit in ICLR2 is set to 1 1288 // ENUMs: 1289 // SET A new data is ready to be read. 1290 // CLR No new data ready. 1291 #define ADC_RIS2_MEMRESIFG3 0x00000800U 1292 #define ADC_RIS2_MEMRESIFG3_M 0x00000800U 1293 #define ADC_RIS2_MEMRESIFG3_S 11U 1294 #define ADC_RIS2_MEMRESIFG3_SET 0x00000800U 1295 #define ADC_RIS2_MEMRESIFG3_CLR 0x00000000U 1296 1297 // Field: [10] MEMRESIFG2 1298 // 1299 // Raw interrupt status for MEMRES2. 1300 // This bit is set to 1 when MEMRES2 is loaded with a new 1301 // conversion result. 1302 // Reading MEMRES2 register will clear this bit, or when the 1303 // corresponding bit in ICLR2 is set to 1 1304 // ENUMs: 1305 // SET A new data is ready to be read. 1306 // CLR No new data ready. 1307 #define ADC_RIS2_MEMRESIFG2 0x00000400U 1308 #define ADC_RIS2_MEMRESIFG2_M 0x00000400U 1309 #define ADC_RIS2_MEMRESIFG2_S 10U 1310 #define ADC_RIS2_MEMRESIFG2_SET 0x00000400U 1311 #define ADC_RIS2_MEMRESIFG2_CLR 0x00000000U 1312 1313 // Field: [9] MEMRESIFG1 1314 // 1315 // Raw interrupt status for MEMRES1. 1316 // This bit is set to 1 when MEMRES1 is loaded with a new 1317 // conversion result. 1318 // Reading MEMRES1 register will clear this bit, or when the 1319 // corresponding bit in ICLR2 is set to 1 1320 // ENUMs: 1321 // SET A new data is ready to be read. 1322 // CLR No new data ready. 1323 #define ADC_RIS2_MEMRESIFG1 0x00000200U 1324 #define ADC_RIS2_MEMRESIFG1_M 0x00000200U 1325 #define ADC_RIS2_MEMRESIFG1_S 9U 1326 #define ADC_RIS2_MEMRESIFG1_SET 0x00000200U 1327 #define ADC_RIS2_MEMRESIFG1_CLR 0x00000000U 1328 1329 // Field: [8] MEMRESIFG0 1330 // 1331 // Raw interrupt status for MEMRES0. 1332 // This bit is set to 1 when MEMRES0 is loaded with a new 1333 // conversion result. 1334 // Reading MEMRES0 register will clear this bit, or when the 1335 // corresponding bit in ICLR2 is set to 1 1336 // ENUMs: 1337 // SET A new data is ready to be read. 1338 // CLR No new data ready. 1339 #define ADC_RIS2_MEMRESIFG0 0x00000100U 1340 #define ADC_RIS2_MEMRESIFG0_M 0x00000100U 1341 #define ADC_RIS2_MEMRESIFG0_S 8U 1342 #define ADC_RIS2_MEMRESIFG0_SET 0x00000100U 1343 #define ADC_RIS2_MEMRESIFG0_CLR 0x00000000U 1344 1345 //***************************************************************************** 1346 // 1347 // Register: ADC_O_MIS2 1348 // 1349 //***************************************************************************** 1350 // Field: [11] MEMRESIFG3 1351 // 1352 // Masked interrupt status for MEMRES3. 1353 // ENUMs: 1354 // SET A new data is ready to be read. 1355 // CLR No new data ready. 1356 #define ADC_MIS2_MEMRESIFG3 0x00000800U 1357 #define ADC_MIS2_MEMRESIFG3_M 0x00000800U 1358 #define ADC_MIS2_MEMRESIFG3_S 11U 1359 #define ADC_MIS2_MEMRESIFG3_SET 0x00000800U 1360 #define ADC_MIS2_MEMRESIFG3_CLR 0x00000000U 1361 1362 // Field: [10] MEMRESIFG2 1363 // 1364 // Masked interrupt status for MEMRES2. 1365 // ENUMs: 1366 // SET A new data is ready to be read. 1367 // CLR No new data ready. 1368 #define ADC_MIS2_MEMRESIFG2 0x00000400U 1369 #define ADC_MIS2_MEMRESIFG2_M 0x00000400U 1370 #define ADC_MIS2_MEMRESIFG2_S 10U 1371 #define ADC_MIS2_MEMRESIFG2_SET 0x00000400U 1372 #define ADC_MIS2_MEMRESIFG2_CLR 0x00000000U 1373 1374 // Field: [9] MEMRESIFG1 1375 // 1376 // Masked interrupt status for MEMRES1. 1377 // ENUMs: 1378 // SET A new data is ready to be read. 1379 // CLR No new data ready. 1380 #define ADC_MIS2_MEMRESIFG1 0x00000200U 1381 #define ADC_MIS2_MEMRESIFG1_M 0x00000200U 1382 #define ADC_MIS2_MEMRESIFG1_S 9U 1383 #define ADC_MIS2_MEMRESIFG1_SET 0x00000200U 1384 #define ADC_MIS2_MEMRESIFG1_CLR 0x00000000U 1385 1386 // Field: [8] MEMRESIFG0 1387 // 1388 // Masked interrupt status for MEMRES0. 1389 // ENUMs: 1390 // SET A new data is ready to be read. 1391 // CLR No new data ready. 1392 #define ADC_MIS2_MEMRESIFG0 0x00000100U 1393 #define ADC_MIS2_MEMRESIFG0_M 0x00000100U 1394 #define ADC_MIS2_MEMRESIFG0_S 8U 1395 #define ADC_MIS2_MEMRESIFG0_SET 0x00000100U 1396 #define ADC_MIS2_MEMRESIFG0_CLR 0x00000000U 1397 1398 //***************************************************************************** 1399 // 1400 // Register: ADC_O_ISET2 1401 // 1402 //***************************************************************************** 1403 // Field: [11] MEMRESIFG3 1404 // 1405 // Set interrupt status for MEMRES3. 1406 // ENUMs: 1407 // SET A new data is ready to be read. 1408 // NO_EFFECT No new data ready. 1409 #define ADC_ISET2_MEMRESIFG3 0x00000800U 1410 #define ADC_ISET2_MEMRESIFG3_M 0x00000800U 1411 #define ADC_ISET2_MEMRESIFG3_S 11U 1412 #define ADC_ISET2_MEMRESIFG3_SET 0x00000800U 1413 #define ADC_ISET2_MEMRESIFG3_NO_EFFECT 0x00000000U 1414 1415 // Field: [10] MEMRESIFG2 1416 // 1417 // Set interrupt status for MEMRES2. 1418 // ENUMs: 1419 // SET A new data is ready to be read. 1420 // NO_EFFECT No new data ready. 1421 #define ADC_ISET2_MEMRESIFG2 0x00000400U 1422 #define ADC_ISET2_MEMRESIFG2_M 0x00000400U 1423 #define ADC_ISET2_MEMRESIFG2_S 10U 1424 #define ADC_ISET2_MEMRESIFG2_SET 0x00000400U 1425 #define ADC_ISET2_MEMRESIFG2_NO_EFFECT 0x00000000U 1426 1427 // Field: [9] MEMRESIFG1 1428 // 1429 // Set interrupt status for MEMRES1. 1430 // ENUMs: 1431 // SET A new data is ready to be read. 1432 // NO_EFFECT No new data ready. 1433 #define ADC_ISET2_MEMRESIFG1 0x00000200U 1434 #define ADC_ISET2_MEMRESIFG1_M 0x00000200U 1435 #define ADC_ISET2_MEMRESIFG1_S 9U 1436 #define ADC_ISET2_MEMRESIFG1_SET 0x00000200U 1437 #define ADC_ISET2_MEMRESIFG1_NO_EFFECT 0x00000000U 1438 1439 // Field: [8] MEMRESIFG0 1440 // 1441 // Set Interrupt status for MEMRES0. 1442 // ENUMs: 1443 // SET A new data is ready to be read. 1444 // NO_EFFECT No new data ready. 1445 #define ADC_ISET2_MEMRESIFG0 0x00000100U 1446 #define ADC_ISET2_MEMRESIFG0_M 0x00000100U 1447 #define ADC_ISET2_MEMRESIFG0_S 8U 1448 #define ADC_ISET2_MEMRESIFG0_SET 0x00000100U 1449 #define ADC_ISET2_MEMRESIFG0_NO_EFFECT 0x00000000U 1450 1451 //***************************************************************************** 1452 // 1453 // Register: ADC_O_ICLR2 1454 // 1455 //***************************************************************************** 1456 // Field: [11] MEMRESIFG3 1457 // 1458 // Clear interrupt status for MEMRES3. 1459 // ENUMs: 1460 // CLR A new data is ready to be read. 1461 // NO_EFFECT No new data ready. 1462 #define ADC_ICLR2_MEMRESIFG3 0x00000800U 1463 #define ADC_ICLR2_MEMRESIFG3_M 0x00000800U 1464 #define ADC_ICLR2_MEMRESIFG3_S 11U 1465 #define ADC_ICLR2_MEMRESIFG3_CLR 0x00000800U 1466 #define ADC_ICLR2_MEMRESIFG3_NO_EFFECT 0x00000000U 1467 1468 // Field: [10] MEMRESIFG2 1469 // 1470 // Clear interrupt status for MEMRES2. 1471 // ENUMs: 1472 // CLR A new data is ready to be read. 1473 // NO_EFFECT No new data ready. 1474 #define ADC_ICLR2_MEMRESIFG2 0x00000400U 1475 #define ADC_ICLR2_MEMRESIFG2_M 0x00000400U 1476 #define ADC_ICLR2_MEMRESIFG2_S 10U 1477 #define ADC_ICLR2_MEMRESIFG2_CLR 0x00000400U 1478 #define ADC_ICLR2_MEMRESIFG2_NO_EFFECT 0x00000000U 1479 1480 // Field: [9] MEMRESIFG1 1481 // 1482 // Clear interrupt status for MEMRES1. 1483 // ENUMs: 1484 // CLR A new data is ready to be read. 1485 // NO_EFFECT No new data ready. 1486 #define ADC_ICLR2_MEMRESIFG1 0x00000200U 1487 #define ADC_ICLR2_MEMRESIFG1_M 0x00000200U 1488 #define ADC_ICLR2_MEMRESIFG1_S 9U 1489 #define ADC_ICLR2_MEMRESIFG1_CLR 0x00000200U 1490 #define ADC_ICLR2_MEMRESIFG1_NO_EFFECT 0x00000000U 1491 1492 // Field: [8] MEMRESIFG0 1493 // 1494 // Clear interrupt status for MEMRES0. 1495 // ENUMs: 1496 // CLR A new data is ready to be read. 1497 // NO_EFFECT No new data ready. 1498 #define ADC_ICLR2_MEMRESIFG0 0x00000100U 1499 #define ADC_ICLR2_MEMRESIFG0_M 0x00000100U 1500 #define ADC_ICLR2_MEMRESIFG0_S 8U 1501 #define ADC_ICLR2_MEMRESIFG0_CLR 0x00000100U 1502 #define ADC_ICLR2_MEMRESIFG0_NO_EFFECT 0x00000000U 1503 1504 //***************************************************************************** 1505 // 1506 // Register: ADC_O_CTL0 1507 // 1508 //***************************************************************************** 1509 // Field: [26:24] SCLKDIV 1510 // 1511 // Sample clock divider 1512 // ENUMs: 1513 // DIV_BY_48 Divide clock source by 48 1514 // DIV_BY_32 Divide clock source by 32 1515 // DIV_BY_24 Divide clock source by 24 1516 // DIV_BY_16 Divide clock source by 16 1517 // DIV_BY_8 Divide clock source by 8 1518 // DIV_BY_4 Divide clock source by 4 1519 // DIV_BY_2 Divide clock source by 2 1520 // DIV_BY_1 Do not divide clock source 1521 #define ADC_CTL0_SCLKDIV_W 3U 1522 #define ADC_CTL0_SCLKDIV_M 0x07000000U 1523 #define ADC_CTL0_SCLKDIV_S 24U 1524 #define ADC_CTL0_SCLKDIV_DIV_BY_48 0x07000000U 1525 #define ADC_CTL0_SCLKDIV_DIV_BY_32 0x06000000U 1526 #define ADC_CTL0_SCLKDIV_DIV_BY_24 0x05000000U 1527 #define ADC_CTL0_SCLKDIV_DIV_BY_16 0x04000000U 1528 #define ADC_CTL0_SCLKDIV_DIV_BY_8 0x03000000U 1529 #define ADC_CTL0_SCLKDIV_DIV_BY_4 0x02000000U 1530 #define ADC_CTL0_SCLKDIV_DIV_BY_2 0x01000000U 1531 #define ADC_CTL0_SCLKDIV_DIV_BY_1 0x00000000U 1532 1533 // Field: [16] PWRDN 1534 // 1535 // Power down policy 1536 // ENUMs: 1537 // MANUAL ADC remains powered on as long as it is enabled 1538 // through software. 1539 // AUTO ADC is powered down on completion of a conversion 1540 // if there is no pending trigger 1541 #define ADC_CTL0_PWRDN 0x00010000U 1542 #define ADC_CTL0_PWRDN_M 0x00010000U 1543 #define ADC_CTL0_PWRDN_S 16U 1544 #define ADC_CTL0_PWRDN_MANUAL 0x00010000U 1545 #define ADC_CTL0_PWRDN_AUTO 0x00000000U 1546 1547 // Field: [0] ENC 1548 // 1549 // Enable conversion 1550 // ENUMs: 1551 // ON Conversion enabled. ADC sequencer waits for the 1552 // programmed trigger (software or hardware). 1553 // OFF Conversion disabled. ENC change from ON to OFF 1554 // will abort single or repeat sequence on a 1555 // MEMCTLx boundary. The current conversion will 1556 // finish and result stored in corresponding 1557 // MEMRESx. 1558 #define ADC_CTL0_ENC 0x00000001U 1559 #define ADC_CTL0_ENC_M 0x00000001U 1560 #define ADC_CTL0_ENC_S 0U 1561 #define ADC_CTL0_ENC_ON 0x00000001U 1562 #define ADC_CTL0_ENC_OFF 0x00000000U 1563 1564 //***************************************************************************** 1565 // 1566 // Register: ADC_O_CTL1 1567 // 1568 //***************************************************************************** 1569 // Field: [20] SAMPMODE 1570 // 1571 // Sample mode. This bit selects the source of the sampling signal. 1572 // MANUAL option is not applicable when TRIGSRC is selected as hardware event 1573 // trigger. 1574 // ENUMs: 1575 // MANUAL Software trigger is used as sample signal 1576 // AUTO Sample timer high phase is used as sample signal 1577 #define ADC_CTL1_SAMPMODE 0x00100000U 1578 #define ADC_CTL1_SAMPMODE_M 0x00100000U 1579 #define ADC_CTL1_SAMPMODE_S 20U 1580 #define ADC_CTL1_SAMPMODE_MANUAL 0x00100000U 1581 #define ADC_CTL1_SAMPMODE_AUTO 0x00000000U 1582 1583 // Field: [17:16] CONSEQ 1584 // 1585 // Conversion sequence mode 1586 // ENUMs: 1587 // REPEATSEQUENCE ADC channel sequence pointed by STARTADD and 1588 // ENDADD will be converted repeatedly 1589 // REPEATSINGLE ADC channel in MEMCTLx pointed by STARTADD will be 1590 // converted repeatedly 1591 // SEQUENCE ADC channel sequence pointed by STARTADD and 1592 // ENDADD will be converted once 1593 // SINGLE ADC channel in MEMCTLx pointed by STARTADD will be 1594 // converted once 1595 #define ADC_CTL1_CONSEQ_W 2U 1596 #define ADC_CTL1_CONSEQ_M 0x00030000U 1597 #define ADC_CTL1_CONSEQ_S 16U 1598 #define ADC_CTL1_CONSEQ_REPEATSEQUENCE 0x00030000U 1599 #define ADC_CTL1_CONSEQ_REPEATSINGLE 0x00020000U 1600 #define ADC_CTL1_CONSEQ_SEQUENCE 0x00010000U 1601 #define ADC_CTL1_CONSEQ_SINGLE 0x00000000U 1602 1603 // Field: [8] SC 1604 // 1605 // Start of conversion 1606 // ENUMs: 1607 // START When SAMPMODE is set to MANUAL, setting this bit 1608 // will start the sample phase. Sample phase will 1609 // last as long as this bit is set. 1610 // When SAMPMODE is set to 1611 // AUTO, setting this bit will trigger the timer 1612 // based sample time. 1613 // STOP When SAMPMODE is set to MANUAL, clearing this bit 1614 // will end the sample phase and the conversion 1615 // phase will start. 1616 // When SAMPMODE is set to 1617 // AUTO, writing 0 has no effect. 1618 #define ADC_CTL1_SC 0x00000100U 1619 #define ADC_CTL1_SC_M 0x00000100U 1620 #define ADC_CTL1_SC_S 8U 1621 #define ADC_CTL1_SC_START 0x00000100U 1622 #define ADC_CTL1_SC_STOP 0x00000000U 1623 1624 // Field: [0] TRIGSRC 1625 // 1626 // Sample trigger source 1627 // ENUMs: 1628 // EVENT Hardware event trigger 1629 // SOFTWARE Software trigger 1630 #define ADC_CTL1_TRIGSRC 0x00000001U 1631 #define ADC_CTL1_TRIGSRC_M 0x00000001U 1632 #define ADC_CTL1_TRIGSRC_S 0U 1633 #define ADC_CTL1_TRIGSRC_EVENT 0x00000001U 1634 #define ADC_CTL1_TRIGSRC_SOFTWARE 0x00000000U 1635 1636 //***************************************************************************** 1637 // 1638 // Register: ADC_O_CTL2 1639 // 1640 //***************************************************************************** 1641 // Field: [28:24] ENDADD 1642 // 1643 // Sequence end address. These bits select which MEMCTLx is the last one for 1644 // the sequence mode. 1645 // The value of ENDADD is 0x00 to 0x03 corresponding to MEMRES0 to MEMRES3. 1646 // ENUMs: 1647 // ADDR_03 MEMCTL3 is selected as end address of sequence. 1648 // ADDR_02 MEMCTL2 is selected as end address of sequence. 1649 // ADDR_01 MEMCTL1 is selected as end address of sequence. 1650 // ADDR_00 MEMCTL0 is selected as end address of sequence. 1651 #define ADC_CTL2_ENDADD_W 5U 1652 #define ADC_CTL2_ENDADD_M 0x1F000000U 1653 #define ADC_CTL2_ENDADD_S 24U 1654 #define ADC_CTL2_ENDADD_ADDR_03 0x03000000U 1655 #define ADC_CTL2_ENDADD_ADDR_02 0x02000000U 1656 #define ADC_CTL2_ENDADD_ADDR_01 0x01000000U 1657 #define ADC_CTL2_ENDADD_ADDR_00 0x00000000U 1658 1659 // Field: [20:16] STARTADD 1660 // 1661 // Sequencer start address. These bits select which MEMCTLx is used for single 1662 // conversion or as first MEMCTL for sequence mode. 1663 // The value of STARTADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23. 1664 // ENUMs: 1665 // ADDR_03 MEMCTL3 is selected as start address of a sequence 1666 // or for a single conversion. 1667 // ADDR_02 MEMCTL2 is selected as start address of a sequence 1668 // or for a single conversion. 1669 // ADDR_01 MEMCTL1 is selected as start address of a sequence 1670 // or for a single conversion. 1671 // ADDR_00 MEMCTL0 is selected as start address of a sequence 1672 // or for a single conversion. 1673 #define ADC_CTL2_STARTADD_W 5U 1674 #define ADC_CTL2_STARTADD_M 0x001F0000U 1675 #define ADC_CTL2_STARTADD_S 16U 1676 #define ADC_CTL2_STARTADD_ADDR_03 0x00030000U 1677 #define ADC_CTL2_STARTADD_ADDR_02 0x00020000U 1678 #define ADC_CTL2_STARTADD_ADDR_01 0x00010000U 1679 #define ADC_CTL2_STARTADD_ADDR_00 0x00000000U 1680 1681 // Field: [10] FIFOEN 1682 // 1683 // Enable FIFO based operation 1684 // ENUMs: 1685 // EN Enable 1686 // DIS Disable 1687 #define ADC_CTL2_FIFOEN 0x00000400U 1688 #define ADC_CTL2_FIFOEN_M 0x00000400U 1689 #define ADC_CTL2_FIFOEN_S 10U 1690 #define ADC_CTL2_FIFOEN_EN 0x00000400U 1691 #define ADC_CTL2_FIFOEN_DIS 0x00000000U 1692 1693 // Field: [8] DMAEN 1694 // 1695 // Enable DMA trigger for data transfer. 1696 // Note: DMAEN bit is cleared by hardware based on DMA done signal at the end 1697 // of data transfer. Software has to re-enable DMAEN bit for ADC to generate 1698 // DMA triggers. 1699 // ENUMs: 1700 // EN DMA trigger enabled 1701 // DIS DMA trigger not enabled 1702 #define ADC_CTL2_DMAEN 0x00000100U 1703 #define ADC_CTL2_DMAEN_M 0x00000100U 1704 #define ADC_CTL2_DMAEN_S 8U 1705 #define ADC_CTL2_DMAEN_EN 0x00000100U 1706 #define ADC_CTL2_DMAEN_DIS 0x00000000U 1707 1708 // Field: [2:1] RES 1709 // 1710 // Resolution. These bits define the resolutoin of ADC conversion result. 1711 // Note : A value of 3 defaults to 12-bits resolution. 1712 // ENUMs: 1713 // BIT_8 8-bits resolution 1714 // BIT_10 10-bits resolution 1715 // BIT_12 12-bits resolution 1716 #define ADC_CTL2_RES_W 2U 1717 #define ADC_CTL2_RES_M 0x00000006U 1718 #define ADC_CTL2_RES_S 1U 1719 #define ADC_CTL2_RES_BIT_8 0x00000004U 1720 #define ADC_CTL2_RES_BIT_10 0x00000002U 1721 #define ADC_CTL2_RES_BIT_12 0x00000000U 1722 1723 // Field: [0] DF 1724 // 1725 // Data read-back format. Data is always stored in binary unsigned format. 1726 // ENUMs: 1727 // SIGNED Digital result reads Signed Binary. (2s 1728 // complement), left aligned. 1729 // UNSIGNED Digital result reads as Binary Unsigned. 1730 #define ADC_CTL2_DF 0x00000001U 1731 #define ADC_CTL2_DF_M 0x00000001U 1732 #define ADC_CTL2_DF_S 0U 1733 #define ADC_CTL2_DF_SIGNED 0x00000001U 1734 #define ADC_CTL2_DF_UNSIGNED 0x00000000U 1735 1736 //***************************************************************************** 1737 // 1738 // Register: ADC_O_CTL3 1739 // 1740 //***************************************************************************** 1741 // Field: [13:12] ASCVRSEL 1742 // 1743 // Selects voltage reference for ASC operation. AREF- must be connected to 1744 // on-board ground when external reference option is selected. 1745 // Note: Writing value 0x3 defaults to INTREF. 1746 // ENUMs: 1747 // INTREF Internal reference 1748 // EXTREF External reference from AREF+/AREF- pins 1749 // VDDS VDDS reference 1750 #define ADC_CTL3_ASCVRSEL_W 2U 1751 #define ADC_CTL3_ASCVRSEL_M 0x00003000U 1752 #define ADC_CTL3_ASCVRSEL_S 12U 1753 #define ADC_CTL3_ASCVRSEL_INTREF 0x00002000U 1754 #define ADC_CTL3_ASCVRSEL_EXTREF 0x00001000U 1755 #define ADC_CTL3_ASCVRSEL_VDDS 0x00000000U 1756 1757 // Field: [8] ASCSTIME 1758 // 1759 // ASC sample time compare value select. This is used to select between SCOMP0 1760 // and SCOMP1 registers for ASC operation. 1761 // ENUMs: 1762 // SEL_SCOMP1 Select SCOMP1 1763 // SEL_SCOMP0 Select SCOMP0 1764 #define ADC_CTL3_ASCSTIME 0x00000100U 1765 #define ADC_CTL3_ASCSTIME_M 0x00000100U 1766 #define ADC_CTL3_ASCSTIME_S 8U 1767 #define ADC_CTL3_ASCSTIME_SEL_SCOMP1 0x00000100U 1768 #define ADC_CTL3_ASCSTIME_SEL_SCOMP0 0x00000000U 1769 1770 // Field: [4:0] ASCCHSEL 1771 // 1772 // ASC channel select 1773 // ENUMs: 1774 // CHAN_15 Selects channel 15 1775 // CHAN_14 Selects channel 14 1776 // CHAN_13 Selects channel 13 1777 // CHAN_12 Selects channel 12 1778 // CHAN_11 Selects channel 11 1779 // CHAN_10 Selects channel 10 1780 // CHAN_9 Selects channel 9 1781 // CHAN_8 Selects channel 8 1782 // CHAN_7 Selects channel 7 1783 // CHAN_6 Selects channel 6 1784 // CHAN_5 Selects channel 5 1785 // CHAN_4 Selects channel 4 1786 // CHAN_3 Selects channel 3 1787 // CHAN_2 Selects channel 2 1788 // CHAN_1 Selects channel 1 1789 // CHAN_0 Selects channel 0 1790 #define ADC_CTL3_ASCCHSEL_W 5U 1791 #define ADC_CTL3_ASCCHSEL_M 0x0000001FU 1792 #define ADC_CTL3_ASCCHSEL_S 0U 1793 #define ADC_CTL3_ASCCHSEL_CHAN_15 0x0000000FU 1794 #define ADC_CTL3_ASCCHSEL_CHAN_14 0x0000000EU 1795 #define ADC_CTL3_ASCCHSEL_CHAN_13 0x0000000DU 1796 #define ADC_CTL3_ASCCHSEL_CHAN_12 0x0000000CU 1797 #define ADC_CTL3_ASCCHSEL_CHAN_11 0x0000000BU 1798 #define ADC_CTL3_ASCCHSEL_CHAN_10 0x0000000AU 1799 #define ADC_CTL3_ASCCHSEL_CHAN_9 0x00000009U 1800 #define ADC_CTL3_ASCCHSEL_CHAN_8 0x00000008U 1801 #define ADC_CTL3_ASCCHSEL_CHAN_7 0x00000007U 1802 #define ADC_CTL3_ASCCHSEL_CHAN_6 0x00000006U 1803 #define ADC_CTL3_ASCCHSEL_CHAN_5 0x00000005U 1804 #define ADC_CTL3_ASCCHSEL_CHAN_4 0x00000004U 1805 #define ADC_CTL3_ASCCHSEL_CHAN_3 0x00000003U 1806 #define ADC_CTL3_ASCCHSEL_CHAN_2 0x00000002U 1807 #define ADC_CTL3_ASCCHSEL_CHAN_1 0x00000001U 1808 #define ADC_CTL3_ASCCHSEL_CHAN_0 0x00000000U 1809 1810 //***************************************************************************** 1811 // 1812 // Register: ADC_O_SCOMP0 1813 // 1814 //***************************************************************************** 1815 // Field: [9:0] VAL 1816 // 1817 // Specifies the number of sample clocks. 1818 // When VAL = 0 or 1, number of sample clocks = Sample clock divide value. 1819 // When VAL > 1, number of sample clocks = VAL x Sample clock divide value. 1820 // Note: Sample clock divide value is not the value written to SCLKDIV but the 1821 // actual divide value (SCLKDIV = 2 implies divide value is 4). 1822 // Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles. 1823 #define ADC_SCOMP0_VAL_W 10U 1824 #define ADC_SCOMP0_VAL_M 0x000003FFU 1825 #define ADC_SCOMP0_VAL_S 0U 1826 1827 //***************************************************************************** 1828 // 1829 // Register: ADC_O_SCOMP1 1830 // 1831 //***************************************************************************** 1832 // Field: [9:0] VAL 1833 // 1834 // Specifies the number of sample clocks. 1835 // When VAL = 0 or 1, number of sample clocks = Sample clock divide value. 1836 // When VAL > 1, number of sample clocks = VAL x Sample clock divide value. 1837 // Note: Sample clock divide value is not the value written to SCLKDIV but the 1838 // actual divide value (SCLKDIV = 2 implies divide value is 4). 1839 // Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles. 1840 #define ADC_SCOMP1_VAL_W 10U 1841 #define ADC_SCOMP1_VAL_M 0x000003FFU 1842 #define ADC_SCOMP1_VAL_S 0U 1843 1844 //***************************************************************************** 1845 // 1846 // Register: ADC_O_REFCFG 1847 // 1848 //***************************************************************************** 1849 // Field: [4:3] IBPROG 1850 // 1851 // Configures reference buffer bias current output value 1852 // ENUMs: 1853 // VAL3 0.67uA 1854 // VAL2 1855 // VAL1 0.5uA 1856 // VAL0 1857 #define ADC_REFCFG_IBPROG_W 2U 1858 #define ADC_REFCFG_IBPROG_M 0x00000018U 1859 #define ADC_REFCFG_IBPROG_S 3U 1860 #define ADC_REFCFG_IBPROG_VAL3 0x00000018U 1861 #define ADC_REFCFG_IBPROG_VAL2 0x00000010U 1862 #define ADC_REFCFG_IBPROG_VAL1 0x00000008U 1863 #define ADC_REFCFG_IBPROG_VAL0 0x00000000U 1864 1865 // Field: [2] SPARE 1866 // 1867 // Spare bit 1868 #define ADC_REFCFG_SPARE 0x00000004U 1869 #define ADC_REFCFG_SPARE_M 0x00000004U 1870 #define ADC_REFCFG_SPARE_S 2U 1871 1872 // Field: [1] REFVSEL 1873 // 1874 // Configures reference buffer output voltage 1875 // ENUMs: 1876 // V1P4 REFBUF generates 1.4V output 1877 // V2P5 REFBUF generates 2.5V output 1878 #define ADC_REFCFG_REFVSEL 0x00000002U 1879 #define ADC_REFCFG_REFVSEL_M 0x00000002U 1880 #define ADC_REFCFG_REFVSEL_S 1U 1881 #define ADC_REFCFG_REFVSEL_V1P4 0x00000002U 1882 #define ADC_REFCFG_REFVSEL_V2P5 0x00000000U 1883 1884 // Field: [0] REFEN 1885 // 1886 // Reference buffer enable 1887 // ENUMs: 1888 // EN Enable 1889 // DIS Disable 1890 #define ADC_REFCFG_REFEN 0x00000001U 1891 #define ADC_REFCFG_REFEN_M 0x00000001U 1892 #define ADC_REFCFG_REFEN_S 0U 1893 #define ADC_REFCFG_REFEN_EN 0x00000001U 1894 #define ADC_REFCFG_REFEN_DIS 0x00000000U 1895 1896 //***************************************************************************** 1897 // 1898 // Register: ADC_O_WCLOW 1899 // 1900 //***************************************************************************** 1901 // Field: [15:0] DATA 1902 // 1903 // If DF = 0, unsigned binary format has to be used. 1904 // The value based on the resolution has to be right aligned with the MSB on 1905 // the left. 1906 // For 10-bits and 8-bits resolution, unused bits have to be 0s. 1907 // 1908 // If DF = 1, 2s-complement format has to be used. 1909 // The value based on the resolution has to be left aligned with the LSB on the 1910 // right. 1911 // For 10-bits and 8-bits resolution, unused bits have to be 0s. 1912 #define ADC_WCLOW_DATA_W 16U 1913 #define ADC_WCLOW_DATA_M 0x0000FFFFU 1914 #define ADC_WCLOW_DATA_S 0U 1915 1916 //***************************************************************************** 1917 // 1918 // Register: ADC_O_WCHIGH 1919 // 1920 //***************************************************************************** 1921 // Field: [15:0] DATA 1922 // 1923 // If DF = 0, unsigned binary format has to be used. 1924 // The threshold value has to be right aligned, with the MSB on the left. 1925 // For 10-bits and 8-bits resolution, unused bit have to be 0s. 1926 // 1927 // If DF = 1, 2s-complement format has to be used. 1928 // The value based on the resolution has to be left aligned with the LSB on the 1929 // right. 1930 // For 10-bits and 8-bits resolution, unused bit have to be 0s. 1931 #define ADC_WCHIGH_DATA_W 16U 1932 #define ADC_WCHIGH_DATA_M 0x0000FFFFU 1933 #define ADC_WCHIGH_DATA_S 0U 1934 1935 //***************************************************************************** 1936 // 1937 // Register: ADC_O_FIFODATA 1938 // 1939 //***************************************************************************** 1940 // Field: [31:0] DATA 1941 // 1942 // Read from this data field returns the ADC sample from FIFO. 1943 #define ADC_FIFODATA_DATA_W 32U 1944 #define ADC_FIFODATA_DATA_M 0xFFFFFFFFU 1945 #define ADC_FIFODATA_DATA_S 0U 1946 1947 //***************************************************************************** 1948 // 1949 // Register: ADC_O_ASCRES 1950 // 1951 //***************************************************************************** 1952 // Field: [15:0] DATA 1953 // 1954 // Result of ADC ad-hoc single conversion. 1955 // If DF = 0, unsigned binary: 1956 // The conversion result is right aligned. In 10 and 8 bit modes, the unused 1957 // MSB bits are forced to 0. 1958 // If DF = 1, 2s-complement format: 1959 // The conversion result is left aligned. In 10 and 8 bit modes, the unused LSB 1960 // bits are forced to 0. 1961 // The data is stored in the right-justified format and is converted to the 1962 // left-justified 2s-complement format during read back. 1963 #define ADC_ASCRES_DATA_W 16U 1964 #define ADC_ASCRES_DATA_M 0x0000FFFFU 1965 #define ADC_ASCRES_DATA_S 0U 1966 1967 //***************************************************************************** 1968 // 1969 // Register: ADC_O_MEMCTL0 1970 // 1971 //***************************************************************************** 1972 // Field: [28] WINCOMP 1973 // 1974 // Enable window comparator. 1975 // ENUMs: 1976 // EN Enable 1977 // DIS Disable 1978 #define ADC_MEMCTL0_WINCOMP 0x10000000U 1979 #define ADC_MEMCTL0_WINCOMP_M 0x10000000U 1980 #define ADC_MEMCTL0_WINCOMP_S 28U 1981 #define ADC_MEMCTL0_WINCOMP_EN 0x10000000U 1982 #define ADC_MEMCTL0_WINCOMP_DIS 0x00000000U 1983 1984 // Field: [24] TRG 1985 // 1986 // Trigger policy. Indicates if a trigger will be needed to step to the next 1987 // MEMCTL in the sequence or to perform next conversion in the case of repeat 1988 // single channel conversions. 1989 // ENUMs: 1990 // TRIGGER_NEXT Next conversion requires a trigger 1991 // AUTO_NEXT Next conversion is automatic 1992 #define ADC_MEMCTL0_TRG 0x01000000U 1993 #define ADC_MEMCTL0_TRG_M 0x01000000U 1994 #define ADC_MEMCTL0_TRG_S 24U 1995 #define ADC_MEMCTL0_TRG_TRIGGER_NEXT 0x01000000U 1996 #define ADC_MEMCTL0_TRG_AUTO_NEXT 0x00000000U 1997 1998 // Field: [12] STIME 1999 // 2000 // Selects the source of sample timer period between SCOMP0 and SCOMP1. 2001 // ENUMs: 2002 // SEL_SCOMP1 Select SCOMP1 2003 // SEL_SCOMP0 Select SCOMP0 2004 #define ADC_MEMCTL0_STIME 0x00001000U 2005 #define ADC_MEMCTL0_STIME_M 0x00001000U 2006 #define ADC_MEMCTL0_STIME_S 12U 2007 #define ADC_MEMCTL0_STIME_SEL_SCOMP1 0x00001000U 2008 #define ADC_MEMCTL0_STIME_SEL_SCOMP0 0x00000000U 2009 2010 // Field: [9:8] VRSEL 2011 // 2012 // Voltage reference selection. AREF- must be connected to on-board ground when 2013 // external reference option is selected. 2014 // Note: Writing value 0x3 defaults to INTREF. 2015 // ENUMs: 2016 // INTREF Internal reference 2017 // EXTREF External reference from AREF+/AREF- pins 2018 // VDDS VDDS reference 2019 #define ADC_MEMCTL0_VRSEL_W 2U 2020 #define ADC_MEMCTL0_VRSEL_M 0x00000300U 2021 #define ADC_MEMCTL0_VRSEL_S 8U 2022 #define ADC_MEMCTL0_VRSEL_INTREF 0x00000200U 2023 #define ADC_MEMCTL0_VRSEL_EXTREF 0x00000100U 2024 #define ADC_MEMCTL0_VRSEL_VDDS 0x00000000U 2025 2026 // Field: [4:0] CHANSEL 2027 // 2028 // Input channel select. 2029 // ENUMs: 2030 // CHAN_15 Selects channel 15 2031 // CHAN_14 Selects channel 14 2032 // CHAN_13 Selects channel 13 2033 // CHAN_12 Selects channel 12 2034 // CHAN_11 Selects channel 11 2035 // CHAN_10 Selects channel 10 2036 // CHAN_9 Selects channel 9 2037 // CHAN_8 Selects channel 8 2038 // CHAN_7 Selects channel 7 2039 // CHAN_6 Selects channel 6 2040 // CHAN_5 Selects channel 5 2041 // CHAN_4 Selects channel 4 2042 // CHAN_3 Selects channel 3 2043 // CHAN_2 Selects channel 2 2044 // CHAN_1 Selects channel 1 2045 // CHAN_0 Selects channel 0 2046 #define ADC_MEMCTL0_CHANSEL_W 5U 2047 #define ADC_MEMCTL0_CHANSEL_M 0x0000001FU 2048 #define ADC_MEMCTL0_CHANSEL_S 0U 2049 #define ADC_MEMCTL0_CHANSEL_CHAN_15 0x0000000FU 2050 #define ADC_MEMCTL0_CHANSEL_CHAN_14 0x0000000EU 2051 #define ADC_MEMCTL0_CHANSEL_CHAN_13 0x0000000DU 2052 #define ADC_MEMCTL0_CHANSEL_CHAN_12 0x0000000CU 2053 #define ADC_MEMCTL0_CHANSEL_CHAN_11 0x0000000BU 2054 #define ADC_MEMCTL0_CHANSEL_CHAN_10 0x0000000AU 2055 #define ADC_MEMCTL0_CHANSEL_CHAN_9 0x00000009U 2056 #define ADC_MEMCTL0_CHANSEL_CHAN_8 0x00000008U 2057 #define ADC_MEMCTL0_CHANSEL_CHAN_7 0x00000007U 2058 #define ADC_MEMCTL0_CHANSEL_CHAN_6 0x00000006U 2059 #define ADC_MEMCTL0_CHANSEL_CHAN_5 0x00000005U 2060 #define ADC_MEMCTL0_CHANSEL_CHAN_4 0x00000004U 2061 #define ADC_MEMCTL0_CHANSEL_CHAN_3 0x00000003U 2062 #define ADC_MEMCTL0_CHANSEL_CHAN_2 0x00000002U 2063 #define ADC_MEMCTL0_CHANSEL_CHAN_1 0x00000001U 2064 #define ADC_MEMCTL0_CHANSEL_CHAN_0 0x00000000U 2065 2066 //***************************************************************************** 2067 // 2068 // Register: ADC_O_MEMCTL1 2069 // 2070 //***************************************************************************** 2071 // Field: [28] WINCOMP 2072 // 2073 // Enable window comparator. 2074 // ENUMs: 2075 // EN Enable 2076 // DIS Disable 2077 #define ADC_MEMCTL1_WINCOMP 0x10000000U 2078 #define ADC_MEMCTL1_WINCOMP_M 0x10000000U 2079 #define ADC_MEMCTL1_WINCOMP_S 28U 2080 #define ADC_MEMCTL1_WINCOMP_EN 0x10000000U 2081 #define ADC_MEMCTL1_WINCOMP_DIS 0x00000000U 2082 2083 // Field: [24] TRG 2084 // 2085 // Trigger policy. Indicates if a trigger will be needed to step to the next 2086 // MEMCTL in the sequence or to perform next conversion in the case of repeat 2087 // single channel conversions. 2088 // ENUMs: 2089 // TRIGGER_NEXT Next conversion requires a trigger 2090 // AUTO_NEXT Next conversion is automatic 2091 #define ADC_MEMCTL1_TRG 0x01000000U 2092 #define ADC_MEMCTL1_TRG_M 0x01000000U 2093 #define ADC_MEMCTL1_TRG_S 24U 2094 #define ADC_MEMCTL1_TRG_TRIGGER_NEXT 0x01000000U 2095 #define ADC_MEMCTL1_TRG_AUTO_NEXT 0x00000000U 2096 2097 // Field: [12] STIME 2098 // 2099 // Selects the source of sample timer period between SCOMP0 and SCOMP1. 2100 // ENUMs: 2101 // SEL_SCOMP1 Select SCOMP1 2102 // SEL_SCOMP0 Select SCOMP0 2103 #define ADC_MEMCTL1_STIME 0x00001000U 2104 #define ADC_MEMCTL1_STIME_M 0x00001000U 2105 #define ADC_MEMCTL1_STIME_S 12U 2106 #define ADC_MEMCTL1_STIME_SEL_SCOMP1 0x00001000U 2107 #define ADC_MEMCTL1_STIME_SEL_SCOMP0 0x00000000U 2108 2109 // Field: [9:8] VRSEL 2110 // 2111 // Voltage reference selection. AREF- must be connected to on-board ground when 2112 // external reference option is selected. 2113 // Note: Writing value 0x3 defaults to INTREF. 2114 // ENUMs: 2115 // INTREF Internal reference 2116 // EXTREF External reference from AREF+/AREF- pins 2117 // VDDS VDDS reference 2118 #define ADC_MEMCTL1_VRSEL_W 2U 2119 #define ADC_MEMCTL1_VRSEL_M 0x00000300U 2120 #define ADC_MEMCTL1_VRSEL_S 8U 2121 #define ADC_MEMCTL1_VRSEL_INTREF 0x00000200U 2122 #define ADC_MEMCTL1_VRSEL_EXTREF 0x00000100U 2123 #define ADC_MEMCTL1_VRSEL_VDDS 0x00000000U 2124 2125 // Field: [4:0] CHANSEL 2126 // 2127 // Input channel select. 2128 // ENUMs: 2129 // CHAN_15 Selects channel 15 2130 // CHAN_14 Selects channel 14 2131 // CHAN_13 Selects channel 13 2132 // CHAN_12 Selects channel 12 2133 // CHAN_11 Selects channel 11 2134 // CHAN_10 Selects channel 10 2135 // CHAN_9 Selects channel 9 2136 // CHAN_8 Selects channel 8 2137 // CHAN_7 Selects channel 7 2138 // CHAN_6 Selects channel 6 2139 // CHAN_5 Selects channel 5 2140 // CHAN_4 Selects channel 4 2141 // CHAN_3 Selects channel 3 2142 // CHAN_2 Selects channel 2 2143 // CHAN_1 Selects channel 1 2144 // CHAN_0 Selects channel 0 2145 #define ADC_MEMCTL1_CHANSEL_W 5U 2146 #define ADC_MEMCTL1_CHANSEL_M 0x0000001FU 2147 #define ADC_MEMCTL1_CHANSEL_S 0U 2148 #define ADC_MEMCTL1_CHANSEL_CHAN_15 0x0000000FU 2149 #define ADC_MEMCTL1_CHANSEL_CHAN_14 0x0000000EU 2150 #define ADC_MEMCTL1_CHANSEL_CHAN_13 0x0000000DU 2151 #define ADC_MEMCTL1_CHANSEL_CHAN_12 0x0000000CU 2152 #define ADC_MEMCTL1_CHANSEL_CHAN_11 0x0000000BU 2153 #define ADC_MEMCTL1_CHANSEL_CHAN_10 0x0000000AU 2154 #define ADC_MEMCTL1_CHANSEL_CHAN_9 0x00000009U 2155 #define ADC_MEMCTL1_CHANSEL_CHAN_8 0x00000008U 2156 #define ADC_MEMCTL1_CHANSEL_CHAN_7 0x00000007U 2157 #define ADC_MEMCTL1_CHANSEL_CHAN_6 0x00000006U 2158 #define ADC_MEMCTL1_CHANSEL_CHAN_5 0x00000005U 2159 #define ADC_MEMCTL1_CHANSEL_CHAN_4 0x00000004U 2160 #define ADC_MEMCTL1_CHANSEL_CHAN_3 0x00000003U 2161 #define ADC_MEMCTL1_CHANSEL_CHAN_2 0x00000002U 2162 #define ADC_MEMCTL1_CHANSEL_CHAN_1 0x00000001U 2163 #define ADC_MEMCTL1_CHANSEL_CHAN_0 0x00000000U 2164 2165 //***************************************************************************** 2166 // 2167 // Register: ADC_O_MEMCTL2 2168 // 2169 //***************************************************************************** 2170 // Field: [28] WINCOMP 2171 // 2172 // Enable window comparator. 2173 // ENUMs: 2174 // EN Enable 2175 // DIS Disable 2176 #define ADC_MEMCTL2_WINCOMP 0x10000000U 2177 #define ADC_MEMCTL2_WINCOMP_M 0x10000000U 2178 #define ADC_MEMCTL2_WINCOMP_S 28U 2179 #define ADC_MEMCTL2_WINCOMP_EN 0x10000000U 2180 #define ADC_MEMCTL2_WINCOMP_DIS 0x00000000U 2181 2182 // Field: [24] TRG 2183 // 2184 // Trigger policy. Indicates if a trigger will be needed to step to the next 2185 // MEMCTL in the sequence or to perform next conversion in the case of repeat 2186 // single channel conversions. 2187 // ENUMs: 2188 // TRIGGER_NEXT Next conversion requires a trigger 2189 // AUTO_NEXT Next conversion is automatic 2190 #define ADC_MEMCTL2_TRG 0x01000000U 2191 #define ADC_MEMCTL2_TRG_M 0x01000000U 2192 #define ADC_MEMCTL2_TRG_S 24U 2193 #define ADC_MEMCTL2_TRG_TRIGGER_NEXT 0x01000000U 2194 #define ADC_MEMCTL2_TRG_AUTO_NEXT 0x00000000U 2195 2196 // Field: [12] STIME 2197 // 2198 // Selects the source of sample timer period between SCOMP0 and SCOMP1. 2199 // ENUMs: 2200 // SEL_SCOMP1 Select SCOMP1 2201 // SEL_SCOMP0 Select SCOMP0 2202 #define ADC_MEMCTL2_STIME 0x00001000U 2203 #define ADC_MEMCTL2_STIME_M 0x00001000U 2204 #define ADC_MEMCTL2_STIME_S 12U 2205 #define ADC_MEMCTL2_STIME_SEL_SCOMP1 0x00001000U 2206 #define ADC_MEMCTL2_STIME_SEL_SCOMP0 0x00000000U 2207 2208 // Field: [9:8] VRSEL 2209 // 2210 // Voltage reference selection. AREF- must be connected to on-board ground when 2211 // external reference option is selected. 2212 // Note: Writing value 0x3 defaults to INTREF. 2213 // ENUMs: 2214 // INTREF Internal reference 2215 // EXTREF External reference from AREF+/AREF- pins 2216 // VDDS VDDS reference 2217 #define ADC_MEMCTL2_VRSEL_W 2U 2218 #define ADC_MEMCTL2_VRSEL_M 0x00000300U 2219 #define ADC_MEMCTL2_VRSEL_S 8U 2220 #define ADC_MEMCTL2_VRSEL_INTREF 0x00000200U 2221 #define ADC_MEMCTL2_VRSEL_EXTREF 0x00000100U 2222 #define ADC_MEMCTL2_VRSEL_VDDS 0x00000000U 2223 2224 // Field: [4:0] CHANSEL 2225 // 2226 // Input channel select. 2227 // ENUMs: 2228 // CHAN_15 Selects channel 15 2229 // CHAN_14 Selects channel 14 2230 // CHAN_13 Selects channel 13 2231 // CHAN_12 Selects channel 12 2232 // CHAN_11 Selects channel 11 2233 // CHAN_10 Selects channel 10 2234 // CHAN_9 Selects channel 9 2235 // CHAN_8 Selects channel 8 2236 // CHAN_7 Selects channel 7 2237 // CHAN_6 Selects channel 6 2238 // CHAN_5 Selects channel 5 2239 // CHAN_4 Selects channel 4 2240 // CHAN_3 Selects channel 3 2241 // CHAN_2 Selects channel 2 2242 // CHAN_1 Selects channel 1 2243 // CHAN_0 Selects channel 0 2244 #define ADC_MEMCTL2_CHANSEL_W 5U 2245 #define ADC_MEMCTL2_CHANSEL_M 0x0000001FU 2246 #define ADC_MEMCTL2_CHANSEL_S 0U 2247 #define ADC_MEMCTL2_CHANSEL_CHAN_15 0x0000000FU 2248 #define ADC_MEMCTL2_CHANSEL_CHAN_14 0x0000000EU 2249 #define ADC_MEMCTL2_CHANSEL_CHAN_13 0x0000000DU 2250 #define ADC_MEMCTL2_CHANSEL_CHAN_12 0x0000000CU 2251 #define ADC_MEMCTL2_CHANSEL_CHAN_11 0x0000000BU 2252 #define ADC_MEMCTL2_CHANSEL_CHAN_10 0x0000000AU 2253 #define ADC_MEMCTL2_CHANSEL_CHAN_9 0x00000009U 2254 #define ADC_MEMCTL2_CHANSEL_CHAN_8 0x00000008U 2255 #define ADC_MEMCTL2_CHANSEL_CHAN_7 0x00000007U 2256 #define ADC_MEMCTL2_CHANSEL_CHAN_6 0x00000006U 2257 #define ADC_MEMCTL2_CHANSEL_CHAN_5 0x00000005U 2258 #define ADC_MEMCTL2_CHANSEL_CHAN_4 0x00000004U 2259 #define ADC_MEMCTL2_CHANSEL_CHAN_3 0x00000003U 2260 #define ADC_MEMCTL2_CHANSEL_CHAN_2 0x00000002U 2261 #define ADC_MEMCTL2_CHANSEL_CHAN_1 0x00000001U 2262 #define ADC_MEMCTL2_CHANSEL_CHAN_0 0x00000000U 2263 2264 //***************************************************************************** 2265 // 2266 // Register: ADC_O_MEMCTL3 2267 // 2268 //***************************************************************************** 2269 // Field: [28] WINCOMP 2270 // 2271 // Enable window comparator. 2272 // ENUMs: 2273 // EN Enable 2274 // DIS Disable 2275 #define ADC_MEMCTL3_WINCOMP 0x10000000U 2276 #define ADC_MEMCTL3_WINCOMP_M 0x10000000U 2277 #define ADC_MEMCTL3_WINCOMP_S 28U 2278 #define ADC_MEMCTL3_WINCOMP_EN 0x10000000U 2279 #define ADC_MEMCTL3_WINCOMP_DIS 0x00000000U 2280 2281 // Field: [24] TRG 2282 // 2283 // Trigger policy. Indicates if a trigger will be needed to step to the next 2284 // MEMCTL in the sequence or to perform next conversion in the case of repeat 2285 // single channel conversions. 2286 // ENUMs: 2287 // TRIGGER_NEXT Next conversion requires a trigger 2288 // AUTO_NEXT Next conversion is automatic 2289 #define ADC_MEMCTL3_TRG 0x01000000U 2290 #define ADC_MEMCTL3_TRG_M 0x01000000U 2291 #define ADC_MEMCTL3_TRG_S 24U 2292 #define ADC_MEMCTL3_TRG_TRIGGER_NEXT 0x01000000U 2293 #define ADC_MEMCTL3_TRG_AUTO_NEXT 0x00000000U 2294 2295 // Field: [12] STIME 2296 // 2297 // Selects the source of sample timer period between SCOMP0 and SCOMP1. 2298 // ENUMs: 2299 // SEL_SCOMP1 Select SCOMP1 2300 // SEL_SCOMP0 Select SCOMP0 2301 #define ADC_MEMCTL3_STIME 0x00001000U 2302 #define ADC_MEMCTL3_STIME_M 0x00001000U 2303 #define ADC_MEMCTL3_STIME_S 12U 2304 #define ADC_MEMCTL3_STIME_SEL_SCOMP1 0x00001000U 2305 #define ADC_MEMCTL3_STIME_SEL_SCOMP0 0x00000000U 2306 2307 // Field: [9:8] VRSEL 2308 // 2309 // Voltage reference selection. AREF- must be connected to on-board ground when 2310 // external reference option is selected. 2311 // Note: Writing value 0x3 defaults to INTREF. 2312 // ENUMs: 2313 // INTREF Internal reference 2314 // EXTREF External reference from AREF+/AREF- pins 2315 // VDDS VDDS reference 2316 #define ADC_MEMCTL3_VRSEL_W 2U 2317 #define ADC_MEMCTL3_VRSEL_M 0x00000300U 2318 #define ADC_MEMCTL3_VRSEL_S 8U 2319 #define ADC_MEMCTL3_VRSEL_INTREF 0x00000200U 2320 #define ADC_MEMCTL3_VRSEL_EXTREF 0x00000100U 2321 #define ADC_MEMCTL3_VRSEL_VDDS 0x00000000U 2322 2323 // Field: [4:0] CHANSEL 2324 // 2325 // Input channel select. 2326 // ENUMs: 2327 // CHAN_15 Selects channel 15 2328 // CHAN_14 Selects channel 14 2329 // CHAN_13 Selects channel 13 2330 // CHAN_12 Selects channel 12 2331 // CHAN_11 Selects channel 11 2332 // CHAN_10 Selects channel 10 2333 // CHAN_9 Selects channel 9 2334 // CHAN_8 Selects channel 8 2335 // CHAN_7 Selects channel 7 2336 // CHAN_6 Selects channel 6 2337 // CHAN_5 Selects channel 5 2338 // CHAN_4 Selects channel 4 2339 // CHAN_3 Selects channel 3 2340 // CHAN_2 Selects channel 2 2341 // CHAN_1 Selects channel 1 2342 // CHAN_0 Selects channel 0 2343 #define ADC_MEMCTL3_CHANSEL_W 5U 2344 #define ADC_MEMCTL3_CHANSEL_M 0x0000001FU 2345 #define ADC_MEMCTL3_CHANSEL_S 0U 2346 #define ADC_MEMCTL3_CHANSEL_CHAN_15 0x0000000FU 2347 #define ADC_MEMCTL3_CHANSEL_CHAN_14 0x0000000EU 2348 #define ADC_MEMCTL3_CHANSEL_CHAN_13 0x0000000DU 2349 #define ADC_MEMCTL3_CHANSEL_CHAN_12 0x0000000CU 2350 #define ADC_MEMCTL3_CHANSEL_CHAN_11 0x0000000BU 2351 #define ADC_MEMCTL3_CHANSEL_CHAN_10 0x0000000AU 2352 #define ADC_MEMCTL3_CHANSEL_CHAN_9 0x00000009U 2353 #define ADC_MEMCTL3_CHANSEL_CHAN_8 0x00000008U 2354 #define ADC_MEMCTL3_CHANSEL_CHAN_7 0x00000007U 2355 #define ADC_MEMCTL3_CHANSEL_CHAN_6 0x00000006U 2356 #define ADC_MEMCTL3_CHANSEL_CHAN_5 0x00000005U 2357 #define ADC_MEMCTL3_CHANSEL_CHAN_4 0x00000004U 2358 #define ADC_MEMCTL3_CHANSEL_CHAN_3 0x00000003U 2359 #define ADC_MEMCTL3_CHANSEL_CHAN_2 0x00000002U 2360 #define ADC_MEMCTL3_CHANSEL_CHAN_1 0x00000001U 2361 #define ADC_MEMCTL3_CHANSEL_CHAN_0 0x00000000U 2362 2363 //***************************************************************************** 2364 // 2365 // Register: ADC_O_MEMRES0 2366 // 2367 //***************************************************************************** 2368 // Field: [15:0] DATA 2369 // 2370 // If DF = 0, unsigned binary: 2371 // The conversion results are right aligned. In 10 and 8 bit modes, the unused 2372 // MSB bits are forced to 0. 2373 // If DF = 1, 2s-complement format: 2374 // The conversion results are left aligned. In 10 and 8 bit modes, the unused 2375 // LSB bits are forced to 0. 2376 // The data is stored in the right-justified format and is converted to the 2377 // left-justified 2s-complement format during read back. 2378 // 2379 #define ADC_MEMRES0_DATA_W 16U 2380 #define ADC_MEMRES0_DATA_M 0x0000FFFFU 2381 #define ADC_MEMRES0_DATA_S 0U 2382 2383 //***************************************************************************** 2384 // 2385 // Register: ADC_O_MEMRES1 2386 // 2387 //***************************************************************************** 2388 // Field: [15:0] DATA 2389 // 2390 // If DF = 0, unsigned binary: 2391 // The conversion results are right aligned. In 10 and 8 bit modes, the unused 2392 // MSB bits are forced to 0. 2393 // If DF = 1, 2s-complement format: 2394 // The conversion results are left aligned. In 10 and 8 bit modes, the unused 2395 // LSB bits are forced to 0. 2396 // The data is stored in the right-justified format and is converted to the 2397 // left-justified 2s-complement format during read back. 2398 // 2399 #define ADC_MEMRES1_DATA_W 16U 2400 #define ADC_MEMRES1_DATA_M 0x0000FFFFU 2401 #define ADC_MEMRES1_DATA_S 0U 2402 2403 //***************************************************************************** 2404 // 2405 // Register: ADC_O_MEMRES2 2406 // 2407 //***************************************************************************** 2408 // Field: [15:0] DATA 2409 // 2410 // If DF = 0, unsigned binary: 2411 // The conversion results are right aligned. In 10 and 8 bit modes, the unused 2412 // MSB bits are forced to 0. 2413 // If DF = 1, 2s-complement format: 2414 // The conversion results are left aligned. In 10 and 8 bit modes, the unused 2415 // LSB bits are forced to 0. 2416 // The data is stored in the right-justified format and is converted to the 2417 // left-justified 2s-complement format during read back. 2418 // 2419 #define ADC_MEMRES2_DATA_W 16U 2420 #define ADC_MEMRES2_DATA_M 0x0000FFFFU 2421 #define ADC_MEMRES2_DATA_S 0U 2422 2423 //***************************************************************************** 2424 // 2425 // Register: ADC_O_MEMRES3 2426 // 2427 //***************************************************************************** 2428 // Field: [15:0] DATA 2429 // 2430 // If DF = 0, unsigned binary: 2431 // The conversion results are right aligned. In 10 and 8 bit modes, the unused 2432 // MSB bits are forced to 0. 2433 // If DF = 1, 2s-complement format: 2434 // The conversion results are left aligned. In 10 and 8 bit modes, the unused 2435 // LSB bits are forced to 0. 2436 // The data is stored in the right-justified format and is converted to the 2437 // left-justified 2s-complement format during read back. 2438 // 2439 #define ADC_MEMRES3_DATA_W 16U 2440 #define ADC_MEMRES3_DATA_M 0x0000FFFFU 2441 #define ADC_MEMRES3_DATA_S 0U 2442 2443 //***************************************************************************** 2444 // 2445 // Register: ADC_O_STA 2446 // 2447 //***************************************************************************** 2448 // Field: [2] ASCACT 2449 // 2450 // ASC active 2451 // ENUMs: 2452 // ACTIVE ASC active 2453 // IDLE Idle or done 2454 #define ADC_STA_ASCACT 0x00000004U 2455 #define ADC_STA_ASCACT_M 0x00000004U 2456 #define ADC_STA_ASCACT_S 2U 2457 #define ADC_STA_ASCACT_ACTIVE 0x00000004U 2458 #define ADC_STA_ASCACT_IDLE 0x00000000U 2459 2460 // Field: [0] BUSY 2461 // 2462 // Busy. This bit indicates that an active ADC sample or conversion operation 2463 // is in progress. 2464 // ENUMs: 2465 // ACTIVE ADC sampling or conversion is in progress. 2466 // IDLE No ADC sampling or conversion in progress. 2467 #define ADC_STA_BUSY 0x00000001U 2468 #define ADC_STA_BUSY_M 0x00000001U 2469 #define ADC_STA_BUSY_S 0U 2470 #define ADC_STA_BUSY_ACTIVE 0x00000001U 2471 #define ADC_STA_BUSY_IDLE 0x00000000U 2472 2473 //***************************************************************************** 2474 // 2475 // Register: ADC_O_TEST0 2476 // 2477 //***************************************************************************** 2478 // Field: [30] ATEST0_EN 2479 // 2480 // Internal. Only to be used through TI provided API. 2481 // ENUMs: 2482 // EN Internal. Only to be used through TI provided API. 2483 // DIS Internal. Only to be used through TI provided API. 2484 #define ADC_TEST0_ATEST0_EN 0x40000000U 2485 #define ADC_TEST0_ATEST0_EN_M 0x40000000U 2486 #define ADC_TEST0_ATEST0_EN_S 30U 2487 #define ADC_TEST0_ATEST0_EN_EN 0x40000000U 2488 #define ADC_TEST0_ATEST0_EN_DIS 0x00000000U 2489 2490 // Field: [29] ATEST1_EN 2491 // 2492 // Internal. Only to be used through TI provided API. 2493 // ENUMs: 2494 // EN Internal. Only to be used through TI provided API. 2495 // DIS Internal. Only to be used through TI provided API. 2496 #define ADC_TEST0_ATEST1_EN 0x20000000U 2497 #define ADC_TEST0_ATEST1_EN_M 0x20000000U 2498 #define ADC_TEST0_ATEST1_EN_S 29U 2499 #define ADC_TEST0_ATEST1_EN_EN 0x20000000U 2500 #define ADC_TEST0_ATEST1_EN_DIS 0x00000000U 2501 2502 // Field: [12:8] ATEST1_MUXSEL 2503 // 2504 // Internal. Only to be used through TI provided API. 2505 // ENUMs: 2506 // VAL16 Internal. Only to be used through TI provided API. 2507 // VAL8 Internal. Only to be used through TI provided API. 2508 // VAL4 Internal. Only to be used through TI provided API. 2509 // VAL2 Internal. Only to be used through TI provided API. 2510 // VAL1 Internal. Only to be used through TI provided API. 2511 #define ADC_TEST0_ATEST1_MUXSEL_W 5U 2512 #define ADC_TEST0_ATEST1_MUXSEL_M 0x00001F00U 2513 #define ADC_TEST0_ATEST1_MUXSEL_S 8U 2514 #define ADC_TEST0_ATEST1_MUXSEL_VAL16 0x00001000U 2515 #define ADC_TEST0_ATEST1_MUXSEL_VAL8 0x00000800U 2516 #define ADC_TEST0_ATEST1_MUXSEL_VAL4 0x00000400U 2517 #define ADC_TEST0_ATEST1_MUXSEL_VAL2 0x00000200U 2518 #define ADC_TEST0_ATEST1_MUXSEL_VAL1 0x00000100U 2519 2520 // Field: [4:0] ATEST0_MUXSEL 2521 // 2522 // Internal. Only to be used through TI provided API. 2523 // ENUMs: 2524 // VAL16 Internal. Only to be used through TI provided API. 2525 // VAL8 Internal. Only to be used through TI provided API. 2526 // VAL4 Internal. Only to be used through TI provided API. 2527 // VAL2 Internal. Only to be used through TI provided API. 2528 // VAL1 Internal. Only to be used through TI provided API. 2529 #define ADC_TEST0_ATEST0_MUXSEL_W 5U 2530 #define ADC_TEST0_ATEST0_MUXSEL_M 0x0000001FU 2531 #define ADC_TEST0_ATEST0_MUXSEL_S 0U 2532 #define ADC_TEST0_ATEST0_MUXSEL_VAL16 0x00000010U 2533 #define ADC_TEST0_ATEST0_MUXSEL_VAL8 0x00000008U 2534 #define ADC_TEST0_ATEST0_MUXSEL_VAL4 0x00000004U 2535 #define ADC_TEST0_ATEST0_MUXSEL_VAL2 0x00000002U 2536 #define ADC_TEST0_ATEST0_MUXSEL_VAL1 0x00000001U 2537 2538 //***************************************************************************** 2539 // 2540 // Register: ADC_O_TEST2 2541 // 2542 //***************************************************************************** 2543 // Field: [31] CDAC_OVST_EN 2544 // 2545 // Internal. Only to be used through TI provided API. 2546 #define ADC_TEST2_CDAC_OVST_EN 0x80000000U 2547 #define ADC_TEST2_CDAC_OVST_EN_M 0x80000000U 2548 #define ADC_TEST2_CDAC_OVST_EN_S 31U 2549 2550 // Field: [24] LATCH_TRIM_EN 2551 // 2552 // Internal. Only to be used through TI provided API. 2553 #define ADC_TEST2_LATCH_TRIM_EN 0x01000000U 2554 #define ADC_TEST2_LATCH_TRIM_EN_M 0x01000000U 2555 #define ADC_TEST2_LATCH_TRIM_EN_S 24U 2556 2557 // Field: [20] COMP_GAIN_TRIM 2558 // 2559 // Internal. Only to be used through TI provided API. 2560 #define ADC_TEST2_COMP_GAIN_TRIM 0x00100000U 2561 #define ADC_TEST2_COMP_GAIN_TRIM_M 0x00100000U 2562 #define ADC_TEST2_COMP_GAIN_TRIM_S 20U 2563 2564 // Field: [8] MUX_TEST_SEL 2565 // 2566 // Internal. Only to be used through TI provided API. 2567 #define ADC_TEST2_MUX_TEST_SEL 0x00000100U 2568 #define ADC_TEST2_MUX_TEST_SEL_M 0x00000100U 2569 #define ADC_TEST2_MUX_TEST_SEL_S 8U 2570 2571 //***************************************************************************** 2572 // 2573 // Register: ADC_O_TEST3 2574 // 2575 //***************************************************************************** 2576 // Field: [31:0] CAL_ACUML 2577 // 2578 // Internal. Only to be used through TI provided API. 2579 #define ADC_TEST3_CAL_ACUML_W 32U 2580 #define ADC_TEST3_CAL_ACUML_M 0xFFFFFFFFU 2581 #define ADC_TEST3_CAL_ACUML_S 0U 2582 2583 //***************************************************************************** 2584 // 2585 // Register: ADC_O_TEST4 2586 // 2587 //***************************************************************************** 2588 // Field: [31] HW_STEP_SEL_DIS 2589 // 2590 // Internal. Only to be used through TI provided API. 2591 #define ADC_TEST4_HW_STEP_SEL_DIS 0x80000000U 2592 #define ADC_TEST4_HW_STEP_SEL_DIS_M 0x80000000U 2593 #define ADC_TEST4_HW_STEP_SEL_DIS_S 31U 2594 2595 // Field: [24] CAL_MODE_EN 2596 // 2597 // Internal. Only to be used through TI provided API. 2598 #define ADC_TEST4_CAL_MODE_EN 0x01000000U 2599 #define ADC_TEST4_CAL_MODE_EN_M 0x01000000U 2600 #define ADC_TEST4_CAL_MODE_EN_S 24U 2601 2602 // Field: [21:16] CAL_STEP_SEL 2603 // 2604 // Internal. Only to be used through TI provided API. 2605 #define ADC_TEST4_CAL_STEP_SEL_W 6U 2606 #define ADC_TEST4_CAL_STEP_SEL_M 0x003F0000U 2607 #define ADC_TEST4_CAL_STEP_SEL_S 16U 2608 2609 //***************************************************************************** 2610 // 2611 // Register: ADC_O_TEST5 2612 // 2613 //***************************************************************************** 2614 // Field: [9:0] CAL_CAP_CTL 2615 // 2616 // Internal. Only to be used through TI provided API. 2617 #define ADC_TEST5_CAL_CAP_CTL_W 10U 2618 #define ADC_TEST5_CAL_CAP_CTL_M 0x000003FFU 2619 #define ADC_TEST5_CAL_CAP_CTL_S 0U 2620 2621 //***************************************************************************** 2622 // 2623 // Register: ADC_O_TEST6 2624 // 2625 //***************************************************************************** 2626 // Field: [3:0] ATESTSEL 2627 // 2628 // Internal. Only to be used through TI provided API. 2629 // ENUMs: 2630 // VAL8 Internal. Only to be used through TI provided API. 2631 // VAL4 Internal. Only to be used through TI provided API. 2632 // VAL2 Internal. Only to be used through TI provided API. 2633 // VAL1 Internal. Only to be used through TI provided API. 2634 // VAL0 Internal. Only to be used through TI provided API. 2635 #define ADC_TEST6_ATESTSEL_W 4U 2636 #define ADC_TEST6_ATESTSEL_M 0x0000000FU 2637 #define ADC_TEST6_ATESTSEL_S 0U 2638 #define ADC_TEST6_ATESTSEL_VAL8 0x00000008U 2639 #define ADC_TEST6_ATESTSEL_VAL4 0x00000004U 2640 #define ADC_TEST6_ATESTSEL_VAL2 0x00000002U 2641 #define ADC_TEST6_ATESTSEL_VAL1 0x00000001U 2642 #define ADC_TEST6_ATESTSEL_VAL0 0x00000000U 2643 2644 //***************************************************************************** 2645 // 2646 // Register: ADC_O_DEBUG1 2647 // 2648 //***************************************************************************** 2649 // Field: [31:0] CTRL 2650 // 2651 // Internal. Only to be used through TI provided API. 2652 #define ADC_DEBUG1_CTRL_W 32U 2653 #define ADC_DEBUG1_CTRL_M 0xFFFFFFFFU 2654 #define ADC_DEBUG1_CTRL_S 0U 2655 2656 //***************************************************************************** 2657 // 2658 // Register: ADC_O_DEBUG2 2659 // 2660 //***************************************************************************** 2661 // Field: [29:28] VTOI_CTRL 2662 // 2663 // Internal. Only to be used through TI provided API. 2664 #define ADC_DEBUG2_VTOI_CTRL_W 2U 2665 #define ADC_DEBUG2_VTOI_CTRL_M 0x30000000U 2666 #define ADC_DEBUG2_VTOI_CTRL_S 28U 2667 2668 // Field: [24] VTOI_TESTMODE_EN 2669 // 2670 // Internal. Only to be used through TI provided API. 2671 #define ADC_DEBUG2_VTOI_TESTMODE_EN 0x01000000U 2672 #define ADC_DEBUG2_VTOI_TESTMODE_EN_M 0x01000000U 2673 #define ADC_DEBUG2_VTOI_TESTMODE_EN_S 24U 2674 2675 //***************************************************************************** 2676 // 2677 // Register: ADC_O_DEBUG3 2678 // 2679 //***************************************************************************** 2680 // Field: [5] DEC1_DIS 2681 // 2682 // Internal. Only to be used through TI provided API. 2683 #define ADC_DEBUG3_DEC1_DIS 0x00000020U 2684 #define ADC_DEBUG3_DEC1_DIS_M 0x00000020U 2685 #define ADC_DEBUG3_DEC1_DIS_S 5U 2686 2687 // Field: [4] DEC0_DIS 2688 // 2689 // Internal. Only to be used through TI provided API. 2690 #define ADC_DEBUG3_DEC0_DIS 0x00000010U 2691 #define ADC_DEBUG3_DEC0_DIS_M 0x00000010U 2692 #define ADC_DEBUG3_DEC0_DIS_S 4U 2693 2694 // Field: [0] BOOST_ENZ 2695 // 2696 // Internal. Only to be used through TI provided API. 2697 #define ADC_DEBUG3_BOOST_ENZ 0x00000001U 2698 #define ADC_DEBUG3_BOOST_ENZ_M 0x00000001U 2699 #define ADC_DEBUG3_BOOST_ENZ_S 0U 2700 2701 //***************************************************************************** 2702 // 2703 // Register: ADC_O_DEBUG4 2704 // 2705 //***************************************************************************** 2706 // Field: [15:0] ADC_CTRL0 2707 // 2708 // Internal. Only to be used through TI provided API. 2709 #define ADC_DEBUG4_ADC_CTRL0_W 16U 2710 #define ADC_DEBUG4_ADC_CTRL0_M 0x0000FFFFU 2711 #define ADC_DEBUG4_ADC_CTRL0_S 0U 2712 2713 2714 #endif // __ADC__ 2715
