1 /* 2 * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #pragma once 8 9 #include "esp_err.h" 10 #include "soc/soc_caps.h" 11 #include "hal/dma_types.h" 12 #include "hal/adc_types.h" 13 #include "hal/adc_ll.h" 14 #include "hal/adc_hal_common.h" 15 #include "esp_err.h" 16 17 #if SOC_GDMA_SUPPORTED 18 #include "soc/gdma_struct.h" 19 #include "hal/gdma_ll.h" 20 #endif 21 22 #if CONFIG_IDF_TARGET_ESP32S2 23 //ADC utilises SPI3 DMA on ESP32S2 24 #include "hal/spi_ll.h" 25 #endif 26 27 #if CONFIG_IDF_TARGET_ESP32 28 //ADC utilises I2S0 DMA on ESP32 29 #include "hal/i2s_ll.h" 30 #endif 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if SOC_GDMA_SUPPORTED 37 #define ADC_HAL_DMA_INTR_MASK GDMA_LL_EVENT_RX_SUC_EOF 38 #elif CONFIG_IDF_TARGET_ESP32S2 39 #define ADC_HAL_DMA_INTR_MASK SPI_LL_INTR_IN_SUC_EOF 40 #else //CONFIG_IDF_TARGET_ESP32 41 #define ADC_HAL_DMA_INTR_MASK BIT(9) 42 #endif 43 44 /** 45 * @brief Enum for DMA descriptor status 46 */ 47 typedef enum adc_hal_dma_desc_status_t { 48 ADC_HAL_DMA_DESC_VALID = 0, ///< This DMA descriptor is written by HW already 49 ADC_HAL_DMA_DESC_WAITING = 1, ///< This DMA descriptor is not written by HW yet 50 ADC_HAL_DMA_DESC_NULL = 2 ///< This DMA descriptor is NULL 51 } adc_hal_dma_desc_status_t; 52 53 /** 54 * @brief Configuration of the HAL 55 */ 56 typedef struct adc_hal_dma_config_t { 57 void *dev; ///< DMA peripheral address 58 uint32_t eof_desc_num; ///< Number of dma descriptors that is eof 59 uint32_t eof_step; ///< Number of linked descriptors that is one eof 60 uint32_t dma_chan; ///< DMA channel to be used 61 uint32_t eof_num; ///< Bytes between 2 in_suc_eof interrupts 62 } adc_hal_dma_config_t; 63 64 /** 65 * @brief Context of the HAL 66 */ 67 typedef struct adc_hal_dma_ctx_t { 68 /**< this needs to be malloced by the driver layer first */ 69 dma_descriptor_t *rx_desc; ///< DMA descriptors 70 71 /**< these will be assigned by hal layer itself */ 72 dma_descriptor_t desc_dummy_head; ///< Dummy DMA descriptor for ``cur_desc_ptr`` to start 73 dma_descriptor_t *cur_desc_ptr; ///< Pointer to the current descriptor 74 75 /**< these need to be configured by `adc_hal_dma_config_t` via driver layer*/ 76 void *dev; ///< DMA address 77 uint32_t eof_desc_num; ///< Number of dma descriptors that is eof 78 uint32_t eof_step; ///< Number of linked descriptors that is one eof 79 uint32_t dma_chan; ///< DMA channel to be used 80 uint32_t eof_num; ///< Words between 2 in_suc_eof interrupts 81 } adc_hal_dma_ctx_t; 82 83 typedef struct adc_hal_digi_ctrlr_cfg_t { 84 uint32_t adc_pattern_len; //total pattern item number, including ADC1 and ADC2 85 adc_digi_pattern_config_t *adc_pattern; //pattern item 86 uint32_t sample_freq_hz; //ADC sample frequency 87 adc_digi_convert_mode_t conv_mode; //controller work mode 88 uint32_t bit_width; //output data width 89 adc_continuous_clk_src_t clk_src; ///< Clock source 90 uint32_t clk_src_freq_hz; ///< Clock source frequency in hz 91 } adc_hal_digi_ctrlr_cfg_t; 92 93 94 /*--------------------------------------------------------------- 95 PWDET(Power detect) controller setting 96 ---------------------------------------------------------------*/ 97 /** 98 * Set adc cct for PWDET controller. 99 * 100 * @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY. 101 * @prarm cct Range: 0 ~ 7. 102 */ 103 #define adc_hal_pwdet_set_cct(cct) adc_ll_pwdet_set_cct(cct) 104 105 /** 106 * Get adc cct for PWDET controller. 107 * 108 * @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY. 109 * @return cct Range: 0 ~ 7. 110 */ 111 #define adc_hal_pwdet_get_cct() adc_ll_pwdet_get_cct() 112 113 /*--------------------------------------------------------------- 114 Digital controller setting 115 ---------------------------------------------------------------*/ 116 /** 117 * @brief Initialize the HW 118 * 119 * @param hal Context of the HAL 120 */ 121 void adc_hal_digi_init(adc_hal_dma_ctx_t *hal); 122 123 /** 124 * Digital controller deinitialization. 125 * 126 * @param hal Context of the HAL 127 */ 128 void adc_hal_digi_deinit(adc_hal_dma_ctx_t *hal); 129 130 /** 131 * @brief Initialize the hal context 132 * 133 * @param hal Context of the HAL 134 * @param config Configuration of the HAL 135 */ 136 void adc_hal_dma_ctx_config(adc_hal_dma_ctx_t *hal, const adc_hal_dma_config_t *config); 137 138 /** 139 * Setting the digital controller. 140 * 141 * @param hal Context of the HAL 142 * @param cfg Pointer to digital controller paramter. 143 */ 144 void adc_hal_digi_controller_config(adc_hal_dma_ctx_t *hal, const adc_hal_digi_ctrlr_cfg_t *cfg); 145 146 /** 147 * @brief Start Conversion 148 * 149 * @param hal Context of the HAL 150 * @param data_buf Pointer to the data buffer, the length should be multiple of ``desc_max_num`` and ``eof_num`` in ``adc_hal_dma_ctx_t`` 151 */ 152 void adc_hal_digi_start(adc_hal_dma_ctx_t *hal, uint8_t *data_buf); 153 154 #if !SOC_GDMA_SUPPORTED 155 /** 156 * @brief Get the DMA descriptor that Hardware has finished processing. 157 * 158 * @param hal Context of the HAL 159 * 160 * @return DMA descriptor address 161 */ 162 intptr_t adc_hal_get_desc_addr(adc_hal_dma_ctx_t *hal); 163 164 /** 165 * @brief Check the hardware interrupt event 166 * 167 * @param hal Context of the HAL 168 * @param mask Event mask 169 * 170 * @return True: the event is triggered. False: the event is not triggered yet. 171 */ 172 bool adc_hal_check_event(adc_hal_dma_ctx_t *hal, uint32_t mask); 173 #endif 174 175 /** 176 * @brief Get the ADC reading result 177 * 178 * @param hal Context of the HAL 179 * @param eof_desc_addr The last descriptor that is finished by HW. Should be got from DMA 180 * @param[out] buffer ADC reading result buffer 181 * @param[out] len ADC reading result len 182 * 183 * @return See ``adc_hal_dma_desc_status_t`` 184 */ 185 adc_hal_dma_desc_status_t adc_hal_get_reading_result(adc_hal_dma_ctx_t *hal, const intptr_t eof_desc_addr, uint8_t **buffer, uint32_t *len); 186 187 /** 188 * @brief Clear interrupt 189 * 190 * @param hal Context of the HAL 191 * @param mask mask of the interrupt 192 */ 193 void adc_hal_digi_clr_intr(adc_hal_dma_ctx_t *hal, uint32_t mask); 194 195 /** 196 * @brief Enable interrupt 197 * 198 * @param hal Context of the HAL 199 * @param mask mask of the interrupt 200 */ 201 void adc_hal_digi_dis_intr(adc_hal_dma_ctx_t *hal, uint32_t mask); 202 203 /** 204 * @brief Stop conversion 205 * 206 * @param hal Context of the HAL 207 */ 208 void adc_hal_digi_stop(adc_hal_dma_ctx_t *hal); 209 210 #if ADC_LL_WORKAROUND_CLEAR_EOF_COUNTER 211 /** 212 * @brief Clear the ADC sample counter 213 */ 214 void adc_hal_digi_clr_eof(void); 215 #endif 216 217 #ifdef __cplusplus 218 } 219 #endif 220
