1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2021 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include "fsl_adc_etc.h"
10
11 /* Component ID definition, used by tools. */
12 #ifndef FSL_COMPONENT_ID
13 #define FSL_COMPONENT_ID "platform.drivers.adc_etc"
14 #endif
15
16 /*******************************************************************************
17 * Prototypes
18 ******************************************************************************/
19 #if defined(ADC_ETC_CLOCKS)
20 /*!
21 * @brief Get instance number for ADC_ETC module.
22 *
23 * @param base ADC_ETC peripheral base address
24 */
25 static uint32_t ADC_ETC_GetInstance(ADC_ETC_Type *base);
26
27 /*******************************************************************************
28 * Variables
29 ******************************************************************************/
30 /*! @brief Pointers to ADC_ETC bases for each instance. */
31 static ADC_ETC_Type *const s_adcetcBases[] = ADC_ETC_BASE_PTRS;
32 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
33 /*! @brief Pointers to ADC_ETC clocks for each instance. */
34 static const clock_ip_name_t s_adcetcClocks[] = ADC_ETC_CLOCKS;
35 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
36
37 /*******************************************************************************
38 * Code
39 ******************************************************************************/
ADC_ETC_GetInstance(ADC_ETC_Type * base)40 static uint32_t ADC_ETC_GetInstance(ADC_ETC_Type *base)
41 {
42 uint32_t instance = 0U;
43 uint32_t adcetcArrayCount = (sizeof(s_adcetcBases) / sizeof(s_adcetcBases[0]));
44
45 /* Find the instance index from base address mappings. */
46 for (instance = 0; instance < adcetcArrayCount; instance++)
47 {
48 if (s_adcetcBases[instance] == base)
49 {
50 break;
51 }
52 }
53
54 assert(instance < adcetcArrayCount);
55
56 return instance;
57 }
58 #endif /* ADC_ETC_CLOCKS */
59
60 /*!
61 * brief Initialize the ADC_ETC module.
62 *
63 * param base ADC_ETC peripheral base address.
64 * param config Pointer to "adc_etc_config_t" structure.
65 */
ADC_ETC_Init(ADC_ETC_Type * base,const adc_etc_config_t * config)66 void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config)
67 {
68 assert(NULL != config);
69
70 uint32_t tmp32 = 0U;
71
72 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
73 #if defined(ADC_ETC_CLOCKS)
74 /* Open clock gate. */
75 CLOCK_EnableClock(s_adcetcClocks[ADC_ETC_GetInstance(base)]);
76 #endif /* ADC_ETC_CLOCKS */
77 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
78
79 /* Disable software reset. */
80 ADC_ETC_DoSoftwareReset(base, false);
81
82 /* Set ADC_ETC_CTRL register. */
83 tmp32 =
84 #if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
85 ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(config->TSC0triggerPriority) |
86 #endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
87 #if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
88 ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(config->TSC1triggerPriority) |
89 #endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
90 ADC_ETC_CTRL_PRE_DIVIDER(config->clockPreDivider) | ADC_ETC_CTRL_TRIG_ENABLE(config->XBARtriggerMask)
91 #if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
92 | ADC_ETC_CTRL_DMA_MODE_SEL(config->dmaMode)
93 #endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
94 ;
95
96 #if (!(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)) || \
97 (!(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG))
98 if (config->enableTSCBypass)
99 {
100 tmp32 |= ADC_ETC_CTRL_TSC_BYPASS_MASK;
101 }
102 #endif
103 #if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
104 if (config->enableTSC0Trigger)
105 {
106 tmp32 |= ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK;
107 }
108 #endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
109 #if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
110 if (config->enableTSC1Trigger)
111 {
112 tmp32 |= ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK;
113 }
114 #endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
115 base->CTRL = tmp32;
116 }
117
118 /*!
119 * brief De-Initialize the ADC_ETC module.
120 *
121 * param base ADC_ETC peripheral base address.
122 */
ADC_ETC_Deinit(ADC_ETC_Type * base)123 void ADC_ETC_Deinit(ADC_ETC_Type *base)
124 {
125 /* Do software reset to clear all logical. */
126 ADC_ETC_DoSoftwareReset(base, true);
127
128 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
129 #if defined(ADC_ETC_CLOCKS)
130 /* Close clock gate. */
131 CLOCK_DisableClock(s_adcetcClocks[ADC_ETC_GetInstance(base)]);
132 #endif /* ADC_ETC_CLOCKS */
133 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
134 }
135
136 /*!
137 * brief Gets an available pre-defined settings for the ADC_ETC's configuration.
138 * This function initializes the ADC_ETC's configuration structure with available settings. The default values are:
139 * code
140 * config->enableTSCBypass = true;
141 * config->enableTSC0Trigger = false;
142 * config->enableTSC1Trigger = false;
143 * config->TSC0triggerPriority = 0U;
144 * config->TSC1triggerPriority = 0U;
145 * config->clockPreDivider = 0U;
146 * config->XBARtriggerMask = 0U;
147 * endCode
148 *
149 * param config Pointer to "adc_etc_config_t" structure.
150 */
ADC_ETC_GetDefaultConfig(adc_etc_config_t * config)151 void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config)
152 {
153 /* Initializes the configure structure to zero. */
154 (void)memset(config, 0, sizeof(*config));
155
156 #if (!(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)) || \
157 (!(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG))
158 config->enableTSCBypass = true;
159 #endif
160
161 #if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
162 config->enableTSC0Trigger = false;
163 #endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
164
165 #if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
166 config->enableTSC1Trigger = false;
167 #endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
168
169 #if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
170 config->dmaMode = kADC_ETC_TrigDMAWithLatchedSignal;
171 #endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
172
173 #if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
174 config->TSC0triggerPriority = 0U;
175 #endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
176
177 #if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
178 config->TSC1triggerPriority = 0U;
179 #endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
180 config->clockPreDivider = 0U;
181 config->XBARtriggerMask = 0U;
182 }
183
184 /*!
185 * brief Set the external XBAR trigger configuration.
186 *
187 * param base ADC_ETC peripheral base address.
188 * param triggerGroup Trigger group index.
189 * param config Pointer to "adc_etc_trigger_config_t" structure.
190 */
ADC_ETC_SetTriggerConfig(ADC_ETC_Type * base,uint32_t triggerGroup,const adc_etc_trigger_config_t * config)191 void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const adc_etc_trigger_config_t *config)
192 {
193 assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT);
194 assert(ADC_ETC_TRIGn_COUNTER_COUNT > triggerGroup);
195
196 uint32_t tmp32 = 0U;
197
198 /* Set ADC_ETC_TRGn_CTRL register. */
199 tmp32 = ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(config->triggerChainLength) |
200 ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(config->triggerPriority);
201 if (config->enableSyncMode)
202 {
203 tmp32 |= ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK;
204 }
205 if (config->enableSWTriggerMode)
206 {
207 tmp32 |= ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK;
208 }
209 base->TRIG[triggerGroup].TRIGn_CTRL = tmp32;
210
211 /* Set ADC_ETC_TRGn_COUNTER register. */
212 tmp32 = ADC_ETC_TRIGn_COUNTER_INIT_DELAY(config->initialDelay) |
213 ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(config->sampleIntervalDelay);
214 base->TRIG[triggerGroup].TRIGn_COUNTER = tmp32;
215 }
216
217 /*!
218 * brief Set the external XBAR trigger chain configuration.
219 * For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means Trigger0 source's chain1 would be
220 * configurated.
221 *
222 * param base ADC_ETC peripheral base address.
223 * param triggerGroup Trigger group index. Available number is 0~7.
224 * param chainGroup Trigger chain group index. Available number is 0~7.
225 * param config Pointer to "adc_etc_trigger_chain_config_t" structure.
226 */
ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type * base,uint32_t triggerGroup,uint32_t chainGroup,const adc_etc_trigger_chain_config_t * config)227 void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base,
228 uint32_t triggerGroup,
229 uint32_t chainGroup,
230 const adc_etc_trigger_chain_config_t *config)
231 {
232 assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT);
233
234 uint32_t tmp32 = 0U;
235 uint32_t tmpReg = 0U;
236 uint8_t mRemainder = (uint8_t)(chainGroup % 2U);
237
238 /* Set ADC_ETC_TRIGn_CHAINm register. */
239 tmp32 = ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(config->ADCHCRegisterSelect) |
240 ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(config->ADCChannelSelect) |
241 ADC_ETC_TRIGn_CHAIN_1_0_IE0(config->InterruptEnable);
242 if (true == config->enableB2BMode)
243 {
244 tmp32 |= ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK;
245 }
246 #if defined(FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN) && FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN
247 if (true == config->enableIrq)
248 {
249 tmp32 |= ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_MASK;
250 }
251 #endif /* FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN */
252 switch (chainGroup / 2U)
253 {
254 case 0U: /* Configurate trigger chain0 and chain 1. */
255 tmpReg = base->TRIG[triggerGroup].TRIGn_CHAIN_1_0;
256 if (mRemainder == 0U) /* Chain 0. */
257 {
258 tmpReg &= ~(ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK | ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK |
259 ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK | ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK);
260 tmpReg |= tmp32;
261 }
262 else /* Chain 1. */
263 {
264 tmpReg &= ~(ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK | ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK |
265 ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK | ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK);
266 tmpReg |= (tmp32 << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT);
267 }
268 base->TRIG[triggerGroup].TRIGn_CHAIN_1_0 = tmpReg;
269 break;
270 case 1U: /* Configurate trigger chain2 and chain 3. */
271 tmpReg = base->TRIG[triggerGroup].TRIGn_CHAIN_3_2;
272 if (mRemainder == 0U) /* Chain 2. */
273 {
274 tmpReg &= ~(ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK | ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK |
275 ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK | ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK);
276 tmpReg |= tmp32;
277 }
278 else /* Chain 3. */
279 {
280 tmpReg &= ~(ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK | ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK |
281 ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK | ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK);
282 tmpReg |= (tmp32 << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT);
283 }
284 base->TRIG[triggerGroup].TRIGn_CHAIN_3_2 = tmpReg;
285 break;
286 case 2U: /* Configurate trigger chain4 and chain 5. */
287 tmpReg = base->TRIG[triggerGroup].TRIGn_CHAIN_5_4;
288 if (mRemainder == 0U) /* Chain 4. */
289 {
290 tmpReg &= ~(ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK | ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK |
291 ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK | ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK);
292 tmpReg |= tmp32;
293 }
294 else /* Chain 5. */
295 {
296 tmpReg &= ~(ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK | ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK |
297 ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK | ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK);
298 tmpReg |= (tmp32 << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT);
299 }
300 base->TRIG[triggerGroup].TRIGn_CHAIN_5_4 = tmpReg;
301 break;
302 case 3U: /* Configurate trigger chain6 and chain 7. */
303 tmpReg = base->TRIG[triggerGroup].TRIGn_CHAIN_7_6;
304 if (mRemainder == 0U) /* Chain 6. */
305 {
306 tmpReg &= ~(ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK | ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK |
307 ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK | ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK);
308 tmpReg |= tmp32;
309 }
310 else /* Chain 7. */
311 {
312 tmpReg &= ~(ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK | ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK |
313 ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK | ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK);
314 tmpReg |= (tmp32 << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT);
315 }
316 base->TRIG[triggerGroup].TRIGn_CHAIN_7_6 = tmpReg;
317 break;
318 default:
319 assert(false);
320 break;
321 }
322 }
323
324 /*!
325 * brief Gets the interrupt status flags of external XBAR and TSC triggers.
326 *
327 * param base ADC_ETC peripheral base address.
328 * param sourceIndex trigger source index.
329 *
330 * return Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
331 */
ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type * base,adc_etc_external_trigger_source_t sourceIndex)332 uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex)
333 {
334 uint32_t tmp32 = 0U;
335
336 if (((base->DONE0_1_IRQ) & ((uint32_t)ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK << (uint32_t)sourceIndex)) != 0U)
337 {
338 tmp32 |= (uint32_t)kADC_ETC_Done0StatusFlagMask; /* Customized DONE0 status flags mask, which is defined in
339 fsl_adc_etc.h file. */
340 }
341 if (((base->DONE0_1_IRQ) & ((uint32_t)ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK << (uint32_t)sourceIndex)) != 0U)
342 {
343 tmp32 |= (uint32_t)kADC_ETC_Done1StatusFlagMask; /* Customized DONE1 status flags mask, which is defined in
344 fsl_adc_etc.h file. */
345 }
346 if (((base->DONE2_3_ERR_IRQ) & ((uint32_t)ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_MASK << (uint32_t)sourceIndex)) != 0U)
347 {
348 tmp32 |= (uint32_t)kADC_ETC_Done2StatusFlagMask; /* Customized DONE2 status flags mask, which is defined in
349 fsl_adc_etc.h file. */
350 }
351 #if defined(FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN) && FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN
352 if (((base->DONE2_3_ERR_IRQ) & ((uint32_t)ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_MASK << (uint32_t)sourceIndex)) != 0U)
353 {
354 tmp32 |= (uint32_t)kADC_ETC_Done3StatusFlagMask; /* Customized DONE3 status flags mask, which is defined in
355 fsl_adc_etc.h file. */
356 }
357 #endif /* FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN */
358 if (((base->DONE2_3_ERR_IRQ) & ((uint32_t)ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_MASK << (uint32_t)sourceIndex)) != 0U)
359 {
360 tmp32 |= (uint32_t)kADC_ETC_ErrorStatusFlagMask; /* Customized ERROR status flags mask, which is defined in
361 fsl_adc_etc.h file. */
362 }
363 return tmp32;
364 }
365
366 /*!
367 * brief Clears the ADC_ETC's interrupt status falgs.
368 *
369 * param base ADC_ETC peripheral base address.
370 * param sourceIndex trigger source index.
371 * param mask Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
372 */
ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type * base,adc_etc_external_trigger_source_t sourceIndex,uint32_t mask)373 void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex, uint32_t mask)
374 {
375 if (0U != (mask & (uint32_t)kADC_ETC_Done0StatusFlagMask)) /* Write 1 to clear DONE0 status flags. */
376 {
377 base->DONE0_1_IRQ = ((uint32_t)ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK << (uint32_t)sourceIndex);
378 }
379 if (0U != (mask & (uint32_t)kADC_ETC_Done1StatusFlagMask)) /* Write 1 to clear DONE1 status flags. */
380 {
381 base->DONE0_1_IRQ = ((uint32_t)ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK << (uint32_t)sourceIndex);
382 }
383 if (0U != (mask & (uint32_t)kADC_ETC_Done2StatusFlagMask)) /* Write 1 to clear DONE2 status flags. */
384 {
385 base->DONE2_3_ERR_IRQ = ((uint32_t)ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_MASK << (uint32_t)sourceIndex);
386 }
387 #if defined(FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN) && FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN
388 if (0U != (mask & (uint32_t)kADC_ETC_Done3StatusFlagMask)) /* Write 1 to clear DONE3 status flags. */
389 {
390 base->DONE2_3_ERR_IRQ = ((uint32_t)ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_MASK << (uint32_t)sourceIndex);
391 }
392 #endif /* FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN */
393 if (0U != (mask & (uint32_t)kADC_ETC_ErrorStatusFlagMask)) /* Write 1 to clear ERROR status flags. */
394 {
395 base->DONE2_3_ERR_IRQ = ((uint32_t)ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_MASK << (uint32_t)sourceIndex);
396 }
397 }
398
399 /*!
400 * brief Get ADC conversion result from external XBAR sources.
401 * For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means the API would
402 * return Trigger0 source's chain1 conversion result.
403 *
404 * param base ADC_ETC peripheral base address.
405 * param triggerGroup Trigger group index. Available number is 0~7.
406 * param chainGroup Trigger chain group index. Available number is 0~7.
407 * return ADC conversion result value.
408 */
ADC_ETC_GetADCConversionValue(ADC_ETC_Type * base,uint32_t triggerGroup,uint32_t chainGroup)409 uint32_t ADC_ETC_GetADCConversionValue(ADC_ETC_Type *base, uint32_t triggerGroup, uint32_t chainGroup)
410 {
411 assert(triggerGroup < ADC_ETC_TRIGn_RESULT_1_0_COUNT);
412
413 uint32_t mADCResult;
414 uint8_t mRemainder = (uint8_t)(chainGroup % 2U);
415
416 switch (chainGroup / 2U)
417 {
418 case 0U:
419 if (0U == mRemainder)
420 {
421 mADCResult = ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_1_0);
422 }
423 else
424 {
425 mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_1_0) >> ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT;
426 }
427 break;
428 case 1U:
429 if (0U == mRemainder)
430 {
431 mADCResult = ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_3_2);
432 }
433 else
434 {
435 mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_3_2) >> ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT;
436 }
437 break;
438 case 2U:
439 if (0U == mRemainder)
440 {
441 mADCResult = ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_5_4);
442 }
443 else
444 {
445 mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_5_4) >> ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT;
446 }
447 break;
448 case 3U:
449 if (0U == mRemainder)
450 {
451 mADCResult = ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_7_6);
452 }
453 else
454 {
455 mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_7_6) >> ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT;
456 }
457 break;
458 default:
459 mADCResult = 0U;
460 assert(false);
461 break;
462 }
463 return mADCResult;
464 }
465
