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Searched defs:ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (Results 1 – 23 of 23) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h1342 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h1630 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h1795 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h1779 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h2020 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h2042 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h2045 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h2098 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h2022 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h2102 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h2176 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm4.h3502 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) macro
DMIMXRT1165_cm7.h3505 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm7.h3520 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) macro
DMIMXRT1166_cm4.h3517 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm7.h3516 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) macro
DMIMXRT1175_cm4.h3513 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h3516 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h3525 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) macro
DMIMXRT1173_cm7.h3528 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm4.h3528 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) macro
DMIMXRT1176_cm7.h3531 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h3531 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) macro