1 /*
2  * Copyright 1997-2016 Freescale Semiconductor, Inc.
3  * Copyright 2016-2022 NXP
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /*!
9  * @file S32Z2_ADC.h
10  * @version 1.8
11  * @date 2022-07-13
12  * @brief Peripheral Access Layer for S32Z2_ADC
13  *
14  * This file contains register definitions and macros for easy access to their
15  * bit fields.
16  *
17  * This file assumes LITTLE endian system.
18  */
19 
20 /**
21 * @page misra_violations MISRA-C:2012 violations
22 *
23 * @section [global]
24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced
25 * The SoC header defines typedef for all modules.
26 *
27 * @section [global]
28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced
29 * The SoC header defines macros for all modules and registers.
30 *
31 * @section [global]
32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro
33 * These are generated macros used for accessing the bit-fields from registers.
34 *
35 * @section [global]
36 * Violates MISRA 2012 Required Rule 5.1, identifier clash
37 * The supported compilers use more than 31 significant characters for identifiers.
38 *
39 * @section [global]
40 * Violates MISRA 2012 Required Rule 5.2, identifier clash
41 * The supported compilers use more than 31 significant characters for identifiers.
42 *
43 * @section [global]
44 * Violates MISRA 2012 Required Rule 5.4, identifier clash
45 * The supported compilers use more than 31 significant characters for identifiers.
46 *
47 * @section [global]
48 * Violates MISRA 2012 Required Rule 5.5, identifier clash
49 * The supported compilers use more than 31 significant characters for identifiers.
50 *
51 * @section [global]
52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler
53 * This type qualifier is needed to ensure correct I/O access and addressing.
54 */
55 
56 /* Prevention from multiple including the same memory map */
57 #if !defined(S32Z2_ADC_H_)  /* Check if memory map has not been already included */
58 #define S32Z2_ADC_H_
59 
60 #include "S32Z2_COMMON.h"
61 
62 /* ----------------------------------------------------------------------------
63    -- ADC Peripheral Access Layer
64    ---------------------------------------------------------------------------- */
65 
66 /*!
67  * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
68  * @{
69  */
70 
71 /** ADC - Size of Registers Arrays */
72 #define ADC_CDR0_COUNT                            8u
73 #define ADC_CDR32_COUNT                           8u
74 
75 /** ADC - Register Layout Typedef */
76 typedef struct {
77   __IO uint32_t MCR;                               /**< Main Configuration, offset: 0x0 */
78   __IO uint32_t MSR;                               /**< Main Status, offset: 0x4 */
79   uint8_t RESERVED_0[8];
80   __IO uint32_t ISR;                               /**< Interrupt Status, offset: 0x10 */
81   __IO uint32_t CEOCFR0;                           /**< Channel Pending 0, offset: 0x14 */
82   __IO uint32_t CEOCFR1;                           /**< Channel Pending 1, offset: 0x18 */
83   uint8_t RESERVED_1[4];
84   __IO uint32_t IMR;                               /**< Interrupt Mask, offset: 0x20 */
85   __IO uint32_t CIMR0;                             /**< Channel Interrupt Mask 0, offset: 0x24 */
86   __IO uint32_t CIMR1;                             /**< Channel Interrupt Mask 1, offset: 0x28 */
87   uint8_t RESERVED_2[4];
88   __IO uint32_t WTISR;                             /**< Watchdog Threshold Interrupt Status, offset: 0x30 */
89   __IO uint32_t WTIMR;                             /**< Watchdog Threshold Interrupt Mask, offset: 0x34 */
90   uint8_t RESERVED_3[8];
91   __IO uint32_t DMAE;                              /**< DMAE, offset: 0x40 */
92   __IO uint32_t DMAR0;                             /**< DMA 0, offset: 0x44 */
93   __IO uint32_t DMAR1;                             /**< DMA 1, offset: 0x48 */
94   uint8_t RESERVED_4[20];
95   __IO uint32_t THRHLR0;                           /**< Analog Watchdog Threshold 0, offset: 0x60 */
96   __IO uint32_t THRHLR1;                           /**< Analog Watchdog Threshold 1, offset: 0x64 */
97   __IO uint32_t THRHLR2;                           /**< Analog Watchdog Threshold 2, offset: 0x68 */
98   __IO uint32_t THRHLR3;                           /**< Analog Watchdog Threshold 3, offset: 0x6C */
99   uint8_t RESERVED_5[16];
100   __IO uint32_t PSCR;                              /**< Presampling Control, offset: 0x80 */
101   __IO uint32_t PSR0;                              /**< Presampling 0, offset: 0x84 */
102   __IO uint32_t PSR1;                              /**< Presampling 1, offset: 0x88 */
103   uint8_t RESERVED_6[8];
104   __IO uint32_t CTR0;                              /**< Conversion Timing 0, offset: 0x94 */
105   __IO uint32_t CTR1;                              /**< Conversion Timing 1, offset: 0x98 */
106   uint8_t RESERVED_7[8];
107   __IO uint32_t NCMR0;                             /**< Normal Conversion Mask 0, offset: 0xA4 */
108   __IO uint32_t NCMR1;                             /**< Normal Conversion Mask 1, offset: 0xA8 */
109   uint8_t RESERVED_8[8];
110   __IO uint32_t JCMR0;                             /**< Injected Conversion Mask 0, offset: 0xB4 */
111   __IO uint32_t JCMR1;                             /**< Injected Conversion Mask 1, offset: 0xB8 */
112   uint8_t RESERVED_9[4];
113   __IO uint32_t USROFSGN;                          /**< User OFFSET and Gain, offset: 0xC0 */
114   uint8_t RESERVED_10[4];
115   __IO uint32_t PDEDR;                             /**< Power Down Exit Delay, offset: 0xC8 */
116   uint8_t RESERVED_11[52];
117   __I  uint32_t PCDR[ADC_CDR0_COUNT];              /**< Precision Channel n Data, array offset: 0x100, array step: 0x4 */
118   uint8_t RESERVED_12[96];
119   __I  uint32_t ICDR[ADC_CDR32_COUNT];             /**< Internal Channel n Data, array offset: 0x180, array step: 0x4 */
120   uint8_t RESERVED_13[224];
121   __IO uint32_t THRHLR4;                           /**< Analog Watchdog Threshold 4, offset: 0x280 */
122   __IO uint32_t THRHLR5;                           /**< Analog Watchdog Threshold 5, offset: 0x284 */
123   __IO uint32_t THRHLR6;                           /**< Analog Watchdog Threshold 6, offset: 0x288 */
124   __IO uint32_t THRHLR7;                           /**< Analog Watchdog Threshold 7, offset: 0x28C */
125   uint8_t RESERVED_14[32];
126   __IO uint32_t CWSELR0;                           /**< Channel Watchdog Select 0, offset: 0x2B0 */
127   uint8_t RESERVED_15[12];
128   __IO uint32_t CWSELR4;                           /**< Channel Watchdog Select 4, offset: 0x2C0 */
129   uint8_t RESERVED_16[28];
130   __IO uint32_t CWENR0;                            /**< Channel Watchdog Enable 0, offset: 0x2E0 */
131   __IO uint32_t CWENR1;                            /**< Channel Watchdog Enable 1, offset: 0x2E4 */
132   uint8_t RESERVED_17[8];
133   __IO uint32_t AWORR0;                            /**< Analog Watchdog Out of Range 0, offset: 0x2F0 */
134   __IO uint32_t AWORR1;                            /**< Analog Watchdog Out of Range 1, offset: 0x2F4 */
135   uint8_t RESERVED_18[72];
136   __IO uint32_t STCR1;                             /**< Self-Test Configuration 1, offset: 0x340 */
137   __IO uint32_t STCR2;                             /**< Self-Test Configuration 2, offset: 0x344 */
138   __IO uint32_t STCR3;                             /**< Self-Test Configuration 3, offset: 0x348 */
139   __IO uint32_t STBRR;                             /**< Self-Test Baud Rate, offset: 0x34C */
140   __IO uint32_t STSR1;                             /**< Self-Test Status 1, offset: 0x350 */
141   __I  uint32_t STSR2;                             /**< Self-Test Status 2, offset: 0x354 */
142   __I  uint32_t STSR3;                             /**< Self-Test Status 3, offset: 0x358 */
143   __I  uint32_t STSR4;                             /**< Self-Test Status 4, offset: 0x35C */
144   uint8_t RESERVED_19[16];
145   __I  uint32_t STDR1;                             /**< Self-Test Data 1, offset: 0x370 */
146   __I  uint32_t STDR2;                             /**< Self-Test Data 2, offset: 0x374 */
147   uint8_t RESERVED_20[8];
148   __IO uint32_t STAW0R;                            /**< Self-Test Analog Watchdog 0, offset: 0x380 */
149   __IO uint32_t STAW1AR;                           /**< Self-Test Analog Watchdog 1A, offset: 0x384 */
150   __IO uint32_t STAW1BR;                           /**< Self-Test Analog Watchdog 1B, offset: 0x388 */
151   __IO uint32_t STAW2R;                            /**< Self-Test Analog Watchdog 2, offset: 0x38C */
152        uint32_t STAW3R;                            /**< Self-Test Analog Watchdog 3, offset: 0x390 */
153   __IO uint32_t STAW4R;                            /**< Self-Test Analog Watchdog 4, offset: 0x394 */
154   __IO uint32_t STAW5R;                            /**< Self-Test Analog Watchdog 5, offset: 0x398 */
155   __I  uint32_t CALSTAT;                           /**< Calibration Status, offset: 0x39C */
156 } ADC_Type, *ADC_MemMapPtr;
157 
158 /** Number of instances of the ADC module. */
159 #define ADC_INSTANCE_COUNT                       (2u)
160 
161 /* ADC - Peripheral instance base addresses */
162 /** Peripheral ADC_0 base address */
163 #define IP_ADC_0_BASE                            (0x402C0000u)
164 /** Peripheral ADC_0 base pointer */
165 #define IP_ADC_0                                 ((ADC_Type *)IP_ADC_0_BASE)
166 /** Peripheral ADC_1 base address */
167 #define IP_ADC_1_BASE                            (0x402E0000u)
168 /** Peripheral ADC_1 base pointer */
169 #define IP_ADC_1                                 ((ADC_Type *)IP_ADC_1_BASE)
170 /** Array initializer of ADC peripheral base addresses */
171 #define IP_ADC_BASE_ADDRS                        { IP_ADC_0_BASE, IP_ADC_1_BASE }
172 /** Array initializer of ADC peripheral base pointers */
173 #define IP_ADC_BASE_PTRS                         { IP_ADC_0, IP_ADC_1 }
174 
175 /* ----------------------------------------------------------------------------
176    -- ADC Register Masks
177    ---------------------------------------------------------------------------- */
178 
179 /*!
180  * @addtogroup ADC_Register_Masks ADC Register Masks
181  * @{
182  */
183 
184 /*! @name MCR - Main Configuration */
185 /*! @{ */
186 
187 #define ADC_MCR_PWDN_MASK                        (0x1U)
188 #define ADC_MCR_PWDN_SHIFT                       (0U)
189 #define ADC_MCR_PWDN_WIDTH                       (1U)
190 #define ADC_MCR_PWDN(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_MCR_PWDN_SHIFT)) & ADC_MCR_PWDN_MASK)
191 
192 #define ADC_MCR_ACKO_MASK                        (0x20U)
193 #define ADC_MCR_ACKO_SHIFT                       (5U)
194 #define ADC_MCR_ACKO_WIDTH                       (1U)
195 #define ADC_MCR_ACKO(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_MCR_ACKO_SHIFT)) & ADC_MCR_ACKO_MASK)
196 
197 #define ADC_MCR_ABORT_MASK                       (0x40U)
198 #define ADC_MCR_ABORT_SHIFT                      (6U)
199 #define ADC_MCR_ABORT_WIDTH                      (1U)
200 #define ADC_MCR_ABORT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_MCR_ABORT_SHIFT)) & ADC_MCR_ABORT_MASK)
201 
202 #define ADC_MCR_ABORTCHAIN_MASK                  (0x80U)
203 #define ADC_MCR_ABORTCHAIN_SHIFT                 (7U)
204 #define ADC_MCR_ABORTCHAIN_WIDTH                 (1U)
205 #define ADC_MCR_ABORTCHAIN(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_MCR_ABORTCHAIN_SHIFT)) & ADC_MCR_ABORTCHAIN_MASK)
206 
207 #define ADC_MCR_ADCLKSE_MASK                     (0x100U)
208 #define ADC_MCR_ADCLKSE_SHIFT                    (8U)
209 #define ADC_MCR_ADCLKSE_WIDTH                    (1U)
210 #define ADC_MCR_ADCLKSE(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_MCR_ADCLKSE_SHIFT)) & ADC_MCR_ADCLKSE_MASK)
211 
212 #define ADC_MCR_TSAMP_MASK                       (0x600U)
213 #define ADC_MCR_TSAMP_SHIFT                      (9U)
214 #define ADC_MCR_TSAMP_WIDTH                      (2U)
215 #define ADC_MCR_TSAMP(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_MCR_TSAMP_SHIFT)) & ADC_MCR_TSAMP_MASK)
216 
217 #define ADC_MCR_NRSMPL_MASK                      (0x1800U)
218 #define ADC_MCR_NRSMPL_SHIFT                     (11U)
219 #define ADC_MCR_NRSMPL_WIDTH                     (2U)
220 #define ADC_MCR_NRSMPL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_MCR_NRSMPL_SHIFT)) & ADC_MCR_NRSMPL_MASK)
221 
222 #define ADC_MCR_AVGEN_MASK                       (0x2000U)
223 #define ADC_MCR_AVGEN_SHIFT                      (13U)
224 #define ADC_MCR_AVGEN_WIDTH                      (1U)
225 #define ADC_MCR_AVGEN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_MCR_AVGEN_SHIFT)) & ADC_MCR_AVGEN_MASK)
226 
227 #define ADC_MCR_CALSTART_MASK                    (0x4000U)
228 #define ADC_MCR_CALSTART_SHIFT                   (14U)
229 #define ADC_MCR_CALSTART_WIDTH                   (1U)
230 #define ADC_MCR_CALSTART(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_MCR_CALSTART_SHIFT)) & ADC_MCR_CALSTART_MASK)
231 
232 #define ADC_MCR_STCL_MASK                        (0x8000U)
233 #define ADC_MCR_STCL_SHIFT                       (15U)
234 #define ADC_MCR_STCL_WIDTH                       (1U)
235 #define ADC_MCR_STCL(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_MCR_STCL_SHIFT)) & ADC_MCR_STCL_MASK)
236 
237 #define ADC_MCR_CTU_MODE_MASK                    (0x10000U)
238 #define ADC_MCR_CTU_MODE_SHIFT                   (16U)
239 #define ADC_MCR_CTU_MODE_WIDTH                   (1U)
240 #define ADC_MCR_CTU_MODE(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_MCR_CTU_MODE_SHIFT)) & ADC_MCR_CTU_MODE_MASK)
241 
242 #define ADC_MCR_CTUEN_MASK                       (0x20000U)
243 #define ADC_MCR_CTUEN_SHIFT                      (17U)
244 #define ADC_MCR_CTUEN_WIDTH                      (1U)
245 #define ADC_MCR_CTUEN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_MCR_CTUEN_SHIFT)) & ADC_MCR_CTUEN_MASK)
246 
247 #define ADC_MCR_JSTART_MASK                      (0x100000U)
248 #define ADC_MCR_JSTART_SHIFT                     (20U)
249 #define ADC_MCR_JSTART_WIDTH                     (1U)
250 #define ADC_MCR_JSTART(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_MCR_JSTART_SHIFT)) & ADC_MCR_JSTART_MASK)
251 
252 #define ADC_MCR_JEDGE_MASK                       (0x200000U)
253 #define ADC_MCR_JEDGE_SHIFT                      (21U)
254 #define ADC_MCR_JEDGE_WIDTH                      (1U)
255 #define ADC_MCR_JEDGE(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_MCR_JEDGE_SHIFT)) & ADC_MCR_JEDGE_MASK)
256 
257 #define ADC_MCR_JTRGEN_MASK                      (0x400000U)
258 #define ADC_MCR_JTRGEN_SHIFT                     (22U)
259 #define ADC_MCR_JTRGEN_WIDTH                     (1U)
260 #define ADC_MCR_JTRGEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_MCR_JTRGEN_SHIFT)) & ADC_MCR_JTRGEN_MASK)
261 
262 #define ADC_MCR_NSTART_MASK                      (0x1000000U)
263 #define ADC_MCR_NSTART_SHIFT                     (24U)
264 #define ADC_MCR_NSTART_WIDTH                     (1U)
265 #define ADC_MCR_NSTART(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_MCR_NSTART_SHIFT)) & ADC_MCR_NSTART_MASK)
266 
267 #define ADC_MCR_EDGE_MASK                        (0x4000000U)
268 #define ADC_MCR_EDGE_SHIFT                       (26U)
269 #define ADC_MCR_EDGE_WIDTH                       (1U)
270 #define ADC_MCR_EDGE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_MCR_EDGE_SHIFT)) & ADC_MCR_EDGE_MASK)
271 
272 #define ADC_MCR_TRGEN_MASK                       (0x8000000U)
273 #define ADC_MCR_TRGEN_SHIFT                      (27U)
274 #define ADC_MCR_TRGEN_WIDTH                      (1U)
275 #define ADC_MCR_TRGEN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_MCR_TRGEN_SHIFT)) & ADC_MCR_TRGEN_MASK)
276 
277 #define ADC_MCR_MODE_MASK                        (0x20000000U)
278 #define ADC_MCR_MODE_SHIFT                       (29U)
279 #define ADC_MCR_MODE_WIDTH                       (1U)
280 #define ADC_MCR_MODE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_MCR_MODE_SHIFT)) & ADC_MCR_MODE_MASK)
281 
282 #define ADC_MCR_WLSIDE_MASK                      (0x40000000U)
283 #define ADC_MCR_WLSIDE_SHIFT                     (30U)
284 #define ADC_MCR_WLSIDE_WIDTH                     (1U)
285 #define ADC_MCR_WLSIDE(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_MCR_WLSIDE_SHIFT)) & ADC_MCR_WLSIDE_MASK)
286 
287 #define ADC_MCR_OWREN_MASK                       (0x80000000U)
288 #define ADC_MCR_OWREN_SHIFT                      (31U)
289 #define ADC_MCR_OWREN_WIDTH                      (1U)
290 #define ADC_MCR_OWREN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_MCR_OWREN_SHIFT)) & ADC_MCR_OWREN_MASK)
291 /*! @} */
292 
293 /*! @name MSR - Main Status */
294 /*! @{ */
295 
296 #define ADC_MSR_ADCSTATUS_MASK                   (0x7U)
297 #define ADC_MSR_ADCSTATUS_SHIFT                  (0U)
298 #define ADC_MSR_ADCSTATUS_WIDTH                  (3U)
299 #define ADC_MSR_ADCSTATUS(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_MSR_ADCSTATUS_SHIFT)) & ADC_MSR_ADCSTATUS_MASK)
300 
301 #define ADC_MSR_ACKO_MASK                        (0x20U)
302 #define ADC_MSR_ACKO_SHIFT                       (5U)
303 #define ADC_MSR_ACKO_WIDTH                       (1U)
304 #define ADC_MSR_ACKO(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_MSR_ACKO_SHIFT)) & ADC_MSR_ACKO_MASK)
305 
306 #define ADC_MSR_CHADDR_MASK                      (0xFE00U)
307 #define ADC_MSR_CHADDR_SHIFT                     (9U)
308 #define ADC_MSR_CHADDR_WIDTH                     (7U)
309 #define ADC_MSR_CHADDR(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_MSR_CHADDR_SHIFT)) & ADC_MSR_CHADDR_MASK)
310 
311 #define ADC_MSR_CTUSTART_MASK                    (0x10000U)
312 #define ADC_MSR_CTUSTART_SHIFT                   (16U)
313 #define ADC_MSR_CTUSTART_WIDTH                   (1U)
314 #define ADC_MSR_CTUSTART(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_MSR_CTUSTART_SHIFT)) & ADC_MSR_CTUSTART_MASK)
315 
316 #define ADC_MSR_SELF_TEST_S_MASK                 (0x40000U)
317 #define ADC_MSR_SELF_TEST_S_SHIFT                (18U)
318 #define ADC_MSR_SELF_TEST_S_WIDTH                (1U)
319 #define ADC_MSR_SELF_TEST_S(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_MSR_SELF_TEST_S_SHIFT)) & ADC_MSR_SELF_TEST_S_MASK)
320 
321 #define ADC_MSR_JSTART_MASK                      (0x100000U)
322 #define ADC_MSR_JSTART_SHIFT                     (20U)
323 #define ADC_MSR_JSTART_WIDTH                     (1U)
324 #define ADC_MSR_JSTART(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_MSR_JSTART_SHIFT)) & ADC_MSR_JSTART_MASK)
325 
326 #define ADC_MSR_JABORT_MASK                      (0x800000U)
327 #define ADC_MSR_JABORT_SHIFT                     (23U)
328 #define ADC_MSR_JABORT_WIDTH                     (1U)
329 #define ADC_MSR_JABORT(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_MSR_JABORT_SHIFT)) & ADC_MSR_JABORT_MASK)
330 
331 #define ADC_MSR_NSTART_MASK                      (0x1000000U)
332 #define ADC_MSR_NSTART_SHIFT                     (24U)
333 #define ADC_MSR_NSTART_WIDTH                     (1U)
334 #define ADC_MSR_NSTART(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_MSR_NSTART_SHIFT)) & ADC_MSR_NSTART_MASK)
335 
336 #define ADC_MSR_CALBUSY_MASK                     (0x20000000U)
337 #define ADC_MSR_CALBUSY_SHIFT                    (29U)
338 #define ADC_MSR_CALBUSY_WIDTH                    (1U)
339 #define ADC_MSR_CALBUSY(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_MSR_CALBUSY_SHIFT)) & ADC_MSR_CALBUSY_MASK)
340 
341 #define ADC_MSR_CALFAIL_MASK                     (0x40000000U)
342 #define ADC_MSR_CALFAIL_SHIFT                    (30U)
343 #define ADC_MSR_CALFAIL_WIDTH                    (1U)
344 #define ADC_MSR_CALFAIL(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_MSR_CALFAIL_SHIFT)) & ADC_MSR_CALFAIL_MASK)
345 
346 #define ADC_MSR_CALIBRTD_MASK                    (0x80000000U)
347 #define ADC_MSR_CALIBRTD_SHIFT                   (31U)
348 #define ADC_MSR_CALIBRTD_WIDTH                   (1U)
349 #define ADC_MSR_CALIBRTD(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_MSR_CALIBRTD_SHIFT)) & ADC_MSR_CALIBRTD_MASK)
350 /*! @} */
351 
352 /*! @name ISR - Interrupt Status */
353 /*! @{ */
354 
355 #define ADC_ISR_ECH_MASK                         (0x1U)
356 #define ADC_ISR_ECH_SHIFT                        (0U)
357 #define ADC_ISR_ECH_WIDTH                        (1U)
358 #define ADC_ISR_ECH(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_ISR_ECH_SHIFT)) & ADC_ISR_ECH_MASK)
359 
360 #define ADC_ISR_EOC_MASK                         (0x2U)
361 #define ADC_ISR_EOC_SHIFT                        (1U)
362 #define ADC_ISR_EOC_WIDTH                        (1U)
363 #define ADC_ISR_EOC(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_ISR_EOC_SHIFT)) & ADC_ISR_EOC_MASK)
364 
365 #define ADC_ISR_JECH_MASK                        (0x4U)
366 #define ADC_ISR_JECH_SHIFT                       (2U)
367 #define ADC_ISR_JECH_WIDTH                       (1U)
368 #define ADC_ISR_JECH(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_ISR_JECH_SHIFT)) & ADC_ISR_JECH_MASK)
369 
370 #define ADC_ISR_JEOC_MASK                        (0x8U)
371 #define ADC_ISR_JEOC_SHIFT                       (3U)
372 #define ADC_ISR_JEOC_WIDTH                       (1U)
373 #define ADC_ISR_JEOC(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_ISR_JEOC_SHIFT)) & ADC_ISR_JEOC_MASK)
374 
375 #define ADC_ISR_EOCTU_MASK                       (0x10U)
376 #define ADC_ISR_EOCTU_SHIFT                      (4U)
377 #define ADC_ISR_EOCTU_WIDTH                      (1U)
378 #define ADC_ISR_EOCTU(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_ISR_EOCTU_SHIFT)) & ADC_ISR_EOCTU_MASK)
379 /*! @} */
380 
381 /*! @name CEOCFR0 - Channel Pending 0 */
382 /*! @{ */
383 
384 #define ADC_CEOCFR0_EOC_CH0_MASK                 (0x1U)
385 #define ADC_CEOCFR0_EOC_CH0_SHIFT                (0U)
386 #define ADC_CEOCFR0_EOC_CH0_WIDTH                (1U)
387 #define ADC_CEOCFR0_EOC_CH0(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH0_SHIFT)) & ADC_CEOCFR0_EOC_CH0_MASK)
388 
389 #define ADC_CEOCFR0_EOC_CH1_MASK                 (0x2U)
390 #define ADC_CEOCFR0_EOC_CH1_SHIFT                (1U)
391 #define ADC_CEOCFR0_EOC_CH1_WIDTH                (1U)
392 #define ADC_CEOCFR0_EOC_CH1(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH1_SHIFT)) & ADC_CEOCFR0_EOC_CH1_MASK)
393 
394 #define ADC_CEOCFR0_EOC_CH2_MASK                 (0x4U)
395 #define ADC_CEOCFR0_EOC_CH2_SHIFT                (2U)
396 #define ADC_CEOCFR0_EOC_CH2_WIDTH                (1U)
397 #define ADC_CEOCFR0_EOC_CH2(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH2_SHIFT)) & ADC_CEOCFR0_EOC_CH2_MASK)
398 
399 #define ADC_CEOCFR0_EOC_CH3_MASK                 (0x8U)
400 #define ADC_CEOCFR0_EOC_CH3_SHIFT                (3U)
401 #define ADC_CEOCFR0_EOC_CH3_WIDTH                (1U)
402 #define ADC_CEOCFR0_EOC_CH3(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH3_SHIFT)) & ADC_CEOCFR0_EOC_CH3_MASK)
403 
404 #define ADC_CEOCFR0_EOC_CH4_MASK                 (0x10U)
405 #define ADC_CEOCFR0_EOC_CH4_SHIFT                (4U)
406 #define ADC_CEOCFR0_EOC_CH4_WIDTH                (1U)
407 #define ADC_CEOCFR0_EOC_CH4(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH4_SHIFT)) & ADC_CEOCFR0_EOC_CH4_MASK)
408 
409 #define ADC_CEOCFR0_EOC_CH5_MASK                 (0x20U)
410 #define ADC_CEOCFR0_EOC_CH5_SHIFT                (5U)
411 #define ADC_CEOCFR0_EOC_CH5_WIDTH                (1U)
412 #define ADC_CEOCFR0_EOC_CH5(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH5_SHIFT)) & ADC_CEOCFR0_EOC_CH5_MASK)
413 
414 #define ADC_CEOCFR0_EOC_CH6_MASK                 (0x40U)
415 #define ADC_CEOCFR0_EOC_CH6_SHIFT                (6U)
416 #define ADC_CEOCFR0_EOC_CH6_WIDTH                (1U)
417 #define ADC_CEOCFR0_EOC_CH6(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH6_SHIFT)) & ADC_CEOCFR0_EOC_CH6_MASK)
418 
419 #define ADC_CEOCFR0_EOC_CH7_MASK                 (0x80U)
420 #define ADC_CEOCFR0_EOC_CH7_SHIFT                (7U)
421 #define ADC_CEOCFR0_EOC_CH7_WIDTH                (1U)
422 #define ADC_CEOCFR0_EOC_CH7(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH7_SHIFT)) & ADC_CEOCFR0_EOC_CH7_MASK)
423 /*! @} */
424 
425 /*! @name CEOCFR1 - Channel Pending 1 */
426 /*! @{ */
427 
428 #define ADC_CEOCFR1_EOC_CH32_MASK                (0x1U)
429 #define ADC_CEOCFR1_EOC_CH32_SHIFT               (0U)
430 #define ADC_CEOCFR1_EOC_CH32_WIDTH               (1U)
431 #define ADC_CEOCFR1_EOC_CH32(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH32_SHIFT)) & ADC_CEOCFR1_EOC_CH32_MASK)
432 
433 #define ADC_CEOCFR1_EOC_CH33_MASK                (0x2U)
434 #define ADC_CEOCFR1_EOC_CH33_SHIFT               (1U)
435 #define ADC_CEOCFR1_EOC_CH33_WIDTH               (1U)
436 #define ADC_CEOCFR1_EOC_CH33(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH33_SHIFT)) & ADC_CEOCFR1_EOC_CH33_MASK)
437 
438 #define ADC_CEOCFR1_EOC_CH34_MASK                (0x4U)
439 #define ADC_CEOCFR1_EOC_CH34_SHIFT               (2U)
440 #define ADC_CEOCFR1_EOC_CH34_WIDTH               (1U)
441 #define ADC_CEOCFR1_EOC_CH34(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH34_SHIFT)) & ADC_CEOCFR1_EOC_CH34_MASK)
442 
443 #define ADC_CEOCFR1_EOC_CH35_MASK                (0x8U)
444 #define ADC_CEOCFR1_EOC_CH35_SHIFT               (3U)
445 #define ADC_CEOCFR1_EOC_CH35_WIDTH               (1U)
446 #define ADC_CEOCFR1_EOC_CH35(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH35_SHIFT)) & ADC_CEOCFR1_EOC_CH35_MASK)
447 
448 #define ADC_CEOCFR1_EOC_CH36_MASK                (0x10U)
449 #define ADC_CEOCFR1_EOC_CH36_SHIFT               (4U)
450 #define ADC_CEOCFR1_EOC_CH36_WIDTH               (1U)
451 #define ADC_CEOCFR1_EOC_CH36(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH36_SHIFT)) & ADC_CEOCFR1_EOC_CH36_MASK)
452 
453 #define ADC_CEOCFR1_EOC_CH37_MASK                (0x20U)
454 #define ADC_CEOCFR1_EOC_CH37_SHIFT               (5U)
455 #define ADC_CEOCFR1_EOC_CH37_WIDTH               (1U)
456 #define ADC_CEOCFR1_EOC_CH37(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH37_SHIFT)) & ADC_CEOCFR1_EOC_CH37_MASK)
457 
458 #define ADC_CEOCFR1_EOC_CH38_MASK                (0x40U)
459 #define ADC_CEOCFR1_EOC_CH38_SHIFT               (6U)
460 #define ADC_CEOCFR1_EOC_CH38_WIDTH               (1U)
461 #define ADC_CEOCFR1_EOC_CH38(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH38_SHIFT)) & ADC_CEOCFR1_EOC_CH38_MASK)
462 
463 #define ADC_CEOCFR1_EOC_CH39_MASK                (0x80U)
464 #define ADC_CEOCFR1_EOC_CH39_SHIFT               (7U)
465 #define ADC_CEOCFR1_EOC_CH39_WIDTH               (1U)
466 #define ADC_CEOCFR1_EOC_CH39(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH39_SHIFT)) & ADC_CEOCFR1_EOC_CH39_MASK)
467 /*! @} */
468 
469 /*! @name IMR - Interrupt Mask */
470 /*! @{ */
471 
472 #define ADC_IMR_MSKECH_MASK                      (0x1U)
473 #define ADC_IMR_MSKECH_SHIFT                     (0U)
474 #define ADC_IMR_MSKECH_WIDTH                     (1U)
475 #define ADC_IMR_MSKECH(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_IMR_MSKECH_SHIFT)) & ADC_IMR_MSKECH_MASK)
476 
477 #define ADC_IMR_MSKEOC_MASK                      (0x2U)
478 #define ADC_IMR_MSKEOC_SHIFT                     (1U)
479 #define ADC_IMR_MSKEOC_WIDTH                     (1U)
480 #define ADC_IMR_MSKEOC(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_IMR_MSKEOC_SHIFT)) & ADC_IMR_MSKEOC_MASK)
481 
482 #define ADC_IMR_MSKJECH_MASK                     (0x4U)
483 #define ADC_IMR_MSKJECH_SHIFT                    (2U)
484 #define ADC_IMR_MSKJECH_WIDTH                    (1U)
485 #define ADC_IMR_MSKJECH(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_IMR_MSKJECH_SHIFT)) & ADC_IMR_MSKJECH_MASK)
486 
487 #define ADC_IMR_MSKJEOC_MASK                     (0x8U)
488 #define ADC_IMR_MSKJEOC_SHIFT                    (3U)
489 #define ADC_IMR_MSKJEOC_WIDTH                    (1U)
490 #define ADC_IMR_MSKJEOC(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_IMR_MSKJEOC_SHIFT)) & ADC_IMR_MSKJEOC_MASK)
491 
492 #define ADC_IMR_MSKEOCTU_MASK                    (0x10U)
493 #define ADC_IMR_MSKEOCTU_SHIFT                   (4U)
494 #define ADC_IMR_MSKEOCTU_WIDTH                   (1U)
495 #define ADC_IMR_MSKEOCTU(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_IMR_MSKEOCTU_SHIFT)) & ADC_IMR_MSKEOCTU_MASK)
496 /*! @} */
497 
498 /*! @name CIMR0 - Channel Interrupt Mask 0 */
499 /*! @{ */
500 
501 #define ADC_CIMR0_CIM0_MASK                      (0x1U)
502 #define ADC_CIMR0_CIM0_SHIFT                     (0U)
503 #define ADC_CIMR0_CIM0_WIDTH                     (1U)
504 #define ADC_CIMR0_CIM0(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM0_SHIFT)) & ADC_CIMR0_CIM0_MASK)
505 
506 #define ADC_CIMR0_CIM1_MASK                      (0x2U)
507 #define ADC_CIMR0_CIM1_SHIFT                     (1U)
508 #define ADC_CIMR0_CIM1_WIDTH                     (1U)
509 #define ADC_CIMR0_CIM1(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM1_SHIFT)) & ADC_CIMR0_CIM1_MASK)
510 
511 #define ADC_CIMR0_CIM2_MASK                      (0x4U)
512 #define ADC_CIMR0_CIM2_SHIFT                     (2U)
513 #define ADC_CIMR0_CIM2_WIDTH                     (1U)
514 #define ADC_CIMR0_CIM2(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM2_SHIFT)) & ADC_CIMR0_CIM2_MASK)
515 
516 #define ADC_CIMR0_CIM3_MASK                      (0x8U)
517 #define ADC_CIMR0_CIM3_SHIFT                     (3U)
518 #define ADC_CIMR0_CIM3_WIDTH                     (1U)
519 #define ADC_CIMR0_CIM3(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM3_SHIFT)) & ADC_CIMR0_CIM3_MASK)
520 
521 #define ADC_CIMR0_CIM4_MASK                      (0x10U)
522 #define ADC_CIMR0_CIM4_SHIFT                     (4U)
523 #define ADC_CIMR0_CIM4_WIDTH                     (1U)
524 #define ADC_CIMR0_CIM4(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM4_SHIFT)) & ADC_CIMR0_CIM4_MASK)
525 
526 #define ADC_CIMR0_CIM5_MASK                      (0x20U)
527 #define ADC_CIMR0_CIM5_SHIFT                     (5U)
528 #define ADC_CIMR0_CIM5_WIDTH                     (1U)
529 #define ADC_CIMR0_CIM5(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM5_SHIFT)) & ADC_CIMR0_CIM5_MASK)
530 
531 #define ADC_CIMR0_CIM6_MASK                      (0x40U)
532 #define ADC_CIMR0_CIM6_SHIFT                     (6U)
533 #define ADC_CIMR0_CIM6_WIDTH                     (1U)
534 #define ADC_CIMR0_CIM6(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM6_SHIFT)) & ADC_CIMR0_CIM6_MASK)
535 
536 #define ADC_CIMR0_CIM7_MASK                      (0x80U)
537 #define ADC_CIMR0_CIM7_SHIFT                     (7U)
538 #define ADC_CIMR0_CIM7_WIDTH                     (1U)
539 #define ADC_CIMR0_CIM7(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM7_SHIFT)) & ADC_CIMR0_CIM7_MASK)
540 /*! @} */
541 
542 /*! @name CIMR1 - Channel Interrupt Mask 1 */
543 /*! @{ */
544 
545 #define ADC_CIMR1_CIM32_MASK                     (0x1U)
546 #define ADC_CIMR1_CIM32_SHIFT                    (0U)
547 #define ADC_CIMR1_CIM32_WIDTH                    (1U)
548 #define ADC_CIMR1_CIM32(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM32_SHIFT)) & ADC_CIMR1_CIM32_MASK)
549 
550 #define ADC_CIMR1_CIM33_MASK                     (0x2U)
551 #define ADC_CIMR1_CIM33_SHIFT                    (1U)
552 #define ADC_CIMR1_CIM33_WIDTH                    (1U)
553 #define ADC_CIMR1_CIM33(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM33_SHIFT)) & ADC_CIMR1_CIM33_MASK)
554 
555 #define ADC_CIMR1_CIM34_MASK                     (0x4U)
556 #define ADC_CIMR1_CIM34_SHIFT                    (2U)
557 #define ADC_CIMR1_CIM34_WIDTH                    (1U)
558 #define ADC_CIMR1_CIM34(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM34_SHIFT)) & ADC_CIMR1_CIM34_MASK)
559 
560 #define ADC_CIMR1_CIM35_MASK                     (0x8U)
561 #define ADC_CIMR1_CIM35_SHIFT                    (3U)
562 #define ADC_CIMR1_CIM35_WIDTH                    (1U)
563 #define ADC_CIMR1_CIM35(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM35_SHIFT)) & ADC_CIMR1_CIM35_MASK)
564 
565 #define ADC_CIMR1_CIM36_MASK                     (0x10U)
566 #define ADC_CIMR1_CIM36_SHIFT                    (4U)
567 #define ADC_CIMR1_CIM36_WIDTH                    (1U)
568 #define ADC_CIMR1_CIM36(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM36_SHIFT)) & ADC_CIMR1_CIM36_MASK)
569 
570 #define ADC_CIMR1_CIM37_MASK                     (0x20U)
571 #define ADC_CIMR1_CIM37_SHIFT                    (5U)
572 #define ADC_CIMR1_CIM37_WIDTH                    (1U)
573 #define ADC_CIMR1_CIM37(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM37_SHIFT)) & ADC_CIMR1_CIM37_MASK)
574 
575 #define ADC_CIMR1_CIM38_MASK                     (0x40U)
576 #define ADC_CIMR1_CIM38_SHIFT                    (6U)
577 #define ADC_CIMR1_CIM38_WIDTH                    (1U)
578 #define ADC_CIMR1_CIM38(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM38_SHIFT)) & ADC_CIMR1_CIM38_MASK)
579 
580 #define ADC_CIMR1_CIM39_MASK                     (0x80U)
581 #define ADC_CIMR1_CIM39_SHIFT                    (7U)
582 #define ADC_CIMR1_CIM39_WIDTH                    (1U)
583 #define ADC_CIMR1_CIM39(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM39_SHIFT)) & ADC_CIMR1_CIM39_MASK)
584 /*! @} */
585 
586 /*! @name WTISR - Watchdog Threshold Interrupt Status */
587 /*! @{ */
588 
589 #define ADC_WTISR_WDG0L_MASK                     (0x1U)
590 #define ADC_WTISR_WDG0L_SHIFT                    (0U)
591 #define ADC_WTISR_WDG0L_WIDTH                    (1U)
592 #define ADC_WTISR_WDG0L(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG0L_SHIFT)) & ADC_WTISR_WDG0L_MASK)
593 
594 #define ADC_WTISR_WDG0H_MASK                     (0x2U)
595 #define ADC_WTISR_WDG0H_SHIFT                    (1U)
596 #define ADC_WTISR_WDG0H_WIDTH                    (1U)
597 #define ADC_WTISR_WDG0H(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG0H_SHIFT)) & ADC_WTISR_WDG0H_MASK)
598 
599 #define ADC_WTISR_WDG1L_MASK                     (0x4U)
600 #define ADC_WTISR_WDG1L_SHIFT                    (2U)
601 #define ADC_WTISR_WDG1L_WIDTH                    (1U)
602 #define ADC_WTISR_WDG1L(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG1L_SHIFT)) & ADC_WTISR_WDG1L_MASK)
603 
604 #define ADC_WTISR_WDG1H_MASK                     (0x8U)
605 #define ADC_WTISR_WDG1H_SHIFT                    (3U)
606 #define ADC_WTISR_WDG1H_WIDTH                    (1U)
607 #define ADC_WTISR_WDG1H(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG1H_SHIFT)) & ADC_WTISR_WDG1H_MASK)
608 
609 #define ADC_WTISR_WDG2L_MASK                     (0x10U)
610 #define ADC_WTISR_WDG2L_SHIFT                    (4U)
611 #define ADC_WTISR_WDG2L_WIDTH                    (1U)
612 #define ADC_WTISR_WDG2L(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG2L_SHIFT)) & ADC_WTISR_WDG2L_MASK)
613 
614 #define ADC_WTISR_WDG2H_MASK                     (0x20U)
615 #define ADC_WTISR_WDG2H_SHIFT                    (5U)
616 #define ADC_WTISR_WDG2H_WIDTH                    (1U)
617 #define ADC_WTISR_WDG2H(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG2H_SHIFT)) & ADC_WTISR_WDG2H_MASK)
618 
619 #define ADC_WTISR_WDG3L_MASK                     (0x40U)
620 #define ADC_WTISR_WDG3L_SHIFT                    (6U)
621 #define ADC_WTISR_WDG3L_WIDTH                    (1U)
622 #define ADC_WTISR_WDG3L(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG3L_SHIFT)) & ADC_WTISR_WDG3L_MASK)
623 
624 #define ADC_WTISR_WDG3H_MASK                     (0x80U)
625 #define ADC_WTISR_WDG3H_SHIFT                    (7U)
626 #define ADC_WTISR_WDG3H_WIDTH                    (1U)
627 #define ADC_WTISR_WDG3H(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG3H_SHIFT)) & ADC_WTISR_WDG3H_MASK)
628 
629 #define ADC_WTISR_WDG4L_MASK                     (0x100U)
630 #define ADC_WTISR_WDG4L_SHIFT                    (8U)
631 #define ADC_WTISR_WDG4L_WIDTH                    (1U)
632 #define ADC_WTISR_WDG4L(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG4L_SHIFT)) & ADC_WTISR_WDG4L_MASK)
633 
634 #define ADC_WTISR_WDG4H_MASK                     (0x200U)
635 #define ADC_WTISR_WDG4H_SHIFT                    (9U)
636 #define ADC_WTISR_WDG4H_WIDTH                    (1U)
637 #define ADC_WTISR_WDG4H(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG4H_SHIFT)) & ADC_WTISR_WDG4H_MASK)
638 
639 #define ADC_WTISR_WDG5L_MASK                     (0x400U)
640 #define ADC_WTISR_WDG5L_SHIFT                    (10U)
641 #define ADC_WTISR_WDG5L_WIDTH                    (1U)
642 #define ADC_WTISR_WDG5L(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG5L_SHIFT)) & ADC_WTISR_WDG5L_MASK)
643 
644 #define ADC_WTISR_WDG5H_MASK                     (0x800U)
645 #define ADC_WTISR_WDG5H_SHIFT                    (11U)
646 #define ADC_WTISR_WDG5H_WIDTH                    (1U)
647 #define ADC_WTISR_WDG5H(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG5H_SHIFT)) & ADC_WTISR_WDG5H_MASK)
648 
649 #define ADC_WTISR_WDG6L_MASK                     (0x1000U)
650 #define ADC_WTISR_WDG6L_SHIFT                    (12U)
651 #define ADC_WTISR_WDG6L_WIDTH                    (1U)
652 #define ADC_WTISR_WDG6L(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG6L_SHIFT)) & ADC_WTISR_WDG6L_MASK)
653 
654 #define ADC_WTISR_WDG6H_MASK                     (0x2000U)
655 #define ADC_WTISR_WDG6H_SHIFT                    (13U)
656 #define ADC_WTISR_WDG6H_WIDTH                    (1U)
657 #define ADC_WTISR_WDG6H(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG6H_SHIFT)) & ADC_WTISR_WDG6H_MASK)
658 
659 #define ADC_WTISR_WDG7L_MASK                     (0x4000U)
660 #define ADC_WTISR_WDG7L_SHIFT                    (14U)
661 #define ADC_WTISR_WDG7L_WIDTH                    (1U)
662 #define ADC_WTISR_WDG7L(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG7L_SHIFT)) & ADC_WTISR_WDG7L_MASK)
663 
664 #define ADC_WTISR_WDG7H_MASK                     (0x8000U)
665 #define ADC_WTISR_WDG7H_SHIFT                    (15U)
666 #define ADC_WTISR_WDG7H_WIDTH                    (1U)
667 #define ADC_WTISR_WDG7H(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG7H_SHIFT)) & ADC_WTISR_WDG7H_MASK)
668 /*! @} */
669 
670 /*! @name WTIMR - Watchdog Threshold Interrupt Mask */
671 /*! @{ */
672 
673 #define ADC_WTIMR_MSKWDG0L_MASK                  (0x1U)
674 #define ADC_WTIMR_MSKWDG0L_SHIFT                 (0U)
675 #define ADC_WTIMR_MSKWDG0L_WIDTH                 (1U)
676 #define ADC_WTIMR_MSKWDG0L(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG0L_SHIFT)) & ADC_WTIMR_MSKWDG0L_MASK)
677 
678 #define ADC_WTIMR_MSKWDG0H_MASK                  (0x2U)
679 #define ADC_WTIMR_MSKWDG0H_SHIFT                 (1U)
680 #define ADC_WTIMR_MSKWDG0H_WIDTH                 (1U)
681 #define ADC_WTIMR_MSKWDG0H(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG0H_SHIFT)) & ADC_WTIMR_MSKWDG0H_MASK)
682 
683 #define ADC_WTIMR_MSKWDG1L_MASK                  (0x4U)
684 #define ADC_WTIMR_MSKWDG1L_SHIFT                 (2U)
685 #define ADC_WTIMR_MSKWDG1L_WIDTH                 (1U)
686 #define ADC_WTIMR_MSKWDG1L(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG1L_SHIFT)) & ADC_WTIMR_MSKWDG1L_MASK)
687 
688 #define ADC_WTIMR_MSKWDG1H_MASK                  (0x8U)
689 #define ADC_WTIMR_MSKWDG1H_SHIFT                 (3U)
690 #define ADC_WTIMR_MSKWDG1H_WIDTH                 (1U)
691 #define ADC_WTIMR_MSKWDG1H(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG1H_SHIFT)) & ADC_WTIMR_MSKWDG1H_MASK)
692 
693 #define ADC_WTIMR_MSKWDG2L_MASK                  (0x10U)
694 #define ADC_WTIMR_MSKWDG2L_SHIFT                 (4U)
695 #define ADC_WTIMR_MSKWDG2L_WIDTH                 (1U)
696 #define ADC_WTIMR_MSKWDG2L(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG2L_SHIFT)) & ADC_WTIMR_MSKWDG2L_MASK)
697 
698 #define ADC_WTIMR_MSKWDG2H_MASK                  (0x20U)
699 #define ADC_WTIMR_MSKWDG2H_SHIFT                 (5U)
700 #define ADC_WTIMR_MSKWDG2H_WIDTH                 (1U)
701 #define ADC_WTIMR_MSKWDG2H(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG2H_SHIFT)) & ADC_WTIMR_MSKWDG2H_MASK)
702 
703 #define ADC_WTIMR_MSKWDG3L_MASK                  (0x40U)
704 #define ADC_WTIMR_MSKWDG3L_SHIFT                 (6U)
705 #define ADC_WTIMR_MSKWDG3L_WIDTH                 (1U)
706 #define ADC_WTIMR_MSKWDG3L(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG3L_SHIFT)) & ADC_WTIMR_MSKWDG3L_MASK)
707 
708 #define ADC_WTIMR_MSKWDG3H_MASK                  (0x80U)
709 #define ADC_WTIMR_MSKWDG3H_SHIFT                 (7U)
710 #define ADC_WTIMR_MSKWDG3H_WIDTH                 (1U)
711 #define ADC_WTIMR_MSKWDG3H(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG3H_SHIFT)) & ADC_WTIMR_MSKWDG3H_MASK)
712 
713 #define ADC_WTIMR_MSKWDG4L_MASK                  (0x100U)
714 #define ADC_WTIMR_MSKWDG4L_SHIFT                 (8U)
715 #define ADC_WTIMR_MSKWDG4L_WIDTH                 (1U)
716 #define ADC_WTIMR_MSKWDG4L(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG4L_SHIFT)) & ADC_WTIMR_MSKWDG4L_MASK)
717 
718 #define ADC_WTIMR_MSKWDG4H_MASK                  (0x200U)
719 #define ADC_WTIMR_MSKWDG4H_SHIFT                 (9U)
720 #define ADC_WTIMR_MSKWDG4H_WIDTH                 (1U)
721 #define ADC_WTIMR_MSKWDG4H(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG4H_SHIFT)) & ADC_WTIMR_MSKWDG4H_MASK)
722 
723 #define ADC_WTIMR_MSKWDG5L_MASK                  (0x400U)
724 #define ADC_WTIMR_MSKWDG5L_SHIFT                 (10U)
725 #define ADC_WTIMR_MSKWDG5L_WIDTH                 (1U)
726 #define ADC_WTIMR_MSKWDG5L(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG5L_SHIFT)) & ADC_WTIMR_MSKWDG5L_MASK)
727 
728 #define ADC_WTIMR_MSKWDG5H_MASK                  (0x800U)
729 #define ADC_WTIMR_MSKWDG5H_SHIFT                 (11U)
730 #define ADC_WTIMR_MSKWDG5H_WIDTH                 (1U)
731 #define ADC_WTIMR_MSKWDG5H(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG5H_SHIFT)) & ADC_WTIMR_MSKWDG5H_MASK)
732 
733 #define ADC_WTIMR_MSKWDG6L_MASK                  (0x1000U)
734 #define ADC_WTIMR_MSKWDG6L_SHIFT                 (12U)
735 #define ADC_WTIMR_MSKWDG6L_WIDTH                 (1U)
736 #define ADC_WTIMR_MSKWDG6L(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG6L_SHIFT)) & ADC_WTIMR_MSKWDG6L_MASK)
737 
738 #define ADC_WTIMR_MSKWDG6H_MASK                  (0x2000U)
739 #define ADC_WTIMR_MSKWDG6H_SHIFT                 (13U)
740 #define ADC_WTIMR_MSKWDG6H_WIDTH                 (1U)
741 #define ADC_WTIMR_MSKWDG6H(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG6H_SHIFT)) & ADC_WTIMR_MSKWDG6H_MASK)
742 
743 #define ADC_WTIMR_MSKWDG7L_MASK                  (0x4000U)
744 #define ADC_WTIMR_MSKWDG7L_SHIFT                 (14U)
745 #define ADC_WTIMR_MSKWDG7L_WIDTH                 (1U)
746 #define ADC_WTIMR_MSKWDG7L(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG7L_SHIFT)) & ADC_WTIMR_MSKWDG7L_MASK)
747 
748 #define ADC_WTIMR_MSKWDG7H_MASK                  (0x8000U)
749 #define ADC_WTIMR_MSKWDG7H_SHIFT                 (15U)
750 #define ADC_WTIMR_MSKWDG7H_WIDTH                 (1U)
751 #define ADC_WTIMR_MSKWDG7H(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG7H_SHIFT)) & ADC_WTIMR_MSKWDG7H_MASK)
752 /*! @} */
753 
754 /*! @name DMAE - DMAE */
755 /*! @{ */
756 
757 #define ADC_DMAE_DMAEN_MASK                      (0x1U)
758 #define ADC_DMAE_DMAEN_SHIFT                     (0U)
759 #define ADC_DMAE_DMAEN_WIDTH                     (1U)
760 #define ADC_DMAE_DMAEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_DMAE_DMAEN_SHIFT)) & ADC_DMAE_DMAEN_MASK)
761 
762 #define ADC_DMAE_DCLR_MASK                       (0x2U)
763 #define ADC_DMAE_DCLR_SHIFT                      (1U)
764 #define ADC_DMAE_DCLR_WIDTH                      (1U)
765 #define ADC_DMAE_DCLR(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_DMAE_DCLR_SHIFT)) & ADC_DMAE_DCLR_MASK)
766 /*! @} */
767 
768 /*! @name DMAR0 - DMA 0 */
769 /*! @{ */
770 
771 #define ADC_DMAR0_DMA0_MASK                      (0x1U)
772 #define ADC_DMAR0_DMA0_SHIFT                     (0U)
773 #define ADC_DMAR0_DMA0_WIDTH                     (1U)
774 #define ADC_DMAR0_DMA0(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA0_SHIFT)) & ADC_DMAR0_DMA0_MASK)
775 
776 #define ADC_DMAR0_DMA1_MASK                      (0x2U)
777 #define ADC_DMAR0_DMA1_SHIFT                     (1U)
778 #define ADC_DMAR0_DMA1_WIDTH                     (1U)
779 #define ADC_DMAR0_DMA1(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA1_SHIFT)) & ADC_DMAR0_DMA1_MASK)
780 
781 #define ADC_DMAR0_DMA2_MASK                      (0x4U)
782 #define ADC_DMAR0_DMA2_SHIFT                     (2U)
783 #define ADC_DMAR0_DMA2_WIDTH                     (1U)
784 #define ADC_DMAR0_DMA2(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA2_SHIFT)) & ADC_DMAR0_DMA2_MASK)
785 
786 #define ADC_DMAR0_DMA3_MASK                      (0x8U)
787 #define ADC_DMAR0_DMA3_SHIFT                     (3U)
788 #define ADC_DMAR0_DMA3_WIDTH                     (1U)
789 #define ADC_DMAR0_DMA3(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA3_SHIFT)) & ADC_DMAR0_DMA3_MASK)
790 
791 #define ADC_DMAR0_DMA4_MASK                      (0x10U)
792 #define ADC_DMAR0_DMA4_SHIFT                     (4U)
793 #define ADC_DMAR0_DMA4_WIDTH                     (1U)
794 #define ADC_DMAR0_DMA4(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA4_SHIFT)) & ADC_DMAR0_DMA4_MASK)
795 
796 #define ADC_DMAR0_DMA5_MASK                      (0x20U)
797 #define ADC_DMAR0_DMA5_SHIFT                     (5U)
798 #define ADC_DMAR0_DMA5_WIDTH                     (1U)
799 #define ADC_DMAR0_DMA5(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA5_SHIFT)) & ADC_DMAR0_DMA5_MASK)
800 
801 #define ADC_DMAR0_DMA6_MASK                      (0x40U)
802 #define ADC_DMAR0_DMA6_SHIFT                     (6U)
803 #define ADC_DMAR0_DMA6_WIDTH                     (1U)
804 #define ADC_DMAR0_DMA6(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA6_SHIFT)) & ADC_DMAR0_DMA6_MASK)
805 
806 #define ADC_DMAR0_DMA7_MASK                      (0x80U)
807 #define ADC_DMAR0_DMA7_SHIFT                     (7U)
808 #define ADC_DMAR0_DMA7_WIDTH                     (1U)
809 #define ADC_DMAR0_DMA7(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA7_SHIFT)) & ADC_DMAR0_DMA7_MASK)
810 /*! @} */
811 
812 /*! @name DMAR1 - DMA 1 */
813 /*! @{ */
814 
815 #define ADC_DMAR1_DMA32_MASK                     (0x1U)
816 #define ADC_DMAR1_DMA32_SHIFT                    (0U)
817 #define ADC_DMAR1_DMA32_WIDTH                    (1U)
818 #define ADC_DMAR1_DMA32(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA32_SHIFT)) & ADC_DMAR1_DMA32_MASK)
819 
820 #define ADC_DMAR1_DMA33_MASK                     (0x2U)
821 #define ADC_DMAR1_DMA33_SHIFT                    (1U)
822 #define ADC_DMAR1_DMA33_WIDTH                    (1U)
823 #define ADC_DMAR1_DMA33(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA33_SHIFT)) & ADC_DMAR1_DMA33_MASK)
824 
825 #define ADC_DMAR1_DMA34_MASK                     (0x4U)
826 #define ADC_DMAR1_DMA34_SHIFT                    (2U)
827 #define ADC_DMAR1_DMA34_WIDTH                    (1U)
828 #define ADC_DMAR1_DMA34(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA34_SHIFT)) & ADC_DMAR1_DMA34_MASK)
829 
830 #define ADC_DMAR1_DMA35_MASK                     (0x8U)
831 #define ADC_DMAR1_DMA35_SHIFT                    (3U)
832 #define ADC_DMAR1_DMA35_WIDTH                    (1U)
833 #define ADC_DMAR1_DMA35(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA35_SHIFT)) & ADC_DMAR1_DMA35_MASK)
834 
835 #define ADC_DMAR1_DMA36_MASK                     (0x10U)
836 #define ADC_DMAR1_DMA36_SHIFT                    (4U)
837 #define ADC_DMAR1_DMA36_WIDTH                    (1U)
838 #define ADC_DMAR1_DMA36(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA36_SHIFT)) & ADC_DMAR1_DMA36_MASK)
839 
840 #define ADC_DMAR1_DMA37_MASK                     (0x20U)
841 #define ADC_DMAR1_DMA37_SHIFT                    (5U)
842 #define ADC_DMAR1_DMA37_WIDTH                    (1U)
843 #define ADC_DMAR1_DMA37(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA37_SHIFT)) & ADC_DMAR1_DMA37_MASK)
844 
845 #define ADC_DMAR1_DMA38_MASK                     (0x40U)
846 #define ADC_DMAR1_DMA38_SHIFT                    (6U)
847 #define ADC_DMAR1_DMA38_WIDTH                    (1U)
848 #define ADC_DMAR1_DMA38(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA38_SHIFT)) & ADC_DMAR1_DMA38_MASK)
849 
850 #define ADC_DMAR1_DMA39_MASK                     (0x80U)
851 #define ADC_DMAR1_DMA39_SHIFT                    (7U)
852 #define ADC_DMAR1_DMA39_WIDTH                    (1U)
853 #define ADC_DMAR1_DMA39(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA39_SHIFT)) & ADC_DMAR1_DMA39_MASK)
854 /*! @} */
855 
856 /*! @name THRHLR0 - Analog Watchdog Threshold 0 */
857 /*! @{ */
858 
859 #define ADC_THRHLR0_THRL_MASK                    (0xFFFU)
860 #define ADC_THRHLR0_THRL_SHIFT                   (0U)
861 #define ADC_THRHLR0_THRL_WIDTH                   (12U)
862 #define ADC_THRHLR0_THRL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR0_THRL_SHIFT)) & ADC_THRHLR0_THRL_MASK)
863 
864 #define ADC_THRHLR0_THRH_MASK                    (0xFFF0000U)
865 #define ADC_THRHLR0_THRH_SHIFT                   (16U)
866 #define ADC_THRHLR0_THRH_WIDTH                   (12U)
867 #define ADC_THRHLR0_THRH(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR0_THRH_SHIFT)) & ADC_THRHLR0_THRH_MASK)
868 /*! @} */
869 
870 /*! @name THRHLR1 - Analog Watchdog Threshold 1 */
871 /*! @{ */
872 
873 #define ADC_THRHLR1_THRL_MASK                    (0xFFFU)
874 #define ADC_THRHLR1_THRL_SHIFT                   (0U)
875 #define ADC_THRHLR1_THRL_WIDTH                   (12U)
876 #define ADC_THRHLR1_THRL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR1_THRL_SHIFT)) & ADC_THRHLR1_THRL_MASK)
877 
878 #define ADC_THRHLR1_THRH_MASK                    (0xFFF0000U)
879 #define ADC_THRHLR1_THRH_SHIFT                   (16U)
880 #define ADC_THRHLR1_THRH_WIDTH                   (12U)
881 #define ADC_THRHLR1_THRH(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR1_THRH_SHIFT)) & ADC_THRHLR1_THRH_MASK)
882 /*! @} */
883 
884 /*! @name THRHLR2 - Analog Watchdog Threshold 2 */
885 /*! @{ */
886 
887 #define ADC_THRHLR2_THRL_MASK                    (0xFFFU)
888 #define ADC_THRHLR2_THRL_SHIFT                   (0U)
889 #define ADC_THRHLR2_THRL_WIDTH                   (12U)
890 #define ADC_THRHLR2_THRL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR2_THRL_SHIFT)) & ADC_THRHLR2_THRL_MASK)
891 
892 #define ADC_THRHLR2_THRH_MASK                    (0xFFF0000U)
893 #define ADC_THRHLR2_THRH_SHIFT                   (16U)
894 #define ADC_THRHLR2_THRH_WIDTH                   (12U)
895 #define ADC_THRHLR2_THRH(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR2_THRH_SHIFT)) & ADC_THRHLR2_THRH_MASK)
896 /*! @} */
897 
898 /*! @name THRHLR3 - Analog Watchdog Threshold 3 */
899 /*! @{ */
900 
901 #define ADC_THRHLR3_THRL_MASK                    (0xFFFU)
902 #define ADC_THRHLR3_THRL_SHIFT                   (0U)
903 #define ADC_THRHLR3_THRL_WIDTH                   (12U)
904 #define ADC_THRHLR3_THRL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR3_THRL_SHIFT)) & ADC_THRHLR3_THRL_MASK)
905 
906 #define ADC_THRHLR3_THRH_MASK                    (0xFFF0000U)
907 #define ADC_THRHLR3_THRH_SHIFT                   (16U)
908 #define ADC_THRHLR3_THRH_WIDTH                   (12U)
909 #define ADC_THRHLR3_THRH(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR3_THRH_SHIFT)) & ADC_THRHLR3_THRH_MASK)
910 /*! @} */
911 
912 /*! @name PSCR - Presampling Control */
913 /*! @{ */
914 
915 #define ADC_PSCR_PRECONV_MASK                    (0x1U)
916 #define ADC_PSCR_PRECONV_SHIFT                   (0U)
917 #define ADC_PSCR_PRECONV_WIDTH                   (1U)
918 #define ADC_PSCR_PRECONV(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_PSCR_PRECONV_SHIFT)) & ADC_PSCR_PRECONV_MASK)
919 
920 #define ADC_PSCR_PREVAL0_MASK                    (0x6U)
921 #define ADC_PSCR_PREVAL0_SHIFT                   (1U)
922 #define ADC_PSCR_PREVAL0_WIDTH                   (2U)
923 #define ADC_PSCR_PREVAL0(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_PSCR_PREVAL0_SHIFT)) & ADC_PSCR_PREVAL0_MASK)
924 
925 #define ADC_PSCR_PREVAL1_MASK                    (0x18U)
926 #define ADC_PSCR_PREVAL1_SHIFT                   (3U)
927 #define ADC_PSCR_PREVAL1_WIDTH                   (2U)
928 #define ADC_PSCR_PREVAL1(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_PSCR_PREVAL1_SHIFT)) & ADC_PSCR_PREVAL1_MASK)
929 /*! @} */
930 
931 /*! @name PSR0 - Presampling 0 */
932 /*! @{ */
933 
934 #define ADC_PSR0_PRES0_MASK                      (0x1U)
935 #define ADC_PSR0_PRES0_SHIFT                     (0U)
936 #define ADC_PSR0_PRES0_WIDTH                     (1U)
937 #define ADC_PSR0_PRES0(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES0_SHIFT)) & ADC_PSR0_PRES0_MASK)
938 
939 #define ADC_PSR0_PRES1_MASK                      (0x2U)
940 #define ADC_PSR0_PRES1_SHIFT                     (1U)
941 #define ADC_PSR0_PRES1_WIDTH                     (1U)
942 #define ADC_PSR0_PRES1(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES1_SHIFT)) & ADC_PSR0_PRES1_MASK)
943 
944 #define ADC_PSR0_PRES2_MASK                      (0x4U)
945 #define ADC_PSR0_PRES2_SHIFT                     (2U)
946 #define ADC_PSR0_PRES2_WIDTH                     (1U)
947 #define ADC_PSR0_PRES2(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES2_SHIFT)) & ADC_PSR0_PRES2_MASK)
948 
949 #define ADC_PSR0_PRES3_MASK                      (0x8U)
950 #define ADC_PSR0_PRES3_SHIFT                     (3U)
951 #define ADC_PSR0_PRES3_WIDTH                     (1U)
952 #define ADC_PSR0_PRES3(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES3_SHIFT)) & ADC_PSR0_PRES3_MASK)
953 
954 #define ADC_PSR0_PRES4_MASK                      (0x10U)
955 #define ADC_PSR0_PRES4_SHIFT                     (4U)
956 #define ADC_PSR0_PRES4_WIDTH                     (1U)
957 #define ADC_PSR0_PRES4(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES4_SHIFT)) & ADC_PSR0_PRES4_MASK)
958 
959 #define ADC_PSR0_PRES5_MASK                      (0x20U)
960 #define ADC_PSR0_PRES5_SHIFT                     (5U)
961 #define ADC_PSR0_PRES5_WIDTH                     (1U)
962 #define ADC_PSR0_PRES5(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES5_SHIFT)) & ADC_PSR0_PRES5_MASK)
963 
964 #define ADC_PSR0_PRES6_MASK                      (0x40U)
965 #define ADC_PSR0_PRES6_SHIFT                     (6U)
966 #define ADC_PSR0_PRES6_WIDTH                     (1U)
967 #define ADC_PSR0_PRES6(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES6_SHIFT)) & ADC_PSR0_PRES6_MASK)
968 
969 #define ADC_PSR0_PRES7_MASK                      (0x80U)
970 #define ADC_PSR0_PRES7_SHIFT                     (7U)
971 #define ADC_PSR0_PRES7_WIDTH                     (1U)
972 #define ADC_PSR0_PRES7(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES7_SHIFT)) & ADC_PSR0_PRES7_MASK)
973 /*! @} */
974 
975 /*! @name PSR1 - Presampling 1 */
976 /*! @{ */
977 
978 #define ADC_PSR1_PRES32_MASK                     (0x1U)
979 #define ADC_PSR1_PRES32_SHIFT                    (0U)
980 #define ADC_PSR1_PRES32_WIDTH                    (1U)
981 #define ADC_PSR1_PRES32(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES32_SHIFT)) & ADC_PSR1_PRES32_MASK)
982 
983 #define ADC_PSR1_PRES33_MASK                     (0x2U)
984 #define ADC_PSR1_PRES33_SHIFT                    (1U)
985 #define ADC_PSR1_PRES33_WIDTH                    (1U)
986 #define ADC_PSR1_PRES33(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES33_SHIFT)) & ADC_PSR1_PRES33_MASK)
987 
988 #define ADC_PSR1_PRES34_MASK                     (0x4U)
989 #define ADC_PSR1_PRES34_SHIFT                    (2U)
990 #define ADC_PSR1_PRES34_WIDTH                    (1U)
991 #define ADC_PSR1_PRES34(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES34_SHIFT)) & ADC_PSR1_PRES34_MASK)
992 
993 #define ADC_PSR1_PRES35_MASK                     (0x8U)
994 #define ADC_PSR1_PRES35_SHIFT                    (3U)
995 #define ADC_PSR1_PRES35_WIDTH                    (1U)
996 #define ADC_PSR1_PRES35(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES35_SHIFT)) & ADC_PSR1_PRES35_MASK)
997 
998 #define ADC_PSR1_PRES36_MASK                     (0x10U)
999 #define ADC_PSR1_PRES36_SHIFT                    (4U)
1000 #define ADC_PSR1_PRES36_WIDTH                    (1U)
1001 #define ADC_PSR1_PRES36(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES36_SHIFT)) & ADC_PSR1_PRES36_MASK)
1002 
1003 #define ADC_PSR1_PRES37_MASK                     (0x20U)
1004 #define ADC_PSR1_PRES37_SHIFT                    (5U)
1005 #define ADC_PSR1_PRES37_WIDTH                    (1U)
1006 #define ADC_PSR1_PRES37(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES37_SHIFT)) & ADC_PSR1_PRES37_MASK)
1007 
1008 #define ADC_PSR1_PRES38_MASK                     (0x40U)
1009 #define ADC_PSR1_PRES38_SHIFT                    (6U)
1010 #define ADC_PSR1_PRES38_WIDTH                    (1U)
1011 #define ADC_PSR1_PRES38(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES38_SHIFT)) & ADC_PSR1_PRES38_MASK)
1012 
1013 #define ADC_PSR1_PRES39_MASK                     (0x80U)
1014 #define ADC_PSR1_PRES39_SHIFT                    (7U)
1015 #define ADC_PSR1_PRES39_WIDTH                    (1U)
1016 #define ADC_PSR1_PRES39(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES39_SHIFT)) & ADC_PSR1_PRES39_MASK)
1017 /*! @} */
1018 
1019 /*! @name CTR0 - Conversion Timing 0 */
1020 /*! @{ */
1021 
1022 #define ADC_CTR0_INPSAMP_MASK                    (0xFFU)
1023 #define ADC_CTR0_INPSAMP_SHIFT                   (0U)
1024 #define ADC_CTR0_INPSAMP_WIDTH                   (8U)
1025 #define ADC_CTR0_INPSAMP(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CTR0_INPSAMP_SHIFT)) & ADC_CTR0_INPSAMP_MASK)
1026 /*! @} */
1027 
1028 /*! @name CTR1 - Conversion Timing 1 */
1029 /*! @{ */
1030 
1031 #define ADC_CTR1_INPSAMP_MASK                    (0xFFU)
1032 #define ADC_CTR1_INPSAMP_SHIFT                   (0U)
1033 #define ADC_CTR1_INPSAMP_WIDTH                   (8U)
1034 #define ADC_CTR1_INPSAMP(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CTR1_INPSAMP_SHIFT)) & ADC_CTR1_INPSAMP_MASK)
1035 /*! @} */
1036 
1037 /*! @name NCMR0 - Normal Conversion Mask 0 */
1038 /*! @{ */
1039 
1040 #define ADC_NCMR0_CH0_MASK                       (0x1U)
1041 #define ADC_NCMR0_CH0_SHIFT                      (0U)
1042 #define ADC_NCMR0_CH0_WIDTH                      (1U)
1043 #define ADC_NCMR0_CH0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH0_SHIFT)) & ADC_NCMR0_CH0_MASK)
1044 
1045 #define ADC_NCMR0_CH1_MASK                       (0x2U)
1046 #define ADC_NCMR0_CH1_SHIFT                      (1U)
1047 #define ADC_NCMR0_CH1_WIDTH                      (1U)
1048 #define ADC_NCMR0_CH1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH1_SHIFT)) & ADC_NCMR0_CH1_MASK)
1049 
1050 #define ADC_NCMR0_CH2_MASK                       (0x4U)
1051 #define ADC_NCMR0_CH2_SHIFT                      (2U)
1052 #define ADC_NCMR0_CH2_WIDTH                      (1U)
1053 #define ADC_NCMR0_CH2(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH2_SHIFT)) & ADC_NCMR0_CH2_MASK)
1054 
1055 #define ADC_NCMR0_CH3_MASK                       (0x8U)
1056 #define ADC_NCMR0_CH3_SHIFT                      (3U)
1057 #define ADC_NCMR0_CH3_WIDTH                      (1U)
1058 #define ADC_NCMR0_CH3(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH3_SHIFT)) & ADC_NCMR0_CH3_MASK)
1059 
1060 #define ADC_NCMR0_CH4_MASK                       (0x10U)
1061 #define ADC_NCMR0_CH4_SHIFT                      (4U)
1062 #define ADC_NCMR0_CH4_WIDTH                      (1U)
1063 #define ADC_NCMR0_CH4(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH4_SHIFT)) & ADC_NCMR0_CH4_MASK)
1064 
1065 #define ADC_NCMR0_CH5_MASK                       (0x20U)
1066 #define ADC_NCMR0_CH5_SHIFT                      (5U)
1067 #define ADC_NCMR0_CH5_WIDTH                      (1U)
1068 #define ADC_NCMR0_CH5(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH5_SHIFT)) & ADC_NCMR0_CH5_MASK)
1069 
1070 #define ADC_NCMR0_CH6_MASK                       (0x40U)
1071 #define ADC_NCMR0_CH6_SHIFT                      (6U)
1072 #define ADC_NCMR0_CH6_WIDTH                      (1U)
1073 #define ADC_NCMR0_CH6(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH6_SHIFT)) & ADC_NCMR0_CH6_MASK)
1074 
1075 #define ADC_NCMR0_CH7_MASK                       (0x80U)
1076 #define ADC_NCMR0_CH7_SHIFT                      (7U)
1077 #define ADC_NCMR0_CH7_WIDTH                      (1U)
1078 #define ADC_NCMR0_CH7(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH7_SHIFT)) & ADC_NCMR0_CH7_MASK)
1079 /*! @} */
1080 
1081 /*! @name NCMR1 - Normal Conversion Mask 1 */
1082 /*! @{ */
1083 
1084 #define ADC_NCMR1_CH32_MASK                      (0x1U)
1085 #define ADC_NCMR1_CH32_SHIFT                     (0U)
1086 #define ADC_NCMR1_CH32_WIDTH                     (1U)
1087 #define ADC_NCMR1_CH32(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH32_SHIFT)) & ADC_NCMR1_CH32_MASK)
1088 
1089 #define ADC_NCMR1_CH33_MASK                      (0x2U)
1090 #define ADC_NCMR1_CH33_SHIFT                     (1U)
1091 #define ADC_NCMR1_CH33_WIDTH                     (1U)
1092 #define ADC_NCMR1_CH33(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH33_SHIFT)) & ADC_NCMR1_CH33_MASK)
1093 
1094 #define ADC_NCMR1_CH34_MASK                      (0x4U)
1095 #define ADC_NCMR1_CH34_SHIFT                     (2U)
1096 #define ADC_NCMR1_CH34_WIDTH                     (1U)
1097 #define ADC_NCMR1_CH34(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH34_SHIFT)) & ADC_NCMR1_CH34_MASK)
1098 
1099 #define ADC_NCMR1_CH35_MASK                      (0x8U)
1100 #define ADC_NCMR1_CH35_SHIFT                     (3U)
1101 #define ADC_NCMR1_CH35_WIDTH                     (1U)
1102 #define ADC_NCMR1_CH35(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH35_SHIFT)) & ADC_NCMR1_CH35_MASK)
1103 
1104 #define ADC_NCMR1_CH36_MASK                      (0x10U)
1105 #define ADC_NCMR1_CH36_SHIFT                     (4U)
1106 #define ADC_NCMR1_CH36_WIDTH                     (1U)
1107 #define ADC_NCMR1_CH36(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH36_SHIFT)) & ADC_NCMR1_CH36_MASK)
1108 
1109 #define ADC_NCMR1_CH37_MASK                      (0x20U)
1110 #define ADC_NCMR1_CH37_SHIFT                     (5U)
1111 #define ADC_NCMR1_CH37_WIDTH                     (1U)
1112 #define ADC_NCMR1_CH37(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH37_SHIFT)) & ADC_NCMR1_CH37_MASK)
1113 
1114 #define ADC_NCMR1_CH38_MASK                      (0x40U)
1115 #define ADC_NCMR1_CH38_SHIFT                     (6U)
1116 #define ADC_NCMR1_CH38_WIDTH                     (1U)
1117 #define ADC_NCMR1_CH38(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH38_SHIFT)) & ADC_NCMR1_CH38_MASK)
1118 
1119 #define ADC_NCMR1_CH39_MASK                      (0x80U)
1120 #define ADC_NCMR1_CH39_SHIFT                     (7U)
1121 #define ADC_NCMR1_CH39_WIDTH                     (1U)
1122 #define ADC_NCMR1_CH39(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH39_SHIFT)) & ADC_NCMR1_CH39_MASK)
1123 /*! @} */
1124 
1125 /*! @name JCMR0 - Injected Conversion Mask 0 */
1126 /*! @{ */
1127 
1128 #define ADC_JCMR0_CH0_MASK                       (0x1U)
1129 #define ADC_JCMR0_CH0_SHIFT                      (0U)
1130 #define ADC_JCMR0_CH0_WIDTH                      (1U)
1131 #define ADC_JCMR0_CH0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH0_SHIFT)) & ADC_JCMR0_CH0_MASK)
1132 
1133 #define ADC_JCMR0_CH1_MASK                       (0x2U)
1134 #define ADC_JCMR0_CH1_SHIFT                      (1U)
1135 #define ADC_JCMR0_CH1_WIDTH                      (1U)
1136 #define ADC_JCMR0_CH1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH1_SHIFT)) & ADC_JCMR0_CH1_MASK)
1137 
1138 #define ADC_JCMR0_CH2_MASK                       (0x4U)
1139 #define ADC_JCMR0_CH2_SHIFT                      (2U)
1140 #define ADC_JCMR0_CH2_WIDTH                      (1U)
1141 #define ADC_JCMR0_CH2(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH2_SHIFT)) & ADC_JCMR0_CH2_MASK)
1142 
1143 #define ADC_JCMR0_CH3_MASK                       (0x8U)
1144 #define ADC_JCMR0_CH3_SHIFT                      (3U)
1145 #define ADC_JCMR0_CH3_WIDTH                      (1U)
1146 #define ADC_JCMR0_CH3(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH3_SHIFT)) & ADC_JCMR0_CH3_MASK)
1147 
1148 #define ADC_JCMR0_CH4_MASK                       (0x10U)
1149 #define ADC_JCMR0_CH4_SHIFT                      (4U)
1150 #define ADC_JCMR0_CH4_WIDTH                      (1U)
1151 #define ADC_JCMR0_CH4(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH4_SHIFT)) & ADC_JCMR0_CH4_MASK)
1152 
1153 #define ADC_JCMR0_CH5_MASK                       (0x20U)
1154 #define ADC_JCMR0_CH5_SHIFT                      (5U)
1155 #define ADC_JCMR0_CH5_WIDTH                      (1U)
1156 #define ADC_JCMR0_CH5(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH5_SHIFT)) & ADC_JCMR0_CH5_MASK)
1157 
1158 #define ADC_JCMR0_CH6_MASK                       (0x40U)
1159 #define ADC_JCMR0_CH6_SHIFT                      (6U)
1160 #define ADC_JCMR0_CH6_WIDTH                      (1U)
1161 #define ADC_JCMR0_CH6(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH6_SHIFT)) & ADC_JCMR0_CH6_MASK)
1162 
1163 #define ADC_JCMR0_CH7_MASK                       (0x80U)
1164 #define ADC_JCMR0_CH7_SHIFT                      (7U)
1165 #define ADC_JCMR0_CH7_WIDTH                      (1U)
1166 #define ADC_JCMR0_CH7(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH7_SHIFT)) & ADC_JCMR0_CH7_MASK)
1167 /*! @} */
1168 
1169 /*! @name JCMR1 - Injected Conversion Mask 1 */
1170 /*! @{ */
1171 
1172 #define ADC_JCMR1_CH32_MASK                      (0x1U)
1173 #define ADC_JCMR1_CH32_SHIFT                     (0U)
1174 #define ADC_JCMR1_CH32_WIDTH                     (1U)
1175 #define ADC_JCMR1_CH32(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH32_SHIFT)) & ADC_JCMR1_CH32_MASK)
1176 
1177 #define ADC_JCMR1_CH33_MASK                      (0x2U)
1178 #define ADC_JCMR1_CH33_SHIFT                     (1U)
1179 #define ADC_JCMR1_CH33_WIDTH                     (1U)
1180 #define ADC_JCMR1_CH33(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH33_SHIFT)) & ADC_JCMR1_CH33_MASK)
1181 
1182 #define ADC_JCMR1_CH34_MASK                      (0x4U)
1183 #define ADC_JCMR1_CH34_SHIFT                     (2U)
1184 #define ADC_JCMR1_CH34_WIDTH                     (1U)
1185 #define ADC_JCMR1_CH34(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH34_SHIFT)) & ADC_JCMR1_CH34_MASK)
1186 
1187 #define ADC_JCMR1_CH35_MASK                      (0x8U)
1188 #define ADC_JCMR1_CH35_SHIFT                     (3U)
1189 #define ADC_JCMR1_CH35_WIDTH                     (1U)
1190 #define ADC_JCMR1_CH35(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH35_SHIFT)) & ADC_JCMR1_CH35_MASK)
1191 
1192 #define ADC_JCMR1_CH36_MASK                      (0x10U)
1193 #define ADC_JCMR1_CH36_SHIFT                     (4U)
1194 #define ADC_JCMR1_CH36_WIDTH                     (1U)
1195 #define ADC_JCMR1_CH36(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH36_SHIFT)) & ADC_JCMR1_CH36_MASK)
1196 
1197 #define ADC_JCMR1_CH37_MASK                      (0x20U)
1198 #define ADC_JCMR1_CH37_SHIFT                     (5U)
1199 #define ADC_JCMR1_CH37_WIDTH                     (1U)
1200 #define ADC_JCMR1_CH37(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH37_SHIFT)) & ADC_JCMR1_CH37_MASK)
1201 
1202 #define ADC_JCMR1_CH38_MASK                      (0x40U)
1203 #define ADC_JCMR1_CH38_SHIFT                     (6U)
1204 #define ADC_JCMR1_CH38_WIDTH                     (1U)
1205 #define ADC_JCMR1_CH38(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH38_SHIFT)) & ADC_JCMR1_CH38_MASK)
1206 
1207 #define ADC_JCMR1_CH39_MASK                      (0x80U)
1208 #define ADC_JCMR1_CH39_SHIFT                     (7U)
1209 #define ADC_JCMR1_CH39_WIDTH                     (1U)
1210 #define ADC_JCMR1_CH39(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH39_SHIFT)) & ADC_JCMR1_CH39_MASK)
1211 /*! @} */
1212 
1213 /*! @name USROFSGN - User OFFSET and Gain */
1214 /*! @{ */
1215 
1216 #define ADC_USROFSGN_OFFSUSER_MASK               (0xFFU)
1217 #define ADC_USROFSGN_OFFSUSER_SHIFT              (0U)
1218 #define ADC_USROFSGN_OFFSUSER_WIDTH              (8U)
1219 #define ADC_USROFSGN_OFFSUSER(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_USROFSGN_OFFSUSER_SHIFT)) & ADC_USROFSGN_OFFSUSER_MASK)
1220 
1221 #define ADC_USROFSGN_GAINUSER_MASK               (0x3FF0000U)
1222 #define ADC_USROFSGN_GAINUSER_SHIFT              (16U)
1223 #define ADC_USROFSGN_GAINUSER_WIDTH              (10U)
1224 #define ADC_USROFSGN_GAINUSER(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_USROFSGN_GAINUSER_SHIFT)) & ADC_USROFSGN_GAINUSER_MASK)
1225 /*! @} */
1226 
1227 /*! @name PDEDR - Power Down Exit Delay */
1228 /*! @{ */
1229 
1230 #define ADC_PDEDR_PDED_MASK                      (0xFFU)
1231 #define ADC_PDEDR_PDED_SHIFT                     (0U)
1232 #define ADC_PDEDR_PDED_WIDTH                     (8U)
1233 #define ADC_PDEDR_PDED(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_PDEDR_PDED_SHIFT)) & ADC_PDEDR_PDED_MASK)
1234 /*! @} */
1235 
1236 /*! @name PCDR - Precision Channel n Data */
1237 /*! @{ */
1238 
1239 #define ADC_PCDR_CDATA_MASK                      (0xFFFU)
1240 #define ADC_PCDR_CDATA_SHIFT                     (0U)
1241 #define ADC_PCDR_CDATA_WIDTH                     (12U)
1242 #define ADC_PCDR_CDATA(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_PCDR_CDATA_SHIFT)) & ADC_PCDR_CDATA_MASK)
1243 
1244 #define ADC_PCDR_RESULT_MASK                     (0x30000U)
1245 #define ADC_PCDR_RESULT_SHIFT                    (16U)
1246 #define ADC_PCDR_RESULT_WIDTH                    (2U)
1247 #define ADC_PCDR_RESULT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_PCDR_RESULT_SHIFT)) & ADC_PCDR_RESULT_MASK)
1248 
1249 #define ADC_PCDR_OVERW_MASK                      (0x40000U)
1250 #define ADC_PCDR_OVERW_SHIFT                     (18U)
1251 #define ADC_PCDR_OVERW_WIDTH                     (1U)
1252 #define ADC_PCDR_OVERW(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_PCDR_OVERW_SHIFT)) & ADC_PCDR_OVERW_MASK)
1253 
1254 #define ADC_PCDR_VALID_MASK                      (0x80000U)
1255 #define ADC_PCDR_VALID_SHIFT                     (19U)
1256 #define ADC_PCDR_VALID_WIDTH                     (1U)
1257 #define ADC_PCDR_VALID(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_PCDR_VALID_SHIFT)) & ADC_PCDR_VALID_MASK)
1258 /*! @} */
1259 
1260 /*! @name ICDR - Internal Channel n Data */
1261 /*! @{ */
1262 
1263 #define ADC_ICDR_CDATA_MASK                      (0xFFFU)
1264 #define ADC_ICDR_CDATA_SHIFT                     (0U)
1265 #define ADC_ICDR_CDATA_WIDTH                     (12U)
1266 #define ADC_ICDR_CDATA(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_ICDR_CDATA_SHIFT)) & ADC_ICDR_CDATA_MASK)
1267 
1268 #define ADC_ICDR_RESULT_MASK                     (0x30000U)
1269 #define ADC_ICDR_RESULT_SHIFT                    (16U)
1270 #define ADC_ICDR_RESULT_WIDTH                    (2U)
1271 #define ADC_ICDR_RESULT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_ICDR_RESULT_SHIFT)) & ADC_ICDR_RESULT_MASK)
1272 
1273 #define ADC_ICDR_OVERW_MASK                      (0x40000U)
1274 #define ADC_ICDR_OVERW_SHIFT                     (18U)
1275 #define ADC_ICDR_OVERW_WIDTH                     (1U)
1276 #define ADC_ICDR_OVERW(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_ICDR_OVERW_SHIFT)) & ADC_ICDR_OVERW_MASK)
1277 
1278 #define ADC_ICDR_VALID_MASK                      (0x80000U)
1279 #define ADC_ICDR_VALID_SHIFT                     (19U)
1280 #define ADC_ICDR_VALID_WIDTH                     (1U)
1281 #define ADC_ICDR_VALID(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_ICDR_VALID_SHIFT)) & ADC_ICDR_VALID_MASK)
1282 /*! @} */
1283 
1284 /*! @name THRHLR4 - Analog Watchdog Threshold 4 */
1285 /*! @{ */
1286 
1287 #define ADC_THRHLR4_THRL_MASK                    (0xFFFU)
1288 #define ADC_THRHLR4_THRL_SHIFT                   (0U)
1289 #define ADC_THRHLR4_THRL_WIDTH                   (12U)
1290 #define ADC_THRHLR4_THRL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR4_THRL_SHIFT)) & ADC_THRHLR4_THRL_MASK)
1291 
1292 #define ADC_THRHLR4_THRH_MASK                    (0xFFF0000U)
1293 #define ADC_THRHLR4_THRH_SHIFT                   (16U)
1294 #define ADC_THRHLR4_THRH_WIDTH                   (12U)
1295 #define ADC_THRHLR4_THRH(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR4_THRH_SHIFT)) & ADC_THRHLR4_THRH_MASK)
1296 /*! @} */
1297 
1298 /*! @name THRHLR5 - Analog Watchdog Threshold 5 */
1299 /*! @{ */
1300 
1301 #define ADC_THRHLR5_THRL_MASK                    (0xFFFU)
1302 #define ADC_THRHLR5_THRL_SHIFT                   (0U)
1303 #define ADC_THRHLR5_THRL_WIDTH                   (12U)
1304 #define ADC_THRHLR5_THRL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR5_THRL_SHIFT)) & ADC_THRHLR5_THRL_MASK)
1305 
1306 #define ADC_THRHLR5_THRH_MASK                    (0xFFF0000U)
1307 #define ADC_THRHLR5_THRH_SHIFT                   (16U)
1308 #define ADC_THRHLR5_THRH_WIDTH                   (12U)
1309 #define ADC_THRHLR5_THRH(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR5_THRH_SHIFT)) & ADC_THRHLR5_THRH_MASK)
1310 /*! @} */
1311 
1312 /*! @name THRHLR6 - Analog Watchdog Threshold 6 */
1313 /*! @{ */
1314 
1315 #define ADC_THRHLR6_THRL_MASK                    (0xFFFU)
1316 #define ADC_THRHLR6_THRL_SHIFT                   (0U)
1317 #define ADC_THRHLR6_THRL_WIDTH                   (12U)
1318 #define ADC_THRHLR6_THRL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR6_THRL_SHIFT)) & ADC_THRHLR6_THRL_MASK)
1319 
1320 #define ADC_THRHLR6_THRH_MASK                    (0xFFF0000U)
1321 #define ADC_THRHLR6_THRH_SHIFT                   (16U)
1322 #define ADC_THRHLR6_THRH_WIDTH                   (12U)
1323 #define ADC_THRHLR6_THRH(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR6_THRH_SHIFT)) & ADC_THRHLR6_THRH_MASK)
1324 /*! @} */
1325 
1326 /*! @name THRHLR7 - Analog Watchdog Threshold 7 */
1327 /*! @{ */
1328 
1329 #define ADC_THRHLR7_THRL_MASK                    (0xFFFU)
1330 #define ADC_THRHLR7_THRL_SHIFT                   (0U)
1331 #define ADC_THRHLR7_THRL_WIDTH                   (12U)
1332 #define ADC_THRHLR7_THRL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR7_THRL_SHIFT)) & ADC_THRHLR7_THRL_MASK)
1333 
1334 #define ADC_THRHLR7_THRH_MASK                    (0xFFF0000U)
1335 #define ADC_THRHLR7_THRH_SHIFT                   (16U)
1336 #define ADC_THRHLR7_THRH_WIDTH                   (12U)
1337 #define ADC_THRHLR7_THRH(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR7_THRH_SHIFT)) & ADC_THRHLR7_THRH_MASK)
1338 /*! @} */
1339 
1340 /*! @name CWSELR0 - Channel Watchdog Select 0 */
1341 /*! @{ */
1342 
1343 #define ADC_CWSELR0_WSEL_CH0_MASK                (0x7U)
1344 #define ADC_CWSELR0_WSEL_CH0_SHIFT               (0U)
1345 #define ADC_CWSELR0_WSEL_CH0_WIDTH               (3U)
1346 #define ADC_CWSELR0_WSEL_CH0(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH0_SHIFT)) & ADC_CWSELR0_WSEL_CH0_MASK)
1347 
1348 #define ADC_CWSELR0_WSEL_CH1_MASK                (0x70U)
1349 #define ADC_CWSELR0_WSEL_CH1_SHIFT               (4U)
1350 #define ADC_CWSELR0_WSEL_CH1_WIDTH               (3U)
1351 #define ADC_CWSELR0_WSEL_CH1(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH1_SHIFT)) & ADC_CWSELR0_WSEL_CH1_MASK)
1352 
1353 #define ADC_CWSELR0_WSEL_CH2_MASK                (0x700U)
1354 #define ADC_CWSELR0_WSEL_CH2_SHIFT               (8U)
1355 #define ADC_CWSELR0_WSEL_CH2_WIDTH               (3U)
1356 #define ADC_CWSELR0_WSEL_CH2(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH2_SHIFT)) & ADC_CWSELR0_WSEL_CH2_MASK)
1357 
1358 #define ADC_CWSELR0_WSEL_CH3_MASK                (0x7000U)
1359 #define ADC_CWSELR0_WSEL_CH3_SHIFT               (12U)
1360 #define ADC_CWSELR0_WSEL_CH3_WIDTH               (3U)
1361 #define ADC_CWSELR0_WSEL_CH3(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH3_SHIFT)) & ADC_CWSELR0_WSEL_CH3_MASK)
1362 
1363 #define ADC_CWSELR0_WSEL_CH4_MASK                (0x70000U)
1364 #define ADC_CWSELR0_WSEL_CH4_SHIFT               (16U)
1365 #define ADC_CWSELR0_WSEL_CH4_WIDTH               (3U)
1366 #define ADC_CWSELR0_WSEL_CH4(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH4_SHIFT)) & ADC_CWSELR0_WSEL_CH4_MASK)
1367 
1368 #define ADC_CWSELR0_WSEL_CH5_MASK                (0x700000U)
1369 #define ADC_CWSELR0_WSEL_CH5_SHIFT               (20U)
1370 #define ADC_CWSELR0_WSEL_CH5_WIDTH               (3U)
1371 #define ADC_CWSELR0_WSEL_CH5(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH5_SHIFT)) & ADC_CWSELR0_WSEL_CH5_MASK)
1372 
1373 #define ADC_CWSELR0_WSEL_CH6_MASK                (0x7000000U)
1374 #define ADC_CWSELR0_WSEL_CH6_SHIFT               (24U)
1375 #define ADC_CWSELR0_WSEL_CH6_WIDTH               (3U)
1376 #define ADC_CWSELR0_WSEL_CH6(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH6_SHIFT)) & ADC_CWSELR0_WSEL_CH6_MASK)
1377 
1378 #define ADC_CWSELR0_WSEL_CH7_MASK                (0x70000000U)
1379 #define ADC_CWSELR0_WSEL_CH7_SHIFT               (28U)
1380 #define ADC_CWSELR0_WSEL_CH7_WIDTH               (3U)
1381 #define ADC_CWSELR0_WSEL_CH7(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH7_SHIFT)) & ADC_CWSELR0_WSEL_CH7_MASK)
1382 /*! @} */
1383 
1384 /*! @name CWSELR4 - Channel Watchdog Select 4 */
1385 /*! @{ */
1386 
1387 #define ADC_CWSELR4_WSEL_CH32_MASK               (0x7U)
1388 #define ADC_CWSELR4_WSEL_CH32_SHIFT              (0U)
1389 #define ADC_CWSELR4_WSEL_CH32_WIDTH              (3U)
1390 #define ADC_CWSELR4_WSEL_CH32(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH32_SHIFT)) & ADC_CWSELR4_WSEL_CH32_MASK)
1391 
1392 #define ADC_CWSELR4_WSEL_CH33_MASK               (0x70U)
1393 #define ADC_CWSELR4_WSEL_CH33_SHIFT              (4U)
1394 #define ADC_CWSELR4_WSEL_CH33_WIDTH              (3U)
1395 #define ADC_CWSELR4_WSEL_CH33(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH33_SHIFT)) & ADC_CWSELR4_WSEL_CH33_MASK)
1396 
1397 #define ADC_CWSELR4_WSEL_CH34_MASK               (0x700U)
1398 #define ADC_CWSELR4_WSEL_CH34_SHIFT              (8U)
1399 #define ADC_CWSELR4_WSEL_CH34_WIDTH              (3U)
1400 #define ADC_CWSELR4_WSEL_CH34(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH34_SHIFT)) & ADC_CWSELR4_WSEL_CH34_MASK)
1401 
1402 #define ADC_CWSELR4_WSEL_CH35_MASK               (0x7000U)
1403 #define ADC_CWSELR4_WSEL_CH35_SHIFT              (12U)
1404 #define ADC_CWSELR4_WSEL_CH35_WIDTH              (3U)
1405 #define ADC_CWSELR4_WSEL_CH35(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH35_SHIFT)) & ADC_CWSELR4_WSEL_CH35_MASK)
1406 
1407 #define ADC_CWSELR4_WSEL_CH36_MASK               (0x70000U)
1408 #define ADC_CWSELR4_WSEL_CH36_SHIFT              (16U)
1409 #define ADC_CWSELR4_WSEL_CH36_WIDTH              (3U)
1410 #define ADC_CWSELR4_WSEL_CH36(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH36_SHIFT)) & ADC_CWSELR4_WSEL_CH36_MASK)
1411 
1412 #define ADC_CWSELR4_WSEL_CH37_MASK               (0x700000U)
1413 #define ADC_CWSELR4_WSEL_CH37_SHIFT              (20U)
1414 #define ADC_CWSELR4_WSEL_CH37_WIDTH              (3U)
1415 #define ADC_CWSELR4_WSEL_CH37(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH37_SHIFT)) & ADC_CWSELR4_WSEL_CH37_MASK)
1416 
1417 #define ADC_CWSELR4_WSEL_CH38_MASK               (0x7000000U)
1418 #define ADC_CWSELR4_WSEL_CH38_SHIFT              (24U)
1419 #define ADC_CWSELR4_WSEL_CH38_WIDTH              (3U)
1420 #define ADC_CWSELR4_WSEL_CH38(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH38_SHIFT)) & ADC_CWSELR4_WSEL_CH38_MASK)
1421 
1422 #define ADC_CWSELR4_WSEL_CH39_MASK               (0x70000000U)
1423 #define ADC_CWSELR4_WSEL_CH39_SHIFT              (28U)
1424 #define ADC_CWSELR4_WSEL_CH39_WIDTH              (3U)
1425 #define ADC_CWSELR4_WSEL_CH39(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH39_SHIFT)) & ADC_CWSELR4_WSEL_CH39_MASK)
1426 /*! @} */
1427 
1428 /*! @name CWENR0 - Channel Watchdog Enable 0 */
1429 /*! @{ */
1430 
1431 #define ADC_CWENR0_CWEN0_MASK                    (0x1U)
1432 #define ADC_CWENR0_CWEN0_SHIFT                   (0U)
1433 #define ADC_CWENR0_CWEN0_WIDTH                   (1U)
1434 #define ADC_CWENR0_CWEN0(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN0_SHIFT)) & ADC_CWENR0_CWEN0_MASK)
1435 
1436 #define ADC_CWENR0_CWEN1_MASK                    (0x2U)
1437 #define ADC_CWENR0_CWEN1_SHIFT                   (1U)
1438 #define ADC_CWENR0_CWEN1_WIDTH                   (1U)
1439 #define ADC_CWENR0_CWEN1(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN1_SHIFT)) & ADC_CWENR0_CWEN1_MASK)
1440 
1441 #define ADC_CWENR0_CWEN2_MASK                    (0x4U)
1442 #define ADC_CWENR0_CWEN2_SHIFT                   (2U)
1443 #define ADC_CWENR0_CWEN2_WIDTH                   (1U)
1444 #define ADC_CWENR0_CWEN2(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN2_SHIFT)) & ADC_CWENR0_CWEN2_MASK)
1445 
1446 #define ADC_CWENR0_CWEN3_MASK                    (0x8U)
1447 #define ADC_CWENR0_CWEN3_SHIFT                   (3U)
1448 #define ADC_CWENR0_CWEN3_WIDTH                   (1U)
1449 #define ADC_CWENR0_CWEN3(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN3_SHIFT)) & ADC_CWENR0_CWEN3_MASK)
1450 
1451 #define ADC_CWENR0_CWEN4_MASK                    (0x10U)
1452 #define ADC_CWENR0_CWEN4_SHIFT                   (4U)
1453 #define ADC_CWENR0_CWEN4_WIDTH                   (1U)
1454 #define ADC_CWENR0_CWEN4(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN4_SHIFT)) & ADC_CWENR0_CWEN4_MASK)
1455 
1456 #define ADC_CWENR0_CWEN5_MASK                    (0x20U)
1457 #define ADC_CWENR0_CWEN5_SHIFT                   (5U)
1458 #define ADC_CWENR0_CWEN5_WIDTH                   (1U)
1459 #define ADC_CWENR0_CWEN5(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN5_SHIFT)) & ADC_CWENR0_CWEN5_MASK)
1460 
1461 #define ADC_CWENR0_CWEN6_MASK                    (0x40U)
1462 #define ADC_CWENR0_CWEN6_SHIFT                   (6U)
1463 #define ADC_CWENR0_CWEN6_WIDTH                   (1U)
1464 #define ADC_CWENR0_CWEN6(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN6_SHIFT)) & ADC_CWENR0_CWEN6_MASK)
1465 
1466 #define ADC_CWENR0_CWEN7_MASK                    (0x80U)
1467 #define ADC_CWENR0_CWEN7_SHIFT                   (7U)
1468 #define ADC_CWENR0_CWEN7_WIDTH                   (1U)
1469 #define ADC_CWENR0_CWEN7(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN7_SHIFT)) & ADC_CWENR0_CWEN7_MASK)
1470 /*! @} */
1471 
1472 /*! @name CWENR1 - Channel Watchdog Enable 1 */
1473 /*! @{ */
1474 
1475 #define ADC_CWENR1_CWEN32_MASK                   (0x1U)
1476 #define ADC_CWENR1_CWEN32_SHIFT                  (0U)
1477 #define ADC_CWENR1_CWEN32_WIDTH                  (1U)
1478 #define ADC_CWENR1_CWEN32(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN32_SHIFT)) & ADC_CWENR1_CWEN32_MASK)
1479 
1480 #define ADC_CWENR1_CWEN33_MASK                   (0x2U)
1481 #define ADC_CWENR1_CWEN33_SHIFT                  (1U)
1482 #define ADC_CWENR1_CWEN33_WIDTH                  (1U)
1483 #define ADC_CWENR1_CWEN33(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN33_SHIFT)) & ADC_CWENR1_CWEN33_MASK)
1484 
1485 #define ADC_CWENR1_CWEN34_MASK                   (0x4U)
1486 #define ADC_CWENR1_CWEN34_SHIFT                  (2U)
1487 #define ADC_CWENR1_CWEN34_WIDTH                  (1U)
1488 #define ADC_CWENR1_CWEN34(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN34_SHIFT)) & ADC_CWENR1_CWEN34_MASK)
1489 
1490 #define ADC_CWENR1_CWEN35_MASK                   (0x8U)
1491 #define ADC_CWENR1_CWEN35_SHIFT                  (3U)
1492 #define ADC_CWENR1_CWEN35_WIDTH                  (1U)
1493 #define ADC_CWENR1_CWEN35(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN35_SHIFT)) & ADC_CWENR1_CWEN35_MASK)
1494 
1495 #define ADC_CWENR1_CWEN36_MASK                   (0x10U)
1496 #define ADC_CWENR1_CWEN36_SHIFT                  (4U)
1497 #define ADC_CWENR1_CWEN36_WIDTH                  (1U)
1498 #define ADC_CWENR1_CWEN36(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN36_SHIFT)) & ADC_CWENR1_CWEN36_MASK)
1499 
1500 #define ADC_CWENR1_CWEN37_MASK                   (0x20U)
1501 #define ADC_CWENR1_CWEN37_SHIFT                  (5U)
1502 #define ADC_CWENR1_CWEN37_WIDTH                  (1U)
1503 #define ADC_CWENR1_CWEN37(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN37_SHIFT)) & ADC_CWENR1_CWEN37_MASK)
1504 
1505 #define ADC_CWENR1_CWEN38_MASK                   (0x40U)
1506 #define ADC_CWENR1_CWEN38_SHIFT                  (6U)
1507 #define ADC_CWENR1_CWEN38_WIDTH                  (1U)
1508 #define ADC_CWENR1_CWEN38(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN38_SHIFT)) & ADC_CWENR1_CWEN38_MASK)
1509 
1510 #define ADC_CWENR1_CWEN39_MASK                   (0x80U)
1511 #define ADC_CWENR1_CWEN39_SHIFT                  (7U)
1512 #define ADC_CWENR1_CWEN39_WIDTH                  (1U)
1513 #define ADC_CWENR1_CWEN39(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN39_SHIFT)) & ADC_CWENR1_CWEN39_MASK)
1514 /*! @} */
1515 
1516 /*! @name AWORR0 - Analog Watchdog Out of Range 0 */
1517 /*! @{ */
1518 
1519 #define ADC_AWORR0_AWOR_CH0_MASK                 (0x1U)
1520 #define ADC_AWORR0_AWOR_CH0_SHIFT                (0U)
1521 #define ADC_AWORR0_AWOR_CH0_WIDTH                (1U)
1522 #define ADC_AWORR0_AWOR_CH0(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH0_SHIFT)) & ADC_AWORR0_AWOR_CH0_MASK)
1523 
1524 #define ADC_AWORR0_AWOR_CH1_MASK                 (0x2U)
1525 #define ADC_AWORR0_AWOR_CH1_SHIFT                (1U)
1526 #define ADC_AWORR0_AWOR_CH1_WIDTH                (1U)
1527 #define ADC_AWORR0_AWOR_CH1(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH1_SHIFT)) & ADC_AWORR0_AWOR_CH1_MASK)
1528 
1529 #define ADC_AWORR0_AWOR_CH2_MASK                 (0x4U)
1530 #define ADC_AWORR0_AWOR_CH2_SHIFT                (2U)
1531 #define ADC_AWORR0_AWOR_CH2_WIDTH                (1U)
1532 #define ADC_AWORR0_AWOR_CH2(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH2_SHIFT)) & ADC_AWORR0_AWOR_CH2_MASK)
1533 
1534 #define ADC_AWORR0_AWOR_CH3_MASK                 (0x8U)
1535 #define ADC_AWORR0_AWOR_CH3_SHIFT                (3U)
1536 #define ADC_AWORR0_AWOR_CH3_WIDTH                (1U)
1537 #define ADC_AWORR0_AWOR_CH3(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH3_SHIFT)) & ADC_AWORR0_AWOR_CH3_MASK)
1538 
1539 #define ADC_AWORR0_AWOR_CH4_MASK                 (0x10U)
1540 #define ADC_AWORR0_AWOR_CH4_SHIFT                (4U)
1541 #define ADC_AWORR0_AWOR_CH4_WIDTH                (1U)
1542 #define ADC_AWORR0_AWOR_CH4(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH4_SHIFT)) & ADC_AWORR0_AWOR_CH4_MASK)
1543 
1544 #define ADC_AWORR0_AWOR_CH5_MASK                 (0x20U)
1545 #define ADC_AWORR0_AWOR_CH5_SHIFT                (5U)
1546 #define ADC_AWORR0_AWOR_CH5_WIDTH                (1U)
1547 #define ADC_AWORR0_AWOR_CH5(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH5_SHIFT)) & ADC_AWORR0_AWOR_CH5_MASK)
1548 
1549 #define ADC_AWORR0_AWOR_CH6_MASK                 (0x40U)
1550 #define ADC_AWORR0_AWOR_CH6_SHIFT                (6U)
1551 #define ADC_AWORR0_AWOR_CH6_WIDTH                (1U)
1552 #define ADC_AWORR0_AWOR_CH6(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH6_SHIFT)) & ADC_AWORR0_AWOR_CH6_MASK)
1553 
1554 #define ADC_AWORR0_AWOR_CH7_MASK                 (0x80U)
1555 #define ADC_AWORR0_AWOR_CH7_SHIFT                (7U)
1556 #define ADC_AWORR0_AWOR_CH7_WIDTH                (1U)
1557 #define ADC_AWORR0_AWOR_CH7(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH7_SHIFT)) & ADC_AWORR0_AWOR_CH7_MASK)
1558 /*! @} */
1559 
1560 /*! @name AWORR1 - Analog Watchdog Out of Range 1 */
1561 /*! @{ */
1562 
1563 #define ADC_AWORR1_AWOR_CH32_MASK                (0x1U)
1564 #define ADC_AWORR1_AWOR_CH32_SHIFT               (0U)
1565 #define ADC_AWORR1_AWOR_CH32_WIDTH               (1U)
1566 #define ADC_AWORR1_AWOR_CH32(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH32_SHIFT)) & ADC_AWORR1_AWOR_CH32_MASK)
1567 
1568 #define ADC_AWORR1_AWOR_CH33_MASK                (0x2U)
1569 #define ADC_AWORR1_AWOR_CH33_SHIFT               (1U)
1570 #define ADC_AWORR1_AWOR_CH33_WIDTH               (1U)
1571 #define ADC_AWORR1_AWOR_CH33(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH33_SHIFT)) & ADC_AWORR1_AWOR_CH33_MASK)
1572 
1573 #define ADC_AWORR1_AWOR_CH34_MASK                (0x4U)
1574 #define ADC_AWORR1_AWOR_CH34_SHIFT               (2U)
1575 #define ADC_AWORR1_AWOR_CH34_WIDTH               (1U)
1576 #define ADC_AWORR1_AWOR_CH34(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH34_SHIFT)) & ADC_AWORR1_AWOR_CH34_MASK)
1577 
1578 #define ADC_AWORR1_AWOR_CH35_MASK                (0x8U)
1579 #define ADC_AWORR1_AWOR_CH35_SHIFT               (3U)
1580 #define ADC_AWORR1_AWOR_CH35_WIDTH               (1U)
1581 #define ADC_AWORR1_AWOR_CH35(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH35_SHIFT)) & ADC_AWORR1_AWOR_CH35_MASK)
1582 
1583 #define ADC_AWORR1_AWOR_CH36_MASK                (0x10U)
1584 #define ADC_AWORR1_AWOR_CH36_SHIFT               (4U)
1585 #define ADC_AWORR1_AWOR_CH36_WIDTH               (1U)
1586 #define ADC_AWORR1_AWOR_CH36(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH36_SHIFT)) & ADC_AWORR1_AWOR_CH36_MASK)
1587 
1588 #define ADC_AWORR1_AWOR_CH37_MASK                (0x20U)
1589 #define ADC_AWORR1_AWOR_CH37_SHIFT               (5U)
1590 #define ADC_AWORR1_AWOR_CH37_WIDTH               (1U)
1591 #define ADC_AWORR1_AWOR_CH37(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH37_SHIFT)) & ADC_AWORR1_AWOR_CH37_MASK)
1592 
1593 #define ADC_AWORR1_AWOR_CH38_MASK                (0x40U)
1594 #define ADC_AWORR1_AWOR_CH38_SHIFT               (6U)
1595 #define ADC_AWORR1_AWOR_CH38_WIDTH               (1U)
1596 #define ADC_AWORR1_AWOR_CH38(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH38_SHIFT)) & ADC_AWORR1_AWOR_CH38_MASK)
1597 
1598 #define ADC_AWORR1_AWOR_CH39_MASK                (0x80U)
1599 #define ADC_AWORR1_AWOR_CH39_SHIFT               (7U)
1600 #define ADC_AWORR1_AWOR_CH39_WIDTH               (1U)
1601 #define ADC_AWORR1_AWOR_CH39(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH39_SHIFT)) & ADC_AWORR1_AWOR_CH39_MASK)
1602 /*! @} */
1603 
1604 /*! @name STCR1 - Self-Test Configuration 1 */
1605 /*! @{ */
1606 
1607 #define ADC_STCR1_INPSAMP_S_MASK                 (0xFF00U)
1608 #define ADC_STCR1_INPSAMP_S_SHIFT                (8U)
1609 #define ADC_STCR1_INPSAMP_S_WIDTH                (8U)
1610 #define ADC_STCR1_INPSAMP_S(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STCR1_INPSAMP_S_SHIFT)) & ADC_STCR1_INPSAMP_S_MASK)
1611 
1612 #define ADC_STCR1_INPSAMP_C_MASK                 (0xFF000000U)
1613 #define ADC_STCR1_INPSAMP_C_SHIFT                (24U)
1614 #define ADC_STCR1_INPSAMP_C_WIDTH                (8U)
1615 #define ADC_STCR1_INPSAMP_C(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STCR1_INPSAMP_C_SHIFT)) & ADC_STCR1_INPSAMP_C_MASK)
1616 /*! @} */
1617 
1618 /*! @name STCR2 - Self-Test Configuration 2 */
1619 /*! @{ */
1620 
1621 #define ADC_STCR2_FMA_S_MASK                     (0x1U)
1622 #define ADC_STCR2_FMA_S_SHIFT                    (0U)
1623 #define ADC_STCR2_FMA_S_WIDTH                    (1U)
1624 #define ADC_STCR2_FMA_S(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_FMA_S_SHIFT)) & ADC_STCR2_FMA_S_MASK)
1625 
1626 #define ADC_STCR2_FMA_C_MASK                     (0x4U)
1627 #define ADC_STCR2_FMA_C_SHIFT                    (2U)
1628 #define ADC_STCR2_FMA_C_WIDTH                    (1U)
1629 #define ADC_STCR2_FMA_C(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_FMA_C_SHIFT)) & ADC_STCR2_FMA_C_MASK)
1630 
1631 #define ADC_STCR2_FMA_WDTERR_MASK                (0x8U)
1632 #define ADC_STCR2_FMA_WDTERR_SHIFT               (3U)
1633 #define ADC_STCR2_FMA_WDTERR_WIDTH               (1U)
1634 #define ADC_STCR2_FMA_WDTERR(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_FMA_WDTERR_SHIFT)) & ADC_STCR2_FMA_WDTERR_MASK)
1635 
1636 #define ADC_STCR2_FMA_WDSERR_MASK                (0x10U)
1637 #define ADC_STCR2_FMA_WDSERR_SHIFT               (4U)
1638 #define ADC_STCR2_FMA_WDSERR_WIDTH               (1U)
1639 #define ADC_STCR2_FMA_WDSERR(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_FMA_WDSERR_SHIFT)) & ADC_STCR2_FMA_WDSERR_MASK)
1640 
1641 #define ADC_STCR2_EN_MASK                        (0x80U)
1642 #define ADC_STCR2_EN_SHIFT                       (7U)
1643 #define ADC_STCR2_EN_WIDTH                       (1U)
1644 #define ADC_STCR2_EN(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_EN_SHIFT)) & ADC_STCR2_EN_MASK)
1645 
1646 #define ADC_STCR2_MSKERR_S0_MASK                 (0x800U)
1647 #define ADC_STCR2_MSKERR_S0_SHIFT                (11U)
1648 #define ADC_STCR2_MSKERR_S0_WIDTH                (1U)
1649 #define ADC_STCR2_MSKERR_S0(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKERR_S0_SHIFT)) & ADC_STCR2_MSKERR_S0_MASK)
1650 
1651 #define ADC_STCR2_MSKERR_S1_MASK                 (0x1000U)
1652 #define ADC_STCR2_MSKERR_S1_SHIFT                (12U)
1653 #define ADC_STCR2_MSKERR_S1_WIDTH                (1U)
1654 #define ADC_STCR2_MSKERR_S1(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKERR_S1_SHIFT)) & ADC_STCR2_MSKERR_S1_MASK)
1655 
1656 #define ADC_STCR2_MSKERR_S2_MASK                 (0x2000U)
1657 #define ADC_STCR2_MSKERR_S2_SHIFT                (13U)
1658 #define ADC_STCR2_MSKERR_S2_WIDTH                (1U)
1659 #define ADC_STCR2_MSKERR_S2(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKERR_S2_SHIFT)) & ADC_STCR2_MSKERR_S2_MASK)
1660 
1661 #define ADC_STCR2_MSKERR_C_MASK                  (0x8000U)
1662 #define ADC_STCR2_MSKERR_C_SHIFT                 (15U)
1663 #define ADC_STCR2_MSKERR_C_WIDTH                 (1U)
1664 #define ADC_STCR2_MSKERR_C(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKERR_C_SHIFT)) & ADC_STCR2_MSKERR_C_MASK)
1665 
1666 #define ADC_STCR2_MSKWDG_EOA_S_MASK              (0x10000U)
1667 #define ADC_STCR2_MSKWDG_EOA_S_SHIFT             (16U)
1668 #define ADC_STCR2_MSKWDG_EOA_S_WIDTH             (1U)
1669 #define ADC_STCR2_MSKWDG_EOA_S(x)                (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKWDG_EOA_S_SHIFT)) & ADC_STCR2_MSKWDG_EOA_S_MASK)
1670 
1671 #define ADC_STCR2_MSKWDG_EOA_C_MASK              (0x40000U)
1672 #define ADC_STCR2_MSKWDG_EOA_C_SHIFT             (18U)
1673 #define ADC_STCR2_MSKWDG_EOA_C_WIDTH             (1U)
1674 #define ADC_STCR2_MSKWDG_EOA_C(x)                (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKWDG_EOA_C_SHIFT)) & ADC_STCR2_MSKWDG_EOA_C_MASK)
1675 
1676 #define ADC_STCR2_MSKST_EOC_MASK                 (0x800000U)
1677 #define ADC_STCR2_MSKST_EOC_SHIFT                (23U)
1678 #define ADC_STCR2_MSKST_EOC_WIDTH                (1U)
1679 #define ADC_STCR2_MSKST_EOC(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKST_EOC_SHIFT)) & ADC_STCR2_MSKST_EOC_MASK)
1680 
1681 #define ADC_STCR2_MSKWDTERR_MASK                 (0x2000000U)
1682 #define ADC_STCR2_MSKWDTERR_SHIFT                (25U)
1683 #define ADC_STCR2_MSKWDTERR_WIDTH                (1U)
1684 #define ADC_STCR2_MSKWDTERR(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKWDTERR_SHIFT)) & ADC_STCR2_MSKWDTERR_MASK)
1685 
1686 #define ADC_STCR2_SERR_MASK                      (0x4000000U)
1687 #define ADC_STCR2_SERR_SHIFT                     (26U)
1688 #define ADC_STCR2_SERR_WIDTH                     (1U)
1689 #define ADC_STCR2_SERR(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_SERR_SHIFT)) & ADC_STCR2_SERR_MASK)
1690 
1691 #define ADC_STCR2_MSKWDSERR_MASK                 (0x8000000U)
1692 #define ADC_STCR2_MSKWDSERR_SHIFT                (27U)
1693 #define ADC_STCR2_MSKWDSERR_WIDTH                (1U)
1694 #define ADC_STCR2_MSKWDSERR(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKWDSERR_SHIFT)) & ADC_STCR2_MSKWDSERR_MASK)
1695 /*! @} */
1696 
1697 /*! @name STCR3 - Self-Test Configuration 3 */
1698 /*! @{ */
1699 
1700 #define ADC_STCR3_MSTEP_MASK                     (0x1FU)
1701 #define ADC_STCR3_MSTEP_SHIFT                    (0U)
1702 #define ADC_STCR3_MSTEP_WIDTH                    (5U)
1703 #define ADC_STCR3_MSTEP(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STCR3_MSTEP_SHIFT)) & ADC_STCR3_MSTEP_MASK)
1704 
1705 #define ADC_STCR3_ALG_MASK                       (0x300U)
1706 #define ADC_STCR3_ALG_SHIFT                      (8U)
1707 #define ADC_STCR3_ALG_WIDTH                      (2U)
1708 #define ADC_STCR3_ALG(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STCR3_ALG_SHIFT)) & ADC_STCR3_ALG_MASK)
1709 /*! @} */
1710 
1711 /*! @name STBRR - Self-Test Baud Rate */
1712 /*! @{ */
1713 
1714 #define ADC_STBRR_BR_MASK                        (0xFFU)
1715 #define ADC_STBRR_BR_SHIFT                       (0U)
1716 #define ADC_STBRR_BR_WIDTH                       (8U)
1717 #define ADC_STBRR_BR(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_STBRR_BR_SHIFT)) & ADC_STBRR_BR_MASK)
1718 
1719 #define ADC_STBRR_WDT_MASK                       (0x70000U)
1720 #define ADC_STBRR_WDT_SHIFT                      (16U)
1721 #define ADC_STBRR_WDT_WIDTH                      (3U)
1722 #define ADC_STBRR_WDT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STBRR_WDT_SHIFT)) & ADC_STBRR_WDT_MASK)
1723 /*! @} */
1724 
1725 /*! @name STSR1 - Self-Test Status 1 */
1726 /*! @{ */
1727 
1728 #define ADC_STSR1_STEP_C_MASK                    (0x3E0U)
1729 #define ADC_STSR1_STEP_C_SHIFT                   (5U)
1730 #define ADC_STSR1_STEP_C_WIDTH                   (5U)
1731 #define ADC_STSR1_STEP_C(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_STEP_C_SHIFT)) & ADC_STSR1_STEP_C_MASK)
1732 
1733 #define ADC_STSR1_ERR_S0_MASK                    (0x800U)
1734 #define ADC_STSR1_ERR_S0_SHIFT                   (11U)
1735 #define ADC_STSR1_ERR_S0_WIDTH                   (1U)
1736 #define ADC_STSR1_ERR_S0(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_ERR_S0_SHIFT)) & ADC_STSR1_ERR_S0_MASK)
1737 
1738 #define ADC_STSR1_ERR_S1_MASK                    (0x1000U)
1739 #define ADC_STSR1_ERR_S1_SHIFT                   (12U)
1740 #define ADC_STSR1_ERR_S1_WIDTH                   (1U)
1741 #define ADC_STSR1_ERR_S1(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_ERR_S1_SHIFT)) & ADC_STSR1_ERR_S1_MASK)
1742 
1743 #define ADC_STSR1_ERR_S2_MASK                    (0x2000U)
1744 #define ADC_STSR1_ERR_S2_SHIFT                   (13U)
1745 #define ADC_STSR1_ERR_S2_WIDTH                   (1U)
1746 #define ADC_STSR1_ERR_S2(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_ERR_S2_SHIFT)) & ADC_STSR1_ERR_S2_MASK)
1747 
1748 #define ADC_STSR1_ERR_C_MASK                     (0x8000U)
1749 #define ADC_STSR1_ERR_C_SHIFT                    (15U)
1750 #define ADC_STSR1_ERR_C_WIDTH                    (1U)
1751 #define ADC_STSR1_ERR_C(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_ERR_C_SHIFT)) & ADC_STSR1_ERR_C_MASK)
1752 
1753 #define ADC_STSR1_WDG_EOA_S_MASK                 (0x10000U)
1754 #define ADC_STSR1_WDG_EOA_S_SHIFT                (16U)
1755 #define ADC_STSR1_WDG_EOA_S_WIDTH                (1U)
1756 #define ADC_STSR1_WDG_EOA_S(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_WDG_EOA_S_SHIFT)) & ADC_STSR1_WDG_EOA_S_MASK)
1757 
1758 #define ADC_STSR1_WDG_EOA_C_MASK                 (0x40000U)
1759 #define ADC_STSR1_WDG_EOA_C_SHIFT                (18U)
1760 #define ADC_STSR1_WDG_EOA_C_WIDTH                (1U)
1761 #define ADC_STSR1_WDG_EOA_C(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_WDG_EOA_C_SHIFT)) & ADC_STSR1_WDG_EOA_C_MASK)
1762 
1763 #define ADC_STSR1_ST_EOC_MASK                    (0x800000U)
1764 #define ADC_STSR1_ST_EOC_SHIFT                   (23U)
1765 #define ADC_STSR1_ST_EOC_WIDTH                   (1U)
1766 #define ADC_STSR1_ST_EOC(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_ST_EOC_SHIFT)) & ADC_STSR1_ST_EOC_MASK)
1767 
1768 #define ADC_STSR1_OVERWR_MASK                    (0x1000000U)
1769 #define ADC_STSR1_OVERWR_SHIFT                   (24U)
1770 #define ADC_STSR1_OVERWR_WIDTH                   (1U)
1771 #define ADC_STSR1_OVERWR(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_OVERWR_SHIFT)) & ADC_STSR1_OVERWR_MASK)
1772 
1773 #define ADC_STSR1_WDTERR_MASK                    (0x2000000U)
1774 #define ADC_STSR1_WDTERR_SHIFT                   (25U)
1775 #define ADC_STSR1_WDTERR_WIDTH                   (1U)
1776 #define ADC_STSR1_WDTERR(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_WDTERR_SHIFT)) & ADC_STSR1_WDTERR_MASK)
1777 
1778 #define ADC_STSR1_WDSERR_MASK                    (0x8000000U)
1779 #define ADC_STSR1_WDSERR_SHIFT                   (27U)
1780 #define ADC_STSR1_WDSERR_WIDTH                   (1U)
1781 #define ADC_STSR1_WDSERR(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_WDSERR_SHIFT)) & ADC_STSR1_WDSERR_MASK)
1782 /*! @} */
1783 
1784 /*! @name STSR2 - Self-Test Status 2 */
1785 /*! @{ */
1786 
1787 #define ADC_STSR2_DATA0_MASK                     (0xFFFU)
1788 #define ADC_STSR2_DATA0_SHIFT                    (0U)
1789 #define ADC_STSR2_DATA0_WIDTH                    (12U)
1790 #define ADC_STSR2_DATA0(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STSR2_DATA0_SHIFT)) & ADC_STSR2_DATA0_MASK)
1791 
1792 #define ADC_STSR2_DATA1_MASK                     (0xFFF0000U)
1793 #define ADC_STSR2_DATA1_SHIFT                    (16U)
1794 #define ADC_STSR2_DATA1_WIDTH                    (12U)
1795 #define ADC_STSR2_DATA1(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STSR2_DATA1_SHIFT)) & ADC_STSR2_DATA1_MASK)
1796 
1797 #define ADC_STSR2_OVFL_MASK                      (0x80000000U)
1798 #define ADC_STSR2_OVFL_SHIFT                     (31U)
1799 #define ADC_STSR2_OVFL_WIDTH                     (1U)
1800 #define ADC_STSR2_OVFL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_STSR2_OVFL_SHIFT)) & ADC_STSR2_OVFL_MASK)
1801 /*! @} */
1802 
1803 /*! @name STSR3 - Self-Test Status 3 */
1804 /*! @{ */
1805 
1806 #define ADC_STSR3_DATA0_MASK                     (0xFFFU)
1807 #define ADC_STSR3_DATA0_SHIFT                    (0U)
1808 #define ADC_STSR3_DATA0_WIDTH                    (12U)
1809 #define ADC_STSR3_DATA0(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STSR3_DATA0_SHIFT)) & ADC_STSR3_DATA0_MASK)
1810 
1811 #define ADC_STSR3_DATA1_MASK                     (0xFFF0000U)
1812 #define ADC_STSR3_DATA1_SHIFT                    (16U)
1813 #define ADC_STSR3_DATA1_WIDTH                    (12U)
1814 #define ADC_STSR3_DATA1(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STSR3_DATA1_SHIFT)) & ADC_STSR3_DATA1_MASK)
1815 /*! @} */
1816 
1817 /*! @name STSR4 - Self-Test Status 4 */
1818 /*! @{ */
1819 
1820 #define ADC_STSR4_DATA1_MASK                     (0xFFF0000U)
1821 #define ADC_STSR4_DATA1_SHIFT                    (16U)
1822 #define ADC_STSR4_DATA1_WIDTH                    (12U)
1823 #define ADC_STSR4_DATA1(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STSR4_DATA1_SHIFT)) & ADC_STSR4_DATA1_MASK)
1824 /*! @} */
1825 
1826 /*! @name STDR1 - Self-Test Data 1 */
1827 /*! @{ */
1828 
1829 #define ADC_STDR1_TCDATA_MASK                    (0xFFFU)
1830 #define ADC_STDR1_TCDATA_SHIFT                   (0U)
1831 #define ADC_STDR1_TCDATA_WIDTH                   (12U)
1832 #define ADC_STDR1_TCDATA(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_STDR1_TCDATA_SHIFT)) & ADC_STDR1_TCDATA_MASK)
1833 
1834 #define ADC_STDR1_OWERWR_MASK                    (0x40000U)
1835 #define ADC_STDR1_OWERWR_SHIFT                   (18U)
1836 #define ADC_STDR1_OWERWR_WIDTH                   (1U)
1837 #define ADC_STDR1_OWERWR(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_STDR1_OWERWR_SHIFT)) & ADC_STDR1_OWERWR_MASK)
1838 
1839 #define ADC_STDR1_VALID_MASK                     (0x80000U)
1840 #define ADC_STDR1_VALID_SHIFT                    (19U)
1841 #define ADC_STDR1_VALID_WIDTH                    (1U)
1842 #define ADC_STDR1_VALID(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STDR1_VALID_SHIFT)) & ADC_STDR1_VALID_MASK)
1843 /*! @} */
1844 
1845 /*! @name STDR2 - Self-Test Data 2 */
1846 /*! @{ */
1847 
1848 #define ADC_STDR2_IDATA_MASK                     (0xFFFU)
1849 #define ADC_STDR2_IDATA_SHIFT                    (0U)
1850 #define ADC_STDR2_IDATA_WIDTH                    (12U)
1851 #define ADC_STDR2_IDATA(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STDR2_IDATA_SHIFT)) & ADC_STDR2_IDATA_MASK)
1852 
1853 #define ADC_STDR2_OVERWR_MASK                    (0x40000U)
1854 #define ADC_STDR2_OVERWR_SHIFT                   (18U)
1855 #define ADC_STDR2_OVERWR_WIDTH                   (1U)
1856 #define ADC_STDR2_OVERWR(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_STDR2_OVERWR_SHIFT)) & ADC_STDR2_OVERWR_MASK)
1857 
1858 #define ADC_STDR2_VALID_MASK                     (0x80000U)
1859 #define ADC_STDR2_VALID_SHIFT                    (19U)
1860 #define ADC_STDR2_VALID_WIDTH                    (1U)
1861 #define ADC_STDR2_VALID(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STDR2_VALID_SHIFT)) & ADC_STDR2_VALID_MASK)
1862 
1863 #define ADC_STDR2_FDATA_MASK                     (0xFFF00000U)
1864 #define ADC_STDR2_FDATA_SHIFT                    (20U)
1865 #define ADC_STDR2_FDATA_WIDTH                    (12U)
1866 #define ADC_STDR2_FDATA(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STDR2_FDATA_SHIFT)) & ADC_STDR2_FDATA_MASK)
1867 /*! @} */
1868 
1869 /*! @name STAW0R - Self-Test Analog Watchdog 0 */
1870 /*! @{ */
1871 
1872 #define ADC_STAW0R_THRL_MASK                     (0xFFFU)
1873 #define ADC_STAW0R_THRL_SHIFT                    (0U)
1874 #define ADC_STAW0R_THRL_WIDTH                    (12U)
1875 #define ADC_STAW0R_THRL(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAW0R_THRL_SHIFT)) & ADC_STAW0R_THRL_MASK)
1876 
1877 #define ADC_STAW0R_THRH_MASK                     (0xFFF0000U)
1878 #define ADC_STAW0R_THRH_SHIFT                    (16U)
1879 #define ADC_STAW0R_THRH_WIDTH                    (12U)
1880 #define ADC_STAW0R_THRH(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAW0R_THRH_SHIFT)) & ADC_STAW0R_THRH_MASK)
1881 
1882 #define ADC_STAW0R_WDTE_MASK                     (0x40000000U)
1883 #define ADC_STAW0R_WDTE_SHIFT                    (30U)
1884 #define ADC_STAW0R_WDTE_WIDTH                    (1U)
1885 #define ADC_STAW0R_WDTE(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAW0R_WDTE_SHIFT)) & ADC_STAW0R_WDTE_MASK)
1886 
1887 #define ADC_STAW0R_AWDE_MASK                     (0x80000000U)
1888 #define ADC_STAW0R_AWDE_SHIFT                    (31U)
1889 #define ADC_STAW0R_AWDE_WIDTH                    (1U)
1890 #define ADC_STAW0R_AWDE(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAW0R_AWDE_SHIFT)) & ADC_STAW0R_AWDE_MASK)
1891 /*! @} */
1892 
1893 /*! @name STAW1AR - Self-Test Analog Watchdog 1A */
1894 /*! @{ */
1895 
1896 #define ADC_STAW1AR_THRL_MASK                    (0xFFFU)
1897 #define ADC_STAW1AR_THRL_SHIFT                   (0U)
1898 #define ADC_STAW1AR_THRL_WIDTH                   (12U)
1899 #define ADC_STAW1AR_THRL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_STAW1AR_THRL_SHIFT)) & ADC_STAW1AR_THRL_MASK)
1900 
1901 #define ADC_STAW1AR_THRH_MASK                    (0xFFF0000U)
1902 #define ADC_STAW1AR_THRH_SHIFT                   (16U)
1903 #define ADC_STAW1AR_THRH_WIDTH                   (12U)
1904 #define ADC_STAW1AR_THRH(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_STAW1AR_THRH_SHIFT)) & ADC_STAW1AR_THRH_MASK)
1905 
1906 #define ADC_STAW1AR_AWDE_MASK                    (0x80000000U)
1907 #define ADC_STAW1AR_AWDE_SHIFT                   (31U)
1908 #define ADC_STAW1AR_AWDE_WIDTH                   (1U)
1909 #define ADC_STAW1AR_AWDE(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_STAW1AR_AWDE_SHIFT)) & ADC_STAW1AR_AWDE_MASK)
1910 /*! @} */
1911 
1912 /*! @name STAW1BR - Self-Test Analog Watchdog 1B */
1913 /*! @{ */
1914 
1915 #define ADC_STAW1BR_THRL_MASK                    (0xFFFU)
1916 #define ADC_STAW1BR_THRL_SHIFT                   (0U)
1917 #define ADC_STAW1BR_THRL_WIDTH                   (12U)
1918 #define ADC_STAW1BR_THRL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_STAW1BR_THRL_SHIFT)) & ADC_STAW1BR_THRL_MASK)
1919 
1920 #define ADC_STAW1BR_THRH_MASK                    (0xFFF0000U)
1921 #define ADC_STAW1BR_THRH_SHIFT                   (16U)
1922 #define ADC_STAW1BR_THRH_WIDTH                   (12U)
1923 #define ADC_STAW1BR_THRH(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_STAW1BR_THRH_SHIFT)) & ADC_STAW1BR_THRH_MASK)
1924 /*! @} */
1925 
1926 /*! @name STAW2R - Self-Test Analog Watchdog 2 */
1927 /*! @{ */
1928 
1929 #define ADC_STAW2R_THRL_MASK                     (0xFFFU)
1930 #define ADC_STAW2R_THRL_SHIFT                    (0U)
1931 #define ADC_STAW2R_THRL_WIDTH                    (12U)
1932 #define ADC_STAW2R_THRL(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAW2R_THRL_SHIFT)) & ADC_STAW2R_THRL_MASK)
1933 
1934 #define ADC_STAW2R_AWDE_MASK                     (0x80000000U)
1935 #define ADC_STAW2R_AWDE_SHIFT                    (31U)
1936 #define ADC_STAW2R_AWDE_WIDTH                    (1U)
1937 #define ADC_STAW2R_AWDE(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAW2R_AWDE_SHIFT)) & ADC_STAW2R_AWDE_MASK)
1938 /*! @} */
1939 
1940 /*! @name STAW4R - Self-Test Analog Watchdog 4 */
1941 /*! @{ */
1942 
1943 #define ADC_STAW4R_THRL_MASK                     (0xFFFU)
1944 #define ADC_STAW4R_THRL_SHIFT                    (0U)
1945 #define ADC_STAW4R_THRL_WIDTH                    (12U)
1946 #define ADC_STAW4R_THRL(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAW4R_THRL_SHIFT)) & ADC_STAW4R_THRL_MASK)
1947 
1948 #define ADC_STAW4R_THRH_MASK                     (0xFFF0000U)
1949 #define ADC_STAW4R_THRH_SHIFT                    (16U)
1950 #define ADC_STAW4R_THRH_WIDTH                    (12U)
1951 #define ADC_STAW4R_THRH(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAW4R_THRH_SHIFT)) & ADC_STAW4R_THRH_MASK)
1952 
1953 #define ADC_STAW4R_WDTE_MASK                     (0x40000000U)
1954 #define ADC_STAW4R_WDTE_SHIFT                    (30U)
1955 #define ADC_STAW4R_WDTE_WIDTH                    (1U)
1956 #define ADC_STAW4R_WDTE(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAW4R_WDTE_SHIFT)) & ADC_STAW4R_WDTE_MASK)
1957 
1958 #define ADC_STAW4R_AWDE_MASK                     (0x80000000U)
1959 #define ADC_STAW4R_AWDE_SHIFT                    (31U)
1960 #define ADC_STAW4R_AWDE_WIDTH                    (1U)
1961 #define ADC_STAW4R_AWDE(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAW4R_AWDE_SHIFT)) & ADC_STAW4R_AWDE_MASK)
1962 /*! @} */
1963 
1964 /*! @name STAW5R - Self-Test Analog Watchdog 5 */
1965 /*! @{ */
1966 
1967 #define ADC_STAW5R_THRL_MASK                     (0xFFFU)
1968 #define ADC_STAW5R_THRL_SHIFT                    (0U)
1969 #define ADC_STAW5R_THRL_WIDTH                    (12U)
1970 #define ADC_STAW5R_THRL(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAW5R_THRL_SHIFT)) & ADC_STAW5R_THRL_MASK)
1971 
1972 #define ADC_STAW5R_THRH_MASK                     (0xFFF0000U)
1973 #define ADC_STAW5R_THRH_SHIFT                    (16U)
1974 #define ADC_STAW5R_THRH_WIDTH                    (12U)
1975 #define ADC_STAW5R_THRH(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAW5R_THRH_SHIFT)) & ADC_STAW5R_THRH_MASK)
1976 /*! @} */
1977 
1978 /*! @name CALSTAT - Calibration Status */
1979 /*! @{ */
1980 
1981 #define ADC_CALSTAT_STAT_1_MASK                  (0x1U)
1982 #define ADC_CALSTAT_STAT_1_SHIFT                 (0U)
1983 #define ADC_CALSTAT_STAT_1_WIDTH                 (1U)
1984 #define ADC_CALSTAT_STAT_1(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_1_SHIFT)) & ADC_CALSTAT_STAT_1_MASK)
1985 
1986 #define ADC_CALSTAT_STAT_2_MASK                  (0x2U)
1987 #define ADC_CALSTAT_STAT_2_SHIFT                 (1U)
1988 #define ADC_CALSTAT_STAT_2_WIDTH                 (1U)
1989 #define ADC_CALSTAT_STAT_2(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_2_SHIFT)) & ADC_CALSTAT_STAT_2_MASK)
1990 
1991 #define ADC_CALSTAT_STAT_3_MASK                  (0x4U)
1992 #define ADC_CALSTAT_STAT_3_SHIFT                 (2U)
1993 #define ADC_CALSTAT_STAT_3_WIDTH                 (1U)
1994 #define ADC_CALSTAT_STAT_3(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_3_SHIFT)) & ADC_CALSTAT_STAT_3_MASK)
1995 
1996 #define ADC_CALSTAT_STAT_4_MASK                  (0x8U)
1997 #define ADC_CALSTAT_STAT_4_SHIFT                 (3U)
1998 #define ADC_CALSTAT_STAT_4_WIDTH                 (1U)
1999 #define ADC_CALSTAT_STAT_4(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_4_SHIFT)) & ADC_CALSTAT_STAT_4_MASK)
2000 
2001 #define ADC_CALSTAT_STAT_5_MASK                  (0x10U)
2002 #define ADC_CALSTAT_STAT_5_SHIFT                 (4U)
2003 #define ADC_CALSTAT_STAT_5_WIDTH                 (1U)
2004 #define ADC_CALSTAT_STAT_5(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_5_SHIFT)) & ADC_CALSTAT_STAT_5_MASK)
2005 
2006 #define ADC_CALSTAT_STAT_6_MASK                  (0x20U)
2007 #define ADC_CALSTAT_STAT_6_SHIFT                 (5U)
2008 #define ADC_CALSTAT_STAT_6_WIDTH                 (1U)
2009 #define ADC_CALSTAT_STAT_6(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_6_SHIFT)) & ADC_CALSTAT_STAT_6_MASK)
2010 
2011 #define ADC_CALSTAT_STAT_7_MASK                  (0x40U)
2012 #define ADC_CALSTAT_STAT_7_SHIFT                 (6U)
2013 #define ADC_CALSTAT_STAT_7_WIDTH                 (1U)
2014 #define ADC_CALSTAT_STAT_7(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_7_SHIFT)) & ADC_CALSTAT_STAT_7_MASK)
2015 
2016 #define ADC_CALSTAT_STAT_8_MASK                  (0x80U)
2017 #define ADC_CALSTAT_STAT_8_SHIFT                 (7U)
2018 #define ADC_CALSTAT_STAT_8_WIDTH                 (1U)
2019 #define ADC_CALSTAT_STAT_8(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_8_SHIFT)) & ADC_CALSTAT_STAT_8_MASK)
2020 
2021 #define ADC_CALSTAT_STAT_9_MASK                  (0x100U)
2022 #define ADC_CALSTAT_STAT_9_SHIFT                 (8U)
2023 #define ADC_CALSTAT_STAT_9_WIDTH                 (1U)
2024 #define ADC_CALSTAT_STAT_9(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_9_SHIFT)) & ADC_CALSTAT_STAT_9_MASK)
2025 
2026 #define ADC_CALSTAT_STAT_10_MASK                 (0x200U)
2027 #define ADC_CALSTAT_STAT_10_SHIFT                (9U)
2028 #define ADC_CALSTAT_STAT_10_WIDTH                (1U)
2029 #define ADC_CALSTAT_STAT_10(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_10_SHIFT)) & ADC_CALSTAT_STAT_10_MASK)
2030 
2031 #define ADC_CALSTAT_STAT_11_MASK                 (0x400U)
2032 #define ADC_CALSTAT_STAT_11_SHIFT                (10U)
2033 #define ADC_CALSTAT_STAT_11_WIDTH                (1U)
2034 #define ADC_CALSTAT_STAT_11(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_11_SHIFT)) & ADC_CALSTAT_STAT_11_MASK)
2035 
2036 #define ADC_CALSTAT_STAT_12_MASK                 (0x800U)
2037 #define ADC_CALSTAT_STAT_12_SHIFT                (11U)
2038 #define ADC_CALSTAT_STAT_12_WIDTH                (1U)
2039 #define ADC_CALSTAT_STAT_12(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_12_SHIFT)) & ADC_CALSTAT_STAT_12_MASK)
2040 
2041 #define ADC_CALSTAT_TEST_RESULT_MASK             (0xFFFF0000U)
2042 #define ADC_CALSTAT_TEST_RESULT_SHIFT            (16U)
2043 #define ADC_CALSTAT_TEST_RESULT_WIDTH            (16U)
2044 #define ADC_CALSTAT_TEST_RESULT(x)               (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_TEST_RESULT_SHIFT)) & ADC_CALSTAT_TEST_RESULT_MASK)
2045 /*! @} */
2046 
2047 /*!
2048  * @}
2049  */ /* end of group ADC_Register_Masks */
2050 
2051 /*!
2052  * @}
2053  */ /* end of group ADC_Peripheral_Access_Layer */
2054 
2055 #endif  /* #if !defined(S32Z2_ADC_H_) */
2056