1 /** 2 ****************************************************************************** 3 * @file stm32g4xx_hal_adc.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32G4xx_HAL_ADC_H 21 #define STM32G4xx_HAL_ADC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32g4xx_hal_def.h" 29 30 /* Include low level driver */ 31 #include "stm32g4xx_ll_adc.h" 32 33 /** @addtogroup STM32G4xx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup ADC 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup ADC_Exported_Types ADC Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief ADC group regular oversampling structure definition 48 */ 49 typedef struct 50 { 51 uint32_t Ratio; /*!< Configures the oversampling ratio. 52 This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ 53 54 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 55 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 56 57 uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. 58 This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */ 59 60 uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode. 61 The oversampling is either temporary stopped or reset upon an injected 62 sequence interruption. 63 If oversampling is enabled on both regular and injected groups, this 64 parameter is discarded and forced to setting 65 "ADC_REGOVERSAMPLING_RESUMED_MODE" (the oversampling buffer is zeroed 66 during injection sequence). 67 This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */ 68 69 } ADC_OversamplingTypeDef; 70 71 /** 72 * @brief Structure definition of ADC instance and ADC group regular. 73 * @note Parameters of this structure are shared within 2 scopes: 74 * - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign, 75 * GainCompensation, ScanConvMode, EOCSelection, LowPowerAutoWait. 76 * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, 77 * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling, 78 * SamplingMode. 79 * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. 80 * ADC state can be either: 81 * - For all parameters: ADC disabled 82 * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled 83 * without conversion on going on group regular. 84 * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going 85 * on groups regular and injected. 86 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 87 * without error reporting (as it can be the expected behavior in case of intended action to update another 88 * parameter (which fulfills the ADC state condition) on the fly). 89 */ 90 typedef struct 91 { 92 uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous 93 clock derived from system clock or PLL (Refer to reference manual for list of 94 clocks available)) and clock prescaler. 95 This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. 96 Note: The ADC clock configuration is common to all ADC instances. 97 Note: In case of usage of channels on injected group, ADC frequency should be 98 lower than AHB clock frequency /4 for resolution 12 or 10 bits, 99 AHB clock frequency /3 for resolution 8 bits, 100 AHB clock frequency /2 for resolution 6 bits. 101 Note: In case of synchronous clock mode based on HCLK/1, the configuration must 102 be enabled only if the system clock has a 50% duty clock cycle (APB 103 prescaler configured inside RCC must be bypassed and PCLK clock must have 104 50% duty cycle). Refer to reference manual for details. 105 Note: In case of usage of asynchronous clock, the selected clock must be 106 preliminarily enabled at RCC top level. 107 Note: This parameter can be modified only if all ADC instances are disabled. */ 108 109 uint32_t Resolution; /*!< Configure the ADC resolution. 110 This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ 111 112 uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). 113 Refer to reference manual for alignments formats versus resolutions. 114 This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */ 115 116 uint32_t GainCompensation; /*!< Specify the ADC gain compensation coefficient to be applied to ADC raw conversion 117 data, based on following formula: 118 DATA = DATA(raw) * (gain compensation coef) / 4096 119 "2.12" bit format, unsigned: 2 bits exponents / 12 bits mantissa 120 Gain step is 1/4096 = 0.000244 121 Gain range is 0.0000 to 3.999756 122 This parameter value can be 123 0 Gain compensation will be disabled and coefficient set to 0 124 1 -> 0x3FFF Gain compensation will be enabled and coefficient set to specified 125 value 126 Note: Gain compensation when enabled is applied to all channels. */ 127 128 uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected. 129 This parameter can be associated to parameter 'DiscontinuousConvMode' to have 130 main sequence subdivided in successive parts. 131 If disabled: Conversion is performed in single mode (one channel converted, the 132 one defined in rank 1). Parameters 'NbrOfConversion' and 133 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). 134 If enabled: Conversions are performed in sequence mode (multiple ranks defined 135 by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each 136 channel in sequencer). Scan direction is upward: from rank 1 to 137 rank 'n'. 138 This parameter can be a value of @ref ADC_Scan_mode */ 139 140 uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and 141 interruption: end of unitary conversion or end of sequence conversions. 142 This parameter can be a value of @ref ADC_EOCSelection. */ 143 144 FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the 145 previous conversion (for ADC group regular) or previous sequence (for ADC group 146 injected) has been retrieved by user software, using function HAL_ADC_GetValue() 147 or HAL_ADCEx_InjectedGetValue(). 148 This feature automatically adapts the frequency of ADC conversions triggers to 149 the speed of the system that reads the data. Moreover, this avoids risk of 150 overrun for low frequency applications. 151 This parameter can be set to ENABLE or DISABLE. 152 Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), 153 HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC 154 flag (by CPU to free the IRQ pending event or by DMA). 155 Auto wait will work but fort a very short time, discarding its intended 156 benefit (except specific case of high load of CPU or DMA transfers which 157 can justify usage of auto wait). 158 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, 159 when ADC conversion data is needed: 160 use HAL_ADC_PollForConversion() to ensure that conversion is completed and 161 HAL_ADC_GetValue() to retrieve conversion result and trig another 162 conversion start. (in case of usage of ADC group injected, use the 163 equivalent functions HAL_ADCExInjected_Start(), 164 HAL_ADCEx_InjectedGetValue(), ...). */ 165 166 FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) 167 or continuous mode for ADC group regular, after the first ADC conversion 168 start trigger occurred (software start or external trigger). This parameter 169 can be set to ENABLE or DISABLE. */ 170 171 uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group 172 sequencer. 173 This parameter is dependent on ScanConvMode: 174 - sequencer configured to fully configurable: 175 Number of ranks in the scan sequence is configurable using this parameter. 176 Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to 177 parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'. 178 Afterwards, when all needed sequencer ranks are set, parameter 179 'NbrOfConversion' can be updated without modifying configuration of 180 sequencer ranks (sequencer ranks above 'NbrOfConversion' are discarded). 181 - sequencer configured to not fully configurable: 182 Number of ranks in the scan sequence is defined by number of channels set in 183 the sequence. This parameter is discarded. 184 This parameter must be a number between Min_Data = 1 and Max_Data = 8. 185 Note: This parameter must be modified when no conversion is on going on regular 186 group (ADC disabled, or ADC enabled without continuous mode or external 187 trigger that could launch a conversion). */ 188 189 FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed 190 in Complete-sequence/Discontinuous-sequence (main sequence subdivided in 191 successive parts). 192 Discontinuous mode is used only if sequencer is enabled (parameter 193 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 194 Discontinuous mode can be enabled only if continuous mode is disabled. 195 If continuous mode is enabled, this parameter setting is discarded. 196 This parameter can be set to ENABLE or DISABLE. 197 Note: On this STM32 series, ADC group regular number of discontinuous 198 ranks increment is fixed to one-by-one. */ 199 200 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence 201 of ADC group regular (parameter NbrOfConversion) will be subdivided. 202 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. 203 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ 204 205 uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion 206 start. 207 If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger 208 is used instead. 209 This parameter can be a value of @ref ADC_regular_external_trigger_source. 210 Caution: external trigger source is common to all ADC instances. */ 211 212 uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start 213 If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. 214 This parameter can be a value of @ref ADC_regular_external_trigger_edge */ 215 216 uint32_t SamplingMode; /*!< Select the sampling mode to be used for ADC group regular conversion. 217 This parameter can be a value of @ref ADC_regular_sampling_mode */ 218 219 FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA 220 transfer stops when number of conversions is reached) or in continuous 221 mode (DMA transfer unlimited, whatever number of conversions). 222 This parameter can be set to ENABLE or DISABLE. 223 Note: In continuous mode, DMA must be configured in circular mode. 224 Otherwise an overrun will be triggered when DMA buffer maximum 225 pointer is reached. */ 226 227 uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). 228 This parameter applies to ADC group regular only. 229 This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. 230 Note: In case of overrun set to data preserved and usage with programming model 231 with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of 232 conversion flags, this induces the release of the preserved data. If 233 needed, this data can be saved in function HAL_ADC_ConvCpltCallback(), 234 placed in user program code (called before end of conversion flags clear) 235 Note: Error reporting with respect to the conversion mode: 236 - Usage with ADC conversion by polling for event or interruption: Error is 237 reported only if overrun is set to data preserved. If overrun is set to 238 data overwritten, user can willingly not read all the converted data, 239 this is not considered as an erroneous case. 240 - Usage with ADC conversion by DMA: Error is reported whatever overrun 241 setting (DMA is expected to process all data from data register). */ 242 243 FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. 244 This parameter can be set to ENABLE or DISABLE. 245 Note: This parameter can be modified only if there is no conversion is 246 ongoing on ADC groups regular and injected */ 247 248 ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. 249 Caution: this setting overwrites the previous oversampling configuration 250 if oversampling is already enabled. */ 251 252 } ADC_InitTypeDef; 253 254 /** 255 * @brief Structure definition of ADC channel for regular group 256 * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. 257 * ADC state can be either: 258 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff') 259 * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion 260 * on going on regular group. 261 * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on 262 * regular and injected groups. 263 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 264 * without error reporting (as it can be the expected behavior in case of intended action to update another 265 * parameter (which fulfills the ADC state condition) on the fly). 266 */ 267 typedef struct 268 { 269 uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. 270 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 271 Note: Depending on devices and ADC instances, some channels may not be available 272 on device package pins. Refer to device datasheet for channels 273 availability. */ 274 275 uint32_t Rank; /*!< Specify the rank in the regular group sequencer. 276 This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS 277 Note: to disable a channel or change order of conversion sequencer, rank 278 containing a previous channel setting can be overwritten by the new channel 279 setting (or parameter number of conversions adjusted) */ 280 281 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 282 Unit: ADC clock cycles 283 Conversion time is the addition of sampling time and processing time 284 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 285 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 286 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME 287 Caution: This parameter applies to a channel that can be used into regular 288 and/or injected group. It overwrites the last setting. 289 Note: In case of usage of internal measurement channels (VrefInt, Vbat, ...), 290 sampling time constraints must be respected (sampling time can be adjusted 291 in function of ADC clock frequency and sampling time setting). 292 Refer to device datasheet for timings values. */ 293 294 uint32_t SingleDiff; /*!< Select single-ended or differential input. 295 In differential mode: Differential measurement is carried out between the 296 selected channel 'i' (positive input) and channel 'i+1' (negative input). 297 Only channel 'i' has to be configured, channel 'i+1' is configured automatically 298 This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING 299 Caution: This parameter applies to a channel that can be used in a regular 300 and/or injected group. 301 It overwrites the last setting. 302 Note: Refer to Reference Manual to ensure the selected channel is available in 303 differential mode. 304 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is 305 not usable separately. 306 Note: This parameter must be modified when ADC is disabled (before ADC start 307 conversion or after ADC stop conversion). 308 If ADC is enabled, this parameter setting is bypassed without error 309 reporting (as it can be the expected behavior in case of another parameter 310 update on the fly) */ 311 312 uint32_t OffsetNumber; /*!< Select the offset number 313 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB 314 Caution: Only one offset is allowed per channel. This parameter overwrites the 315 last setting. */ 316 317 uint32_t Offset; /*!< Define the offset to be applied on the raw converted data. 318 Offset value must be a positive number. 319 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter 320 must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 321 0x3FF, 0xFF or 0x3F respectively. 322 Note: This parameter must be modified when no conversion is on going on both 323 regular and injected groups (ADC disabled, or ADC enabled without 324 continuous mode or external trigger that could launch a conversion). */ 325 326 uint32_t OffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive 327 sign) from or to the raw converted data. 328 This parameter can be a value of @ref ADCEx_OffsetSign. 329 Note: This parameter must be modified when no conversion is on going on both 330 regular and injected groups (ADC disabled, or ADC enabled without 331 continuous mode or external trigger that could launch a conversion).*/ 332 FunctionalState OffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow. 333 This parameter value can be ENABLE or DISABLE. 334 Note: This parameter must be modified when no conversion is on going on both 335 regular and injected groups (ADC disabled, or ADC enabled without 336 continuous mode or external trigger that could launch a conversion). */ 337 338 } ADC_ChannelConfTypeDef; 339 340 /** 341 * @brief Structure definition of ADC analog watchdog 342 * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. 343 * ADC state can be either: 344 * - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion 345 on going on ADC groups regular and injected. 346 * - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular and 347 injected groups. 348 */ 349 typedef struct 350 { 351 uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. 352 For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels 353 by setting parameter 'WatchdogMode') 354 For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls 355 of 'HAL_ADC_AnalogWDGConfig()' for each channel) 356 This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ 357 358 uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. 359 For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all 360 channels, ADC groups regular and-or injected. 361 For Analog Watchdog 2 and 3: Several channels can be monitored by applying 362 successively the AWD init structure. Channels on ADC 363 group regular and injected are not differentiated: Set 364 value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 365 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor 366 all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no 367 channel. 368 This parameter can be a value of @ref ADC_analog_watchdog_mode. */ 369 370 uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. 371 For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' 372 is configured on single channel (only 1 channel can be 373 monitored). 374 For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, 375 call successively the function HAL_ADC_AnalogWDGConfig() 376 for each channel to be added (or removed with value 377 'ADC_ANALOGWATCHDOG_NONE'). 378 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ 379 380 FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. 381 This parameter can be set to ENABLE or DISABLE */ 382 383 uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. 384 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a 385 number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F 386 respectively. 387 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC 388 resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 389 LSB are ignored. 390 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 391 impacted: the comparison of analog watchdog thresholds is done on 392 oversampling final computation (after ratio and shift application): 393 ADC data register bitfield [15:4] (12 most significant bits). */ 394 395 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. 396 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a 397 number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F 398 respectively. 399 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC 400 resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 401 LSB are ignored. 402 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 403 impacted: the comparison of analog watchdog thresholds is done on 404 oversampling final computation (after ratio and shift application): 405 ADC data register bitfield [15:4] (12 most significant bits).*/ 406 407 uint32_t FilteringConfig; /*!< Specify whether filtering should be use and the number of samples to consider. 408 Before setting flag or raising interrupt, analog watchdog can wait to have several 409 consecutive out-of-window samples. This parameter allows to configure this number. 410 This parameter only applies to Analog watchdog 1. For others, use value 411 ADC_AWD_FILTERING_NONE. 412 This parameter can be a value of @ref ADC_analog_watchdog_filtering_config. */ 413 } ADC_AnalogWDGConfTypeDef; 414 415 /** 416 * @brief ADC group injected contexts queue configuration 417 * @note Structure intended to be used only through structure "ADC_HandleTypeDef" 418 */ 419 typedef struct 420 { 421 uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each 422 HAL_ADCEx_InjectedConfigChannel() call to finally initialize 423 JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */ 424 425 uint32_t ChannelCount; /*!< Number of channels in the injected sequence */ 426 } ADC_InjectionConfigTypeDef; 427 428 /** @defgroup ADC_States ADC States 429 * @{ 430 */ 431 432 /** 433 * @brief HAL ADC state machine: ADC states definition (bitfields) 434 * @note ADC state machine is managed by bitfields, state must be compared 435 * with bit by bit. 436 * For example: 437 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " 438 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " 439 */ 440 /* States of ADC global scope */ 441 #define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ 442 #define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ 443 #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, 444 calibration, ...) */ 445 #define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ 446 447 /* States of ADC errors */ 448 #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */ 449 #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */ 450 #define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */ 451 452 /* States of ADC group regular */ 453 #define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur 454 (either by continuous mode, external trigger, low power 455 auto power-on (if feature available), multimode ADC master 456 control (if feature available)) */ 457 #define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ 458 #define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ 459 #define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag 460 raised */ 461 462 /* States of ADC group injected */ 463 #define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur 464 (either by auto-injection mode, external trigger, low 465 power auto power-on (if feature available), multimode 466 ADC master control (if feature available)) */ 467 #define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */ 468 #define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */ 469 470 /* States of ADC analog watchdogs */ 471 #define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ 472 #define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */ 473 #define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ 474 475 /* States of ADC multi-mode */ 476 #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another ADC 477 master (when feature available) */ 478 479 /** 480 * @} 481 */ 482 483 /** 484 * @brief ADC handle Structure definition 485 */ 486 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 487 typedef struct __ADC_HandleTypeDef 488 #else 489 typedef struct 490 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 491 { 492 ADC_TypeDef *Instance; /*!< Register base address */ 493 ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular 494 conversions setting */ 495 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 496 HAL_LockTypeDef Lock; /*!< ADC locking object */ 497 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ 498 __IO uint32_t ErrorCode; /*!< ADC Error code */ 499 ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up 500 structure */ 501 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 502 void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ 503 void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer 504 callback */ 505 void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ 506 void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ 507 void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete 508 callback */ 509 void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue 510 overflow callback */ 511 void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ 512 void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ 513 void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ 514 void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ 515 void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ 516 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 517 } ADC_HandleTypeDef; 518 519 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 520 /** 521 * @brief HAL ADC Callback ID enumeration definition 522 */ 523 typedef enum 524 { 525 HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ 526 HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ 527 HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ 528 HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ 529 HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ 530 HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, /*!< ADC group injected context queue overflow callback ID */ 531 HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */ 532 HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */ 533 HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */ 534 HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ 535 HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ 536 } HAL_ADC_CallbackIDTypeDef; 537 538 /** 539 * @brief HAL ADC Callback pointer definition 540 */ 541 typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ 542 543 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 544 545 /** 546 * @} 547 */ 548 549 550 /* Exported constants --------------------------------------------------------*/ 551 552 /** @defgroup ADC_Exported_Constants ADC Exported Constants 553 * @{ 554 */ 555 556 /** @defgroup ADC_Error_Code ADC Error Code 557 * @{ 558 */ 559 #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ 560 #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking, 561 enable/disable, erroneous state, ...) */ 562 #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ 563 #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ 564 #define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */ 565 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 566 #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ 567 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 568 /** 569 * @} 570 */ 571 572 /** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source 573 * @{ 574 */ 575 576 #define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock from AHB clock 577 without prescaler */ 578 #define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock from AHB clock 579 with prescaler division by 2 */ 580 #define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock from AHB clock 581 with prescaler division by 4 */ 582 #define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without 583 prescaler */ 584 #define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler 585 division by 2 */ 586 #define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler 587 division by 4 */ 588 #define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler 589 division by 6 */ 590 #define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler 591 division by 8 */ 592 #define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler 593 division by 10 */ 594 #define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler 595 division by 12 */ 596 #define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler 597 division by 16 */ 598 #define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler 599 division by 32 */ 600 #define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler 601 division by 64 */ 602 #define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler 603 division by 128 */ 604 #define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler 605 division by 256 */ 606 /** 607 * @} 608 */ 609 610 /** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution 611 * @{ 612 */ 613 #define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */ 614 #define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */ 615 #define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */ 616 #define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits */ 617 /** 618 * @} 619 */ 620 621 /** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment 622 * @{ 623 */ 624 #define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned 625 (alignment on data register LSB bit 0)*/ 626 #define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned 627 (alignment on data register MSB bit 15)*/ 628 /** 629 * @} 630 */ 631 632 /** @defgroup ADC_Scan_mode ADC sequencer scan mode 633 * @{ 634 */ 635 #define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */ 636 #define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */ 637 /** 638 * @} 639 */ 640 641 /** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source 642 * @{ 643 */ 644 /* ADC group regular trigger sources for all ADC instances */ 645 #define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion 646 trigger software start */ 647 #define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion 648 trigger from external peripheral: TIM1 TRGO. */ 649 #define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion 650 trigger from external peripheral: TIM1 TRGO2. */ 651 #define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion 652 trigger from external peripheral: TIM1 channel 1 event (capture compare). */ 653 #define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion 654 trigger from external peripheral: TIM1 channel 2 event (capture compare). */ 655 #define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion 656 trigger from external peripheral: TIM1 channel 3 event (capture compare). */ 657 #define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion 658 trigger from external peripheral: TIM2 TRGO. */ 659 #define ADC_EXTERNALTRIG_T2_CC1 (LL_ADC_REG_TRIG_EXT_TIM2_CH1) /*!< ADC group regular conversion 660 trigger from external peripheral: TIM2 channel 1 event (capture compare). */ 661 #define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion 662 trigger from external peripheral: TIM2 channel 2 event (capture compare). */ 663 #define ADC_EXTERNALTRIG_T2_CC3 (LL_ADC_REG_TRIG_EXT_TIM2_CH3) /*!< ADC group regular conversion 664 trigger from external peripheral: TIM2 channel 3 event (capture compare). */ 665 #define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion 666 trigger from external peripheral: TIM3 TRGO. */ 667 #define ADC_EXTERNALTRIG_T3_CC1 (LL_ADC_REG_TRIG_EXT_TIM3_CH1) /*!< ADC group regular conversion 668 trigger from external peripheral: TIM3 channel 1 event (capture compare). */ 669 #define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion 670 trigger from external peripheral: TIM3 channel 4 event (capture compare). */ 671 #define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion 672 trigger from external peripheral: TIM4 TRGO. */ 673 #define ADC_EXTERNALTRIG_T4_CC1 (LL_ADC_REG_TRIG_EXT_TIM4_CH1) /*!< ADC group regular conversion 674 trigger from external peripheral: TIM4 channel 1 event (capture compare). */ 675 #define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion 676 trigger from external peripheral: TIM4 channel 4 event (capture compare). */ 677 #define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion 678 trigger from external peripheral: TIM6 TRGO. */ 679 #define ADC_EXTERNALTRIG_T7_TRGO (LL_ADC_REG_TRIG_EXT_TIM7_TRGO) /*!< ADC group regular conversion 680 trigger from external peripheral: TIM7 TRGO. */ 681 #define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion 682 trigger from external peripheral: TIM8 TRGO. */ 683 #define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion 684 trigger from external peripheral: TIM8 TRGO2. */ 685 #define ADC_EXTERNALTRIG_T8_CC1 (LL_ADC_REG_TRIG_EXT_TIM8_CH1) /*!< ADC group regular conversion 686 trigger from external peripheral: TIM8 channel 1 event (capture compare). */ 687 #define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion 688 trigger from external peripheral: TIM15 TRGO. */ 689 #define ADC_EXTERNALTRIG_T20_TRGO (LL_ADC_REG_TRIG_EXT_TIM20_TRGO) /*!< ADC group regular conversion 690 trigger from external peripheral: TIM20 TRGO. */ 691 #define ADC_EXTERNALTRIG_T20_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) /*!< ADC group regular conversion 692 trigger from external peripheral: TIM20 TRGO2. */ 693 #define ADC_EXTERNALTRIG_T20_CC1 (LL_ADC_REG_TRIG_EXT_TIM20_CH1) /*!< ADC group regular conversion 694 trigger from external peripheral: TIM20 channel 1 event (capture compare). */ 695 #define ADC_EXTERNALTRIG_T20_CC2 (LL_ADC_REG_TRIG_EXT_TIM20_CH2) /*!< ADC group regular conversion 696 trigger from external peripheral: TIM20 channel 2 event (capture compare). */ 697 #define ADC_EXTERNALTRIG_T20_CC3 (LL_ADC_REG_TRIG_EXT_TIM20_CH3) /*!< ADC group regular conversion 698 trigger from external peripheral: TIM20 channel 3 event (capture compare). */ 699 #define ADC_EXTERNALTRIG_HRTIM_TRG1 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) /*!< ADC group regular conversion 700 trigger from external peripheral: HRTIMER ADC trigger 1 event. */ 701 #define ADC_EXTERNALTRIG_HRTIM_TRG2 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG2) /*!< ADC group regular conversion 702 trigger from external peripheral: HRTIMER ADC trigger 2 event. */ 703 #define ADC_EXTERNALTRIG_HRTIM_TRG3 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) /*!< ADC group regular conversion 704 trigger from external peripheral: HRTIMER ADC trigger 3 event. */ 705 #define ADC_EXTERNALTRIG_HRTIM_TRG4 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG4) /*!< ADC group regular conversion 706 trigger from external peripheral: HRTIMER ADC trigger 4 event. */ 707 #define ADC_EXTERNALTRIG_HRTIM_TRG5 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG5) /*!< ADC group regular conversion 708 trigger from external peripheral: HRTIMER ADC trigger 5 event. */ 709 #define ADC_EXTERNALTRIG_HRTIM_TRG6 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG6) /*!< ADC group regular conversion 710 trigger from external peripheral: HRTIMER ADC trigger 6 event. */ 711 #define ADC_EXTERNALTRIG_HRTIM_TRG7 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG7) /*!< ADC group regular conversion 712 trigger from external peripheral: HRTIMER ADC trigger 7 event. */ 713 #define ADC_EXTERNALTRIG_HRTIM_TRG8 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG8) /*!< ADC group regular conversion 714 trigger from external peripheral: HRTIMER ADC trigger 8 event. */ 715 #define ADC_EXTERNALTRIG_HRTIM_TRG9 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG9) /*!< ADC group regular conversion 716 trigger from external peripheral: HRTIMER ADC trigger 9 event. */ 717 #define ADC_EXTERNALTRIG_HRTIM_TRG10 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG10) /*!< ADC group regular conversion 718 trigger from external peripheral: HRTIMER ADC trigger 10 event. */ 719 #define ADC_EXTERNALTRIG_EXT_IT2 (LL_ADC_REG_TRIG_EXT_EXTI_LINE2) /*!< ADC group regular conversion 720 trigger from external peripheral: external interrupt line 2. */ 721 #define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion 722 trigger from external peripheral: external interrupt line 11. */ 723 #define ADC_EXTERNALTRIG_LPTIM_OUT (LL_ADC_REG_TRIG_EXT_LPTIM_OUT) /*!< ADC group regular conversion 724 trigger from external peripheral: LPTIMER OUT event. */ 725 /** 726 * @} 727 */ 728 729 /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) 730 * @{ 731 */ 732 #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< ADC group regular trigger 733 disabled (SW start)*/ 734 #define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion 735 trigger polarity set to rising edge */ 736 #define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion 737 trigger polarity set to falling edge */ 738 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion 739 trigger polarity set to both rising and falling edges */ 740 /** 741 * @} 742 */ 743 744 /** @defgroup ADC_regular_sampling_mode ADC group regular sampling mode 745 * @{ 746 */ 747 #define ADC_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is 748 defined using @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME */ 749 #define ADC_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts 750 immediately after end of conversion, and stops upon trigger event. 751 Note: First conversion is using minimal sampling time 752 (see @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME) */ 753 #define ADC_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled 754 by trigger events: 755 Trigger rising edge = start sampling 756 Trigger falling edge = stop sampling and start conversion */ 757 /** 758 * @} 759 */ 760 761 /** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions 762 * @{ 763 */ 764 #define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */ 765 #define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */ 766 /** 767 * @} 768 */ 769 770 /** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data 771 * @{ 772 */ 773 #define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case 774 of overrun: data preserved */ 775 #define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case 776 of overrun: data overwritten */ 777 /** 778 * @} 779 */ 780 781 /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks 782 * @{ 783 */ 784 #define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ 785 #define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ 786 #define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ 787 #define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ 788 #define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ 789 #define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ 790 #define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ 791 #define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ 792 #define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */ 793 #define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */ 794 #define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */ 795 #define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */ 796 #define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */ 797 #define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */ 798 #define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */ 799 #define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */ 800 /** 801 * @} 802 */ 803 804 /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time 805 * @{ 806 */ 807 #define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles */ 808 #define ADC_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_6CYCLES_5) /*!< Sampling time 6.5 ADC clock cycles */ 809 #define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ 810 #define ADC_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_24CYCLES_5) /*!< Sampling time 24.5 ADC clock cycles */ 811 #define ADC_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_47CYCLES_5) /*!< Sampling time 47.5 ADC clock cycles */ 812 #define ADC_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_92CYCLES_5) /*!< Sampling time 92.5 ADC clock cycles */ 813 #define ADC_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_247CYCLES_5) /*!< Sampling time 247.5 ADC clock cycles */ 814 #define ADC_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_640CYCLES_5) /*!< Sampling time 640.5 ADC clock cycles */ 815 #define ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 3.5 816 ADC clock cycles. If selected, this sampling time replaces sampling time 817 2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. */ 818 /** 819 * @} 820 */ 821 822 /** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number 823 * @{ 824 */ 825 /* Note: VrefInt, TempSensor and Vbat internal channels are not available on */ 826 /* all ADC instances (refer to Reference Manual). */ 827 #define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< External channel (GPIO pin) ADCx_IN0 */ 828 #define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< External channel (GPIO pin) ADCx_IN1 */ 829 #define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< External channel (GPIO pin) ADCx_IN2 */ 830 #define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< External channel (GPIO pin) ADCx_IN3 */ 831 #define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< External channel (GPIO pin) ADCx_IN4 */ 832 #define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< External channel (GPIO pin) ADCx_IN5 */ 833 #define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< External channel (GPIO pin) ADCx_IN6 */ 834 #define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< External channel (GPIO pin) ADCx_IN7 */ 835 #define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< External channel (GPIO pin) ADCx_IN8 */ 836 #define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< External channel (GPIO pin) ADCx_IN9 */ 837 #define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< External channel (GPIO pin) ADCx_IN10 */ 838 #define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< External channel (GPIO pin) ADCx_IN11 */ 839 #define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< External channel (GPIO pin) ADCx_IN12 */ 840 #define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< External channel (GPIO pin) ADCx_IN13 */ 841 #define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< External channel (GPIO pin) ADCx_IN14 */ 842 #define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< External channel (GPIO pin) ADCx_IN15 */ 843 #define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< External channel (GPIO pin) ADCx_IN16 */ 844 #define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< External channel (GPIO pin) ADCx_IN17 */ 845 #define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< External channel (GPIO pin) ADCx_IN18 */ 846 #define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< Internal channel VrefInt: Internal 847 voltage reference. On this STM32 series, ADC channel available on all 848 instances but ADC2. */ 849 #define ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_TEMPSENSOR_ADC1) /*!< Internal channel Temperature sensor. 850 On this STM32 series, ADC channel available only on ADC1 instance. */ 851 #define ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_TEMPSENSOR_ADC5) /*!< Internal channel Temperature sensor. 852 On this STM32 series, ADC channel available only on ADC5 instance. 853 Refer to device datasheet for ADC5 availability */ 854 #define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< Internal channel Vbat/3: Vbat voltage 855 through a divider ladder of factor 1/3 to have channel voltage always below 856 Vdda. 857 On this STM32 series, ADC channel available on all Instances but ADC2 & ADC4. 858 Refer to device datasheet for ADC4 availability */ 859 #define ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_VOPAMP1) /*!< Internal channel OPAMP1 output. 860 On this STM32 series, ADC channel available only on ADC1 instance. */ 861 #define ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_VOPAMP2) /*!< Internal channel OPAMP2 output. 862 On this STM32 series, ADC channel available only on ADC2 instance. */ 863 #define ADC_CHANNEL_VOPAMP3_ADC2 (LL_ADC_CHANNEL_VOPAMP3_ADC2) /*!< Internal channel OPAMP3 output. 864 On this STM32 series, ADC channel available only on ADC2 instance. */ 865 #define ADC_CHANNEL_VOPAMP3_ADC3 (LL_ADC_CHANNEL_VOPAMP3_ADC3) /*!< Internal channel OPAMP3 output. 866 On this STM32 series, ADC channel available only on ADC3 instance. 867 Refer to device datasheet for ADC3 availability */ 868 #define ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_VOPAMP4) /*!< Internal channel OPAMP4 output. 869 On this STM32 series, ADC channel available only on ADC5 instance. 870 Refer to device datasheet for ADC5 availability */ 871 #define ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_VOPAMP5) /*!< Internal channel OPAMP5 output. 872 On this STM32 series, ADC channel available only on ADC5 instance. 873 Refer to device datasheet for ADC5 availability */ 874 #define ADC_CHANNEL_VOPAMP6 (LL_ADC_CHANNEL_VOPAMP6) /*!< Internal channel OPAMP6 output. 875 On this STM32 series, ADC channel available only on ADC4 instance. 876 Refer to device datasheet for ADC4 availability */ 877 /** 878 * @} 879 */ 880 881 /** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - ADC analog watchdog (AWD) number 882 * @{ 883 */ 884 #define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ 885 #define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */ 886 #define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */ 887 /** 888 * @} 889 */ 890 891 /** @defgroup ADC_analog_watchdog_filtering_config ADC analog watchdog (AWD) filtering configuration 892 * @{ 893 */ 894 #define ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC AWD no filtering, one 895 out-of-window sample to raise flag or interrupt */ 896 #define ADC_AWD_FILTERING_2SAMPLES ((ADC_TR1_AWDFILT_0)) /*!< ADC AWD 2 consecutives 897 out-of-window samples to raise flag or interrupt */ 898 #define ADC_AWD_FILTERING_3SAMPLES ((ADC_TR1_AWDFILT_1)) /*!< ADC AWD 3 consecutives 899 out-of-window samples to raise flag or interrupt */ 900 #define ADC_AWD_FILTERING_4SAMPLES ((ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0)) /*!< ADC AWD 4 consecutives 901 out-of-window samples to raise flag or interrupt */ 902 #define ADC_AWD_FILTERING_5SAMPLES ((ADC_TR1_AWDFILT_2)) /*!< ADC AWD 5 consecutives 903 out-of-window samples to raise flag or interrupt */ 904 #define ADC_AWD_FILTERING_6SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0)) /*!< ADC AWD 6 consecutives 905 out-of-window samples to raise flag or interrupt */ 906 #define ADC_AWD_FILTERING_7SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1)) /*!< ADC AWD 7 consecutives 907 out-of-window samples to raise flag or interrupt */ 908 #define ADC_AWD_FILTERING_8SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 \ 909 | ADC_TR1_AWDFILT_0)) /*!< ADC AWD 8 consecutives 910 out-of-window samples to raise flag or interrupt */ 911 /** 912 * @} 913 */ 914 915 /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog (AWD) mode 916 * @{ 917 */ 918 #define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< ADC AWD not selected */ 919 #define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< ADC AWD applied to a regular 920 group single channel */ 921 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to an 922 injected group single channel */ 923 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN\ 924 | ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to a regular 925 and injected groups single channel */ 926 #define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< ADC AWD applied to regular 927 group all channels */ 928 #define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to injected 929 group all channels */ 930 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to regular 931 and injected groups all channels */ 932 /** 933 * @} 934 */ 935 936 /** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio 937 * @{ 938 */ 939 /** 940 * @note The oversampling ratio is the number of ADC conversions performed, sum of these conversions data is computed 941 * to result as the ADC oversampling conversion data (before potential shift) 942 */ 943 #define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio 2 */ 944 #define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio 4 */ 945 #define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio 8 */ 946 #define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio 16 */ 947 #define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio 32 */ 948 #define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio 64 */ 949 #define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio 128 */ 950 #define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio 256 */ 951 /** 952 * @} 953 */ 954 955 /** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift 956 * @{ 957 */ 958 /** 959 * @note The sum of the ADC conversions data is divided by "Rightbitshift" number to result as the ADC oversampling 960 * conversion data) 961 */ 962 #define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift */ 963 #define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling right shift of 1 ranks */ 964 #define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling right shift of 2 ranks */ 965 #define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling right shift of 3 ranks */ 966 #define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling right shift of 4 ranks */ 967 #define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling right shift of 5 ranks */ 968 #define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling right shift of 6 ranks */ 969 #define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling right shift of 7 ranks */ 970 #define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling right shift of 8 ranks */ 971 /** 972 * @} 973 */ 974 975 /** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode 976 * @{ 977 */ 978 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: 979 continuous mode (all conversions of OVS ratio are done from 1 trigger) */ 980 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: 981 discontinuous mode (each conversion of OVS ratio needs a trigger) */ 982 /** 983 * @} 984 */ 985 986 /** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular 987 * @{ 988 */ 989 #define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained 990 during injection sequence */ 991 #define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during 992 injection sequence */ 993 /** 994 * @} 995 */ 996 997 /** @defgroup ADC_Event_type ADC Event type 998 * @{ 999 */ 1000 /** 1001 * @note Analog watchdog 1 is available on all stm32 series 1002 * Analog watchdog 2 and 3 are not available on all series 1003 */ 1004 #define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ 1005 #define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog) */ 1006 #define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog) */ 1007 #define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog) */ 1008 #define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ 1009 #define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */ 1010 /** 1011 * @} 1012 */ 1013 #define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility 1014 with other STM32 devices having only one analog watchdog */ 1015 1016 /** @defgroup ADC_interrupts_definition ADC interrupts definition 1017 * @{ 1018 */ 1019 #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ 1020 #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ 1021 #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ 1022 #define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ 1023 #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ 1024 #define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */ 1025 #define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */ 1026 #define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ 1027 #define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog 1028 watchdog) */ 1029 #define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog 1030 watchdog) */ 1031 #define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */ 1032 1033 /** 1034 * @} 1035 */ 1036 1037 /** @defgroup ADC_flags_definition ADC flags definition 1038 * @{ 1039 */ 1040 #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ 1041 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ 1042 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ 1043 #define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ 1044 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ 1045 #define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */ 1046 #define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */ 1047 #define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */ 1048 #define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ 1049 #define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ 1050 #define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */ 1051 1052 /** 1053 * @} 1054 */ 1055 1056 /** 1057 * @} 1058 */ 1059 1060 /* Private macro -------------------------------------------------------------*/ 1061 1062 /** @defgroup ADC_Private_Macros ADC Private Macros 1063 * @{ 1064 */ 1065 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 1066 /* code of final user. */ 1067 1068 /** 1069 * @brief Return resolution bits in CFGR register RES[1:0] field. 1070 * @param __HANDLE__ ADC handle 1071 * @retval Value of bitfield RES in CFGR register. 1072 */ 1073 #define ADC_GET_RESOLUTION(__HANDLE__) \ 1074 (LL_ADC_GetResolution((__HANDLE__)->Instance)) 1075 1076 /** 1077 * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE"). 1078 * @param __HANDLE__ ADC handle 1079 * @retval None 1080 */ 1081 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 1082 1083 /** 1084 * @brief Simultaneously clear and set specific bits of the handle State. 1085 * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 1086 * the first parameter is the ADC handle State, the second parameter is the 1087 * bit field to clear, the third and last parameter is the bit field to set. 1088 * @retval None 1089 */ 1090 #define ADC_STATE_CLR_SET MODIFY_REG 1091 1092 /** 1093 * @brief Verify that a given value is aligned with the ADC resolution range. 1094 * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits). 1095 * @param __ADC_VALUE__ value checked against the resolution. 1096 * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) 1097 */ 1098 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ 1099 ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__)) 1100 1101 /** 1102 * @brief Verify the length of the scheduled regular conversions group. 1103 * @param __LENGTH__ number of programmed conversions. 1104 * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) 1105 * or RESET (__LENGTH__ is null or too large) 1106 */ 1107 #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL))) 1108 1109 1110 /** 1111 * @brief Verify the number of scheduled regular conversions in discontinuous mode. 1112 * @param NUMBER number of scheduled regular conversions in discontinuous mode. 1113 * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) 1114 * or RESET (NUMBER is null or too large) 1115 */ 1116 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL))) 1117 1118 1119 /** 1120 * @brief Verify the ADC clock setting. 1121 * @param __ADC_CLOCK__ programmed ADC clock. 1122 * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid) 1123 */ 1124 #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \ 1125 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ 1126 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ 1127 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \ 1128 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \ 1129 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \ 1130 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \ 1131 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \ 1132 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \ 1133 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \ 1134 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \ 1135 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \ 1136 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \ 1137 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \ 1138 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) ) 1139 1140 /** 1141 * @brief Verify the ADC resolution setting. 1142 * @param __RESOLUTION__ programmed ADC resolution. 1143 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 1144 */ 1145 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ 1146 ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ 1147 ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ 1148 ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) 1149 1150 /** 1151 * @brief Verify the ADC resolution setting when limited to 6 or 8 bits. 1152 * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits. 1153 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 1154 */ 1155 #define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ 1156 ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) 1157 1158 /** 1159 * @brief Verify the ADC converted data alignment. 1160 * @param __ALIGN__ programmed ADC converted data alignment. 1161 * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid) 1162 */ 1163 #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \ 1164 ((__ALIGN__) == ADC_DATAALIGN_LEFT) ) 1165 1166 /** 1167 * @brief Verify the ADC gain compensation. 1168 * @param __GAIN_COMPENSATION__ programmed ADC gain compensation coefficient. 1169 * @retval SET (__GAIN_COMPENSATION__ is a valid value) or RESET (__GAIN_COMPENSATION__ is invalid) 1170 */ 1171 #define IS_ADC_GAIN_COMPENSATION(__GAIN_COMPENSATION__) ((__GAIN_COMPENSATION__) <= 16393UL) 1172 1173 /** 1174 * @brief Verify the ADC scan mode. 1175 * @param __SCAN_MODE__ programmed ADC scan mode. 1176 * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid) 1177 */ 1178 #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \ 1179 ((__SCAN_MODE__) == ADC_SCAN_ENABLE) ) 1180 1181 /** 1182 * @brief Verify the ADC edge trigger setting for regular group. 1183 * @param __EDGE__ programmed ADC edge trigger setting. 1184 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 1185 */ 1186 #define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 1187 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 1188 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 1189 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) 1190 1191 /** 1192 * @brief Verify the ADC regular conversions external trigger. 1193 * @param __HANDLE__ ADC handle 1194 * @param __REGTRIG__ programmed ADC regular conversions external trigger. 1195 * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid) 1196 */ 1197 #if defined(STM32G474xx) || defined(STM32G484xx) 1198 #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ 1199 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 1200 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ 1201 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ 1202 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ 1203 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ 1204 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ 1205 ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \ 1206 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ 1207 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ 1208 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ 1209 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO) || \ 1210 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \ 1211 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \ 1212 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG1) || \ 1213 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG3) || \ 1214 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG5) || \ 1215 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG6) || \ 1216 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG7) || \ 1217 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG8) || \ 1218 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG9) || \ 1219 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG10) || \ 1220 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ 1221 ((((__HANDLE__)->Instance == ADC1) || \ 1222 ((__HANDLE__)->Instance == ADC2)) && \ 1223 (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ 1224 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ 1225 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ 1226 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ 1227 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ 1228 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \ 1229 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \ 1230 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \ 1231 ((((__HANDLE__)->Instance == ADC3) || \ 1232 ((__HANDLE__)->Instance == ADC4) || \ 1233 ((__HANDLE__)->Instance == ADC5)) && \ 1234 (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ 1235 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ 1236 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ 1237 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ 1238 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ 1239 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG2) || \ 1240 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG4) || \ 1241 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \ 1242 ((__REGTRIG__) == ADC_SOFTWARE_START) ) 1243 #elif defined(STM32G473xx) || defined(STM32G483xx) 1244 #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ 1245 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 1246 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ 1247 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ 1248 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ 1249 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ 1250 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ 1251 ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \ 1252 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ 1253 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ 1254 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ 1255 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO) || \ 1256 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \ 1257 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \ 1258 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ 1259 ((((__HANDLE__)->Instance == ADC1) || \ 1260 ((__HANDLE__)->Instance == ADC2)) && \ 1261 (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ 1262 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ 1263 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ 1264 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ 1265 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ 1266 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \ 1267 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \ 1268 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \ 1269 ((((__HANDLE__)->Instance == ADC3) || \ 1270 ((__HANDLE__)->Instance == ADC4) || \ 1271 ((__HANDLE__)->Instance == ADC5)) && \ 1272 (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ 1273 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ 1274 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ 1275 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ 1276 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ 1277 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \ 1278 ((__REGTRIG__) == ADC_SOFTWARE_START) ) 1279 #elif defined(STM32G471xx) 1280 #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ 1281 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 1282 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ 1283 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ 1284 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ 1285 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ 1286 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ 1287 ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \ 1288 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ 1289 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ 1290 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ 1291 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ 1292 ((((__HANDLE__)->Instance == ADC1) || \ 1293 ((__HANDLE__)->Instance == ADC2)) && \ 1294 (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ 1295 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ 1296 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ 1297 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ 1298 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ 1299 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \ 1300 ((((__HANDLE__)->Instance == ADC3)) && \ 1301 (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ 1302 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ 1303 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ 1304 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ 1305 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ 1306 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \ 1307 ((__REGTRIG__) == ADC_SOFTWARE_START) ) 1308 #elif defined(STM32G411xB) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) 1309 #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ 1310 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 1311 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ 1312 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ 1313 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ 1314 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ 1315 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ 1316 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ 1317 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ 1318 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ 1319 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ 1320 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ 1321 ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \ 1322 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ 1323 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ 1324 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ 1325 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ 1326 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ 1327 ((__REGTRIG__) == ADC_SOFTWARE_START) ) 1328 #elif defined(STM32G491xx) || defined(STM32G4A1xx) || defined(STM32G411xC) 1329 #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ 1330 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 1331 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ 1332 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ 1333 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ 1334 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ 1335 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ 1336 ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \ 1337 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ 1338 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ 1339 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ 1340 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO) || \ 1341 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \ 1342 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \ 1343 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ 1344 ((((__HANDLE__)->Instance == ADC1) || \ 1345 ((__HANDLE__)->Instance == ADC2)) && \ 1346 (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ 1347 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ 1348 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ 1349 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ 1350 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ 1351 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \ 1352 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \ 1353 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \ 1354 (((__HANDLE__)->Instance == ADC3) && \ 1355 (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ 1356 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ 1357 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ 1358 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ 1359 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ 1360 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \ 1361 ((__REGTRIG__) == ADC_SOFTWARE_START) ) 1362 #endif /* STM32G4xx */ 1363 1364 /** 1365 * @brief Verify the ADC regular conversions external trigger. 1366 * @param __SAMPLINGMODE__ programmed ADC regular conversions external trigger. 1367 * @retval SET (__SAMPLINGMODE__ is a valid value) or RESET (__SAMPLINGMODE__ is invalid) 1368 */ 1369 #define IS_ADC_SAMPLINGMODE(__SAMPLINGMODE__) (((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_NORMAL) || \ 1370 ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_BULB) || \ 1371 ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_TRIGGER_CONTROLED) ) 1372 1373 /** 1374 * @brief Verify the ADC regular conversions check for converted data availability. 1375 * @param __EOC_SELECTION__ converted data availability check. 1376 * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid) 1377 */ 1378 #define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \ 1379 ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) ) 1380 1381 /** 1382 * @brief Verify the ADC regular conversions overrun handling. 1383 * @param __OVR__ ADC regular conversions overrun handling. 1384 * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid) 1385 */ 1386 #define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \ 1387 ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) ) 1388 1389 /** 1390 * @brief Verify the ADC conversions sampling time. 1391 * @param __TIME__ ADC conversions sampling time. 1392 * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid) 1393 */ 1394 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \ 1395 ((__TIME__) == ADC_SAMPLETIME_3CYCLES_5) || \ 1396 ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \ 1397 ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \ 1398 ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5) || \ 1399 ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5) || \ 1400 ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \ 1401 ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \ 1402 ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) ) 1403 1404 /** 1405 * @brief Verify the ADC regular channel setting. 1406 * @param __CHANNEL__ programmed ADC regular channel. 1407 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 1408 */ 1409 #define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \ 1410 ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \ 1411 ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \ 1412 ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \ 1413 ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \ 1414 ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \ 1415 ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \ 1416 ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \ 1417 ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \ 1418 ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \ 1419 ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \ 1420 ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \ 1421 ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \ 1422 ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \ 1423 ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \ 1424 ((__CHANNEL__) == ADC_REGULAR_RANK_16) ) 1425 1426 /** 1427 * @} 1428 */ 1429 1430 1431 /* Private constants ---------------------------------------------------------*/ 1432 1433 /** @defgroup ADC_Private_Constants ADC Private Constants 1434 * @{ 1435 */ 1436 1437 /* Fixed timeout values for ADC conversion (including sampling time) */ 1438 /* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111 */ 1439 /* Maximum conversion time is 12.5 + Maximum sampling time */ 1440 /* or 12.5 + 640.5 = 653 ADC clock cycles */ 1441 /* Minimum ADC Clock frequency is 0.14 MHz */ 1442 /* Maximum conversion time is */ 1443 /* 653 / 0.14 MHz = 4.66 ms */ 1444 #define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */ 1445 1446 /* Delay for temperature sensor stabilization time. */ 1447 /* Maximum delay is 120us (refer device datasheet, parameter tSTART). */ 1448 /* Unit: us */ 1449 #define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US) 1450 1451 /** 1452 * @} 1453 */ 1454 1455 /* Exported macro ------------------------------------------------------------*/ 1456 1457 /** @defgroup ADC_Exported_Macros ADC Exported Macros 1458 * @{ 1459 */ 1460 /* Macro for internal HAL driver usage, and possibly can be used into code of */ 1461 /* final user. */ 1462 1463 /** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags. 1464 * @{ 1465 */ 1466 1467 /** @brief Reset ADC handle state. 1468 * @param __HANDLE__ ADC handle 1469 * @retval None 1470 */ 1471 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1472 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1473 do{ \ 1474 (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ 1475 (__HANDLE__)->MspInitCallback = NULL; \ 1476 (__HANDLE__)->MspDeInitCallback = NULL; \ 1477 } while(0) 1478 #else 1479 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1480 ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 1481 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 1482 1483 /** 1484 * @brief Enable ADC interrupt. 1485 * @param __HANDLE__ ADC handle 1486 * @param __INTERRUPT__ ADC Interrupt 1487 * This parameter can be one of the following values: 1488 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1489 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1490 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1491 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1492 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1493 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1494 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1495 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1496 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1497 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1498 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1499 * @retval None 1500 */ 1501 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 1502 (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) 1503 1504 /** 1505 * @brief Disable ADC interrupt. 1506 * @param __HANDLE__ ADC handle 1507 * @param __INTERRUPT__ ADC Interrupt 1508 * This parameter can be one of the following values: 1509 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1510 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1511 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1512 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1513 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1514 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1515 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1516 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1517 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1518 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1519 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1520 * @retval None 1521 */ 1522 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 1523 (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) 1524 1525 /** @brief Checks if the specified ADC interrupt source is enabled or disabled. 1526 * @param __HANDLE__ ADC handle 1527 * @param __INTERRUPT__ ADC interrupt source to check 1528 * This parameter can be one of the following values: 1529 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1530 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1531 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1532 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1533 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1534 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1535 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1536 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1537 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1538 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1539 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1540 * @retval State of interruption (SET or RESET) 1541 */ 1542 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 1543 (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) 1544 1545 /** 1546 * @brief Check whether the specified ADC flag is set or not. 1547 * @param __HANDLE__ ADC handle 1548 * @param __FLAG__ ADC flag 1549 * This parameter can be one of the following values: 1550 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1551 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1552 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1553 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1554 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1555 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag 1556 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag 1557 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1558 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1559 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1560 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. 1561 * @retval State of flag (TRUE or FALSE). 1562 */ 1563 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ 1564 ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) 1565 1566 /** 1567 * @brief Clear the specified ADC flag. 1568 * @param __HANDLE__ ADC handle 1569 * @param __FLAG__ ADC flag 1570 * This parameter can be one of the following values: 1571 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1572 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1573 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1574 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1575 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1576 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag 1577 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag 1578 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1579 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1580 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1581 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. 1582 * @retval None 1583 */ 1584 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ 1585 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 1586 (((__HANDLE__)->Instance->ISR) = (__FLAG__)) 1587 1588 /** 1589 * @} 1590 */ 1591 1592 /** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro 1593 * @{ 1594 */ 1595 1596 /** 1597 * @brief Helper macro to get ADC channel number in decimal format 1598 * from literals ADC_CHANNEL_x. 1599 * @note Example: 1600 * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) 1601 * will return decimal number "4". 1602 * @note The input can be a value from functions where a channel 1603 * number is returned, either defined with number 1604 * or with bitfield (only one bit must be set). 1605 * @param __CHANNEL__ This parameter can be one of the following values: 1606 * @arg @ref ADC_CHANNEL_0 1607 * @arg @ref ADC_CHANNEL_1 (8) 1608 * @arg @ref ADC_CHANNEL_2 (8) 1609 * @arg @ref ADC_CHANNEL_3 (8) 1610 * @arg @ref ADC_CHANNEL_4 (8) 1611 * @arg @ref ADC_CHANNEL_5 (8) 1612 * @arg @ref ADC_CHANNEL_6 1613 * @arg @ref ADC_CHANNEL_7 1614 * @arg @ref ADC_CHANNEL_8 1615 * @arg @ref ADC_CHANNEL_9 1616 * @arg @ref ADC_CHANNEL_10 1617 * @arg @ref ADC_CHANNEL_11 1618 * @arg @ref ADC_CHANNEL_12 1619 * @arg @ref ADC_CHANNEL_13 1620 * @arg @ref ADC_CHANNEL_14 1621 * @arg @ref ADC_CHANNEL_15 1622 * @arg @ref ADC_CHANNEL_16 1623 * @arg @ref ADC_CHANNEL_17 1624 * @arg @ref ADC_CHANNEL_18 1625 * @arg @ref ADC_CHANNEL_VREFINT (7) 1626 * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1) 1627 * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5) 1628 * @arg @ref ADC_CHANNEL_VBAT (6) 1629 * @arg @ref ADC_CHANNEL_VOPAMP1 (1) 1630 * @arg @ref ADC_CHANNEL_VOPAMP2 (2) 1631 * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2) 1632 * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3) 1633 * @arg @ref ADC_CHANNEL_VOPAMP4 (5) 1634 * @arg @ref ADC_CHANNEL_VOPAMP5 (5) 1635 * @arg @ref ADC_CHANNEL_VOPAMP6 (4) 1636 * 1637 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n 1638 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n 1639 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n 1640 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n 1641 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n 1642 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n 1643 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n 1644 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet 1645 * for more details. 1646 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to 1647 * convert in 12-bit resolution. 1648 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles 1649 * (fADC) to convert in 12-bit resolution.\n 1650 * @retval Value between Min_Data=0 and Max_Data=18 1651 */ 1652 #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 1653 __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) 1654 1655 /** 1656 * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x 1657 * from number in decimal format. 1658 * @note Example: 1659 * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) 1660 * will return a data equivalent to "ADC_CHANNEL_4". 1661 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 1662 * @retval Returned value can be one of the following values: 1663 * @arg @ref ADC_CHANNEL_0 1664 * @arg @ref ADC_CHANNEL_1 (8) 1665 * @arg @ref ADC_CHANNEL_2 (8) 1666 * @arg @ref ADC_CHANNEL_3 (8) 1667 * @arg @ref ADC_CHANNEL_4 (8) 1668 * @arg @ref ADC_CHANNEL_5 (8) 1669 * @arg @ref ADC_CHANNEL_6 1670 * @arg @ref ADC_CHANNEL_7 1671 * @arg @ref ADC_CHANNEL_8 1672 * @arg @ref ADC_CHANNEL_9 1673 * @arg @ref ADC_CHANNEL_10 1674 * @arg @ref ADC_CHANNEL_11 1675 * @arg @ref ADC_CHANNEL_12 1676 * @arg @ref ADC_CHANNEL_13 1677 * @arg @ref ADC_CHANNEL_14 1678 * @arg @ref ADC_CHANNEL_15 1679 * @arg @ref ADC_CHANNEL_16 1680 * @arg @ref ADC_CHANNEL_17 1681 * @arg @ref ADC_CHANNEL_18 1682 * @arg @ref ADC_CHANNEL_VREFINT (7) 1683 * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1) 1684 * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5) 1685 * @arg @ref ADC_CHANNEL_VBAT (6) 1686 * @arg @ref ADC_CHANNEL_VOPAMP1 (1) 1687 * @arg @ref ADC_CHANNEL_VOPAMP2 (2) 1688 * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2) 1689 * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3) 1690 * @arg @ref ADC_CHANNEL_VOPAMP4 (5) 1691 * @arg @ref ADC_CHANNEL_VOPAMP5 (5) 1692 * @arg @ref ADC_CHANNEL_VOPAMP6 (4) 1693 * 1694 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n 1695 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n 1696 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n 1697 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n 1698 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n 1699 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n 1700 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n 1701 * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for 1702 * more details. 1703 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) 1704 * to convert in 12-bit resolution. 1705 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles 1706 * (fADC) to convert in 12-bit resolution.\n 1707 * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, 1708 * comparison with internal channel parameter to be done 1709 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 1710 */ 1711 #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 1712 __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) 1713 1714 /** 1715 * @brief Helper macro to determine whether the selected channel 1716 * corresponds to literal definitions of driver. 1717 * @note The different literal definitions of ADC channels are: 1718 * - ADC internal channel: 1719 * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ... 1720 * - ADC external channel (channel connected to a GPIO pin): 1721 * ADC_CHANNEL_1, ADC_CHANNEL_2, ... 1722 * @note The channel parameter must be a value defined from literal 1723 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1724 * ADC_CHANNEL_TEMPSENSOR, ...), 1725 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), 1726 * must not be a value from functions where a channel number is 1727 * returned from ADC registers, 1728 * because internal and external channels share the same channel 1729 * number in ADC registers. The differentiation is made only with 1730 * parameters definitions of driver. 1731 * @param __CHANNEL__ This parameter can be one of the following values: 1732 * @arg @ref ADC_CHANNEL_0 1733 * @arg @ref ADC_CHANNEL_1 (8) 1734 * @arg @ref ADC_CHANNEL_2 (8) 1735 * @arg @ref ADC_CHANNEL_3 (8) 1736 * @arg @ref ADC_CHANNEL_4 (8) 1737 * @arg @ref ADC_CHANNEL_5 (8) 1738 * @arg @ref ADC_CHANNEL_6 1739 * @arg @ref ADC_CHANNEL_7 1740 * @arg @ref ADC_CHANNEL_8 1741 * @arg @ref ADC_CHANNEL_9 1742 * @arg @ref ADC_CHANNEL_10 1743 * @arg @ref ADC_CHANNEL_11 1744 * @arg @ref ADC_CHANNEL_12 1745 * @arg @ref ADC_CHANNEL_13 1746 * @arg @ref ADC_CHANNEL_14 1747 * @arg @ref ADC_CHANNEL_15 1748 * @arg @ref ADC_CHANNEL_16 1749 * @arg @ref ADC_CHANNEL_17 1750 * @arg @ref ADC_CHANNEL_18 1751 * @arg @ref ADC_CHANNEL_VREFINT (7) 1752 * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1) 1753 * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5) 1754 * @arg @ref ADC_CHANNEL_VBAT (6) 1755 * @arg @ref ADC_CHANNEL_VOPAMP1 (1) 1756 * @arg @ref ADC_CHANNEL_VOPAMP2 (2) 1757 * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2) 1758 * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3) 1759 * @arg @ref ADC_CHANNEL_VOPAMP4 (5) 1760 * @arg @ref ADC_CHANNEL_VOPAMP5 (5) 1761 * @arg @ref ADC_CHANNEL_VOPAMP6 (4) 1762 * 1763 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n 1764 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n 1765 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n 1766 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n 1767 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n 1768 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n 1769 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n 1770 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet 1771 * for more details. 1772 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to 1773 * convert in 12-bit resolution. 1774 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles 1775 * (fADC) to convert in 12-bit resolution.\n 1776 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel 1777 * connected to a GPIO pin). 1778 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. 1779 */ 1780 #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ 1781 __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) 1782 1783 /** 1784 * @brief Helper macro to convert a channel defined from parameter 1785 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1786 * ADC_CHANNEL_TEMPSENSOR, ...), 1787 * to its equivalent parameter definition of a ADC external channel 1788 * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...). 1789 * @note The channel parameter can be, additionally to a value 1790 * defined from parameter definition of a ADC internal channel 1791 * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), 1792 * a value defined from parameter definition of 1793 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1794 * or a value from functions where a channel number is returned 1795 * from ADC registers. 1796 * @param __CHANNEL__ This parameter can be one of the following values: 1797 * @arg @ref ADC_CHANNEL_0 1798 * @arg @ref ADC_CHANNEL_1 (8) 1799 * @arg @ref ADC_CHANNEL_2 (8) 1800 * @arg @ref ADC_CHANNEL_3 (8) 1801 * @arg @ref ADC_CHANNEL_4 (8) 1802 * @arg @ref ADC_CHANNEL_5 (8) 1803 * @arg @ref ADC_CHANNEL_6 1804 * @arg @ref ADC_CHANNEL_7 1805 * @arg @ref ADC_CHANNEL_8 1806 * @arg @ref ADC_CHANNEL_9 1807 * @arg @ref ADC_CHANNEL_10 1808 * @arg @ref ADC_CHANNEL_11 1809 * @arg @ref ADC_CHANNEL_12 1810 * @arg @ref ADC_CHANNEL_13 1811 * @arg @ref ADC_CHANNEL_14 1812 * @arg @ref ADC_CHANNEL_15 1813 * @arg @ref ADC_CHANNEL_16 1814 * @arg @ref ADC_CHANNEL_17 1815 * @arg @ref ADC_CHANNEL_18 1816 * @arg @ref ADC_CHANNEL_VREFINT (7) 1817 * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1) 1818 * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5) 1819 * @arg @ref ADC_CHANNEL_VBAT (6) 1820 * @arg @ref ADC_CHANNEL_VOPAMP1 (1) 1821 * @arg @ref ADC_CHANNEL_VOPAMP2 (2) 1822 * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2) 1823 * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3) 1824 * @arg @ref ADC_CHANNEL_VOPAMP4 (5) 1825 * @arg @ref ADC_CHANNEL_VOPAMP5 (5) 1826 * @arg @ref ADC_CHANNEL_VOPAMP6 (4) 1827 * 1828 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n 1829 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n 1830 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n 1831 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n 1832 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n 1833 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n 1834 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n 1835 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet 1836 * for more details. 1837 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to 1838 * convert in 12-bit resolution. 1839 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles 1840 * (fADC) to convert in 12-bit resolution.\n 1841 * @retval Returned value can be one of the following values: 1842 * @arg @ref ADC_CHANNEL_0 1843 * @arg @ref ADC_CHANNEL_1 1844 * @arg @ref ADC_CHANNEL_2 1845 * @arg @ref ADC_CHANNEL_3 1846 * @arg @ref ADC_CHANNEL_4 1847 * @arg @ref ADC_CHANNEL_5 1848 * @arg @ref ADC_CHANNEL_6 1849 * @arg @ref ADC_CHANNEL_7 1850 * @arg @ref ADC_CHANNEL_8 1851 * @arg @ref ADC_CHANNEL_9 1852 * @arg @ref ADC_CHANNEL_10 1853 * @arg @ref ADC_CHANNEL_11 1854 * @arg @ref ADC_CHANNEL_12 1855 * @arg @ref ADC_CHANNEL_13 1856 * @arg @ref ADC_CHANNEL_14 1857 * @arg @ref ADC_CHANNEL_15 1858 * @arg @ref ADC_CHANNEL_16 1859 * @arg @ref ADC_CHANNEL_17 1860 * @arg @ref ADC_CHANNEL_18 1861 */ 1862 #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ 1863 __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) 1864 1865 /** 1866 * @brief Helper macro to determine whether the internal channel 1867 * selected is available on the ADC instance selected. 1868 * @note The channel parameter must be a value defined from parameter 1869 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1870 * ADC_CHANNEL_TEMPSENSOR, ...), 1871 * must not be a value defined from parameter definition of 1872 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1873 * or a value from functions where a channel number is 1874 * returned from ADC registers, 1875 * because internal and external channels share the same channel 1876 * number in ADC registers. The differentiation is made only with 1877 * parameters definitions of driver. 1878 * @param __ADC_INSTANCE__ ADC instance 1879 * @param __CHANNEL__ This parameter can be one of the following values: 1880 * @arg @ref ADC_CHANNEL_VREFINT (7) 1881 * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1) 1882 * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5) 1883 * @arg @ref ADC_CHANNEL_VBAT (6) 1884 * @arg @ref ADC_CHANNEL_VOPAMP1 (1) 1885 * @arg @ref ADC_CHANNEL_VOPAMP2 (2) 1886 * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2) 1887 * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3) 1888 * @arg @ref ADC_CHANNEL_VOPAMP4 (5) 1889 * @arg @ref ADC_CHANNEL_VOPAMP5 (5) 1890 * @arg @ref ADC_CHANNEL_VOPAMP6 (4) 1891 * 1892 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n 1893 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n 1894 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n 1895 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n 1896 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n 1897 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n 1898 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n 1899 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet 1900 * for more details. 1901 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. 1902 * Value "1" if the internal channel selected is available on the ADC instance selected. 1903 */ 1904 #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ 1905 __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) 1906 1907 #if defined(ADC_MULTIMODE_SUPPORT) 1908 /** 1909 * @brief Helper macro to get the ADC multimode conversion data of ADC master 1910 * or ADC slave from raw value with both ADC conversion data concatenated. 1911 * @note This macro is intended to be used when multimode transfer by DMA 1912 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). 1913 * In this case the transferred data need to processed with this macro 1914 * to separate the conversion data of ADC master and ADC slave. 1915 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: 1916 * @arg @ref LL_ADC_MULTI_MASTER 1917 * @arg @ref LL_ADC_MULTI_SLAVE 1918 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF 1919 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 1920 */ 1921 #define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ 1922 __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__)) 1923 #endif /* ADC_MULTIMODE_SUPPORT */ 1924 1925 /** 1926 * @brief Helper macro to select the ADC common instance 1927 * to which is belonging the selected ADC instance. 1928 * @note ADC common register instance can be used for: 1929 * - Set parameters common to several ADC instances 1930 * - Multimode (for devices with several ADC instances) 1931 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1932 * @param __ADCx__ ADC instance 1933 * @retval ADC common register instance 1934 */ 1935 #define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ 1936 __LL_ADC_COMMON_INSTANCE((__ADCx__)) 1937 1938 /** 1939 * @brief Helper macro to check if all ADC instances sharing the same 1940 * ADC common instance are disabled. 1941 * @note This check is required by functions with setting conditioned to 1942 * ADC state: 1943 * All ADC instances of the ADC common group must be disabled. 1944 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1945 * @note On devices with only 1 ADC common instance, parameter of this macro 1946 * is useless and can be ignored (parameter kept for compatibility 1947 * with devices featuring several ADC common instances). 1948 * @param __ADCXY_COMMON__ ADC common instance 1949 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 1950 * @retval Value "0" if all ADC instances sharing the same ADC common instance 1951 * are disabled. 1952 * Value "1" if at least one ADC instance sharing the same ADC common instance 1953 * is enabled. 1954 */ 1955 #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 1956 __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) 1957 1958 /** 1959 * @brief Helper macro to define the ADC conversion data full-scale digital 1960 * value corresponding to the selected ADC resolution. 1961 * @note ADC conversion data full-scale corresponds to voltage range 1962 * determined by analog voltage references Vref+ and Vref- 1963 * (refer to reference manual). 1964 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1965 * @arg @ref ADC_RESOLUTION_12B 1966 * @arg @ref ADC_RESOLUTION_10B 1967 * @arg @ref ADC_RESOLUTION_8B 1968 * @arg @ref ADC_RESOLUTION_6B 1969 * @retval ADC conversion data full-scale digital value 1970 */ 1971 #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 1972 __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) 1973 1974 /** 1975 * @brief Helper macro to convert the ADC conversion data from 1976 * a resolution to another resolution. 1977 * @param __DATA__ ADC conversion data to be converted 1978 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted 1979 * This parameter can be one of the following values: 1980 * @arg @ref ADC_RESOLUTION_12B 1981 * @arg @ref ADC_RESOLUTION_10B 1982 * @arg @ref ADC_RESOLUTION_8B 1983 * @arg @ref ADC_RESOLUTION_6B 1984 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion 1985 * This parameter can be one of the following values: 1986 * @arg @ref ADC_RESOLUTION_12B 1987 * @arg @ref ADC_RESOLUTION_10B 1988 * @arg @ref ADC_RESOLUTION_8B 1989 * @arg @ref ADC_RESOLUTION_6B 1990 * @retval ADC conversion data to the requested resolution 1991 */ 1992 #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ 1993 __ADC_RESOLUTION_CURRENT__,\ 1994 __ADC_RESOLUTION_TARGET__) \ 1995 __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ 1996 (__ADC_RESOLUTION_CURRENT__),\ 1997 (__ADC_RESOLUTION_TARGET__)) 1998 1999 /** 2000 * @brief Helper macro to calculate the voltage (unit: mVolt) 2001 * corresponding to a ADC conversion data (unit: digital value). 2002 * @note Analog reference voltage (Vref+) must be either known from 2003 * user board environment or can be calculated using ADC measurement 2004 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 2005 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 2006 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) 2007 * (unit: digital value). 2008 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 2009 * @arg @ref ADC_RESOLUTION_12B 2010 * @arg @ref ADC_RESOLUTION_10B 2011 * @arg @ref ADC_RESOLUTION_8B 2012 * @arg @ref ADC_RESOLUTION_6B 2013 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 2014 */ 2015 #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ 2016 __ADC_DATA__,\ 2017 __ADC_RESOLUTION__) \ 2018 __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ 2019 (__ADC_DATA__),\ 2020 (__ADC_RESOLUTION__)) 2021 2022 /** 2023 * @brief Helper macro to calculate the voltage (unit: mVolt) 2024 * corresponding to a ADC conversion data (unit: digital value) 2025 * in differential ended mode. 2026 * @note Analog reference voltage (Vref+) must be either known from 2027 * user board environment or can be calculated using ADC measurement 2028 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 2029 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 2030 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) 2031 * (unit: digital value). 2032 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 2033 * @arg @ref ADC_RESOLUTION_12B 2034 * @arg @ref ADC_RESOLUTION_10B 2035 * @arg @ref ADC_RESOLUTION_8B 2036 * @arg @ref ADC_RESOLUTION_6B 2037 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 2038 */ 2039 #define __HAL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ 2040 __ADC_DATA__,\ 2041 __ADC_RESOLUTION__) \ 2042 __LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ 2043 (__ADC_DATA__),\ 2044 (__ADC_RESOLUTION__)) 2045 2046 /** 2047 * @brief Helper macro to calculate analog reference voltage (Vref+) 2048 * (unit: mVolt) from ADC conversion data of internal voltage 2049 * reference VrefInt. 2050 * @note Computation is using VrefInt calibration value 2051 * stored in system memory for each device during production. 2052 * @note This voltage depends on user board environment: voltage level 2053 * connected to pin Vref+. 2054 * On devices with small package, the pin Vref+ is not present 2055 * and internally bonded to pin Vdda. 2056 * @note On this STM32 series, calibration data of internal voltage reference 2057 * VrefInt corresponds to a resolution of 12 bits, 2058 * this is the recommended ADC resolution to convert voltage of 2059 * internal voltage reference VrefInt. 2060 * Otherwise, this macro performs the processing to scale 2061 * ADC conversion data to 12 bits. 2062 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) 2063 * of internal voltage reference VrefInt (unit: digital value). 2064 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 2065 * @arg @ref ADC_RESOLUTION_12B 2066 * @arg @ref ADC_RESOLUTION_10B 2067 * @arg @ref ADC_RESOLUTION_8B 2068 * @arg @ref ADC_RESOLUTION_6B 2069 * @retval Analog reference voltage (unit: mV) 2070 */ 2071 #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ 2072 __ADC_RESOLUTION__) \ 2073 __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ 2074 (__ADC_RESOLUTION__)) 2075 2076 /** 2077 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 2078 * from ADC conversion data of internal temperature sensor. 2079 * @note Computation is using temperature sensor calibration values 2080 * stored in system memory for each device during production. 2081 * @note Calculation formula: 2082 * Temperature = ((TS_ADC_DATA - TS_CAL1) 2083 * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) 2084 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP 2085 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 2086 * Avg_Slope = (TS_CAL2 - TS_CAL1) 2087 * / (TS_CAL2_TEMP - TS_CAL1_TEMP) 2088 * TS_CAL1 = equivalent TS_ADC_DATA at temperature 2089 * TEMP_DEGC_CAL1 (calibrated in factory) 2090 * TS_CAL2 = equivalent TS_ADC_DATA at temperature 2091 * TEMP_DEGC_CAL2 (calibrated in factory) 2092 * Caution: Calculation relevancy under reserve that calibration 2093 * parameters are correct (address and data). 2094 * To calculate temperature using temperature sensor 2095 * datasheet typical values (generic values less, therefore 2096 * less accurate than calibrated values), 2097 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). 2098 * @note As calculation input, the analog reference voltage (Vref+) must be 2099 * defined as it impacts the ADC LSB equivalent voltage. 2100 * @note Analog reference voltage (Vref+) must be either known from 2101 * user board environment or can be calculated using ADC measurement 2102 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 2103 * @note On this STM32 series, calibration data of temperature sensor 2104 * corresponds to a resolution of 12 bits, 2105 * this is the recommended ADC resolution to convert voltage of 2106 * temperature sensor. 2107 * Otherwise, this macro performs the processing to scale 2108 * ADC conversion data to 12 bits. 2109 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 2110 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal 2111 * temperature sensor (unit: digital value). 2112 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature 2113 * sensor voltage has been measured. 2114 * This parameter can be one of the following values: 2115 * @arg @ref ADC_RESOLUTION_12B 2116 * @arg @ref ADC_RESOLUTION_10B 2117 * @arg @ref ADC_RESOLUTION_8B 2118 * @arg @ref ADC_RESOLUTION_6B 2119 * @retval Temperature (unit: degree Celsius) 2120 */ 2121 #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ 2122 __TEMPSENSOR_ADC_DATA__,\ 2123 __ADC_RESOLUTION__) \ 2124 __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ 2125 (__TEMPSENSOR_ADC_DATA__),\ 2126 (__ADC_RESOLUTION__)) 2127 2128 /** 2129 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 2130 * from ADC conversion data of internal temperature sensor. 2131 * @note Computation is using temperature sensor typical values 2132 * (refer to device datasheet). 2133 * @note Calculation formula: 2134 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) 2135 * / Avg_Slope + CALx_TEMP 2136 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 2137 * (unit: digital value) 2138 * Avg_Slope = temperature sensor slope 2139 * (unit: uV/Degree Celsius) 2140 * TS_TYP_CALx_VOLT = temperature sensor digital value at 2141 * temperature CALx_TEMP (unit: mV) 2142 * Caution: Calculation relevancy under reserve the temperature sensor 2143 * of the current device has characteristics in line with 2144 * datasheet typical values. 2145 * If temperature sensor calibration values are available on 2146 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), 2147 * temperature calculation will be more accurate using 2148 * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). 2149 * @note As calculation input, the analog reference voltage (Vref+) must be 2150 * defined as it impacts the ADC LSB equivalent voltage. 2151 * @note Analog reference voltage (Vref+) must be either known from 2152 * user board environment or can be calculated using ADC measurement 2153 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 2154 * @note ADC measurement data must correspond to a resolution of 12bits 2155 * (full scale digital value 4095). If not the case, the data must be 2156 * preliminarily rescaled to an equivalent resolution of 12 bits. 2157 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value 2158 (unit: uV/DegCelsius). 2159 * On STM32G4, refer to device datasheet parameter "Avg_Slope". 2160 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at 2161 temperature and Vref+ defined in parameters below) (unit: mV). 2162 * On STM32G4, refer to device datasheet parameter "V30" 2163 (corresponding to TS_CAL1). 2164 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see 2165 parameter above) is corresponding (unit: mV) 2166 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) 2167 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). 2168 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. 2169 * This parameter can be one of the following values: 2170 * @arg @ref ADC_RESOLUTION_12B 2171 * @arg @ref ADC_RESOLUTION_10B 2172 * @arg @ref ADC_RESOLUTION_8B 2173 * @arg @ref ADC_RESOLUTION_6B 2174 * @retval Temperature (unit: degree Celsius) 2175 */ 2176 #define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ 2177 __TEMPSENSOR_TYP_CALX_V__,\ 2178 __TEMPSENSOR_CALX_TEMP__,\ 2179 __VREFANALOG_VOLTAGE__,\ 2180 __TEMPSENSOR_ADC_DATA__,\ 2181 __ADC_RESOLUTION__) \ 2182 __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ 2183 (__TEMPSENSOR_TYP_CALX_V__),\ 2184 (__TEMPSENSOR_CALX_TEMP__),\ 2185 (__VREFANALOG_VOLTAGE__),\ 2186 (__TEMPSENSOR_ADC_DATA__),\ 2187 (__ADC_RESOLUTION__)) 2188 2189 /** 2190 * @} 2191 */ 2192 2193 /** 2194 * @} 2195 */ 2196 2197 /* Include ADC HAL Extended module */ 2198 #include "stm32g4xx_hal_adc_ex.h" 2199 2200 /* Exported functions --------------------------------------------------------*/ 2201 /** @addtogroup ADC_Exported_Functions 2202 * @{ 2203 */ 2204 2205 /** @addtogroup ADC_Exported_Functions_Group1 2206 * @brief Initialization and Configuration functions 2207 * @{ 2208 */ 2209 /* Initialization and de-initialization functions ****************************/ 2210 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); 2211 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 2212 void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); 2213 void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); 2214 2215 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 2216 /* Callbacks Register/UnRegister functions ***********************************/ 2217 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, 2218 pADC_CallbackTypeDef pCallback); 2219 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); 2220 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 2221 /** 2222 * @} 2223 */ 2224 2225 /** @addtogroup ADC_Exported_Functions_Group2 2226 * @brief IO operation functions 2227 * @{ 2228 */ 2229 /* IO operation functions *****************************************************/ 2230 2231 /* Blocking mode: Polling */ 2232 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); 2233 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); 2234 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 2235 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); 2236 2237 /* Non-blocking mode: Interruption */ 2238 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); 2239 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); 2240 2241 /* Non-blocking mode: DMA */ 2242 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 2243 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); 2244 2245 /* ADC retrieve conversion value intended to be used with polling or interruption */ 2246 uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc); 2247 2248 /* ADC sampling control */ 2249 HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc); 2250 HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc); 2251 2252 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ 2253 void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); 2254 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); 2255 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); 2256 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); 2257 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 2258 /** 2259 * @} 2260 */ 2261 2262 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions 2263 * @brief Peripheral Control functions 2264 * @{ 2265 */ 2266 /* Peripheral Control functions ***********************************************/ 2267 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig); 2268 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, 2269 const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig); 2270 2271 /** 2272 * @} 2273 */ 2274 2275 /* Peripheral State functions *************************************************/ 2276 /** @addtogroup ADC_Exported_Functions_Group4 2277 * @{ 2278 */ 2279 uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc); 2280 uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc); 2281 2282 /** 2283 * @} 2284 */ 2285 2286 /** 2287 * @} 2288 */ 2289 2290 /* Private functions ---------------------------------------------------------*/ 2291 /** @addtogroup ADC_Private_Functions ADC Private Functions 2292 * @{ 2293 */ 2294 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup); 2295 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc); 2296 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc); 2297 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); 2298 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); 2299 void ADC_DMAError(DMA_HandleTypeDef *hdma); 2300 2301 /** 2302 * @} 2303 */ 2304 2305 /** 2306 * @} 2307 */ 2308 2309 /** 2310 * @} 2311 */ 2312 2313 #ifdef __cplusplus 2314 } 2315 #endif 2316 2317 2318 #endif /* STM32G4xx_HAL_ADC_H */ 2319
