1 /** 2 ****************************************************************************** 3 * @file stm32f3xx_hal_adc_ex.h 4 * @author MCD Application Team 5 * @brief Header file containing functions prototypes of ADC HAL library. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32F3xx_ADC_EX_H 21 #define __STM32F3xx_ADC_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f3xx_hal_def.h" 29 30 /** @addtogroup STM32F3xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup ADCEx ADCEx 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup ADCEx_Exported_Types ADCEx Exported Types 40 * @{ 41 */ 42 struct __ADC_HandleTypeDef; 43 44 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ 45 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ 46 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ 47 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 48 /** 49 * @brief Structure definition of ADC initialization and regular group 50 * @note Parameters of this structure are shared within 2 scopes: 51 * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, DataAlign, 52 * ScanConvMode, EOCSelection, LowPowerAutoWait. 53 * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv, DMAContinuousRequests, Overrun. 54 * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. 55 * ADC state can be either: 56 * - For all parameters: ADC disabled 57 * - For all parameters except 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on regular group. 58 * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on regular and injected groups. 59 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 60 * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). 61 */ 62 typedef struct 63 { 64 uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from AHB clock or asynchronous clock derived from ADC dedicated PLL 72MHz) and clock prescaler. 65 The clock is common for all the ADCs. 66 This parameter can be a value of @ref ADCEx_ClockPrescaler 67 Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, 68 AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. 69 Note: In case of usage of the ADC dedicated PLL clock, this clock must be preliminarily enabled and prescaler set at RCC top level. 70 Note: This parameter can be modified only if all ADCs of the common ADC group are disabled (for products with several ADCs) */ 71 uint32_t Resolution; /*!< Configures the ADC resolution. 72 This parameter can be a value of @ref ADCEx_Resolution */ 73 uint32_t DataAlign; /*!< Specifies ADC data alignment to right (for resolution 12 bits: MSB on register bit 11 and LSB on register bit 0U) (default setting) 74 or to left (for resolution 12 bits, if offset disabled: MSB on register bit 15 and LSB on register bit 4U, if offset enabled: MSB on register bit 14 and LSB on register bit 3U). 75 See reference manual for alignments with other resolutions. 76 This parameter can be a value of @ref ADCEx_Data_align */ 77 uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. 78 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. 79 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1U). 80 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1U). 81 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). 82 Scan direction is upward: from rank1 to rank 'n'. 83 This parameter can be a value of @ref ADCEx_Scan_mode */ 84 uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. 85 This parameter can be a value of @ref ADCEx_EOCSelection. */ 86 FunctionalState LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: ADC conversions are performed only when necessary. 87 New conversion starts only when the previous conversion (for regular group) or previous sequence (for injected group) has been treated by user software. 88 This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. 89 This parameter can be set to ENABLE or DISABLE. 90 Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA). 91 Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait). 92 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: 93 and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */ 94 FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, 95 after the selected trigger occurred (software start or external trigger). 96 This parameter can be set to ENABLE or DISABLE. */ 97 uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. 98 To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 99 This parameter must be a number between Min_Data = 1 and Max_Data = 16. 100 Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ 101 FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). 102 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 103 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. 104 This parameter can be set to ENABLE or DISABLE. */ 105 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. 106 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. 107 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ 108 uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. 109 If set to ADC_SOFTWARE_START, external triggers are disabled. 110 This parameter can be a value of @ref ADCEx_External_trigger_source_Regular 111 Caution: For devices with several ADCs, external trigger source is common to ADC common group (for example: ADC1&ADC2, ADC3&ADC4, if available) */ 112 uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group. 113 If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. 114 This parameter can be a value of @ref ADCEx_External_trigger_edge_Regular */ 115 FunctionalState DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) 116 or in Continuous mode (DMA transfer unlimited, whatever number of conversions). 117 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. 118 This parameter can be set to ENABLE or DISABLE. 119 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ 120 uint32_t Overrun; /*!< Select the behaviour in case of overrun: data overwritten (default) or preserved. 121 This parameter is for regular group only. 122 This parameter can be a value of @ref ADCEx_Overrun 123 Note: Case of overrun set to data preserved and usage with end on conversion interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved into function HAL_ADC_ConvCpltCallback() (called before end of conversion flags clear). 124 Note: Error reporting in function of conversion mode: 125 - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data overwritten, user can willingly not read the conversion data each time, this is not considered as an erroneous case. 126 - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register, any data missed would be abnormal). */ 127 }ADC_InitTypeDef; 128 129 /** 130 * @brief Structure definition of ADC channel for regular group 131 * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. 132 * ADC state can be either: 133 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff') 134 * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group. 135 * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups. 136 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 137 * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). 138 */ 139 typedef struct 140 { 141 uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. 142 This parameter can be a value of @ref ADCEx_channels 143 Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ 144 uint32_t Rank; /*!< Specifies the rank in the regular group sequencer. 145 This parameter can be a value of @ref ADCEx_regular_rank 146 Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ 147 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 148 Unit: ADC clock cycles 149 Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 150 This parameter can be a value of @ref ADCEx_sampling_times 151 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. 152 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. 153 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 154 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 155 Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 2.2us min). */ 156 uint32_t SingleDiff; /*!< Selection of single-ended or differential input. 157 In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input). 158 Only channel 'i' has to be configured, channel 'i+1' is configured automatically. 159 This parameter must be a value of @ref ADCEx_SingleDifferential 160 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. 161 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. 162 Note: Channels 1 to 14 are available in differential mode. Channels 15U, 16U, 17U, 18 can be used only in single-ended mode. 163 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. 164 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 165 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) */ 166 uint32_t OffsetNumber; /*!< Selects the offset number 167 This parameter can be a value of @ref ADCEx_OffsetNumber 168 Caution: Only one channel is allowed per channel. If another channel was on this offset number, the offset will be changed to the new channel */ 169 uint32_t Offset; /*!< Defines the offset to be subtracted from the raw converted data when convert channels. 170 Offset value must be a positive number. 171 Depending of ADC resolution selected (12U, 10U, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively. 172 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ 173 }ADC_ChannelConfTypeDef; 174 175 /** 176 * @brief Structure definition of ADC injected group and ADC channel for injected group 177 * @note Parameters of this structure are shared within 2 scopes: 178 * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset 179 * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, 180 * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConvEdge, ExternalTrigInjecConv. 181 * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. 182 * ADC state can be either: 183 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff') 184 * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext': ADC enabled without conversion on going on injected group. 185 * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups. 186 * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going on regular and injected groups. 187 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 188 * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). 189 */ 190 typedef struct 191 { 192 uint32_t InjectedChannel; /*!< Configure the ADC injected channel 193 This parameter can be a value of @ref ADCEx_channels 194 Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ 195 uint32_t InjectedRank; /*!< The rank in the regular group sequencer 196 This parameter must be a value of @ref ADCEx_injected_rank 197 Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ 198 uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. 199 Unit: ADC clock cycles 200 Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 201 This parameter can be a value of @ref ADCEx_sampling_times 202 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. 203 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. 204 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 205 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 206 Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 2.2us min). */ 207 uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input. 208 In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input). 209 Only channel 'i' has to be configured, channel 'i+1' is configured automatically. 210 This parameter must be a value of @ref ADCEx_SingleDifferential 211 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. 212 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. 213 Note: Channels 1 to 14 are available in differential mode. Channels 15U, 16U, 17U, 18 can be used only in single-ended mode. 214 Note: When configuring a channel 'i' in differential mode, the channel 'i-1' is not usable separately. 215 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 216 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) */ 217 uint32_t InjectedOffsetNumber; /*!< Selects the offset number 218 This parameter can be a value of @ref ADCEx_OffsetNumber 219 Caution: Only one channel is allowed per offset number. If another channel was on this offset number, the offset will be changed to the new channel. */ 220 uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data. 221 Offset value must be a positive number. 222 Depending of ADC resolution selected (12U, 10U, 8 or 6 bits), 223 this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively. */ 224 uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer. 225 To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 226 This parameter must be a number between Min_Data = 1 and Max_Data = 4. 227 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 228 configure a channel on injected group can impact the configuration of other channels previously set. */ 229 FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). 230 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 231 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. 232 This parameter can be set to ENABLE or DISABLE. 233 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 234 Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. 235 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 236 configure a channel on injected group can impact the configuration of other channels previously set. */ 237 FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one 238 This parameter can be set to ENABLE or DISABLE. 239 Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) 240 Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START) 241 Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. 242 To maintain JAUTO always enabled, DMA must be configured in circular mode. 243 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 244 configure a channel on injected group can impact the configuration of other channels previously set. */ 245 FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. 246 This parameter can be set to ENABLE or DISABLE. 247 If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a 248 new injected context is set when queue is full, error is triggered by interruption and through function 'HAL_ADCEx_InjectedQueueOverflowCallback'. 249 Caution: This feature request that the sequence is fully configured before injected conversion start. 250 Therefore, configure channels with HAL_ADCEx_InjectedConfigChannel() as many times as value of 'InjectedNbrOfConversion' parameter. 251 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 252 configure a channel on injected group can impact the configuration of other channels previously set. 253 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */ 254 uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. 255 If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled. 256 This parameter can be a value of @ref ADCEx_External_trigger_source_Injected 257 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 258 configure a channel on injected group can impact the configuration of other channels previously set. */ 259 uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. 260 This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected. 261 If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. 262 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 263 configure a channel on injected group can impact the configuration of other channels previously set. */ 264 }ADC_InjectionConfTypeDef; 265 266 /** 267 * @brief ADC Injection Configuration 268 */ 269 typedef struct 270 { 271 uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each 272 HAL_ADCEx_InjectedConfigChannel() call to finally initialize 273 JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */ 274 275 uint32_t ChannelCount; /*!< Number of channels in the injected sequence */ 276 }ADC_InjectionConfigTypeDef; 277 278 /** 279 * @brief Structure definition of ADC analog watchdog 280 * @note The setting of these parameters with function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. 281 * ADC state can be either: ADC disabled or ADC enabled without conversion on going on regular and injected groups. 282 */ 283 typedef struct 284 { 285 uint32_t WatchdogNumber; /*!< Selects which ADC analog watchdog to apply to the selected channel. 286 For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode') 287 For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel) 288 This parameter can be a value of @ref ADCEx_analog_watchdog_number. */ 289 uint32_t WatchdogMode; /*!< For Analog Watchdog 1: Configures the ADC analog watchdog mode: single channel/overall group of channels, regular/injected group. 290 For Analog Watchdog 2 and 3: There is no configuration for overall group of channels as AWD1. Set value 'ADC_ANALOGWATCHDOG_NONE' to reset channels group programmed with parameter 'Channel', set any other value to not use this parameter. 291 This parameter can be a value of @ref ADCEx_analog_watchdog_mode. */ 292 uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog. 293 For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel. Only 1 channel can be monitored. 294 For Analog Watchdog 2 and 3: Several channels can be monitored (successive calls of HAL_ADC_AnalogWDGConfig() must be done, one for each channel. 295 Channels group reset can be done by setting WatchdogMode to 'ADC_ANALOGWATCHDOG_NONE'). 296 This parameter can be a value of @ref ADCEx_channels. */ 297 FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode. 298 This parameter can be set to ENABLE or DISABLE */ 299 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. 300 Depending of ADC resolution selected (12U, 10U, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively. 301 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 302 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */ 303 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. 304 Depending of ADC resolution selected (12U, 10U, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively. 305 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 306 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */ 307 }ADC_AnalogWDGConfTypeDef; 308 309 /** 310 * @brief Structure definition of ADC multimode 311 * @note The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group). 312 * ADC state can be either: 313 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'DMAAccessMode') 314 * - For parameter 'DMAAccessMode': ADC enabled without conversion on going on regular group. 315 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 316 * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). 317 */ 318 typedef struct 319 { 320 uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode. 321 This parameter can be a value of @ref ADCEx_Common_mode */ 322 uint32_t DMAAccessMode; /*!< Configures the DMA mode for multi ADC mode: 323 selection whether 2 DMA channels (each ADC use its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master) 324 This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multimode 325 Caution: Limitations with multimode DMA access enabled (1 DMA channel used): In case of dual mode in high speed (more than 5Msps) or high activity of DMA by other peripherals, there is a risk of DMA overrun. 326 Therefore, it is recommended to disable multimode DMA access: each ADC uses its own DMA channel. 327 Refer to device errata sheet for more details. */ 328 uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. 329 This parameter can be a value of @ref ADCEx_delay_between_2_sampling_phases 330 Delay range depends on selected resolution: from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits 331 from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits */ 332 }ADC_MultiModeTypeDef; 333 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ 334 /* STM32F302xC || STM32F303xC || STM32F358xx || */ 335 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ 336 /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 337 338 339 #if defined(STM32F373xC) || defined(STM32F378xx) 340 /** 341 * @brief Structure definition of ADC and regular group initialization 342 * @note Parameters of this structure are shared within 2 scopes: 343 * - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode. 344 * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv. 345 * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. 346 * ADC can be either disabled or enabled without conversion on going on regular group. 347 */ 348 typedef struct 349 { 350 uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0U) (default setting) 351 or to left (if regular group: MSB on register bit 15 and LSB on register bit 4U, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3U). 352 This parameter can be a value of @ref ADCEx_Data_align */ 353 uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. 354 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. 355 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1U). 356 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1U). 357 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). 358 Scan direction is upward: from rank1 to rank 'n'. 359 This parameter can be a value of @ref ADCEx_Scan_mode 360 Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1U) 361 or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the 362 the last conversion of the sequence. All previous conversions would be overwritten by the last one. 363 Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */ 364 FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, 365 after the selected trigger occurred (software start or external trigger). 366 This parameter can be set to ENABLE or DISABLE. */ 367 uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. 368 To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 369 This parameter must be a number between Min_Data = 1 and Max_Data = 16. */ 370 FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). 371 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 372 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. 373 This parameter can be set to ENABLE or DISABLE. */ 374 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. 375 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. 376 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ 377 uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. 378 If set to ADC_SOFTWARE_START, external triggers are disabled. 379 If set to external trigger source, triggering is on event rising edge. 380 This parameter can be a value of @ref ADCEx_External_trigger_source_Regular */ 381 }ADC_InitTypeDef; 382 383 /** 384 * @brief Structure definition of ADC channel for regular group 385 * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. 386 * ADC can be either disabled or enabled without conversion on going on regular group. 387 */ 388 typedef struct 389 { 390 uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. 391 This parameter can be a value of @ref ADCEx_channels 392 Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ 393 uint32_t Rank; /*!< Specifies the rank in the regular group sequencer 394 This parameter can be a value of @ref ADCEx_regular_rank 395 Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ 396 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 397 Unit: ADC clock cycles 398 Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits). 399 This parameter can be a value of @ref ADCEx_sampling_times 400 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. 401 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. 402 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 403 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 404 Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17.1us min). */ 405 }ADC_ChannelConfTypeDef; 406 407 /** 408 * @brief ADC Configuration injected Channel structure definition 409 * @note Parameters of this structure are shared within 2 scopes: 410 * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset 411 * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, 412 * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv. 413 * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. 414 * ADC state can be either: 415 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv') 416 * - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group. 417 */ 418 typedef struct 419 { 420 uint32_t InjectedChannel; /*!< Selection of ADC channel to configure 421 This parameter can be a value of @ref ADCEx_channels 422 Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ 423 uint32_t InjectedRank; /*!< Rank in the injected group sequencer 424 This parameter must be a value of @ref ADCEx_injected_rank 425 Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ 426 uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. 427 Unit: ADC clock cycles 428 Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits). 429 This parameter can be a value of @ref ADCEx_sampling_times 430 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. 431 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. 432 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 433 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 434 Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17.1us min). */ 435 uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only). 436 Offset value must be a positive number. 437 Depending of ADC resolution selected (12U, 10U, 8 or 6 bits), 438 this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively. */ 439 uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer. 440 To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 441 This parameter must be a number between Min_Data = 1 and Max_Data = 4. 442 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 443 configure a channel on injected group can impact the configuration of other channels previously set. */ 444 FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). 445 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 446 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. 447 This parameter can be set to ENABLE or DISABLE. 448 Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. 449 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 450 configure a channel on injected group can impact the configuration of other channels previously set. */ 451 FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one 452 This parameter can be set to ENABLE or DISABLE. 453 Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) 454 Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START) 455 Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. 456 To maintain JAUTO always enabled, DMA must be configured in circular mode. 457 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 458 configure a channel on injected group can impact the configuration of other channels previously set. */ 459 uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. 460 If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled. 461 If set to external trigger source, triggering is on event rising edge. 462 This parameter can be a value of @ref ADCEx_External_trigger_source_Injected 463 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 464 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) 465 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 466 configure a channel on injected group can impact the configuration of other channels previously set. */ 467 }ADC_InjectionConfTypeDef; 468 469 /** 470 * @brief ADC Configuration analog watchdog definition 471 * @note The setting of these parameters with function is conditioned to ADC state. 472 * ADC state can be either disabled or enabled without conversion on going on regular and injected groups. 473 */ 474 typedef struct 475 { 476 uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group. 477 This parameter can be a value of @ref ADCEx_analog_watchdog_mode. */ 478 uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog. 479 This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode) 480 This parameter can be a value of @ref ADCEx_channels. */ 481 FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode. 482 This parameter can be set to ENABLE or DISABLE */ 483 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. 484 This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ 485 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. 486 This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ 487 uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0U */ 488 }ADC_AnalogWDGConfTypeDef; 489 #endif /* STM32F373xC || STM32F378xx */ 490 /** 491 * @} 492 */ 493 494 /* Exported constants --------------------------------------------------------*/ 495 496 /** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants 497 * @{ 498 */ 499 500 /** @defgroup ADCEx_Error_Code ADC Extended Error Code 501 * @{ 502 */ 503 #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ 504 #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error: if problem of clocking, 505 enable/disable, erroneous state */ 506 #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ 507 #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ 508 #define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */ 509 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 510 #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ 511 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 512 /** 513 * @} 514 */ 515 516 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ 517 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ 518 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ 519 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 520 /** @defgroup ADCEx_ClockPrescaler ADC Extended Clock Prescaler 521 * @{ 522 */ 523 #define ADC_CLOCK_ASYNC_DIV1 (0x00000000U) /*!< ADC asynchronous clock derived from ADC dedicated PLL */ 524 525 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ 526 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ 527 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 528 #define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC12_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */ 529 #define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC12_CCR_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2U */ 530 #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC12_CCR_CKMODE) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4U */ 531 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ 532 /* STM32F302xC || STM32F303xC || STM32F358xx || */ 533 /* STM32F303x8 || STM32F334x8 || STM32F328xx */ 534 535 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 536 #define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC1_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */ 537 #define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC1_CCR_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2U */ 538 #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC1_CCR_CKMODE) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4U */ 539 #endif /* STM32F301x8 || STM32F318xx || STM32F302x8 */ 540 541 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || \ 542 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) || \ 543 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ 544 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ) 545 /** 546 * @} 547 */ 548 549 /** @defgroup ADCEx_Resolution ADC Extended Resolution 550 * @{ 551 */ 552 #define ADC_RESOLUTION_12B (0x00000000U) /*!< ADC 12-bit resolution */ 553 #define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR_RES_0) /*!< ADC 10-bit resolution */ 554 #define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR_RES_1) /*!< ADC 8-bit resolution */ 555 #define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR_RES) /*!< ADC 6-bit resolution */ 556 /** 557 * @} 558 */ 559 560 /** @defgroup ADCEx_Data_align ADC Extended Data Alignment 561 * @{ 562 */ 563 #define ADC_DATAALIGN_RIGHT (0x00000000U) 564 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR_ALIGN) 565 /** 566 * @} 567 */ 568 569 /** @defgroup ADCEx_Scan_mode ADC Extended Scan Mode 570 * @{ 571 */ 572 #define ADC_SCAN_DISABLE (0x00000000U) 573 #define ADC_SCAN_ENABLE (0x00000001U) 574 /** 575 * @} 576 */ 577 578 /** @defgroup ADCEx_External_trigger_edge_Regular ADC Extended External trigger enable and polarity selection for regular group 579 * @{ 580 */ 581 #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U) 582 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR_EXTEN_0) 583 #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR_EXTEN_1) 584 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR_EXTEN) 585 /** 586 * @} 587 */ 588 589 /** @defgroup ADCEx_External_trigger_source_Regular ADC Extended External trigger selection for regular group 590 * @{ 591 */ 592 #if defined(STM32F303xE) || defined(STM32F398xx) || \ 593 defined(STM32F303xC) || defined(STM32F358xx) 594 /*!< List of external triggers with generic trigger name, independently of */ 595 /* ADC target (caution: applies to other ADCs sharing the same common group), */ 596 /* sorted by trigger name: */ 597 598 /*!< External triggers of regular group for ADC1&ADC2 only */ 599 #define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1 600 #define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2 601 #define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2 602 #define ADC_EXTERNALTRIGCONV_T3_CC4 ADC1_2_EXTERNALTRIG_T3_CC4 603 #define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4 604 #define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO 605 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11 606 607 /*!< External triggers of regular group for ADC3&ADC4 only */ 608 #define ADC_EXTERNALTRIGCONV_T2_CC1 ADC3_4_EXTERNALTRIG_T2_CC1 609 #define ADC_EXTERNALTRIGCONV_T2_CC3 ADC3_4_EXTERNALTRIG_T2_CC3 610 #define ADC_EXTERNALTRIGCONV_T3_CC1 ADC3_4_EXTERNALTRIG_T3_CC1 611 #define ADC_EXTERNALTRIGCONV_T4_CC1 ADC3_4_EXTERNALTRIG_T4_CC1 612 #define ADC_EXTERNALTRIGCONV_T7_TRGO ADC3_4_EXTERNALTRIG_T7_TRGO 613 #define ADC_EXTERNALTRIGCONV_T8_CC1 ADC3_4_EXTERNALTRIG_T8_CC1 614 #define ADC_EXTERNALTRIGCONV_EXT_IT2 ADC3_4_EXTERNALTRIG_EXT_IT2 615 616 /*!< External triggers of regular group for ADC1&ADC2, ADC3&ADC4 */ 617 /* Note: Triggers affected to group ADC1_2 by default, redirected to group */ 618 /* ADC3_4 by driver when needed. */ 619 #define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_EXTERNALTRIG_T1_CC3 620 #define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO 621 #define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_2_EXTERNALTRIG_T1_TRGO2 622 #define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO 623 #define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO 624 #define ADC_EXTERNALTRIGCONV_T4_TRGO ADC1_2_EXTERNALTRIG_T4_TRGO 625 #define ADC_EXTERNALTRIGCONV_T8_TRGO ADC1_2_EXTERNALTRIG_T8_TRGO 626 #define ADC_EXTERNALTRIGCONV_T8_TRGO2 ADC1_2_EXTERNALTRIG_T8_TRGO2 627 #define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO 628 629 #define ADC_SOFTWARE_START (0x00000001U) 630 631 #if defined(STM32F303xE) || defined(STM32F398xx) 632 /* ADC external triggers specific to device STM303xE: mask to differentiate */ 633 /* standard triggers from specific timer 20U, needed for reallocation of */ 634 /* triggers common to ADC1&2U/ADC3&4 and to avoid mixing with standard */ 635 /* triggers without remap. */ 636 #define ADC_EXTERNALTRIGCONV_T20_MASK 0x1000 637 638 /*!< List of external triggers specific to device STM303xE: using Timer20 */ 639 /* with ADC trigger input remap. */ 640 /* To remap ADC trigger from other timers/ExtLine to timer20: use macro */ 641 /* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below: */ 642 643 /*!< External triggers of regular group for ADC1&ADC2 only, specific to */ 644 /* device STM303xE: : using Timer20 with ADC trigger input remap */ 645 #define ADC_EXTERNALTRIGCONV_T20_CC2 ADC_EXTERNALTRIGCONV_T6_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT13U) */ 646 #define ADC_EXTERNALTRIGCONV_T20_CC3 ADC_EXTERNALTRIGCONV_T3_CC4 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT15U) */ 647 648 /*!< External triggers of regular group for ADC3&ADC4 only, specific to */ 649 /* device STM303xE: : using Timer20 with ADC trigger input remap */ 650 /* None */ 651 652 /*!< External triggers of regular group for ADC1&ADC2, ADC3&ADC4, specific to */ 653 /* device STM303xE: : using Timer20 with ADC trigger input remap */ 654 /* Note: Triggers affected to group ADC1_2 by default, redirected to group */ 655 /* ADC3_4 by driver when needed. */ 656 #define ADC_EXTERNALTRIGCONV_T20_CC1 (ADC_EXTERNALTRIGCONV_T4_CC4 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT5) */ 657 /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_EXT15U) */ 658 #define ADC_EXTERNALTRIGCONV_T20_TRGO (ADC_EXTERNALTRIGCONV_T1_CC3 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT2) */ 659 /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_EXT5) */ 660 #define ADC_EXTERNALTRIGCONV_T20_TRGO2 (ADC_EXTERNALTRIGCONV_T2_CC2 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT3) */ 661 /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_EXT6) */ 662 #endif /* STM32F303xE || STM32F398xx */ 663 664 #endif /* STM32F303xE || STM32F398xx || */ 665 /* STM32F303xC || STM32F358xx */ 666 667 #if defined(STM32F302xE) || \ 668 defined(STM32F302xC) 669 /*!< List of external triggers with generic trigger name, independently of */ 670 /* ADC target (caution: applies to other ADCs sharing the same common group), */ 671 /* sorted by trigger name: */ 672 673 /*!< External triggers of regular group for ADC1&ADC2 */ 674 #define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1 675 #define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2 676 #define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_EXTERNALTRIG_T1_CC3 677 #define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO 678 #define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_2_EXTERNALTRIG_T1_TRGO2 679 #define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2 680 #define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO 681 #define ADC_EXTERNALTRIGCONV_T3_CC4 ADC1_2_EXTERNALTRIG_T3_CC4 682 #define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO 683 #define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4 684 #define ADC_EXTERNALTRIGCONV_T4_TRGO ADC1_2_EXTERNALTRIG_T4_TRGO 685 #define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO 686 #define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO 687 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11 688 #define ADC_SOFTWARE_START (0x00000001U) 689 690 #if defined(STM32F302xE) 691 /* ADC external triggers specific to device STM302xE: mask to differentiate */ 692 /* standard triggers from specific timer 20U, needed for reallocation of */ 693 /* triggers common to ADC1&2 and to avoid mixing with standard */ 694 /* triggers without remap. */ 695 #define ADC_EXTERNALTRIGCONV_T20_MASK 0x1000 696 697 /*!< List of external triggers specific to device STM302xE: using Timer20 */ 698 /* with ADC trigger input remap. */ 699 /* To remap ADC trigger from other timers/ExtLine to timer20: use macro */ 700 /* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below: */ 701 702 /*!< External triggers of regular group for ADC1&ADC2 only, specific to */ 703 /* device STM302xE: : using Timer20 with ADC trigger input remap */ 704 #define ADC_EXTERNALTRIGCONV_T20_CC2 ADC_EXTERNALTRIGCONV_T6_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT13U) */ 705 #define ADC_EXTERNALTRIGCONV_T20_CC3 ADC_EXTERNALTRIGCONV_T3_CC4 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT15U) */ 706 #endif /* STM32F302xE */ 707 708 #endif /* STM32F302xE || */ 709 /* STM32F302xC */ 710 711 #if defined(STM32F303x8) || defined(STM32F328xx) 712 /*!< List of external triggers with generic trigger name, independently of */ 713 /* ADC target (caution: applies to other ADCs sharing the same common group), */ 714 /* sorted by trigger name: */ 715 716 /*!< External triggers of regular group for ADC1&ADC2 */ 717 #define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1 718 #define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2 719 #define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_EXTERNALTRIG_T1_CC3 720 #define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO 721 #define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_2_EXTERNALTRIG_T1_TRGO2 722 #define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2 723 #define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO 724 #define ADC_EXTERNALTRIGCONV_T3_CC4 ADC1_2_EXTERNALTRIG_T3_CC4 725 #define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO 726 #define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4 727 #define ADC_EXTERNALTRIGCONV_T4_TRGO ADC1_2_EXTERNALTRIG_T4_TRGO 728 #define ADC_EXTERNALTRIGCONV_T8_TRGO ADC1_2_EXTERNALTRIG_T8_TRGO 729 #define ADC_EXTERNALTRIGCONV_T8_TRGO2 ADC1_2_EXTERNALTRIG_T8_TRGO2 730 #define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO 731 #define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO 732 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11 733 #define ADC_SOFTWARE_START (0x00000001U) 734 735 #endif /* STM32F303x8 || STM32F328xx */ 736 737 #if defined(STM32F334x8) 738 /*!< List of external triggers with generic trigger name, independently of */ 739 /* ADC target (caution: applies to other ADCs sharing the same common group), */ 740 /* sorted by trigger name: */ 741 742 /*!< External triggers of regular group for ADC1&ADC2 */ 743 #define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1 744 #define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2 745 #define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_EXTERNALTRIG_T1_CC3 746 #define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO 747 #define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_2_EXTERNALTRIG_T1_TRGO2 748 #define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2 749 #define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO 750 #define ADC_EXTERNALTRIGCONV_T3_CC4 ADC1_2_EXTERNALTRIG_T3_CC4 751 #define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO 752 #define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO 753 #define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO 754 #define ADC_EXTERNALTRIGCONVHRTIM_TRG1 ADC1_2_EXTERNALTRIG_HRTIM_TRG1 755 #define ADC_EXTERNALTRIGCONVHRTIM_TRG3 ADC1_2_EXTERNALTRIG_HRTIM_TRG3 756 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11 757 #define ADC_SOFTWARE_START (0x00000001U) 758 #endif /* STM32F334x8 */ 759 760 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 761 /* List of external triggers with generic trigger name, sorted by trigger */ 762 /* name: */ 763 764 /* External triggers of regular group for ADC1 */ 765 #define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_EXTERNALTRIG_T1_CC1 766 #define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_EXTERNALTRIG_T1_CC2 767 #define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_EXTERNALTRIG_T1_CC3 768 #define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_EXTERNALTRIG_T2_CC2 769 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_EXTERNALTRIG_EXT_IT11 770 #define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_EXTERNALTRIG_T1_TRGO 771 #define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_EXTERNALTRIG_T1_TRGO2 772 #define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_EXTERNALTRIG_T2_TRGO 773 #define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_EXTERNALTRIG_T6_TRGO 774 #define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_EXTERNALTRIG_T15_TRGO 775 #define ADC_SOFTWARE_START (0x00000001U) 776 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 777 /** 778 * @} 779 */ 780 781 /** @defgroup ADCEx_EOCSelection ADC Extended End of Regular Sequence/Conversion 782 * @{ 783 */ 784 #define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC) 785 #define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS) 786 /** 787 * @} 788 */ 789 790 /** @defgroup ADCEx_Overrun ADC Extended overrun 791 * @{ 792 */ 793 #define ADC_OVR_DATA_OVERWRITTEN (0x00000000U) /*!< Default setting, to be used for compatibility with other STM32 devices */ 794 #define ADC_OVR_DATA_PRESERVED (0x00000001U) 795 /** 796 * @} 797 */ 798 799 /** @defgroup ADCEx_channels ADC Extended Channels 800 * @{ 801 */ 802 /* Note: Depending on devices, some channels may not be available on package */ 803 /* pins. Refer to device datasheet for channels availability. */ 804 #define ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ10_0)) 805 #define ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ10_1)) 806 #define ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0)) 807 #define ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ10_2)) 808 #define ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0)) 809 #define ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1)) 810 #define ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0)) 811 #define ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ10_3)) 812 #define ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_0)) 813 #define ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1)) 814 #define ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0)) 815 #define ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2)) 816 #define ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0)) 817 #define ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1)) 818 #define ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0)) 819 #define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ10_4)) 820 #define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_0)) 821 #define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_1)) 822 823 /* Note: Vopamp1, TempSensor and Vbat internal channels available on ADC1 only */ 824 #define ADC_CHANNEL_VOPAMP1 ADC_CHANNEL_15 825 #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 826 #define ADC_CHANNEL_VBAT ADC_CHANNEL_17 827 828 /* Note: Vopamp2/3U/4 internal channels available on ADC2/3U/4 respectively */ 829 #define ADC_CHANNEL_VOPAMP2 ADC_CHANNEL_17 830 #define ADC_CHANNEL_VOPAMP3 ADC_CHANNEL_17 831 #define ADC_CHANNEL_VOPAMP4 ADC_CHANNEL_17 832 833 /* Note: VrefInt internal channels available on all ADCs, but only */ 834 /* one ADC is allowed to be connected to VrefInt at the same time. */ 835 #define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_18) 836 /** 837 * @} 838 */ 839 840 /** @defgroup ADCEx_sampling_times ADC Extended Sampling Times 841 * @{ 842 */ 843 #define ADC_SAMPLETIME_1CYCLE_5 (0x00000000U) /*!< Sampling time 1.5 ADC clock cycle */ 844 #define ADC_SAMPLETIME_2CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_0) /*!< Sampling time 2.5 ADC clock cycles */ 845 #define ADC_SAMPLETIME_4CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_1) /*!< Sampling time 4.5 ADC clock cycles */ 846 #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 7.5 ADC clock cycles */ 847 #define ADC_SAMPLETIME_19CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_2) /*!< Sampling time 19.5 ADC clock cycles */ 848 #define ADC_SAMPLETIME_61CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 61.5 ADC clock cycles */ 849 #define ADC_SAMPLETIME_181CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1)) /*!< Sampling time 181.5 ADC clock cycles */ 850 #define ADC_SAMPLETIME_601CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10) /*!< Sampling time 601.5 ADC clock cycles */ 851 /** 852 * @} 853 */ 854 855 /** @defgroup ADCEx_SingleDifferential ADC Extended Single-ended/Differential input mode 856 * @{ 857 */ 858 #define ADC_SINGLE_ENDED (0x00000000U) 859 #define ADC_DIFFERENTIAL_ENDED (0x00000001U) 860 /** 861 * @} 862 */ 863 864 /** @defgroup ADCEx_OffsetNumber ADC Extended Offset Number 865 * @{ 866 */ 867 #define ADC_OFFSET_NONE (0x00U) 868 #define ADC_OFFSET_1 (0x01U) 869 #define ADC_OFFSET_2 (0x02U) 870 #define ADC_OFFSET_3 (0x03U) 871 #define ADC_OFFSET_4 (0x04U) 872 /** 873 * @} 874 */ 875 876 /** @defgroup ADCEx_regular_rank ADC Extended rank into regular group 877 * @{ 878 */ 879 #define ADC_REGULAR_RANK_1 (0x00000001U) 880 #define ADC_REGULAR_RANK_2 (0x00000002U) 881 #define ADC_REGULAR_RANK_3 (0x00000003U) 882 #define ADC_REGULAR_RANK_4 (0x00000004U) 883 #define ADC_REGULAR_RANK_5 (0x00000005U) 884 #define ADC_REGULAR_RANK_6 (0x00000006U) 885 #define ADC_REGULAR_RANK_7 (0x00000007U) 886 #define ADC_REGULAR_RANK_8 (0x00000008U) 887 #define ADC_REGULAR_RANK_9 (0x00000009U) 888 #define ADC_REGULAR_RANK_10 (0x0000000AU) 889 #define ADC_REGULAR_RANK_11 (0x0000000BU) 890 #define ADC_REGULAR_RANK_12 (0x0000000CU) 891 #define ADC_REGULAR_RANK_13 (0x0000000DU) 892 #define ADC_REGULAR_RANK_14 (0x0000000EU) 893 #define ADC_REGULAR_RANK_15 (0x0000000FU) 894 #define ADC_REGULAR_RANK_16 (0x00000010U) 895 /** 896 * @} 897 */ 898 899 /** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank 900 * @{ 901 */ 902 #define ADC_INJECTED_RANK_1 (0x00000001U) 903 #define ADC_INJECTED_RANK_2 (0x00000002U) 904 #define ADC_INJECTED_RANK_3 (0x00000003U) 905 #define ADC_INJECTED_RANK_4 (0x00000004U) 906 /** 907 * @} 908 */ 909 910 /** @defgroup ADCEx_External_trigger_edge_Injected External Trigger Edge of Injected Group 911 * @{ 912 */ 913 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000U) 914 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_JSQR_JEXTEN_0) 915 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_JSQR_JEXTEN_1) 916 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_JSQR_JEXTEN) 917 /** 918 * @} 919 */ 920 921 /** @defgroup ADCEx_External_trigger_source_Injected External Trigger Source of Injected Group 922 * @{ 923 */ 924 #if defined(STM32F303xE) || defined(STM32F398xx) || \ 925 defined(STM32F303xC) || defined(STM32F358xx) 926 /* List of external triggers with generic trigger name, independently of ADC */ 927 /* target (caution: applies to other ADCs sharing the same common group), */ 928 /* sorted by trigger name: */ 929 930 /* External triggers of injected group for ADC1&ADC2 only */ 931 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1 932 #define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ADC1_2_EXTERNALTRIGINJEC_T3_CC1 933 #define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ADC1_2_EXTERNALTRIGINJEC_T3_CC3 934 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4 935 #define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_2_EXTERNALTRIGINJEC_T6_TRGO 936 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 937 938 /* External triggers of injected group for ADC3&ADC4 only */ 939 #define ADC_EXTERNALTRIGINJECCONV_T1_CC3 ADC3_4_EXTERNALTRIGINJEC_T1_CC3 940 #define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ADC3_4_EXTERNALTRIGINJEC_T4_CC3 941 #define ADC_EXTERNALTRIGINJECCONV_T4_CC4 ADC3_4_EXTERNALTRIGINJEC_T4_CC4 942 #define ADC_EXTERNALTRIGINJECCONV_T7_TRGO ADC3_4_EXTERNALTRIGINJEC_T7_TRGO 943 #define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ADC3_4_EXTERNALTRIGINJEC_T8_CC2 944 945 /* External triggers of injected group for ADC1&ADC2, ADC3&ADC4 */ 946 /* Note: Triggers affected to group ADC1_2 by default, redirected to group */ 947 /* ADC3_4 by driver when needed. */ 948 #define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_EXTERNALTRIGINJEC_T1_CC4 949 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_EXTERNALTRIGINJEC_T1_TRGO 950 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 951 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO 952 #define ADC_EXTERNALTRIGINJECCONV_T3_TRGO ADC1_2_EXTERNALTRIGINJEC_T3_TRGO 953 #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO 954 #define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T8_CC4 955 #define ADC_EXTERNALTRIGINJECCONV_T8_TRGO ADC1_2_EXTERNALTRIGINJEC_T8_TRGO 956 #define ADC_EXTERNALTRIGINJECCONV_T8_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2 957 #define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO 958 959 #define ADC_INJECTED_SOFTWARE_START (0x00000001U) 960 961 #if defined(STM32F303xE) || defined(STM32F398xx) 962 /*!< List of external triggers specific to device STM303xE: using Timer20 */ 963 /* with ADC trigger input remap. */ 964 /* To remap ADC trigger from other timers/ExtLine to timer20: use macro */ 965 /* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below: */ 966 967 /*!< External triggers of injected group for ADC1&ADC2 only, specific to */ 968 /* device STM303xE: : using Timer20 with ADC trigger input remap */ 969 #define ADC_EXTERNALTRIGINJECCONV_T20_CC4 ADC_EXTERNALTRIGINJECCONV_T3_CC1 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT13U) */ 970 971 /*!< External triggers of injected group for ADC3&ADC4 only, specific to */ 972 /* device STM303xE: : using Timer20 with ADC trigger input remap */ 973 #define ADC_EXTERNALTRIGINJECCONV_T20_CC2 ADC_EXTERNALTRIGINJECCONV_T7_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT14U) */ 974 975 /*!< External triggers of regular group for ADC1&ADC2, ADC3&ADC4, specific to */ 976 /* device STM303xE: : using Timer20 with ADC trigger input remap */ 977 /* Note: Triggers affected to group ADC1_2 by default, redirected to group */ 978 /* ADC3_4 by driver when needed. */ 979 #define ADC_EXTERNALTRIGINJECCONV_T20_TRGO (ADC_EXTERNALTRIGINJECCONV_T2_CC1 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT3) */ 980 /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT5) */ 981 #define ADC_EXTERNALTRIGINJECCONV_T20_TRGO2 (ADC_EXTERNALTRIGINJECCONV_EXT_IT15 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT6) */ 982 /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT11U) */ 983 #endif /* STM32F303xE || STM32F398xx */ 984 985 #if defined(STM32F303xC) || defined(STM32F358xx) 986 #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ 987 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \ 988 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ 989 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \ 990 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ 991 \ 992 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \ 993 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC4) || \ 994 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \ 995 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \ 996 \ 997 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ 998 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ 999 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \ 1000 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ 1001 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \ 1002 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \ 1003 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ 1004 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \ 1005 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \ 1006 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \ 1007 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \ 1008 \ 1009 ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) ) 1010 #endif /* STM32F303xC || STM32F358xx */ 1011 1012 #if defined(STM32F303xE) || defined(STM32F398xx) 1013 #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ 1014 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \ 1015 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ 1016 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \ 1017 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ 1018 \ 1019 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \ 1020 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC4) || \ 1021 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \ 1022 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \ 1023 \ 1024 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ 1025 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ 1026 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \ 1027 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ 1028 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \ 1029 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \ 1030 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ 1031 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \ 1032 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \ 1033 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \ 1034 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \ 1035 \ 1036 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC4) || \ 1037 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC2) || \ 1038 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO) || \ 1039 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO2) || \ 1040 \ 1041 ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) ) 1042 #endif /* STM32F303xE || STM32F398xx */ 1043 1044 #endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */ 1045 1046 #if defined(STM32F302xE) || \ 1047 defined(STM32F302xC) 1048 /*!< List of external triggers with generic trigger name, independently of */ 1049 /* ADC target (caution: applies to other ADCs sharing the same common group), */ 1050 /* sorted by trigger name: */ 1051 1052 /* External triggers of injected group for ADC1&ADC2 */ 1053 #define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_EXTERNALTRIGINJEC_T1_CC4 1054 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_EXTERNALTRIGINJEC_T1_TRGO 1055 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 1056 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1 1057 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO 1058 #define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ADC1_2_EXTERNALTRIGINJEC_T3_CC1 1059 #define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ADC1_2_EXTERNALTRIGINJEC_T3_CC3 1060 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4 1061 #define ADC_EXTERNALTRIGINJECCONV_T3_TRGO ADC1_2_EXTERNALTRIGINJEC_T3_TRGO 1062 #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO 1063 #define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_2_EXTERNALTRIGINJEC_T6_TRGO 1064 #define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO 1065 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 1066 1067 #define ADC_INJECTED_SOFTWARE_START (0x00000001U) 1068 1069 #if defined(STM32F302xE) 1070 /*!< List of external triggers specific to device STM302xE: using Timer20 */ 1071 /* with ADC trigger input remap. */ 1072 /* To remap ADC trigger from other timers/ExtLine to timer20: use macro */ 1073 /* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below: */ 1074 1075 /*!< External triggers of injected group for ADC1&ADC2 only, specific to */ 1076 /* device STM302xE: : using Timer20 with ADC trigger input remap */ 1077 #define ADC_EXTERNALTRIGINJECCONV_T20_CC4 ADC_EXTERNALTRIGINJECCONV_T3_CC1 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT13U) */ 1078 #define ADC_EXTERNALTRIGINJECCONV_T20_TRGO (ADC_EXTERNALTRIGINJECCONV_T2_CC1 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT3) */ 1079 #define ADC_EXTERNALTRIGINJECCONV_T20_TRGO2 (ADC_EXTERNALTRIGINJECCONV_EXT_IT15 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT6) */ 1080 #endif /* STM32F302xE */ 1081 1082 #endif /* STM32F302xE || */ 1083 /* STM32F302xC */ 1084 1085 #if defined(STM32F303x8) || defined(STM32F328xx) 1086 /*!< List of external triggers with generic trigger name, independently of */ 1087 /* ADC target (caution: applies to other ADCs sharing the same common group), */ 1088 /* sorted by trigger name: */ 1089 1090 /* External triggers of injected group for ADC1&ADC2 */ 1091 #define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_EXTERNALTRIGINJEC_T1_CC4 1092 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_EXTERNALTRIGINJEC_T1_TRGO 1093 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 1094 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1 1095 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO 1096 #define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ADC1_2_EXTERNALTRIGINJEC_T3_CC1 1097 #define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ADC1_2_EXTERNALTRIGINJEC_T3_CC3 1098 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4 1099 #define ADC_EXTERNALTRIGINJECCONV_T3_TRGO ADC1_2_EXTERNALTRIGINJEC_T3_TRGO 1100 #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO 1101 #define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_2_EXTERNALTRIGINJEC_T6_TRGO 1102 #define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T8_CC4 1103 #define ADC_EXTERNALTRIGINJECCONV_T8_TRGO ADC1_2_EXTERNALTRIGINJEC_T8_TRGO 1104 #define ADC_EXTERNALTRIGINJECCONV_T8_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2 1105 #define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO 1106 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 1107 1108 #define ADC_INJECTED_SOFTWARE_START (0x00000001U) 1109 #endif /* STM32F303x8 || STM32F328xx */ 1110 1111 #if defined(STM32F334x8) 1112 /*!< List of external triggers with generic trigger name, independently of */ 1113 /* ADC target (caution: applies to other ADCs sharing the same common group), */ 1114 /* sorted by trigger name: */ 1115 1116 /* External triggers of injected group for ADC1&ADC2 */ 1117 #define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_EXTERNALTRIGINJEC_T1_CC4 1118 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_EXTERNALTRIGINJEC_T1_TRGO 1119 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 1120 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1 1121 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO 1122 #define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ADC1_2_EXTERNALTRIGINJEC_T3_CC1 1123 #define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ADC1_2_EXTERNALTRIGINJEC_T3_CC3 1124 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4 1125 #define ADC_EXTERNALTRIGINJECCONV_T3_TRGO ADC1_2_EXTERNALTRIGINJEC_T3_TRGO 1126 #define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_2_EXTERNALTRIGINJEC_T6_TRGO 1127 #define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO 1128 #define ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG2 ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG2 1129 #define ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG4 ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG4 1130 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 1131 1132 #define ADC_INJECTED_SOFTWARE_START (0x00000001U) 1133 #endif /* STM32F334x8 */ 1134 1135 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 1136 /* List of external triggers with generic trigger name, sorted by trigger */ 1137 /* name: */ 1138 1139 /* External triggers of injected group for ADC1 */ 1140 #define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_EXTERNALTRIGINJEC_T1_CC4 1141 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_EXTERNALTRIGINJEC_T1_TRGO 1142 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_EXTERNALTRIGINJEC_T1_TRGO2 1143 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_EXTERNALTRIGINJEC_T2_CC1 1144 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_EXTERNALTRIGINJEC_T2_TRGO 1145 #define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_EXTERNALTRIGINJEC_T6_TRGO 1146 #define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_EXTERNALTRIGINJEC_T15_TRGO 1147 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_EXTERNALTRIGINJEC_EXT_IT15 1148 1149 #define ADC_INJECTED_SOFTWARE_START (0x00000001U) 1150 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 1151 /** 1152 * @} 1153 */ 1154 1155 1156 /** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode 1157 * @{ 1158 */ 1159 #define ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000U)) 1160 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC12_CCR_MULTI_0)) 1161 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)(ADC12_CCR_MULTI_1)) 1162 #define ADC_DUALMODE_REGINTERL_INJECSIMULT ((uint32_t)(ADC12_CCR_MULTI_1 | ADC12_CCR_MULTI_0)) 1163 #define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC12_CCR_MULTI_2 | ADC12_CCR_MULTI_0)) 1164 #define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC12_CCR_MULTI_2 | ADC12_CCR_MULTI_1)) 1165 #define ADC_DUALMODE_INTERL ((uint32_t)(ADC12_CCR_MULTI_2 | ADC12_CCR_MULTI_1 | ADC12_CCR_MULTI_0)) 1166 #define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC12_CCR_MULTI_3 | ADC12_CCR_MULTI_0)) 1167 /** 1168 * @} 1169 */ 1170 1171 1172 /** @defgroup ADCEx_Direct_memory_access_mode_for_multimode ADC Extended DMA Mode for Dual ADC Mode 1173 * @{ 1174 */ 1175 #define ADC_DMAACCESSMODE_DISABLED (0x00000000U) /*!< DMA multimode disabled: each ADC will use its own DMA channel */ 1176 #define ADC_DMAACCESSMODE_12_10_BITS ((uint32_t)ADC12_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */ 1177 #define ADC_DMAACCESSMODE_8_6_BITS ((uint32_t)ADC12_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */ 1178 /** 1179 * @} 1180 */ 1181 1182 /** @defgroup ADCEx_delay_between_2_sampling_phases ADC Extended Delay Between 2 Sampling Phases 1183 * @{ 1184 */ 1185 #define ADC_TWOSAMPLINGDELAY_1CYCLE ((uint32_t)(0x00000000U)) 1186 #define ADC_TWOSAMPLINGDELAY_2CYCLES ((uint32_t)(ADC12_CCR_DELAY_0)) 1187 #define ADC_TWOSAMPLINGDELAY_3CYCLES ((uint32_t)(ADC12_CCR_DELAY_1)) 1188 #define ADC_TWOSAMPLINGDELAY_4CYCLES ((uint32_t)(ADC12_CCR_DELAY_1 | ADC12_CCR_DELAY_0)) 1189 #define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)(ADC12_CCR_DELAY_2)) 1190 #define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)(ADC12_CCR_DELAY_2 | ADC12_CCR_DELAY_0)) 1191 #define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)(ADC12_CCR_DELAY_2 | ADC12_CCR_DELAY_1)) 1192 #define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC12_CCR_DELAY_2 | ADC12_CCR_DELAY_1 | ADC12_CCR_DELAY_0)) 1193 #define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)(ADC12_CCR_DELAY_3)) 1194 #define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC12_CCR_DELAY_3 | ADC12_CCR_DELAY_0)) 1195 #define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC12_CCR_DELAY_3 | ADC12_CCR_DELAY_1)) 1196 #define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC12_CCR_DELAY_3 | ADC12_CCR_DELAY_1 | ADC12_CCR_DELAY_0)) 1197 /** 1198 * @} 1199 */ 1200 1201 /** @defgroup ADCEx_analog_watchdog_number ADC Extended Analog Watchdog Selection 1202 * @{ 1203 */ 1204 #define ADC_ANALOGWATCHDOG_1 (0x00000001U) 1205 #define ADC_ANALOGWATCHDOG_2 (0x00000002U) 1206 #define ADC_ANALOGWATCHDOG_3 (0x00000003U) 1207 /** 1208 * @} 1209 */ 1210 1211 /** @defgroup ADCEx_analog_watchdog_mode ADC Extended Analog Watchdog Mode 1212 * @{ 1213 */ 1214 #define ADC_ANALOGWATCHDOG_NONE ( 0x00000000U) 1215 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN)) 1216 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN)) 1217 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)) 1218 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR_AWD1EN) 1219 #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CFGR_JAWD1EN) 1220 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)) 1221 /** 1222 * @} 1223 */ 1224 1225 /** @defgroup ADC_conversion_group ADC Conversion Group 1226 * @{ 1227 */ 1228 #define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS)) 1229 #define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC | ADC_FLAG_JEOS)) 1230 #define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS)) 1231 1232 /** 1233 * @} 1234 */ 1235 1236 /** @defgroup ADCEx_Event_type ADC Extended Event Type 1237 * @{ 1238 */ 1239 #define ADC_AWD1_EVENT ((uint32_t)ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices) */ 1240 #define ADC_AWD2_EVENT ((uint32_t)ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families) */ 1241 #define ADC_AWD3_EVENT ((uint32_t)ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families) */ 1242 #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */ 1243 #define ADC_JQOVF_EVENT ((uint32_t)ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */ 1244 1245 #define ADC_AWD_EVENT ADC_AWD1_EVENT /* ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having only 1 analog watchdog */ 1246 /** 1247 * @} 1248 */ 1249 1250 /** @defgroup ADCEx_interrupts_definition ADC Extended Interrupts Definition 1251 * @{ 1252 */ 1253 #define ADC_IT_RDY ADC_IER_RDY /*!< ADC Ready (ADRDY) interrupt source */ 1254 #define ADC_IT_EOSMP ADC_IER_EOSMP /*!< ADC End of Sampling interrupt source */ 1255 #define ADC_IT_EOC ADC_IER_EOC /*!< ADC End of Regular Conversion interrupt source */ 1256 #define ADC_IT_EOS ADC_IER_EOS /*!< ADC End of Regular sequence of Conversions interrupt source */ 1257 #define ADC_IT_OVR ADC_IER_OVR /*!< ADC overrun interrupt source */ 1258 #define ADC_IT_JEOC ADC_IER_JEOC /*!< ADC End of Injected Conversion interrupt source */ 1259 #define ADC_IT_JEOS ADC_IER_JEOS /*!< ADC End of Injected sequence of Conversions interrupt source */ 1260 #define ADC_IT_AWD1 ADC_IER_AWD1 /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog, present on all STM32 devices) */ 1261 #define ADC_IT_AWD2 ADC_IER_AWD2 /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog, present only on STM32F3 devices) */ 1262 #define ADC_IT_AWD3 ADC_IER_AWD3 /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog, present only on STM32F3 devices) */ 1263 #define ADC_IT_JQOVF ADC_IER_JQOVF /*!< ADC Injected Context Queue Overflow interrupt source */ 1264 1265 #define ADC_IT_AWD ADC_IT_AWD1 /* ADC Analog watchdog 1 interrupt source: Alternate naming for compatibility with other STM32 devices having only 1 analog watchdog */ 1266 /** 1267 * @} 1268 */ 1269 1270 /** @defgroup ADCEx_flags_definition ADC Extended Flags Definition 1271 * @{ 1272 */ 1273 #define ADC_FLAG_RDY ADC_ISR_ADRD /*!< ADC Ready (ADRDY) flag */ 1274 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ 1275 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ 1276 #define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ 1277 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ 1278 #define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */ 1279 #define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */ 1280 #define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog, present on all STM32 devices) */ 1281 #define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog, present only on STM32F3 devices) */ 1282 #define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog, present only on STM32F3 devices) */ 1283 #define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */ 1284 1285 #define ADC_FLAG_AWD ADC_FLAG_AWD1 /* ADC Analog watchdog 1 flag: Alternate naming for compatibility with other STM32 devices having only 1 analog watchdog */ 1286 /** 1287 * @} 1288 */ 1289 1290 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ 1291 /* STM32F302xC || STM32F303xC || STM32F358xx || */ 1292 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ 1293 /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 1294 1295 1296 #if defined(STM32F373xC) || defined(STM32F378xx) 1297 /** @defgroup ADCEx_Data_align ADC Extended Data Alignment 1298 * @{ 1299 */ 1300 #define ADC_DATAALIGN_RIGHT (0x00000000U) 1301 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) 1302 /** 1303 * @} 1304 */ 1305 1306 /** @defgroup ADCEx_Scan_mode ADC Extended Scan Mode 1307 * @{ 1308 */ 1309 #define ADC_SCAN_DISABLE (0x00000000U) 1310 #define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN) 1311 /** 1312 * @} 1313 */ 1314 1315 /** @defgroup ADCEx_External_trigger_edge_Regular ADC Extended External trigger enable for regular group 1316 * @{ 1317 */ 1318 #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U) 1319 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG) 1320 /** 1321 * @} 1322 */ 1323 1324 /** @defgroup ADCEx_External_trigger_source_Regular ADC Extended External trigger selection for regular group 1325 * @{ 1326 */ 1327 /* List of external triggers with generic trigger name, sorted by trigger */ 1328 /* name: */ 1329 1330 /* External triggers of regular group for ADC1 */ 1331 #define ADC_EXTERNALTRIGCONV_T2_CC2 ADC_EXTERNALTRIG_T2_CC2 1332 #define ADC_EXTERNALTRIGCONV_T3_TRGO ADC_EXTERNALTRIG_T3_TRGO 1333 #define ADC_EXTERNALTRIGCONV_T4_CC4 ADC_EXTERNALTRIG_T4_CC4 1334 #define ADC_EXTERNALTRIGCONV_T19_TRGO ADC_EXTERNALTRIG_T19_TRGO 1335 #define ADC_EXTERNALTRIGCONV_T19_CC3 ADC_EXTERNALTRIG_T19_CC3 1336 #define ADC_EXTERNALTRIGCONV_T19_CC4 ADC_EXTERNALTRIG_T19_CC4 1337 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC_EXTERNALTRIG_EXT_IT11 1338 #define ADC_SOFTWARE_START ADC_SWSTART 1339 /** 1340 * @} 1341 */ 1342 1343 /** @defgroup ADCEx_channels ADC Extended Channels 1344 * @{ 1345 */ 1346 /* Note: Depending on devices, some channels may not be available on package */ 1347 /* pins. Refer to device datasheet for channels availability. */ 1348 #define ADC_CHANNEL_0 (0x00000000U) 1349 #define ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ1_0)) 1350 #define ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ1_1)) 1351 #define ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) 1352 #define ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ1_2)) 1353 #define ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0)) 1354 #define ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1)) 1355 #define ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) 1356 #define ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ1_3)) 1357 #define ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0)) 1358 #define ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1)) 1359 #define ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) 1360 #define ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2)) 1361 #define ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0)) 1362 #define ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1)) 1363 #define ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) 1364 #define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4)) 1365 #define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0)) 1366 #define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_1)) 1367 1368 #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 1369 #define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 1370 #define ADC_CHANNEL_VBAT ADC_CHANNEL_18 1371 /** 1372 * @} 1373 */ 1374 1375 /** @defgroup ADCEx_sampling_times ADC Extended Sampling Times 1376 * @{ 1377 */ 1378 #define ADC_SAMPLETIME_1CYCLE_5 (0x00000000U) /*!< Sampling time 1.5 ADC clock cycle */ 1379 #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_0) /*!< Sampling time 7.5 ADC clock cycles */ 1380 #define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_1) /*!< Sampling time 13.5 ADC clock cycles */ 1381 #define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 28.5 ADC clock cycles */ 1382 #define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_2) /*!< Sampling time 41.5 ADC clock cycles */ 1383 #define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 55.5 ADC clock cycles */ 1384 #define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1)) /*!< Sampling time 71.5 ADC clock cycles */ 1385 #define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0) /*!< Sampling time 239.5 ADC clock cycles */ 1386 /** 1387 * @} 1388 */ 1389 1390 /** @defgroup ADCEx_regular_rank ADC Extended rank into regular group 1391 * @{ 1392 */ 1393 #define ADC_REGULAR_RANK_1 (0x00000001U) 1394 #define ADC_REGULAR_RANK_2 (0x00000002U) 1395 #define ADC_REGULAR_RANK_3 (0x00000003U) 1396 #define ADC_REGULAR_RANK_4 (0x00000004U) 1397 #define ADC_REGULAR_RANK_5 (0x00000005U) 1398 #define ADC_REGULAR_RANK_6 (0x00000006U) 1399 #define ADC_REGULAR_RANK_7 (0x00000007U) 1400 #define ADC_REGULAR_RANK_8 (0x00000008U) 1401 #define ADC_REGULAR_RANK_9 (0x00000009U) 1402 #define ADC_REGULAR_RANK_10 (0x0000000AU) 1403 #define ADC_REGULAR_RANK_11 (0x0000000BU) 1404 #define ADC_REGULAR_RANK_12 (0x0000000CU) 1405 #define ADC_REGULAR_RANK_13 (0x0000000DU) 1406 #define ADC_REGULAR_RANK_14 (0x0000000EU) 1407 #define ADC_REGULAR_RANK_15 (0x0000000FU) 1408 #define ADC_REGULAR_RANK_16 (0x00000010U) 1409 /** 1410 * @} 1411 */ 1412 1413 /** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank 1414 * @{ 1415 */ 1416 #define ADC_INJECTED_RANK_1 (0x00000001U) 1417 #define ADC_INJECTED_RANK_2 (0x00000002U) 1418 #define ADC_INJECTED_RANK_3 (0x00000003U) 1419 #define ADC_INJECTED_RANK_4 (0x00000004U) 1420 /** 1421 * @} 1422 */ 1423 1424 /** @defgroup ADCEx_External_trigger_edge_Injected External Trigger Edge of Injected Group 1425 * @{ 1426 */ 1427 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000U) 1428 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG) 1429 /** 1430 * @} 1431 */ 1432 1433 /** @defgroup ADCEx_External_trigger_source_Injected External Trigger Source of Injected Group 1434 * @{ 1435 */ 1436 /* External triggers for injected groups of ADC1 */ 1437 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC_EXTERNALTRIGINJEC_T2_CC1 1438 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC_EXTERNALTRIGINJEC_T2_TRGO 1439 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC_EXTERNALTRIGINJEC_T3_CC4 1440 #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC_EXTERNALTRIGINJEC_T4_TRGO 1441 #define ADC_EXTERNALTRIGINJECCONV_T19_CC1 ADC_EXTERNALTRIGINJEC_T19_CC1 1442 #define ADC_EXTERNALTRIGINJECCONV_T19_CC2 ADC_EXTERNALTRIGINJEC_T19_CC2 1443 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC_EXTERNALTRIGINJEC_EXT_IT15 1444 #define ADC_INJECTED_SOFTWARE_START ADC_JSWSTART 1445 /** 1446 * @} 1447 */ 1448 1449 1450 /** @defgroup ADCEx_analog_watchdog_mode ADC Extended analog watchdog mode 1451 * @{ 1452 */ 1453 #define ADC_ANALOGWATCHDOG_NONE (0x00000000U) 1454 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) 1455 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) 1456 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) 1457 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CR1_AWDEN) 1458 #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CR1_JAWDEN) 1459 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) 1460 /** 1461 * @} 1462 */ 1463 1464 /** @defgroup ADC_conversion_group ADC Conversion Group 1465 * @{ 1466 */ 1467 #define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC)) 1468 #define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC)) 1469 #define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC)) 1470 /** 1471 * @} 1472 */ 1473 1474 /** @defgroup ADCEx_Event_type ADC Extended Event Type 1475 * @{ 1476 */ 1477 #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */ 1478 /** 1479 * @} 1480 */ 1481 1482 /** @defgroup ADCEx_interrupts_definition ADC Extended Interrupts Definition 1483 * @{ 1484 */ 1485 #define ADC_IT_EOC ADC_CR1_EOCIE /*!< ADC End of Regular Conversion interrupt source */ 1486 #define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */ 1487 #define ADC_IT_AWD ADC_CR1_AWDIE /*!< ADC Analog watchdog interrupt source */ 1488 /** 1489 * @} 1490 */ 1491 1492 /** @defgroup ADCEx_flags_definition ADC Extended Flags Definition 1493 * @{ 1494 */ 1495 #define ADC_FLAG_AWD ADC_SR_AWD /*!< ADC Analog watchdog flag */ 1496 #define ADC_FLAG_EOC ADC_SR_EOC /*!< ADC End of Regular conversion flag */ 1497 #define ADC_FLAG_JEOC ADC_SR_JEOC /*!< ADC End of Injected conversion flag */ 1498 #define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */ 1499 #define ADC_FLAG_STRT ADC_SR_STRT /*!< ADC Regular group start flag */ 1500 1501 /** 1502 * @} 1503 */ 1504 #endif /* STM32F373xC || STM32F378xx */ 1505 1506 /** 1507 * @} 1508 */ 1509 1510 1511 1512 /* Private constants ---------------------------------------------------------*/ 1513 1514 /** @addtogroup ADCEx_Private_Constants ADCEx Private Constants 1515 * @{ 1516 */ 1517 1518 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ 1519 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ 1520 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ 1521 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 1522 1523 1524 /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group 1525 * @{ 1526 */ 1527 #if defined(STM32F303xE) || defined(STM32F398xx) || \ 1528 defined(STM32F303xC) || defined(STM32F358xx) 1529 /* List of external triggers for common groups ADC1&ADC2 and/or ADC3&ADC4: */ 1530 /* (used internally by HAL driver. To not use into HAL structure parameters) */ 1531 1532 /* External triggers of regular group for ADC1 & ADC2 */ 1533 #define ADC1_2_EXTERNALTRIG_T1_CC1 (0x00000000U) 1534 #define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0) 1535 #define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1) 1536 #define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) 1537 #define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2) 1538 #define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) 1539 #define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) 1540 #define ADC1_2_EXTERNALTRIG_T8_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) 1541 #define ADC1_2_EXTERNALTRIG_T8_TRGO2 ((uint32_t) ADC_CFGR_EXTSEL_3) 1542 #define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0)) 1543 #define ADC1_2_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1)) 1544 #define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) 1545 #define ADC1_2_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2)) 1546 #define ADC1_2_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) 1547 #define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) 1548 #define ADC1_2_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL) 1549 1550 /* External triggers of regular group for ADC3 & ADC4 */ 1551 #define ADC3_4_EXTERNALTRIG_T3_CC1 (0x00000000U) 1552 #define ADC3_4_EXTERNALTRIG_T2_CC3 ((uint32_t)ADC_CFGR_EXTSEL_0) 1553 #define ADC3_4_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1) 1554 #define ADC3_4_EXTERNALTRIG_T8_CC1 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) 1555 #define ADC3_4_EXTERNALTRIG_T8_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2) 1556 #define ADC3_4_EXTERNALTRIG_EXT_IT2 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) 1557 #define ADC3_4_EXTERNALTRIG_T4_CC1 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) 1558 #define ADC3_4_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) 1559 #define ADC3_4_EXTERNALTRIG_T8_TRGO2 ((uint32_t)ADC_CFGR_EXTSEL_3) 1560 #define ADC3_4_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0)) 1561 #define ADC3_4_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1)) 1562 #define ADC3_4_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) 1563 #define ADC3_4_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2)) 1564 #define ADC3_4_EXTERNALTRIG_T7_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) 1565 #define ADC3_4_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) 1566 #define ADC3_4_EXTERNALTRIG_T2_CC1 ((uint32_t)ADC_CFGR_EXTSEL) 1567 #endif /* STM32F303xE || STM32F398xx || */ 1568 /* STM32F303xC || STM32F358xx */ 1569 1570 #if defined(STM32F302xE) || \ 1571 defined(STM32F302xC) 1572 /* List of external triggers of common group ADC1&ADC2: */ 1573 /* (used internally by HAL driver. To not use into HAL structure parameters) */ 1574 #define ADC1_2_EXTERNALTRIG_T1_CC1 (0x00000000U) 1575 #define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0) 1576 #define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1) 1577 #define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0)) 1578 #define ADC1_2_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1)) 1579 #define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) 1580 #define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) 1581 #define ADC1_2_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL) 1582 #define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2) 1583 #define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) 1584 #define ADC1_2_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2)) 1585 #define ADC1_2_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) 1586 #define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) 1587 #define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) 1588 #endif /* STM32F302xE || */ 1589 /* STM32F302xC */ 1590 1591 #if defined(STM32F303x8) || defined(STM32F328xx) 1592 /* List of external triggers of common group ADC1&ADC2: */ 1593 /* (used internally by HAL driver. To not use into HAL structure parameters) */ 1594 #define ADC1_2_EXTERNALTRIG_T1_CC1 (0x00000000U) 1595 #define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0) 1596 #define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1) 1597 #define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) 1598 #define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2) 1599 #define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) 1600 #define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) 1601 #define ADC1_2_EXTERNALTRIG_T8_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) 1602 #define ADC1_2_EXTERNALTRIG_T8_TRGO2 ((uint32_t) ADC_CFGR_EXTSEL_3) 1603 #define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0)) 1604 #define ADC1_2_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1)) 1605 #define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) 1606 #define ADC1_2_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2)) 1607 #define ADC1_2_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) 1608 #define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) 1609 #define ADC1_2_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL) 1610 #endif /* STM32F303x8 || STM32F328xx */ 1611 1612 #if defined(STM32F334x8) 1613 /* List of external triggers of common group ADC1&ADC2: */ 1614 /* (used internally by HAL driver. To not use into HAL structure parameters) */ 1615 #define ADC1_2_EXTERNALTRIG_T1_CC1 (0x00000000U) 1616 #define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0) 1617 #define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1) 1618 #define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) 1619 #define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2) 1620 #define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) 1621 #define ADC1_2_EXTERNALTRIG_HRTIM_TRG1 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) 1622 #define ADC1_2_EXTERNALTRIG_HRTIM_TRG3 ((uint32_t) ADC_CFGR_EXTSEL_3) 1623 #define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0)) 1624 #define ADC1_2_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1)) 1625 #define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) 1626 #define ADC1_2_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) 1627 #define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) 1628 #define ADC1_2_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL) 1629 #endif /* STM32F334x8 */ 1630 1631 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 1632 /* List of external triggers of regular group for ADC1: */ 1633 /* (used internally by HAL driver. To not use into HAL structure parameters) */ 1634 #define ADC1_EXTERNALTRIG_T1_CC1 (0x00000000U) 1635 #define ADC1_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0) 1636 #define ADC1_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1) 1637 #define ADC1_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) 1638 #define ADC1_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) 1639 #define ADC1_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0)) 1640 #define ADC1_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1)) 1641 #define ADC1_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) 1642 #define ADC1_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) 1643 #define ADC1_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) 1644 #define ADC_SOFTWARE_START (0x00000001U) 1645 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 1646 /** 1647 * @} 1648 */ 1649 1650 1651 /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended Internal HAL driver trigger selection for injected group 1652 * @{ 1653 */ 1654 #if defined(STM32F303xE) || defined(STM32F398xx) || \ 1655 defined(STM32F303xC) || defined(STM32F358xx) 1656 /* List of external triggers sorted of groups ADC1&ADC2 and/or ADC3&ADC4: */ 1657 /* (used internally by HAL driver. To not use into HAL structure parameters) */ 1658 1659 /* External triggers for injected groups of ADC1 & ADC2 */ 1660 #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U) 1661 #define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0) 1662 #define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1) 1663 #define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) 1664 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2) 1665 #define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) 1666 #define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) 1667 #define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) 1668 #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3) 1669 #define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0)) 1670 #define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1)) 1671 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) 1672 #define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2)) 1673 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) 1674 #define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) 1675 #define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL) 1676 1677 /* External triggers for injected groups of ADC3 & ADC4 */ 1678 /* Note: External triggers JEXT2 and JEXT5 are the same (TIM4_CC3 event). */ 1679 /* JEXT2 is the main trigger, JEXT5 could be redirected to another */ 1680 /* in future devices. */ 1681 /* However, this channel is implemented with a SW offset of 0x10000 for */ 1682 /* differentiation between similar triggers of common groups ADC1&ADC2, */ 1683 /* ADC3&ADC4 (Differentiation processed into macro */ 1684 /* ADC_JSQR_JEXTSEL_SET) */ 1685 #define ADC3_4_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U) 1686 #define ADC3_4_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0) 1687 #define ADC3_4_EXTERNALTRIGINJEC_T4_CC3 ((uint32_t)ADC_JSQR_JEXTSEL_1 | 0x10000U) 1688 #define ADC3_4_EXTERNALTRIGINJEC_T8_CC2 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) 1689 #define ADC3_4_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2) 1690 1691 #if defined(STM32F303xE) || defined(STM32F398xx) 1692 #define ADC3_4_EXTERNALTRIGINJEC_T20_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) 1693 #endif /* STM32F303xE || STM32F398xx */ 1694 1695 #define ADC3_4_EXTERNALTRIGINJEC_T4_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) 1696 #define ADC3_4_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) 1697 #define ADC3_4_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3) 1698 #define ADC3_4_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0)) 1699 #define ADC3_4_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1)) 1700 #define ADC3_4_EXTERNALTRIGINJEC_T1_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) 1701 #define ADC3_4_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2)) 1702 #define ADC3_4_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) 1703 #define ADC3_4_EXTERNALTRIGINJEC_T7_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) 1704 #define ADC3_4_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL) 1705 #endif /* STM32F303xE || STM32F398xx || */ 1706 /* STM32F303xC || STM32F358xx */ 1707 1708 #if defined(STM32F302xE) || \ 1709 defined(STM32F302xC) 1710 /* List of external triggers of group ADC1&ADC2: */ 1711 /* (used internally by HAL driver. To not use into HAL structure parameters) */ 1712 #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U) 1713 #define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0) 1714 #define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1) 1715 #define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) 1716 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2) 1717 #define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) 1718 #define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) 1719 #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3) 1720 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) 1721 #define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2)) 1722 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) 1723 #define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) 1724 #define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL) 1725 #endif /* STM32F302xE || */ 1726 /* STM32F302xC */ 1727 1728 #if defined(STM32F303x8) || defined(STM32F328xx) 1729 /* List of external triggers of group ADC1&ADC2: */ 1730 /* (used internally by HAL driver. To not use into HAL structure parameters) */ 1731 #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U) 1732 #define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0) 1733 #define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1) 1734 #define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) 1735 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2) 1736 #define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) 1737 #define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) 1738 #define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) 1739 #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3) 1740 #define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0)) 1741 #define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1)) 1742 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) 1743 #define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2)) 1744 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) 1745 #define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) 1746 #define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL) 1747 #endif /* STM32F303x8 || STM32F328xx */ 1748 1749 #if defined(STM32F334x8) 1750 /* List of external triggers of group ADC1&ADC2: */ 1751 /* (used internally by HAL driver. To not use into HAL structure parameters) */ 1752 #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U) 1753 #define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0) 1754 #define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1) 1755 #define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) 1756 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2) 1757 #define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) 1758 #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3) 1759 #define ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0)) 1760 #define ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG4 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1)) 1761 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) 1762 #define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2)) 1763 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) 1764 #define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) 1765 #define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL) 1766 #endif /* STM32F334x8 */ 1767 1768 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 1769 /* List of external triggers of injected group for ADC1: */ 1770 /* (used internally by HAL driver. To not use into HAL structure parameters) */ 1771 #define ADC1_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U) 1772 #define ADC1_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0) 1773 #define ADC1_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1) 1774 #define ADC1_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) 1775 #define ADC1_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) 1776 #define ADC1_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3) 1777 #define ADC1_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) 1778 #define ADC1_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL) 1779 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 1780 /** 1781 * @} 1782 */ 1783 1784 #define ADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | \ 1785 ADC_FLAG_JEOC | ADC_FLAG_JEOS | ADC_FLAG_OVR | ADC_FLAG_AWD1 | \ 1786 ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | ADC_FLAG_JQOVF) 1787 1788 /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */ 1789 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS | \ 1790 ADC_FLAG_OVR | ADC_FLAG_AWD1 | ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | \ 1791 ADC_FLAG_JQOVF) 1792 1793 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ 1794 /* STM32F302xC || STM32F303xC || STM32F358xx || */ 1795 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ 1796 /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 1797 1798 1799 #if defined(STM32F373xC) || defined(STM32F378xx) 1800 1801 /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group 1802 * @{ 1803 */ 1804 /* List of external triggers of regular group for ADC1: */ 1805 /* (used internally by HAL driver. To not use into HAL structure parameters) */ 1806 1807 /* External triggers of regular group for ADC1 */ 1808 #define ADC_EXTERNALTRIG_T19_TRGO (0x00000000U) 1809 #define ADC_EXTERNALTRIG_T19_CC3 ((uint32_t)ADC_CR2_EXTSEL_0) 1810 #define ADC_EXTERNALTRIG_T19_CC4 ((uint32_t)ADC_CR2_EXTSEL_1) 1811 #define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) 1812 #define ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_2) 1813 #define ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) 1814 #define ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)) 1815 #define ADC_SWSTART ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) 1816 /** 1817 * @} 1818 */ 1819 1820 /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended Internal HAL driver trigger selection for injected group 1821 * @{ 1822 */ 1823 /* List of external triggers of injected group for ADC1: */ 1824 /* (used internally by HAL driver. To not use into HAL structure parameters) */ 1825 1826 /* External triggers of injected group for ADC1 */ 1827 #define ADC_EXTERNALTRIGINJEC_T19_CC1 ( 0x00000000U) 1828 #define ADC_EXTERNALTRIGINJEC_T19_CC2 ((uint32_t) ADC_CR2_JEXTSEL_0) 1829 #define ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t) ADC_CR2_JEXTSEL_1) 1830 #define ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) 1831 #define ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t) ADC_CR2_JEXTSEL_2) 1832 #define ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) 1833 #define ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1)) 1834 #define ADC_JSWSTART ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) 1835 /** 1836 * @} 1837 */ 1838 1839 /** @defgroup ADCEx_sampling_times_all_channels ADC Extended Sampling Times All Channels 1840 * @{ 1841 */ 1842 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \ 1843 (ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 | \ 1844 ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 | \ 1845 ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2) 1846 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \ 1847 (ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | \ 1848 ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2 ) 1849 1850 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \ 1851 (ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 | \ 1852 ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 | \ 1853 ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1) 1854 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \ 1855 (ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | \ 1856 ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1 ) 1857 1858 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \ 1859 (ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 | \ 1860 ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 | \ 1861 ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0) 1862 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \ 1863 (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \ 1864 ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 ) 1865 1866 #define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS (0x00000000U) 1867 #define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) 1868 #define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) 1869 #define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) 1870 #define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) 1871 #define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) 1872 #define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) 1873 #define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) 1874 1875 #define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS (0x00000000U) 1876 #define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) 1877 #define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) 1878 #define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) 1879 #define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) 1880 #define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) 1881 #define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) 1882 #define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) 1883 1884 /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */ 1885 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD ) 1886 /** 1887 * @} 1888 */ 1889 1890 #endif /* STM32F373xC || STM32F378xx */ 1891 1892 /** 1893 * @} 1894 */ 1895 1896 /* Exported macro ------------------------------------------------------------*/ 1897 1898 /** @defgroup ADCEx_Exported_Macros ADCEx Exported Macros 1899 * @{ 1900 */ 1901 /* Macro for internal HAL driver usage, and possibly can be used into code of */ 1902 /* final user. */ 1903 1904 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ 1905 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ 1906 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ 1907 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 1908 1909 /** 1910 * @brief Enable the ADC peripheral 1911 * @param __HANDLE__ ADC handle 1912 * @note ADC enable requires a delay for ADC stabilization time 1913 * (refer to device datasheet, parameter tSTAB) 1914 * @note On STM32F3 devices, some hardware constraints must be strictly 1915 * respected before using this macro: 1916 * - ADC internal voltage regulator must be preliminarily enabled. 1917 * This is performed by function HAL_ADC_Init(). 1918 * - ADC state requirements: ADC must be disabled, no conversion on 1919 * going, no calibration on going. 1920 * These checks are performed by functions HAL_ADC_start_xxx(). 1921 * @retval None 1922 */ 1923 #define __HAL_ADC_ENABLE(__HANDLE__) \ 1924 (SET_BIT((__HANDLE__)->Instance->CR, ADC_CR_ADEN)) 1925 1926 /** 1927 * @brief Disable the ADC peripheral 1928 * @param __HANDLE__ ADC handle 1929 * @note On STM32F3 devices, some hardware constraints must be strictly 1930 * respected before using this macro: 1931 * - ADC state requirements: ADC must be enabled, no conversion on 1932 * going. 1933 * These checks are performed by functions HAL_ADC_start_xxx(). 1934 * @retval None 1935 */ 1936 #define __HAL_ADC_DISABLE(__HANDLE__) \ 1937 do{ \ 1938 SET_BIT((__HANDLE__)->Instance->CR, ADC_CR_ADDIS); \ 1939 __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \ 1940 } while(0U) 1941 1942 /** 1943 * @brief Enable the ADC end of conversion interrupt. 1944 * @param __HANDLE__ ADC handle 1945 * @param __INTERRUPT__ ADC Interrupt 1946 * This parameter can be any combination of the following values: 1947 * @arg ADC_IT_RDY: ADC Ready (ADRDY) interrupt source 1948 * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source 1949 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source 1950 * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source 1951 * @arg ADC_IT_OVR: ADC overrun interrupt source 1952 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source 1953 * @arg ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source 1954 * @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source (main analog watchdog, present on all STM32 devices) 1955 * @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source (additional analog watchdog, present only on STM32F3 devices) 1956 * @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source (additional analog watchdog, present only on STM32F3 devices) 1957 * @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source 1958 * @retval None 1959 */ 1960 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 1961 (SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))) 1962 1963 /** 1964 * @brief Disable the ADC end of conversion interrupt. 1965 * @param __HANDLE__ ADC handle 1966 * @param __INTERRUPT__ ADC Interrupt 1967 * This parameter can be any combination of the following values: 1968 * @arg ADC_IT_RDY: ADC Ready (ADRDY) interrupt source 1969 * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source 1970 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source 1971 * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source 1972 * @arg ADC_IT_OVR: ADC overrun interrupt source 1973 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source 1974 * @arg ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source 1975 * @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source (main analog watchdog, present on all STM32 devices) 1976 * @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source (additional analog watchdog, present only on STM32F3 devices) 1977 * @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source (additional analog watchdog, present only on STM32F3 devices) 1978 * @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source 1979 * @retval None 1980 */ 1981 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 1982 (CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))) 1983 1984 /** @brief Checks if the specified ADC interrupt source is enabled or disabled. 1985 * @param __HANDLE__ ADC handle 1986 * @param __INTERRUPT__ ADC interrupt source to check 1987 * This parameter can be any combination of the following values: 1988 * @arg ADC_IT_RDY: ADC Ready (ADRDY) interrupt source 1989 * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source 1990 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source 1991 * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source 1992 * @arg ADC_IT_OVR: ADC overrun interrupt source 1993 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source 1994 * @arg ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source 1995 * @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source (main analog watchdog, present on all STM32 devices) 1996 * @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source (additional analog watchdog, present only on STM32F3 devices) 1997 * @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source (additional analog watchdog, present only on STM32F3 devices) 1998 * @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source 1999 * @retval State of interruption (SET or RESET) 2000 */ 2001 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 2002 (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) 2003 2004 /** 2005 * @brief Get the selected ADC's flag status. 2006 * @param __HANDLE__ ADC handle 2007 * @param __FLAG__ ADC flag 2008 * This parameter can be any combination of the following values: 2009 * @arg ADC_FLAG_RDY: ADC Ready (ADRDY) flag 2010 * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag 2011 * @arg ADC_FLAG_EOC: ADC End of Regular Conversion flag 2012 * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag 2013 * @arg ADC_FLAG_OVR: ADC overrun flag 2014 * @arg ADC_FLAG_JEOC: ADC End of Injected Conversion flag 2015 * @arg ADC_FLAG_JEOS: ADC End of Injected sequence of Conversions flag 2016 * @arg ADC_FLAG_AWD1: ADC Analog watchdog 1 flag (main analog watchdog, present on all STM32 devices) 2017 * @arg ADC_FLAG_AWD2: ADC Analog watchdog 2 flag (additional analog watchdog, present only on STM32F3 devices) 2018 * @arg ADC_FLAG_AWD3: ADC Analog watchdog 3 flag (additional analog watchdog, present only on STM32F3 devices) 2019 * @arg ADC_FLAG_JQOVF: ADC Injected Context Queue Overflow flag 2020 * @retval None 2021 */ 2022 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ 2023 ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) 2024 2025 /** 2026 * @brief Clear the ADC's pending flags 2027 * @param __HANDLE__ ADC handle 2028 * @param __FLAG__ ADC flag 2029 * This parameter can be any combination of the following values: 2030 * @arg ADC_FLAG_RDY: ADC Ready (ADRDY) flag 2031 * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag 2032 * @arg ADC_FLAG_EOC: ADC End of Regular Conversion flag 2033 * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag 2034 * @arg ADC_FLAG_OVR: ADC overrun flag 2035 * @arg ADC_FLAG_JEOC: ADC End of Injected Conversion flag 2036 * @arg ADC_FLAG_JEOS: ADC End of Injected sequence of Conversions flag 2037 * @arg ADC_FLAG_AWD1: ADC Analog watchdog 1 flag (main analog watchdog, present on all STM32 devices) 2038 * @arg ADC_FLAG_AWD2: ADC Analog watchdog 2 flag (additional analog watchdog, present only on STM32F3 devices) 2039 * @arg ADC_FLAG_AWD3: ADC Analog watchdog 3 flag (additional analog watchdog, present only on STM32F3 devices) 2040 * @arg ADC_FLAG_JQOVF: ADC Injected Context Queue Overflow flag 2041 * @retval None 2042 */ 2043 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of */ 2044 /* register ISR). */ 2045 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 2046 (WRITE_REG((__HANDLE__)->Instance->ISR, (__FLAG__))) 2047 2048 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ 2049 /* STM32F302xC || STM32F303xC || STM32F358xx || */ 2050 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ 2051 /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 2052 2053 2054 #if defined(STM32F373xC) || defined(STM32F378xx) 2055 2056 /** 2057 * @brief Enable the ADC peripheral 2058 * @note ADC enable requires a delay for ADC stabilization time 2059 * (refer to device datasheet, parameter tSTAB) 2060 * @note On STM32F37x devices, if ADC is already enabled this macro trigs 2061 * a conversion SW start on regular group. 2062 * @param __HANDLE__ ADC handle 2063 * @retval None 2064 */ 2065 #define __HAL_ADC_ENABLE(__HANDLE__) \ 2066 (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON))) 2067 2068 /** 2069 * @brief Disable the ADC peripheral 2070 * @param __HANDLE__ ADC handle 2071 * @retval None 2072 */ 2073 #define __HAL_ADC_DISABLE(__HANDLE__) \ 2074 (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON))) 2075 2076 /** @brief Enable the ADC end of conversion interrupt. 2077 * @param __HANDLE__ ADC handle 2078 * @param __INTERRUPT__ ADC Interrupt 2079 * This parameter can be any combination of the following values: 2080 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source 2081 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source 2082 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source 2083 * @retval None 2084 */ 2085 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 2086 (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) 2087 2088 /** @brief Disable the ADC end of conversion interrupt. 2089 * @param __HANDLE__ ADC handle 2090 * @param __INTERRUPT__ ADC Interrupt 2091 * This parameter can be any combination of the following values: 2092 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source 2093 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source 2094 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source 2095 * @retval None 2096 */ 2097 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 2098 (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) 2099 2100 /** @brief Checks if the specified ADC interrupt source is enabled or disabled. 2101 * @param __HANDLE__ ADC handle 2102 * @param __INTERRUPT__ ADC interrupt source to check 2103 * This parameter can be any combination of the following values: 2104 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source 2105 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source 2106 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source 2107 * @retval State of interruption (SET or RESET) 2108 */ 2109 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 2110 (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) 2111 2112 /** @brief Get the selected ADC's flag status. 2113 * @param __HANDLE__ ADC handle 2114 * @param __FLAG__ ADC flag 2115 * This parameter can be any combination of the following values: 2116 * @arg ADC_FLAG_STRT: ADC Regular group start flag 2117 * @arg ADC_FLAG_JSTRT: ADC Injected group start flag 2118 * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag 2119 * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag 2120 * @arg ADC_FLAG_AWD: ADC Analog watchdog flag 2121 * @retval None 2122 */ 2123 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ 2124 ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 2125 2126 /** @brief Clear the ADC's pending flags 2127 * @param __HANDLE__ ADC handle 2128 * @param __FLAG__ ADC flag 2129 * This parameter can be any combination of the following values: 2130 * @arg ADC_FLAG_STRT: ADC Regular group start flag 2131 * @arg ADC_FLAG_JSTRT: ADC Injected group start flag 2132 * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag 2133 * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag 2134 * @arg ADC_FLAG_AWD: ADC Analog watchdog flag 2135 * @retval None 2136 */ 2137 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 2138 (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__))) 2139 2140 #endif /* STM32F373xC || STM32F378xx */ 2141 2142 /** 2143 * @} 2144 */ 2145 2146 /* Private macro ------------------------------------------------------------*/ 2147 2148 /** @addtogroup ADCEx_Private_Macro ADCEx Private Macros 2149 * @{ 2150 */ 2151 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 2152 /* code of final user. */ 2153 2154 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ 2155 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ 2156 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ 2157 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 2158 2159 /** 2160 * @brief Verification of hardware constraints before ADC can be enabled 2161 * @param __HANDLE__ ADC handle 2162 * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled) 2163 */ 2164 #define ADC_ENABLING_CONDITIONS(__HANDLE__) \ 2165 (( HAL_IS_BIT_CLR((__HANDLE__)->Instance->CR , \ 2166 (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | \ 2167 ADC_CR_JADSTART |ADC_CR_ADSTART | ADC_CR_ADDIS | \ 2168 ADC_CR_ADEN ) ) \ 2169 ) ? SET : RESET) 2170 2171 /** 2172 * @brief Verification of ADC state: enabled or disabled 2173 * @param __HANDLE__ ADC handle 2174 * @retval SET (ADC enabled) or RESET (ADC disabled) 2175 */ 2176 #define ADC_IS_ENABLE(__HANDLE__) \ 2177 (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ 2178 ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \ 2179 ) ? SET : RESET) 2180 2181 /** 2182 * @brief Test if conversion trigger of regular group is software start 2183 * or external trigger. 2184 * @param __HANDLE__ ADC handle 2185 * @retval SET (software start) or RESET (external trigger) 2186 */ 2187 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ 2188 (((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET) 2189 2190 /** 2191 * @brief Test if conversion trigger of injected group is software start 2192 * or external trigger. 2193 * @param __HANDLE__ ADC handle 2194 * @retval SET (software start) or RESET (external trigger) 2195 */ 2196 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ 2197 (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET) 2198 2199 /** 2200 * @brief Check if no conversion on going on regular and/or injected groups 2201 * @param __HANDLE__ ADC handle 2202 * @retval SET (conversion is on going) or RESET (no conversion is on going) 2203 */ 2204 #define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \ 2205 (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == RESET \ 2206 ) ? RESET : SET) 2207 2208 /** 2209 * @brief Check if no conversion on going on regular group 2210 * @param __HANDLE__ ADC handle 2211 * @retval SET (conversion is on going) or RESET (no conversion is on going) 2212 */ 2213 #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ 2214 (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \ 2215 ) ? RESET : SET) 2216 2217 /** 2218 * @brief Check if no conversion on going on injected group 2219 * @param __HANDLE__ ADC handle 2220 * @retval SET (conversion is on going) or RESET (no conversion is on going) 2221 */ 2222 #define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \ 2223 (( (((__HANDLE__)->Instance->CR) & ADC_CR_JADSTART) == RESET \ 2224 ) ? RESET : SET) 2225 2226 /** 2227 * @brief Returns resolution bits in CFGR1 register: RES[1:0]. 2228 * Returned value is among parameters to @ref ADCEx_Resolution. 2229 * @param __HANDLE__ ADC handle 2230 * @retval None 2231 */ 2232 #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES) 2233 2234 /** 2235 * @brief Simultaneously clears and sets specific bits of the handle State 2236 * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 2237 * the first parameter is the ADC handle State, the second parameter is the 2238 * bit field to clear, the third and last parameter is the bit field to set. 2239 * @retval None 2240 */ 2241 #define ADC_STATE_CLR_SET MODIFY_REG 2242 2243 /** 2244 * @brief Clear ADC error code (set it to error code: "no error") 2245 * @param __HANDLE__ ADC handle 2246 * @retval None 2247 */ 2248 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 2249 2250 /** 2251 * @brief Set the ADC's sample time for Channels numbers between 0 and 9. 2252 * @param _SAMPLETIME_ Sample time parameter. 2253 * @param _CHANNELNB_ Channel number. 2254 * @retval None 2255 */ 2256 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (_CHANNELNB_))) 2257 2258 /** 2259 * @brief Set the ADC's sample time for Channels numbers between 10 and 18. 2260 * @param _SAMPLETIME_ Sample time parameter. 2261 * @param _CHANNELNB_ Channel number. 2262 * @retval None 2263 */ 2264 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((_CHANNELNB_) - 10U))) 2265 2266 /** 2267 * @brief Set the selected regular Channel rank for rank between 1 and 4. 2268 * @param _CHANNELNB_ Channel number. 2269 * @param _RANKNB_ Rank number. 2270 * @retval None 2271 */ 2272 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * (_RANKNB_))) 2273 2274 /** 2275 * @brief Set the selected regular Channel rank for rank between 5 and 9. 2276 * @param _CHANNELNB_ Channel number. 2277 * @param _RANKNB_ Rank number. 2278 * @retval None 2279 */ 2280 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * ((_RANKNB_) - 5U))) 2281 2282 /** 2283 * @brief Set the selected regular Channel rank for rank between 10 and 14. 2284 * @param _CHANNELNB_ Channel number. 2285 * @param _RANKNB_ Rank number. 2286 * @retval None 2287 */ 2288 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * ((_RANKNB_) - 10U))) 2289 2290 /** 2291 * @brief Set the selected regular Channel rank for rank between 15 and 16. 2292 * @param _CHANNELNB_ Channel number. 2293 * @param _RANKNB_ Rank number. 2294 * @retval None 2295 */ 2296 #define ADC_SQR4_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * ((_RANKNB_) - 15U))) 2297 2298 /** 2299 * @brief Set the selected injected Channel rank. 2300 * @param _CHANNELNB_ Channel number. 2301 * @param _RANKNB_ Rank number. 2302 * @retval None 2303 */ 2304 #define ADC_JSQR_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * (_RANKNB_) +2U)) 2305 2306 2307 /** 2308 * @brief Set the Analog Watchdog 1 channel. 2309 * @param _CHANNEL_ channel to be monitored by Analog Watchdog 1. 2310 * @retval None 2311 */ 2312 #define ADC_CFGR_AWD1CH_SHIFT(_CHANNEL_) ((_CHANNEL_) << 26U) 2313 2314 /** 2315 * @brief Configure the channel number into Analog Watchdog 2 or 3. 2316 * @param _CHANNEL_ ADC Channel 2317 * @retval None 2318 */ 2319 #define ADC_CFGR_AWD23CR(_CHANNEL_) (1U << (_CHANNEL_)) 2320 2321 /** 2322 * @brief Enable automatic conversion of injected group 2323 * @param _INJECT_AUTO_CONVERSION_ Injected automatic conversion. 2324 * @retval None 2325 */ 2326 #define ADC_CFGR_INJECT_AUTO_CONVERSION(_INJECT_AUTO_CONVERSION_) ((_INJECT_AUTO_CONVERSION_) << 25U) 2327 2328 /** 2329 * @brief Enable ADC injected context queue 2330 * @param _INJECT_CONTEXT_QUEUE_MODE_ Injected context queue mode. 2331 * @retval None 2332 */ 2333 #define ADC_CFGR_INJECT_CONTEXT_QUEUE(_INJECT_CONTEXT_QUEUE_MODE_) ((_INJECT_CONTEXT_QUEUE_MODE_) << 21U) 2334 2335 /** 2336 * @brief Enable ADC discontinuous conversion mode for injected group 2337 * @param _INJECT_DISCONTINUOUS_MODE_ Injected discontinuous mode. 2338 * @retval None 2339 */ 2340 #define ADC_CFGR_INJECT_DISCCONTINUOUS(_INJECT_DISCONTINUOUS_MODE_) ((_INJECT_DISCONTINUOUS_MODE_) << 20U) 2341 2342 /** 2343 * @brief Enable ADC discontinuous conversion mode for regular group 2344 * @param _REG_DISCONTINUOUS_MODE_ Regular discontinuous mode. 2345 * @retval None 2346 */ 2347 #define ADC_CFGR_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) ((_REG_DISCONTINUOUS_MODE_) << 16U) 2348 2349 /** 2350 * @brief Configures the number of discontinuous conversions for regular group. 2351 * @param _NBR_DISCONTINUOUS_CONV_ Number of discontinuous conversions. 2352 * @retval None 2353 */ 2354 #define ADC_CFGR_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 17U) 2355 2356 /** 2357 * @brief Enable the ADC auto delay mode. 2358 * @param _AUTOWAIT_ Auto delay bit enable or disable. 2359 * @retval None 2360 */ 2361 #define ADC_CFGR_AUTOWAIT(_AUTOWAIT_) ((_AUTOWAIT_) << 14U) 2362 2363 /** 2364 * @brief Enable ADC continuous conversion mode. 2365 * @param _CONTINUOUS_MODE_ Continuous mode. 2366 * @retval None 2367 */ 2368 #define ADC_CFGR_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13U) 2369 2370 /** 2371 * @brief Enable ADC overrun mode. 2372 * @param _OVERRUN_MODE_ Overrun mode. 2373 * @retval Overrun bit setting to be programmed into CFGR register 2374 */ 2375 /* Note: Bit ADC_CFGR_OVRMOD not used directly in constant */ 2376 /* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00U, to set it */ 2377 /* as the default case to be compliant with other STM32 devices. */ 2378 #define ADC_CFGR_OVERRUN(_OVERRUN_MODE_) \ 2379 ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \ 2380 )? (ADC_CFGR_OVRMOD) : (0x00000000U) \ 2381 ) 2382 2383 /** 2384 * @brief Enable the ADC DMA continuous request. 2385 * @param _DMACONTREQ_MODE_ DMA continuous request mode. 2386 * @retval None 2387 */ 2388 #define ADC_CFGR_DMACONTREQ(_DMACONTREQ_MODE_) ((_DMACONTREQ_MODE_) << 1U) 2389 2390 /** 2391 * @brief For devices with 3 ADCs or more: Defines the external trigger source 2392 * for regular group according to ADC into common group ADC1&ADC2 or 2393 * ADC3&ADC4 (some triggers with same source have different value to 2394 * be programmed into ADC EXTSEL bits of CFGR register). 2395 * Note: No risk of trigger bits value of common group ADC1&ADC2 2396 * misleading to another trigger at same bits value, because the 3 2397 * exceptions below are circular and do not point to any other trigger 2398 * with direct treatment. 2399 * For devices with 2 ADCs or less: this macro makes no change. 2400 * @param __HANDLE__ ADC handle 2401 * @param __EXT_TRIG_CONV__ External trigger selected for regular group. 2402 * @retval External trigger to be programmed into EXTSEL bits of CFGR register 2403 */ 2404 #if defined(STM32F303xE) || defined(STM32F398xx) || \ 2405 defined(STM32F303xC) || defined(STM32F358xx) 2406 2407 #if defined(STM32F303xC) || defined(STM32F358xx) 2408 #define ADC_CFGR_EXTSEL_SET(__HANDLE__, __EXT_TRIG_CONV__) \ 2409 (( ((((__HANDLE__)->Instance) == ADC3) || (((__HANDLE__)->Instance) == ADC4)) \ 2410 )? \ 2411 ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T2_TRGO \ 2412 )? \ 2413 (ADC3_4_EXTERNALTRIG_T2_TRGO) \ 2414 : \ 2415 ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T3_TRGO \ 2416 )? \ 2417 (ADC3_4_EXTERNALTRIG_T3_TRGO) \ 2418 : \ 2419 ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO \ 2420 )? \ 2421 (ADC3_4_EXTERNALTRIG_T8_TRGO) \ 2422 : \ 2423 (__EXT_TRIG_CONV__) \ 2424 ) \ 2425 ) \ 2426 ) \ 2427 : \ 2428 (__EXT_TRIG_CONV__) \ 2429 ) 2430 #endif /* STM32F303xC || STM32F358xx */ 2431 2432 #if defined(STM32F303xE) || defined(STM32F398xx) 2433 /* Note: Macro including external triggers specific to device STM303xE: using */ 2434 /* Timer20 with ADC trigger input remap. */ 2435 #define ADC_CFGR_EXTSEL_SET(__HANDLE__, __EXT_TRIG_CONV__) \ 2436 (( ((((__HANDLE__)->Instance) == ADC3) || (((__HANDLE__)->Instance) == ADC4)) \ 2437 )? \ 2438 ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T2_TRGO \ 2439 )? \ 2440 (ADC3_4_EXTERNALTRIG_T2_TRGO) \ 2441 : \ 2442 ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T3_TRGO \ 2443 )? \ 2444 (ADC3_4_EXTERNALTRIG_T3_TRGO) \ 2445 : \ 2446 ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO \ 2447 )? \ 2448 (ADC3_4_EXTERNALTRIG_T8_TRGO) \ 2449 : \ 2450 ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T20_CC1 \ 2451 )? \ 2452 (ADC3_4_EXTERNALTRIG_T2_CC1) \ 2453 : \ 2454 ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T20_TRGO \ 2455 )? \ 2456 (ADC3_4_EXTERNALTRIG_EXT_IT2) \ 2457 : \ 2458 ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T20_TRGO2 \ 2459 )? \ 2460 (ADC3_4_EXTERNALTRIG_T4_CC1) \ 2461 : \ 2462 (__EXT_TRIG_CONV__) \ 2463 ) \ 2464 ) \ 2465 ) \ 2466 ) \ 2467 ) \ 2468 ) \ 2469 : \ 2470 (__EXT_TRIG_CONV__ & (~ADC_EXTERNALTRIGCONV_T20_MASK)) \ 2471 ) 2472 #endif /* STM32F303xE || STM32F398xx */ 2473 #else 2474 #define ADC_CFGR_EXTSEL_SET(__HANDLE__, __EXT_TRIG_CONV__) \ 2475 (__EXT_TRIG_CONV__) 2476 #endif /* STM32F303xE || STM32F398xx || */ 2477 /* STM32F303xC || STM32F358xx */ 2478 2479 /** 2480 * @brief For devices with 3 ADCs or more: Defines the external trigger source 2481 * for injected group according to ADC into common group ADC1&ADC2 or 2482 * ADC3&ADC4 (some triggers with same source have different value to 2483 * be programmed into ADC JEXTSEL bits of JSQR register). 2484 * Note: No risk of trigger bits value of common group ADC1&ADC2 2485 * misleading to another trigger at same bits value, because the 3 2486 * exceptions below are circular and do not point to any other trigger 2487 * with direct treatment, except trigger 2488 * ADC_EXTERNALTRIGINJECCONV_T4_CC3 differentiated with SW offset. 2489 * For devices with 2 ADCs or less: this macro makes no change. 2490 * @param __HANDLE__ ADC handle 2491 * @param __EXT_TRIG_INJECTCONV__ External trigger selected for injected group 2492 * @retval External trigger to be programmed into JEXTSEL bits of JSQR register 2493 */ 2494 #if defined(STM32F303xC) || defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F358xx) 2495 #if defined(STM32F303xC) || defined(STM32F358xx) 2496 #define ADC_JSQR_JEXTSEL_SET(__HANDLE__, __EXT_TRIG_INJECTCONV__) \ 2497 (( ((((__HANDLE__)->Instance) == ADC3) || (((__HANDLE__)->Instance) == ADC4)) \ 2498 )? \ 2499 ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO \ 2500 )? \ 2501 (ADC3_4_EXTERNALTRIGINJEC_T2_TRGO) \ 2502 : \ 2503 ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO \ 2504 )? \ 2505 (ADC3_4_EXTERNALTRIGINJEC_T4_TRGO) \ 2506 : \ 2507 ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4 \ 2508 )? \ 2509 (ADC3_4_EXTERNALTRIGINJEC_T8_CC4) \ 2510 : \ 2511 ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_CC3 \ 2512 )? \ 2513 (ADC3_4_EXTERNALTRIGINJEC_T4_CC3) \ 2514 : \ 2515 (__EXT_TRIG_INJECTCONV__) \ 2516 ) \ 2517 ) \ 2518 ) \ 2519 ) \ 2520 : \ 2521 (__EXT_TRIG_INJECTCONV__) \ 2522 ) 2523 #endif /* STM32F303xC || STM32F358xx */ 2524 2525 #if defined(STM32F303xE) || defined(STM32F398xx) 2526 /* Note: Macro including external triggers specific to device STM303xE: using */ 2527 /* Timer20 with ADC trigger input remap. */ 2528 #define ADC_JSQR_JEXTSEL_SET(__HANDLE__, __EXT_TRIG_INJECTCONV__) \ 2529 (( ((((__HANDLE__)->Instance) == ADC3) || (((__HANDLE__)->Instance) == ADC4)) \ 2530 )? \ 2531 ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO \ 2532 )? \ 2533 (ADC3_4_EXTERNALTRIGINJEC_T2_TRGO) \ 2534 : \ 2535 ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO \ 2536 )? \ 2537 (ADC3_4_EXTERNALTRIGINJEC_T4_TRGO) \ 2538 : \ 2539 ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4 \ 2540 )? \ 2541 (ADC3_4_EXTERNALTRIGINJEC_T8_CC4) \ 2542 : \ 2543 ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_CC3 \ 2544 )? \ 2545 (ADC3_4_EXTERNALTRIGINJEC_T4_CC3) \ 2546 : \ 2547 ( ( (__EXT_TRIG_INJECTCONV__) \ 2548 == ADC_EXTERNALTRIGINJECCONV_T20_TRGO \ 2549 )? \ 2550 (ADC3_4_EXTERNALTRIGINJEC_T20_TRGO) \ 2551 : \ 2552 ( ( (__EXT_TRIG_INJECTCONV__) \ 2553 == ADC_EXTERNALTRIGINJECCONV_T20_TRGO2 \ 2554 )? \ 2555 (ADC3_4_EXTERNALTRIGINJEC_T1_CC3) \ 2556 : \ 2557 (__EXT_TRIG_INJECTCONV__) \ 2558 ) \ 2559 ) \ 2560 ) \ 2561 ) \ 2562 ) \ 2563 ) \ 2564 : \ 2565 (__EXT_TRIG_INJECTCONV__ & (~ADC_EXTERNALTRIGCONV_T20_MASK)) \ 2566 ) 2567 #endif /* STM32F303xE || STM32F398xx */ 2568 #else 2569 #define ADC_JSQR_JEXTSEL_SET(__HANDLE__, __EXT_TRIG_INJECTCONV__) \ 2570 (__EXT_TRIG_INJECTCONV__) 2571 #endif /* STM32F303xE || STM32F398xx || */ 2572 /* STM32F303xC || STM32F358xx */ 2573 2574 /** 2575 * @brief Configure the channel number into offset OFRx register 2576 * @param _CHANNEL_ ADC Channel 2577 * @retval None 2578 */ 2579 #define ADC_OFR_CHANNEL(_CHANNEL_) ((_CHANNEL_) << 26U) 2580 2581 /** 2582 * @brief Configure the channel number into differential mode selection register 2583 * @param _CHANNEL_ ADC Channel 2584 * @retval None 2585 */ 2586 #define ADC_DIFSEL_CHANNEL(_CHANNEL_) (1U << (_CHANNEL_)) 2587 2588 /** 2589 * @brief Calibration factor in differential mode to be set into calibration register 2590 * @param _Calibration_Factor_ Calibration factor value 2591 * @retval None 2592 */ 2593 #define ADC_CALFACT_DIFF_SET(_Calibration_Factor_) ((_Calibration_Factor_) << 16U) 2594 2595 /** 2596 * @brief Calibration factor in differential mode to be retrieved from calibration register 2597 * @param _Calibration_Factor_ Calibration factor value 2598 * @retval None 2599 */ 2600 #define ADC_CALFACT_DIFF_GET(_Calibration_Factor_) ((_Calibration_Factor_) >> 16U) 2601 2602 /** 2603 * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3. 2604 * @param _Threshold_ Threshold value 2605 * @retval None 2606 */ 2607 #define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16U) 2608 2609 /** 2610 * @brief Enable the ADC DMA continuous request for ADC multimode. 2611 * @param _DMAContReq_MODE_ DMA continuous request mode. 2612 * @retval None 2613 */ 2614 #define ADC_CCR_MULTI_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 13U) 2615 2616 /** 2617 * @brief Verification of hardware constraints before ADC can be disabled 2618 * @param __HANDLE__ ADC handle 2619 * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled) 2620 */ 2621 #define ADC_DISABLING_CONDITIONS(__HANDLE__) \ 2622 (( ( ((__HANDLE__)->Instance->CR) & \ 2623 (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \ 2624 ) ? SET : RESET) 2625 2626 2627 /** 2628 * @brief Shift the offset in function of the selected ADC resolution. 2629 * Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 2630 * If resolution 12 bits, no shift. 2631 * If resolution 10 bits, shift of 2 ranks on the left. 2632 * If resolution 8 bits, shift of 4 ranks on the left. 2633 * If resolution 6 bits, shift of 6 ranks on the left. 2634 * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)) 2635 * @param __HANDLE__ ADC handle 2636 * @param _Offset_ Value to be shifted 2637 * @retval None 2638 */ 2639 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, _Offset_) \ 2640 ((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3U)*2U)) 2641 2642 /** 2643 * @brief Shift the AWD1 threshold in function of the selected ADC resolution. 2644 * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. 2645 * If resolution 12 bits, no shift. 2646 * If resolution 10 bits, shift of 2 ranks on the left. 2647 * If resolution 8 bits, shift of 4 ranks on the left. 2648 * If resolution 6 bits, shift of 6 ranks on the left. 2649 * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)) 2650 * @param __HANDLE__ ADC handle 2651 * @param _Threshold_ Value to be shifted 2652 * @retval None 2653 */ 2654 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \ 2655 ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3U)*2U)) 2656 2657 /** 2658 * @brief Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution. 2659 * Thresholds have to be left-aligned on bit 7. 2660 * If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded) 2661 * If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded) 2662 * If resolution 8 bits, no shift. 2663 * If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0) 2664 * @param __HANDLE__ ADC handle 2665 * @param _Threshold_ Value to be shifted 2666 * @retval None 2667 */ 2668 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \ 2669 ( ((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ? \ 2670 ((_Threshold_) >> (4U- ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3U)*2U))) : \ 2671 (_Threshold_) << 2U ) 2672 2673 /** 2674 * @brief Defines if the selected ADC is within ADC common register ADC1_2 or ADC3_4 2675 * if available (ADC2, ADC3, ADC4 availability depends on STM32 product) 2676 * @param __HANDLE__ ADC handle 2677 * @retval Common control register ADC1_2 or ADC3_4 2678 */ 2679 #if defined(STM32F303xE) || defined(STM32F398xx) || \ 2680 defined(STM32F303xC) || defined(STM32F358xx) 2681 #define ADC_MASTER_INSTANCE(__HANDLE__) \ 2682 ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \ 2683 )? (ADC1) : (ADC3) \ 2684 ) 2685 #endif /* STM32F303xE || STM32F398xx || */ 2686 /* STM32F303xC || STM32F358xx */ 2687 2688 #if defined(STM32F302xE) || \ 2689 defined(STM32F302xC) || \ 2690 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 2691 #define ADC_MASTER_INSTANCE(__HANDLE__) \ 2692 (ADC1) 2693 #endif /* STM32F302xE || */ 2694 /* STM32F302xC || */ 2695 /* STM32F303x8 || STM32F328xx || STM32F334x8 */ 2696 2697 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 2698 #define ADC_MASTER_INSTANCE(__HANDLE__) \ 2699 (ADC1) 2700 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 2701 2702 /** 2703 * @brief Defines if the selected ADC is within ADC common register ADC1_2 or ADC3_4 2704 * if available (ADC2, ADC3, ADC4 availability depends on STM32 product) 2705 * @param __HANDLE__ ADC handle 2706 * @retval Common control register ADC1_2 or ADC3_4 2707 */ 2708 #if defined(STM32F303xE) || defined(STM32F398xx) || \ 2709 defined(STM32F303xC) || defined(STM32F358xx) 2710 #define ADC_COMMON_REGISTER(__HANDLE__) \ 2711 ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \ 2712 )? (ADC1_2_COMMON) : (ADC3_4_COMMON) \ 2713 ) 2714 #endif /* STM32F303xE || STM32F398xx || */ 2715 /* STM32F303xC || STM32F358xx */ 2716 2717 #if defined(STM32F302xE) || \ 2718 defined(STM32F302xC) || \ 2719 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 2720 #define ADC_COMMON_REGISTER(__HANDLE__) \ 2721 (ADC1_2_COMMON) 2722 #endif /* STM32F302xE || */ 2723 /* STM32F302xC || */ 2724 /* STM32F303x8 || STM32F328xx || STM32F334x8 */ 2725 2726 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 2727 #define ADC_COMMON_REGISTER(__HANDLE__) \ 2728 (ADC1_COMMON) 2729 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 2730 2731 /** 2732 * @brief Selection of ADC common register CCR bits MULTI[4:0]corresponding to the selected ADC (applicable for devices with several ADCs) 2733 * @param __HANDLE__ ADC handle 2734 * @retval None 2735 */ 2736 #if defined(STM32F303xE) || defined(STM32F398xx) || \ 2737 defined(STM32F303xC) || defined(STM32F358xx) 2738 #define ADC_COMMON_CCR_MULTI(__HANDLE__) \ 2739 ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \ 2740 )? \ 2741 (ADC1_2_COMMON->CCR & ADC12_CCR_MULTI) \ 2742 : \ 2743 (ADC3_4_COMMON->CCR & ADC34_CCR_MULTI) \ 2744 ) 2745 #endif /* STM32F303xE || STM32F398xx || */ 2746 /* STM32F303xC || STM32F358xx */ 2747 2748 #if defined(STM32F302xE) || \ 2749 defined(STM32F302xC) || \ 2750 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 2751 #define ADC_COMMON_CCR_MULTI(__HANDLE__) \ 2752 (ADC1_2_COMMON->CCR & ADC12_CCR_MULTI) 2753 #endif /* STM32F302xE || */ 2754 /* STM32F302xC || */ 2755 /* STM32F303x8 || STM32F328xx || STM32F334x8 */ 2756 2757 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 2758 #define ADC_COMMON_CCR_MULTI(__HANDLE__) \ 2759 (RESET) 2760 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 2761 2762 /** 2763 * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode, or multimode with handle of ADC master (applicable for devices with several ADCs) 2764 * @param __HANDLE__ ADC handle 2765 * @retval None 2766 */ 2767 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ 2768 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ 2769 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 2770 #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ 2771 ((ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_MODE_INDEPENDENT) || \ 2772 (IS_ADC_MULTIMODE_MASTER_INSTANCE((__HANDLE__)->Instance)) ) 2773 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ 2774 /* STM32F302xC || STM32F303xC || STM32F358xx || */ 2775 /* STM32F303x8 || STM32F334x8 || STM32F328xx */ 2776 2777 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 2778 #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ 2779 (!RESET) 2780 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 2781 2782 /** 2783 * @brief Verification of condition for ADC group regular start conversion: ADC must be in non-multimode or multimode on group injected only, or multimode with handle of ADC master (applicable for devices with several ADCs) 2784 * @param __HANDLE__ ADC handle. 2785 * @retval None 2786 */ 2787 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ 2788 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ 2789 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 2790 #define ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(__HANDLE__) \ 2791 ((ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_MODE_INDEPENDENT) || \ 2792 (ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_DUALMODE_INJECSIMULT) || \ 2793 (ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_DUALMODE_ALTERTRIG) || \ 2794 (IS_ADC_MULTIMODE_MASTER_INSTANCE((__HANDLE__)->Instance)) ) 2795 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ 2796 /* STM32F302xC || STM32F303xC || STM32F358xx || */ 2797 /* STM32F303x8 || STM32F334x8 || STM32F328xx */ 2798 2799 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 2800 #define ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(__HANDLE__) \ 2801 (!RESET) 2802 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 2803 2804 /** 2805 * @brief Verification of condition for ADC group injected start conversion: ADC must be in non-multimode or multimode on group regular only, or multimode with handle of ADC master (applicable for devices with several ADCs) 2806 * @param __HANDLE__ ADC handle. 2807 * @retval None 2808 */ 2809 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ 2810 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ 2811 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 2812 #define ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(__HANDLE__) \ 2813 ((ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_MODE_INDEPENDENT) || \ 2814 (ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_DUALMODE_REGSIMULT) || \ 2815 (ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_DUALMODE_INTERL) || \ 2816 (IS_ADC_MULTIMODE_MASTER_INSTANCE((__HANDLE__)->Instance)) ) 2817 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ 2818 /* STM32F302xC || STM32F303xC || STM32F358xx || */ 2819 /* STM32F303x8 || STM32F334x8 || STM32F328xx */ 2820 2821 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 2822 #define ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(__HANDLE__) \ 2823 (!RESET) 2824 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 2825 2826 /** 2827 * @brief Check ADC multimode setting: In case of multimode, check whether ADC master of the selected ADC has feature auto-injection enabled (applicable for devices with several ADCs) 2828 * @param __HANDLE__ ADC handle 2829 * @retval None 2830 */ 2831 #if defined(STM32F303xE) || defined(STM32F398xx) || \ 2832 defined(STM32F303xC) || defined(STM32F358xx) 2833 #define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \ 2834 (( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \ 2835 )? \ 2836 (ADC1->CFGR & ADC_CFGR_JAUTO) \ 2837 : \ 2838 (ADC3->CFGR & ADC_CFGR_JAUTO) \ 2839 ) 2840 #elif defined(STM32F302xE) || \ 2841 defined(STM32F302xC) || \ 2842 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 2843 #define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \ 2844 (( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \ 2845 )? \ 2846 (ADC1->CFGR & ADC_CFGR_JAUTO) \ 2847 : \ 2848 (RESET) \ 2849 ) 2850 #else 2851 #define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \ 2852 (RESET) 2853 #endif 2854 2855 /** 2856 * @brief Set handle of the other ADC sharing the same common register ADC1_2 or ADC3_4 2857 * if available (ADC2, ADC3, ADC4 availability depends on STM32 product) 2858 * @param __HANDLE__ ADC handle 2859 * @param __HANDLE_OTHER_ADC__ other ADC handle 2860 * @retval None 2861 */ 2862 #if defined(STM32F303xE) || defined(STM32F398xx) || \ 2863 defined(STM32F303xC) || defined(STM32F358xx) 2864 #define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \ 2865 ( ( ((__HANDLE__)->Instance == ADC1) \ 2866 )? \ 2867 ((__HANDLE_OTHER_ADC__)->Instance = ADC2) \ 2868 : \ 2869 ( ( ((__HANDLE__)->Instance == ADC2) \ 2870 )? \ 2871 ((__HANDLE_OTHER_ADC__)->Instance = ADC1) \ 2872 : \ 2873 ( ( ((__HANDLE__)->Instance == ADC3) \ 2874 )? \ 2875 ((__HANDLE_OTHER_ADC__)->Instance = ADC4) \ 2876 : \ 2877 ( ( ((__HANDLE__)->Instance == ADC4) \ 2878 )? \ 2879 ((__HANDLE_OTHER_ADC__)->Instance = ADC3) \ 2880 : \ 2881 ((__HANDLE_OTHER_ADC__)->Instance = NULL) \ 2882 ) \ 2883 ) \ 2884 ) \ 2885 ) 2886 #endif /* STM32F303xE || STM32F398xx || */ 2887 /* STM32F303xC || STM32F358xx */ 2888 2889 #if defined(STM32F302xE) || \ 2890 defined(STM32F302xC) || \ 2891 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 2892 #define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \ 2893 ( ( ((__HANDLE__)->Instance == ADC1) \ 2894 )? \ 2895 ((__HANDLE_OTHER_ADC__)->Instance = ADC2) \ 2896 : \ 2897 ((__HANDLE_OTHER_ADC__)->Instance = ADC1) \ 2898 ) 2899 #endif /* STM32F302xE || */ 2900 /* STM32F302xC || */ 2901 /* STM32F303x8 || STM32F328xx || STM32F334x8 */ 2902 2903 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 2904 #define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \ 2905 ((__HANDLE_OTHER_ADC__)->Instance = NULL) 2906 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 2907 2908 /** 2909 * @brief Set handle of the ADC slave associated to the ADC master 2910 * if available (ADC2, ADC3, ADC4 availability depends on STM32 product) 2911 * @param __HANDLE_MASTER__ ADC master handle 2912 * @param __HANDLE_SLAVE__ ADC slave handle 2913 * @retval None 2914 */ 2915 #if defined(STM32F303xE) || defined(STM32F398xx) || \ 2916 defined(STM32F303xC) || defined(STM32F358xx) 2917 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ 2918 ( ( ((__HANDLE_MASTER__)->Instance == ADC1) \ 2919 )? \ 2920 ((__HANDLE_SLAVE__)->Instance = ADC2) \ 2921 : \ 2922 ( ( ((__HANDLE_MASTER__)->Instance == ADC3) \ 2923 )? \ 2924 ((__HANDLE_SLAVE__)->Instance = ADC4) \ 2925 : \ 2926 ((__HANDLE_SLAVE__)->Instance = NULL) \ 2927 ) \ 2928 ) 2929 #endif /* STM32F303xE || STM32F398xx || */ 2930 /* STM32F303xC || STM32F358xx */ 2931 2932 #if defined(STM32F302xE) || \ 2933 defined(STM32F302xC) || \ 2934 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 2935 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ 2936 ( ( ((__HANDLE_MASTER__)->Instance == ADC1) \ 2937 )? \ 2938 ((__HANDLE_SLAVE__)->Instance = ADC2) \ 2939 : \ 2940 ( NULL ) \ 2941 ) 2942 #endif /* STM32F302xE || */ 2943 /* STM32F302xC || */ 2944 /* STM32F303x8 || STM32F328xx || STM32F334x8 */ 2945 2946 2947 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ 2948 ((RESOLUTION) == ADC_RESOLUTION_10B) || \ 2949 ((RESOLUTION) == ADC_RESOLUTION_8B) || \ 2950 ((RESOLUTION) == ADC_RESOLUTION_6B) ) 2951 2952 #define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) || \ 2953 ((RESOLUTION) == ADC_RESOLUTION_6B) ) 2954 2955 2956 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ 2957 ((ALIGN) == ADC_DATAALIGN_LEFT) ) 2958 2959 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \ 2960 ((SCAN_MODE) == ADC_SCAN_ENABLE) ) 2961 2962 #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \ 2963 ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) ) 2964 2965 #define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \ 2966 ((OVR) == ADC_OVR_DATA_OVERWRITTEN) ) 2967 2968 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_1) || \ 2969 ((CHANNEL) == ADC_CHANNEL_2) || \ 2970 ((CHANNEL) == ADC_CHANNEL_3) || \ 2971 ((CHANNEL) == ADC_CHANNEL_4) || \ 2972 ((CHANNEL) == ADC_CHANNEL_5) || \ 2973 ((CHANNEL) == ADC_CHANNEL_6) || \ 2974 ((CHANNEL) == ADC_CHANNEL_7) || \ 2975 ((CHANNEL) == ADC_CHANNEL_8) || \ 2976 ((CHANNEL) == ADC_CHANNEL_9) || \ 2977 ((CHANNEL) == ADC_CHANNEL_10) || \ 2978 ((CHANNEL) == ADC_CHANNEL_11) || \ 2979 ((CHANNEL) == ADC_CHANNEL_12) || \ 2980 ((CHANNEL) == ADC_CHANNEL_13) || \ 2981 ((CHANNEL) == ADC_CHANNEL_14) || \ 2982 ((CHANNEL) == ADC_CHANNEL_15) || \ 2983 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \ 2984 ((CHANNEL) == ADC_CHANNEL_VBAT) || \ 2985 ((CHANNEL) == ADC_CHANNEL_VREFINT) || \ 2986 ((CHANNEL) == ADC_CHANNEL_VOPAMP1) || \ 2987 ((CHANNEL) == ADC_CHANNEL_VOPAMP2) || \ 2988 ((CHANNEL) == ADC_CHANNEL_VOPAMP3) || \ 2989 ((CHANNEL) == ADC_CHANNEL_VOPAMP4) ) 2990 2991 #define IS_ADC_DIFF_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_1) || \ 2992 ((CHANNEL) == ADC_CHANNEL_2) || \ 2993 ((CHANNEL) == ADC_CHANNEL_3) || \ 2994 ((CHANNEL) == ADC_CHANNEL_4) || \ 2995 ((CHANNEL) == ADC_CHANNEL_5) || \ 2996 ((CHANNEL) == ADC_CHANNEL_6) || \ 2997 ((CHANNEL) == ADC_CHANNEL_7) || \ 2998 ((CHANNEL) == ADC_CHANNEL_8) || \ 2999 ((CHANNEL) == ADC_CHANNEL_9) || \ 3000 ((CHANNEL) == ADC_CHANNEL_10) || \ 3001 ((CHANNEL) == ADC_CHANNEL_11) || \ 3002 ((CHANNEL) == ADC_CHANNEL_12) || \ 3003 ((CHANNEL) == ADC_CHANNEL_13) || \ 3004 ((CHANNEL) == ADC_CHANNEL_14) ) 3005 3006 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ 3007 ((TIME) == ADC_SAMPLETIME_2CYCLES_5) || \ 3008 ((TIME) == ADC_SAMPLETIME_4CYCLES_5) || \ 3009 ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ 3010 ((TIME) == ADC_SAMPLETIME_19CYCLES_5) || \ 3011 ((TIME) == ADC_SAMPLETIME_61CYCLES_5) || \ 3012 ((TIME) == ADC_SAMPLETIME_181CYCLES_5) || \ 3013 ((TIME) == ADC_SAMPLETIME_601CYCLES_5) ) 3014 3015 #define IS_ADC_SINGLE_DIFFERENTIAL(SING_DIFF) (((SING_DIFF) == ADC_SINGLE_ENDED) || \ 3016 ((SING_DIFF) == ADC_DIFFERENTIAL_ENDED) ) 3017 3018 #define IS_ADC_OFFSET_NUMBER(OFFSET_NUMBER) (((OFFSET_NUMBER) == ADC_OFFSET_NONE) || \ 3019 ((OFFSET_NUMBER) == ADC_OFFSET_1) || \ 3020 ((OFFSET_NUMBER) == ADC_OFFSET_2) || \ 3021 ((OFFSET_NUMBER) == ADC_OFFSET_3) || \ 3022 ((OFFSET_NUMBER) == ADC_OFFSET_4) ) 3023 3024 #define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \ 3025 ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \ 3026 ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \ 3027 ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \ 3028 ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \ 3029 ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \ 3030 ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \ 3031 ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \ 3032 ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \ 3033 ((CHANNEL) == ADC_REGULAR_RANK_10) || \ 3034 ((CHANNEL) == ADC_REGULAR_RANK_11) || \ 3035 ((CHANNEL) == ADC_REGULAR_RANK_12) || \ 3036 ((CHANNEL) == ADC_REGULAR_RANK_13) || \ 3037 ((CHANNEL) == ADC_REGULAR_RANK_14) || \ 3038 ((CHANNEL) == ADC_REGULAR_RANK_15) || \ 3039 ((CHANNEL) == ADC_REGULAR_RANK_16) ) 3040 3041 #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 3042 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 3043 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 3044 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) 3045 3046 #if defined(STM32F303xE) || defined(STM32F398xx) || \ 3047 defined(STM32F303xC) || defined(STM32F358xx) 3048 3049 #if defined(STM32F303xC) || defined(STM32F358xx) 3050 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ 3051 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ 3052 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ 3053 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \ 3054 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ 3055 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \ 3056 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ 3057 \ 3058 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC1) || \ 3059 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \ 3060 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \ 3061 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC1) || \ 3062 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T7_TRGO) || \ 3063 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \ 3064 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT2) || \ 3065 \ 3066 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ 3067 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ 3068 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \ 3069 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ 3070 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ 3071 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \ 3072 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \ 3073 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \ 3074 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \ 3075 \ 3076 ((REGTRIG) == ADC_SOFTWARE_START) ) 3077 #endif /* STM32F303xC || STM32F358xx */ 3078 3079 #if defined(STM32F303xE) || defined(STM32F398xx) 3080 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ 3081 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ 3082 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ 3083 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \ 3084 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ 3085 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \ 3086 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ 3087 \ 3088 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC1) || \ 3089 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \ 3090 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \ 3091 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC1) || \ 3092 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T7_TRGO) || \ 3093 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \ 3094 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT2) || \ 3095 \ 3096 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ 3097 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ 3098 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \ 3099 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ 3100 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ 3101 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \ 3102 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \ 3103 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \ 3104 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \ 3105 \ 3106 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC2) || \ 3107 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC3) || \ 3108 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC1) || \ 3109 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_TRGO) || \ 3110 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_TRGO2) || \ 3111 \ 3112 ((REGTRIG) == ADC_SOFTWARE_START) ) 3113 #endif /* STM32F303xE || STM32F398xx */ 3114 3115 #endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */ 3116 3117 #if defined(STM32F302xE) || \ 3118 defined(STM32F302xC) 3119 3120 #if defined(STM32F302xE) 3121 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ 3122 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ 3123 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ 3124 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ 3125 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ 3126 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ 3127 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ 3128 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ 3129 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \ 3130 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ 3131 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \ 3132 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \ 3133 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \ 3134 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \ 3135 \ 3136 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC2) || \ 3137 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC3) || \ 3138 \ 3139 ((REGTRIG) == ADC_SOFTWARE_START) ) 3140 #endif /* STM32F302xE */ 3141 3142 #if defined(STM32F302xC) 3143 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ 3144 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ 3145 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ 3146 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ 3147 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ 3148 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ 3149 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ 3150 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ 3151 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \ 3152 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ 3153 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \ 3154 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \ 3155 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \ 3156 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \ 3157 \ 3158 ((REGTRIG) == ADC_SOFTWARE_START) ) 3159 #endif /* STM32F302xC */ 3160 3161 #endif /* STM32F302xE || */ 3162 /* STM32F302xC */ 3163 3164 #if defined(STM32F303x8) || defined(STM32F328xx) 3165 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ 3166 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ 3167 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ 3168 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ 3169 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ 3170 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ 3171 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ 3172 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \ 3173 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \ 3174 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ 3175 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \ 3176 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ 3177 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \ 3178 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \ 3179 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \ 3180 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \ 3181 \ 3182 ((REGTRIG) == ADC_SOFTWARE_START) ) 3183 #endif /* STM32F303x8 || STM32F328xx */ 3184 3185 #if defined(STM32F334x8) 3186 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ 3187 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ 3188 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ 3189 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ 3190 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ 3191 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ 3192 ((REGTRIG) == ADC_EXTERNALTRIGCONVHRTIM_TRG1) || \ 3193 ((REGTRIG) == ADC_EXTERNALTRIGCONVHRTIM_TRG3) || \ 3194 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ 3195 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \ 3196 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ 3197 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \ 3198 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \ 3199 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \ 3200 \ 3201 ((REGTRIG) == ADC_SOFTWARE_START) ) 3202 #endif /* STM32F334x8 */ 3203 3204 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 3205 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ 3206 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ 3207 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ 3208 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ 3209 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ 3210 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ 3211 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \ 3212 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ 3213 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \ 3214 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \ 3215 ((REGTRIG) == ADC_SOFTWARE_START) ) 3216 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 3217 3218 #define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ 3219 ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ 3220 ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ 3221 ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) 3222 3223 3224 #if defined(STM32F303xE) || defined(STM32F398xx) || \ 3225 defined(STM32F303xC) || defined(STM32F358xx) 3226 3227 #if defined(STM32F303xC) || defined(STM32F358xx) 3228 #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ 3229 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \ 3230 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ 3231 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \ 3232 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ 3233 \ 3234 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \ 3235 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC4) || \ 3236 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \ 3237 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \ 3238 \ 3239 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ 3240 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ 3241 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \ 3242 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ 3243 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \ 3244 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \ 3245 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ 3246 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \ 3247 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \ 3248 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \ 3249 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \ 3250 \ 3251 ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) ) 3252 #endif /* STM32F303xC || STM32F358xx */ 3253 3254 #if defined(STM32F303xE) || defined(STM32F398xx) 3255 #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ 3256 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \ 3257 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ 3258 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \ 3259 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ 3260 \ 3261 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \ 3262 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC4) || \ 3263 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \ 3264 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \ 3265 \ 3266 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ 3267 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ 3268 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \ 3269 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ 3270 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \ 3271 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \ 3272 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ 3273 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \ 3274 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \ 3275 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \ 3276 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \ 3277 \ 3278 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC4) || \ 3279 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC2) || \ 3280 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO) || \ 3281 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO2) || \ 3282 \ 3283 ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) ) 3284 #endif /* STM32F303xE || STM32F398xx */ 3285 3286 #endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */ 3287 3288 #if defined(STM32F302xE) || \ 3289 defined(STM32F302xC) 3290 3291 #if defined(STM32F302xE) 3292 #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ 3293 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ 3294 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \ 3295 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ 3296 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ 3297 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \ 3298 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \ 3299 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ 3300 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \ 3301 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ 3302 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \ 3303 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \ 3304 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ 3305 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC4) || \ 3306 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO) || \ 3307 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO2) || \ 3308 ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) ) 3309 #endif /* STM32F302xE */ 3310 3311 #if defined(STM32F302xC) 3312 #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ 3313 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ 3314 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \ 3315 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ 3316 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ 3317 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \ 3318 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \ 3319 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ 3320 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \ 3321 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ 3322 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \ 3323 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \ 3324 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ 3325 ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) ) 3326 #endif /* STM32F302xC */ 3327 3328 #endif /* STM32F302xE || */ 3329 /* STM32F302xC */ 3330 3331 #if defined(STM32F303x8) || defined(STM32F328xx) 3332 #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ 3333 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ 3334 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ 3335 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ 3336 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ 3337 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ 3338 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ 3339 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \ 3340 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \ 3341 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \ 3342 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \ 3343 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \ 3344 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \ 3345 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \ 3346 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \ 3347 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \ 3348 ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) ) 3349 #endif /* STM32F303x8 || STM32F328xx */ 3350 3351 #if defined(STM32F334x8) 3352 #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ 3353 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ 3354 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ 3355 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ 3356 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ 3357 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ 3358 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \ 3359 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG2) || \ 3360 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG4) || \ 3361 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \ 3362 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \ 3363 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \ 3364 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \ 3365 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \ 3366 ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) ) 3367 #endif /* STM32F334x8 */ 3368 3369 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 3370 #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ 3371 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ 3372 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ 3373 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \ 3374 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \ 3375 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \ 3376 ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) ) 3377 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 3378 3379 #define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \ 3380 ((CHANNEL) == ADC_INJECTED_RANK_2) || \ 3381 ((CHANNEL) == ADC_INJECTED_RANK_3) || \ 3382 ((CHANNEL) == ADC_INJECTED_RANK_4) ) 3383 3384 #define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \ 3385 ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ 3386 ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ 3387 ((MODE) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \ 3388 ((MODE) == ADC_DUALMODE_INJECSIMULT) || \ 3389 ((MODE) == ADC_DUALMODE_REGSIMULT) || \ 3390 ((MODE) == ADC_DUALMODE_INTERL) || \ 3391 ((MODE) == ADC_DUALMODE_ALTERTRIG) ) 3392 3393 #define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAACCESSMODE_DISABLED) || \ 3394 ((MODE) == ADC_DMAACCESSMODE_12_10_BITS) || \ 3395 ((MODE) == ADC_DMAACCESSMODE_8_6_BITS) ) 3396 3397 #define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \ 3398 ((DELAY) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \ 3399 ((DELAY) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \ 3400 ((DELAY) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \ 3401 ((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ 3402 ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ 3403 ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ 3404 ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ 3405 ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ 3406 ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ 3407 ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ 3408 ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) ) 3409 3410 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_1) || \ 3411 ((WATCHDOG) == ADC_ANALOGWATCHDOG_2) || \ 3412 ((WATCHDOG) == ADC_ANALOGWATCHDOG_3) ) 3413 3414 #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ 3415 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 3416 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ 3417 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ 3418 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \ 3419 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ 3420 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) 3421 3422 #define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \ 3423 ((CONVERSION) == ADC_INJECTED_GROUP) || \ 3424 ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) ) 3425 3426 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \ 3427 ((EVENT) == ADC_AWD2_EVENT) || \ 3428 ((EVENT) == ADC_AWD3_EVENT) || \ 3429 ((EVENT) == ADC_OVR_EVENT) || \ 3430 ((EVENT) == ADC_JQOVF_EVENT) ) 3431 3432 /** @defgroup ADCEx_range_verification ADC Extended Range Verification 3433 * in function of ADC resolution selected (12, 10, 8 or 6 bits) 3434 * @{ 3435 */ 3436 #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \ 3437 ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= (0x0FFFU))) || \ 3438 (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= (0x03FFU))) || \ 3439 (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= (0x00FFU))) || \ 3440 (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= (0x003FU))) ) 3441 /** 3442 * @} 3443 */ 3444 3445 /** @defgroup ADC_injected_nb_conv_verification ADC Injected Conversion Number Verification 3446 * @{ 3447 */ 3448 #define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (4U))) 3449 /** 3450 * @} 3451 */ 3452 3453 /** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification 3454 * @{ 3455 */ 3456 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (16U))) 3457 /** 3458 * @} 3459 */ 3460 3461 /** @defgroup ADC_regular_discontinuous_mode_number_verification ADC Regular Discontinuous Mode NumberVerification 3462 * @{ 3463 */ 3464 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U))) 3465 /** 3466 * @} 3467 */ 3468 3469 /** @defgroup ADC_calibration_factor_length_verification ADC Calibration Factor Length Verification 3470 * @{ 3471 */ 3472 /** 3473 * @brief Calibration factor length verification (7 bits maximum) 3474 * @param _Calibration_Factor_ Calibration factor value 3475 * @retval None 3476 */ 3477 #define IS_ADC_CALFACT(_Calibration_Factor_) ((_Calibration_Factor_) <= (0x7FU)) 3478 /** 3479 * @} 3480 */ 3481 3482 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ 3483 /* STM32F302xC || STM32F303xC || STM32F358xx || */ 3484 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ 3485 /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 3486 3487 3488 #if defined(STM32F373xC) || defined(STM32F378xx) 3489 3490 /** 3491 * @brief Verification of ADC state: enabled or disabled 3492 * @param __HANDLE__ ADC handle 3493 * @retval SET (ADC enabled) or RESET (ADC disabled) 3494 */ 3495 #define ADC_IS_ENABLE(__HANDLE__) \ 3496 ((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON ) \ 3497 ) ? SET : RESET) 3498 3499 /** 3500 * @brief Test if conversion trigger of regular group is software start 3501 * or external trigger. 3502 * @param __HANDLE__ ADC handle 3503 * @retval SET (software start) or RESET (external trigger) 3504 */ 3505 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ 3506 (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTSEL) == ADC_SOFTWARE_START) 3507 3508 /** 3509 * @brief Test if conversion trigger of injected group is software start 3510 * or external trigger. 3511 * @param __HANDLE__ ADC handle 3512 * @retval SET (software start) or RESET (external trigger) 3513 */ 3514 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ 3515 (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START) 3516 3517 /** 3518 * @brief Simultaneously clears and sets specific bits of the handle State 3519 * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 3520 * the first parameter is the ADC handle State, the second parameter is the 3521 * bit field to clear, the third and last parameter is the bit field to set. 3522 * @retval None 3523 */ 3524 #define ADC_STATE_CLR_SET MODIFY_REG 3525 3526 /** 3527 * @brief Clear ADC error code (set it to error code: "no error") 3528 * @param __HANDLE__ ADC handle 3529 * @retval None 3530 */ 3531 #define ADC_CLEAR_ERRORCODE(__HANDLE__) \ 3532 ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 3533 3534 /** 3535 * @brief Set ADC number of conversions into regular channel sequence length. 3536 * @param _NbrOfConversion_ Regular channel sequence length 3537 * @retval None 3538 */ 3539 #define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \ 3540 (((_NbrOfConversion_) - (uint8_t)1U) << 20U) 3541 3542 /** 3543 * @brief Set the ADC's sample time for channel numbers between 10 and 18. 3544 * @param _SAMPLETIME_ Sample time parameter. 3545 * @param _CHANNELNB_ Channel number. 3546 * @retval None 3547 */ 3548 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \ 3549 ((_SAMPLETIME_) << (3U * ((_CHANNELNB_) - 10U))) 3550 3551 /** 3552 * @brief Set the ADC's sample time for channel numbers between 0 and 9. 3553 * @param _SAMPLETIME_ Sample time parameter. 3554 * @param _CHANNELNB_ Channel number. 3555 * @retval None 3556 */ 3557 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \ 3558 ((_SAMPLETIME_) << (3U * (_CHANNELNB_))) 3559 3560 /** 3561 * @brief Set the selected regular channel rank for rank between 1 and 6. 3562 * @param _CHANNELNB_ Channel number. 3563 * @param _RANKNB_ Rank number. 3564 * @retval None 3565 */ 3566 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \ 3567 ((_CHANNELNB_) << (5U * ((_RANKNB_) - 1U))) 3568 3569 /** 3570 * @brief Set the selected regular channel rank for rank between 7 and 12. 3571 * @param _CHANNELNB_ Channel number. 3572 * @param _RANKNB_ Rank number. 3573 * @retval None 3574 */ 3575 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \ 3576 ((_CHANNELNB_) << (5U * ((_RANKNB_) - 7U))) 3577 3578 /** 3579 * @brief Set the selected regular channel rank for rank between 13 and 16. 3580 * @param _CHANNELNB_ Channel number. 3581 * @param _RANKNB_ Rank number. 3582 * @retval None 3583 */ 3584 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \ 3585 ((_CHANNELNB_) << (5U * ((_RANKNB_) - 13U))) 3586 3587 /** 3588 * @brief Set the injected sequence length. 3589 * @param _JSQR_JL_ Sequence length. 3590 * @retval None 3591 */ 3592 #define ADC_JSQR_JL_SHIFT(_JSQR_JL_) \ 3593 (((_JSQR_JL_) -1U) << 20U) 3594 3595 /** 3596 * @brief Set the selected injected channel rank 3597 * Note: on STM32F37x devices, channel rank position in JSQR register 3598 * is depending on total number of ranks selected into 3599 * injected sequencer (ranks sequence starting from 4-JL) 3600 * @param _CHANNELNB_ Channel number. 3601 * @param _RANKNB_ Rank number. 3602 * @param _JSQR_JL_ Sequence length. 3603 * @retval None 3604 */ 3605 #define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \ 3606 ((_CHANNELNB_) << (5U * ((4U - ((_JSQR_JL_) - (_RANKNB_))) - 1U))) 3607 3608 /** 3609 * @brief Enable ADC continuous conversion mode. 3610 * @param _CONTINUOUS_MODE_ Continuous mode. 3611 * @retval None 3612 */ 3613 #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \ 3614 ((_CONTINUOUS_MODE_) << 1U) 3615 3616 /** 3617 * @brief Configures the number of discontinuous conversions for the regular group channels. 3618 * @param _NBR_DISCONTINUOUS_CONV_ Number of discontinuous conversions. 3619 * @retval None 3620 */ 3621 #define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \ 3622 (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 13U) 3623 3624 /** 3625 * @brief Enable ADC scan mode to convert multiple ranks with sequencer. 3626 * @param _SCAN_MODE_ Scan conversion mode. 3627 * @retval None 3628 */ 3629 /* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */ 3630 /* is equivalent to ADC_SCAN_ENABLE. */ 3631 #define ADC_CR1_SCAN_SET(_SCAN_MODE_) \ 3632 (( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE) \ 3633 )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \ 3634 ) 3635 3636 /** 3637 * @brief Calibration factor in differential mode to be set into calibration register 3638 * @param _Calibration_Factor_ Calibration factor value 3639 * @retval None 3640 */ 3641 #define ADC_CALFACT_DIFF_SET(_Calibration_Factor_) \ 3642 ((_Calibration_Factor_) << 16U) 3643 3644 /** 3645 * @brief Calibration factor in differential mode to be retrieved from calibration register 3646 * @param _Calibration_Factor_ Calibration factor value 3647 * @retval None 3648 */ 3649 #define ADC_CALFACT_DIFF_GET(_Calibration_Factor_) \ 3650 ((_Calibration_Factor_) >> 16U) 3651 3652 3653 /** 3654 * @brief Get the maximum ADC conversion cycles on all channels. 3655 * Returns the selected sampling time + conversion time (12.5 ADC clock cycles) 3656 * Approximation of sampling time within 4 ranges, returns the highest value: 3657 * below 7.5 cycles {1.5 cycle; 7.5 cycles}, 3658 * between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles} 3659 * between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles} 3660 * equal to 239.5 cycles 3661 * Unit: ADC clock cycles 3662 * @param __HANDLE__ ADC handle 3663 * @retval ADC conversion cycles on all channels 3664 */ 3665 #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ 3666 (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \ 3667 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \ 3668 \ 3669 (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \ 3670 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ? \ 3671 ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \ 3672 : \ 3673 ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \ 3674 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) || \ 3675 ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && \ 3676 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ? \ 3677 ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \ 3678 ) 3679 3680 /** 3681 * @brief Get the total ADC clock prescaler (APB2 prescaler x ADC prescaler) 3682 * from system clock configuration register. 3683 * Approximation within 3 ranges, returns the higher value: 3684 * total prescaler minimum: 2 (ADC presc 2, APB2 presc 0) 3685 * total prescaler 32 (ADC presc 0 and APB2 presc all, or 3686 * ADC presc {4, 6, 8} and APB2 presc {0, 2, 4}) 3687 * total prescaler maximum: 128 (ADC presc {4, 6, 8} and APB2 presc {8, 16}) 3688 * Unit: none (prescaler factor) 3689 * @retval ADC and APB2 prescaler factor 3690 */ 3691 #define ADC_CLOCK_PRESCALER_RANGE() \ 3692 (( (RCC->CFGR & (RCC_CFGR_ADCPRE_1 | RCC_CFGR_ADCPRE_0)) == RESET) ? \ 3693 (( (RCC->CFGR & RCC_CFGR_PPRE2_2) == RESET) ? 2 : 32U ) \ 3694 : \ 3695 (( (RCC->CFGR & RCC_CFGR_PPRE2_1) == RESET) ? 32 : 128U ) \ 3696 ) 3697 3698 /** 3699 * @brief Get the ADC clock prescaler from system clock configuration register. 3700 * @retval None 3701 */ 3702 #define ADC_GET_CLOCK_PRESCALER() (((RCC->CFGR & RCC_CFGR_ADCPRE) >> 14U) +1U) 3703 3704 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ 3705 ((ALIGN) == ADC_DATAALIGN_LEFT) ) 3706 3707 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \ 3708 ((SCAN_MODE) == ADC_SCAN_ENABLE) ) 3709 3710 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ 3711 ((CHANNEL) == ADC_CHANNEL_1) || \ 3712 ((CHANNEL) == ADC_CHANNEL_2) || \ 3713 ((CHANNEL) == ADC_CHANNEL_3) || \ 3714 ((CHANNEL) == ADC_CHANNEL_4) || \ 3715 ((CHANNEL) == ADC_CHANNEL_5) || \ 3716 ((CHANNEL) == ADC_CHANNEL_6) || \ 3717 ((CHANNEL) == ADC_CHANNEL_7) || \ 3718 ((CHANNEL) == ADC_CHANNEL_8) || \ 3719 ((CHANNEL) == ADC_CHANNEL_9) || \ 3720 ((CHANNEL) == ADC_CHANNEL_10) || \ 3721 ((CHANNEL) == ADC_CHANNEL_11) || \ 3722 ((CHANNEL) == ADC_CHANNEL_12) || \ 3723 ((CHANNEL) == ADC_CHANNEL_13) || \ 3724 ((CHANNEL) == ADC_CHANNEL_14) || \ 3725 ((CHANNEL) == ADC_CHANNEL_15) || \ 3726 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \ 3727 ((CHANNEL) == ADC_CHANNEL_VREFINT) || \ 3728 ((CHANNEL) == ADC_CHANNEL_VBAT) ) 3729 3730 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ 3731 ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ 3732 ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \ 3733 ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \ 3734 ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \ 3735 ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \ 3736 ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \ 3737 ((TIME) == ADC_SAMPLETIME_239CYCLES_5) ) 3738 3739 #define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \ 3740 ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \ 3741 ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \ 3742 ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \ 3743 ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \ 3744 ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \ 3745 ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \ 3746 ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \ 3747 ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \ 3748 ((CHANNEL) == ADC_REGULAR_RANK_10) || \ 3749 ((CHANNEL) == ADC_REGULAR_RANK_11) || \ 3750 ((CHANNEL) == ADC_REGULAR_RANK_12) || \ 3751 ((CHANNEL) == ADC_REGULAR_RANK_13) || \ 3752 ((CHANNEL) == ADC_REGULAR_RANK_14) || \ 3753 ((CHANNEL) == ADC_REGULAR_RANK_15) || \ 3754 ((CHANNEL) == ADC_REGULAR_RANK_16) ) 3755 3756 #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 3757 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) ) 3758 3759 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ 3760 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ 3761 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ 3762 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T19_TRGO) || \ 3763 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T19_CC3) || \ 3764 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T19_CC4) || \ 3765 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ 3766 ((REGTRIG) == ADC_SOFTWARE_START) ) 3767 3768 #define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ 3769 ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) ) 3770 3771 #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ 3772 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ 3773 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ 3774 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ 3775 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T19_CC1) || \ 3776 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T19_CC2) || \ 3777 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ 3778 ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) ) 3779 3780 #define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \ 3781 ((CHANNEL) == ADC_INJECTED_RANK_2) || \ 3782 ((CHANNEL) == ADC_INJECTED_RANK_3) || \ 3783 ((CHANNEL) == ADC_INJECTED_RANK_4) ) 3784 3785 #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ 3786 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 3787 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ 3788 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ 3789 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \ 3790 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ 3791 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) 3792 3793 #define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \ 3794 ((CONVERSION) == ADC_INJECTED_GROUP) || \ 3795 ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) ) 3796 3797 #define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT) 3798 3799 /** @defgroup ADCEx_range_verification ADC Extended Range Verification 3800 * For a unique ADC resolution: 12 bits 3801 * @{ 3802 */ 3803 #define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= (0x0FFFU)) 3804 /** 3805 * @} 3806 */ 3807 3808 /** @defgroup ADC_injected_nb_conv_verification ADC Injected Conversion Number Verification 3809 * @{ 3810 */ 3811 #define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (4U))) 3812 /** 3813 * @} 3814 */ 3815 3816 /** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification 3817 * @{ 3818 */ 3819 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (16U))) 3820 /** 3821 * @} 3822 */ 3823 3824 /** @defgroup ADC_regular_discontinuous_mode_number_verification ADC Regular Discontinuous Mode NumberVerification 3825 * @{ 3826 */ 3827 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U))) 3828 /** 3829 * @} 3830 */ 3831 3832 #endif /* STM32F373xC || STM32F378xx */ 3833 /** 3834 * @} 3835 */ 3836 3837 3838 /* Exported functions --------------------------------------------------------*/ 3839 /** @addtogroup ADCEx_Exported_Functions ADCEx Exported Functions 3840 * @{ 3841 */ 3842 3843 /* Initialization/de-initialization functions *********************************/ 3844 3845 /** @addtogroup ADCEx_Exported_Functions_Group2 ADCEx Input and Output operation functions 3846 * @{ 3847 */ 3848 /* I/O operation functions ****************************************************/ 3849 3850 /* ADC calibration */ 3851 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ 3852 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ 3853 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ 3854 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 3855 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(struct __ADC_HandleTypeDef* hadc, uint32_t SingleDiff); 3856 uint32_t HAL_ADCEx_Calibration_GetValue(struct __ADC_HandleTypeDef *hadc, uint32_t SingleDiff); 3857 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(struct __ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor); 3858 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ 3859 /* STM32F302xC || STM32F303xC || STM32F358xx || */ 3860 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ 3861 /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 3862 3863 #if defined(STM32F373xC) || defined(STM32F378xx) 3864 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(struct __ADC_HandleTypeDef* hadc); 3865 #endif /* STM32F373xC || STM32F378xx */ 3866 3867 /* Blocking mode: Polling */ 3868 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(struct __ADC_HandleTypeDef* hadc); 3869 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(struct __ADC_HandleTypeDef* hadc); 3870 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(struct __ADC_HandleTypeDef* hadc, uint32_t Timeout); 3871 3872 /* Non-blocking mode: Interruption */ 3873 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(struct __ADC_HandleTypeDef* hadc); 3874 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(struct __ADC_HandleTypeDef* hadc); 3875 3876 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ 3877 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ 3878 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ 3879 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 3880 /* ADC multimode */ 3881 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(struct __ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 3882 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(struct __ADC_HandleTypeDef *hadc); 3883 uint32_t HAL_ADCEx_MultiModeGetValue(struct __ADC_HandleTypeDef *hadc); 3884 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ 3885 /* STM32F302xC || STM32F303xC || STM32F358xx || */ 3886 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ 3887 /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 3888 3889 /* ADC group regular stop conversion without impacting group injected */ 3890 /* Blocking mode: Polling */ 3891 HAL_StatusTypeDef HAL_ADCEx_RegularStop(struct __ADC_HandleTypeDef* hadc); 3892 /* Non-blocking mode: Interruption */ 3893 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(struct __ADC_HandleTypeDef* hadc); 3894 /* Non-blocking mode: DMA */ 3895 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(struct __ADC_HandleTypeDef* hadc); 3896 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ 3897 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ 3898 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ 3899 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 3900 /* ADC multimode */ 3901 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(struct __ADC_HandleTypeDef *hadc); 3902 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ 3903 /* STM32F302xC || STM32F303xC || STM32F358xx || */ 3904 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ 3905 /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 3906 3907 /* ADC retrieve conversion value intended to be used with polling or interruption */ 3908 uint32_t HAL_ADCEx_InjectedGetValue(struct __ADC_HandleTypeDef* hadc, uint32_t InjectedRank); 3909 3910 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ 3911 void HAL_ADCEx_InjectedConvCpltCallback(struct __ADC_HandleTypeDef* hadc); 3912 3913 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ 3914 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ 3915 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ 3916 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 3917 void HAL_ADCEx_InjectedQueueOverflowCallback(struct __ADC_HandleTypeDef* hadc); 3918 void HAL_ADCEx_LevelOutOfWindow2Callback(struct __ADC_HandleTypeDef* hadc); 3919 void HAL_ADCEx_LevelOutOfWindow3Callback(struct __ADC_HandleTypeDef* hadc); 3920 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ 3921 /* STM32F302xC || STM32F303xC || STM32F358xx || */ 3922 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ 3923 /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 3924 /** 3925 * @} 3926 */ 3927 3928 /** @addtogroup ADCEx_Exported_Functions_Group3 ADCEx Peripheral Control functions 3929 * @{ 3930 */ 3931 /* Peripheral Control functions ***********************************************/ 3932 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(struct __ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); 3933 3934 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ 3935 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ 3936 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ 3937 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) 3938 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(struct __ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); 3939 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ 3940 /* STM32F302xC || STM32F303xC || STM32F358xx || */ 3941 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ 3942 /* STM32F301x8 || STM32F302x8 || STM32F318xx */ 3943 /** 3944 * @} 3945 */ 3946 3947 /** 3948 * @} 3949 */ 3950 3951 /** 3952 * @} 3953 */ 3954 3955 /** 3956 * @} 3957 */ 3958 3959 #ifdef __cplusplus 3960 } 3961 #endif 3962 3963 #endif /*__STM32F3xx_ADC_H */ 3964 3965 3966
