1 /* 2 * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdbool.h> 9 #include <stdint.h> 10 #include "sdkconfig.h" 11 #include "soc/soc_caps.h" 12 #include "soc/clk_tree_defs.h" 13 #include "esp_attr.h" 14 15 /** 16 * @brief ADC unit 17 */ 18 typedef enum { 19 ADC_UNIT_1, ///< SAR ADC 1 20 ADC_UNIT_2, ///< SAR ADC 2 21 } adc_unit_t; 22 23 /** 24 * @brief ADC channels 25 */ 26 typedef enum { 27 ADC_CHANNEL_0, ///< ADC channel 28 ADC_CHANNEL_1, ///< ADC channel 29 ADC_CHANNEL_2, ///< ADC channel 30 ADC_CHANNEL_3, ///< ADC channel 31 ADC_CHANNEL_4, ///< ADC channel 32 ADC_CHANNEL_5, ///< ADC channel 33 ADC_CHANNEL_6, ///< ADC channel 34 ADC_CHANNEL_7, ///< ADC channel 35 ADC_CHANNEL_8, ///< ADC channel 36 ADC_CHANNEL_9, ///< ADC channel 37 } adc_channel_t; 38 39 /** 40 * @brief ADC attenuation parameter. Different parameters determine the range of the ADC. 41 */ 42 typedef enum { 43 ADC_ATTEN_DB_0 = 0, ///<No input attenuation, ADC can measure up to approx. 44 ADC_ATTEN_DB_2_5 = 1, ///<The input voltage of ADC will be attenuated extending the range of measurement by about 2.5 dB (1.33 x) 45 ADC_ATTEN_DB_6 = 2, ///<The input voltage of ADC will be attenuated extending the range of measurement by about 6 dB (2 x) 46 ADC_ATTEN_DB_11 = 3, ///<The input voltage of ADC will be attenuated extending the range of measurement by about 11 dB (3.55 x) 47 } adc_atten_t; 48 49 typedef enum { 50 ADC_BITWIDTH_DEFAULT = 0, ///< Default ADC output bits, max supported width will be selected 51 ADC_BITWIDTH_9 = 9, ///< ADC output width is 9Bit 52 ADC_BITWIDTH_10 = 10, ///< ADC output width is 10Bit 53 ADC_BITWIDTH_11 = 11, ///< ADC output width is 11Bit 54 ADC_BITWIDTH_12 = 12, ///< ADC output width is 12Bit 55 ADC_BITWIDTH_13 = 13, ///< ADC output width is 13Bit 56 } adc_bitwidth_t; 57 58 typedef enum { 59 ADC_ULP_MODE_DISABLE = 0, ///< ADC ULP mode is disabled 60 ADC_ULP_MODE_FSM = 1, ///< ADC is controlled by ULP FSM 61 ADC_ULP_MODE_RISCV = 2, ///< ADC is controlled by ULP RISCV 62 } adc_ulp_mode_t; 63 64 /** 65 * @brief ADC digital controller (DMA mode) work mode. 66 */ 67 typedef enum { 68 ADC_CONV_SINGLE_UNIT_1 = 1, ///< Only use ADC1 for conversion 69 ADC_CONV_SINGLE_UNIT_2 = 2, ///< Only use ADC2 for conversion 70 ADC_CONV_BOTH_UNIT = 3, ///< Use Both ADC1 and ADC2 for conversion simultaneously 71 ADC_CONV_ALTER_UNIT = 7, ///< Use both ADC1 and ADC2 for conversion by turn. e.g. ADC1 -> ADC2 -> ADC1 -> ADC2 ..... 72 } adc_digi_convert_mode_t; 73 74 /** 75 * @brief ADC digital controller (DMA mode) output data format option. 76 */ 77 typedef enum { 78 ADC_DIGI_OUTPUT_FORMAT_TYPE1, ///< See `adc_digi_output_data_t.type1` 79 ADC_DIGI_OUTPUT_FORMAT_TYPE2, ///< See `adc_digi_output_data_t.type2` 80 } adc_digi_output_format_t; 81 82 #if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED 83 typedef soc_periph_adc_digi_clk_src_t adc_oneshot_clk_src_t; ///< Clock source type of oneshot mode which uses digital controller 84 typedef soc_periph_adc_digi_clk_src_t adc_continuous_clk_src_t; ///< Clock source type of continuous mode which uses digital controller 85 #elif SOC_ADC_RTC_CTRL_SUPPORTED 86 typedef soc_periph_adc_rtc_clk_src_t adc_oneshot_clk_src_t; ///< Clock source type of oneshot mode which uses RTC controller 87 typedef soc_periph_adc_digi_clk_src_t adc_continuous_clk_src_t; ///< Clock source type of continuous mode which uses digital controller 88 #endif 89 90 /** 91 * @brief ADC digital controller pattern configuration 92 */ 93 typedef struct { 94 uint8_t atten; ///< Attenuation of this ADC channel 95 uint8_t channel; ///< ADC channel 96 uint8_t unit; ///< ADC unit 97 uint8_t bit_width; ///< ADC output bit width 98 } adc_digi_pattern_config_t; 99 100 /** 101 * @brief ADC IIR Filter ID 102 */ 103 typedef enum { 104 ADC_DIGI_IIR_FILTER_0, ///< Filter 0 105 ADC_DIGI_IIR_FILTER_1, ///< Filter 1 106 } adc_digi_iir_filter_t; 107 108 /** 109 * @brief IIR Filter Coefficient 110 */ 111 typedef enum { 112 ADC_DIGI_IIR_FILTER_COEFF_2, ///< The filter coefficient is 2 113 ADC_DIGI_IIR_FILTER_COEFF_4, ///< The filter coefficient is 4 114 ADC_DIGI_IIR_FILTER_COEFF_8, ///< The filter coefficient is 8 115 ADC_DIGI_IIR_FILTER_COEFF_16, ///< The filter coefficient is 16 116 ADC_DIGI_IIR_FILTER_COEFF_64, ///< The filter coefficient is 64 117 } adc_digi_iir_filter_coeff_t; 118 119 /*--------------------------------------------------------------- 120 Output Format 121 ---------------------------------------------------------------*/ 122 #if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 123 /** 124 * @brief ADC digital controller (DMA mode) output data format. 125 * Used to analyze the acquired ADC (DMA) data. 126 * @note ESP32: Only `type1` is valid. ADC2 does not support DMA mode. 127 * @note ESP32-S2: Member `channel` can be used to judge the validity of the ADC data, 128 * because the role of the arbiter may get invalid ADC data. 129 */ 130 typedef struct { 131 union { 132 struct { 133 uint16_t data: 12; /*!<ADC real output data info. Resolution: 12 bit. */ 134 uint16_t channel: 4; /*!<ADC channel index info. */ 135 } type1; /*!<ADC type1 */ 136 struct { 137 uint16_t data: 11; /*!<ADC real output data info. Resolution: 11 bit. */ 138 uint16_t channel: 4; /*!<ADC channel index info. For ESP32-S2: 139 If (channel < ADC_CHANNEL_MAX), The data is valid. 140 If (channel > ADC_CHANNEL_MAX), The data is invalid. */ 141 uint16_t unit: 1; /*!<ADC unit index info. 0: ADC1; 1: ADC2. */ 142 } type2; /*!<When the configured output format is 11bit.*/ 143 uint16_t val; /*!<Raw data value */ 144 }; 145 } adc_digi_output_data_t; 146 147 #elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 148 /** 149 * @brief ADC digital controller (DMA mode) output data format. 150 * Used to analyze the acquired ADC (DMA) data. 151 */ 152 typedef struct { 153 union { 154 struct { 155 uint32_t data: 12; /*!<ADC real output data info. Resolution: 12 bit. */ 156 uint32_t reserved12: 1; /*!<Reserved12. */ 157 uint32_t channel: 3; /*!<ADC channel index info. 158 If (channel < ADC_CHANNEL_MAX), The data is valid. 159 If (channel > ADC_CHANNEL_MAX), The data is invalid. */ 160 uint32_t unit: 1; /*!<ADC unit index info. 0: ADC1; 1: ADC2. */ 161 uint32_t reserved17_31: 15; /*!<Reserved17. */ 162 } type2; /*!<When the configured output format is 12bit. */ 163 uint32_t val; /*!<Raw data value */ 164 }; 165 } adc_digi_output_data_t; 166 167 #elif CONFIG_IDF_TARGET_ESP32S3 168 /** 169 * @brief ADC digital controller (DMA mode) output data format. 170 * Used to analyze the acquired ADC (DMA) data. 171 */ 172 typedef struct { 173 union { 174 struct { 175 uint32_t data: 12; /*!<ADC real output data info. Resolution: 12 bit. */ 176 uint32_t reserved12: 1; /*!<Reserved12. */ 177 uint32_t channel: 4; /*!<ADC channel index info. 178 If (channel < ADC_CHANNEL_MAX), The data is valid. 179 If (channel > ADC_CHANNEL_MAX), The data is invalid. */ 180 uint32_t unit: 1; /*!<ADC unit index info. 0: ADC1; 1: ADC2. */ 181 uint32_t reserved17_31: 14; /*!<Reserved17. */ 182 } type2; /*!<When the configured output format is 12bit. */ 183 uint32_t val; /*!<Raw data value */ 184 }; 185 } adc_digi_output_data_t; 186 187 #elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 188 /** 189 * @brief ADC digital controller (DMA mode) output data format. 190 * Used to analyze the acquired ADC (DMA) data. 191 */ 192 typedef struct { 193 union { 194 struct { 195 uint32_t data: 12; /*!<ADC real output data info. Resolution: 12 bit. */ 196 uint32_t reserved12: 1; /*!<Reserved12. */ 197 uint32_t channel: 4; /*!<ADC channel index info. 198 If (channel < ADC_CHANNEL_MAX), The data is valid. 199 If (channel > ADC_CHANNEL_MAX), The data is invalid. */ 200 uint32_t reserved17_31: 15; /*!<Reserved 17-31. */ 201 } type2; /*!<When the configured output format is 12bit. */ 202 uint32_t val; /*!<Raw data value */ 203 }; 204 } adc_digi_output_data_t; 205 206 #endif 207 208 #if CONFIG_IDF_TARGET_ESP32S2 209 /** 210 * @brief ADC digital controller (DMA mode) clock system setting. 211 * Calculation formula: controller_clk = (`APLL` or `APB`) / (div_num + div_a / div_b + 1). 212 * 213 * @note: The clocks of the DAC digital controller use the ADC digital controller clock divider. 214 */ 215 typedef struct { 216 bool use_apll; /*!<true: use APLL clock; false: use APB clock. */ 217 uint32_t div_num; /*!<Division factor. Range: 0 ~ 255. 218 Note: When a higher frequency clock is used (the division factor is less than 9), 219 the ADC reading value will be slightly offset. */ 220 uint32_t div_b; /*!<Division factor. Range: 1 ~ 63. */ 221 uint32_t div_a; /*!<Division factor. Range: 0 ~ 63. */ 222 } adc_digi_clk_t; 223 #endif 224
