1 /***************************************************************************//** 2 * \file cyip_mxs40adcmic.h 3 * 4 * \brief 5 * MXS40ADCMIC IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_MXS40ADCMIC_H_ 28 #define _CYIP_MXS40ADCMIC_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * MXS40ADCMIC 34 *******************************************************************************/ 35 36 #define MXS40ADCMIC_SECTION_SIZE 0x00010000UL 37 38 /** 39 * \brief ADC (MXS40ADCMIC) 40 */ 41 typedef struct { 42 __IOM uint32_t ADCMIC_CTRL; /*!< 0x00000000 Control the operation of the ADCMIC block including clock 43 generation,clock selection and pdm data latching */ 44 __IOM uint32_t ADCMIC_PAD_CTRL; /*!< 0x00000004 Control the pads in the ADCMIC block */ 45 __IOM uint32_t ADCMIC_FIFO_CTRL; /*!< 0x00000008 Controls the operation of the fifo */ 46 __IOM uint32_t ADCMIC_LFSR_CTRL; /*!< 0x0000000C Controls the operation of the LFSR */ 47 __IM uint32_t ADCMIC_TRIGGER; /*!< 0x00000010 Register to control Trigger */ 48 __IOM uint32_t ADCMIC_TRIGGER_CLR; /*!< 0x00000014 Register to clear Trigger */ 49 __IOM uint32_t ADCMIC_TRIGGER_SET; /*!< 0x00000018 Register to set Trigger */ 50 __IOM uint32_t ADCMIC_TRIGGER_MASK; /*!< 0x0000001C Register to mask Trigger */ 51 __IOM uint32_t ADCMIC_INTR; /*!< 0x00000020 Register to cause Interrupt */ 52 __IOM uint32_t ADCMIC_INTR_SET; /*!< 0x00000024 Register to set Interrupt */ 53 __IOM uint32_t ADCMIC_INTR_MASK; /*!< 0x00000028 Register to mask Interrupt */ 54 __IM uint32_t ADCMIC_INTR_MASKED; /*!< 0x0000002C Register to and intr_mask Intr to crreate the interrupt */ 55 __IOM uint32_t ADCMIC_TRIG_INTRPT_TIMER_CTRL; /*!< 0x00000030 Controls the timer for the generation of triggers and 56 interrupts for dc measurement in the block */ 57 __IOM uint32_t ADCMIC_TP; /*!< 0x00000034 Data used for DFT test for setting and observing test points */ 58 __IM uint32_t RESERVED[2]; 59 __IM uint32_t ADCMIC_DATA; /*!< 0x00000040 N/A */ 60 __IM uint32_t RESERVED1[47]; 61 __IOM uint32_t ADC_CLK_CTRL; /*!< 0x00000100 Control the clocks in the ADC block */ 62 __IOM uint32_t ADC_GPIO_CTRL; /*!< 0x00000104 GPIO control for ADC */ 63 __IOM uint32_t ADC_PD_CTRL; /*!< 0x00000108 Control the power down controls in the ADC block. */ 64 __IOM uint32_t ADC_BG_REF_CTRL; /*!< 0x0000010C Control the Band Gap and Reference Voltages of the ADC */ 65 __IOM uint32_t ADC_CORE_CTRL; /*!< 0x00000110 Control the clocks in the ADC block */ 66 __IOM uint32_t ADC_MIC_BIAS_PGA_CTRL; /*!< 0x00000114 Control the BIAS and PGA of ADC block */ 67 __IOM uint32_t ADC_SPARE; /*!< 0x00000118 Spare registers in the ADC block */ 68 __IM uint32_t RESERVED2[57]; 69 __IOM uint32_t AUXADC_CTRL; /*!< 0x00000200 Register to control AuxAdcDecim operation */ 70 __IOM uint32_t AUXADC_CIC_CTRL; /*!< 0x00000204 Register to control CIC operation in AuxAdcDecim block */ 71 __IOM uint32_t AUXADC_OVERRIDE; /*!< 0x00000208 Register that holds the override values for AuxAdcDecim block */ 72 __IOM uint32_t AUXADC_DF3_COEFF; /*!< 0x0000020C Register that controls the RAM operation for writing DF3 73 Coefficients into the RAM */ 74 __IOM uint32_t AUXADC_BIQUAD0_COEFF_0; /*!< 0x00000210 Register holding the coefficients for BIQUAD0 operation. */ 75 __IOM uint32_t AUXADC_BIQUAD0_COEFF_1; /*!< 0x00000214 Register holding the coefficients for BIQUAD0 operation. */ 76 __IOM uint32_t AUXADC_BIQUAD0_COEFF_2; /*!< 0x00000218 Register holding the coefficients for BIQUAD0 operation. */ 77 __IOM uint32_t AUXADC_BIQUAD1_COEFF_0; /*!< 0x0000021C Register holding the coefficients for BIQUAD1 operation. */ 78 __IOM uint32_t AUXADC_BIQUAD1_COEFF_1; /*!< 0x00000220 Register holding the coefficients for BIQUAD1 operation. */ 79 __IOM uint32_t AUXADC_BIQUAD1_COEFF_2; /*!< 0x00000224 Register holding the coefficients for BIQUAD1 operation. */ 80 __IOM uint32_t AUXADC_BIQUAD2_COEFF_0; /*!< 0x00000228 Register holding the coefficients for BIQUAD2 operation. */ 81 __IOM uint32_t AUXADC_BIQUAD2_COEFF_1; /*!< 0x0000022C Register holding the coefficients for BIQUAD2 operation. */ 82 __IOM uint32_t AUXADC_BIQUAD2_COEFF_2; /*!< 0x00000230 Register holding the coefficients for BIQUAD2 operation. */ 83 __IOM uint32_t AUXADC_BIQUAD3_COEFF_0; /*!< 0x00000234 Register holding the coefficients for BIQUAD3 operation. */ 84 __IOM uint32_t AUXADC_BIQUAD3_COEFF_1; /*!< 0x00000238 Register holding the coefficients for BIQUAD3 operation. */ 85 __IOM uint32_t AUXADC_BIQUAD3_COEFF_2; /*!< 0x0000023C Register holding the coefficients for BIQUAD3 operation. */ 86 __IOM uint32_t AUXADC_BIQUAD4_COEFF_0; /*!< 0x00000240 Register holding the coefficients for BIQUAD4 operation. */ 87 __IOM uint32_t AUXADC_BIQUAD4_COEFF_1; /*!< 0x00000244 Register holding the coefficients for BIQUAD4 operation. */ 88 __IOM uint32_t AUXADC_BIQUAD4_COEFF_2; /*!< 0x00000248 Register holding the coefficients for BIQUAD4 operation. */ 89 __IM uint32_t RESERVED3; 90 __IOM uint32_t AUXADC_CIC_STATUS; /*!< 0x00000250 Status of the CIC in AuxAdcDecim block */ 91 __IM uint32_t AUXADC_DF1_STATUS; /*!< 0x00000254 Status of the DF1 FIR Filter in AuxAdcDecim block */ 92 __IM uint32_t AUXADC_DF2_STATUS; /*!< 0x00000258 Status of the DF2 FIR Filter in AuxAdcDecim block */ 93 __IM uint32_t AUXADC_DF3_STATUS; /*!< 0x0000025C Status of the DF3 FIR Filter in AuxAdcDecim block */ 94 __IM uint32_t AUXADC_BIQUAD_STATUS; /*!< 0x00000260 Status of the BIQUAD IIR Filter in AuxAdcDecim block */ 95 } MXS40ADCMIC_Type; /*!< Size = 612 (0x264) */ 96 97 98 /* MXS40ADCMIC.ADCMIC_CTRL */ 99 #define MXS40ADCMIC_ADCMIC_CTRL_ADC_DIV_RATIO_Pos 0UL 100 #define MXS40ADCMIC_ADCMIC_CTRL_ADC_DIV_RATIO_Msk 0x1FUL 101 #define MXS40ADCMIC_ADCMIC_CTRL_PDM_DIV_RATIO_Pos 5UL 102 #define MXS40ADCMIC_ADCMIC_CTRL_PDM_DIV_RATIO_Msk 0x3E0UL 103 #define MXS40ADCMIC_ADCMIC_CTRL_ADC_RESET_Pos 10UL 104 #define MXS40ADCMIC_ADCMIC_CTRL_ADC_RESET_Msk 0x400UL 105 #define MXS40ADCMIC_ADCMIC_CTRL_PDM_LATCH_NEG_EDGE_Pos 11UL 106 #define MXS40ADCMIC_ADCMIC_CTRL_PDM_LATCH_NEG_EDGE_Msk 0x800UL 107 #define MXS40ADCMIC_ADCMIC_CTRL_PDM_DATA_Pos 12UL 108 #define MXS40ADCMIC_ADCMIC_CTRL_PDM_DATA_Msk 0x1000UL 109 #define MXS40ADCMIC_ADCMIC_CTRL_CLK_GATE_EN_Pos 13UL 110 #define MXS40ADCMIC_ADCMIC_CTRL_CLK_GATE_EN_Msk 0x6000UL 111 #define MXS40ADCMIC_ADCMIC_CTRL_PDM_LATCH_DELAY_Pos 15UL 112 #define MXS40ADCMIC_ADCMIC_CTRL_PDM_LATCH_DELAY_Msk 0xF8000UL 113 #define MXS40ADCMIC_ADCMIC_CTRL_CLKS_ACTIVE_ADC_Pos 20UL 114 #define MXS40ADCMIC_ADCMIC_CTRL_CLKS_ACTIVE_ADC_Msk 0x1F00000UL 115 #define MXS40ADCMIC_ADCMIC_CTRL_CLKS_ACTIVE_PDM_Pos 25UL 116 #define MXS40ADCMIC_ADCMIC_CTRL_CLKS_ACTIVE_PDM_Msk 0x1E000000UL 117 #define MXS40ADCMIC_ADCMIC_CTRL_ADCMIC_EN_Pos 31UL 118 #define MXS40ADCMIC_ADCMIC_CTRL_ADCMIC_EN_Msk 0x80000000UL 119 /* MXS40ADCMIC.ADCMIC_PAD_CTRL */ 120 #define MXS40ADCMIC_ADCMIC_PAD_CTRL_CLK_PDM_OE_Pos 0UL 121 #define MXS40ADCMIC_ADCMIC_PAD_CTRL_CLK_PDM_OE_Msk 0x1UL 122 /* MXS40ADCMIC.ADCMIC_FIFO_CTRL */ 123 #define MXS40ADCMIC_ADCMIC_FIFO_CTRL_PGMBLE_FULL_Pos 0UL 124 #define MXS40ADCMIC_ADCMIC_FIFO_CTRL_PGMBLE_FULL_Msk 0x3FUL 125 #define MXS40ADCMIC_ADCMIC_FIFO_CTRL_PGMBLE_EMPTY_Pos 8UL 126 #define MXS40ADCMIC_ADCMIC_FIFO_CTRL_PGMBLE_EMPTY_Msk 0x3F00UL 127 #define MXS40ADCMIC_ADCMIC_FIFO_CTRL_FIFO_RESET_Pos 14UL 128 #define MXS40ADCMIC_ADCMIC_FIFO_CTRL_FIFO_RESET_Msk 0xC000UL 129 #define MXS40ADCMIC_ADCMIC_FIFO_CTRL_FIFO_STATUS_Pos 16UL 130 #define MXS40ADCMIC_ADCMIC_FIFO_CTRL_FIFO_STATUS_Msk 0xFF0000UL 131 #define MXS40ADCMIC_ADCMIC_FIFO_CTRL_FIFO_WR_BYPASS_Pos 31UL 132 #define MXS40ADCMIC_ADCMIC_FIFO_CTRL_FIFO_WR_BYPASS_Msk 0x80000000UL 133 /* MXS40ADCMIC.ADCMIC_LFSR_CTRL */ 134 #define MXS40ADCMIC_ADCMIC_LFSR_CTRL_LFSR_EN_Pos 0UL 135 #define MXS40ADCMIC_ADCMIC_LFSR_CTRL_LFSR_EN_Msk 0x1UL 136 #define MXS40ADCMIC_ADCMIC_LFSR_CTRL_LFSR_SET_Pos 1UL 137 #define MXS40ADCMIC_ADCMIC_LFSR_CTRL_LFSR_SET_Msk 0x2UL 138 #define MXS40ADCMIC_ADCMIC_LFSR_CTRL_LFSR_MODE_Pos 2UL 139 #define MXS40ADCMIC_ADCMIC_LFSR_CTRL_LFSR_MODE_Msk 0xCUL 140 #define MXS40ADCMIC_ADCMIC_LFSR_CTRL_LFSR_VALID_CNTR_LIMIT_Pos 4UL 141 #define MXS40ADCMIC_ADCMIC_LFSR_CTRL_LFSR_VALID_CNTR_LIMIT_Msk 0x3FF0UL 142 #define MXS40ADCMIC_ADCMIC_LFSR_CTRL_LFSR_CLR_Pos 15UL 143 #define MXS40ADCMIC_ADCMIC_LFSR_CTRL_LFSR_CLR_Msk 0x8000UL 144 #define MXS40ADCMIC_ADCMIC_LFSR_CTRL_LFSR_TAPS_Pos 16UL 145 #define MXS40ADCMIC_ADCMIC_LFSR_CTRL_LFSR_TAPS_Msk 0xFFFF0000UL 146 /* MXS40ADCMIC.ADCMIC_TRIGGER */ 147 #define MXS40ADCMIC_ADCMIC_TRIGGER_TR_DC_Pos 0UL 148 #define MXS40ADCMIC_ADCMIC_TRIGGER_TR_DC_Msk 0x1UL 149 #define MXS40ADCMIC_ADCMIC_TRIGGER_TR_DATA_Pos 1UL 150 #define MXS40ADCMIC_ADCMIC_TRIGGER_TR_DATA_Msk 0x2UL 151 /* MXS40ADCMIC.ADCMIC_TRIGGER_CLR */ 152 #define MXS40ADCMIC_ADCMIC_TRIGGER_CLR_TR_DC_Pos 0UL 153 #define MXS40ADCMIC_ADCMIC_TRIGGER_CLR_TR_DC_Msk 0x1UL 154 #define MXS40ADCMIC_ADCMIC_TRIGGER_CLR_TR_DATA_Pos 1UL 155 #define MXS40ADCMIC_ADCMIC_TRIGGER_CLR_TR_DATA_Msk 0x2UL 156 /* MXS40ADCMIC.ADCMIC_TRIGGER_SET */ 157 #define MXS40ADCMIC_ADCMIC_TRIGGER_SET_TR_DC_Pos 0UL 158 #define MXS40ADCMIC_ADCMIC_TRIGGER_SET_TR_DC_Msk 0x1UL 159 #define MXS40ADCMIC_ADCMIC_TRIGGER_SET_TR_DATA_Pos 1UL 160 #define MXS40ADCMIC_ADCMIC_TRIGGER_SET_TR_DATA_Msk 0x2UL 161 /* MXS40ADCMIC.ADCMIC_TRIGGER_MASK */ 162 #define MXS40ADCMIC_ADCMIC_TRIGGER_MASK_TR_DC_Pos 0UL 163 #define MXS40ADCMIC_ADCMIC_TRIGGER_MASK_TR_DC_Msk 0x1UL 164 #define MXS40ADCMIC_ADCMIC_TRIGGER_MASK_TR_DATA_Pos 1UL 165 #define MXS40ADCMIC_ADCMIC_TRIGGER_MASK_TR_DATA_Msk 0x2UL 166 /* MXS40ADCMIC.ADCMIC_INTR */ 167 #define MXS40ADCMIC_ADCMIC_INTR_INTERRUPT_DC_Pos 0UL 168 #define MXS40ADCMIC_ADCMIC_INTR_INTERRUPT_DC_Msk 0x1UL 169 #define MXS40ADCMIC_ADCMIC_INTR_INTERRUPT_DATA_Pos 1UL 170 #define MXS40ADCMIC_ADCMIC_INTR_INTERRUPT_DATA_Msk 0x2UL 171 /* MXS40ADCMIC.ADCMIC_INTR_SET */ 172 #define MXS40ADCMIC_ADCMIC_INTR_SET_INTERRUPT_DC_Pos 0UL 173 #define MXS40ADCMIC_ADCMIC_INTR_SET_INTERRUPT_DC_Msk 0x1UL 174 #define MXS40ADCMIC_ADCMIC_INTR_SET_INTERRUPT_DATA_Pos 1UL 175 #define MXS40ADCMIC_ADCMIC_INTR_SET_INTERRUPT_DATA_Msk 0x2UL 176 /* MXS40ADCMIC.ADCMIC_INTR_MASK */ 177 #define MXS40ADCMIC_ADCMIC_INTR_MASK_INTERRUPT_DC_Pos 0UL 178 #define MXS40ADCMIC_ADCMIC_INTR_MASK_INTERRUPT_DC_Msk 0x1UL 179 #define MXS40ADCMIC_ADCMIC_INTR_MASK_INTERRUPT_DATA_Pos 1UL 180 #define MXS40ADCMIC_ADCMIC_INTR_MASK_INTERRUPT_DATA_Msk 0x2UL 181 /* MXS40ADCMIC.ADCMIC_INTR_MASKED */ 182 #define MXS40ADCMIC_ADCMIC_INTR_MASKED_INTERRUPT_DC_Pos 0UL 183 #define MXS40ADCMIC_ADCMIC_INTR_MASKED_INTERRUPT_DC_Msk 0x1UL 184 #define MXS40ADCMIC_ADCMIC_INTR_MASKED_INTERRUPT_DATA_Pos 1UL 185 #define MXS40ADCMIC_ADCMIC_INTR_MASKED_INTERRUPT_DATA_Msk 0x2UL 186 /* MXS40ADCMIC.ADCMIC_TRIG_INTRPT_TIMER_CTRL */ 187 #define MXS40ADCMIC_ADCMIC_TRIG_INTRPT_TIMER_CTRL_TIMER_LIMIT_Pos 0UL 188 #define MXS40ADCMIC_ADCMIC_TRIG_INTRPT_TIMER_CTRL_TIMER_LIMIT_Msk 0xFFFFUL 189 #define MXS40ADCMIC_ADCMIC_TRIG_INTRPT_TIMER_CTRL_TIMER_CLR_Pos 30UL 190 #define MXS40ADCMIC_ADCMIC_TRIG_INTRPT_TIMER_CTRL_TIMER_CLR_Msk 0x40000000UL 191 #define MXS40ADCMIC_ADCMIC_TRIG_INTRPT_TIMER_CTRL_TIMER_INC_Pos 31UL 192 #define MXS40ADCMIC_ADCMIC_TRIG_INTRPT_TIMER_CTRL_TIMER_INC_Msk 0x80000000UL 193 /* MXS40ADCMIC.ADCMIC_TP */ 194 #define MXS40ADCMIC_ADCMIC_TP_TEST_POINT_SET_DATA_Pos 0UL 195 #define MXS40ADCMIC_ADCMIC_TP_TEST_POINT_SET_DATA_Msk 0xFFUL 196 #define MXS40ADCMIC_ADCMIC_TP_TEST_POINT_OBSERVE_DATA_Pos 16UL 197 #define MXS40ADCMIC_ADCMIC_TP_TEST_POINT_OBSERVE_DATA_Msk 0xFFFF0000UL 198 /* MXS40ADCMIC.ADCMIC_DATA */ 199 #define MXS40ADCMIC_ADCMIC_DATA_FIFO_DATA_Pos 0UL 200 #define MXS40ADCMIC_ADCMIC_DATA_FIFO_DATA_Msk 0xFFFFFFFFUL 201 /* MXS40ADCMIC.ADC_CLK_CTRL */ 202 #define MXS40ADCMIC_ADC_CLK_CTRL_ADC_SYN_CLK_PHASE_Pos 0UL 203 #define MXS40ADCMIC_ADC_CLK_CTRL_ADC_SYN_CLK_PHASE_Msk 0x1UL 204 #define MXS40ADCMIC_ADC_CLK_CTRL_ADC_CLK_GATE_EN_Pos 3UL 205 #define MXS40ADCMIC_ADC_CLK_CTRL_ADC_CLK_GATE_EN_Msk 0x8UL 206 #define MXS40ADCMIC_ADC_CLK_CTRL_ADC_DATA_OUT_Pos 4UL 207 #define MXS40ADCMIC_ADC_CLK_CTRL_ADC_DATA_OUT_Msk 0x30UL 208 /* MXS40ADCMIC.ADC_GPIO_CTRL */ 209 #define MXS40ADCMIC_ADC_GPIO_CTRL_ADC_DCIN_MUX_Pos 0UL 210 #define MXS40ADCMIC_ADC_GPIO_CTRL_ADC_DCIN_MUX_Msk 0x1FUL 211 /* MXS40ADCMIC.ADC_PD_CTRL */ 212 #define MXS40ADCMIC_ADC_PD_CTRL_ADC_EN_VBAT_Pos 0UL 213 #define MXS40ADCMIC_ADC_PD_CTRL_ADC_EN_VBAT_Msk 0x1UL 214 #define MXS40ADCMIC_ADC_PD_CTRL_ADC_PWRUP_Pos 1UL 215 #define MXS40ADCMIC_ADC_PD_CTRL_ADC_PWRUP_Msk 0x2UL 216 #define MXS40ADCMIC_ADC_PD_CTRL_ADC_REF_PWRUP_Pos 2UL 217 #define MXS40ADCMIC_ADC_PD_CTRL_ADC_REF_PWRUP_Msk 0x4UL 218 #define MXS40ADCMIC_ADC_PD_CTRL_ADC_CORE_PWRUP_Pos 3UL 219 #define MXS40ADCMIC_ADC_PD_CTRL_ADC_CORE_PWRUP_Msk 0x8UL 220 #define MXS40ADCMIC_ADC_PD_CTRL_MIC_PWRUP_Pos 4UL 221 #define MXS40ADCMIC_ADC_PD_CTRL_MIC_PWRUP_Msk 0x10UL 222 #define MXS40ADCMIC_ADC_PD_CTRL_MIC_CLAMP_EN_Pos 5UL 223 #define MXS40ADCMIC_ADC_PD_CTRL_MIC_CLAMP_EN_Msk 0x20UL 224 #define MXS40ADCMIC_ADC_PD_CTRL_MICBIAS_PWRUP_Pos 6UL 225 #define MXS40ADCMIC_ADC_PD_CTRL_MICBIAS_PWRUP_Msk 0x40UL 226 #define MXS40ADCMIC_ADC_PD_CTRL_ADC_MODE_Pos 7UL 227 #define MXS40ADCMIC_ADC_PD_CTRL_ADC_MODE_Msk 0x80UL 228 #define MXS40ADCMIC_ADC_PD_CTRL_ADC_MIC_PDSLT_Pos 8UL 229 #define MXS40ADCMIC_ADC_PD_CTRL_ADC_MIC_PDSLT_Msk 0x100UL 230 #define MXS40ADCMIC_ADC_PD_CTRL_IDDQ_Pos 9UL 231 #define MXS40ADCMIC_ADC_PD_CTRL_IDDQ_Msk 0x200UL 232 /* MXS40ADCMIC.ADC_BG_REF_CTRL */ 233 #define MXS40ADCMIC_ADC_BG_REF_CTRL_ADC_BG_PTAT_CTRL_Pos 0UL 234 #define MXS40ADCMIC_ADC_BG_REF_CTRL_ADC_BG_PTAT_CTRL_Msk 0x7UL 235 #define MXS40ADCMIC_ADC_BG_REF_CTRL_ADC_BG_CTAT_CTRL_Pos 3UL 236 #define MXS40ADCMIC_ADC_BG_REF_CTRL_ADC_BG_CTAT_CTRL_Msk 0x38UL 237 #define MXS40ADCMIC_ADC_BG_REF_CTRL_ADC_REF_CTRL_Pos 6UL 238 #define MXS40ADCMIC_ADC_BG_REF_CTRL_ADC_REF_CTRL_Msk 0x3C0UL 239 #define MXS40ADCMIC_ADC_BG_REF_CTRL_ADC_SCF_CLKDIV_Pos 10UL 240 #define MXS40ADCMIC_ADC_BG_REF_CTRL_ADC_SCF_CLKDIV_Msk 0xC00UL 241 #define MXS40ADCMIC_ADC_BG_REF_CTRL_ADC_SCF_BYPASS_Pos 12UL 242 #define MXS40ADCMIC_ADC_BG_REF_CTRL_ADC_SCF_BYPASS_Msk 0x1000UL 243 #define MXS40ADCMIC_ADC_BG_REF_CTRL_ADC_SCF_BYPASS_SEQ_Pos 13UL 244 #define MXS40ADCMIC_ADC_BG_REF_CTRL_ADC_SCF_BYPASS_SEQ_Msk 0x2000UL 245 #define MXS40ADCMIC_ADC_BG_REF_CTRL_ADC_SCF_SEQ_SLT_Pos 14UL 246 #define MXS40ADCMIC_ADC_BG_REF_CTRL_ADC_SCF_SEQ_SLT_Msk 0x4000UL 247 #define MXS40ADCMIC_ADC_BG_REF_CTRL_ADC_BIAS_CTRL_Pos 15UL 248 #define MXS40ADCMIC_ADC_BG_REF_CTRL_ADC_BIAS_CTRL_Msk 0x18000UL 249 /* MXS40ADCMIC.ADC_CORE_CTRL */ 250 #define MXS40ADCMIC_ADC_CORE_CTRL_ADC_DITH_CTRL_Pos 0UL 251 #define MXS40ADCMIC_ADC_CORE_CTRL_ADC_DITH_CTRL_Msk 0x3UL 252 #define MXS40ADCMIC_ADC_CORE_CTRL_ADC_SHUFF_EN_Pos 2UL 253 #define MXS40ADCMIC_ADC_CORE_CTRL_ADC_SHUFF_EN_Msk 0x4UL 254 #define MXS40ADCMIC_ADC_CORE_CTRL_ADC_RESET_EN_Pos 3UL 255 #define MXS40ADCMIC_ADC_CORE_CTRL_ADC_RESET_EN_Msk 0x8UL 256 #define MXS40ADCMIC_ADC_CORE_CTRL_ADC_DCINPUT_RANGE_Pos 4UL 257 #define MXS40ADCMIC_ADC_CORE_CTRL_ADC_DCINPUT_RANGE_Msk 0x10UL 258 #define MXS40ADCMIC_ADC_CORE_CTRL_ADC_CLK_DIV2_Pos 5UL 259 #define MXS40ADCMIC_ADC_CORE_CTRL_ADC_CLK_DIV2_Msk 0x20UL 260 /* MXS40ADCMIC.ADC_MIC_BIAS_PGA_CTRL */ 261 #define MXS40ADCMIC_ADC_MIC_BIAS_PGA_CTRL_MIC_BIAS_REF_CTRL_Pos 0UL 262 #define MXS40ADCMIC_ADC_MIC_BIAS_PGA_CTRL_MIC_BIAS_REF_CTRL_Msk 0x3UL 263 #define MXS40ADCMIC_ADC_MIC_BIAS_PGA_CTRL_MIC_BIAS_CTRL_Pos 2UL 264 #define MXS40ADCMIC_ADC_MIC_BIAS_PGA_CTRL_MIC_BIAS_CTRL_Msk 0xCUL 265 #define MXS40ADCMIC_ADC_MIC_BIAS_PGA_CTRL_MIC_REF_SLT_Pos 4UL 266 #define MXS40ADCMIC_ADC_MIC_BIAS_PGA_CTRL_MIC_REF_SLT_Msk 0x10UL 267 #define MXS40ADCMIC_ADC_MIC_BIAS_PGA_CTRL_MIC_SCF_CLK_CTRL_Pos 5UL 268 #define MXS40ADCMIC_ADC_MIC_BIAS_PGA_CTRL_MIC_SCF_CLK_CTRL_Msk 0x60UL 269 #define MXS40ADCMIC_ADC_MIC_BIAS_PGA_CTRL_MIC_SCF_BYPASS_Pos 7UL 270 #define MXS40ADCMIC_ADC_MIC_BIAS_PGA_CTRL_MIC_SCF_BYPASS_Msk 0x80UL 271 #define MXS40ADCMIC_ADC_MIC_BIAS_PGA_CTRL_MIC_SCF_BYPASS_SEQ_Pos 8UL 272 #define MXS40ADCMIC_ADC_MIC_BIAS_PGA_CTRL_MIC_SCF_BYPASS_SEQ_Msk 0x100UL 273 #define MXS40ADCMIC_ADC_MIC_BIAS_PGA_CTRL_MIC_SCF_SEQ_SLT_Pos 9UL 274 #define MXS40ADCMIC_ADC_MIC_BIAS_PGA_CTRL_MIC_SCF_SEQ_SLT_Msk 0x200UL 275 #define MXS40ADCMIC_ADC_MIC_BIAS_PGA_CTRL_MIC_BIAS_LZ_Pos 10UL 276 #define MXS40ADCMIC_ADC_MIC_BIAS_PGA_CTRL_MIC_BIAS_LZ_Msk 0x400UL 277 #define MXS40ADCMIC_ADC_MIC_BIAS_PGA_CTRL_MIC_PGA_GAIN_CTRL_Pos 11UL 278 #define MXS40ADCMIC_ADC_MIC_BIAS_PGA_CTRL_MIC_PGA_GAIN_CTRL_Msk 0x1F800UL 279 #define MXS40ADCMIC_ADC_MIC_BIAS_PGA_CTRL_MIC_PGA_INCM_CTRL_Pos 17UL 280 #define MXS40ADCMIC_ADC_MIC_BIAS_PGA_CTRL_MIC_PGA_INCM_CTRL_Msk 0x60000UL 281 #define MXS40ADCMIC_ADC_MIC_BIAS_PGA_CTRL_MIC_PGA_OUTCM_CTRL_Pos 19UL 282 #define MXS40ADCMIC_ADC_MIC_BIAS_PGA_CTRL_MIC_PGA_OUTCM_CTRL_Msk 0x180000UL 283 #define MXS40ADCMIC_ADC_MIC_BIAS_PGA_CTRL_MIC_PGA_CLAMPVREF_CTRL_Pos 21UL 284 #define MXS40ADCMIC_ADC_MIC_BIAS_PGA_CTRL_MIC_PGA_CLAMPVREF_CTRL_Msk 0x600000UL 285 #define MXS40ADCMIC_ADC_MIC_BIAS_PGA_CTRL_MIC_NEG_INPUT_SLT_Pos 23UL 286 #define MXS40ADCMIC_ADC_MIC_BIAS_PGA_CTRL_MIC_NEG_INPUT_SLT_Msk 0x800000UL 287 /* MXS40ADCMIC.ADC_SPARE */ 288 #define MXS40ADCMIC_ADC_SPARE_ADC_SPARE_Pos 0UL 289 #define MXS40ADCMIC_ADC_SPARE_ADC_SPARE_Msk 0x3FFUL 290 /* MXS40ADCMIC.AUXADC_CTRL */ 291 #define MXS40ADCMIC_AUXADC_CTRL_EN_Pos 0UL 292 #define MXS40ADCMIC_AUXADC_CTRL_EN_Msk 0x1UL 293 #define MXS40ADCMIC_AUXADC_CTRL_DF3_BYPASS_Pos 2UL 294 #define MXS40ADCMIC_AUXADC_CTRL_DF3_BYPASS_Msk 0x4UL 295 #define MXS40ADCMIC_AUXADC_CTRL_BIQUAD_BYPASS_Pos 3UL 296 #define MXS40ADCMIC_AUXADC_CTRL_BIQUAD_BYPASS_Msk 0x8UL 297 #define MXS40ADCMIC_AUXADC_CTRL_DFMODE_Pos 4UL 298 #define MXS40ADCMIC_AUXADC_CTRL_DFMODE_Msk 0x70UL 299 #define MXS40ADCMIC_AUXADC_CTRL_MPR0_Pos 8UL 300 #define MXS40ADCMIC_AUXADC_CTRL_MPR0_Msk 0x300UL 301 #define MXS40ADCMIC_AUXADC_CTRL_MPR1_Pos 10UL 302 #define MXS40ADCMIC_AUXADC_CTRL_MPR1_Msk 0xC00UL 303 #define MXS40ADCMIC_AUXADC_CTRL_MPR2_Pos 12UL 304 #define MXS40ADCMIC_AUXADC_CTRL_MPR2_Msk 0x3000UL 305 #define MXS40ADCMIC_AUXADC_CTRL_MPR3_Pos 14UL 306 #define MXS40ADCMIC_AUXADC_CTRL_MPR3_Msk 0xC000UL 307 /* MXS40ADCMIC.AUXADC_CIC_CTRL */ 308 #define MXS40ADCMIC_AUXADC_CIC_CTRL_CIC_GAIN_Pos 0UL 309 #define MXS40ADCMIC_AUXADC_CIC_CTRL_CIC_GAIN_Msk 0xFFFFUL 310 /* MXS40ADCMIC.AUXADC_OVERRIDE */ 311 #define MXS40ADCMIC_AUXADC_OVERRIDE_OVERRIDE_Pos 0UL 312 #define MXS40ADCMIC_AUXADC_OVERRIDE_OVERRIDE_Msk 0x7FFFFFUL 313 /* MXS40ADCMIC.AUXADC_DF3_COEFF */ 314 #define MXS40ADCMIC_AUXADC_DF3_COEFF_DF3_COEFF_SEL_Pos 0UL 315 #define MXS40ADCMIC_AUXADC_DF3_COEFF_DF3_COEFF_SEL_Msk 0x1UL 316 #define MXS40ADCMIC_AUXADC_DF3_COEFF_DF3_COEFF_PGM_EN_Pos 1UL 317 #define MXS40ADCMIC_AUXADC_DF3_COEFF_DF3_COEFF_PGM_EN_Msk 0x2UL 318 #define MXS40ADCMIC_AUXADC_DF3_COEFF_DF3_COEFF_WREN_Pos 2UL 319 #define MXS40ADCMIC_AUXADC_DF3_COEFF_DF3_COEFF_WREN_Msk 0x4UL 320 #define MXS40ADCMIC_AUXADC_DF3_COEFF_DF3_COEFF_ADDR_Pos 4UL 321 #define MXS40ADCMIC_AUXADC_DF3_COEFF_DF3_COEFF_ADDR_Msk 0x1F0UL 322 #define MXS40ADCMIC_AUXADC_DF3_COEFF_DF3_ACCESS_DONE_Pos 15UL 323 #define MXS40ADCMIC_AUXADC_DF3_COEFF_DF3_ACCESS_DONE_Msk 0x8000UL 324 #define MXS40ADCMIC_AUXADC_DF3_COEFF_DF3_COEFF_DATA_Pos 16UL 325 #define MXS40ADCMIC_AUXADC_DF3_COEFF_DF3_COEFF_DATA_Msk 0xFFFF0000UL 326 /* MXS40ADCMIC.AUXADC_BIQUAD0_COEFF_0 */ 327 #define MXS40ADCMIC_AUXADC_BIQUAD0_COEFF_0_BQ0_NUM1_COEFF_Pos 0UL 328 #define MXS40ADCMIC_AUXADC_BIQUAD0_COEFF_0_BQ0_NUM1_COEFF_Msk 0xFFFFUL 329 #define MXS40ADCMIC_AUXADC_BIQUAD0_COEFF_0_BQ0_NUM2_COEFF_Pos 16UL 330 #define MXS40ADCMIC_AUXADC_BIQUAD0_COEFF_0_BQ0_NUM2_COEFF_Msk 0xFFFF0000UL 331 /* MXS40ADCMIC.AUXADC_BIQUAD0_COEFF_1 */ 332 #define MXS40ADCMIC_AUXADC_BIQUAD0_COEFF_1_BQ0_NUM3_COEFF_Pos 0UL 333 #define MXS40ADCMIC_AUXADC_BIQUAD0_COEFF_1_BQ0_NUM3_COEFF_Msk 0xFFFFUL 334 /* MXS40ADCMIC.AUXADC_BIQUAD0_COEFF_2 */ 335 #define MXS40ADCMIC_AUXADC_BIQUAD0_COEFF_2_BQ0_DEN2_COEFF_Pos 0UL 336 #define MXS40ADCMIC_AUXADC_BIQUAD0_COEFF_2_BQ0_DEN2_COEFF_Msk 0xFFFFUL 337 #define MXS40ADCMIC_AUXADC_BIQUAD0_COEFF_2_BQ0_DEN3_COEFF_Pos 16UL 338 #define MXS40ADCMIC_AUXADC_BIQUAD0_COEFF_2_BQ0_DEN3_COEFF_Msk 0xFFFF0000UL 339 /* MXS40ADCMIC.AUXADC_BIQUAD1_COEFF_0 */ 340 #define MXS40ADCMIC_AUXADC_BIQUAD1_COEFF_0_BQ1_NUM1_COEFF_Pos 0UL 341 #define MXS40ADCMIC_AUXADC_BIQUAD1_COEFF_0_BQ1_NUM1_COEFF_Msk 0xFFFFUL 342 #define MXS40ADCMIC_AUXADC_BIQUAD1_COEFF_0_BQ1_NUM2_COEFF_Pos 16UL 343 #define MXS40ADCMIC_AUXADC_BIQUAD1_COEFF_0_BQ1_NUM2_COEFF_Msk 0xFFFF0000UL 344 /* MXS40ADCMIC.AUXADC_BIQUAD1_COEFF_1 */ 345 #define MXS40ADCMIC_AUXADC_BIQUAD1_COEFF_1_BQ1_NUM3_COEFF_Pos 0UL 346 #define MXS40ADCMIC_AUXADC_BIQUAD1_COEFF_1_BQ1_NUM3_COEFF_Msk 0xFFFFUL 347 /* MXS40ADCMIC.AUXADC_BIQUAD1_COEFF_2 */ 348 #define MXS40ADCMIC_AUXADC_BIQUAD1_COEFF_2_BQ1_DEN2_COEFF_Pos 0UL 349 #define MXS40ADCMIC_AUXADC_BIQUAD1_COEFF_2_BQ1_DEN2_COEFF_Msk 0xFFFFUL 350 #define MXS40ADCMIC_AUXADC_BIQUAD1_COEFF_2_BQ1_DEN3_COEFF_Pos 16UL 351 #define MXS40ADCMIC_AUXADC_BIQUAD1_COEFF_2_BQ1_DEN3_COEFF_Msk 0xFFFF0000UL 352 /* MXS40ADCMIC.AUXADC_BIQUAD2_COEFF_0 */ 353 #define MXS40ADCMIC_AUXADC_BIQUAD2_COEFF_0_BQ2_NUM1_COEFF_Pos 0UL 354 #define MXS40ADCMIC_AUXADC_BIQUAD2_COEFF_0_BQ2_NUM1_COEFF_Msk 0xFFFFUL 355 #define MXS40ADCMIC_AUXADC_BIQUAD2_COEFF_0_BQ2_NUM2_COEFF_Pos 16UL 356 #define MXS40ADCMIC_AUXADC_BIQUAD2_COEFF_0_BQ2_NUM2_COEFF_Msk 0xFFFF0000UL 357 /* MXS40ADCMIC.AUXADC_BIQUAD2_COEFF_1 */ 358 #define MXS40ADCMIC_AUXADC_BIQUAD2_COEFF_1_BQ2_NUM3_COEFF_Pos 0UL 359 #define MXS40ADCMIC_AUXADC_BIQUAD2_COEFF_1_BQ2_NUM3_COEFF_Msk 0xFFFFUL 360 /* MXS40ADCMIC.AUXADC_BIQUAD2_COEFF_2 */ 361 #define MXS40ADCMIC_AUXADC_BIQUAD2_COEFF_2_BQ2_DEN2_COEFF_Pos 0UL 362 #define MXS40ADCMIC_AUXADC_BIQUAD2_COEFF_2_BQ2_DEN2_COEFF_Msk 0xFFFFUL 363 #define MXS40ADCMIC_AUXADC_BIQUAD2_COEFF_2_BQ2_DEN3_COEFF_Pos 16UL 364 #define MXS40ADCMIC_AUXADC_BIQUAD2_COEFF_2_BQ2_DEN3_COEFF_Msk 0xFFFF0000UL 365 /* MXS40ADCMIC.AUXADC_BIQUAD3_COEFF_0 */ 366 #define MXS40ADCMIC_AUXADC_BIQUAD3_COEFF_0_BQ3_NUM1_COEFF_Pos 0UL 367 #define MXS40ADCMIC_AUXADC_BIQUAD3_COEFF_0_BQ3_NUM1_COEFF_Msk 0xFFFFUL 368 #define MXS40ADCMIC_AUXADC_BIQUAD3_COEFF_0_BQ3_NUM2_COEFF_Pos 16UL 369 #define MXS40ADCMIC_AUXADC_BIQUAD3_COEFF_0_BQ3_NUM2_COEFF_Msk 0xFFFF0000UL 370 /* MXS40ADCMIC.AUXADC_BIQUAD3_COEFF_1 */ 371 #define MXS40ADCMIC_AUXADC_BIQUAD3_COEFF_1_BQ3_NUM3_COEFF_Pos 0UL 372 #define MXS40ADCMIC_AUXADC_BIQUAD3_COEFF_1_BQ3_NUM3_COEFF_Msk 0xFFFFUL 373 /* MXS40ADCMIC.AUXADC_BIQUAD3_COEFF_2 */ 374 #define MXS40ADCMIC_AUXADC_BIQUAD3_COEFF_2_BQ3_DEN2_COEFF_Pos 0UL 375 #define MXS40ADCMIC_AUXADC_BIQUAD3_COEFF_2_BQ3_DEN2_COEFF_Msk 0xFFFFUL 376 #define MXS40ADCMIC_AUXADC_BIQUAD3_COEFF_2_BQ3_DEN3_COEFF_Pos 16UL 377 #define MXS40ADCMIC_AUXADC_BIQUAD3_COEFF_2_BQ3_DEN3_COEFF_Msk 0xFFFF0000UL 378 /* MXS40ADCMIC.AUXADC_BIQUAD4_COEFF_0 */ 379 #define MXS40ADCMIC_AUXADC_BIQUAD4_COEFF_0_BQ4_NUM1_COEFF_Pos 0UL 380 #define MXS40ADCMIC_AUXADC_BIQUAD4_COEFF_0_BQ4_NUM1_COEFF_Msk 0xFFFFUL 381 #define MXS40ADCMIC_AUXADC_BIQUAD4_COEFF_0_BQ4_NUM2_COEFF_Pos 16UL 382 #define MXS40ADCMIC_AUXADC_BIQUAD4_COEFF_0_BQ4_NUM2_COEFF_Msk 0xFFFF0000UL 383 /* MXS40ADCMIC.AUXADC_BIQUAD4_COEFF_1 */ 384 #define MXS40ADCMIC_AUXADC_BIQUAD4_COEFF_1_BQ4_NUM3_COEFF_Pos 0UL 385 #define MXS40ADCMIC_AUXADC_BIQUAD4_COEFF_1_BQ4_NUM3_COEFF_Msk 0xFFFFUL 386 /* MXS40ADCMIC.AUXADC_BIQUAD4_COEFF_2 */ 387 #define MXS40ADCMIC_AUXADC_BIQUAD4_COEFF_2_BQ4_DEN2_COEFF_Pos 0UL 388 #define MXS40ADCMIC_AUXADC_BIQUAD4_COEFF_2_BQ4_DEN2_COEFF_Msk 0xFFFFUL 389 #define MXS40ADCMIC_AUXADC_BIQUAD4_COEFF_2_BQ4_DEN3_COEFF_Pos 16UL 390 #define MXS40ADCMIC_AUXADC_BIQUAD4_COEFF_2_BQ4_DEN3_COEFF_Msk 0xFFFF0000UL 391 /* MXS40ADCMIC.AUXADC_CIC_STATUS */ 392 #define MXS40ADCMIC_AUXADC_CIC_STATUS_CIC_Pos 0UL 393 #define MXS40ADCMIC_AUXADC_CIC_STATUS_CIC_Msk 0xFFFFUL 394 #define MXS40ADCMIC_AUXADC_CIC_STATUS_LATCH_ON_TIMER_Pos 16UL 395 #define MXS40ADCMIC_AUXADC_CIC_STATUS_LATCH_ON_TIMER_Msk 0x10000UL 396 /* MXS40ADCMIC.AUXADC_DF1_STATUS */ 397 #define MXS40ADCMIC_AUXADC_DF1_STATUS_DF1_Pos 0UL 398 #define MXS40ADCMIC_AUXADC_DF1_STATUS_DF1_Msk 0xFFFFUL 399 /* MXS40ADCMIC.AUXADC_DF2_STATUS */ 400 #define MXS40ADCMIC_AUXADC_DF2_STATUS_DF2_Pos 0UL 401 #define MXS40ADCMIC_AUXADC_DF2_STATUS_DF2_Msk 0xFFFFUL 402 /* MXS40ADCMIC.AUXADC_DF3_STATUS */ 403 #define MXS40ADCMIC_AUXADC_DF3_STATUS_DF3_Pos 0UL 404 #define MXS40ADCMIC_AUXADC_DF3_STATUS_DF3_Msk 0xFFFFUL 405 /* MXS40ADCMIC.AUXADC_BIQUAD_STATUS */ 406 #define MXS40ADCMIC_AUXADC_BIQUAD_STATUS_BQ_Pos 0UL 407 #define MXS40ADCMIC_AUXADC_BIQUAD_STATUS_BQ_Msk 0xFFFFUL 408 409 410 #endif /* _CYIP_MXS40ADCMIC_H_ */ 411 412 413 /* [] END OF FILE */ 414
