1 /**************************************************************************//** 2 * @file acmp_reg.h 3 * @version V1.00 4 * @brief ACMP register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2023 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __ACMP_REG_H__ 10 #define __ACMP_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup ACMP Analog Comparator Controller (ACMP) 23 Memory Mapped Structure for ACMP Controller 24 @{ */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var ACMP_T::CTL[2] 32 * Offset: 0x00/0x04 Analog Comparator 0/1 Control Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[0] |ACMPEN |Comparator Enable Bit 37 * | | |0 = Comparator 0 Disabled. 38 * | | |1 = Comparator 0 Enabled. 39 * |[1] |ACMPIE |Comparator Interrupt Enable Bit 40 * | | |0 = Comparator 0 interrupt Disabled. 41 * | | |1 = Comparator 0 interrupt Enabled 42 * | | |If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well. 43 * |[3] |ACMPOINV |Comparator Output Inverse 44 * | | |0 = Comparator 0 output inverse Disabled. 45 * | | |1 = Comparator 0 output inverse Enabled. 46 * |[6:4] |NEGSEL |Comparator Negative Input Selection 47 * | | |000 = ACMP0_N pin. 48 * | | |001 = Internal comparator reference voltage (CRV0). 49 * | | |010 = Band-gap voltage. 50 * | | |011 = DAC0 output. 51 * | | |100 = DAC1 output. 52 * | | |Note: NEGSEL must select 0x1 in calibration mode. 53 * |[10:8] |POSSEL |Comparator Positive Input Selection 54 * | | |000 = ACMP0_P0 pin. 55 * | | |001 = ACMP0_P1 pin. 56 * | | |010 = ACMP0_P2 pin. 57 * | | |011 = ACMP0_P3 pin. 58 * | | |100 = OPA0_int_OUT. 59 * | | |101 = OPA1_int_OUT. 60 * | | |110 = OPA2_int_OUT. 61 * |[12] |OUTSEL |Comparator Output Select 62 * | | |0 = Comparator 0 output to ACMP0_O pin is unfiltered comparator output. 63 * | | |1 = Comparator 0 output to ACMP0_O pin is from filter output. 64 * |[15:13] |FILTSEL |Comparator Output Filter Count Selection 65 * | | |000 = Filter function is Disabled. 66 * | | |001 = ACMP0 output is sampled 1 consecutive PCLK. 67 * | | |010 = ACMP0 output is sampled 2 consecutive PCLKs. 68 * | | |011 = ACMP0 output is sampled 4 consecutive PCLKs. 69 * | | |100 = ACMP0 output is sampled 8 consecutive PCLKs. 70 * | | |101 = ACMP0 output is sampled 16 consecutive PCLKs. 71 * | | |110 = ACMP0 output is sampled 32 consecutive PCLKs. 72 * | | |111 = ACMP0 output is sampled 64 consecutive PCLKs. 73 * |[16] |WKEN |Power-down Wake-up Enable Bit 74 * | | |0 = Wake-up function Disabled. 75 * | | |1 = Wake-up function Enabled. 76 * |[17] |WLATEN |Window Latch Mode Enable Bit 77 * | | |0 = Window Latch Mode Disabled. 78 * | | |1 = Window Latch Mode Enabled. 79 * |[18] |WCMPSEL |Window Compare Mode Selection 80 * | | |0 = Window Compare Mode Disabled. 81 * | | |1 = Window Compare Mode Selected. 82 * |[21:20] |FCLKDIV |Comparator Output Filter Clock Divider 83 * | | |00 = Comparator output filter clock = PCLK. 84 * | | |01 = Comparator output filter clock = PCLK/2. 85 * | | |10 = Comparator output filter clock = PCLK/4. 86 * | | |11 = Reserved. 87 * | | |Note: Use FCLKDIV under the condition of FILTSEL = 3'h7, then set FCLKDIV to get the effect of filtering 128,256 consecutive PCLKs. 88 * |[26:24] |HYSSEL |Hysteresis Mode Selection 89 * | | |000 = Hysteresis is 0mV. 90 * | | |010 = Hysteresis is 20mV for MODESEL = 2'b00, 2'b01. 91 * | | |011 = Hysteresis is 20mV for MODESEL = 2'b10, 2'b11. 92 * | | |100 = Hysteresis is 40mV for MODESEL = 2'b00, 2'b01. 93 * | | |101 = Hysteresis is 40mV for MODESEL = 2'b10, 2'b11. 94 * | | |Others = Reserved. 95 * |[29:28] |MODESEL |Comparator Power Mode Selection 96 * | | |00 = Low power mode comparator AVDD current 1uA. 97 * | | |01 = Low power mode comparator AVDD current 2uA. 98 * | | |10 = Active mode comparator AVDD current 35uA. 99 * | | |11 = Active mode comparator AVDD current 70uA. 100 * |[31:30] |INTPOL |Interrupt Condition Polarity Selection 101 * | | |ACMPIF0 will be set to 1 when comparator output edge condition is detected. 102 * | | |00 = Rising edge or falling edge. 103 * | | |01 = Rising edge. 104 * | | |10 = Falling edge. 105 * | | |11 = Reserved. 106 * @var ACMP_T::STATUS 107 * Offset: 0x08 Analog Comparator Status Register 108 * --------------------------------------------------------------------------------------------------- 109 * |Bits |Field |Descriptions 110 * | :----: | :----: | :---- | 111 * |[0] |ACMPIF0 |Comparator 0 Interrupt Flag 112 * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[31:30]) is detected on comparator 0 output 113 * | | |This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1. 114 * | | |Note: Write 1 to clear this bit to 0. 115 * |[1] |ACMPIF1 |Comparator 1 Interrupt Flag 116 * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[31:30]) is detected on comparator 1 output 117 * | | |This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1. 118 * | | |Note: Write 1 to clear this bit to 0. 119 * |[4] |ACMPO0 |Comparator 0 Output 120 * | | |Synchronized to the PCLK to allow reading by software 121 * | | |Cleared when the comparator 0 is disabled, i.e 122 * | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0. 123 * |[5] |ACMPO1 |Comparator 1 Output 124 * | | |Synchronized to the PCLK to allow reading by software 125 * | | |Cleared when the comparator 1 is disabled, i.e 126 * | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0. 127 * |[8] |WKIF0 |Comparator 0 Power-down Wake-up Interrupt Flag 128 * | | |This bit will be set to 1 when ACMP0 wake-up interrupt event occurs. 129 * | | |0 = No power-down wake-up occurred. 130 * | | |1 = Power-down wake-up occurred. 131 * | | |Note: Write 1 to clear this bit to 0. 132 * |[9] |WKIF1 |Comparator 1 Power-down Wake-up Interrupt Flag 133 * | | |This bit will be set to 1 when ACMP1 wake-up interrupt event occurs. 134 * | | |0 = No power-down wake-up occurred. 135 * | | |1 = Power-down wake-up occurred. 136 * | | |Note: Write 1 to clear this bit to 0. 137 * |[12] |ACMPS0 |Comparator 0 Status 138 * | | |Synchronized to the PCLK to allow reading by software 139 * | | |Cleared when the comparator 0 is disabled, i.e 140 * | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0. 141 * |[13] |ACMPS1 |Comparator 1 Status 142 * | | |Synchronized to the PCLK to allow reading by software 143 * | | |Cleared when the comparator 1 is disabled, i.e 144 * | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0. 145 * |[16] |ACMPWO |Comparator Window Output 146 * | | |This bit shows the output status of window compare mode 147 * | | |0 = The positive input voltage is outside the window. 148 * | | |1 = The positive input voltage is in the window. 149 * @var ACMP_T::VREF 150 * Offset: 0x0C Analog Comparator Reference Voltage Control Register 151 * --------------------------------------------------------------------------------------------------- 152 * |Bits |Field |Descriptions 153 * | :----: | :----: | :---- | 154 * |[5:0] |CRV0SEL |Comparator0 Reference Voltage Setting 155 * | | |CRV0 = CRV0 source voltage * (ACMP_VREF[5:0]) / 63. 156 * |[6] |CRV0SSEL |CRV0 Source Voltage Selection 157 * | | |0 = AVDD is selected as CRV0 source voltage. 158 * | | |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV0 source voltage. 159 * |[8] |CRV0EN |CRV0 Enable Bit 160 * | | |0 = CRV0 Disabled. 161 * | | |1 = CRV0 Enabled. 162 * |[21:16] |CRV1SEL |Comparator1 Reference Voltage Setting 163 * | | |CRV1 = CRV1 source voltage * (ACMP_VREF[21:16]) / 63. 164 * |[22] |CRV1SSEL |CRV1 Source Voltage Selection 165 * | | |0 = AVDD is selected as CRV1 source voltage. 166 * | | |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV1 source voltage. 167 * |[24] |CRV1EN |CRV1 Enable Bit 168 * | | |0 = CRV1 Disabled. 169 * | | |1 = CRV1 Enabled. 170 * @var ACMP_T::CALCTL 171 * Offset: 0x10 Analog Comparator Calibration Control Register 172 * --------------------------------------------------------------------------------------------------- 173 * |Bits |Field |Descriptions 174 * | :----: | :----: | :---- | 175 * |[0] |CALTRG0 |Comparator0 Calibration Trigger Bit 176 * | | |0 = Calibration is stopped. 177 * | | |1 = Calibration is triggered. 178 * | | |Note 1: Before this bit is enabled, ACMPEN(ACMP_CTL0[0]) should be set and the internal high speed RC oscillator (HIRC) should be enabled in advance. 179 * | | |Note 2: Hardware will auto clear this bit when the next calibration is triggered by software. 180 * | | |Note 3: If user must trigger calibration twice or more times, the second trigger has to wait at least 300us after the previous calibration is done. 181 * |[1] |CALTRG1 |Comparator1 Calibration Trigger Bit 182 * | | |0 = Calibration is stopped. 183 * | | |1 = Calibration is triggered. 184 * | | |Note 1: Before this bit is enabled, ACMPEN(ACMP_CTL1[0]) should be set and the internal high speed RC oscillator (HIRC) should be enabled in advance. 185 * | | |Note 2: Hardware will auto clear this bit when the next calibration is triggered by software. 186 * | | |Note 3: If user must trigger calibration twice or more times, the second trigger has to wait at least 300us after the previous calibration is done. 187 * @var ACMP_T::CALSR 188 * Offset: 0x14 Analog Comparator Calibration Status Register 189 * --------------------------------------------------------------------------------------------------- 190 * |Bits |Field |Descriptions 191 * | :----: | :----: | :---- | 192 * |[0] |DONE0 |Comparator0 Calibration Done Status 193 * | | |0 = Calibrating. 194 * | | |1 = Calibration done. 195 * | | |Note: This bit is cleared by writing 1 into it. 196 * |[4] |DONE1 |Comparator1 Calibration Done Status 197 * | | |0 = Calibrating. 198 * | | |1 = Calibration done. 199 * | | |Note: This bit is cleared by writing 1 into it. 200 */ 201 __IO uint32_t CTL[2]; /*!< [0x0000-0x0004] Analog Comparator Control Register */ 202 __IO uint32_t STATUS; /*!< [0x0008] Analog Comparator Status Register */ 203 __IO uint32_t VREF; /*!< [0x000c] Analog Comparator Reference Voltage Control Register */ 204 __IO uint32_t CALCTL; /*!< [0x0010] Analog Comparator Calibration Control Register */ 205 __I uint32_t CALSR; /*!< [0x0014] Analog Comparator Calibration Status Register */ 206 207 } ACMP_T; 208 209 /** 210 @addtogroup ACMP_CONST ACMP Bit Field Definition 211 Constant Definitions for ACMP Controller 212 @{ */ 213 214 #define ACMP_CTL_ACMPEN_Pos (0) /*!< ACMP_T::CTL: ACMPEN Position */ 215 #define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos) /*!< ACMP_T::CTL: ACMPEN Mask */ 216 217 #define ACMP_CTL_ACMPIE_Pos (1) /*!< ACMP_T::CTL: ACMPIE Position */ 218 #define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos) /*!< ACMP_T::CTL: ACMPIE Mask */ 219 220 #define ACMP_CTL_ACMPOINV_Pos (3) /*!< ACMP_T::CTL: ACMPOINV Position */ 221 #define ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos) /*!< ACMP_T::CTL: ACMPOINV Mask */ 222 223 #define ACMP_CTL_NEGSEL_Pos (4) /*!< ACMP_T::CTL: NEGSEL Position */ 224 #define ACMP_CTL_NEGSEL_Msk (0x7ul << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_T::CTL: NEGSEL Mask */ 225 226 #define ACMP_CTL_POSSEL_Pos (8) /*!< ACMP_T::CTL: POSSEL Position */ 227 #define ACMP_CTL_POSSEL_Msk (0x7ul << ACMP_CTL_POSSEL_Pos) /*!< ACMP_T::CTL: POSSEL Mask */ 228 229 #define ACMP_CTL_OUTSEL_Pos (12) /*!< ACMP_T::CTL: OUTSEL Position */ 230 #define ACMP_CTL_OUTSEL_Msk (0x1ul << ACMP_CTL_OUTSEL_Pos) /*!< ACMP_T::CTL: OUTSEL Mask */ 231 232 #define ACMP_CTL_FILTSEL_Pos (13) /*!< ACMP_T::CTL: FILTSEL Position */ 233 #define ACMP_CTL_FILTSEL_Msk (0x7ul << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_T::CTL: FILTSEL Mask */ 234 235 #define ACMP_CTL_WKEN_Pos (16) /*!< ACMP_T::CTL: WKEN Position */ 236 #define ACMP_CTL_WKEN_Msk (0x1ul << ACMP_CTL_WKEN_Pos) /*!< ACMP_T::CTL: WKEN Mask */ 237 238 #define ACMP_CTL_WLATEN_Pos (17) /*!< ACMP_T::CTL: WLATEN Position */ 239 #define ACMP_CTL_WLATEN_Msk (0x1ul << ACMP_CTL_WLATEN_Pos) /*!< ACMP_T::CTL: WLATEN Mask */ 240 241 #define ACMP_CTL_WCMPSEL_Pos (18) /*!< ACMP_T::CTL: WCMPSEL Position */ 242 #define ACMP_CTL_WCMPSEL_Msk (0x1ul << ACMP_CTL_WCMPSEL_Pos) /*!< ACMP_T::CTL: WCMPSEL Mask */ 243 244 #define ACMP_CTL_FCLKDIV_Pos (20) /*!< ACMP_T::CTL: FCLKDIV Position */ 245 #define ACMP_CTL_FCLKDIV_Msk (0x3ul << ACMP_CTL_FCLKDIV_Pos) /*!< ACMP_T::CTL: FCLKDIV Mask */ 246 247 #define ACMP_CTL_HYSSEL_Pos (24) /*!< ACMP_T::CTL: HYSSEL Position */ 248 #define ACMP_CTL_HYSSEL_Msk (0x7ul << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_T::CTL: HYSSEL Mask */ 249 250 #define ACMP_CTL_MODESEL_Pos (28) /*!< ACMP_T::CTL: MODESEL Position */ 251 #define ACMP_CTL_MODESEL_Msk (0x3ul << ACMP_CTL_MODESEL_Pos) /*!< ACMP_T::CTL: MODESEL Mask */ 252 253 #define ACMP_CTL_INTPOL_Pos (30) /*!< ACMP_T::CTL: INTPOL Position */ 254 #define ACMP_CTL_INTPOL_Msk (0x3ul << ACMP_CTL_INTPOL_Pos) /*!< ACMP_T::CTL: INTPOL Mask */ 255 256 #define ACMP_CTL0_ACMPEN_Pos (0) /*!< ACMP_T::CTL0: ACMPEN Position */ 257 #define ACMP_CTL0_ACMPEN_Msk (0x1ul << ACMP_CTL0_ACMPEN_Pos) /*!< ACMP_T::CTL0: ACMPEN Mask */ 258 259 #define ACMP_CTL0_ACMPIE_Pos (1) /*!< ACMP_T::CTL0: ACMPIE Position */ 260 #define ACMP_CTL0_ACMPIE_Msk (0x1ul << ACMP_CTL0_ACMPIE_Pos) /*!< ACMP_T::CTL0: ACMPIE Mask */ 261 262 #define ACMP_CTL0_ACMPOINV_Pos (3) /*!< ACMP_T::CTL0: ACMPOINV Position */ 263 #define ACMP_CTL0_ACMPOINV_Msk (0x1ul << ACMP_CTL0_ACMPOINV_Pos) /*!< ACMP_T::CTL0: ACMPOINV Mask */ 264 265 #define ACMP_CTL0_NEGSEL_Pos (4) /*!< ACMP_T::CTL0: NEGSEL Position */ 266 #define ACMP_CTL0_NEGSEL_Msk (0x7ul << ACMP_CTL0_NEGSEL_Pos) /*!< ACMP_T::CTL0: NEGSEL Mask */ 267 268 #define ACMP_CTL0_POSSEL_Pos (8) /*!< ACMP_T::CTL0: POSSEL Position */ 269 #define ACMP_CTL0_POSSEL_Msk (0x7ul << ACMP_CTL0_POSSEL_Pos) /*!< ACMP_T::CTL0: POSSEL Mask */ 270 271 #define ACMP_CTL0_OUTSEL_Pos (12) /*!< ACMP_T::CTL0: OUTSEL Position */ 272 #define ACMP_CTL0_OUTSEL_Msk (0x1ul << ACMP_CTL0_OUTSEL_Pos) /*!< ACMP_T::CTL0: OUTSEL Mask */ 273 274 #define ACMP_CTL0_FILTSEL_Pos (13) /*!< ACMP_T::CTL0: FILTSEL Position */ 275 #define ACMP_CTL0_FILTSEL_Msk (0x7ul << ACMP_CTL0_FILTSEL_Pos) /*!< ACMP_T::CTL0: FILTSEL Mask */ 276 277 #define ACMP_CTL0_WKEN_Pos (16) /*!< ACMP_T::CTL0: WKEN Position */ 278 #define ACMP_CTL0_WKEN_Msk (0x1ul << ACMP_CTL0_WKEN_Pos) /*!< ACMP_T::CTL0: WKEN Mask */ 279 280 #define ACMP_CTL0_WLATEN_Pos (17) /*!< ACMP_T::CTL0: WLATEN Position */ 281 #define ACMP_CTL0_WLATEN_Msk (0x1ul << ACMP_CTL0_WLATEN_Pos) /*!< ACMP_T::CTL0: WLATEN Mask */ 282 283 #define ACMP_CTL0_WCMPSEL_Pos (18) /*!< ACMP_T::CTL0: WCMPSEL Position */ 284 #define ACMP_CTL0_WCMPSEL_Msk (0x1ul << ACMP_CTL0_WCMPSEL_Pos) /*!< ACMP_T::CTL0: WCMPSEL Mask */ 285 286 #define ACMP_CTL0_FCLKDIV_Pos (20) /*!< ACMP_T::CTL0: FCLKDIV Position */ 287 #define ACMP_CTL0_FCLKDIV_Msk (0x3ul << ACMP_CTL0_FCLKDIV_Pos) /*!< ACMP_T::CTL0: FCLKDIV Mask */ 288 289 #define ACMP_CTL0_HYSSEL_Pos (24) /*!< ACMP_T::CTL0: HYSSEL Position */ 290 #define ACMP_CTL0_HYSSEL_Msk (0x7ul << ACMP_CTL0_HYSSEL_Pos) /*!< ACMP_T::CTL0: HYSSEL Mask */ 291 292 #define ACMP_CTL0_MODESEL_Pos (28) /*!< ACMP_T::CTL0: MODESEL Position */ 293 #define ACMP_CTL0_MODESEL_Msk (0x3ul << ACMP_CTL0_MODESEL_Pos) /*!< ACMP_T::CTL0: MODESEL Mask */ 294 295 #define ACMP_CTL0_INTPOL_Pos (30) /*!< ACMP_T::CTL0: INTPOL Position */ 296 #define ACMP_CTL0_INTPOL_Msk (0x3ul << ACMP_CTL0_INTPOL_Pos) /*!< ACMP_T::CTL0: INTPOL Mask */ 297 298 #define ACMP_CTL1_ACMPEN_Pos (0) /*!< ACMP_T::CTL1: ACMPEN Position */ 299 #define ACMP_CTL1_ACMPEN_Msk (0x1ul << ACMP_CTL1_ACMPEN_Pos) /*!< ACMP_T::CTL1: ACMPEN Mask */ 300 301 #define ACMP_CTL1_ACMPIE_Pos (1) /*!< ACMP_T::CTL1: ACMPIE Position */ 302 #define ACMP_CTL1_ACMPIE_Msk (0x1ul << ACMP_CTL1_ACMPIE_Pos) /*!< ACMP_T::CTL1: ACMPIE Mask */ 303 304 #define ACMP_CTL1_ACMPOINV_Pos (3) /*!< ACMP_T::CTL1: ACMPOINV Position */ 305 #define ACMP_CTL1_ACMPOINV_Msk (0x1ul << ACMP_CTL1_ACMPOINV_Pos) /*!< ACMP_T::CTL1: ACMPOINV Mask */ 306 307 #define ACMP_CTL1_NEGSEL_Pos (4) /*!< ACMP_T::CTL1: NEGSEL Position */ 308 #define ACMP_CTL1_NEGSEL_Msk (0x7ul << ACMP_CTL1_NEGSEL_Pos) /*!< ACMP_T::CTL1: NEGSEL Mask */ 309 310 #define ACMP_CTL1_POSSEL_Pos (8) /*!< ACMP_T::CTL1: POSSEL Position */ 311 #define ACMP_CTL1_POSSEL_Msk (0x7ul << ACMP_CTL1_POSSEL_Pos) /*!< ACMP_T::CTL1: POSSEL Mask */ 312 313 #define ACMP_CTL1_OUTSEL_Pos (12) /*!< ACMP_T::CTL1: OUTSEL Position */ 314 #define ACMP_CTL1_OUTSEL_Msk (0x1ul << ACMP_CTL1_OUTSEL_Pos) /*!< ACMP_T::CTL1: OUTSEL Mask */ 315 316 #define ACMP_CTL1_FILTSEL_Pos (13) /*!< ACMP_T::CTL1: FILTSEL Position */ 317 #define ACMP_CTL1_FILTSEL_Msk (0x7ul << ACMP_CTL1_FILTSEL_Pos) /*!< ACMP_T::CTL1: FILTSEL Mask */ 318 319 #define ACMP_CTL1_WKEN_Pos (16) /*!< ACMP_T::CTL1: WKEN Position */ 320 #define ACMP_CTL1_WKEN_Msk (0x1ul << ACMP_CTL1_WKEN_Pos) /*!< ACMP_T::CTL1: WKEN Mask */ 321 322 #define ACMP_CTL1_WLATEN_Pos (17) /*!< ACMP_T::CTL1: WLATEN Position */ 323 #define ACMP_CTL1_WLATEN_Msk (0x1ul << ACMP_CTL1_WLATEN_Pos) /*!< ACMP_T::CTL1: WLATEN Mask */ 324 325 #define ACMP_CTL1_WCMPSEL_Pos (18) /*!< ACMP_T::CTL1: WCMPSEL Position */ 326 #define ACMP_CTL1_WCMPSEL_Msk (0x1ul << ACMP_CTL1_WCMPSEL_Pos) /*!< ACMP_T::CTL1: WCMPSEL Mask */ 327 328 #define ACMP_CTL1_FCLKDIV_Pos (20) /*!< ACMP_T::CTL1: FCLKDIV Position */ 329 #define ACMP_CTL1_FCLKDIV_Msk (0x3ul << ACMP_CTL1_FCLKDIV_Pos) /*!< ACMP_T::CTL1: FCLKDIV Mask */ 330 331 #define ACMP_CTL1_HYSSEL_Pos (24) /*!< ACMP_T::CTL1: HYSSEL Position */ 332 #define ACMP_CTL1_HYSSEL_Msk (0x7ul << ACMP_CTL1_HYSSEL_Pos) /*!< ACMP_T::CTL1: HYSSEL Mask */ 333 334 #define ACMP_CTL1_MODESEL_Pos (28) /*!< ACMP_T::CTL1: MODESEL Position */ 335 #define ACMP_CTL1_MODESEL_Msk (0x3ul << ACMP_CTL1_MODESEL_Pos) /*!< ACMP_T::CTL1: MODESEL Mask */ 336 337 #define ACMP_CTL1_INTPOL_Pos (30) /*!< ACMP_T::CTL1: INTPOL Position */ 338 #define ACMP_CTL1_INTPOL_Msk (0x3ul << ACMP_CTL1_INTPOL_Pos) /*!< ACMP_T::CTL1: INTPOL Mask */ 339 340 #define ACMP_STATUS_ACMPIF0_Pos (0) /*!< ACMP_T::STATUS: ACMPIF0 Position */ 341 #define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos) /*!< ACMP_T::STATUS: ACMPIF0 Mask */ 342 343 #define ACMP_STATUS_ACMPIF1_Pos (1) /*!< ACMP_T::STATUS: ACMPIF1 Position */ 344 #define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos) /*!< ACMP_T::STATUS: ACMPIF1 Mask */ 345 346 #define ACMP_STATUS_ACMPIF2_Pos (0) /*!< ACMP_T::STATUS: ACMPIF2 Position */ 347 #define ACMP_STATUS_ACMPIF2_Msk (0x1ul << ACMP_STATUS_ACMPIF2_Pos) /*!< ACMP_T::STATUS: ACMPIF2 Mask */ 348 349 #define ACMP_STATUS_ACMPO0_Pos (4) /*!< ACMP_T::STATUS: ACMPO0 Position */ 350 #define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos) /*!< ACMP_T::STATUS: ACMPO0 Mask */ 351 352 #define ACMP_STATUS_ACMPO1_Pos (5) /*!< ACMP_T::STATUS: ACMPO1 Position */ 353 #define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos) /*!< ACMP_T::STATUS: ACMPO1 Mask */ 354 355 #define ACMP_STATUS_ACMPO2_Pos (4) /*!< ACMP_T::STATUS: ACMPO2 Position */ 356 #define ACMP_STATUS_ACMPO2_Msk (0x1ul << ACMP_STATUS_ACMPO2_Pos) /*!< ACMP_T::STATUS: ACMPO2 Mask */ 357 358 #define ACMP_STATUS_WKIF0_Pos (8) /*!< ACMP_T::STATUS: WKIF0 Position */ 359 #define ACMP_STATUS_WKIF0_Msk (0x1ul << ACMP_STATUS_WKIF0_Pos) /*!< ACMP_T::STATUS: WKIF0 Mask */ 360 361 #define ACMP_STATUS_WKIF1_Pos (9) /*!< ACMP_T::STATUS: WKIF1 Position */ 362 #define ACMP_STATUS_WKIF1_Msk (0x1ul << ACMP_STATUS_WKIF1_Pos) /*!< ACMP_T::STATUS: WKIF1 Mask */ 363 364 #define ACMP_STATUS_WKIF2_Pos (8) /*!< ACMP_T::STATUS: WKIF2 Position */ 365 #define ACMP_STATUS_WKIF2_Msk (0x1ul << ACMP_STATUS_WKIF2_Pos) /*!< ACMP_T::STATUS: WKIF2 Mask */ 366 367 #define ACMP_STATUS_ACMPS0_Pos (12) /*!< ACMP_T::STATUS: ACMPS0 Position */ 368 #define ACMP_STATUS_ACMPS0_Msk (0x1ul << ACMP_STATUS_ACMPS0_Pos) /*!< ACMP_T::STATUS: ACMPS0 Mask */ 369 370 #define ACMP_STATUS_ACMPS1_Pos (13) /*!< ACMP_T::STATUS: ACMPS1 Position */ 371 #define ACMP_STATUS_ACMPS1_Msk (0x1ul << ACMP_STATUS_ACMPS1_Pos) /*!< ACMP_T::STATUS: ACMPS1 Mask */ 372 373 #define ACMP_STATUS_ACMPS2_Pos (12) /*!< ACMP_T::STATUS: ACMPS2 Position */ 374 #define ACMP_STATUS_ACMPS2_Msk (0x1ul << ACMP_STATUS_ACMPS2_Pos) /*!< ACMP_T::STATUS: ACMPS2 Mask */ 375 376 #define ACMP_STATUS_ACMPWO_Pos (16) /*!< ACMP_T::STATUS: ACMPWO Position */ 377 #define ACMP_STATUS_ACMPWO_Msk (0x1ul << ACMP_STATUS_ACMPWO_Pos) /*!< ACMP_T::STATUS: ACMPWO Mask */ 378 379 #define ACMP_VREF_CRV0SEL_Pos (0) /*!< ACMP_T::VREF: CRV0SEL Position */ 380 #define ACMP_VREF_CRV0SEL_Msk (0x3ful << ACMP_VREF_CRV0SEL_Pos) /*!< ACMP_T::VREF: CRV0SEL Mask */ 381 382 #define ACMP_VREF_CRV0SSEL_Pos (6) /*!< ACMP_T::VREF: CRV0SSEL Position */ 383 #define ACMP_VREF_CRV0SSEL_Msk (0x1ul << ACMP_VREF_CRV0SSEL_Pos) /*!< ACMP_T::VREF: CRV0SSEL Mask */ 384 385 #define ACMP_VREF_CRV0EN_Pos (8) /*!< ACMP_T::VREF: CRV0EN Position */ 386 #define ACMP_VREF_CRV0EN_Msk (0x1ul << ACMP_VREF_CRV0EN_Pos) /*!< ACMP_T::VREF: CRV0EN Mask */ 387 388 #define ACMP_VREF_CRV1SEL_Pos (16) /*!< ACMP_T::VREF: CRV1SEL Position */ 389 #define ACMP_VREF_CRV1SEL_Msk (0x3ful << ACMP_VREF_CRV1SEL_Pos) /*!< ACMP_T::VREF: CRV1SEL Mask */ 390 391 #define ACMP_VREF_CRV1SSEL_Pos (22) /*!< ACMP_T::VREF: CRV1SSEL Position */ 392 #define ACMP_VREF_CRV1SSEL_Msk (0x1ul << ACMP_VREF_CRV1SSEL_Pos) /*!< ACMP_T::VREF: CRV1SSEL Mask */ 393 394 #define ACMP_VREF_CRV1EN_Pos (24) /*!< ACMP_T::VREF: CRV1EN Position */ 395 #define ACMP_VREF_CRV1EN_Msk (0x1ul << ACMP_VREF_CRV1EN_Pos) /*!< ACMP_T::VREF: CRV1EN Mask */ 396 397 #define ACMP_VREF_CRV2SEL_Pos (0) /*!< ACMP_T::VREF: CRV2SEL Position */ 398 #define ACMP_VREF_CRV2SEL_Msk (0x3ful << ACMP_VREF_CRV2SEL_Pos) /*!< ACMP_T::VREF: CRV2SEL Mask */ 399 400 #define ACMP_VREF_CRV2SSEL_Pos (6) /*!< ACMP_T::VREF: CRV2SSEL Position */ 401 #define ACMP_VREF_CRV2SSEL_Msk (0x1ul << ACMP_VREF_CRV2SSEL_Pos) /*!< ACMP_T::VREF: CRV2SSEL Mask */ 402 403 #define ACMP_VREF_CRV2EN_Pos (8) /*!< ACMP_T::VREF: CRV2EN Position */ 404 #define ACMP_VREF_CRV2EN_Msk (0x1ul << ACMP_VREF_CRV2EN_Pos) /*!< ACMP_T::VREF: CRV2EN Mask */ 405 406 #define ACMP_CALCTL_CALTRG0_Pos (0) /*!< ACMP_T::CALCTL: CALTRG0 Position */ 407 #define ACMP_CALCTL_CALTRG0_Msk (0x1ul << ACMP_CALCTL_CALTRG0_Pos) /*!< ACMP_T::CALCTL: CALTRG0 Mask */ 408 409 #define ACMP_CALCTL_CALTRG1_Pos (1) /*!< ACMP_T::CALCTL: CALTRG1 Position */ 410 #define ACMP_CALCTL_CALTRG1_Msk (0x1ul << ACMP_CALCTL_CALTRG1_Pos) /*!< ACMP_T::CALCTL: CALTRG1 Mask */ 411 412 #define ACMP_CALCTL_CALTRG2_Pos (0) /*!< ACMP_T::CALCTL: CALTRG2 Position */ 413 #define ACMP_CALCTL_CALTRG2_Msk (0x1ul << ACMP_CALCTL_CALTRG2_Pos) /*!< ACMP_T::CALCTL: CALTRG2 Mask */ 414 415 #define ACMP_CALSR_DONE0_Pos (0) /*!< ACMP_T::CALSR: DONE0 Position */ 416 #define ACMP_CALSR_DONE0_Msk (0x1ul << ACMP_CALSR_DONE0_Pos) /*!< ACMP_T::CALSR: DONE0 Mask */ 417 418 #define ACMP_CALSR_DONE1_Pos (4) /*!< ACMP_T::CALSR: DONE1 Position */ 419 #define ACMP_CALSR_DONE1_Msk (0x1ul << ACMP_CALSR_DONE1_Pos) /*!< ACMP_T::CALSR: DONE1 Mask */ 420 421 #define ACMP_CALSR_DONE2_Pos (0) /*!< ACMP_T::CALSR: DONE2 Position */ 422 #define ACMP_CALSR_DONE2_Msk (0x1ul << ACMP_CALSR_DONE2_Pos) /*!< ACMP_T::CALSR: DONE2 Mask */ 423 424 /**@}*/ /* ACMP_CONST */ 425 /**@}*/ /* end of ACMP register group */ 426 /**@}*/ /* end of REGISTER group */ 427 428 #if defined ( __CC_ARM ) 429 #pragma no_anon_unions 430 #endif 431 432 #endif /* __ACMP_REG_H__ */ 433
