RX
RX
TX
TX
DISABLED
DISABLED
[T,R]XDISABLED
[T,R]XDISABLED

Notes & notation:

@Time : Time trigger/when it happens
condition: Condition for transition
Effect: What happens at moment of transition

All states are "waiting states". A Task, end of a procedure, or timer will trigger a transition. And during a transition something may happen (Effect)

Due to the similarity between Tx/Rx/CCA/ED their states are grouped together, but the transitions can only occur thru the valid paths:

TXRU ->  [TXIDLE, TXDISABLED]
RXRU ->  [RXIDLE, RXDISABLED]
TXIDLE -> [TX, TXDISABLED]
RXIDLE -> [RX, CCA, ED , RXDISABLED]

Similarly TASK_CCASTOP & TASK_EDSTOP only have any effect on CCA and ED states


Notes & notation:...
EVENT_DISABLED
stop bitcounter
EVENT_DISABLED...
reset
reset
@+ [T,R]x rampdown time
@+ [T,R]x rampdown time
[T,R]XIDLE
[T,R]XIDLE
[T,R]XRU
[T,R]XRU
TASK_DISABLE
TASK_DISA...
TASK_DISABLE
TASK_DISA...
TASK_DISABLE
TASK_DISABLE
Abort current procedure
Abort current procedu...
TASK_DISABLE
TASK_DISABLE
TASK_[T,R]XEN
(can be caused by TIFS auto-trigger @TIMER_TIFS)

TASK_[T,R]XEN...
@+ [T,R]x rampup time
@+ [T,R]x rampup time
TASK_STOP
TASK_STOP
Abort current procedure

Abort current...
TASK_[CCA/ED]STOP
TASK_[CCA/ED]STOP

Stop bitcounter
Stop bitcounter...
TASK_START
OR TASK_[ED,CCA]START
TASK_STAR...
EVENT_[CCA/ED]STOPPED

EVENT_[CCA/ED]STOPPED...
Overall states in the RADIO
model main state machine
Overall states in the RADIO...
@End of [T,R]x
Maybe schedule TIFS proced.
stop bitcounter

@End of [T,R]x...
@End of CCA/ED
@End of CCA/ED
[T,R]X / CCA / ED
[T,R]X / CCA / ED
EVENT_READY
EVENT_[T,R]XREADY
EVENT_READY...
        CCA/ED
        CCA/ED
CCA_ED
CCA_ED
@ CCA end time
@ CCA end time
EVENT_ADDRESS
EVENT_EDEND / CCA[BUSY/IDLE]
EVENT_ADDRESS...
End of CCA/ED
End of CCA/ED
TASK_DISABLE
TASK_DISABLE
TASK_STOP
TASK_STOP
From RXIDLE
From RXIDLE
TX_WAIT_
ADDR_END
TX_WAIT_...
TX_WAIT_
PAYLOAD_END
TX_WAIT_...
TX_WAIT_
CRC_END
TX_WAIT_...
@ address end
@ address end
EVENT_ADDRESS
EVENT_FRAME_START
EVENT_ADDRESS...
Yes
Yes
@ payload end
@ payload end
EVENT_END
EVENT_PHYEND
EVENT_END...
EVENT_PAYLOAD
EVENT_PAYLOAD
@ CRC end
@ CRC end
End of Tx
End of Tx
TASK_DISABLE
TASK_DISABLE
TASK_STOP
TASK_STOP
From TXIDLE
From TXIDLE
TW_WAIT_
FEC1_END
TW_WAIT_...
CodedPhy
CodedPhy
No
No
@ FEC2 start
@ FEC2 start
start_Tx_FEC2()
start_Tx_FEC2()
RX_WAIT_
ADDR_END
RX_WAIT_...
TX_WAIT_
PAYLOAD_END
TX_WAIT_...
TX_WAIT_
CRC_END
TX_WAIT_...
@ address end
@ address end
Rx_addr_recv()
EVENT_SYNC
EVENT_ADDRESS
EVENT_FRAME_START
Rx_addr_recv()...
@ payload end
@ payload end
EVENT_END
EVENT_PHYEND
EVENT_CRCOK/ERROR
EVENT_END...
EVENT_PAYLOAD
EVENT_PAYLOAD
@ CRC end
@ CRC end
End of Rx
End of Rx
TASK_DISABLE
TASK_DISABLE
TASK_STOP
TASK_STOP
From RXIDLE
From RXIDLE
Packet rejected
Packet rejected
No
No
Yes
Yes
A packet may be rejected if the lenght is > max lenght or if CI is corrupted or if lenght == 0  & MODE = 15.4
(not yet implemented)
A packet may be rejected if...
Yes
Yes
RW_WAIT_
FEC1_END
RW_WAIT_...
CodedPhy
CodedPhy
No
No
@ FEC2 start
@ FEC2 start
EVENT_RATEBOOST (if)
start_Rx_FEC2()
EVENT_RATEBOOST (if)...
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