//----------------------------------------------------------------------------- // Copyright 2012 (c) Silicon Laboratories Inc. // // SPDX-License-Identifier: Zlib // // This siHAL software is provided 'as-is', without any express or implied // warranty. In no event will the authors be held liable for any damages // arising from the use of this software. // // Permission is granted to anyone to use this software for any purpose, // including commercial applications, and to alter it and redistribute it // freely, subject to the following restrictions: // // 1. The origin of this software must not be misrepresented; you must not // claim that you wrote the original software. If you use this software // in a product, an acknowledgment in the product documentation would be // appreciated but is not required. // 2. Altered source versions must be plainly marked as such, and must not be // misrepresented as being the original software. // 3. This notice may not be removed or altered from any source distribution. //----------------------------------------------------------------------------- // // Script: 0.61 // Version: 1 #ifndef __SI32_SARADC_A_REGISTERS_H__ #define __SI32_SARADC_A_REGISTERS_H__ #include #ifdef __cplusplus extern "C" { #endif struct SI32_SARADC_A_CONFIG_Struct { union { struct { // Sampling Phase Select volatile uint32_t SPSEL: 4; // Sampling Phase Enable volatile uint32_t SPEN: 1; // Synchronous Sample Generator Enable volatile uint32_t SSGEN: 1; // Output Packing Mode volatile uint32_t PACKMD: 2; // Simultaneous Conversion Packing Enable volatile uint32_t SIMCEN: 1; // Interleaved Conversion Packing Enable volatile uint32_t INTLVEN: 1; // Scan Mode Enable volatile uint32_t SCANEN: 1; uint32_t reserved0: 1; // Scan Mode Select volatile uint32_t SCANMD: 1; uint32_t reserved1: 1; // DMA Interface Enable volatile uint32_t DMAEN: 1; // Burst Mode Clock Select volatile uint32_t BCLKSEL: 1; // SAR Clock Divider volatile uint32_t CLKDIV: 11; // Single Conversion Complete Interrupt Enable volatile uint32_t SCCIEN: 1; // Scan Done Interrupt Enable volatile uint32_t SDIEN: 1; // FIFO Overrun Interrupt Enable volatile uint32_t FORIEN: 1; // FIFO Underrun Interrupt Enable volatile uint32_t FURIEN: 1; uint32_t reserved2: 1; }; volatile uint32_t U32; }; }; #define SI32_SARADC_A_CONFIG_SPSEL_MASK 0x0000000F #define SI32_SARADC_A_CONFIG_SPSEL_SHIFT 0 // The ADC samples at SSG phase 0. #define SI32_SARADC_A_CONFIG_SPSEL_PHASE0_VALUE 0 #define SI32_SARADC_A_CONFIG_SPSEL_PHASE0_U32 \ (SI32_SARADC_A_CONFIG_SPSEL_PHASE0_VALUE << SI32_SARADC_A_CONFIG_SPSEL_SHIFT) // The ADC samples at SSG phase 1. #define SI32_SARADC_A_CONFIG_SPSEL_PHASE1_VALUE 1 #define SI32_SARADC_A_CONFIG_SPSEL_PHASE1_U32 \ (SI32_SARADC_A_CONFIG_SPSEL_PHASE1_VALUE << SI32_SARADC_A_CONFIG_SPSEL_SHIFT) // The ADC samples at SSG phase 2. #define SI32_SARADC_A_CONFIG_SPSEL_PHASE2_VALUE 2 #define SI32_SARADC_A_CONFIG_SPSEL_PHASE2_U32 \ (SI32_SARADC_A_CONFIG_SPSEL_PHASE2_VALUE << SI32_SARADC_A_CONFIG_SPSEL_SHIFT) // The ADC samples at SSG phase 3. #define SI32_SARADC_A_CONFIG_SPSEL_PHASE3_VALUE 3 #define SI32_SARADC_A_CONFIG_SPSEL_PHASE3_U32 \ (SI32_SARADC_A_CONFIG_SPSEL_PHASE3_VALUE << SI32_SARADC_A_CONFIG_SPSEL_SHIFT) // The ADC samples at SSG phase 4. #define SI32_SARADC_A_CONFIG_SPSEL_PHASE4_VALUE 4 #define SI32_SARADC_A_CONFIG_SPSEL_PHASE4_U32 \ (SI32_SARADC_A_CONFIG_SPSEL_PHASE4_VALUE << SI32_SARADC_A_CONFIG_SPSEL_SHIFT) // The ADC samples at SSG phase 5. #define SI32_SARADC_A_CONFIG_SPSEL_PHASE5_VALUE 5 #define SI32_SARADC_A_CONFIG_SPSEL_PHASE5_U32 \ (SI32_SARADC_A_CONFIG_SPSEL_PHASE5_VALUE << SI32_SARADC_A_CONFIG_SPSEL_SHIFT) // The ADC samples at SSG phase 6. #define SI32_SARADC_A_CONFIG_SPSEL_PHASE6_VALUE 6 #define SI32_SARADC_A_CONFIG_SPSEL_PHASE6_U32 \ (SI32_SARADC_A_CONFIG_SPSEL_PHASE6_VALUE << SI32_SARADC_A_CONFIG_SPSEL_SHIFT) // The ADC samples at SSG phase 7. #define SI32_SARADC_A_CONFIG_SPSEL_PHASE7_VALUE 7 #define SI32_SARADC_A_CONFIG_SPSEL_PHASE7_U32 \ (SI32_SARADC_A_CONFIG_SPSEL_PHASE7_VALUE << SI32_SARADC_A_CONFIG_SPSEL_SHIFT) // The ADC samples at SSG phase 8. #define SI32_SARADC_A_CONFIG_SPSEL_PHASE8_VALUE 8 #define SI32_SARADC_A_CONFIG_SPSEL_PHASE8_U32 \ (SI32_SARADC_A_CONFIG_SPSEL_PHASE8_VALUE << SI32_SARADC_A_CONFIG_SPSEL_SHIFT) // The ADC samples at SSG phase 9. #define SI32_SARADC_A_CONFIG_SPSEL_PHASE9_VALUE 9 #define SI32_SARADC_A_CONFIG_SPSEL_PHASE9_U32 \ (SI32_SARADC_A_CONFIG_SPSEL_PHASE9_VALUE << SI32_SARADC_A_CONFIG_SPSEL_SHIFT) // The ADC samples at SSG phase 10. #define SI32_SARADC_A_CONFIG_SPSEL_PHASE10_VALUE 10 #define SI32_SARADC_A_CONFIG_SPSEL_PHASE10_U32 \ (SI32_SARADC_A_CONFIG_SPSEL_PHASE10_VALUE << SI32_SARADC_A_CONFIG_SPSEL_SHIFT) // The ADC samples at SSG phase 11. #define SI32_SARADC_A_CONFIG_SPSEL_PHASE11_VALUE 11 #define SI32_SARADC_A_CONFIG_SPSEL_PHASE11_U32 \ (SI32_SARADC_A_CONFIG_SPSEL_PHASE11_VALUE << SI32_SARADC_A_CONFIG_SPSEL_SHIFT) // The ADC samples at SSG phase 12. #define SI32_SARADC_A_CONFIG_SPSEL_PHASE12_VALUE 12 #define SI32_SARADC_A_CONFIG_SPSEL_PHASE12_U32 \ (SI32_SARADC_A_CONFIG_SPSEL_PHASE12_VALUE << SI32_SARADC_A_CONFIG_SPSEL_SHIFT) // The ADC samples at SSG phase 13. #define SI32_SARADC_A_CONFIG_SPSEL_PHASE13_VALUE 13 #define SI32_SARADC_A_CONFIG_SPSEL_PHASE13_U32 \ (SI32_SARADC_A_CONFIG_SPSEL_PHASE13_VALUE << SI32_SARADC_A_CONFIG_SPSEL_SHIFT) // The ADC samples at SSG phase 14. #define SI32_SARADC_A_CONFIG_SPSEL_PHASE14_VALUE 14 #define SI32_SARADC_A_CONFIG_SPSEL_PHASE14_U32 \ (SI32_SARADC_A_CONFIG_SPSEL_PHASE14_VALUE << SI32_SARADC_A_CONFIG_SPSEL_SHIFT) // The ADC samples at SSG phase 15. #define SI32_SARADC_A_CONFIG_SPSEL_PHASE15_VALUE 15 #define SI32_SARADC_A_CONFIG_SPSEL_PHASE15_U32 \ (SI32_SARADC_A_CONFIG_SPSEL_PHASE15_VALUE << SI32_SARADC_A_CONFIG_SPSEL_SHIFT) #define SI32_SARADC_A_CONFIG_SPEN_MASK 0x00000010 #define SI32_SARADC_A_CONFIG_SPEN_SHIFT 4 // Disable Phase Select. The ADC will always sample on the start-of-conversion // trigger selected by the SCSEL field. #define SI32_SARADC_A_CONFIG_SPEN_DISABLED_VALUE 0 #define SI32_SARADC_A_CONFIG_SPEN_DISABLED_U32 \ (SI32_SARADC_A_CONFIG_SPEN_DISABLED_VALUE << SI32_SARADC_A_CONFIG_SPEN_SHIFT) // Enable Phase Select. The ADC will sample according to the phase selected by the // SPSEL field. #define SI32_SARADC_A_CONFIG_SPEN_ENABLED_VALUE 1 #define SI32_SARADC_A_CONFIG_SPEN_ENABLED_U32 \ (SI32_SARADC_A_CONFIG_SPEN_ENABLED_VALUE << SI32_SARADC_A_CONFIG_SPEN_SHIFT) #define SI32_SARADC_A_CONFIG_SSGEN_MASK 0x00000020 #define SI32_SARADC_A_CONFIG_SSGEN_SHIFT 5 // Disables conversion trigger generation from the SSG module phase output. #define SI32_SARADC_A_CONFIG_SSGEN_DISABLED_VALUE 0 #define SI32_SARADC_A_CONFIG_SSGEN_DISABLED_U32 \ (SI32_SARADC_A_CONFIG_SSGEN_DISABLED_VALUE << SI32_SARADC_A_CONFIG_SSGEN_SHIFT) // Enables conversion trigger generation from the SSG module phase output. #define SI32_SARADC_A_CONFIG_SSGEN_ENABLED_VALUE 1 #define SI32_SARADC_A_CONFIG_SSGEN_ENABLED_U32 \ (SI32_SARADC_A_CONFIG_SSGEN_ENABLED_VALUE << SI32_SARADC_A_CONFIG_SSGEN_SHIFT) #define SI32_SARADC_A_CONFIG_PACKMD_MASK 0x000000C0 #define SI32_SARADC_A_CONFIG_PACKMD_SHIFT 6 // Data is written to the upper half-word and the lower half-word is filled with // 0's. An SCI interrupt is triggered when data is written, if enabled. #define SI32_SARADC_A_CONFIG_PACKMD_UPPER_ONLY_VALUE 0 #define SI32_SARADC_A_CONFIG_PACKMD_UPPER_ONLY_U32 \ (SI32_SARADC_A_CONFIG_PACKMD_UPPER_ONLY_VALUE << SI32_SARADC_A_CONFIG_PACKMD_SHIFT) // Data is written to the lower half-word, and the upper half-word is filled with // 0's. An SCI interrupt is triggered when data is written, if enabled. #define SI32_SARADC_A_CONFIG_PACKMD_LOWER_ONLY_VALUE 1 #define SI32_SARADC_A_CONFIG_PACKMD_LOWER_ONLY_U32 \ (SI32_SARADC_A_CONFIG_PACKMD_LOWER_ONLY_VALUE << SI32_SARADC_A_CONFIG_PACKMD_SHIFT) // Two data words are packed into the register with the upper half-word // representing the earlier data, and the lower half-word representing the later // data. If SIMCEN is set to 1, the upper half-word represents data from the // master ADC and the lower half-word represents data from the slave ADC. The ADC // write to the lower half-word will trigger the SCI interrupt, if enabled. #define SI32_SARADC_A_CONFIG_PACKMD_UPPER_FIRST_VALUE 2 #define SI32_SARADC_A_CONFIG_PACKMD_UPPER_FIRST_U32 \ (SI32_SARADC_A_CONFIG_PACKMD_UPPER_FIRST_VALUE << SI32_SARADC_A_CONFIG_PACKMD_SHIFT) // Two data words are packed into the register with the lower half-word // representing the earlier data, and the upper half-word representing the later // data. If SIMCEN is set to 1, the lower half-word represents data from the // master ADC and the upper half-word represents data from the slave ADC. The ADC // write to the upper half-word will trigger the SCI interrupt, if enabled. #define SI32_SARADC_A_CONFIG_PACKMD_LOWER_FIRST_VALUE 3 #define SI32_SARADC_A_CONFIG_PACKMD_LOWER_FIRST_U32 \ (SI32_SARADC_A_CONFIG_PACKMD_LOWER_FIRST_VALUE << SI32_SARADC_A_CONFIG_PACKMD_SHIFT) #define SI32_SARADC_A_CONFIG_SIMCEN_MASK 0x00000100 #define SI32_SARADC_A_CONFIG_SIMCEN_SHIFT 8 // Disable simultaneous mode conversion packing. #define SI32_SARADC_A_CONFIG_SIMCEN_DISABLED_VALUE 0 #define SI32_SARADC_A_CONFIG_SIMCEN_DISABLED_U32 \ (SI32_SARADC_A_CONFIG_SIMCEN_DISABLED_VALUE << SI32_SARADC_A_CONFIG_SIMCEN_SHIFT) // Enable simultaneous mode conversion packing. #define SI32_SARADC_A_CONFIG_SIMCEN_ENABLED_VALUE 1 #define SI32_SARADC_A_CONFIG_SIMCEN_ENABLED_U32 \ (SI32_SARADC_A_CONFIG_SIMCEN_ENABLED_VALUE << SI32_SARADC_A_CONFIG_SIMCEN_SHIFT) #define SI32_SARADC_A_CONFIG_INTLVEN_MASK 0x00000200 #define SI32_SARADC_A_CONFIG_INTLVEN_SHIFT 9 // Disable interleaved mode conversion packing. #define SI32_SARADC_A_CONFIG_INTLVEN_DISABLED_VALUE 0 #define SI32_SARADC_A_CONFIG_INTLVEN_DISABLED_U32 \ (SI32_SARADC_A_CONFIG_INTLVEN_DISABLED_VALUE << SI32_SARADC_A_CONFIG_INTLVEN_SHIFT) // Enable interleaved mode conversion packing. #define SI32_SARADC_A_CONFIG_INTLVEN_ENABLED_VALUE 1 #define SI32_SARADC_A_CONFIG_INTLVEN_ENABLED_U32 \ (SI32_SARADC_A_CONFIG_INTLVEN_ENABLED_VALUE << SI32_SARADC_A_CONFIG_INTLVEN_SHIFT) #define SI32_SARADC_A_CONFIG_SCANEN_MASK 0x00000400 #define SI32_SARADC_A_CONFIG_SCANEN_SHIFT 10 // Disable ADC scan mode. #define SI32_SARADC_A_CONFIG_SCANEN_DISABLED_VALUE 0 #define SI32_SARADC_A_CONFIG_SCANEN_DISABLED_U32 \ (SI32_SARADC_A_CONFIG_SCANEN_DISABLED_VALUE << SI32_SARADC_A_CONFIG_SCANEN_SHIFT) // Enable ADC scan mode. The ADC will scan through the defined time slots in // sequence on every start of conversion. #define SI32_SARADC_A_CONFIG_SCANEN_ENABLED_VALUE 1 #define SI32_SARADC_A_CONFIG_SCANEN_ENABLED_U32 \ (SI32_SARADC_A_CONFIG_SCANEN_ENABLED_VALUE << SI32_SARADC_A_CONFIG_SCANEN_SHIFT) #define SI32_SARADC_A_CONFIG_SCANMD_MASK 0x00001000 #define SI32_SARADC_A_CONFIG_SCANMD_SHIFT 12 // The channel sequencer will cycle through all of the specified time slots once. #define SI32_SARADC_A_CONFIG_SCANMD_ONCE_VALUE 0 #define SI32_SARADC_A_CONFIG_SCANMD_ONCE_U32 \ (SI32_SARADC_A_CONFIG_SCANMD_ONCE_VALUE << SI32_SARADC_A_CONFIG_SCANMD_SHIFT) // The channel sequencer will cycle through all of the specified time slots in a // loop until SCANEN is cleared to 0. #define SI32_SARADC_A_CONFIG_SCANMD_LOOP_VALUE 1 #define SI32_SARADC_A_CONFIG_SCANMD_LOOP_U32 \ (SI32_SARADC_A_CONFIG_SCANMD_LOOP_VALUE << SI32_SARADC_A_CONFIG_SCANMD_SHIFT) #define SI32_SARADC_A_CONFIG_DMAEN_MASK 0x00004000 #define SI32_SARADC_A_CONFIG_DMAEN_SHIFT 14 // Disable the ADC module DMA interface. #define SI32_SARADC_A_CONFIG_DMAEN_DISABLED_VALUE 0 #define SI32_SARADC_A_CONFIG_DMAEN_DISABLED_U32 \ (SI32_SARADC_A_CONFIG_DMAEN_DISABLED_VALUE << SI32_SARADC_A_CONFIG_DMAEN_SHIFT) // Enable the ADC module DMA interface. #define SI32_SARADC_A_CONFIG_DMAEN_ENABLED_VALUE 1 #define SI32_SARADC_A_CONFIG_DMAEN_ENABLED_U32 \ (SI32_SARADC_A_CONFIG_DMAEN_ENABLED_VALUE << SI32_SARADC_A_CONFIG_DMAEN_SHIFT) #define SI32_SARADC_A_CONFIG_BCLKSEL_MASK 0x00008000 #define SI32_SARADC_A_CONFIG_BCLKSEL_SHIFT 15 // Burst mode uses the Low Power Oscillator. #define SI32_SARADC_A_CONFIG_BCLKSEL_LPOSC0_VALUE 0 #define SI32_SARADC_A_CONFIG_BCLKSEL_LPOSC0_U32 \ (SI32_SARADC_A_CONFIG_BCLKSEL_LPOSC0_VALUE << SI32_SARADC_A_CONFIG_BCLKSEL_SHIFT) // Burst mode uses the APB clock. #define SI32_SARADC_A_CONFIG_BCLKSEL_APB_VALUE 1 #define SI32_SARADC_A_CONFIG_BCLKSEL_APB_U32 \ (SI32_SARADC_A_CONFIG_BCLKSEL_APB_VALUE << SI32_SARADC_A_CONFIG_BCLKSEL_SHIFT) #define SI32_SARADC_A_CONFIG_CLKDIV_MASK 0x07FF0000 #define SI32_SARADC_A_CONFIG_CLKDIV_SHIFT 16 #define SI32_SARADC_A_CONFIG_SCCIEN_MASK 0x08000000 #define SI32_SARADC_A_CONFIG_SCCIEN_SHIFT 27 // Disable the ADC single data conversion complete interrupt. #define SI32_SARADC_A_CONFIG_SCCIEN_DISABLED_VALUE 0 #define SI32_SARADC_A_CONFIG_SCCIEN_DISABLED_U32 \ (SI32_SARADC_A_CONFIG_SCCIEN_DISABLED_VALUE << SI32_SARADC_A_CONFIG_SCCIEN_SHIFT) // Enable the ADC single data conversion complete interrupt. #define SI32_SARADC_A_CONFIG_SCCIEN_ENABLED_VALUE 1 #define SI32_SARADC_A_CONFIG_SCCIEN_ENABLED_U32 \ (SI32_SARADC_A_CONFIG_SCCIEN_ENABLED_VALUE << SI32_SARADC_A_CONFIG_SCCIEN_SHIFT) #define SI32_SARADC_A_CONFIG_SDIEN_MASK 0x10000000 #define SI32_SARADC_A_CONFIG_SDIEN_SHIFT 28 // Disable the ADC scan complete interrupt. #define SI32_SARADC_A_CONFIG_SDIEN_DISABLED_VALUE 0 #define SI32_SARADC_A_CONFIG_SDIEN_DISABLED_U32 \ (SI32_SARADC_A_CONFIG_SDIEN_DISABLED_VALUE << SI32_SARADC_A_CONFIG_SDIEN_SHIFT) // Enable the ADC scan complete interrupt. #define SI32_SARADC_A_CONFIG_SDIEN_ENABLED_VALUE 1 #define SI32_SARADC_A_CONFIG_SDIEN_ENABLED_U32 \ (SI32_SARADC_A_CONFIG_SDIEN_ENABLED_VALUE << SI32_SARADC_A_CONFIG_SDIEN_SHIFT) #define SI32_SARADC_A_CONFIG_FORIEN_MASK 0x20000000 #define SI32_SARADC_A_CONFIG_FORIEN_SHIFT 29 // Disable the data FIFO overrun interrupt. #define SI32_SARADC_A_CONFIG_FORIEN_DISABLED_VALUE 0 #define SI32_SARADC_A_CONFIG_FORIEN_DISABLED_U32 \ (SI32_SARADC_A_CONFIG_FORIEN_DISABLED_VALUE << SI32_SARADC_A_CONFIG_FORIEN_SHIFT) // Enable the data FIFO overrun interrupt. #define SI32_SARADC_A_CONFIG_FORIEN_ENABLED_VALUE 1 #define SI32_SARADC_A_CONFIG_FORIEN_ENABLED_U32 \ (SI32_SARADC_A_CONFIG_FORIEN_ENABLED_VALUE << SI32_SARADC_A_CONFIG_FORIEN_SHIFT) #define SI32_SARADC_A_CONFIG_FURIEN_MASK 0x40000000 #define SI32_SARADC_A_CONFIG_FURIEN_SHIFT 30 // Disable the data FIFO underrun interrupt. #define SI32_SARADC_A_CONFIG_FURIEN_DISABLED_VALUE 0 #define SI32_SARADC_A_CONFIG_FURIEN_DISABLED_U32 \ (SI32_SARADC_A_CONFIG_FURIEN_DISABLED_VALUE << SI32_SARADC_A_CONFIG_FURIEN_SHIFT) // Enable the data FIFO underrun interrupt. #define SI32_SARADC_A_CONFIG_FURIEN_ENABLED_VALUE 1 #define SI32_SARADC_A_CONFIG_FURIEN_ENABLED_U32 \ (SI32_SARADC_A_CONFIG_FURIEN_ENABLED_VALUE << SI32_SARADC_A_CONFIG_FURIEN_SHIFT) struct SI32_SARADC_A_CONTROL_Struct { union { struct { // Reference Ground Select volatile uint32_t REFGNDSEL: 1; // Sampling Clock Edge Select volatile uint32_t CLKESEL: 1; // Burst Mode Tracking Time volatile uint32_t BMTK: 6; // Start-Of-Conversion Source Select volatile uint32_t SCSEL: 4; // Burst Mode Power Up Time volatile uint32_t PWRTIME: 4; // Burst Mode Enable volatile uint32_t BURSTEN: 1; // ADC Enable volatile uint32_t ADCEN: 1; // 12-Bit Mode Sample Select volatile uint32_t AD12BSSEL: 1; // Common Mode Buffer Enable volatile uint32_t VCMEN: 1; uint32_t reserved0: 1; // Accumulation Mode volatile uint32_t ACCMD: 1; // ADC Tracking Mode volatile uint32_t TRKMD: 1; // ADC Busy volatile uint32_t ADBUSY: 1; // Bias Power Select volatile uint32_t BIASSEL: 2; // Low Power Mode Enable volatile uint32_t LPMDEN: 1; // MUX and VREF Low Power Enable volatile uint32_t MREFLPEN: 1; uint32_t reserved1: 2; // Voltage Reference Select volatile uint32_t VREFSEL: 2; }; volatile uint32_t U32; }; }; #define SI32_SARADC_A_CONTROL_REFGNDSEL_MASK 0x00000001 #define SI32_SARADC_A_CONTROL_REFGNDSEL_SHIFT 0 // The internal device ground is used as the ground reference for ADC conversions. #define SI32_SARADC_A_CONTROL_REFGNDSEL_INTERNAL_VALUE 0 #define SI32_SARADC_A_CONTROL_REFGNDSEL_INTERNAL_U32 \ (SI32_SARADC_A_CONTROL_REFGNDSEL_INTERNAL_VALUE << SI32_SARADC_A_CONTROL_REFGNDSEL_SHIFT) // The VREFGND pin is used as the ground reference for ADC conversions. #define SI32_SARADC_A_CONTROL_REFGNDSEL_EXTERNAL_VALUE 1 #define SI32_SARADC_A_CONTROL_REFGNDSEL_EXTERNAL_U32 \ (SI32_SARADC_A_CONTROL_REFGNDSEL_EXTERNAL_VALUE << SI32_SARADC_A_CONTROL_REFGNDSEL_SHIFT) #define SI32_SARADC_A_CONTROL_CLKESEL_MASK 0x00000002 #define SI32_SARADC_A_CONTROL_CLKESEL_SHIFT 1 // Select the rising edge of the APB clock. #define SI32_SARADC_A_CONTROL_CLKESEL_RISING_VALUE 0 #define SI32_SARADC_A_CONTROL_CLKESEL_RISING_U32 \ (SI32_SARADC_A_CONTROL_CLKESEL_RISING_VALUE << SI32_SARADC_A_CONTROL_CLKESEL_SHIFT) // Select the falling edge of the APB clock. #define SI32_SARADC_A_CONTROL_CLKESEL_FALLING_VALUE 1 #define SI32_SARADC_A_CONTROL_CLKESEL_FALLING_U32 \ (SI32_SARADC_A_CONTROL_CLKESEL_FALLING_VALUE << SI32_SARADC_A_CONTROL_CLKESEL_SHIFT) #define SI32_SARADC_A_CONTROL_BMTK_MASK 0x000000FC #define SI32_SARADC_A_CONTROL_BMTK_SHIFT 2 #define SI32_SARADC_A_CONTROL_SCSEL_MASK 0x00000F00 #define SI32_SARADC_A_CONTROL_SCSEL_SHIFT 8 // An ADC conversion triggers from the ADCnT0 trigger source. #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT0_VALUE 0 #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT0_U32 \ (SI32_SARADC_A_CONTROL_SCSEL_ADCNT0_VALUE << SI32_SARADC_A_CONTROL_SCSEL_SHIFT) // An ADC conversion triggers from the ADCnT1 trigger source. #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT1_VALUE 1 #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT1_U32 \ (SI32_SARADC_A_CONTROL_SCSEL_ADCNT1_VALUE << SI32_SARADC_A_CONTROL_SCSEL_SHIFT) // An ADC conversion triggers from the ADCnT2 trigger source. #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT2_VALUE 2 #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT2_U32 \ (SI32_SARADC_A_CONTROL_SCSEL_ADCNT2_VALUE << SI32_SARADC_A_CONTROL_SCSEL_SHIFT) // An ADC conversion triggers from the ADCnT3 trigger source. #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT3_VALUE 3 #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT3_U32 \ (SI32_SARADC_A_CONTROL_SCSEL_ADCNT3_VALUE << SI32_SARADC_A_CONTROL_SCSEL_SHIFT) // An ADC conversion triggers from the ADCnT4 trigger source. #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT4_VALUE 4 #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT4_U32 \ (SI32_SARADC_A_CONTROL_SCSEL_ADCNT4_VALUE << SI32_SARADC_A_CONTROL_SCSEL_SHIFT) // An ADC conversion triggers from the ADCnT5 trigger source. #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT5_VALUE 5 #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT5_U32 \ (SI32_SARADC_A_CONTROL_SCSEL_ADCNT5_VALUE << SI32_SARADC_A_CONTROL_SCSEL_SHIFT) // An ADC conversion triggers from the ADCnT6 trigger source. #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT6_VALUE 6 #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT6_U32 \ (SI32_SARADC_A_CONTROL_SCSEL_ADCNT6_VALUE << SI32_SARADC_A_CONTROL_SCSEL_SHIFT) // An ADC conversion triggers from the ADCnT7 trigger source. #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT7_VALUE 7 #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT7_U32 \ (SI32_SARADC_A_CONTROL_SCSEL_ADCNT7_VALUE << SI32_SARADC_A_CONTROL_SCSEL_SHIFT) // An ADC conversion triggers from the ADCnT8 trigger source. #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT8_VALUE 8 #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT8_U32 \ (SI32_SARADC_A_CONTROL_SCSEL_ADCNT8_VALUE << SI32_SARADC_A_CONTROL_SCSEL_SHIFT) // An ADC conversion triggers from the ADCnT9 trigger source. #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT9_VALUE 9 #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT9_U32 \ (SI32_SARADC_A_CONTROL_SCSEL_ADCNT9_VALUE << SI32_SARADC_A_CONTROL_SCSEL_SHIFT) // An ADC conversion triggers from the ADCnT10 trigger source. #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT10_VALUE 10 #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT10_U32 \ (SI32_SARADC_A_CONTROL_SCSEL_ADCNT10_VALUE << SI32_SARADC_A_CONTROL_SCSEL_SHIFT) // An ADC conversion triggers from the ADCnT11 trigger source. #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT11_VALUE 11 #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT11_U32 \ (SI32_SARADC_A_CONTROL_SCSEL_ADCNT11_VALUE << SI32_SARADC_A_CONTROL_SCSEL_SHIFT) // An ADC conversion triggers from the ADCnT12 trigger source. #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT12_VALUE 12 #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT12_U32 \ (SI32_SARADC_A_CONTROL_SCSEL_ADCNT12_VALUE << SI32_SARADC_A_CONTROL_SCSEL_SHIFT) // An ADC conversion triggers from the ADCnT13 trigger source. #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT13_VALUE 13 #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT13_U32 \ (SI32_SARADC_A_CONTROL_SCSEL_ADCNT13_VALUE << SI32_SARADC_A_CONTROL_SCSEL_SHIFT) // An ADC conversion triggers from the ADCnT14 trigger source. #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT14_VALUE 14 #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT14_U32 \ (SI32_SARADC_A_CONTROL_SCSEL_ADCNT14_VALUE << SI32_SARADC_A_CONTROL_SCSEL_SHIFT) // An ADC conversion triggers from the ADCnT15 trigger source. #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT15_VALUE 15 #define SI32_SARADC_A_CONTROL_SCSEL_ADCNT15_U32 \ (SI32_SARADC_A_CONTROL_SCSEL_ADCNT15_VALUE << SI32_SARADC_A_CONTROL_SCSEL_SHIFT) #define SI32_SARADC_A_CONTROL_PWRTIME_MASK 0x0000F000 #define SI32_SARADC_A_CONTROL_PWRTIME_SHIFT 12 #define SI32_SARADC_A_CONTROL_BURSTEN_MASK 0x00010000 #define SI32_SARADC_A_CONTROL_BURSTEN_SHIFT 16 // Disable burst mode. #define SI32_SARADC_A_CONTROL_BURSTEN_DISABLED_VALUE 0 #define SI32_SARADC_A_CONTROL_BURSTEN_DISABLED_U32 \ (SI32_SARADC_A_CONTROL_BURSTEN_DISABLED_VALUE << SI32_SARADC_A_CONTROL_BURSTEN_SHIFT) // Enable burst mode. #define SI32_SARADC_A_CONTROL_BURSTEN_ENABLED_VALUE 1 #define SI32_SARADC_A_CONTROL_BURSTEN_ENABLED_U32 \ (SI32_SARADC_A_CONTROL_BURSTEN_ENABLED_VALUE << SI32_SARADC_A_CONTROL_BURSTEN_SHIFT) #define SI32_SARADC_A_CONTROL_ADCEN_MASK 0x00020000 #define SI32_SARADC_A_CONTROL_ADCEN_SHIFT 17 // Disable the ADC (low-power shutdown). #define SI32_SARADC_A_CONTROL_ADCEN_DISABLED_VALUE 0 #define SI32_SARADC_A_CONTROL_ADCEN_DISABLED_U32 \ (SI32_SARADC_A_CONTROL_ADCEN_DISABLED_VALUE << SI32_SARADC_A_CONTROL_ADCEN_SHIFT) // Enable the ADC (active and ready for data conversions). #define SI32_SARADC_A_CONTROL_ADCEN_ENABLED_VALUE 1 #define SI32_SARADC_A_CONTROL_ADCEN_ENABLED_U32 \ (SI32_SARADC_A_CONTROL_ADCEN_ENABLED_VALUE << SI32_SARADC_A_CONTROL_ADCEN_SHIFT) #define SI32_SARADC_A_CONTROL_AD12BSSEL_MASK 0x00040000 #define SI32_SARADC_A_CONTROL_AD12BSSEL_SHIFT 18 // The ADC re-samples the input before each of the four conversions. #define SI32_SARADC_A_CONTROL_AD12BSSEL_FOUR_VALUE 0 #define SI32_SARADC_A_CONTROL_AD12BSSEL_FOUR_U32 \ (SI32_SARADC_A_CONTROL_AD12BSSEL_FOUR_VALUE << SI32_SARADC_A_CONTROL_AD12BSSEL_SHIFT) // The ADC samples once before the first conversion and converts four times. #define SI32_SARADC_A_CONTROL_AD12BSSEL_ONE_VALUE 1 #define SI32_SARADC_A_CONTROL_AD12BSSEL_ONE_U32 \ (SI32_SARADC_A_CONTROL_AD12BSSEL_ONE_VALUE << SI32_SARADC_A_CONTROL_AD12BSSEL_SHIFT) #define SI32_SARADC_A_CONTROL_VCMEN_MASK 0x00080000 #define SI32_SARADC_A_CONTROL_VCMEN_SHIFT 19 // Disable the common mode buffer. #define SI32_SARADC_A_CONTROL_VCMEN_DISABLED_VALUE 0 #define SI32_SARADC_A_CONTROL_VCMEN_DISABLED_U32 \ (SI32_SARADC_A_CONTROL_VCMEN_DISABLED_VALUE << SI32_SARADC_A_CONTROL_VCMEN_SHIFT) // Enable the common mode buffer. #define SI32_SARADC_A_CONTROL_VCMEN_ENABLED_VALUE 1 #define SI32_SARADC_A_CONTROL_VCMEN_ENABLED_U32 \ (SI32_SARADC_A_CONTROL_VCMEN_ENABLED_VALUE << SI32_SARADC_A_CONTROL_VCMEN_SHIFT) #define SI32_SARADC_A_CONTROL_ACCMD_MASK 0x00200000 #define SI32_SARADC_A_CONTROL_ACCMD_SHIFT 21 // Conversions will be accumulated for the specified number of cycles in burst mode // according to the channel configuration. #define SI32_SARADC_A_CONTROL_ACCMD_ACCUMULATE_VALUE 0 #define SI32_SARADC_A_CONTROL_ACCMD_ACCUMULATE_U32 \ (SI32_SARADC_A_CONTROL_ACCMD_ACCUMULATE_VALUE << SI32_SARADC_A_CONTROL_ACCMD_SHIFT) // Conversions will not be accumulated in burst mode. #define SI32_SARADC_A_CONTROL_ACCMD_REPEAT_VALUE 1 #define SI32_SARADC_A_CONTROL_ACCMD_REPEAT_U32 \ (SI32_SARADC_A_CONTROL_ACCMD_REPEAT_VALUE << SI32_SARADC_A_CONTROL_ACCMD_SHIFT) #define SI32_SARADC_A_CONTROL_TRKMD_MASK 0x00400000 #define SI32_SARADC_A_CONTROL_TRKMD_SHIFT 22 // Normal Tracking Mode: When the ADC is enabled, a conversion begins immediately // following the start-of-conversion signal. #define SI32_SARADC_A_CONTROL_TRKMD_NORMAL_VALUE 0 #define SI32_SARADC_A_CONTROL_TRKMD_NORMAL_U32 \ (SI32_SARADC_A_CONTROL_TRKMD_NORMAL_VALUE << SI32_SARADC_A_CONTROL_TRKMD_SHIFT) // Delayed Tracking Mode: When the ADC is enabled, a conversion begins 3 SAR clock // cycles following the start-of-conversion signal. The ADC is allowed to track // during this time. #define SI32_SARADC_A_CONTROL_TRKMD_DELAYED_VALUE 1 #define SI32_SARADC_A_CONTROL_TRKMD_DELAYED_U32 \ (SI32_SARADC_A_CONTROL_TRKMD_DELAYED_VALUE << SI32_SARADC_A_CONTROL_TRKMD_SHIFT) #define SI32_SARADC_A_CONTROL_ADBUSY_MASK 0x00800000 #define SI32_SARADC_A_CONTROL_ADBUSY_SHIFT 23 #define SI32_SARADC_A_CONTROL_BIASSEL_MASK 0x03000000 #define SI32_SARADC_A_CONTROL_BIASSEL_SHIFT 24 // Select bias current mode 0. Recommended to use modes 1, 2, or 3. #define SI32_SARADC_A_CONTROL_BIASSEL_MODE0_VALUE 0 #define SI32_SARADC_A_CONTROL_BIASSEL_MODE0_U32 \ (SI32_SARADC_A_CONTROL_BIASSEL_MODE0_VALUE << SI32_SARADC_A_CONTROL_BIASSEL_SHIFT) // Select bias current mode 1 (SARCLK = 16 MHz). #define SI32_SARADC_A_CONTROL_BIASSEL_MODE1_VALUE 1 #define SI32_SARADC_A_CONTROL_BIASSEL_MODE1_U32 \ (SI32_SARADC_A_CONTROL_BIASSEL_MODE1_VALUE << SI32_SARADC_A_CONTROL_BIASSEL_SHIFT) // Select bias current mode 2. #define SI32_SARADC_A_CONTROL_BIASSEL_MODE2_VALUE 2 #define SI32_SARADC_A_CONTROL_BIASSEL_MODE2_U32 \ (SI32_SARADC_A_CONTROL_BIASSEL_MODE2_VALUE << SI32_SARADC_A_CONTROL_BIASSEL_SHIFT) // Select bias current mode 3 (SARCLK = 4 MHz). #define SI32_SARADC_A_CONTROL_BIASSEL_MODE3_VALUE 3 #define SI32_SARADC_A_CONTROL_BIASSEL_MODE3_U32 \ (SI32_SARADC_A_CONTROL_BIASSEL_MODE3_VALUE << SI32_SARADC_A_CONTROL_BIASSEL_SHIFT) #define SI32_SARADC_A_CONTROL_LPMDEN_MASK 0x04000000 #define SI32_SARADC_A_CONTROL_LPMDEN_SHIFT 26 // Disable low power mode. #define SI32_SARADC_A_CONTROL_LPMDEN_DISABLED_VALUE 0 #define SI32_SARADC_A_CONTROL_LPMDEN_DISABLED_U32 \ (SI32_SARADC_A_CONTROL_LPMDEN_DISABLED_VALUE << SI32_SARADC_A_CONTROL_LPMDEN_SHIFT) // Enable low power mode (requires extended tracking time). #define SI32_SARADC_A_CONTROL_LPMDEN_ENABLED_VALUE 1 #define SI32_SARADC_A_CONTROL_LPMDEN_ENABLED_U32 \ (SI32_SARADC_A_CONTROL_LPMDEN_ENABLED_VALUE << SI32_SARADC_A_CONTROL_LPMDEN_SHIFT) #define SI32_SARADC_A_CONTROL_MREFLPEN_MASK 0x08000000 #define SI32_SARADC_A_CONTROL_MREFLPEN_SHIFT 27 // Disable low power mode. #define SI32_SARADC_A_CONTROL_MREFLPEN_DISABLED_VALUE 0 #define SI32_SARADC_A_CONTROL_MREFLPEN_DISABLED_U32 \ (SI32_SARADC_A_CONTROL_MREFLPEN_DISABLED_VALUE << SI32_SARADC_A_CONTROL_MREFLPEN_SHIFT) // Enable low power mode (SAR clock <= 4 MHz). #define SI32_SARADC_A_CONTROL_MREFLPEN_ENABLED_VALUE 1 #define SI32_SARADC_A_CONTROL_MREFLPEN_ENABLED_U32 \ (SI32_SARADC_A_CONTROL_MREFLPEN_ENABLED_VALUE << SI32_SARADC_A_CONTROL_MREFLPEN_SHIFT) #define SI32_SARADC_A_CONTROL_VREFSEL_MASK 0xC0000000 #define SI32_SARADC_A_CONTROL_VREFSEL_SHIFT 30 // Select the internal, dedicated SARADC voltage reference as the ADC reference. #define SI32_SARADC_A_CONTROL_VREFSEL_INTERNAL_VREF_VALUE 0U #define SI32_SARADC_A_CONTROL_VREFSEL_INTERNAL_VREF_U32 \ (SI32_SARADC_A_CONTROL_VREFSEL_INTERNAL_VREF_VALUE << SI32_SARADC_A_CONTROL_VREFSEL_SHIFT) // Select the VDD pin as the ADC reference. #define SI32_SARADC_A_CONTROL_VREFSEL_VDD_VALUE 1U #define SI32_SARADC_A_CONTROL_VREFSEL_VDD_U32 \ (SI32_SARADC_A_CONTROL_VREFSEL_VDD_VALUE << SI32_SARADC_A_CONTROL_VREFSEL_SHIFT) // Select the output of the internal LDO regulator (~1.8 V) as the ADC reference. #define SI32_SARADC_A_CONTROL_VREFSEL_LDO_OUT_VALUE 2U #define SI32_SARADC_A_CONTROL_VREFSEL_LDO_OUT_U32 \ (SI32_SARADC_A_CONTROL_VREFSEL_LDO_OUT_VALUE << SI32_SARADC_A_CONTROL_VREFSEL_SHIFT) // Select the VREF pin as the ADC reference. This option is used for either an // external VREF or the on-chip VREF driving out to the VREF pin. #define SI32_SARADC_A_CONTROL_VREFSEL_EXTERNAL_VREF_VALUE 3U #define SI32_SARADC_A_CONTROL_VREFSEL_EXTERNAL_VREF_U32 \ (SI32_SARADC_A_CONTROL_VREFSEL_EXTERNAL_VREF_VALUE << SI32_SARADC_A_CONTROL_VREFSEL_SHIFT) struct SI32_SARADC_A_SQ7654_Struct { union { struct { // Time Slot 4 Conversion Characteristic volatile uint32_t TS4CHR: 2; // Time Slot 4 Input Channel volatile uint32_t TS4MUX: 5; uint32_t reserved0: 1; // Time Slot 5 Conversion Characteristic volatile uint32_t TS5CHR: 2; // Time Slot 5 Input Channel volatile uint32_t TS5MUX: 5; uint32_t reserved1: 1; // Time Slot 6 Conversion Characteristic volatile uint32_t TS6CHR: 2; // Time Slot 6 Input Channel volatile uint32_t TS6MUX: 5; uint32_t reserved2: 1; // Time Slot 7 Conversion Characteristic volatile uint32_t TS7CHR: 2; // Time Slot 7 Input Channel volatile uint32_t TS7MUX: 5; uint32_t reserved3: 1; }; volatile uint32_t U32; }; }; #define SI32_SARADC_A_SQ7654_TS4CHR_MASK 0x00000003 #define SI32_SARADC_A_SQ7654_TS4CHR_SHIFT 0 // Select conversion characteristic 0 for time slot 4. #define SI32_SARADC_A_SQ7654_TS4CHR_CC0_VALUE 0 #define SI32_SARADC_A_SQ7654_TS4CHR_CC0_U32 \ (SI32_SARADC_A_SQ7654_TS4CHR_CC0_VALUE << SI32_SARADC_A_SQ7654_TS4CHR_SHIFT) // Select conversion characteristic 1 for time slot 4. #define SI32_SARADC_A_SQ7654_TS4CHR_CC1_VALUE 1 #define SI32_SARADC_A_SQ7654_TS4CHR_CC1_U32 \ (SI32_SARADC_A_SQ7654_TS4CHR_CC1_VALUE << SI32_SARADC_A_SQ7654_TS4CHR_SHIFT) // Select conversion characteristic 2 for time slot 4. #define SI32_SARADC_A_SQ7654_TS4CHR_CC2_VALUE 2 #define SI32_SARADC_A_SQ7654_TS4CHR_CC2_U32 \ (SI32_SARADC_A_SQ7654_TS4CHR_CC2_VALUE << SI32_SARADC_A_SQ7654_TS4CHR_SHIFT) // Select conversion characteristic 3 for time slot 4. #define SI32_SARADC_A_SQ7654_TS4CHR_CC3_VALUE 3 #define SI32_SARADC_A_SQ7654_TS4CHR_CC3_U32 \ (SI32_SARADC_A_SQ7654_TS4CHR_CC3_VALUE << SI32_SARADC_A_SQ7654_TS4CHR_SHIFT) #define SI32_SARADC_A_SQ7654_TS4MUX_MASK 0x0000007C #define SI32_SARADC_A_SQ7654_TS4MUX_SHIFT 2 // Select channel ADCn.0. #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN0_VALUE 0 #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN0_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_ADCN0_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) // Select channel ADCn.1. #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN1_VALUE 1 #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN1_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_ADCN1_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) // Select channel ADCn.2. #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN2_VALUE 2 #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN2_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_ADCN2_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) // Select channel ADCn.3. #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN3_VALUE 3 #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN3_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_ADCN3_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) // Select channel ADCn.4. #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN4_VALUE 4 #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN4_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_ADCN4_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) // Select channel ADCn.5. #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN5_VALUE 5 #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN5_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_ADCN5_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) // Select channel ADCn.6. #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN6_VALUE 6 #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN6_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_ADCN6_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) // Select channel ADCn.7. #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN7_VALUE 7 #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN7_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_ADCN7_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) // Select channel ADCn.8. #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN8_VALUE 8 #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN8_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_ADCN8_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) // Select channel ADCn.9. #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN9_VALUE 9 #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN9_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_ADCN9_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) // Select channel ADCn.10. #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN10_VALUE 10 #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN10_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_ADCN10_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) // Select channel ADCn.11. #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN11_VALUE 11 #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN11_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_ADCN11_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) // Select channel ADCn.12. #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN12_VALUE 12 #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN12_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_ADCN12_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) // Select channel ADCn.13. #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN13_VALUE 13 #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN13_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_ADCN13_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) // Select channel ADCn.14. #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN14_VALUE 14 #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN14_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_ADCN14_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) // Select channel ADCn.15. #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN15_VALUE 15 #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN15_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_ADCN15_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) // Select channel ADCn.16. #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN16_VALUE 16 #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN16_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_ADCN16_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) // Select channel ADCn.17. #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN17_VALUE 17 #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN17_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_ADCN17_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) // Select channel ADCn.18. #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN18_VALUE 18 #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN18_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_ADCN18_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) // Select channel ADCn.19. #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN19_VALUE 19 #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN19_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_ADCN19_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) // Select channel ADCn.20. #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN20_VALUE 20 #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN20_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_ADCN20_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) // Select channel ADCn.21. #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN21_VALUE 21 #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN21_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_ADCN21_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) // Select channel ADCn.22. #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN22_VALUE 22 #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN22_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_ADCN22_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) // Select channel ADCn.23. #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN23_VALUE 23 #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN23_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_ADCN23_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) // Select channel ADCn.24. #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN24_VALUE 24 #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN24_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_ADCN24_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) // Select channel ADCn.25. #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN25_VALUE 25 #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN25_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_ADCN25_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) // Select channel ADCn.26. #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN26_VALUE 26 #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN26_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_ADCN26_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) // Select channel ADCn.27. #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN27_VALUE 27 #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN27_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_ADCN27_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) // Select channel ADCn.28. #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN28_VALUE 28 #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN28_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_ADCN28_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) // Select channel ADCn.29. #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN29_VALUE 29 #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN29_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_ADCN29_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) // Select channel ADCn.30. #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN30_VALUE 30 #define SI32_SARADC_A_SQ7654_TS4MUX_ADCN30_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_ADCN30_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) // None - End the sequence. #define SI32_SARADC_A_SQ7654_TS4MUX_END_VALUE 31 #define SI32_SARADC_A_SQ7654_TS4MUX_END_U32 \ (SI32_SARADC_A_SQ7654_TS4MUX_END_VALUE << SI32_SARADC_A_SQ7654_TS4MUX_SHIFT) #define SI32_SARADC_A_SQ7654_TS5CHR_MASK 0x00000300 #define SI32_SARADC_A_SQ7654_TS5CHR_SHIFT 8 // Select conversion characteristic 0 for time slot 5. #define SI32_SARADC_A_SQ7654_TS5CHR_CC0_VALUE 0 #define SI32_SARADC_A_SQ7654_TS5CHR_CC0_U32 \ (SI32_SARADC_A_SQ7654_TS5CHR_CC0_VALUE << SI32_SARADC_A_SQ7654_TS5CHR_SHIFT) // Select conversion characteristic 1 for time slot 5. #define SI32_SARADC_A_SQ7654_TS5CHR_CC1_VALUE 1 #define SI32_SARADC_A_SQ7654_TS5CHR_CC1_U32 \ (SI32_SARADC_A_SQ7654_TS5CHR_CC1_VALUE << SI32_SARADC_A_SQ7654_TS5CHR_SHIFT) // Select conversion characteristic 2 for time slot 5. #define SI32_SARADC_A_SQ7654_TS5CHR_CC2_VALUE 2 #define SI32_SARADC_A_SQ7654_TS5CHR_CC2_U32 \ (SI32_SARADC_A_SQ7654_TS5CHR_CC2_VALUE << SI32_SARADC_A_SQ7654_TS5CHR_SHIFT) // Select conversion characteristic 3 for time slot 5. #define SI32_SARADC_A_SQ7654_TS5CHR_CC3_VALUE 3 #define SI32_SARADC_A_SQ7654_TS5CHR_CC3_U32 \ (SI32_SARADC_A_SQ7654_TS5CHR_CC3_VALUE << SI32_SARADC_A_SQ7654_TS5CHR_SHIFT) #define SI32_SARADC_A_SQ7654_TS5MUX_MASK 0x00007C00 #define SI32_SARADC_A_SQ7654_TS5MUX_SHIFT 10 // Select channel ADCn.0. #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN0_VALUE 0 #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN0_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_ADCN0_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) // Select channel ADCn.1. #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN1_VALUE 1 #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN1_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_ADCN1_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) // Select channel ADCn.2. #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN2_VALUE 2 #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN2_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_ADCN2_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) // Select channel ADCn.3. #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN3_VALUE 3 #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN3_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_ADCN3_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) // Select channel ADCn.4. #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN4_VALUE 4 #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN4_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_ADCN4_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) // Select channel ADCn.5. #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN5_VALUE 5 #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN5_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_ADCN5_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) // Select channel ADCn.6. #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN6_VALUE 6 #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN6_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_ADCN6_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) // Select channel ADCn.7. #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN7_VALUE 7 #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN7_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_ADCN7_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) // Select channel ADCn.8. #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN8_VALUE 8 #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN8_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_ADCN8_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) // Select channel ADCn.9. #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN9_VALUE 9 #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN9_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_ADCN9_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) // Select channel ADCn.10. #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN10_VALUE 10 #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN10_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_ADCN10_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) // Select channel ADCn.11. #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN11_VALUE 11 #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN11_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_ADCN11_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) // Select channel ADCn.12. #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN12_VALUE 12 #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN12_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_ADCN12_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) // Select channel ADCn.13. #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN13_VALUE 13 #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN13_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_ADCN13_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) // Select channel ADCn.14. #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN14_VALUE 14 #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN14_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_ADCN14_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) // Select channel ADCn.15. #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN15_VALUE 15 #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN15_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_ADCN15_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) // Select channel ADCn.16. #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN16_VALUE 16 #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN16_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_ADCN16_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) // Select channel ADCn.17. #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN17_VALUE 17 #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN17_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_ADCN17_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) // Select channel ADCn.18. #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN18_VALUE 18 #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN18_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_ADCN18_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) // Select channel ADCn.19. #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN19_VALUE 19 #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN19_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_ADCN19_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) // Select channel ADCn.20. #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN20_VALUE 20 #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN20_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_ADCN20_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) // Select channel ADCn.21. #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN21_VALUE 21 #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN21_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_ADCN21_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) // Select channel ADCn.22. #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN22_VALUE 22 #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN22_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_ADCN22_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) // Select channel ADCn.23. #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN23_VALUE 23 #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN23_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_ADCN23_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) // Select channel ADCn.24. #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN24_VALUE 24 #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN24_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_ADCN24_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) // Select channel ADCn.25. #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN25_VALUE 25 #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN25_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_ADCN25_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) // Select channel ADCn.26. #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN26_VALUE 26 #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN26_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_ADCN26_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) // Select channel ADCn.27. #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN27_VALUE 27 #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN27_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_ADCN27_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) // Select channel ADCn.28. #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN28_VALUE 28 #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN28_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_ADCN28_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) // Select channel ADCn.29. #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN29_VALUE 29 #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN29_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_ADCN29_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) // Select channel ADCn.30. #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN30_VALUE 30 #define SI32_SARADC_A_SQ7654_TS5MUX_ADCN30_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_ADCN30_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) // None - End the sequence. #define SI32_SARADC_A_SQ7654_TS5MUX_END_VALUE 31 #define SI32_SARADC_A_SQ7654_TS5MUX_END_U32 \ (SI32_SARADC_A_SQ7654_TS5MUX_END_VALUE << SI32_SARADC_A_SQ7654_TS5MUX_SHIFT) #define SI32_SARADC_A_SQ7654_TS6CHR_MASK 0x00030000 #define SI32_SARADC_A_SQ7654_TS6CHR_SHIFT 16 // Select conversion characteristic 0 for time slot 6. #define SI32_SARADC_A_SQ7654_TS6CHR_CC0_VALUE 0 #define SI32_SARADC_A_SQ7654_TS6CHR_CC0_U32 \ (SI32_SARADC_A_SQ7654_TS6CHR_CC0_VALUE << SI32_SARADC_A_SQ7654_TS6CHR_SHIFT) // Select conversion characteristic 1 for time slot 6. #define SI32_SARADC_A_SQ7654_TS6CHR_CC1_VALUE 1 #define SI32_SARADC_A_SQ7654_TS6CHR_CC1_U32 \ (SI32_SARADC_A_SQ7654_TS6CHR_CC1_VALUE << SI32_SARADC_A_SQ7654_TS6CHR_SHIFT) // Select conversion characteristic 2 for time slot 6. #define SI32_SARADC_A_SQ7654_TS6CHR_CC2_VALUE 2 #define SI32_SARADC_A_SQ7654_TS6CHR_CC2_U32 \ (SI32_SARADC_A_SQ7654_TS6CHR_CC2_VALUE << SI32_SARADC_A_SQ7654_TS6CHR_SHIFT) // Select conversion characteristic 3 for time slot 6. #define SI32_SARADC_A_SQ7654_TS6CHR_CC3_VALUE 3 #define SI32_SARADC_A_SQ7654_TS6CHR_CC3_U32 \ (SI32_SARADC_A_SQ7654_TS6CHR_CC3_VALUE << SI32_SARADC_A_SQ7654_TS6CHR_SHIFT) #define SI32_SARADC_A_SQ7654_TS6MUX_MASK 0x007C0000 #define SI32_SARADC_A_SQ7654_TS6MUX_SHIFT 18 // Select channel ADCn.0. #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN0_VALUE 0 #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN0_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_ADCN0_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) // Select channel ADCn.1. #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN1_VALUE 1 #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN1_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_ADCN1_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) // Select channel ADCn.2. #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN2_VALUE 2 #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN2_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_ADCN2_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) // Select channel ADCn.3. #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN3_VALUE 3 #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN3_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_ADCN3_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) // Select channel ADCn.4. #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN4_VALUE 4 #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN4_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_ADCN4_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) // Select channel ADCn.5. #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN5_VALUE 5 #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN5_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_ADCN5_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) // Select channel ADCn.6. #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN6_VALUE 6 #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN6_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_ADCN6_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) // Select channel ADCn.7. #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN7_VALUE 7 #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN7_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_ADCN7_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) // Select channel ADCn.8. #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN8_VALUE 8 #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN8_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_ADCN8_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) // Select channel ADCn.9. #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN9_VALUE 9 #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN9_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_ADCN9_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) // Select channel ADCn.10. #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN10_VALUE 10 #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN10_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_ADCN10_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) // Select channel ADCn.11. #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN11_VALUE 11 #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN11_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_ADCN11_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) // Select channel ADCn.12. #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN12_VALUE 12 #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN12_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_ADCN12_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) // Select channel ADCn.13. #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN13_VALUE 13 #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN13_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_ADCN13_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) // Select channel ADCn.14. #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN14_VALUE 14 #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN14_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_ADCN14_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) // Select channel ADCn.15. #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN15_VALUE 15 #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN15_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_ADCN15_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) // Select channel ADCn.16. #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN16_VALUE 16 #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN16_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_ADCN16_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) // Select channel ADCn.17. #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN17_VALUE 17 #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN17_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_ADCN17_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) // Select channel ADCn.18. #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN18_VALUE 18 #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN18_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_ADCN18_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) // Select channel ADCn.19. #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN19_VALUE 19 #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN19_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_ADCN19_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) // Select channel ADCn.20. #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN20_VALUE 20 #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN20_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_ADCN20_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) // Select channel ADCn.21. #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN21_VALUE 21 #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN21_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_ADCN21_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) // Select channel ADCn.22. #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN22_VALUE 22 #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN22_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_ADCN22_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) // Select channel ADCn.23. #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN23_VALUE 23 #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN23_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_ADCN23_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) // Select channel ADCn.24. #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN24_VALUE 24 #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN24_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_ADCN24_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) // Select channel ADCn.25. #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN25_VALUE 25 #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN25_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_ADCN25_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) // Select channel ADCn.26. #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN26_VALUE 26 #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN26_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_ADCN26_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) // Select channel ADCn.27. #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN27_VALUE 27 #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN27_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_ADCN27_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) // Select channel ADCn.28. #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN28_VALUE 28 #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN28_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_ADCN28_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) // Select channel ADCn.29. #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN29_VALUE 29 #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN29_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_ADCN29_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) // Select channel ADCn.30. #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN30_VALUE 30 #define SI32_SARADC_A_SQ7654_TS6MUX_ADCN30_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_ADCN30_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) // None - End the sequence. #define SI32_SARADC_A_SQ7654_TS6MUX_END_VALUE 31 #define SI32_SARADC_A_SQ7654_TS6MUX_END_U32 \ (SI32_SARADC_A_SQ7654_TS6MUX_END_VALUE << SI32_SARADC_A_SQ7654_TS6MUX_SHIFT) #define SI32_SARADC_A_SQ7654_TS7CHR_MASK 0x03000000 #define SI32_SARADC_A_SQ7654_TS7CHR_SHIFT 24 // Select conversion characteristic 0 for time slot 7. #define SI32_SARADC_A_SQ7654_TS7CHR_CC0_VALUE 0 #define SI32_SARADC_A_SQ7654_TS7CHR_CC0_U32 \ (SI32_SARADC_A_SQ7654_TS7CHR_CC0_VALUE << SI32_SARADC_A_SQ7654_TS7CHR_SHIFT) // Select conversion characteristic 1 for time slot 7. #define SI32_SARADC_A_SQ7654_TS7CHR_CC1_VALUE 1 #define SI32_SARADC_A_SQ7654_TS7CHR_CC1_U32 \ (SI32_SARADC_A_SQ7654_TS7CHR_CC1_VALUE << SI32_SARADC_A_SQ7654_TS7CHR_SHIFT) // Select conversion characteristic 2 for time slot 7. #define SI32_SARADC_A_SQ7654_TS7CHR_CC2_VALUE 2 #define SI32_SARADC_A_SQ7654_TS7CHR_CC2_U32 \ (SI32_SARADC_A_SQ7654_TS7CHR_CC2_VALUE << SI32_SARADC_A_SQ7654_TS7CHR_SHIFT) // Select conversion characteristic 3 for time slot 7. #define SI32_SARADC_A_SQ7654_TS7CHR_CC3_VALUE 3 #define SI32_SARADC_A_SQ7654_TS7CHR_CC3_U32 \ (SI32_SARADC_A_SQ7654_TS7CHR_CC3_VALUE << SI32_SARADC_A_SQ7654_TS7CHR_SHIFT) #define SI32_SARADC_A_SQ7654_TS7MUX_MASK 0x7C000000 #define SI32_SARADC_A_SQ7654_TS7MUX_SHIFT 26 // Select channel ADCn.0. #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN0_VALUE 0 #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN0_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_ADCN0_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) // Select channel ADCn.1. #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN1_VALUE 1 #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN1_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_ADCN1_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) // Select channel ADCn.2. #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN2_VALUE 2 #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN2_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_ADCN2_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) // Select channel ADCn.3. #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN3_VALUE 3 #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN3_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_ADCN3_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) // Select channel ADCn.4. #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN4_VALUE 4 #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN4_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_ADCN4_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) // Select channel ADCn.5. #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN5_VALUE 5 #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN5_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_ADCN5_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) // Select channel ADCn.6. #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN6_VALUE 6 #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN6_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_ADCN6_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) // Select channel ADCn.7. #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN7_VALUE 7 #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN7_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_ADCN7_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) // Select channel ADCn.8. #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN8_VALUE 8 #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN8_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_ADCN8_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) // Select channel ADCn.9. #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN9_VALUE 9 #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN9_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_ADCN9_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) // Select channel ADCn.10. #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN10_VALUE 10 #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN10_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_ADCN10_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) // Select channel ADCn.11. #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN11_VALUE 11 #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN11_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_ADCN11_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) // Select channel ADCn.12. #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN12_VALUE 12 #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN12_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_ADCN12_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) // Select channel ADCn.13. #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN13_VALUE 13 #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN13_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_ADCN13_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) // Select channel ADCn.14. #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN14_VALUE 14 #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN14_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_ADCN14_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) // Select channel ADCn.15. #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN15_VALUE 15 #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN15_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_ADCN15_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) // Select channel ADCn.16. #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN16_VALUE 16 #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN16_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_ADCN16_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) // Select channel ADCn.17. #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN17_VALUE 17 #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN17_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_ADCN17_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) // Select channel ADCn.18. #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN18_VALUE 18 #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN18_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_ADCN18_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) // Select channel ADCn.19. #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN19_VALUE 19 #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN19_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_ADCN19_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) // Select channel ADCn.20. #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN20_VALUE 20 #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN20_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_ADCN20_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) // Select channel ADCn.21. #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN21_VALUE 21 #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN21_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_ADCN21_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) // Select channel ADCn.22. #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN22_VALUE 22 #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN22_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_ADCN22_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) // Select channel ADCn.23. #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN23_VALUE 23 #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN23_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_ADCN23_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) // Select channel ADCn.24. #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN24_VALUE 24 #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN24_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_ADCN24_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) // Select channel ADCn.25. #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN25_VALUE 25 #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN25_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_ADCN25_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) // Select channel ADCn.26. #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN26_VALUE 26 #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN26_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_ADCN26_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) // Select channel ADCn.27. #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN27_VALUE 27 #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN27_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_ADCN27_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) // Select channel ADCn.28. #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN28_VALUE 28 #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN28_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_ADCN28_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) // Select channel ADCn.29. #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN29_VALUE 29 #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN29_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_ADCN29_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) // Select channel ADCn.30. #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN30_VALUE 30 #define SI32_SARADC_A_SQ7654_TS7MUX_ADCN30_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_ADCN30_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) // None - End the sequence. #define SI32_SARADC_A_SQ7654_TS7MUX_END_VALUE 31 #define SI32_SARADC_A_SQ7654_TS7MUX_END_U32 \ (SI32_SARADC_A_SQ7654_TS7MUX_END_VALUE << SI32_SARADC_A_SQ7654_TS7MUX_SHIFT) struct SI32_SARADC_A_SQ3210_Struct { union { struct { // Time Slot 0 Conversion Characteristic volatile uint32_t TS0CHR: 2; // Time Slot 0 Input Channel volatile uint32_t TS0MUX: 5; uint32_t reserved0: 1; // Time Slot 1 Conversion Characteristic volatile uint32_t TS1CHR: 2; // Time Slot 1 Input Channel volatile uint32_t TS1MUX: 5; uint32_t reserved1: 1; // Time Slot 2 Conversion Characteristic volatile uint32_t TS2CHR: 2; // Time Slot 2 Input Channel volatile uint32_t TS2MUX: 5; uint32_t reserved2: 1; // Time Slot 3 Conversion Characteristic volatile uint32_t TS3CHR: 2; // Time Slot 3 Input Channel volatile uint32_t TS3MUX: 5; uint32_t reserved3: 1; }; volatile uint32_t U32; }; }; #define SI32_SARADC_A_SQ3210_TS0CHR_MASK 0x00000003 #define SI32_SARADC_A_SQ3210_TS0CHR_SHIFT 0 // Select conversion characteristic 0 for time slot 0. #define SI32_SARADC_A_SQ3210_TS0CHR_CC0_VALUE 0 #define SI32_SARADC_A_SQ3210_TS0CHR_CC0_U32 \ (SI32_SARADC_A_SQ3210_TS0CHR_CC0_VALUE << SI32_SARADC_A_SQ3210_TS0CHR_SHIFT) // Select conversion characteristic 1 for time slot 0. #define SI32_SARADC_A_SQ3210_TS0CHR_CC1_VALUE 1 #define SI32_SARADC_A_SQ3210_TS0CHR_CC1_U32 \ (SI32_SARADC_A_SQ3210_TS0CHR_CC1_VALUE << SI32_SARADC_A_SQ3210_TS0CHR_SHIFT) // Select conversion characteristic 2 for time slot 0. #define SI32_SARADC_A_SQ3210_TS0CHR_CC2_VALUE 2 #define SI32_SARADC_A_SQ3210_TS0CHR_CC2_U32 \ (SI32_SARADC_A_SQ3210_TS0CHR_CC2_VALUE << SI32_SARADC_A_SQ3210_TS0CHR_SHIFT) // Select conversion characteristic 3 for time slot 0. #define SI32_SARADC_A_SQ3210_TS0CHR_CC3_VALUE 3 #define SI32_SARADC_A_SQ3210_TS0CHR_CC3_U32 \ (SI32_SARADC_A_SQ3210_TS0CHR_CC3_VALUE << SI32_SARADC_A_SQ3210_TS0CHR_SHIFT) #define SI32_SARADC_A_SQ3210_TS0MUX_MASK 0x0000007C #define SI32_SARADC_A_SQ3210_TS0MUX_SHIFT 2 // Select channel ADCn.0. #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN0_VALUE 0 #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN0_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_ADCN0_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) // Select channel ADCn.1. #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN1_VALUE 1 #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN1_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_ADCN1_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) // Select channel ADCn.2. #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN2_VALUE 2 #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN2_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_ADCN2_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) // Select channel ADCn.3. #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN3_VALUE 3 #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN3_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_ADCN3_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) // Select channel ADCn.4. #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN4_VALUE 4 #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN4_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_ADCN4_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) // Select channel ADCn.5. #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN5_VALUE 5 #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN5_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_ADCN5_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) // Select channel ADCn.6. #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN6_VALUE 6 #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN6_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_ADCN6_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) // Select channel ADCn.7. #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN7_VALUE 7 #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN7_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_ADCN7_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) // Select channel ADCn.8. #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN8_VALUE 8 #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN8_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_ADCN8_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) // Select channel ADCn.9. #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN9_VALUE 9 #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN9_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_ADCN9_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) // Select channel ADCn.10. #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN10_VALUE 10 #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN10_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_ADCN10_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) // Select channel ADCn.11. #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN11_VALUE 11 #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN11_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_ADCN11_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) // Select channel ADCn.12. #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN12_VALUE 12 #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN12_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_ADCN12_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) // Select channel ADCn.13. #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN13_VALUE 13 #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN13_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_ADCN13_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) // Select channel ADCn.14. #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN14_VALUE 14 #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN14_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_ADCN14_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) // Select channel ADCn.15. #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN15_VALUE 15 #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN15_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_ADCN15_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) // Select channel ADCn.16. #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN16_VALUE 16 #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN16_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_ADCN16_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) // Select channel ADCn.17. #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN17_VALUE 17 #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN17_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_ADCN17_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) // Select channel ADCn.18. #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN18_VALUE 18 #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN18_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_ADCN18_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) // Select channel ADCn.19. #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN19_VALUE 19 #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN19_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_ADCN19_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) // Select channel ADCn.20. #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN20_VALUE 20 #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN20_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_ADCN20_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) // Select channel ADCn.21. #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN21_VALUE 21 #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN21_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_ADCN21_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) // Select channel ADCn.22. #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN22_VALUE 22 #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN22_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_ADCN22_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) // Select channel ADCn.23. #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN23_VALUE 23 #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN23_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_ADCN23_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) // Select channel ADCn.24. #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN24_VALUE 24 #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN24_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_ADCN24_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) // Select channel ADCn.25. #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN25_VALUE 25 #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN25_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_ADCN25_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) // Select channel ADCn.26. #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN26_VALUE 26 #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN26_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_ADCN26_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) // Select channel ADCn.27. #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN27_VALUE 27 #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN27_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_ADCN27_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) // Select channel ADCn.28. #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN28_VALUE 28 #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN28_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_ADCN28_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) // Select channel ADCn.29. #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN29_VALUE 29 #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN29_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_ADCN29_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) // Select channel ADCn.30. #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN30_VALUE 30 #define SI32_SARADC_A_SQ3210_TS0MUX_ADCN30_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_ADCN30_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) // None - End the sequence. #define SI32_SARADC_A_SQ3210_TS0MUX_END_VALUE 31 #define SI32_SARADC_A_SQ3210_TS0MUX_END_U32 \ (SI32_SARADC_A_SQ3210_TS0MUX_END_VALUE << SI32_SARADC_A_SQ3210_TS0MUX_SHIFT) #define SI32_SARADC_A_SQ3210_TS1CHR_MASK 0x00000300 #define SI32_SARADC_A_SQ3210_TS1CHR_SHIFT 8 // Select conversion characteristic 0 for time slot 1. #define SI32_SARADC_A_SQ3210_TS1CHR_CC0_VALUE 0 #define SI32_SARADC_A_SQ3210_TS1CHR_CC0_U32 \ (SI32_SARADC_A_SQ3210_TS1CHR_CC0_VALUE << SI32_SARADC_A_SQ3210_TS1CHR_SHIFT) // Select conversion characteristic 1 for time slot 1. #define SI32_SARADC_A_SQ3210_TS1CHR_CC1_VALUE 1 #define SI32_SARADC_A_SQ3210_TS1CHR_CC1_U32 \ (SI32_SARADC_A_SQ3210_TS1CHR_CC1_VALUE << SI32_SARADC_A_SQ3210_TS1CHR_SHIFT) // Select conversion characteristic 2 for time slot 1. #define SI32_SARADC_A_SQ3210_TS1CHR_CC2_VALUE 2 #define SI32_SARADC_A_SQ3210_TS1CHR_CC2_U32 \ (SI32_SARADC_A_SQ3210_TS1CHR_CC2_VALUE << SI32_SARADC_A_SQ3210_TS1CHR_SHIFT) // Select conversion characteristic 3 for time slot 1. #define SI32_SARADC_A_SQ3210_TS1CHR_CC3_VALUE 3 #define SI32_SARADC_A_SQ3210_TS1CHR_CC3_U32 \ (SI32_SARADC_A_SQ3210_TS1CHR_CC3_VALUE << SI32_SARADC_A_SQ3210_TS1CHR_SHIFT) #define SI32_SARADC_A_SQ3210_TS1MUX_MASK 0x00007C00 #define SI32_SARADC_A_SQ3210_TS1MUX_SHIFT 10 // Select channel ADCn.0. #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN0_VALUE 0 #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN0_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_ADCN0_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) // Select channel ADCn.1. #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN1_VALUE 1 #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN1_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_ADCN1_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) // Select channel ADCn.2. #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN2_VALUE 2 #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN2_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_ADCN2_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) // Select channel ADCn.3. #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN3_VALUE 3 #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN3_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_ADCN3_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) // Select channel ADCn.4. #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN4_VALUE 4 #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN4_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_ADCN4_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) // Select channel ADCn.5. #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN5_VALUE 5 #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN5_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_ADCN5_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) // Select channel ADCn.6. #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN6_VALUE 6 #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN6_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_ADCN6_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) // Select channel ADCn.7. #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN7_VALUE 7 #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN7_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_ADCN7_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) // Select channel ADCn.8. #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN8_VALUE 8 #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN8_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_ADCN8_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) // Select channel ADCn.9. #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN9_VALUE 9 #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN9_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_ADCN9_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) // Select channel ADCn.10. #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN10_VALUE 10 #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN10_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_ADCN10_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) // Select channel ADCn.11. #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN11_VALUE 11 #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN11_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_ADCN11_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) // Select channel ADCn.12. #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN12_VALUE 12 #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN12_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_ADCN12_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) // Select channel ADCn.13. #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN13_VALUE 13 #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN13_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_ADCN13_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) // Select channel ADCn.14. #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN14_VALUE 14 #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN14_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_ADCN14_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) // Select channel ADCn.15. #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN15_VALUE 15 #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN15_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_ADCN15_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) // Select channel ADCn.16. #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN16_VALUE 16 #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN16_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_ADCN16_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) // Select channel ADCn.17. #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN17_VALUE 17 #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN17_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_ADCN17_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) // Select channel ADCn.18. #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN18_VALUE 18 #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN18_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_ADCN18_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) // Select channel ADCn.19. #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN19_VALUE 19 #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN19_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_ADCN19_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) // Select channel ADCn.20. #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN20_VALUE 20 #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN20_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_ADCN20_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) // Select channel ADCn.21. #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN21_VALUE 21 #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN21_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_ADCN21_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) // Select channel ADCn.22. #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN22_VALUE 22 #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN22_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_ADCN22_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) // Select channel ADCn.23. #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN23_VALUE 23 #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN23_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_ADCN23_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) // Select channel ADCn.24. #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN24_VALUE 24 #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN24_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_ADCN24_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) // Select channel ADCn.25. #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN25_VALUE 25 #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN25_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_ADCN25_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) // Select channel ADCn.26. #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN26_VALUE 26 #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN26_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_ADCN26_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) // Select channel ADCn.27. #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN27_VALUE 27 #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN27_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_ADCN27_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) // Select channel ADCn.28. #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN28_VALUE 28 #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN28_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_ADCN28_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) // Select channel ADCn.29. #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN29_VALUE 29 #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN29_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_ADCN29_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) // Select channel ADCn.30. #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN30_VALUE 30 #define SI32_SARADC_A_SQ3210_TS1MUX_ADCN30_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_ADCN30_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) // None - End the sequence. #define SI32_SARADC_A_SQ3210_TS1MUX_END_VALUE 31 #define SI32_SARADC_A_SQ3210_TS1MUX_END_U32 \ (SI32_SARADC_A_SQ3210_TS1MUX_END_VALUE << SI32_SARADC_A_SQ3210_TS1MUX_SHIFT) #define SI32_SARADC_A_SQ3210_TS2CHR_MASK 0x00030000 #define SI32_SARADC_A_SQ3210_TS2CHR_SHIFT 16 // Select conversion characteristic 0 for time slot 2. #define SI32_SARADC_A_SQ3210_TS2CHR_CC0_VALUE 0 #define SI32_SARADC_A_SQ3210_TS2CHR_CC0_U32 \ (SI32_SARADC_A_SQ3210_TS2CHR_CC0_VALUE << SI32_SARADC_A_SQ3210_TS2CHR_SHIFT) // Select conversion characteristic 1 for time slot 2. #define SI32_SARADC_A_SQ3210_TS2CHR_CC1_VALUE 1 #define SI32_SARADC_A_SQ3210_TS2CHR_CC1_U32 \ (SI32_SARADC_A_SQ3210_TS2CHR_CC1_VALUE << SI32_SARADC_A_SQ3210_TS2CHR_SHIFT) // Select conversion characteristic 2 for time slot 2. #define SI32_SARADC_A_SQ3210_TS2CHR_CC2_VALUE 2 #define SI32_SARADC_A_SQ3210_TS2CHR_CC2_U32 \ (SI32_SARADC_A_SQ3210_TS2CHR_CC2_VALUE << SI32_SARADC_A_SQ3210_TS2CHR_SHIFT) // Select conversion characteristic 3 for time slot 2. #define SI32_SARADC_A_SQ3210_TS2CHR_CC3_VALUE 3 #define SI32_SARADC_A_SQ3210_TS2CHR_CC3_U32 \ (SI32_SARADC_A_SQ3210_TS2CHR_CC3_VALUE << SI32_SARADC_A_SQ3210_TS2CHR_SHIFT) #define SI32_SARADC_A_SQ3210_TS2MUX_MASK 0x007C0000 #define SI32_SARADC_A_SQ3210_TS2MUX_SHIFT 18 // Select channel ADCn.0. #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN0_VALUE 0 #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN0_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_ADCN0_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) // Select channel ADCn.1. #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN1_VALUE 1 #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN1_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_ADCN1_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) // Select channel ADCn.2. #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN2_VALUE 2 #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN2_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_ADCN2_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) // Select channel ADCn.3. #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN3_VALUE 3 #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN3_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_ADCN3_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) // Select channel ADCn.4. #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN4_VALUE 4 #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN4_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_ADCN4_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) // Select channel ADCn.5. #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN5_VALUE 5 #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN5_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_ADCN5_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) // Select channel ADCn.6. #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN6_VALUE 6 #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN6_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_ADCN6_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) // Select channel ADCn.7. #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN7_VALUE 7 #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN7_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_ADCN7_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) // Select channel ADCn.8. #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN8_VALUE 8 #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN8_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_ADCN8_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) // Select channel ADCn.9. #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN9_VALUE 9 #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN9_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_ADCN9_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) // Select channel ADCn.10. #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN10_VALUE 10 #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN10_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_ADCN10_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) // Select channel ADCn.11. #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN11_VALUE 11 #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN11_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_ADCN11_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) // Select channel ADCn.12. #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN12_VALUE 12 #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN12_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_ADCN12_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) // Select channel ADCn.13. #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN13_VALUE 13 #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN13_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_ADCN13_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) // Select channel ADCn.14. #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN14_VALUE 14 #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN14_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_ADCN14_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) // Select channel ADCn.15. #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN15_VALUE 15 #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN15_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_ADCN15_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) // Select channel ADCn.16. #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN16_VALUE 16 #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN16_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_ADCN16_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) // Select channel ADCn.17. #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN17_VALUE 17 #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN17_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_ADCN17_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) // Select channel ADCn.18. #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN18_VALUE 18 #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN18_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_ADCN18_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) // Select channel ADCn.19. #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN19_VALUE 19 #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN19_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_ADCN19_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) // Select channel ADCn.20. #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN20_VALUE 20 #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN20_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_ADCN20_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) // Select channel ADCn.21. #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN21_VALUE 21 #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN21_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_ADCN21_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) // Select channel ADCn.22. #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN22_VALUE 22 #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN22_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_ADCN22_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) // Select channel ADCn.23. #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN23_VALUE 23 #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN23_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_ADCN23_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) // Select channel ADCn.24. #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN24_VALUE 24 #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN24_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_ADCN24_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) // Select channel ADCn.25. #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN25_VALUE 25 #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN25_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_ADCN25_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) // Select channel ADCn.26. #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN26_VALUE 26 #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN26_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_ADCN26_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) // Select channel ADCn.27. #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN27_VALUE 27 #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN27_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_ADCN27_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) // Select channel ADCn.28. #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN28_VALUE 28 #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN28_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_ADCN28_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) // Select channel ADCn.29. #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN29_VALUE 29 #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN29_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_ADCN29_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) // Select channel ADCn.30. #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN30_VALUE 30 #define SI32_SARADC_A_SQ3210_TS2MUX_ADCN30_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_ADCN30_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) // None - End the sequence. #define SI32_SARADC_A_SQ3210_TS2MUX_END_VALUE 31 #define SI32_SARADC_A_SQ3210_TS2MUX_END_U32 \ (SI32_SARADC_A_SQ3210_TS2MUX_END_VALUE << SI32_SARADC_A_SQ3210_TS2MUX_SHIFT) #define SI32_SARADC_A_SQ3210_TS3CHR_MASK 0x03000000 #define SI32_SARADC_A_SQ3210_TS3CHR_SHIFT 24 // Select conversion characteristic 0 for time slot 3. #define SI32_SARADC_A_SQ3210_TS3CHR_CC0_VALUE 0 #define SI32_SARADC_A_SQ3210_TS3CHR_CC0_U32 \ (SI32_SARADC_A_SQ3210_TS3CHR_CC0_VALUE << SI32_SARADC_A_SQ3210_TS3CHR_SHIFT) // Select conversion characteristic 1 for time slot 3. #define SI32_SARADC_A_SQ3210_TS3CHR_CC1_VALUE 1 #define SI32_SARADC_A_SQ3210_TS3CHR_CC1_U32 \ (SI32_SARADC_A_SQ3210_TS3CHR_CC1_VALUE << SI32_SARADC_A_SQ3210_TS3CHR_SHIFT) // Select conversion characteristic 2 for time slot 3. #define SI32_SARADC_A_SQ3210_TS3CHR_CC2_VALUE 2 #define SI32_SARADC_A_SQ3210_TS3CHR_CC2_U32 \ (SI32_SARADC_A_SQ3210_TS3CHR_CC2_VALUE << SI32_SARADC_A_SQ3210_TS3CHR_SHIFT) // Select conversion characteristic 3 for time slot 3. #define SI32_SARADC_A_SQ3210_TS3CHR_CC3_VALUE 3 #define SI32_SARADC_A_SQ3210_TS3CHR_CC3_U32 \ (SI32_SARADC_A_SQ3210_TS3CHR_CC3_VALUE << SI32_SARADC_A_SQ3210_TS3CHR_SHIFT) #define SI32_SARADC_A_SQ3210_TS3MUX_MASK 0x7C000000 #define SI32_SARADC_A_SQ3210_TS3MUX_SHIFT 26 // Select channel ADCn.0. #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN0_VALUE 0 #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN0_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_ADCN0_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) // Select channel ADCn.1. #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN1_VALUE 1 #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN1_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_ADCN1_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) // Select channel ADCn.2. #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN2_VALUE 2 #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN2_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_ADCN2_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) // Select channel ADCn.3. #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN3_VALUE 3 #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN3_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_ADCN3_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) // Select channel ADCn.4. #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN4_VALUE 4 #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN4_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_ADCN4_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) // Select channel ADCn.5. #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN5_VALUE 5 #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN5_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_ADCN5_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) // Select channel ADCn.6. #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN6_VALUE 6 #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN6_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_ADCN6_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) // Select channel ADCn.7. #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN7_VALUE 7 #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN7_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_ADCN7_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) // Select channel ADCn.8. #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN8_VALUE 8 #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN8_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_ADCN8_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) // Select channel ADCn.9. #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN9_VALUE 9 #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN9_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_ADCN9_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) // Select channel ADCn.10. #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN10_VALUE 10 #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN10_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_ADCN10_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) // Select channel ADCn.11. #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN11_VALUE 11 #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN11_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_ADCN11_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) // Select channel ADCn.12. #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN12_VALUE 12 #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN12_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_ADCN12_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) // Select channel ADCn.13. #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN13_VALUE 13 #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN13_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_ADCN13_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) // Select channel ADCn.14. #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN14_VALUE 14 #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN14_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_ADCN14_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) // Select channel ADCn.15. #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN15_VALUE 15 #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN15_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_ADCN15_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) // Select channel ADCn.16. #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN16_VALUE 16 #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN16_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_ADCN16_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) // Select channel ADCn.17. #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN17_VALUE 17 #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN17_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_ADCN17_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) // Select channel ADCn.18. #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN18_VALUE 18 #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN18_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_ADCN18_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) // Select channel ADCn.19. #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN19_VALUE 19 #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN19_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_ADCN19_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) // Select channel ADCn.20. #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN20_VALUE 20 #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN20_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_ADCN20_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) // Select channel ADCn.21. #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN21_VALUE 21 #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN21_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_ADCN21_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) // Select channel ADCn.22. #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN22_VALUE 22 #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN22_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_ADCN22_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) // Select channel ADCn.23. #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN23_VALUE 23 #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN23_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_ADCN23_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) // Select channel ADCn.24. #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN24_VALUE 24 #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN24_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_ADCN24_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) // Select channel ADCn.25. #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN25_VALUE 25 #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN25_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_ADCN25_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) // Select channel ADCn.26. #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN26_VALUE 26 #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN26_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_ADCN26_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) // Select channel ADCn.27. #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN27_VALUE 27 #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN27_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_ADCN27_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) // Select channel ADCn.28. #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN28_VALUE 28 #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN28_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_ADCN28_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) // Select channel ADCn.29. #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN29_VALUE 29 #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN29_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_ADCN29_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) // Select channel ADCn.30. #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN30_VALUE 30 #define SI32_SARADC_A_SQ3210_TS3MUX_ADCN30_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_ADCN30_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) // None - End the sequence. #define SI32_SARADC_A_SQ3210_TS3MUX_END_VALUE 31 #define SI32_SARADC_A_SQ3210_TS3MUX_END_U32 \ (SI32_SARADC_A_SQ3210_TS3MUX_END_VALUE << SI32_SARADC_A_SQ3210_TS3MUX_SHIFT) struct SI32_SARADC_A_CHAR32_Struct { union { struct { // Conversion Characteristic 2 Gain volatile uint32_t CHR2GN: 1; // Conversion Characteristic 2 Repeat Counter volatile uint32_t CHR2RPT: 3; // Conversion Characteristic 2 Left-Shift Bits volatile uint32_t CHR2LS: 3; // Conversion Characteristic 2 Resolution Selection volatile uint32_t CHR2RSEL: 1; // Conversion Characteristic 2 Window Comparator Interrupt Enable volatile uint32_t CHR2WCIEN: 1; uint32_t reserved0: 7; // Conversion Characteristic 3 Gain volatile uint32_t CHR3GN: 1; // Conversion Characteristic 3 Repeat Counter volatile uint32_t CHR3RPT: 3; // Conversion Characteristic 3 Left-Shift Bits volatile uint32_t CHR3LS: 3; // Conversion Characteristic 3 Resolution Selection volatile uint32_t CHR3RSEL: 1; // Conversion Characteristic 3 Window Comparator Interrupt Enable volatile uint32_t CHR3WCIEN: 1; uint32_t reserved1: 7; }; volatile uint32_t U32; }; }; #define SI32_SARADC_A_CHAR32_CHR2GN_MASK 0x00000001 #define SI32_SARADC_A_CHAR32_CHR2GN_SHIFT 0 // The on-chip PGA gain is 1. #define SI32_SARADC_A_CHAR32_CHR2GN_UNITY_VALUE 0 #define SI32_SARADC_A_CHAR32_CHR2GN_UNITY_U32 \ (SI32_SARADC_A_CHAR32_CHR2GN_UNITY_VALUE << SI32_SARADC_A_CHAR32_CHR2GN_SHIFT) // The on-chip PGA gain is 0.5. #define SI32_SARADC_A_CHAR32_CHR2GN_HALF_VALUE 1 #define SI32_SARADC_A_CHAR32_CHR2GN_HALF_U32 \ (SI32_SARADC_A_CHAR32_CHR2GN_HALF_VALUE << SI32_SARADC_A_CHAR32_CHR2GN_SHIFT) #define SI32_SARADC_A_CHAR32_CHR2RPT_MASK 0x0000000E #define SI32_SARADC_A_CHAR32_CHR2RPT_SHIFT 1 // Accumulate one sample. #define SI32_SARADC_A_CHAR32_CHR2RPT_ACC1_VALUE 0 #define SI32_SARADC_A_CHAR32_CHR2RPT_ACC1_U32 \ (SI32_SARADC_A_CHAR32_CHR2RPT_ACC1_VALUE << SI32_SARADC_A_CHAR32_CHR2RPT_SHIFT) // Accumulate four samples. #define SI32_SARADC_A_CHAR32_CHR2RPT_ACC4_VALUE 1 #define SI32_SARADC_A_CHAR32_CHR2RPT_ACC4_U32 \ (SI32_SARADC_A_CHAR32_CHR2RPT_ACC4_VALUE << SI32_SARADC_A_CHAR32_CHR2RPT_SHIFT) // Accumulate eight samples. #define SI32_SARADC_A_CHAR32_CHR2RPT_ACC8_VALUE 2 #define SI32_SARADC_A_CHAR32_CHR2RPT_ACC8_U32 \ (SI32_SARADC_A_CHAR32_CHR2RPT_ACC8_VALUE << SI32_SARADC_A_CHAR32_CHR2RPT_SHIFT) // Accumulate sixteen samples. #define SI32_SARADC_A_CHAR32_CHR2RPT_ACC16_VALUE 3 #define SI32_SARADC_A_CHAR32_CHR2RPT_ACC16_U32 \ (SI32_SARADC_A_CHAR32_CHR2RPT_ACC16_VALUE << SI32_SARADC_A_CHAR32_CHR2RPT_SHIFT) // Accumulate thirty-two samples (10-bit mode only). #define SI32_SARADC_A_CHAR32_CHR2RPT_ACC32_VALUE 4 #define SI32_SARADC_A_CHAR32_CHR2RPT_ACC32_U32 \ (SI32_SARADC_A_CHAR32_CHR2RPT_ACC32_VALUE << SI32_SARADC_A_CHAR32_CHR2RPT_SHIFT) // Accumulate sixty-four samples (10-bit mode only). #define SI32_SARADC_A_CHAR32_CHR2RPT_ACC64_VALUE 5 #define SI32_SARADC_A_CHAR32_CHR2RPT_ACC64_U32 \ (SI32_SARADC_A_CHAR32_CHR2RPT_ACC64_VALUE << SI32_SARADC_A_CHAR32_CHR2RPT_SHIFT) #define SI32_SARADC_A_CHAR32_CHR2LS_MASK 0x00000070 #define SI32_SARADC_A_CHAR32_CHR2LS_SHIFT 4 #define SI32_SARADC_A_CHAR32_CHR2RSEL_MASK 0x00000080 #define SI32_SARADC_A_CHAR32_CHR2RSEL_SHIFT 7 // Select 10-bit Mode. #define SI32_SARADC_A_CHAR32_CHR2RSEL_B10_VALUE 0 #define SI32_SARADC_A_CHAR32_CHR2RSEL_B10_U32 \ (SI32_SARADC_A_CHAR32_CHR2RSEL_B10_VALUE << SI32_SARADC_A_CHAR32_CHR2RSEL_SHIFT) // Select 12-bit Mode (burst mode must be enabled). #define SI32_SARADC_A_CHAR32_CHR2RSEL_B12_VALUE 1 #define SI32_SARADC_A_CHAR32_CHR2RSEL_B12_U32 \ (SI32_SARADC_A_CHAR32_CHR2RSEL_B12_VALUE << SI32_SARADC_A_CHAR32_CHR2RSEL_SHIFT) #define SI32_SARADC_A_CHAR32_CHR2WCIEN_MASK 0x00000100 #define SI32_SARADC_A_CHAR32_CHR2WCIEN_SHIFT 8 // Disable window comparison interrupts. #define SI32_SARADC_A_CHAR32_CHR2WCIEN_DISABLED_VALUE 0 #define SI32_SARADC_A_CHAR32_CHR2WCIEN_DISABLED_U32 \ (SI32_SARADC_A_CHAR32_CHR2WCIEN_DISABLED_VALUE << SI32_SARADC_A_CHAR32_CHR2WCIEN_SHIFT) // Enabled window comparison interrupts. The window comparator will be used to // check the ADC result on channels that use this characteristic. #define SI32_SARADC_A_CHAR32_CHR2WCIEN_ENABLED_VALUE 1 #define SI32_SARADC_A_CHAR32_CHR2WCIEN_ENABLED_U32 \ (SI32_SARADC_A_CHAR32_CHR2WCIEN_ENABLED_VALUE << SI32_SARADC_A_CHAR32_CHR2WCIEN_SHIFT) #define SI32_SARADC_A_CHAR32_CHR3GN_MASK 0x00010000 #define SI32_SARADC_A_CHAR32_CHR3GN_SHIFT 16 // The on-chip PGA gain is 1. #define SI32_SARADC_A_CHAR32_CHR3GN_UNITY_VALUE 0 #define SI32_SARADC_A_CHAR32_CHR3GN_UNITY_U32 \ (SI32_SARADC_A_CHAR32_CHR3GN_UNITY_VALUE << SI32_SARADC_A_CHAR32_CHR3GN_SHIFT) // The on-chip PGA gain is 0.5. #define SI32_SARADC_A_CHAR32_CHR3GN_HALF_VALUE 1 #define SI32_SARADC_A_CHAR32_CHR3GN_HALF_U32 \ (SI32_SARADC_A_CHAR32_CHR3GN_HALF_VALUE << SI32_SARADC_A_CHAR32_CHR3GN_SHIFT) #define SI32_SARADC_A_CHAR32_CHR3RPT_MASK 0x000E0000 #define SI32_SARADC_A_CHAR32_CHR3RPT_SHIFT 17 // Accumulate one sample. #define SI32_SARADC_A_CHAR32_CHR3RPT_ACC1_VALUE 0 #define SI32_SARADC_A_CHAR32_CHR3RPT_ACC1_U32 \ (SI32_SARADC_A_CHAR32_CHR3RPT_ACC1_VALUE << SI32_SARADC_A_CHAR32_CHR3RPT_SHIFT) // Accumulate four samples. #define SI32_SARADC_A_CHAR32_CHR3RPT_ACC4_VALUE 1 #define SI32_SARADC_A_CHAR32_CHR3RPT_ACC4_U32 \ (SI32_SARADC_A_CHAR32_CHR3RPT_ACC4_VALUE << SI32_SARADC_A_CHAR32_CHR3RPT_SHIFT) // Accumulate eight samples. #define SI32_SARADC_A_CHAR32_CHR3RPT_ACC8_VALUE 2 #define SI32_SARADC_A_CHAR32_CHR3RPT_ACC8_U32 \ (SI32_SARADC_A_CHAR32_CHR3RPT_ACC8_VALUE << SI32_SARADC_A_CHAR32_CHR3RPT_SHIFT) // Accumulate sixteen samples. #define SI32_SARADC_A_CHAR32_CHR3RPT_ACC16_VALUE 3 #define SI32_SARADC_A_CHAR32_CHR3RPT_ACC16_U32 \ (SI32_SARADC_A_CHAR32_CHR3RPT_ACC16_VALUE << SI32_SARADC_A_CHAR32_CHR3RPT_SHIFT) // Accumulate thirty-two samples (10-bit mode only). #define SI32_SARADC_A_CHAR32_CHR3RPT_ACC32_VALUE 4 #define SI32_SARADC_A_CHAR32_CHR3RPT_ACC32_U32 \ (SI32_SARADC_A_CHAR32_CHR3RPT_ACC32_VALUE << SI32_SARADC_A_CHAR32_CHR3RPT_SHIFT) // Accumulate sixty-four samples (10-bit mode only). #define SI32_SARADC_A_CHAR32_CHR3RPT_ACC64_VALUE 5 #define SI32_SARADC_A_CHAR32_CHR3RPT_ACC64_U32 \ (SI32_SARADC_A_CHAR32_CHR3RPT_ACC64_VALUE << SI32_SARADC_A_CHAR32_CHR3RPT_SHIFT) #define SI32_SARADC_A_CHAR32_CHR3LS_MASK 0x00700000 #define SI32_SARADC_A_CHAR32_CHR3LS_SHIFT 20 #define SI32_SARADC_A_CHAR32_CHR3RSEL_MASK 0x00800000 #define SI32_SARADC_A_CHAR32_CHR3RSEL_SHIFT 23 // Select 10-bit Mode. #define SI32_SARADC_A_CHAR32_CHR3RSEL_B10_VALUE 0 #define SI32_SARADC_A_CHAR32_CHR3RSEL_B10_U32 \ (SI32_SARADC_A_CHAR32_CHR3RSEL_B10_VALUE << SI32_SARADC_A_CHAR32_CHR3RSEL_SHIFT) // Select 12-bit Mode (burst mode must be enabled). #define SI32_SARADC_A_CHAR32_CHR3RSEL_B12_VALUE 1 #define SI32_SARADC_A_CHAR32_CHR3RSEL_B12_U32 \ (SI32_SARADC_A_CHAR32_CHR3RSEL_B12_VALUE << SI32_SARADC_A_CHAR32_CHR3RSEL_SHIFT) #define SI32_SARADC_A_CHAR32_CHR3WCIEN_MASK 0x01000000 #define SI32_SARADC_A_CHAR32_CHR3WCIEN_SHIFT 24 // Disable window comparison interrupts. #define SI32_SARADC_A_CHAR32_CHR3WCIEN_DISABLED_VALUE 0 #define SI32_SARADC_A_CHAR32_CHR3WCIEN_DISABLED_U32 \ (SI32_SARADC_A_CHAR32_CHR3WCIEN_DISABLED_VALUE << SI32_SARADC_A_CHAR32_CHR3WCIEN_SHIFT) // Enabled window comparison interrupts. The window comparator will be used to // check the ADC result on channels that use this characteristic. #define SI32_SARADC_A_CHAR32_CHR3WCIEN_ENABLED_VALUE 1 #define SI32_SARADC_A_CHAR32_CHR3WCIEN_ENABLED_U32 \ (SI32_SARADC_A_CHAR32_CHR3WCIEN_ENABLED_VALUE << SI32_SARADC_A_CHAR32_CHR3WCIEN_SHIFT) struct SI32_SARADC_A_CHAR10_Struct { union { struct { // Conversion Characteristic 0 Gain volatile uint32_t CHR0GN: 1; // Conversion Characteristic 0 Repeat Counter volatile uint32_t CHR0RPT: 3; // Conversion Characteristic 0 Left-Shift Bits volatile uint32_t CHR0LS: 3; // Conversion Characteristic 0 Resolution Selection volatile uint32_t CHR0RSEL: 1; // Conversion Characteristic 0 Window Comparator Interrupt Enable volatile uint32_t CHR0WCIEN: 1; uint32_t reserved0: 7; // Conversion Characteristic 1 Gain volatile uint32_t CHR1GN: 1; // Conversion Characteristic 1 Repeat Counter volatile uint32_t CHR1RPT: 3; // Conversion Characteristic 1 Left-Shift Bits volatile uint32_t CHR1LS: 3; // Conversion Characteristic 1 Resolution Selection volatile uint32_t CHR1RSEL: 1; // Conversion Characteristic 1 Window Comparator Interrupt Enable volatile uint32_t CHR1WCIEN: 1; uint32_t reserved1: 7; }; volatile uint32_t U32; }; }; #define SI32_SARADC_A_CHAR10_CHR0GN_MASK 0x00000001 #define SI32_SARADC_A_CHAR10_CHR0GN_SHIFT 0 // The on-chip PGA gain is 1. #define SI32_SARADC_A_CHAR10_CHR0GN_UNITY_VALUE 0 #define SI32_SARADC_A_CHAR10_CHR0GN_UNITY_U32 \ (SI32_SARADC_A_CHAR10_CHR0GN_UNITY_VALUE << SI32_SARADC_A_CHAR10_CHR0GN_SHIFT) // The on-chip PGA gain is 0.5. #define SI32_SARADC_A_CHAR10_CHR0GN_HALF_VALUE 1 #define SI32_SARADC_A_CHAR10_CHR0GN_HALF_U32 \ (SI32_SARADC_A_CHAR10_CHR0GN_HALF_VALUE << SI32_SARADC_A_CHAR10_CHR0GN_SHIFT) #define SI32_SARADC_A_CHAR10_CHR0RPT_MASK 0x0000000E #define SI32_SARADC_A_CHAR10_CHR0RPT_SHIFT 1 // Accumulate one sample. #define SI32_SARADC_A_CHAR10_CHR0RPT_ACC1_VALUE 0 #define SI32_SARADC_A_CHAR10_CHR0RPT_ACC1_U32 \ (SI32_SARADC_A_CHAR10_CHR0RPT_ACC1_VALUE << SI32_SARADC_A_CHAR10_CHR0RPT_SHIFT) // Accumulate four samples. #define SI32_SARADC_A_CHAR10_CHR0RPT_ACC4_VALUE 1 #define SI32_SARADC_A_CHAR10_CHR0RPT_ACC4_U32 \ (SI32_SARADC_A_CHAR10_CHR0RPT_ACC4_VALUE << SI32_SARADC_A_CHAR10_CHR0RPT_SHIFT) // Accumulate eight samples. #define SI32_SARADC_A_CHAR10_CHR0RPT_ACC8_VALUE 2 #define SI32_SARADC_A_CHAR10_CHR0RPT_ACC8_U32 \ (SI32_SARADC_A_CHAR10_CHR0RPT_ACC8_VALUE << SI32_SARADC_A_CHAR10_CHR0RPT_SHIFT) // Accumulate sixteen samples. #define SI32_SARADC_A_CHAR10_CHR0RPT_ACC16_VALUE 3 #define SI32_SARADC_A_CHAR10_CHR0RPT_ACC16_U32 \ (SI32_SARADC_A_CHAR10_CHR0RPT_ACC16_VALUE << SI32_SARADC_A_CHAR10_CHR0RPT_SHIFT) // Accumulate thirty-two samples (10-bit mode only). #define SI32_SARADC_A_CHAR10_CHR0RPT_ACC32_VALUE 4 #define SI32_SARADC_A_CHAR10_CHR0RPT_ACC32_U32 \ (SI32_SARADC_A_CHAR10_CHR0RPT_ACC32_VALUE << SI32_SARADC_A_CHAR10_CHR0RPT_SHIFT) // Accumulate sixty-four samples (10-bit mode only). #define SI32_SARADC_A_CHAR10_CHR0RPT_ACC64_VALUE 5 #define SI32_SARADC_A_CHAR10_CHR0RPT_ACC64_U32 \ (SI32_SARADC_A_CHAR10_CHR0RPT_ACC64_VALUE << SI32_SARADC_A_CHAR10_CHR0RPT_SHIFT) #define SI32_SARADC_A_CHAR10_CHR0LS_MASK 0x00000070 #define SI32_SARADC_A_CHAR10_CHR0LS_SHIFT 4 #define SI32_SARADC_A_CHAR10_CHR0RSEL_MASK 0x00000080 #define SI32_SARADC_A_CHAR10_CHR0RSEL_SHIFT 7 // Select 10-bit Mode. #define SI32_SARADC_A_CHAR10_CHR0RSEL_B10_VALUE 0 #define SI32_SARADC_A_CHAR10_CHR0RSEL_B10_U32 \ (SI32_SARADC_A_CHAR10_CHR0RSEL_B10_VALUE << SI32_SARADC_A_CHAR10_CHR0RSEL_SHIFT) // Select 12-bit Mode (burst mode must be enabled). #define SI32_SARADC_A_CHAR10_CHR0RSEL_B12_VALUE 1 #define SI32_SARADC_A_CHAR10_CHR0RSEL_B12_U32 \ (SI32_SARADC_A_CHAR10_CHR0RSEL_B12_VALUE << SI32_SARADC_A_CHAR10_CHR0RSEL_SHIFT) #define SI32_SARADC_A_CHAR10_CHR0WCIEN_MASK 0x00000100 #define SI32_SARADC_A_CHAR10_CHR0WCIEN_SHIFT 8 // Disable window comparison interrupts. #define SI32_SARADC_A_CHAR10_CHR0WCIEN_DISABLED_VALUE 0 #define SI32_SARADC_A_CHAR10_CHR0WCIEN_DISABLED_U32 \ (SI32_SARADC_A_CHAR10_CHR0WCIEN_DISABLED_VALUE << SI32_SARADC_A_CHAR10_CHR0WCIEN_SHIFT) // Enabled window comparison interrupts. The window comparator will be used to // check the ADC result on channels that use this characteristic. #define SI32_SARADC_A_CHAR10_CHR0WCIEN_ENABLED_VALUE 1 #define SI32_SARADC_A_CHAR10_CHR0WCIEN_ENABLED_U32 \ (SI32_SARADC_A_CHAR10_CHR0WCIEN_ENABLED_VALUE << SI32_SARADC_A_CHAR10_CHR0WCIEN_SHIFT) #define SI32_SARADC_A_CHAR10_CHR1GN_MASK 0x00010000 #define SI32_SARADC_A_CHAR10_CHR1GN_SHIFT 16 // The on-chip PGA gain is 1. #define SI32_SARADC_A_CHAR10_CHR1GN_UNITY_VALUE 0 #define SI32_SARADC_A_CHAR10_CHR1GN_UNITY_U32 \ (SI32_SARADC_A_CHAR10_CHR1GN_UNITY_VALUE << SI32_SARADC_A_CHAR10_CHR1GN_SHIFT) // The on-chip PGA gain is 0.5. #define SI32_SARADC_A_CHAR10_CHR1GN_HALF_VALUE 1 #define SI32_SARADC_A_CHAR10_CHR1GN_HALF_U32 \ (SI32_SARADC_A_CHAR10_CHR1GN_HALF_VALUE << SI32_SARADC_A_CHAR10_CHR1GN_SHIFT) #define SI32_SARADC_A_CHAR10_CHR1RPT_MASK 0x000E0000 #define SI32_SARADC_A_CHAR10_CHR1RPT_SHIFT 17 // Accumulate one sample. #define SI32_SARADC_A_CHAR10_CHR1RPT_ACC1_VALUE 0 #define SI32_SARADC_A_CHAR10_CHR1RPT_ACC1_U32 \ (SI32_SARADC_A_CHAR10_CHR1RPT_ACC1_VALUE << SI32_SARADC_A_CHAR10_CHR1RPT_SHIFT) // Accumulate four samples. #define SI32_SARADC_A_CHAR10_CHR1RPT_ACC4_VALUE 1 #define SI32_SARADC_A_CHAR10_CHR1RPT_ACC4_U32 \ (SI32_SARADC_A_CHAR10_CHR1RPT_ACC4_VALUE << SI32_SARADC_A_CHAR10_CHR1RPT_SHIFT) // Accumulate eight samples. #define SI32_SARADC_A_CHAR10_CHR1RPT_ACC8_VALUE 2 #define SI32_SARADC_A_CHAR10_CHR1RPT_ACC8_U32 \ (SI32_SARADC_A_CHAR10_CHR1RPT_ACC8_VALUE << SI32_SARADC_A_CHAR10_CHR1RPT_SHIFT) // Accumulate sixteen samples. #define SI32_SARADC_A_CHAR10_CHR1RPT_ACC16_VALUE 3 #define SI32_SARADC_A_CHAR10_CHR1RPT_ACC16_U32 \ (SI32_SARADC_A_CHAR10_CHR1RPT_ACC16_VALUE << SI32_SARADC_A_CHAR10_CHR1RPT_SHIFT) // Accumulate thirty-two samples (10-bit mode only). #define SI32_SARADC_A_CHAR10_CHR1RPT_ACC32_VALUE 4 #define SI32_SARADC_A_CHAR10_CHR1RPT_ACC32_U32 \ (SI32_SARADC_A_CHAR10_CHR1RPT_ACC32_VALUE << SI32_SARADC_A_CHAR10_CHR1RPT_SHIFT) // Accumulate sixty-four samples (10-bit mode only). #define SI32_SARADC_A_CHAR10_CHR1RPT_ACC64_VALUE 5 #define SI32_SARADC_A_CHAR10_CHR1RPT_ACC64_U32 \ (SI32_SARADC_A_CHAR10_CHR1RPT_ACC64_VALUE << SI32_SARADC_A_CHAR10_CHR1RPT_SHIFT) #define SI32_SARADC_A_CHAR10_CHR1LS_MASK 0x00700000 #define SI32_SARADC_A_CHAR10_CHR1LS_SHIFT 20 #define SI32_SARADC_A_CHAR10_CHR1RSEL_MASK 0x00800000 #define SI32_SARADC_A_CHAR10_CHR1RSEL_SHIFT 23 // Select 10-bit Mode. #define SI32_SARADC_A_CHAR10_CHR1RSEL_B10_VALUE 0 #define SI32_SARADC_A_CHAR10_CHR1RSEL_B10_U32 \ (SI32_SARADC_A_CHAR10_CHR1RSEL_B10_VALUE << SI32_SARADC_A_CHAR10_CHR1RSEL_SHIFT) // Select 12-bit Mode (burst mode must be enabled). #define SI32_SARADC_A_CHAR10_CHR1RSEL_B12_VALUE 1 #define SI32_SARADC_A_CHAR10_CHR1RSEL_B12_U32 \ (SI32_SARADC_A_CHAR10_CHR1RSEL_B12_VALUE << SI32_SARADC_A_CHAR10_CHR1RSEL_SHIFT) #define SI32_SARADC_A_CHAR10_CHR1WCIEN_MASK 0x01000000 #define SI32_SARADC_A_CHAR10_CHR1WCIEN_SHIFT 24 // Disable window comparison interrupts. #define SI32_SARADC_A_CHAR10_CHR1WCIEN_DISABLED_VALUE 0 #define SI32_SARADC_A_CHAR10_CHR1WCIEN_DISABLED_U32 \ (SI32_SARADC_A_CHAR10_CHR1WCIEN_DISABLED_VALUE << SI32_SARADC_A_CHAR10_CHR1WCIEN_SHIFT) // Enabled window comparison interrupts. The window comparator will be used to // check the ADC result on channels that use this characteristic. #define SI32_SARADC_A_CHAR10_CHR1WCIEN_ENABLED_VALUE 1 #define SI32_SARADC_A_CHAR10_CHR1WCIEN_ENABLED_U32 \ (SI32_SARADC_A_CHAR10_CHR1WCIEN_ENABLED_VALUE << SI32_SARADC_A_CHAR10_CHR1WCIEN_SHIFT) struct SI32_SARADC_A_DATA_Struct { union { struct { // Output Data Word volatile uint32_t DATA_BITS; }; volatile uint32_t U32; }; }; #define SI32_SARADC_A_DATA_DATA_MASK 0xFFFFFFFF #define SI32_SARADC_A_DATA_DATA_SHIFT 0 struct SI32_SARADC_A_WCLIMITS_Struct { union { struct { // Less-Than Window Comparator Limit volatile uint16_t WCLT; // Greater-Than Window Comparator Limit volatile uint16_t WCGT; }; volatile uint32_t U32; }; }; #define SI32_SARADC_A_WCLIMITS_WCLT_MASK 0x0000FFFF #define SI32_SARADC_A_WCLIMITS_WCLT_SHIFT 0 #define SI32_SARADC_A_WCLIMITS_WCGT_MASK 0xFFFF0000 #define SI32_SARADC_A_WCLIMITS_WCGT_SHIFT 16 struct SI32_SARADC_A_ACC_Struct { union { struct { // Accumulator Initial Value volatile uint16_t ACC_BITS; uint32_t reserved0: 16; }; volatile uint32_t U32; }; }; #define SI32_SARADC_A_ACC_ACC_MASK 0x0000FFFF #define SI32_SARADC_A_ACC_ACC_SHIFT 0 struct SI32_SARADC_A_STATUS_Struct { union { struct { // Window Compare Interrupt Flag volatile uint32_t WCI: 1; // Single Conversion Complete Interrupt Flag volatile uint32_t SCCI: 1; // Scan Done Interrupt Flag volatile uint32_t SDI: 1; // FIFO Overrun Interrupt Flag volatile uint32_t FORI: 1; // FIFO Underrun Interrupt Flag volatile uint32_t FURI: 1; uint32_t reserved0: 27; }; volatile uint32_t U32; }; }; #define SI32_SARADC_A_STATUS_WCI_MASK 0x00000001 #define SI32_SARADC_A_STATUS_WCI_SHIFT 0 // Read: A window compare interrupt has not occurred. Write: Clear the interrupt. #define SI32_SARADC_A_STATUS_WCI_NOT_SET_VALUE 0 #define SI32_SARADC_A_STATUS_WCI_NOT_SET_U32 \ (SI32_SARADC_A_STATUS_WCI_NOT_SET_VALUE << SI32_SARADC_A_STATUS_WCI_SHIFT) // Read: A window compare interrupt occurred. Write: Force a window compare // interrupt. #define SI32_SARADC_A_STATUS_WCI_SET_VALUE 1 #define SI32_SARADC_A_STATUS_WCI_SET_U32 \ (SI32_SARADC_A_STATUS_WCI_SET_VALUE << SI32_SARADC_A_STATUS_WCI_SHIFT) #define SI32_SARADC_A_STATUS_SCCI_MASK 0x00000002 #define SI32_SARADC_A_STATUS_SCCI_SHIFT 1 // Read: A single data conversion interrupt has not occurred. Write: Clear the // interrupt. #define SI32_SARADC_A_STATUS_SCCI_NOT_SET_VALUE 0 #define SI32_SARADC_A_STATUS_SCCI_NOT_SET_U32 \ (SI32_SARADC_A_STATUS_SCCI_NOT_SET_VALUE << SI32_SARADC_A_STATUS_SCCI_SHIFT) // Read: A single data conversion interrupt occurred. Write: Force a single data // conversion interrupt. #define SI32_SARADC_A_STATUS_SCCI_SET_VALUE 1 #define SI32_SARADC_A_STATUS_SCCI_SET_U32 \ (SI32_SARADC_A_STATUS_SCCI_SET_VALUE << SI32_SARADC_A_STATUS_SCCI_SHIFT) #define SI32_SARADC_A_STATUS_SDI_MASK 0x00000004 #define SI32_SARADC_A_STATUS_SDI_SHIFT 2 // Read: A scan done interrupt has not occurred. Write: Clear the interrupt. #define SI32_SARADC_A_STATUS_SDI_NOT_SET_VALUE 0 #define SI32_SARADC_A_STATUS_SDI_NOT_SET_U32 \ (SI32_SARADC_A_STATUS_SDI_NOT_SET_VALUE << SI32_SARADC_A_STATUS_SDI_SHIFT) // Read: A scan done interrupt occurred. Write: Force a scan done interrupt. #define SI32_SARADC_A_STATUS_SDI_SET_VALUE 1 #define SI32_SARADC_A_STATUS_SDI_SET_U32 \ (SI32_SARADC_A_STATUS_SDI_SET_VALUE << SI32_SARADC_A_STATUS_SDI_SHIFT) #define SI32_SARADC_A_STATUS_FORI_MASK 0x00000008 #define SI32_SARADC_A_STATUS_FORI_SHIFT 3 // Read: A data FIFO overrun interrupt has not occurred. Write: Clear the // interrupt. #define SI32_SARADC_A_STATUS_FORI_NOT_SET_VALUE 0 #define SI32_SARADC_A_STATUS_FORI_NOT_SET_U32 \ (SI32_SARADC_A_STATUS_FORI_NOT_SET_VALUE << SI32_SARADC_A_STATUS_FORI_SHIFT) // Read: A data FIFO overrun interrupt occurred. Write: Force a data FIFO overrun // interrupt. #define SI32_SARADC_A_STATUS_FORI_SET_VALUE 1 #define SI32_SARADC_A_STATUS_FORI_SET_U32 \ (SI32_SARADC_A_STATUS_FORI_SET_VALUE << SI32_SARADC_A_STATUS_FORI_SHIFT) #define SI32_SARADC_A_STATUS_FURI_MASK 0x00000010 #define SI32_SARADC_A_STATUS_FURI_SHIFT 4 // Read: A data FIFO underrun interrupt has not occurred. Write: Clear the // interrupt. #define SI32_SARADC_A_STATUS_FURI_NOT_SET_VALUE 0 #define SI32_SARADC_A_STATUS_FURI_NOT_SET_U32 \ (SI32_SARADC_A_STATUS_FURI_NOT_SET_VALUE << SI32_SARADC_A_STATUS_FURI_SHIFT) // Read: A data FIFO underrun interrupt occurred. Write: Force a data FIFO underrun // interrupt. #define SI32_SARADC_A_STATUS_FURI_SET_VALUE 1 #define SI32_SARADC_A_STATUS_FURI_SET_U32 \ (SI32_SARADC_A_STATUS_FURI_SET_VALUE << SI32_SARADC_A_STATUS_FURI_SHIFT) struct SI32_SARADC_A_FIFOSTATUS_Struct { union { struct { // FIFO Level volatile uint32_t FIFOLVL: 4; // Data Packing Status volatile uint32_t DPSTS: 1; // Data Ready Flag volatile uint32_t DRDYF: 1; uint32_t reserved0: 26; }; volatile uint32_t U32; }; }; #define SI32_SARADC_A_FIFOSTATUS_FIFOLVL_MASK 0x0000000F #define SI32_SARADC_A_FIFOSTATUS_FIFOLVL_SHIFT 0 #define SI32_SARADC_A_FIFOSTATUS_DPSTS_MASK 0x00000010 #define SI32_SARADC_A_FIFOSTATUS_DPSTS_SHIFT 4 // The next ADC conversion will be written to the lower half-word. #define SI32_SARADC_A_FIFOSTATUS_DPSTS_LOWER_VALUE 0 #define SI32_SARADC_A_FIFOSTATUS_DPSTS_LOWER_U32 \ (SI32_SARADC_A_FIFOSTATUS_DPSTS_LOWER_VALUE << SI32_SARADC_A_FIFOSTATUS_DPSTS_SHIFT) // The next ADC conversion will be written to the upper half-word. #define SI32_SARADC_A_FIFOSTATUS_DPSTS_UPPER_VALUE 1 #define SI32_SARADC_A_FIFOSTATUS_DPSTS_UPPER_U32 \ (SI32_SARADC_A_FIFOSTATUS_DPSTS_UPPER_VALUE << SI32_SARADC_A_FIFOSTATUS_DPSTS_SHIFT) #define SI32_SARADC_A_FIFOSTATUS_DRDYF_MASK 0x00000020 #define SI32_SARADC_A_FIFOSTATUS_DRDYF_SHIFT 5 // New data is not produced yet. #define SI32_SARADC_A_FIFOSTATUS_DRDYF_NOT_SET_VALUE 0 #define SI32_SARADC_A_FIFOSTATUS_DRDYF_NOT_SET_U32 \ (SI32_SARADC_A_FIFOSTATUS_DRDYF_NOT_SET_VALUE << SI32_SARADC_A_FIFOSTATUS_DRDYF_SHIFT) // New data is ready. #define SI32_SARADC_A_FIFOSTATUS_DRDYF_SET_VALUE 1 #define SI32_SARADC_A_FIFOSTATUS_DRDYF_SET_U32 \ (SI32_SARADC_A_FIFOSTATUS_DRDYF_SET_VALUE << SI32_SARADC_A_FIFOSTATUS_DRDYF_SHIFT) typedef struct SI32_SARADC_A_Struct { struct SI32_SARADC_A_CONFIG_Struct CONFIG ; // Base Address + 0x0 volatile uint32_t CONFIG_SET; volatile uint32_t CONFIG_CLR; uint32_t reserved0; struct SI32_SARADC_A_CONTROL_Struct CONTROL ; // Base Address + 0x10 volatile uint32_t CONTROL_SET; volatile uint32_t CONTROL_CLR; uint32_t reserved1; struct SI32_SARADC_A_SQ7654_Struct SQ7654 ; // Base Address + 0x20 uint32_t reserved2; uint32_t reserved3; uint32_t reserved4; struct SI32_SARADC_A_SQ3210_Struct SQ3210 ; // Base Address + 0x30 uint32_t reserved5; uint32_t reserved6; uint32_t reserved7; struct SI32_SARADC_A_CHAR32_Struct CHAR32 ; // Base Address + 0x40 volatile uint32_t CHAR32_SET; volatile uint32_t CHAR32_CLR; uint32_t reserved8; struct SI32_SARADC_A_CHAR10_Struct CHAR10 ; // Base Address + 0x50 volatile uint32_t CHAR10_SET; volatile uint32_t CHAR10_CLR; uint32_t reserved9; struct SI32_SARADC_A_DATA_Struct DATA ; // Base Address + 0x60 uint32_t reserved10; uint32_t reserved11; uint32_t reserved12; struct SI32_SARADC_A_WCLIMITS_Struct WCLIMITS ; // Base Address + 0x70 uint32_t reserved13; uint32_t reserved14; uint32_t reserved15; struct SI32_SARADC_A_ACC_Struct ACC ; // Base Address + 0x80 uint32_t reserved16; uint32_t reserved17; uint32_t reserved18; struct SI32_SARADC_A_STATUS_Struct STATUS ; // Base Address + 0x90 volatile uint32_t STATUS_SET; volatile uint32_t STATUS_CLR; uint32_t reserved19; struct SI32_SARADC_A_FIFOSTATUS_Struct FIFOSTATUS ; // Base Address + 0xa0 uint32_t reserved20; uint32_t reserved21; uint32_t reserved22; uint32_t reserved23[4]; } SI32_SARADC_A_Type; #ifdef __cplusplus } #endif #endif // __SI32_SARADC_A_REGISTERS_H__ //-eof--------------------------------------------------------------------------