//------------------------------------------------------------------------------ // Copyright 2012 (c) Silicon Laboratories Inc. // // SPDX-License-Identifier: Zlib // // This siHAL software is provided 'as-is', without any express or implied // warranty. In no event will the authors be held liable for any damages // arising from the use of this software. // // Permission is granted to anyone to use this software for any purpose, // including commercial applications, and to alter it and redistribute it // freely, subject to the following restrictions: // // 1. The origin of this software must not be misrepresented; you must not // claim that you wrote the original software. If you use this software // in a product, an acknowledgment in the product documentation would be // appreciated but is not required. // 2. Altered source versions must be plainly marked as such, and must not be // misrepresented as being the original software. // 3. This notice may not be removed or altered from any source distribution. //------------------------------------------------------------------------------ // // Script: 0.57 // Version: 1 #ifndef __SI32_DMACTRL_A_REGISTERS_H__ #define __SI32_DMACTRL_A_REGISTERS_H__ #include #ifdef __cplusplus extern "C" { #endif struct SI32_DMACTRL_A_STATUS_Struct { union { struct { // DMA Enable Status volatile uint32_t DMAENSTS: 1; uint32_t reserved0: 3; // State Machine State volatile uint32_t STATE: 4; uint32_t reserved1: 8; // Number of Supported DMA Channels volatile uint32_t NUMCHAN: 5; uint32_t reserved2: 11; }; volatile uint32_t U32; }; }; #define SI32_DMACTRL_A_STATUS_DMAENSTS_MASK 0x00000001 #define SI32_DMACTRL_A_STATUS_DMAENSTS_SHIFT 0 // DMA controller is disabled #define SI32_DMACTRL_A_STATUS_DMAENSTS_NOT_SET_VALUE 0 #define SI32_DMACTRL_A_STATUS_DMAENSTS_NOT_SET_U32 \ (SI32_DMACTRL_A_STATUS_DMAENSTS_NOT_SET_VALUE << SI32_DMACTRL_A_STATUS_DMAENSTS_SHIFT) // DMA controller is enabled. #define SI32_DMACTRL_A_STATUS_DMAENSTS_SET_VALUE 1 #define SI32_DMACTRL_A_STATUS_DMAENSTS_SET_U32 \ (SI32_DMACTRL_A_STATUS_DMAENSTS_SET_VALUE << SI32_DMACTRL_A_STATUS_DMAENSTS_SHIFT) #define SI32_DMACTRL_A_STATUS_STATE_MASK 0x000000F0 #define SI32_DMACTRL_A_STATUS_STATE_SHIFT 4 // Idle. #define SI32_DMACTRL_A_STATUS_STATE_IDLE_VALUE 0 #define SI32_DMACTRL_A_STATUS_STATE_IDLE_U32 \ (SI32_DMACTRL_A_STATUS_STATE_IDLE_VALUE << SI32_DMACTRL_A_STATUS_STATE_SHIFT) // Reading channel controller data. #define SI32_DMACTRL_A_STATUS_STATE_READING_CHANNEL_CONFIG_VALUE 1 #define SI32_DMACTRL_A_STATUS_STATE_READING_CHANNEL_CONFIG_U32 \ (SI32_DMACTRL_A_STATUS_STATE_READING_CHANNEL_CONFIG_VALUE << SI32_DMACTRL_A_STATUS_STATE_SHIFT) // Reading source data end pointer. #define SI32_DMACTRL_A_STATUS_STATE_READING_SOURCE_POINTER_VALUE 2 #define SI32_DMACTRL_A_STATUS_STATE_READING_SOURCE_POINTER_U32 \ (SI32_DMACTRL_A_STATUS_STATE_READING_SOURCE_POINTER_VALUE << SI32_DMACTRL_A_STATUS_STATE_SHIFT) // Reading destination data end pointer. #define SI32_DMACTRL_A_STATUS_STATE_READING_DEST_POINTER_VALUE 3 #define SI32_DMACTRL_A_STATUS_STATE_READING_DEST_POINTER_U32 \ (SI32_DMACTRL_A_STATUS_STATE_READING_DEST_POINTER_VALUE << SI32_DMACTRL_A_STATUS_STATE_SHIFT) // Reading source data. #define SI32_DMACTRL_A_STATUS_STATE_READING_SOURCE_DATA_VALUE 4 #define SI32_DMACTRL_A_STATUS_STATE_READING_SOURCE_DATA_U32 \ (SI32_DMACTRL_A_STATUS_STATE_READING_SOURCE_DATA_VALUE << SI32_DMACTRL_A_STATUS_STATE_SHIFT) // Writing destination data. #define SI32_DMACTRL_A_STATUS_STATE_WRITING_DEST_DATA_VALUE 5 #define SI32_DMACTRL_A_STATUS_STATE_WRITING_DEST_DATA_U32 \ (SI32_DMACTRL_A_STATUS_STATE_WRITING_DEST_DATA_VALUE << SI32_DMACTRL_A_STATUS_STATE_SHIFT) // Waiting for a DMA request to clear. #define SI32_DMACTRL_A_STATUS_STATE_WAITING_DMA_REQ_CLEAR_VALUE 6 #define SI32_DMACTRL_A_STATUS_STATE_WAITING_DMA_REQ_CLEAR_U32 \ (SI32_DMACTRL_A_STATUS_STATE_WAITING_DMA_REQ_CLEAR_VALUE << SI32_DMACTRL_A_STATUS_STATE_SHIFT) // Writing channel controller data. #define SI32_DMACTRL_A_STATUS_STATE_WRITING_CHANNEL_CONFIG_VALUE 7 #define SI32_DMACTRL_A_STATUS_STATE_WRITING_CHANNEL_CONFIG_U32 \ (SI32_DMACTRL_A_STATUS_STATE_WRITING_CHANNEL_CONFIG_VALUE << SI32_DMACTRL_A_STATUS_STATE_SHIFT) // Stalled. #define SI32_DMACTRL_A_STATUS_STATE_STALLED_VALUE 8 #define SI32_DMACTRL_A_STATUS_STATE_STALLED_U32 \ (SI32_DMACTRL_A_STATUS_STATE_STALLED_VALUE << SI32_DMACTRL_A_STATUS_STATE_SHIFT) // Done. #define SI32_DMACTRL_A_STATUS_STATE_DONE_VALUE 9 #define SI32_DMACTRL_A_STATUS_STATE_DONE_U32 \ (SI32_DMACTRL_A_STATUS_STATE_DONE_VALUE << SI32_DMACTRL_A_STATUS_STATE_SHIFT) // Peripheral scatter-gather transition. #define SI32_DMACTRL_A_STATUS_STATE_SCATTER_GATHER_TRANSITION_VALUE 10 #define SI32_DMACTRL_A_STATUS_STATE_SCATTER_GATHER_TRANSITION_U32 \ (SI32_DMACTRL_A_STATUS_STATE_SCATTER_GATHER_TRANSITION_VALUE << SI32_DMACTRL_A_STATUS_STATE_SHIFT) #define SI32_DMACTRL_A_STATUS_NUMCHAN_MASK 0x001F0000 #define SI32_DMACTRL_A_STATUS_NUMCHAN_SHIFT 16 struct SI32_DMACTRL_A_CONFIG_Struct { union { struct { // DMA Enable volatile uint32_t DMAEN: 1; uint32_t reserved0: 31; }; volatile uint32_t U32; }; }; #define SI32_DMACTRL_A_CONFIG_DMAEN_MASK 0x00000001 #define SI32_DMACTRL_A_CONFIG_DMAEN_SHIFT 0 // Disable the DMA controller. #define SI32_DMACTRL_A_CONFIG_DMAEN_DISABLED_VALUE 0 #define SI32_DMACTRL_A_CONFIG_DMAEN_DISABLED_U32 \ (SI32_DMACTRL_A_CONFIG_DMAEN_DISABLED_VALUE << SI32_DMACTRL_A_CONFIG_DMAEN_SHIFT) // Enable the DMA controller. #define SI32_DMACTRL_A_CONFIG_DMAEN_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CONFIG_DMAEN_ENABLED_U32 \ (SI32_DMACTRL_A_CONFIG_DMAEN_ENABLED_VALUE << SI32_DMACTRL_A_CONFIG_DMAEN_SHIFT) struct SI32_DMACTRL_A_BASEPTR_Struct { union { struct { uint32_t reserved0: 5; // Control Base Pointer volatile uint32_t BASEPTR_BITS: 27; }; volatile uint32_t U32; }; }; #define SI32_DMACTRL_A_BASEPTR_BASEPTR_MASK 0xFFFFFFE0 #define SI32_DMACTRL_A_BASEPTR_BASEPTR_SHIFT 5 struct SI32_DMACTRL_A_ABASEPTR_Struct { union { struct { // Alternate Control Base Pointer volatile uint32_t ABASEPTR_BITS; }; volatile uint32_t U32; }; }; #define SI32_DMACTRL_A_ABASEPTR_ABASEPTR_MASK 0xFFFFFFFF #define SI32_DMACTRL_A_ABASEPTR_ABASEPTR_SHIFT 0 struct SI32_DMACTRL_A_CHSTATUS_Struct { union { struct { // Channel 0 Status volatile uint32_t CH0: 1; // Channel 1 Status volatile uint32_t CH1: 1; // Channel 2 Status volatile uint32_t CH2: 1; // Channel 3 Status volatile uint32_t CH3: 1; // Channel 4 Status volatile uint32_t CH4: 1; // Channel 5 Status volatile uint32_t CH5: 1; // Channel 6 Status volatile uint32_t CH6: 1; // Channel 7 Status volatile uint32_t CH7: 1; // Channel 8 Status volatile uint32_t CH8: 1; // Channel 9 Status volatile uint32_t CH9: 1; // Channel 10 Status volatile uint32_t CH10: 1; // Channel 11 Status volatile uint32_t CH11: 1; // Channel 12 Status volatile uint32_t CH12: 1; // Channel 13 Status volatile uint32_t CH13: 1; // Channel 14 Status volatile uint32_t CH14: 1; // Channel 15 Status volatile uint32_t CH15: 1; // Channel 16 Status volatile uint32_t CH16: 1; // Channel 17 Status volatile uint32_t CH17: 1; // Channel 18 Status volatile uint32_t CH18: 1; // Channel 19 Status volatile uint32_t CH19: 1; // Channel 20 Status volatile uint32_t CH20: 1; // Channel 21 Status volatile uint32_t CH21: 1; // Channel 22 Status volatile uint32_t CH22: 1; // Channel 23 Status volatile uint32_t CH23: 1; // Channel 24 Status volatile uint32_t CH24: 1; // Channel 25 Status volatile uint32_t CH25: 1; // Channel 26 Status volatile uint32_t CH26: 1; // Channel 27 Status volatile uint32_t CH27: 1; // Channel 28 Status volatile uint32_t CH28: 1; // Channel 29 Status volatile uint32_t CH29: 1; // Channel 30 Status volatile uint32_t CH30: 1; // Channel 31 Status volatile uint32_t CH31: 1; }; volatile uint32_t U32; }; }; #define SI32_DMACTRL_A_CHSTATUS_CH0_MASK 0x00000001 #define SI32_DMACTRL_A_CHSTATUS_CH0_SHIFT 0 // DMA Channel 0 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH0_NOT_WAITING_VALUE 0 #define SI32_DMACTRL_A_CHSTATUS_CH0_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH0_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH0_SHIFT) // DMA Channel 0 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH0_WAITING_VALUE 1 #define SI32_DMACTRL_A_CHSTATUS_CH0_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH0_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH0_SHIFT) #define SI32_DMACTRL_A_CHSTATUS_CH1_MASK 0x00000002 #define SI32_DMACTRL_A_CHSTATUS_CH1_SHIFT 1 // DMA Channel 1 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH1_NOT_WAITING_VALUE 0 #define SI32_DMACTRL_A_CHSTATUS_CH1_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH1_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH1_SHIFT) // DMA Channel 1 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH1_WAITING_VALUE 1 #define SI32_DMACTRL_A_CHSTATUS_CH1_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH1_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH1_SHIFT) #define SI32_DMACTRL_A_CHSTATUS_CH2_MASK 0x00000004 #define SI32_DMACTRL_A_CHSTATUS_CH2_SHIFT 2 // DMA Channel 2 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH2_NOT_WAITING_VALUE 0 #define SI32_DMACTRL_A_CHSTATUS_CH2_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH2_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH2_SHIFT) // DMA Channel 2 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH2_WAITING_VALUE 1 #define SI32_DMACTRL_A_CHSTATUS_CH2_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH2_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH2_SHIFT) #define SI32_DMACTRL_A_CHSTATUS_CH3_MASK 0x00000008 #define SI32_DMACTRL_A_CHSTATUS_CH3_SHIFT 3 // DMA Channel 3 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH3_NOT_WAITING_VALUE 0 #define SI32_DMACTRL_A_CHSTATUS_CH3_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH3_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH3_SHIFT) // DMA Channel 3 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH3_WAITING_VALUE 1 #define SI32_DMACTRL_A_CHSTATUS_CH3_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH3_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH3_SHIFT) #define SI32_DMACTRL_A_CHSTATUS_CH4_MASK 0x00000010 #define SI32_DMACTRL_A_CHSTATUS_CH4_SHIFT 4 // DMA Channel 4 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH4_NOT_WAITING_VALUE 0 #define SI32_DMACTRL_A_CHSTATUS_CH4_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH4_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH4_SHIFT) // DMA Channel 4 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH4_WAITING_VALUE 1 #define SI32_DMACTRL_A_CHSTATUS_CH4_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH4_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH4_SHIFT) #define SI32_DMACTRL_A_CHSTATUS_CH5_MASK 0x00000020 #define SI32_DMACTRL_A_CHSTATUS_CH5_SHIFT 5 // DMA Channel 5 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH5_NOT_WAITING_VALUE 0 #define SI32_DMACTRL_A_CHSTATUS_CH5_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH5_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH5_SHIFT) // DMA Channel 5 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH5_WAITING_VALUE 1 #define SI32_DMACTRL_A_CHSTATUS_CH5_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH5_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH5_SHIFT) #define SI32_DMACTRL_A_CHSTATUS_CH6_MASK 0x00000040 #define SI32_DMACTRL_A_CHSTATUS_CH6_SHIFT 6 // DMA Channel 6 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH6_NOT_WAITING_VALUE 0 #define SI32_DMACTRL_A_CHSTATUS_CH6_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH6_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH6_SHIFT) // DMA Channel 6 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH6_WAITING_VALUE 1 #define SI32_DMACTRL_A_CHSTATUS_CH6_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH6_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH6_SHIFT) #define SI32_DMACTRL_A_CHSTATUS_CH7_MASK 0x00000080 #define SI32_DMACTRL_A_CHSTATUS_CH7_SHIFT 7 // DMA Channel 7 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH7_NOT_WAITING_VALUE 0 #define SI32_DMACTRL_A_CHSTATUS_CH7_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH7_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH7_SHIFT) // DMA Channel 7 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH7_WAITING_VALUE 1 #define SI32_DMACTRL_A_CHSTATUS_CH7_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH7_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH7_SHIFT) #define SI32_DMACTRL_A_CHSTATUS_CH8_MASK 0x00000100 #define SI32_DMACTRL_A_CHSTATUS_CH8_SHIFT 8 // DMA Channel 8 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH8_NOT_WAITING_VALUE 0 #define SI32_DMACTRL_A_CHSTATUS_CH8_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH8_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH8_SHIFT) // DMA Channel 8 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH8_WAITING_VALUE 1 #define SI32_DMACTRL_A_CHSTATUS_CH8_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH8_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH8_SHIFT) #define SI32_DMACTRL_A_CHSTATUS_CH9_MASK 0x00000200 #define SI32_DMACTRL_A_CHSTATUS_CH9_SHIFT 9 // DMA Channel 9 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH9_NOT_WAITING_VALUE 0 #define SI32_DMACTRL_A_CHSTATUS_CH9_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH9_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH9_SHIFT) // DMA Channel 9 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH9_WAITING_VALUE 1 #define SI32_DMACTRL_A_CHSTATUS_CH9_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH9_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH9_SHIFT) #define SI32_DMACTRL_A_CHSTATUS_CH10_MASK 0x00000400 #define SI32_DMACTRL_A_CHSTATUS_CH10_SHIFT 10 // DMA Channel 10 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH10_NOT_WAITING_VALUE 0 #define SI32_DMACTRL_A_CHSTATUS_CH10_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH10_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH10_SHIFT) // DMA Channel 10 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH10_WAITING_VALUE 1 #define SI32_DMACTRL_A_CHSTATUS_CH10_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH10_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH10_SHIFT) #define SI32_DMACTRL_A_CHSTATUS_CH11_MASK 0x00000800 #define SI32_DMACTRL_A_CHSTATUS_CH11_SHIFT 11 // DMA Channel 11 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH11_NOT_WAITING_VALUE 0 #define SI32_DMACTRL_A_CHSTATUS_CH11_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH11_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH11_SHIFT) // DMA Channel 11 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH11_WAITING_VALUE 1 #define SI32_DMACTRL_A_CHSTATUS_CH11_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH11_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH11_SHIFT) #define SI32_DMACTRL_A_CHSTATUS_CH12_MASK 0x00001000 #define SI32_DMACTRL_A_CHSTATUS_CH12_SHIFT 12 // DMA Channel 12 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH12_NOT_WAITING_VALUE 0 #define SI32_DMACTRL_A_CHSTATUS_CH12_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH12_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH12_SHIFT) // DMA Channel 12 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH12_WAITING_VALUE 1 #define SI32_DMACTRL_A_CHSTATUS_CH12_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH12_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH12_SHIFT) #define SI32_DMACTRL_A_CHSTATUS_CH13_MASK 0x00002000 #define SI32_DMACTRL_A_CHSTATUS_CH13_SHIFT 13 // DMA Channel 13 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH13_NOT_WAITING_VALUE 0 #define SI32_DMACTRL_A_CHSTATUS_CH13_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH13_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH13_SHIFT) // DMA Channel 13 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH13_WAITING_VALUE 1 #define SI32_DMACTRL_A_CHSTATUS_CH13_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH13_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH13_SHIFT) #define SI32_DMACTRL_A_CHSTATUS_CH14_MASK 0x00004000 #define SI32_DMACTRL_A_CHSTATUS_CH14_SHIFT 14 // DMA Channel 14 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH14_NOT_WAITING_VALUE 0 #define SI32_DMACTRL_A_CHSTATUS_CH14_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH14_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH14_SHIFT) // DMA Channel 14 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH14_WAITING_VALUE 1 #define SI32_DMACTRL_A_CHSTATUS_CH14_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH14_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH14_SHIFT) #define SI32_DMACTRL_A_CHSTATUS_CH15_MASK 0x00008000 #define SI32_DMACTRL_A_CHSTATUS_CH15_SHIFT 15 // DMA Channel 15 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH15_NOT_WAITING_VALUE 0 #define SI32_DMACTRL_A_CHSTATUS_CH15_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH15_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH15_SHIFT) // DMA Channel 15 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH15_WAITING_VALUE 1 #define SI32_DMACTRL_A_CHSTATUS_CH15_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH15_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH15_SHIFT) #define SI32_DMACTRL_A_CHSTATUS_CH16_MASK 0x00010000 #define SI32_DMACTRL_A_CHSTATUS_CH16_SHIFT 16 // DMA Channel 16 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH16_NOT_WAITING_VALUE 0 #define SI32_DMACTRL_A_CHSTATUS_CH16_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH16_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH16_SHIFT) // DMA Channel 16 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH16_WAITING_VALUE 1 #define SI32_DMACTRL_A_CHSTATUS_CH16_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH16_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH16_SHIFT) #define SI32_DMACTRL_A_CHSTATUS_CH17_MASK 0x00020000 #define SI32_DMACTRL_A_CHSTATUS_CH17_SHIFT 17 // DMA Channel 17 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH17_NOT_WAITING_VALUE 0 #define SI32_DMACTRL_A_CHSTATUS_CH17_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH17_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH17_SHIFT) // DMA Channel 17 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH17_WAITING_VALUE 1 #define SI32_DMACTRL_A_CHSTATUS_CH17_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH17_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH17_SHIFT) #define SI32_DMACTRL_A_CHSTATUS_CH18_MASK 0x00040000 #define SI32_DMACTRL_A_CHSTATUS_CH18_SHIFT 18 // DMA Channel 18 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH18_NOT_WAITING_VALUE 0 #define SI32_DMACTRL_A_CHSTATUS_CH18_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH18_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH18_SHIFT) // DMA Channel 18 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH18_WAITING_VALUE 1 #define SI32_DMACTRL_A_CHSTATUS_CH18_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH18_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH18_SHIFT) #define SI32_DMACTRL_A_CHSTATUS_CH19_MASK 0x00080000 #define SI32_DMACTRL_A_CHSTATUS_CH19_SHIFT 19 // DMA Channel 19 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH19_NOT_WAITING_VALUE 0 #define SI32_DMACTRL_A_CHSTATUS_CH19_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH19_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH19_SHIFT) // DMA Channel 19 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH19_WAITING_VALUE 1 #define SI32_DMACTRL_A_CHSTATUS_CH19_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH19_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH19_SHIFT) #define SI32_DMACTRL_A_CHSTATUS_CH20_MASK 0x00100000 #define SI32_DMACTRL_A_CHSTATUS_CH20_SHIFT 20 // DMA Channel 20 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH20_NOT_WAITING_VALUE 0 #define SI32_DMACTRL_A_CHSTATUS_CH20_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH20_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH20_SHIFT) // DMA Channel 20 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH20_WAITING_VALUE 1 #define SI32_DMACTRL_A_CHSTATUS_CH20_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH20_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH20_SHIFT) #define SI32_DMACTRL_A_CHSTATUS_CH21_MASK 0x00200000 #define SI32_DMACTRL_A_CHSTATUS_CH21_SHIFT 21 // DMA Channel 21 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH21_NOT_WAITING_VALUE 0 #define SI32_DMACTRL_A_CHSTATUS_CH21_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH21_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH21_SHIFT) // DMA Channel 21 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH21_WAITING_VALUE 1 #define SI32_DMACTRL_A_CHSTATUS_CH21_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH21_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH21_SHIFT) #define SI32_DMACTRL_A_CHSTATUS_CH22_MASK 0x00400000 #define SI32_DMACTRL_A_CHSTATUS_CH22_SHIFT 22 // DMA Channel 22 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH22_NOT_WAITING_VALUE 0 #define SI32_DMACTRL_A_CHSTATUS_CH22_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH22_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH22_SHIFT) // DMA Channel 22 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH22_WAITING_VALUE 1 #define SI32_DMACTRL_A_CHSTATUS_CH22_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH22_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH22_SHIFT) #define SI32_DMACTRL_A_CHSTATUS_CH23_MASK 0x00800000 #define SI32_DMACTRL_A_CHSTATUS_CH23_SHIFT 23 // DMA Channel 23 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH23_NOT_WAITING_VALUE 0 #define SI32_DMACTRL_A_CHSTATUS_CH23_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH23_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH23_SHIFT) // DMA Channel 23 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH23_WAITING_VALUE 1 #define SI32_DMACTRL_A_CHSTATUS_CH23_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH23_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH23_SHIFT) #define SI32_DMACTRL_A_CHSTATUS_CH24_MASK 0x01000000 #define SI32_DMACTRL_A_CHSTATUS_CH24_SHIFT 24 // DMA Channel 24 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH24_NOT_WAITING_VALUE 0 #define SI32_DMACTRL_A_CHSTATUS_CH24_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH24_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH24_SHIFT) // DMA Channel 24 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH24_WAITING_VALUE 1 #define SI32_DMACTRL_A_CHSTATUS_CH24_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH24_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH24_SHIFT) #define SI32_DMACTRL_A_CHSTATUS_CH25_MASK 0x02000000 #define SI32_DMACTRL_A_CHSTATUS_CH25_SHIFT 25 // DMA Channel 25 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH25_NOT_WAITING_VALUE 0 #define SI32_DMACTRL_A_CHSTATUS_CH25_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH25_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH25_SHIFT) // DMA Channel 25 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH25_WAITING_VALUE 1 #define SI32_DMACTRL_A_CHSTATUS_CH25_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH25_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH25_SHIFT) #define SI32_DMACTRL_A_CHSTATUS_CH26_MASK 0x04000000 #define SI32_DMACTRL_A_CHSTATUS_CH26_SHIFT 26 // DMA Channel 26 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH26_NOT_WAITING_VALUE 0 #define SI32_DMACTRL_A_CHSTATUS_CH26_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH26_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH26_SHIFT) // DMA Channel 26 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH26_WAITING_VALUE 1 #define SI32_DMACTRL_A_CHSTATUS_CH26_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH26_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH26_SHIFT) #define SI32_DMACTRL_A_CHSTATUS_CH27_MASK 0x08000000 #define SI32_DMACTRL_A_CHSTATUS_CH27_SHIFT 27 // DMA Channel 27 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH27_NOT_WAITING_VALUE 0 #define SI32_DMACTRL_A_CHSTATUS_CH27_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH27_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH27_SHIFT) // DMA Channel 27 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH27_WAITING_VALUE 1 #define SI32_DMACTRL_A_CHSTATUS_CH27_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH27_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH27_SHIFT) #define SI32_DMACTRL_A_CHSTATUS_CH28_MASK 0x10000000 #define SI32_DMACTRL_A_CHSTATUS_CH28_SHIFT 28 // DMA Channel 28 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH28_NOT_WAITING_VALUE 0 #define SI32_DMACTRL_A_CHSTATUS_CH28_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH28_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH28_SHIFT) // DMA Channel 28 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH28_WAITING_VALUE 1 #define SI32_DMACTRL_A_CHSTATUS_CH28_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH28_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH28_SHIFT) #define SI32_DMACTRL_A_CHSTATUS_CH29_MASK 0x20000000 #define SI32_DMACTRL_A_CHSTATUS_CH29_SHIFT 29 // DMA Channel 29 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH29_NOT_WAITING_VALUE 0 #define SI32_DMACTRL_A_CHSTATUS_CH29_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH29_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH29_SHIFT) // DMA Channel 29 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH29_WAITING_VALUE 1 #define SI32_DMACTRL_A_CHSTATUS_CH29_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH29_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH29_SHIFT) #define SI32_DMACTRL_A_CHSTATUS_CH30_MASK 0x40000000 #define SI32_DMACTRL_A_CHSTATUS_CH30_SHIFT 30 // DMA Channel 30 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH30_NOT_WAITING_VALUE 0 #define SI32_DMACTRL_A_CHSTATUS_CH30_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH30_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH30_SHIFT) // DMA Channel 30 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH30_WAITING_VALUE 1 #define SI32_DMACTRL_A_CHSTATUS_CH30_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH30_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH30_SHIFT) #define SI32_DMACTRL_A_CHSTATUS_CH31_MASK 0x80000000 #define SI32_DMACTRL_A_CHSTATUS_CH31_SHIFT 31 // DMA Channel 31 is not waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH31_NOT_WAITING_VALUE 0U #define SI32_DMACTRL_A_CHSTATUS_CH31_NOT_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH31_NOT_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH31_SHIFT) // DMA Channel 31 is waiting for a data request. #define SI32_DMACTRL_A_CHSTATUS_CH31_WAITING_VALUE 1U #define SI32_DMACTRL_A_CHSTATUS_CH31_WAITING_U32 \ (SI32_DMACTRL_A_CHSTATUS_CH31_WAITING_VALUE << SI32_DMACTRL_A_CHSTATUS_CH31_SHIFT) struct SI32_DMACTRL_A_CHSWRCN_Struct { union { struct { // Channel 0 Software Request volatile uint32_t CH0: 1; // Channel 1 Software Request volatile uint32_t CH1: 1; // Channel 2 Software Request volatile uint32_t CH2: 1; // Channel 3 Software Request volatile uint32_t CH3: 1; // Channel 4 Software Request volatile uint32_t CH4: 1; // Channel 5 Software Request volatile uint32_t CH5: 1; // Channel 6 Software Request volatile uint32_t CH6: 1; // Channel 7 Software Request volatile uint32_t CH7: 1; // Channel 8 Software Request volatile uint32_t CH8: 1; // Channel 9 Software Request volatile uint32_t CH9: 1; // Channel 10 Software Request volatile uint32_t CH10: 1; // Channel 11 Software Request volatile uint32_t CH11: 1; // Channel 12 Software Request volatile uint32_t CH12: 1; // Channel 13 Software Request volatile uint32_t CH13: 1; // Channel 14 Software Request volatile uint32_t CH14: 1; // Channel 15 Software Request volatile uint32_t CH15: 1; // Channel 16 Software Request volatile uint32_t CH16: 1; // Channel 17 Software Request volatile uint32_t CH17: 1; // Channel 18 Software Request volatile uint32_t CH18: 1; // Channel 19 Software Request volatile uint32_t CH19: 1; // Channel 20 Software Request volatile uint32_t CH20: 1; // Channel 21 Software Request volatile uint32_t CH21: 1; // Channel 22 Software Request volatile uint32_t CH22: 1; // Channel 23 Software Request volatile uint32_t CH23: 1; // Channel 24 Software Request volatile uint32_t CH24: 1; // Channel 25 Software Request volatile uint32_t CH25: 1; // Channel 26 Software Request volatile uint32_t CH26: 1; // Channel 27 Software Request volatile uint32_t CH27: 1; // Channel 28 Software Request volatile uint32_t CH28: 1; // Channel 29 Software Request volatile uint32_t CH29: 1; // Channel 30 Software Request volatile uint32_t CH30: 1; // Channel 31 Software Request volatile uint32_t CH31: 1; }; volatile uint32_t U32; }; }; #define SI32_DMACTRL_A_CHSWRCN_CH0_MASK 0x00000001 #define SI32_DMACTRL_A_CHSWRCN_CH0_SHIFT 0 // DMA Channel 0 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH0_DO_NOT_GENERATE_SW_REQ_VALUE 0 #define SI32_DMACTRL_A_CHSWRCN_CH0_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH0_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH0_SHIFT) // DMA Channel 0 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH0_GENERATE_SW_REQ_VALUE 1 #define SI32_DMACTRL_A_CHSWRCN_CH0_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH0_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH0_SHIFT) #define SI32_DMACTRL_A_CHSWRCN_CH1_MASK 0x00000002 #define SI32_DMACTRL_A_CHSWRCN_CH1_SHIFT 1 // DMA Channel 1 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH1_DO_NOT_GENERATE_SW_REQ_VALUE 0 #define SI32_DMACTRL_A_CHSWRCN_CH1_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH1_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH1_SHIFT) // DMA Channel 1 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH1_GENERATE_SW_REQ_VALUE 1 #define SI32_DMACTRL_A_CHSWRCN_CH1_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH1_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH1_SHIFT) #define SI32_DMACTRL_A_CHSWRCN_CH2_MASK 0x00000004 #define SI32_DMACTRL_A_CHSWRCN_CH2_SHIFT 2 // DMA Channel 2 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH2_DO_NOT_GENERATE_SW_REQ_VALUE 0 #define SI32_DMACTRL_A_CHSWRCN_CH2_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH2_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH2_SHIFT) // DMA Channel 2 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH2_GENERATE_SW_REQ_VALUE 1 #define SI32_DMACTRL_A_CHSWRCN_CH2_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH2_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH2_SHIFT) #define SI32_DMACTRL_A_CHSWRCN_CH3_MASK 0x00000008 #define SI32_DMACTRL_A_CHSWRCN_CH3_SHIFT 3 // DMA Channel 3 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH3_DO_NOT_GENERATE_SW_REQ_VALUE 0 #define SI32_DMACTRL_A_CHSWRCN_CH3_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH3_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH3_SHIFT) // DMA Channel 3 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH3_GENERATE_SW_REQ_VALUE 1 #define SI32_DMACTRL_A_CHSWRCN_CH3_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH3_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH3_SHIFT) #define SI32_DMACTRL_A_CHSWRCN_CH4_MASK 0x00000010 #define SI32_DMACTRL_A_CHSWRCN_CH4_SHIFT 4 // DMA Channel 4 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH4_DO_NOT_GENERATE_SW_REQ_VALUE 0 #define SI32_DMACTRL_A_CHSWRCN_CH4_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH4_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH4_SHIFT) // DMA Channel 4 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH4_GENERATE_SW_REQ_VALUE 1 #define SI32_DMACTRL_A_CHSWRCN_CH4_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH4_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH4_SHIFT) #define SI32_DMACTRL_A_CHSWRCN_CH5_MASK 0x00000020 #define SI32_DMACTRL_A_CHSWRCN_CH5_SHIFT 5 // DMA Channel 5 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH5_DO_NOT_GENERATE_SW_REQ_VALUE 0 #define SI32_DMACTRL_A_CHSWRCN_CH5_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH5_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH5_SHIFT) // DMA Channel 5 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH5_GENERATE_SW_REQ_VALUE 1 #define SI32_DMACTRL_A_CHSWRCN_CH5_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH5_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH5_SHIFT) #define SI32_DMACTRL_A_CHSWRCN_CH6_MASK 0x00000040 #define SI32_DMACTRL_A_CHSWRCN_CH6_SHIFT 6 // DMA Channel 6 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH6_DO_NOT_GENERATE_SW_REQ_VALUE 0 #define SI32_DMACTRL_A_CHSWRCN_CH6_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH6_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH6_SHIFT) // DMA Channel 6 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH6_GENERATE_SW_REQ_VALUE 1 #define SI32_DMACTRL_A_CHSWRCN_CH6_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH6_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH6_SHIFT) #define SI32_DMACTRL_A_CHSWRCN_CH7_MASK 0x00000080 #define SI32_DMACTRL_A_CHSWRCN_CH7_SHIFT 7 // DMA Channel 7 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH7_DO_NOT_GENERATE_SW_REQ_VALUE 0 #define SI32_DMACTRL_A_CHSWRCN_CH7_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH7_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH7_SHIFT) // DMA Channel 7 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH7_GENERATE_SW_REQ_VALUE 1 #define SI32_DMACTRL_A_CHSWRCN_CH7_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH7_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH7_SHIFT) #define SI32_DMACTRL_A_CHSWRCN_CH8_MASK 0x00000100 #define SI32_DMACTRL_A_CHSWRCN_CH8_SHIFT 8 // DMA Channel 8 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH8_DO_NOT_GENERATE_SW_REQ_VALUE 0 #define SI32_DMACTRL_A_CHSWRCN_CH8_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH8_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH8_SHIFT) // DMA Channel 8 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH8_GENERATE_SW_REQ_VALUE 1 #define SI32_DMACTRL_A_CHSWRCN_CH8_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH8_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH8_SHIFT) #define SI32_DMACTRL_A_CHSWRCN_CH9_MASK 0x00000200 #define SI32_DMACTRL_A_CHSWRCN_CH9_SHIFT 9 // DMA Channel 9 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH9_DO_NOT_GENERATE_SW_REQ_VALUE 0 #define SI32_DMACTRL_A_CHSWRCN_CH9_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH9_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH9_SHIFT) // DMA Channel 9 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH9_GENERATE_SW_REQ_VALUE 1 #define SI32_DMACTRL_A_CHSWRCN_CH9_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH9_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH9_SHIFT) #define SI32_DMACTRL_A_CHSWRCN_CH10_MASK 0x00000400 #define SI32_DMACTRL_A_CHSWRCN_CH10_SHIFT 10 // DMA Channel 10 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH10_DO_NOT_GENERATE_SW_REQ_VALUE 0 #define SI32_DMACTRL_A_CHSWRCN_CH10_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH10_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH10_SHIFT) // DMA Channel 10 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH10_GENERATE_SW_REQ_VALUE 1 #define SI32_DMACTRL_A_CHSWRCN_CH10_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH10_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH10_SHIFT) #define SI32_DMACTRL_A_CHSWRCN_CH11_MASK 0x00000800 #define SI32_DMACTRL_A_CHSWRCN_CH11_SHIFT 11 // DMA Channel 11 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH11_DO_NOT_GENERATE_SW_REQ_VALUE 0 #define SI32_DMACTRL_A_CHSWRCN_CH11_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH11_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH11_SHIFT) // DMA Channel 11 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH11_GENERATE_SW_REQ_VALUE 1 #define SI32_DMACTRL_A_CHSWRCN_CH11_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH11_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH11_SHIFT) #define SI32_DMACTRL_A_CHSWRCN_CH12_MASK 0x00001000 #define SI32_DMACTRL_A_CHSWRCN_CH12_SHIFT 12 // DMA Channel 12 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH12_DO_NOT_GENERATE_SW_REQ_VALUE 0 #define SI32_DMACTRL_A_CHSWRCN_CH12_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH12_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH12_SHIFT) // DMA Channel 12 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH12_GENERATE_SW_REQ_VALUE 1 #define SI32_DMACTRL_A_CHSWRCN_CH12_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH12_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH12_SHIFT) #define SI32_DMACTRL_A_CHSWRCN_CH13_MASK 0x00002000 #define SI32_DMACTRL_A_CHSWRCN_CH13_SHIFT 13 // DMA Channel 13 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH13_DO_NOT_GENERATE_SW_REQ_VALUE 0 #define SI32_DMACTRL_A_CHSWRCN_CH13_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH13_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH13_SHIFT) // DMA Channel 13 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH13_GENERATE_SW_REQ_VALUE 1 #define SI32_DMACTRL_A_CHSWRCN_CH13_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH13_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH13_SHIFT) #define SI32_DMACTRL_A_CHSWRCN_CH14_MASK 0x00004000 #define SI32_DMACTRL_A_CHSWRCN_CH14_SHIFT 14 // DMA Channel 14 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH14_DO_NOT_GENERATE_SW_REQ_VALUE 0 #define SI32_DMACTRL_A_CHSWRCN_CH14_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH14_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH14_SHIFT) // DMA Channel 14 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH14_GENERATE_SW_REQ_VALUE 1 #define SI32_DMACTRL_A_CHSWRCN_CH14_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH14_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH14_SHIFT) #define SI32_DMACTRL_A_CHSWRCN_CH15_MASK 0x00008000 #define SI32_DMACTRL_A_CHSWRCN_CH15_SHIFT 15 // DMA Channel 15 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH15_DO_NOT_GENERATE_SW_REQ_VALUE 0 #define SI32_DMACTRL_A_CHSWRCN_CH15_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH15_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH15_SHIFT) // DMA Channel 15 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH15_GENERATE_SW_REQ_VALUE 1 #define SI32_DMACTRL_A_CHSWRCN_CH15_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH15_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH15_SHIFT) #define SI32_DMACTRL_A_CHSWRCN_CH16_MASK 0x00010000 #define SI32_DMACTRL_A_CHSWRCN_CH16_SHIFT 16 // DMA Channel 16 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH16_DO_NOT_GENERATE_SW_REQ_VALUE 0 #define SI32_DMACTRL_A_CHSWRCN_CH16_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH16_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH16_SHIFT) // DMA Channel 16 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH16_GENERATE_SW_REQ_VALUE 1 #define SI32_DMACTRL_A_CHSWRCN_CH16_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH16_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH16_SHIFT) #define SI32_DMACTRL_A_CHSWRCN_CH17_MASK 0x00020000 #define SI32_DMACTRL_A_CHSWRCN_CH17_SHIFT 17 // DMA Channel 17 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH17_DO_NOT_GENERATE_SW_REQ_VALUE 0 #define SI32_DMACTRL_A_CHSWRCN_CH17_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH17_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH17_SHIFT) // DMA Channel 17 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH17_GENERATE_SW_REQ_VALUE 1 #define SI32_DMACTRL_A_CHSWRCN_CH17_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH17_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH17_SHIFT) #define SI32_DMACTRL_A_CHSWRCN_CH18_MASK 0x00040000 #define SI32_DMACTRL_A_CHSWRCN_CH18_SHIFT 18 // DMA Channel 18 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH18_DO_NOT_GENERATE_SW_REQ_VALUE 0 #define SI32_DMACTRL_A_CHSWRCN_CH18_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH18_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH18_SHIFT) // DMA Channel 18 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH18_GENERATE_SW_REQ_VALUE 1 #define SI32_DMACTRL_A_CHSWRCN_CH18_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH18_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH18_SHIFT) #define SI32_DMACTRL_A_CHSWRCN_CH19_MASK 0x00080000 #define SI32_DMACTRL_A_CHSWRCN_CH19_SHIFT 19 // DMA Channel 19 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH19_DO_NOT_GENERATE_SW_REQ_VALUE 0 #define SI32_DMACTRL_A_CHSWRCN_CH19_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH19_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH19_SHIFT) // DMA Channel 19 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH19_GENERATE_SW_REQ_VALUE 1 #define SI32_DMACTRL_A_CHSWRCN_CH19_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH19_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH19_SHIFT) #define SI32_DMACTRL_A_CHSWRCN_CH20_MASK 0x00100000 #define SI32_DMACTRL_A_CHSWRCN_CH20_SHIFT 20 // DMA Channel 20 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH20_DO_NOT_GENERATE_SW_REQ_VALUE 0 #define SI32_DMACTRL_A_CHSWRCN_CH20_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH20_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH20_SHIFT) // DMA Channel 20 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH20_GENERATE_SW_REQ_VALUE 1 #define SI32_DMACTRL_A_CHSWRCN_CH20_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH20_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH20_SHIFT) #define SI32_DMACTRL_A_CHSWRCN_CH21_MASK 0x00200000 #define SI32_DMACTRL_A_CHSWRCN_CH21_SHIFT 21 // DMA Channel 21 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH21_DO_NOT_GENERATE_SW_REQ_VALUE 0 #define SI32_DMACTRL_A_CHSWRCN_CH21_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH21_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH21_SHIFT) // DMA Channel 21 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH21_GENERATE_SW_REQ_VALUE 1 #define SI32_DMACTRL_A_CHSWRCN_CH21_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH21_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH21_SHIFT) #define SI32_DMACTRL_A_CHSWRCN_CH22_MASK 0x00400000 #define SI32_DMACTRL_A_CHSWRCN_CH22_SHIFT 22 // DMA Channel 22 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH22_DO_NOT_GENERATE_SW_REQ_VALUE 0 #define SI32_DMACTRL_A_CHSWRCN_CH22_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH22_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH22_SHIFT) // DMA Channel 22 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH22_GENERATE_SW_REQ_VALUE 1 #define SI32_DMACTRL_A_CHSWRCN_CH22_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH22_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH22_SHIFT) #define SI32_DMACTRL_A_CHSWRCN_CH23_MASK 0x00800000 #define SI32_DMACTRL_A_CHSWRCN_CH23_SHIFT 23 // DMA Channel 23 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH23_DO_NOT_GENERATE_SW_REQ_VALUE 0 #define SI32_DMACTRL_A_CHSWRCN_CH23_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH23_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH23_SHIFT) // DMA Channel 23 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH23_GENERATE_SW_REQ_VALUE 1 #define SI32_DMACTRL_A_CHSWRCN_CH23_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH23_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH23_SHIFT) #define SI32_DMACTRL_A_CHSWRCN_CH24_MASK 0x01000000 #define SI32_DMACTRL_A_CHSWRCN_CH24_SHIFT 24 // DMA Channel 24 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH24_DO_NOT_GENERATE_SW_REQ_VALUE 0 #define SI32_DMACTRL_A_CHSWRCN_CH24_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH24_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH24_SHIFT) // DMA Channel 24 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH24_GENERATE_SW_REQ_VALUE 1 #define SI32_DMACTRL_A_CHSWRCN_CH24_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH24_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH24_SHIFT) #define SI32_DMACTRL_A_CHSWRCN_CH25_MASK 0x02000000 #define SI32_DMACTRL_A_CHSWRCN_CH25_SHIFT 25 // DMA Channel 25 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH25_DO_NOT_GENERATE_SW_REQ_VALUE 0 #define SI32_DMACTRL_A_CHSWRCN_CH25_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH25_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH25_SHIFT) // DMA Channel 25 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH25_GENERATE_SW_REQ_VALUE 1 #define SI32_DMACTRL_A_CHSWRCN_CH25_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH25_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH25_SHIFT) #define SI32_DMACTRL_A_CHSWRCN_CH26_MASK 0x04000000 #define SI32_DMACTRL_A_CHSWRCN_CH26_SHIFT 26 // DMA Channel 26 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH26_DO_NOT_GENERATE_SW_REQ_VALUE 0 #define SI32_DMACTRL_A_CHSWRCN_CH26_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH26_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH26_SHIFT) // DMA Channel 26 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH26_GENERATE_SW_REQ_VALUE 1 #define SI32_DMACTRL_A_CHSWRCN_CH26_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH26_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH26_SHIFT) #define SI32_DMACTRL_A_CHSWRCN_CH27_MASK 0x08000000 #define SI32_DMACTRL_A_CHSWRCN_CH27_SHIFT 27 // DMA Channel 27 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH27_DO_NOT_GENERATE_SW_REQ_VALUE 0 #define SI32_DMACTRL_A_CHSWRCN_CH27_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH27_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH27_SHIFT) // DMA Channel 27 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH27_GENERATE_SW_REQ_VALUE 1 #define SI32_DMACTRL_A_CHSWRCN_CH27_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH27_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH27_SHIFT) #define SI32_DMACTRL_A_CHSWRCN_CH28_MASK 0x10000000 #define SI32_DMACTRL_A_CHSWRCN_CH28_SHIFT 28 // DMA Channel 28 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH28_DO_NOT_GENERATE_SW_REQ_VALUE 0 #define SI32_DMACTRL_A_CHSWRCN_CH28_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH28_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH28_SHIFT) // DMA Channel 28 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH28_GENERATE_SW_REQ_VALUE 1 #define SI32_DMACTRL_A_CHSWRCN_CH28_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH28_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH28_SHIFT) #define SI32_DMACTRL_A_CHSWRCN_CH29_MASK 0x20000000 #define SI32_DMACTRL_A_CHSWRCN_CH29_SHIFT 29 // DMA Channel 29 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH29_DO_NOT_GENERATE_SW_REQ_VALUE 0 #define SI32_DMACTRL_A_CHSWRCN_CH29_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH29_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH29_SHIFT) // DMA Channel 29 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH29_GENERATE_SW_REQ_VALUE 1 #define SI32_DMACTRL_A_CHSWRCN_CH29_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH29_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH29_SHIFT) #define SI32_DMACTRL_A_CHSWRCN_CH30_MASK 0x40000000 #define SI32_DMACTRL_A_CHSWRCN_CH30_SHIFT 30 // DMA Channel 30 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH30_DO_NOT_GENERATE_SW_REQ_VALUE 0 #define SI32_DMACTRL_A_CHSWRCN_CH30_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH30_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH30_SHIFT) // DMA Channel 30 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH30_GENERATE_SW_REQ_VALUE 1 #define SI32_DMACTRL_A_CHSWRCN_CH30_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH30_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH30_SHIFT) #define SI32_DMACTRL_A_CHSWRCN_CH31_MASK 0x80000000 #define SI32_DMACTRL_A_CHSWRCN_CH31_SHIFT 31 // DMA Channel 31 does not generate a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH31_DO_NOT_GENERATE_SW_REQ_VALUE 0U #define SI32_DMACTRL_A_CHSWRCN_CH31_DO_NOT_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH31_DO_NOT_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH31_SHIFT) // DMA Channel 31 generates a software data request. #define SI32_DMACTRL_A_CHSWRCN_CH31_GENERATE_SW_REQ_VALUE 1U #define SI32_DMACTRL_A_CHSWRCN_CH31_GENERATE_SW_REQ_U32 \ (SI32_DMACTRL_A_CHSWRCN_CH31_GENERATE_SW_REQ_VALUE << SI32_DMACTRL_A_CHSWRCN_CH31_SHIFT) struct SI32_DMACTRL_A_CHREQMSET_Struct { union { struct { // Channel 0 Request Mask Enable volatile uint32_t CH0: 1; // Channel 1 Request Mask Enable volatile uint32_t CH1: 1; // Channel 2 Request Mask Enable volatile uint32_t CH2: 1; // Channel 3 Request Mask Enable volatile uint32_t CH3: 1; // Channel 4 Request Mask Enable volatile uint32_t CH4: 1; // Channel 5 Request Mask Enable volatile uint32_t CH5: 1; // Channel 6 Request Mask Enable volatile uint32_t CH6: 1; // Channel 7 Request Mask Enable volatile uint32_t CH7: 1; // Channel 8 Request Mask Enable volatile uint32_t CH8: 1; // Channel 9 Request Mask Enable volatile uint32_t CH9: 1; // Channel 10 Request Mask Enable volatile uint32_t CH10: 1; // Channel 11 Request Mask Enable volatile uint32_t CH11: 1; // Channel 12 Request Mask Enable volatile uint32_t CH12: 1; // Channel 13 Request Mask Enable volatile uint32_t CH13: 1; // Channel 14 Request Mask Enable volatile uint32_t CH14: 1; // Channel 15 Request Mask Enable volatile uint32_t CH15: 1; // Channel 16 Request Mask Enable volatile uint32_t CH16: 1; // Channel 17 Request Mask Enable volatile uint32_t CH17: 1; // Channel 18 Request Mask Enable volatile uint32_t CH18: 1; // Channel 19 Request Mask Enable volatile uint32_t CH19: 1; // Channel 20 Request Mask Enable volatile uint32_t CH20: 1; // Channel 21 Request Mask Enable volatile uint32_t CH21: 1; // Channel 22 Request Mask Enable volatile uint32_t CH22: 1; // Channel 23 Request Mask Enable volatile uint32_t CH23: 1; // Channel 24 Request Mask Enable volatile uint32_t CH24: 1; // Channel 25 Request Mask Enable volatile uint32_t CH25: 1; // Channel 26 Request Mask Enable volatile uint32_t CH26: 1; // Channel 27 Request Mask Enable volatile uint32_t CH27: 1; // Channel 28 Request Mask Enable volatile uint32_t CH28: 1; // Channel 29 Request Mask Enable volatile uint32_t CH29: 1; // Channel 30 Request Mask Enable volatile uint32_t CH30: 1; // Channel 31 Request Mask Enable volatile uint32_t CH31: 1; }; volatile uint32_t U32; }; }; #define SI32_DMACTRL_A_CHREQMSET_CH0_MASK 0x00000001 #define SI32_DMACTRL_A_CHREQMSET_CH0_SHIFT 0 // Read: 0: DMA Channel 0 peripheral data requests enabled. 1: DMA Channel 0 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 0 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH0_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMSET_CH0_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH0_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH0_SHIFT) #define SI32_DMACTRL_A_CHREQMSET_CH1_MASK 0x00000002 #define SI32_DMACTRL_A_CHREQMSET_CH1_SHIFT 1 // Read: 0: DMA Channel 1 peripheral data requests enabled. 1: DMA Channel 1 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 1 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH1_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMSET_CH1_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH1_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH1_SHIFT) #define SI32_DMACTRL_A_CHREQMSET_CH2_MASK 0x00000004 #define SI32_DMACTRL_A_CHREQMSET_CH2_SHIFT 2 // Read: 0: DMA Channel 2 peripheral data requests enabled. 1: DMA Channel 2 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 2 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH2_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMSET_CH2_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH2_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH2_SHIFT) #define SI32_DMACTRL_A_CHREQMSET_CH3_MASK 0x00000008 #define SI32_DMACTRL_A_CHREQMSET_CH3_SHIFT 3 // Read: 0: DMA Channel 3 peripheral data requests enabled. 1: DMA Channel 3 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 3 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH3_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMSET_CH3_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH3_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH3_SHIFT) #define SI32_DMACTRL_A_CHREQMSET_CH4_MASK 0x00000010 #define SI32_DMACTRL_A_CHREQMSET_CH4_SHIFT 4 // Read: 0: DMA Channel 4 peripheral data requests enabled. 1: DMA Channel 4 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 4 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH4_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMSET_CH4_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH4_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH4_SHIFT) #define SI32_DMACTRL_A_CHREQMSET_CH5_MASK 0x00000020 #define SI32_DMACTRL_A_CHREQMSET_CH5_SHIFT 5 // Read: 0: DMA Channel 5 peripheral data requests enabled. 1: DMA Channel 5 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 5 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH5_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMSET_CH5_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH5_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH5_SHIFT) #define SI32_DMACTRL_A_CHREQMSET_CH6_MASK 0x00000040 #define SI32_DMACTRL_A_CHREQMSET_CH6_SHIFT 6 // Read: 0: DMA Channel 6 peripheral data requests enabled. 1: DMA Channel 6 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 6 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH6_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMSET_CH6_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH6_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH6_SHIFT) #define SI32_DMACTRL_A_CHREQMSET_CH7_MASK 0x00000080 #define SI32_DMACTRL_A_CHREQMSET_CH7_SHIFT 7 // Read: 0: DMA Channel 7 peripheral data requests enabled. 1: DMA Channel 7 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 7 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH7_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMSET_CH7_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH7_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH7_SHIFT) #define SI32_DMACTRL_A_CHREQMSET_CH8_MASK 0x00000100 #define SI32_DMACTRL_A_CHREQMSET_CH8_SHIFT 8 // Read: 0: DMA Channel 8 peripheral data requests enabled. 1: DMA Channel 8 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 8 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH8_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMSET_CH8_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH8_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH8_SHIFT) #define SI32_DMACTRL_A_CHREQMSET_CH9_MASK 0x00000200 #define SI32_DMACTRL_A_CHREQMSET_CH9_SHIFT 9 // Read: 0: DMA Channel 9 peripheral data requests enabled. 1: DMA Channel 9 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 9 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH9_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMSET_CH9_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH9_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH9_SHIFT) #define SI32_DMACTRL_A_CHREQMSET_CH10_MASK 0x00000400 #define SI32_DMACTRL_A_CHREQMSET_CH10_SHIFT 10 // Read: 0: DMA Channel 10 peripheral data requests enabled. 1: DMA Channel 10 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 10 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH10_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMSET_CH10_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH10_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH10_SHIFT) #define SI32_DMACTRL_A_CHREQMSET_CH11_MASK 0x00000800 #define SI32_DMACTRL_A_CHREQMSET_CH11_SHIFT 11 // Read: 0: DMA Channel 11 peripheral data requests enabled. 1: DMA Channel 11 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 11 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH11_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMSET_CH11_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH11_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH11_SHIFT) #define SI32_DMACTRL_A_CHREQMSET_CH12_MASK 0x00001000 #define SI32_DMACTRL_A_CHREQMSET_CH12_SHIFT 12 // Read: 0: DMA Channel 12 peripheral data requests enabled. 1: DMA Channel 12 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 12 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH12_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMSET_CH12_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH12_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH12_SHIFT) #define SI32_DMACTRL_A_CHREQMSET_CH13_MASK 0x00002000 #define SI32_DMACTRL_A_CHREQMSET_CH13_SHIFT 13 // Read: 0: DMA Channel 13 peripheral data requests enabled. 1: DMA Channel 13 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 13 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH13_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMSET_CH13_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH13_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH13_SHIFT) #define SI32_DMACTRL_A_CHREQMSET_CH14_MASK 0x00004000 #define SI32_DMACTRL_A_CHREQMSET_CH14_SHIFT 14 // Read: 0: DMA Channel 14 peripheral data requests enabled. 1: DMA Channel 14 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 14 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH14_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMSET_CH14_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH14_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH14_SHIFT) #define SI32_DMACTRL_A_CHREQMSET_CH15_MASK 0x00008000 #define SI32_DMACTRL_A_CHREQMSET_CH15_SHIFT 15 // Read: 0: DMA Channel 15 peripheral data requests enabled. 1: DMA Channel 15 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 15 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH15_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMSET_CH15_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH15_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH15_SHIFT) #define SI32_DMACTRL_A_CHREQMSET_CH16_MASK 0x00010000 #define SI32_DMACTRL_A_CHREQMSET_CH16_SHIFT 16 // Read: 0: DMA Channel 16 peripheral data requests enabled. 1: DMA Channel 16 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 16 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH16_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMSET_CH16_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH16_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH16_SHIFT) #define SI32_DMACTRL_A_CHREQMSET_CH17_MASK 0x00020000 #define SI32_DMACTRL_A_CHREQMSET_CH17_SHIFT 17 // Read: 0: DMA Channel 17 peripheral data requests enabled. 1: DMA Channel 17 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 17 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH17_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMSET_CH17_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH17_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH17_SHIFT) #define SI32_DMACTRL_A_CHREQMSET_CH18_MASK 0x00040000 #define SI32_DMACTRL_A_CHREQMSET_CH18_SHIFT 18 // Read: 0: DMA Channel 18 peripheral data requests enabled. 1: DMA Channel 18 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 18 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH18_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMSET_CH18_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH18_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH18_SHIFT) #define SI32_DMACTRL_A_CHREQMSET_CH19_MASK 0x00080000 #define SI32_DMACTRL_A_CHREQMSET_CH19_SHIFT 19 // Read: 0: DMA Channel 19 peripheral data requests enabled. 1: DMA Channel 19 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 19 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH19_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMSET_CH19_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH19_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH19_SHIFT) #define SI32_DMACTRL_A_CHREQMSET_CH20_MASK 0x00100000 #define SI32_DMACTRL_A_CHREQMSET_CH20_SHIFT 20 // Read: 0: DMA Channel 20 peripheral data requests enabled. 1: DMA Channel 20 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 20 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH20_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMSET_CH20_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH20_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH20_SHIFT) #define SI32_DMACTRL_A_CHREQMSET_CH21_MASK 0x00200000 #define SI32_DMACTRL_A_CHREQMSET_CH21_SHIFT 21 // Read: 0: DMA Channel 21 peripheral data requests enabled. 1: DMA Channel 21 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 21 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH21_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMSET_CH21_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH21_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH21_SHIFT) #define SI32_DMACTRL_A_CHREQMSET_CH22_MASK 0x00400000 #define SI32_DMACTRL_A_CHREQMSET_CH22_SHIFT 22 // Read: 0: DMA Channel 22 peripheral data requests enabled. 1: DMA Channel 22 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 22 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH22_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMSET_CH22_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH22_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH22_SHIFT) #define SI32_DMACTRL_A_CHREQMSET_CH23_MASK 0x00800000 #define SI32_DMACTRL_A_CHREQMSET_CH23_SHIFT 23 // Read: 0: DMA Channel 23 peripheral data requests enabled. 1: DMA Channel 23 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 23 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH23_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMSET_CH23_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH23_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH23_SHIFT) #define SI32_DMACTRL_A_CHREQMSET_CH24_MASK 0x01000000 #define SI32_DMACTRL_A_CHREQMSET_CH24_SHIFT 24 // Read: 0: DMA Channel 24 peripheral data requests enabled. 1: DMA Channel 24 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 24 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH24_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMSET_CH24_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH24_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH24_SHIFT) #define SI32_DMACTRL_A_CHREQMSET_CH25_MASK 0x02000000 #define SI32_DMACTRL_A_CHREQMSET_CH25_SHIFT 25 // Read: 0: DMA Channel 25 peripheral data requests enabled. 1: DMA Channel 25 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 25 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH25_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMSET_CH25_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH25_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH25_SHIFT) #define SI32_DMACTRL_A_CHREQMSET_CH26_MASK 0x04000000 #define SI32_DMACTRL_A_CHREQMSET_CH26_SHIFT 26 // Read: 0: DMA Channel 26 peripheral data requests enabled. 1: DMA Channel 26 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 26 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH26_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMSET_CH26_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH26_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH26_SHIFT) #define SI32_DMACTRL_A_CHREQMSET_CH27_MASK 0x08000000 #define SI32_DMACTRL_A_CHREQMSET_CH27_SHIFT 27 // Read: 0: DMA Channel 27 peripheral data requests enabled. 1: DMA Channel 27 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 27 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH27_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMSET_CH27_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH27_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH27_SHIFT) #define SI32_DMACTRL_A_CHREQMSET_CH28_MASK 0x10000000 #define SI32_DMACTRL_A_CHREQMSET_CH28_SHIFT 28 // Read: 0: DMA Channel 28 peripheral data requests enabled. 1: DMA Channel 28 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 28 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH28_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMSET_CH28_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH28_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH28_SHIFT) #define SI32_DMACTRL_A_CHREQMSET_CH29_MASK 0x20000000 #define SI32_DMACTRL_A_CHREQMSET_CH29_SHIFT 29 // Read: 0: DMA Channel 29 peripheral data requests enabled. 1: DMA Channel 29 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 29 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH29_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMSET_CH29_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH29_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH29_SHIFT) #define SI32_DMACTRL_A_CHREQMSET_CH30_MASK 0x40000000 #define SI32_DMACTRL_A_CHREQMSET_CH30_SHIFT 30 // Read: 0: DMA Channel 30 peripheral data requests enabled. 1: DMA Channel 30 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 30 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH30_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMSET_CH30_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH30_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH30_SHIFT) #define SI32_DMACTRL_A_CHREQMSET_CH31_MASK 0x80000000 #define SI32_DMACTRL_A_CHREQMSET_CH31_SHIFT 31 // Read: 0: DMA Channel 31 peripheral data requests enabled. 1: DMA Channel 31 // peripheral data requests disabled. Write: 0: No effect (use CHREQMCLR to clear). // 1: Disable DMA Channel 31 peripheral data requests. #define SI32_DMACTRL_A_CHREQMSET_CH31_ENABLED_VALUE 1U #define SI32_DMACTRL_A_CHREQMSET_CH31_ENABLED_U32 \ (SI32_DMACTRL_A_CHREQMSET_CH31_ENABLED_VALUE << SI32_DMACTRL_A_CHREQMSET_CH31_SHIFT) struct SI32_DMACTRL_A_CHREQMCLR_Struct { union { struct { // Channel 0 Request Mask Disable volatile uint32_t CH0: 1; // Channel 1 Request Mask Disable volatile uint32_t CH1: 1; // Channel 2 Request Mask Disable volatile uint32_t CH2: 1; // Channel 3 Request Mask Disable volatile uint32_t CH3: 1; // Channel 4 Request Mask Disable volatile uint32_t CH4: 1; // Channel 5 Request Mask Disable volatile uint32_t CH5: 1; // Channel 6 Request Mask Disable volatile uint32_t CH6: 1; // Channel 7 Request Mask Disable volatile uint32_t CH7: 1; // Channel 8 Request Mask Disable volatile uint32_t CH8: 1; // Channel 9 Request Mask Disable volatile uint32_t CH9: 1; // Channel 10 Request Mask Disable volatile uint32_t CH10: 1; // Channel 11 Request Mask Disable volatile uint32_t CH11: 1; // Channel 12 Request Mask Disable volatile uint32_t CH12: 1; // Channel 13 Request Mask Disable volatile uint32_t CH13: 1; // Channel 14 Request Mask Disable volatile uint32_t CH14: 1; // Channel 15 Request Mask Disable volatile uint32_t CH15: 1; // Channel 16 Request Mask Disable volatile uint32_t CH16: 1; // Channel 17 Request Mask Disable volatile uint32_t CH17: 1; // Channel 18 Request Mask Disable volatile uint32_t CH18: 1; // Channel 19 Request Mask Disable volatile uint32_t CH19: 1; // Channel 20 Request Mask Disable volatile uint32_t CH20: 1; // Channel 21 Request Mask Disable volatile uint32_t CH21: 1; // Channel 22 Request Mask Disable volatile uint32_t CH22: 1; // Channel 23 Request Mask Disable volatile uint32_t CH23: 1; // Channel 24 Request Mask Disable volatile uint32_t CH24: 1; // Channel 25 Request Mask Disable volatile uint32_t CH25: 1; // Channel 26 Request Mask Disable volatile uint32_t CH26: 1; // Channel 27 Request Mask Disable volatile uint32_t CH27: 1; // Channel 28 Request Mask Disable volatile uint32_t CH28: 1; // Channel 29 Request Mask Disable volatile uint32_t CH29: 1; // Channel 30 Request Mask Disable volatile uint32_t CH30: 1; // Channel 31 Request Mask Disable volatile uint32_t CH31: 1; }; volatile uint32_t U32; }; }; #define SI32_DMACTRL_A_CHREQMCLR_CH0_MASK 0x00000001 #define SI32_DMACTRL_A_CHREQMCLR_CH0_SHIFT 0 // Enable DMA Channel 0 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH0_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMCLR_CH0_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH0_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH0_SHIFT) #define SI32_DMACTRL_A_CHREQMCLR_CH1_MASK 0x00000002 #define SI32_DMACTRL_A_CHREQMCLR_CH1_SHIFT 1 // Enable DMA Channel 1 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH1_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMCLR_CH1_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH1_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH1_SHIFT) #define SI32_DMACTRL_A_CHREQMCLR_CH2_MASK 0x00000004 #define SI32_DMACTRL_A_CHREQMCLR_CH2_SHIFT 2 // Enable DMA Channel 2 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH2_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMCLR_CH2_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH2_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH2_SHIFT) #define SI32_DMACTRL_A_CHREQMCLR_CH3_MASK 0x00000008 #define SI32_DMACTRL_A_CHREQMCLR_CH3_SHIFT 3 // Enable DMA Channel 3 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH3_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMCLR_CH3_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH3_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH3_SHIFT) #define SI32_DMACTRL_A_CHREQMCLR_CH4_MASK 0x00000010 #define SI32_DMACTRL_A_CHREQMCLR_CH4_SHIFT 4 // Enable DMA Channel 4 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH4_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMCLR_CH4_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH4_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH4_SHIFT) #define SI32_DMACTRL_A_CHREQMCLR_CH5_MASK 0x00000020 #define SI32_DMACTRL_A_CHREQMCLR_CH5_SHIFT 5 // Enable DMA Channel 5 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH5_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMCLR_CH5_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH5_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH5_SHIFT) #define SI32_DMACTRL_A_CHREQMCLR_CH6_MASK 0x00000040 #define SI32_DMACTRL_A_CHREQMCLR_CH6_SHIFT 6 // Enable DMA Channel 6 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH6_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMCLR_CH6_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH6_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH6_SHIFT) #define SI32_DMACTRL_A_CHREQMCLR_CH7_MASK 0x00000080 #define SI32_DMACTRL_A_CHREQMCLR_CH7_SHIFT 7 // Enable DMA Channel 7 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH7_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMCLR_CH7_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH7_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH7_SHIFT) #define SI32_DMACTRL_A_CHREQMCLR_CH8_MASK 0x00000100 #define SI32_DMACTRL_A_CHREQMCLR_CH8_SHIFT 8 // Enable DMA Channel 8 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH8_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMCLR_CH8_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH8_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH8_SHIFT) #define SI32_DMACTRL_A_CHREQMCLR_CH9_MASK 0x00000200 #define SI32_DMACTRL_A_CHREQMCLR_CH9_SHIFT 9 // Enable DMA Channel 9 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH9_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMCLR_CH9_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH9_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH9_SHIFT) #define SI32_DMACTRL_A_CHREQMCLR_CH10_MASK 0x00000400 #define SI32_DMACTRL_A_CHREQMCLR_CH10_SHIFT 10 // Enable DMA Channel 10 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH10_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMCLR_CH10_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH10_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH10_SHIFT) #define SI32_DMACTRL_A_CHREQMCLR_CH11_MASK 0x00000800 #define SI32_DMACTRL_A_CHREQMCLR_CH11_SHIFT 11 // Enable DMA Channel 11 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH11_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMCLR_CH11_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH11_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH11_SHIFT) #define SI32_DMACTRL_A_CHREQMCLR_CH12_MASK 0x00001000 #define SI32_DMACTRL_A_CHREQMCLR_CH12_SHIFT 12 // Enable DMA Channel 12 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH12_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMCLR_CH12_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH12_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH12_SHIFT) #define SI32_DMACTRL_A_CHREQMCLR_CH13_MASK 0x00002000 #define SI32_DMACTRL_A_CHREQMCLR_CH13_SHIFT 13 // Enable DMA Channel 13 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH13_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMCLR_CH13_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH13_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH13_SHIFT) #define SI32_DMACTRL_A_CHREQMCLR_CH14_MASK 0x00004000 #define SI32_DMACTRL_A_CHREQMCLR_CH14_SHIFT 14 // Enable DMA Channel 14 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH14_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMCLR_CH14_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH14_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH14_SHIFT) #define SI32_DMACTRL_A_CHREQMCLR_CH15_MASK 0x00008000 #define SI32_DMACTRL_A_CHREQMCLR_CH15_SHIFT 15 // Enable DMA Channel 15 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH15_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMCLR_CH15_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH15_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH15_SHIFT) #define SI32_DMACTRL_A_CHREQMCLR_CH16_MASK 0x00010000 #define SI32_DMACTRL_A_CHREQMCLR_CH16_SHIFT 16 // Enable DMA Channel 16 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH16_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMCLR_CH16_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH16_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH16_SHIFT) #define SI32_DMACTRL_A_CHREQMCLR_CH17_MASK 0x00020000 #define SI32_DMACTRL_A_CHREQMCLR_CH17_SHIFT 17 // Enable DMA Channel 17 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH17_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMCLR_CH17_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH17_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH17_SHIFT) #define SI32_DMACTRL_A_CHREQMCLR_CH18_MASK 0x00040000 #define SI32_DMACTRL_A_CHREQMCLR_CH18_SHIFT 18 // Enable DMA Channel 18 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH18_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMCLR_CH18_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH18_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH18_SHIFT) #define SI32_DMACTRL_A_CHREQMCLR_CH19_MASK 0x00080000 #define SI32_DMACTRL_A_CHREQMCLR_CH19_SHIFT 19 // Enable DMA Channel 19 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH19_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMCLR_CH19_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH19_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH19_SHIFT) #define SI32_DMACTRL_A_CHREQMCLR_CH20_MASK 0x00100000 #define SI32_DMACTRL_A_CHREQMCLR_CH20_SHIFT 20 // Enable DMA Channel 20 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH20_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMCLR_CH20_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH20_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH20_SHIFT) #define SI32_DMACTRL_A_CHREQMCLR_CH21_MASK 0x00200000 #define SI32_DMACTRL_A_CHREQMCLR_CH21_SHIFT 21 // Enable DMA Channel 21 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH21_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMCLR_CH21_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH21_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH21_SHIFT) #define SI32_DMACTRL_A_CHREQMCLR_CH22_MASK 0x00400000 #define SI32_DMACTRL_A_CHREQMCLR_CH22_SHIFT 22 // Enable DMA Channel 22 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH22_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMCLR_CH22_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH22_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH22_SHIFT) #define SI32_DMACTRL_A_CHREQMCLR_CH23_MASK 0x00800000 #define SI32_DMACTRL_A_CHREQMCLR_CH23_SHIFT 23 // Enable DMA Channel 23 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH23_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMCLR_CH23_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH23_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH23_SHIFT) #define SI32_DMACTRL_A_CHREQMCLR_CH24_MASK 0x01000000 #define SI32_DMACTRL_A_CHREQMCLR_CH24_SHIFT 24 // Enable DMA Channel 24 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH24_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMCLR_CH24_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH24_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH24_SHIFT) #define SI32_DMACTRL_A_CHREQMCLR_CH25_MASK 0x02000000 #define SI32_DMACTRL_A_CHREQMCLR_CH25_SHIFT 25 // Enable DMA Channel 25 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH25_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMCLR_CH25_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH25_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH25_SHIFT) #define SI32_DMACTRL_A_CHREQMCLR_CH26_MASK 0x04000000 #define SI32_DMACTRL_A_CHREQMCLR_CH26_SHIFT 26 // Enable DMA Channel 26 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH26_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMCLR_CH26_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH26_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH26_SHIFT) #define SI32_DMACTRL_A_CHREQMCLR_CH27_MASK 0x08000000 #define SI32_DMACTRL_A_CHREQMCLR_CH27_SHIFT 27 // Enable DMA Channel 27 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH27_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMCLR_CH27_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH27_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH27_SHIFT) #define SI32_DMACTRL_A_CHREQMCLR_CH28_MASK 0x10000000 #define SI32_DMACTRL_A_CHREQMCLR_CH28_SHIFT 28 // Enable DMA Channel 28 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH28_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMCLR_CH28_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH28_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH28_SHIFT) #define SI32_DMACTRL_A_CHREQMCLR_CH29_MASK 0x20000000 #define SI32_DMACTRL_A_CHREQMCLR_CH29_SHIFT 29 // Enable DMA Channel 29 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH29_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMCLR_CH29_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH29_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH29_SHIFT) #define SI32_DMACTRL_A_CHREQMCLR_CH30_MASK 0x40000000 #define SI32_DMACTRL_A_CHREQMCLR_CH30_SHIFT 30 // Enable DMA Channel 30 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH30_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHREQMCLR_CH30_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH30_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH30_SHIFT) #define SI32_DMACTRL_A_CHREQMCLR_CH31_MASK 0x80000000 #define SI32_DMACTRL_A_CHREQMCLR_CH31_SHIFT 31 // Enable DMA Channel 31 peripheral data requests. #define SI32_DMACTRL_A_CHREQMCLR_CH31_DISABLED_VALUE 1U #define SI32_DMACTRL_A_CHREQMCLR_CH31_DISABLED_U32 \ (SI32_DMACTRL_A_CHREQMCLR_CH31_DISABLED_VALUE << SI32_DMACTRL_A_CHREQMCLR_CH31_SHIFT) struct SI32_DMACTRL_A_CHENSET_Struct { union { struct { // Channel 0 Enable volatile uint32_t CH0: 1; // Channel 1 Enable volatile uint32_t CH1: 1; // Channel 2 Enable volatile uint32_t CH2: 1; // Channel 3 Enable volatile uint32_t CH3: 1; // Channel 4 Enable volatile uint32_t CH4: 1; // Channel 5 Enable volatile uint32_t CH5: 1; // Channel 6 Enable volatile uint32_t CH6: 1; // Channel 7 Enable volatile uint32_t CH7: 1; // Channel 8 Enable volatile uint32_t CH8: 1; // Channel 9 Enable volatile uint32_t CH9: 1; // Channel 10 Enable volatile uint32_t CH10: 1; // Channel 11 Enable volatile uint32_t CH11: 1; // Channel 12 Enable volatile uint32_t CH12: 1; // Channel 13 Enable volatile uint32_t CH13: 1; // Channel 14 Enable volatile uint32_t CH14: 1; // Channel 15 Enable volatile uint32_t CH15: 1; // Channel 16 Enable volatile uint32_t CH16: 1; // Channel 17 Enable volatile uint32_t CH17: 1; // Channel 18 Enable volatile uint32_t CH18: 1; // Channel 19 Enable volatile uint32_t CH19: 1; // Channel 20 Enable volatile uint32_t CH20: 1; // Channel 21 Enable volatile uint32_t CH21: 1; // Channel 22 Enable volatile uint32_t CH22: 1; // Channel 23 Enable volatile uint32_t CH23: 1; // Channel 24 Enable volatile uint32_t CH24: 1; // Channel 25 Enable volatile uint32_t CH25: 1; // Channel 26 Enable volatile uint32_t CH26: 1; // Channel 27 Enable volatile uint32_t CH27: 1; // Channel 28 Enable volatile uint32_t CH28: 1; // Channel 29 Enable volatile uint32_t CH29: 1; // Channel 30 Enable volatile uint32_t CH30: 1; // Channel 31 Enable volatile uint32_t CH31: 1; }; volatile uint32_t U32; }; }; #define SI32_DMACTRL_A_CHENSET_CH0_MASK 0x00000001 #define SI32_DMACTRL_A_CHENSET_CH0_SHIFT 0 // Read: 0: DMA Channel 0 disabled. 1: DMA Channel 0 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 0. #define SI32_DMACTRL_A_CHENSET_CH0_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHENSET_CH0_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH0_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH0_SHIFT) #define SI32_DMACTRL_A_CHENSET_CH1_MASK 0x00000002 #define SI32_DMACTRL_A_CHENSET_CH1_SHIFT 1 // Read: 0: DMA Channel 1 disabled. 1: DMA Channel 1 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 1. #define SI32_DMACTRL_A_CHENSET_CH1_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHENSET_CH1_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH1_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH1_SHIFT) #define SI32_DMACTRL_A_CHENSET_CH2_MASK 0x00000004 #define SI32_DMACTRL_A_CHENSET_CH2_SHIFT 2 // Read: 0: DMA Channel 2 disabled. 1: DMA Channel 2 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 2. #define SI32_DMACTRL_A_CHENSET_CH2_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHENSET_CH2_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH2_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH2_SHIFT) #define SI32_DMACTRL_A_CHENSET_CH3_MASK 0x00000008 #define SI32_DMACTRL_A_CHENSET_CH3_SHIFT 3 // Read: 0: DMA Channel 3 disabled. 1: DMA Channel 3 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 3. #define SI32_DMACTRL_A_CHENSET_CH3_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHENSET_CH3_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH3_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH3_SHIFT) #define SI32_DMACTRL_A_CHENSET_CH4_MASK 0x00000010 #define SI32_DMACTRL_A_CHENSET_CH4_SHIFT 4 // Read: 0: DMA Channel 4 disabled. 1: DMA Channel 4 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 4. #define SI32_DMACTRL_A_CHENSET_CH4_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHENSET_CH4_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH4_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH4_SHIFT) #define SI32_DMACTRL_A_CHENSET_CH5_MASK 0x00000020 #define SI32_DMACTRL_A_CHENSET_CH5_SHIFT 5 // Read: 0: DMA Channel 5 disabled. 1: DMA Channel 5 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 5. #define SI32_DMACTRL_A_CHENSET_CH5_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHENSET_CH5_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH5_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH5_SHIFT) #define SI32_DMACTRL_A_CHENSET_CH6_MASK 0x00000040 #define SI32_DMACTRL_A_CHENSET_CH6_SHIFT 6 // Read: 0: DMA Channel 6 disabled. 1: DMA Channel 6 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 6. #define SI32_DMACTRL_A_CHENSET_CH6_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHENSET_CH6_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH6_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH6_SHIFT) #define SI32_DMACTRL_A_CHENSET_CH7_MASK 0x00000080 #define SI32_DMACTRL_A_CHENSET_CH7_SHIFT 7 // Read: 0: DMA Channel 7 disabled. 1: DMA Channel 7 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 7. #define SI32_DMACTRL_A_CHENSET_CH7_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHENSET_CH7_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH7_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH7_SHIFT) #define SI32_DMACTRL_A_CHENSET_CH8_MASK 0x00000100 #define SI32_DMACTRL_A_CHENSET_CH8_SHIFT 8 // Read: 0: DMA Channel 8 disabled. 1: DMA Channel 8 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 8. #define SI32_DMACTRL_A_CHENSET_CH8_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHENSET_CH8_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH8_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH8_SHIFT) #define SI32_DMACTRL_A_CHENSET_CH9_MASK 0x00000200 #define SI32_DMACTRL_A_CHENSET_CH9_SHIFT 9 // Read: 0: DMA Channel 9 disabled. 1: DMA Channel 9 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 9. #define SI32_DMACTRL_A_CHENSET_CH9_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHENSET_CH9_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH9_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH9_SHIFT) #define SI32_DMACTRL_A_CHENSET_CH10_MASK 0x00000400 #define SI32_DMACTRL_A_CHENSET_CH10_SHIFT 10 // Read: 0: DMA Channel 10 disabled. 1: DMA Channel 10 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 10. #define SI32_DMACTRL_A_CHENSET_CH10_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHENSET_CH10_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH10_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH10_SHIFT) #define SI32_DMACTRL_A_CHENSET_CH11_MASK 0x00000800 #define SI32_DMACTRL_A_CHENSET_CH11_SHIFT 11 // Read: 0: DMA Channel 11 disabled. 1: DMA Channel 11 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 11. #define SI32_DMACTRL_A_CHENSET_CH11_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHENSET_CH11_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH11_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH11_SHIFT) #define SI32_DMACTRL_A_CHENSET_CH12_MASK 0x00001000 #define SI32_DMACTRL_A_CHENSET_CH12_SHIFT 12 // Read: 0: DMA Channel 12 disabled. 1: DMA Channel 12 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 12. #define SI32_DMACTRL_A_CHENSET_CH12_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHENSET_CH12_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH12_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH12_SHIFT) #define SI32_DMACTRL_A_CHENSET_CH13_MASK 0x00002000 #define SI32_DMACTRL_A_CHENSET_CH13_SHIFT 13 // Read: 0: DMA Channel 13 disabled. 1: DMA Channel 13 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 13. #define SI32_DMACTRL_A_CHENSET_CH13_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHENSET_CH13_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH13_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH13_SHIFT) #define SI32_DMACTRL_A_CHENSET_CH14_MASK 0x00004000 #define SI32_DMACTRL_A_CHENSET_CH14_SHIFT 14 // Read: 0: DMA Channel 14 disabled. 1: DMA Channel 14 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 14. #define SI32_DMACTRL_A_CHENSET_CH14_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHENSET_CH14_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH14_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH14_SHIFT) #define SI32_DMACTRL_A_CHENSET_CH15_MASK 0x00008000 #define SI32_DMACTRL_A_CHENSET_CH15_SHIFT 15 // Read: 0: DMA Channel 15 disabled. 1: DMA Channel 15 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 15. #define SI32_DMACTRL_A_CHENSET_CH15_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHENSET_CH15_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH15_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH15_SHIFT) #define SI32_DMACTRL_A_CHENSET_CH16_MASK 0x00010000 #define SI32_DMACTRL_A_CHENSET_CH16_SHIFT 16 // Read: 0: DMA Channel 16 disabled. 1: DMA Channel 16 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 16. #define SI32_DMACTRL_A_CHENSET_CH16_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHENSET_CH16_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH16_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH16_SHIFT) #define SI32_DMACTRL_A_CHENSET_CH17_MASK 0x00020000 #define SI32_DMACTRL_A_CHENSET_CH17_SHIFT 17 // Read: 0: DMA Channel 17 disabled. 1: DMA Channel 17 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 17. #define SI32_DMACTRL_A_CHENSET_CH17_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHENSET_CH17_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH17_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH17_SHIFT) #define SI32_DMACTRL_A_CHENSET_CH18_MASK 0x00040000 #define SI32_DMACTRL_A_CHENSET_CH18_SHIFT 18 // Read: 0: DMA Channel 18 disabled. 1: DMA Channel 18 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 18. #define SI32_DMACTRL_A_CHENSET_CH18_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHENSET_CH18_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH18_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH18_SHIFT) #define SI32_DMACTRL_A_CHENSET_CH19_MASK 0x00080000 #define SI32_DMACTRL_A_CHENSET_CH19_SHIFT 19 // Read: 0: DMA Channel 19 disabled. 1: DMA Channel 19 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 19. #define SI32_DMACTRL_A_CHENSET_CH19_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHENSET_CH19_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH19_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH19_SHIFT) #define SI32_DMACTRL_A_CHENSET_CH20_MASK 0x00100000 #define SI32_DMACTRL_A_CHENSET_CH20_SHIFT 20 // Read: 0: DMA Channel 20 disabled. 1: DMA Channel 20 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 20. #define SI32_DMACTRL_A_CHENSET_CH20_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHENSET_CH20_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH20_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH20_SHIFT) #define SI32_DMACTRL_A_CHENSET_CH21_MASK 0x00200000 #define SI32_DMACTRL_A_CHENSET_CH21_SHIFT 21 // Read: 0: DMA Channel 21 disabled. 1: DMA Channel 21 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 21. #define SI32_DMACTRL_A_CHENSET_CH21_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHENSET_CH21_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH21_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH21_SHIFT) #define SI32_DMACTRL_A_CHENSET_CH22_MASK 0x00400000 #define SI32_DMACTRL_A_CHENSET_CH22_SHIFT 22 // Read: 0: DMA Channel 22 disabled. 1: DMA Channel 22 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 22. #define SI32_DMACTRL_A_CHENSET_CH22_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHENSET_CH22_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH22_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH22_SHIFT) #define SI32_DMACTRL_A_CHENSET_CH23_MASK 0x00800000 #define SI32_DMACTRL_A_CHENSET_CH23_SHIFT 23 // Read: 0: DMA Channel 23 disabled. 1: DMA Channel 23 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 23. #define SI32_DMACTRL_A_CHENSET_CH23_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHENSET_CH23_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH23_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH23_SHIFT) #define SI32_DMACTRL_A_CHENSET_CH24_MASK 0x01000000 #define SI32_DMACTRL_A_CHENSET_CH24_SHIFT 24 // Read: 0: DMA Channel 24 disabled. 1: DMA Channel 24 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 24. #define SI32_DMACTRL_A_CHENSET_CH24_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHENSET_CH24_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH24_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH24_SHIFT) #define SI32_DMACTRL_A_CHENSET_CH25_MASK 0x02000000 #define SI32_DMACTRL_A_CHENSET_CH25_SHIFT 25 // Read: 0: DMA Channel 25 disabled. 1: DMA Channel 25 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 25. #define SI32_DMACTRL_A_CHENSET_CH25_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHENSET_CH25_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH25_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH25_SHIFT) #define SI32_DMACTRL_A_CHENSET_CH26_MASK 0x04000000 #define SI32_DMACTRL_A_CHENSET_CH26_SHIFT 26 // Read: 0: DMA Channel 26 disabled. 1: DMA Channel 26 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 26. #define SI32_DMACTRL_A_CHENSET_CH26_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHENSET_CH26_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH26_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH26_SHIFT) #define SI32_DMACTRL_A_CHENSET_CH27_MASK 0x08000000 #define SI32_DMACTRL_A_CHENSET_CH27_SHIFT 27 // Read: 0: DMA Channel 27 disabled. 1: DMA Channel 27 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 27. #define SI32_DMACTRL_A_CHENSET_CH27_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHENSET_CH27_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH27_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH27_SHIFT) #define SI32_DMACTRL_A_CHENSET_CH28_MASK 0x10000000 #define SI32_DMACTRL_A_CHENSET_CH28_SHIFT 28 // Read: 0: DMA Channel 28 disabled. 1: DMA Channel 28 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 28. #define SI32_DMACTRL_A_CHENSET_CH28_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHENSET_CH28_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH28_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH28_SHIFT) #define SI32_DMACTRL_A_CHENSET_CH29_MASK 0x20000000 #define SI32_DMACTRL_A_CHENSET_CH29_SHIFT 29 // Read: 0: DMA Channel 29 disabled. 1: DMA Channel 29 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 29. #define SI32_DMACTRL_A_CHENSET_CH29_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHENSET_CH29_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH29_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH29_SHIFT) #define SI32_DMACTRL_A_CHENSET_CH30_MASK 0x40000000 #define SI32_DMACTRL_A_CHENSET_CH30_SHIFT 30 // Read: 0: DMA Channel 30 disabled. 1: DMA Channel 30 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 30. #define SI32_DMACTRL_A_CHENSET_CH30_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHENSET_CH30_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH30_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH30_SHIFT) #define SI32_DMACTRL_A_CHENSET_CH31_MASK 0x80000000 #define SI32_DMACTRL_A_CHENSET_CH31_SHIFT 31 // Read: 0: DMA Channel 31 disabled. 1: DMA Channel 31 enabled. Write: 0: No effect // (use CHENCLR to clear). 1: Enable DMA Channel 31. #define SI32_DMACTRL_A_CHENSET_CH31_ENABLED_VALUE 1U #define SI32_DMACTRL_A_CHENSET_CH31_ENABLED_U32 \ (SI32_DMACTRL_A_CHENSET_CH31_ENABLED_VALUE << SI32_DMACTRL_A_CHENSET_CH31_SHIFT) struct SI32_DMACTRL_A_CHENCLR_Struct { union { struct { // Channel 0 Disable volatile uint32_t CH0: 1; // Channel 1 Disable volatile uint32_t CH1: 1; // Channel 2 Disable volatile uint32_t CH2: 1; // Channel 3 Disable volatile uint32_t CH3: 1; // Channel 4 Disable volatile uint32_t CH4: 1; // Channel 5 Disable volatile uint32_t CH5: 1; // Channel 6 Disable volatile uint32_t CH6: 1; // Channel 7 Disable volatile uint32_t CH7: 1; // Channel 8 Disable volatile uint32_t CH8: 1; // Channel 9 Disable volatile uint32_t CH9: 1; // Channel 10 Disable volatile uint32_t CH10: 1; // Channel 11 Disable volatile uint32_t CH11: 1; // Channel 12 Disable volatile uint32_t CH12: 1; // Channel 13 Disable volatile uint32_t CH13: 1; // Channel 14 Disable volatile uint32_t CH14: 1; // Channel 15 Disable volatile uint32_t CH15: 1; // Channel 16 Disable volatile uint32_t CH16: 1; // Channel 17 Disable volatile uint32_t CH17: 1; // Channel 18 Disable volatile uint32_t CH18: 1; // Channel 19 Disable volatile uint32_t CH19: 1; // Channel 20 Disable volatile uint32_t CH20: 1; // Channel 21 Disable volatile uint32_t CH21: 1; // Channel 22 Disable volatile uint32_t CH22: 1; // Channel 23 Disable volatile uint32_t CH23: 1; // Channel 24 Disable volatile uint32_t CH24: 1; // Channel 25 Disable volatile uint32_t CH25: 1; // Channel 26 Disable volatile uint32_t CH26: 1; // Channel 27 Disable volatile uint32_t CH27: 1; // Channel 28 Disable volatile uint32_t CH28: 1; // Channel 29 Disable volatile uint32_t CH29: 1; // Channel 30 Disable volatile uint32_t CH30: 1; // Channel 31 Disable volatile uint32_t CH31: 1; }; volatile uint32_t U32; }; }; #define SI32_DMACTRL_A_CHENCLR_CH0_MASK 0x00000001 #define SI32_DMACTRL_A_CHENCLR_CH0_SHIFT 0 // Disable DMA Channel 0. #define SI32_DMACTRL_A_CHENCLR_CH0_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHENCLR_CH0_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH0_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH0_SHIFT) #define SI32_DMACTRL_A_CHENCLR_CH1_MASK 0x00000002 #define SI32_DMACTRL_A_CHENCLR_CH1_SHIFT 1 // Disable DMA Channel 1. #define SI32_DMACTRL_A_CHENCLR_CH1_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHENCLR_CH1_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH1_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH1_SHIFT) #define SI32_DMACTRL_A_CHENCLR_CH2_MASK 0x00000004 #define SI32_DMACTRL_A_CHENCLR_CH2_SHIFT 2 // Disable DMA Channel 2. #define SI32_DMACTRL_A_CHENCLR_CH2_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHENCLR_CH2_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH2_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH2_SHIFT) #define SI32_DMACTRL_A_CHENCLR_CH3_MASK 0x00000008 #define SI32_DMACTRL_A_CHENCLR_CH3_SHIFT 3 // Disable DMA Channel 3. #define SI32_DMACTRL_A_CHENCLR_CH3_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHENCLR_CH3_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH3_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH3_SHIFT) #define SI32_DMACTRL_A_CHENCLR_CH4_MASK 0x00000010 #define SI32_DMACTRL_A_CHENCLR_CH4_SHIFT 4 // Disable DMA Channel 4. #define SI32_DMACTRL_A_CHENCLR_CH4_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHENCLR_CH4_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH4_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH4_SHIFT) #define SI32_DMACTRL_A_CHENCLR_CH5_MASK 0x00000020 #define SI32_DMACTRL_A_CHENCLR_CH5_SHIFT 5 // Disable DMA Channel 5. #define SI32_DMACTRL_A_CHENCLR_CH5_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHENCLR_CH5_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH5_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH5_SHIFT) #define SI32_DMACTRL_A_CHENCLR_CH6_MASK 0x00000040 #define SI32_DMACTRL_A_CHENCLR_CH6_SHIFT 6 // Disable DMA Channel 6. #define SI32_DMACTRL_A_CHENCLR_CH6_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHENCLR_CH6_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH6_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH6_SHIFT) #define SI32_DMACTRL_A_CHENCLR_CH7_MASK 0x00000080 #define SI32_DMACTRL_A_CHENCLR_CH7_SHIFT 7 // Disable DMA Channel 7. #define SI32_DMACTRL_A_CHENCLR_CH7_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHENCLR_CH7_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH7_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH7_SHIFT) #define SI32_DMACTRL_A_CHENCLR_CH8_MASK 0x00000100 #define SI32_DMACTRL_A_CHENCLR_CH8_SHIFT 8 // Disable DMA Channel 8. #define SI32_DMACTRL_A_CHENCLR_CH8_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHENCLR_CH8_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH8_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH8_SHIFT) #define SI32_DMACTRL_A_CHENCLR_CH9_MASK 0x00000200 #define SI32_DMACTRL_A_CHENCLR_CH9_SHIFT 9 // Disable DMA Channel 9. #define SI32_DMACTRL_A_CHENCLR_CH9_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHENCLR_CH9_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH9_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH9_SHIFT) #define SI32_DMACTRL_A_CHENCLR_CH10_MASK 0x00000400 #define SI32_DMACTRL_A_CHENCLR_CH10_SHIFT 10 // Disable DMA Channel 10. #define SI32_DMACTRL_A_CHENCLR_CH10_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHENCLR_CH10_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH10_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH10_SHIFT) #define SI32_DMACTRL_A_CHENCLR_CH11_MASK 0x00000800 #define SI32_DMACTRL_A_CHENCLR_CH11_SHIFT 11 // Disable DMA Channel 11. #define SI32_DMACTRL_A_CHENCLR_CH11_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHENCLR_CH11_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH11_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH11_SHIFT) #define SI32_DMACTRL_A_CHENCLR_CH12_MASK 0x00001000 #define SI32_DMACTRL_A_CHENCLR_CH12_SHIFT 12 // Disable DMA Channel 12. #define SI32_DMACTRL_A_CHENCLR_CH12_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHENCLR_CH12_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH12_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH12_SHIFT) #define SI32_DMACTRL_A_CHENCLR_CH13_MASK 0x00002000 #define SI32_DMACTRL_A_CHENCLR_CH13_SHIFT 13 // Disable DMA Channel 13. #define SI32_DMACTRL_A_CHENCLR_CH13_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHENCLR_CH13_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH13_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH13_SHIFT) #define SI32_DMACTRL_A_CHENCLR_CH14_MASK 0x00004000 #define SI32_DMACTRL_A_CHENCLR_CH14_SHIFT 14 // Disable DMA Channel 14. #define SI32_DMACTRL_A_CHENCLR_CH14_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHENCLR_CH14_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH14_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH14_SHIFT) #define SI32_DMACTRL_A_CHENCLR_CH15_MASK 0x00008000 #define SI32_DMACTRL_A_CHENCLR_CH15_SHIFT 15 // Disable DMA Channel 15. #define SI32_DMACTRL_A_CHENCLR_CH15_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHENCLR_CH15_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH15_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH15_SHIFT) #define SI32_DMACTRL_A_CHENCLR_CH16_MASK 0x00010000 #define SI32_DMACTRL_A_CHENCLR_CH16_SHIFT 16 // Disable DMA Channel 16. #define SI32_DMACTRL_A_CHENCLR_CH16_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHENCLR_CH16_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH16_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH16_SHIFT) #define SI32_DMACTRL_A_CHENCLR_CH17_MASK 0x00020000 #define SI32_DMACTRL_A_CHENCLR_CH17_SHIFT 17 // Disable DMA Channel 17. #define SI32_DMACTRL_A_CHENCLR_CH17_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHENCLR_CH17_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH17_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH17_SHIFT) #define SI32_DMACTRL_A_CHENCLR_CH18_MASK 0x00040000 #define SI32_DMACTRL_A_CHENCLR_CH18_SHIFT 18 // Disable DMA Channel 18. #define SI32_DMACTRL_A_CHENCLR_CH18_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHENCLR_CH18_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH18_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH18_SHIFT) #define SI32_DMACTRL_A_CHENCLR_CH19_MASK 0x00080000 #define SI32_DMACTRL_A_CHENCLR_CH19_SHIFT 19 // Disable DMA Channel 19. #define SI32_DMACTRL_A_CHENCLR_CH19_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHENCLR_CH19_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH19_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH19_SHIFT) #define SI32_DMACTRL_A_CHENCLR_CH20_MASK 0x00100000 #define SI32_DMACTRL_A_CHENCLR_CH20_SHIFT 20 // Disable DMA Channel 20. #define SI32_DMACTRL_A_CHENCLR_CH20_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHENCLR_CH20_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH20_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH20_SHIFT) #define SI32_DMACTRL_A_CHENCLR_CH21_MASK 0x00200000 #define SI32_DMACTRL_A_CHENCLR_CH21_SHIFT 21 // Disable DMA Channel 21. #define SI32_DMACTRL_A_CHENCLR_CH21_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHENCLR_CH21_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH21_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH21_SHIFT) #define SI32_DMACTRL_A_CHENCLR_CH22_MASK 0x00400000 #define SI32_DMACTRL_A_CHENCLR_CH22_SHIFT 22 // Disable DMA Channel 22. #define SI32_DMACTRL_A_CHENCLR_CH22_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHENCLR_CH22_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH22_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH22_SHIFT) #define SI32_DMACTRL_A_CHENCLR_CH23_MASK 0x00800000 #define SI32_DMACTRL_A_CHENCLR_CH23_SHIFT 23 // Disable DMA Channel 23. #define SI32_DMACTRL_A_CHENCLR_CH23_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHENCLR_CH23_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH23_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH23_SHIFT) #define SI32_DMACTRL_A_CHENCLR_CH24_MASK 0x01000000 #define SI32_DMACTRL_A_CHENCLR_CH24_SHIFT 24 // Disable DMA Channel 24. #define SI32_DMACTRL_A_CHENCLR_CH24_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHENCLR_CH24_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH24_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH24_SHIFT) #define SI32_DMACTRL_A_CHENCLR_CH25_MASK 0x02000000 #define SI32_DMACTRL_A_CHENCLR_CH25_SHIFT 25 // Disable DMA Channel 25. #define SI32_DMACTRL_A_CHENCLR_CH25_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHENCLR_CH25_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH25_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH25_SHIFT) #define SI32_DMACTRL_A_CHENCLR_CH26_MASK 0x04000000 #define SI32_DMACTRL_A_CHENCLR_CH26_SHIFT 26 // Disable DMA Channel 26. #define SI32_DMACTRL_A_CHENCLR_CH26_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHENCLR_CH26_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH26_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH26_SHIFT) #define SI32_DMACTRL_A_CHENCLR_CH27_MASK 0x08000000 #define SI32_DMACTRL_A_CHENCLR_CH27_SHIFT 27 // Disable DMA Channel 27. #define SI32_DMACTRL_A_CHENCLR_CH27_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHENCLR_CH27_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH27_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH27_SHIFT) #define SI32_DMACTRL_A_CHENCLR_CH28_MASK 0x10000000 #define SI32_DMACTRL_A_CHENCLR_CH28_SHIFT 28 // Disable DMA Channel 28. #define SI32_DMACTRL_A_CHENCLR_CH28_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHENCLR_CH28_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH28_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH28_SHIFT) #define SI32_DMACTRL_A_CHENCLR_CH29_MASK 0x20000000 #define SI32_DMACTRL_A_CHENCLR_CH29_SHIFT 29 // Disable DMA Channel 29. #define SI32_DMACTRL_A_CHENCLR_CH29_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHENCLR_CH29_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH29_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH29_SHIFT) #define SI32_DMACTRL_A_CHENCLR_CH30_MASK 0x40000000 #define SI32_DMACTRL_A_CHENCLR_CH30_SHIFT 30 // Disable DMA Channel 30. #define SI32_DMACTRL_A_CHENCLR_CH30_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHENCLR_CH30_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH30_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH30_SHIFT) #define SI32_DMACTRL_A_CHENCLR_CH31_MASK 0x80000000 #define SI32_DMACTRL_A_CHENCLR_CH31_SHIFT 31 // Disable DMA Channel 31. #define SI32_DMACTRL_A_CHENCLR_CH31_DISABLED_VALUE 1U #define SI32_DMACTRL_A_CHENCLR_CH31_DISABLED_U32 \ (SI32_DMACTRL_A_CHENCLR_CH31_DISABLED_VALUE << SI32_DMACTRL_A_CHENCLR_CH31_SHIFT) struct SI32_DMACTRL_A_CHALTSET_Struct { union { struct { // Channel 0 Alternate Enable volatile uint32_t CH0: 1; // Channel 1 Alternate Enable volatile uint32_t CH1: 1; // Channel 2 Alternate Enable volatile uint32_t CH2: 1; // Channel 3 Alternate Enable volatile uint32_t CH3: 1; // Channel 4 Alternate Enable volatile uint32_t CH4: 1; // Channel 5 Alternate Enable volatile uint32_t CH5: 1; // Channel 6 Alternate Enable volatile uint32_t CH6: 1; // Channel 7 Alternate Enable volatile uint32_t CH7: 1; // Channel 8 Alternate Enable volatile uint32_t CH8: 1; // Channel 9 Alternate Enable volatile uint32_t CH9: 1; // Channel 10 Alternate Enable volatile uint32_t CH10: 1; // Channel 11 Alternate Enable volatile uint32_t CH11: 1; // Channel 12 Alternate Enable volatile uint32_t CH12: 1; // Channel 13 Alternate Enable volatile uint32_t CH13: 1; // Channel 14 Alternate Enable volatile uint32_t CH14: 1; // Channel 15 Alternate Enable volatile uint32_t CH15: 1; // Channel 16 Alternate Enable volatile uint32_t CH16: 1; // Channel 17 Alternate Enable volatile uint32_t CH17: 1; // Channel 18 Alternate Enable volatile uint32_t CH18: 1; // Channel 19 Alternate Enable volatile uint32_t CH19: 1; // Channel 20 Alternate Enable volatile uint32_t CH20: 1; // Channel 21 Alternate Enable volatile uint32_t CH21: 1; // Channel 22 Alternate Enable volatile uint32_t CH22: 1; // Channel 23 Alternate Enable volatile uint32_t CH23: 1; // Channel 24 Alternate Enable volatile uint32_t CH24: 1; // Channel 25 Alternate Enable volatile uint32_t CH25: 1; // Channel 26 Alternate Enable volatile uint32_t CH26: 1; // Channel 27 Alternate Enable volatile uint32_t CH27: 1; // Channel 28 Alternate Enable volatile uint32_t CH28: 1; // Channel 29 Alternate Enable volatile uint32_t CH29: 1; // Channel 30 Alternate Enable volatile uint32_t CH30: 1; // Channel 31 Alternate Enable volatile uint32_t CH31: 1; }; volatile uint32_t U32; }; }; #define SI32_DMACTRL_A_CHALTSET_CH0_MASK 0x00000001 #define SI32_DMACTRL_A_CHALTSET_CH0_SHIFT 0 // Read: 0: DMA Channel 0 is using primary data structure. 1: DMA Channel 0 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 0. #define SI32_DMACTRL_A_CHALTSET_CH0_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTSET_CH0_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH0_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH0_SHIFT) #define SI32_DMACTRL_A_CHALTSET_CH1_MASK 0x00000002 #define SI32_DMACTRL_A_CHALTSET_CH1_SHIFT 1 // Read: 0: DMA Channel 1 is using primary data structure. 1: DMA Channel 1 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 1. #define SI32_DMACTRL_A_CHALTSET_CH1_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTSET_CH1_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH1_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH1_SHIFT) #define SI32_DMACTRL_A_CHALTSET_CH2_MASK 0x00000004 #define SI32_DMACTRL_A_CHALTSET_CH2_SHIFT 2 // Read: 0: DMA Channel 2 is using primary data structure. 1: DMA Channel 2 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 2. #define SI32_DMACTRL_A_CHALTSET_CH2_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTSET_CH2_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH2_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH2_SHIFT) #define SI32_DMACTRL_A_CHALTSET_CH3_MASK 0x00000008 #define SI32_DMACTRL_A_CHALTSET_CH3_SHIFT 3 // Read: 0: DMA Channel 3 is using primary data structure. 1: DMA Channel 3 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 3. #define SI32_DMACTRL_A_CHALTSET_CH3_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTSET_CH3_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH3_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH3_SHIFT) #define SI32_DMACTRL_A_CHALTSET_CH4_MASK 0x00000010 #define SI32_DMACTRL_A_CHALTSET_CH4_SHIFT 4 // Read: 0: DMA Channel 4 is using primary data structure. 1: DMA Channel 4 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 4. #define SI32_DMACTRL_A_CHALTSET_CH4_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTSET_CH4_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH4_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH4_SHIFT) #define SI32_DMACTRL_A_CHALTSET_CH5_MASK 0x00000020 #define SI32_DMACTRL_A_CHALTSET_CH5_SHIFT 5 // Read: 0: DMA Channel 5 is using primary data structure. 1: DMA Channel 5 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 5. #define SI32_DMACTRL_A_CHALTSET_CH5_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTSET_CH5_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH5_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH5_SHIFT) #define SI32_DMACTRL_A_CHALTSET_CH6_MASK 0x00000040 #define SI32_DMACTRL_A_CHALTSET_CH6_SHIFT 6 // Read: 0: DMA Channel 6 is using primary data structure. 1: DMA Channel 6 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 6. #define SI32_DMACTRL_A_CHALTSET_CH6_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTSET_CH6_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH6_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH6_SHIFT) #define SI32_DMACTRL_A_CHALTSET_CH7_MASK 0x00000080 #define SI32_DMACTRL_A_CHALTSET_CH7_SHIFT 7 // Read: 0: DMA Channel 7 is using primary data structure. 1: DMA Channel 7 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 7. #define SI32_DMACTRL_A_CHALTSET_CH7_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTSET_CH7_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH7_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH7_SHIFT) #define SI32_DMACTRL_A_CHALTSET_CH8_MASK 0x00000100 #define SI32_DMACTRL_A_CHALTSET_CH8_SHIFT 8 // Read: 0: DMA Channel 8 is using primary data structure. 1: DMA Channel 8 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 8. #define SI32_DMACTRL_A_CHALTSET_CH8_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTSET_CH8_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH8_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH8_SHIFT) #define SI32_DMACTRL_A_CHALTSET_CH9_MASK 0x00000200 #define SI32_DMACTRL_A_CHALTSET_CH9_SHIFT 9 // Read: 0: DMA Channel 9 is using primary data structure. 1: DMA Channel 9 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 9. #define SI32_DMACTRL_A_CHALTSET_CH9_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTSET_CH9_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH9_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH9_SHIFT) #define SI32_DMACTRL_A_CHALTSET_CH10_MASK 0x00000400 #define SI32_DMACTRL_A_CHALTSET_CH10_SHIFT 10 // Read: 0: DMA Channel 10 is using primary data structure. 1: DMA Channel 10 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 10. #define SI32_DMACTRL_A_CHALTSET_CH10_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTSET_CH10_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH10_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH10_SHIFT) #define SI32_DMACTRL_A_CHALTSET_CH11_MASK 0x00000800 #define SI32_DMACTRL_A_CHALTSET_CH11_SHIFT 11 // Read: 0: DMA Channel 11 is using primary data structure. 1: DMA Channel 11 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 11. #define SI32_DMACTRL_A_CHALTSET_CH11_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTSET_CH11_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH11_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH11_SHIFT) #define SI32_DMACTRL_A_CHALTSET_CH12_MASK 0x00001000 #define SI32_DMACTRL_A_CHALTSET_CH12_SHIFT 12 // Read: 0: DMA Channel 12 is using primary data structure. 1: DMA Channel 12 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 12. #define SI32_DMACTRL_A_CHALTSET_CH12_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTSET_CH12_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH12_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH12_SHIFT) #define SI32_DMACTRL_A_CHALTSET_CH13_MASK 0x00002000 #define SI32_DMACTRL_A_CHALTSET_CH13_SHIFT 13 // Read: 0: DMA Channel 13 is using primary data structure. 1: DMA Channel 13 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 13. #define SI32_DMACTRL_A_CHALTSET_CH13_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTSET_CH13_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH13_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH13_SHIFT) #define SI32_DMACTRL_A_CHALTSET_CH14_MASK 0x00004000 #define SI32_DMACTRL_A_CHALTSET_CH14_SHIFT 14 // Read: 0: DMA Channel 14 is using primary data structure. 1: DMA Channel 14 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 14. #define SI32_DMACTRL_A_CHALTSET_CH14_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTSET_CH14_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH14_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH14_SHIFT) #define SI32_DMACTRL_A_CHALTSET_CH15_MASK 0x00008000 #define SI32_DMACTRL_A_CHALTSET_CH15_SHIFT 15 // Read: 0: DMA Channel 15 is using primary data structure. 1: DMA Channel 15 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 15. #define SI32_DMACTRL_A_CHALTSET_CH15_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTSET_CH15_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH15_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH15_SHIFT) #define SI32_DMACTRL_A_CHALTSET_CH16_MASK 0x00010000 #define SI32_DMACTRL_A_CHALTSET_CH16_SHIFT 16 // Read: 0: DMA Channel 16 is using primary data structure. 1: DMA Channel 16 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 16. #define SI32_DMACTRL_A_CHALTSET_CH16_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTSET_CH16_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH16_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH16_SHIFT) #define SI32_DMACTRL_A_CHALTSET_CH17_MASK 0x00020000 #define SI32_DMACTRL_A_CHALTSET_CH17_SHIFT 17 // Read: 0: DMA Channel 17 is using primary data structure. 1: DMA Channel 17 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 17. #define SI32_DMACTRL_A_CHALTSET_CH17_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTSET_CH17_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH17_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH17_SHIFT) #define SI32_DMACTRL_A_CHALTSET_CH18_MASK 0x00040000 #define SI32_DMACTRL_A_CHALTSET_CH18_SHIFT 18 // Read: 0: DMA Channel 18 is using primary data structure. 1: DMA Channel 18 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 18. #define SI32_DMACTRL_A_CHALTSET_CH18_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTSET_CH18_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH18_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH18_SHIFT) #define SI32_DMACTRL_A_CHALTSET_CH19_MASK 0x00080000 #define SI32_DMACTRL_A_CHALTSET_CH19_SHIFT 19 // Read: 0: DMA Channel 19 is using primary data structure. 1: DMA Channel 19 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 19. #define SI32_DMACTRL_A_CHALTSET_CH19_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTSET_CH19_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH19_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH19_SHIFT) #define SI32_DMACTRL_A_CHALTSET_CH20_MASK 0x00100000 #define SI32_DMACTRL_A_CHALTSET_CH20_SHIFT 20 // Read: 0: DMA Channel 20 is using primary data structure. 1: DMA Channel 20 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 20. #define SI32_DMACTRL_A_CHALTSET_CH20_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTSET_CH20_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH20_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH20_SHIFT) #define SI32_DMACTRL_A_CHALTSET_CH21_MASK 0x00200000 #define SI32_DMACTRL_A_CHALTSET_CH21_SHIFT 21 // Read: 0: DMA Channel 21 is using primary data structure. 1: DMA Channel 21 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 21. #define SI32_DMACTRL_A_CHALTSET_CH21_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTSET_CH21_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH21_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH21_SHIFT) #define SI32_DMACTRL_A_CHALTSET_CH22_MASK 0x00400000 #define SI32_DMACTRL_A_CHALTSET_CH22_SHIFT 22 // Read: 0: DMA Channel 22 is using primary data structure. 1: DMA Channel 22 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 22. #define SI32_DMACTRL_A_CHALTSET_CH22_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTSET_CH22_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH22_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH22_SHIFT) #define SI32_DMACTRL_A_CHALTSET_CH23_MASK 0x00800000 #define SI32_DMACTRL_A_CHALTSET_CH23_SHIFT 23 // Read: 0: DMA Channel 23 is using primary data structure. 1: DMA Channel 23 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 23. #define SI32_DMACTRL_A_CHALTSET_CH23_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTSET_CH23_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH23_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH23_SHIFT) #define SI32_DMACTRL_A_CHALTSET_CH24_MASK 0x01000000 #define SI32_DMACTRL_A_CHALTSET_CH24_SHIFT 24 // Read: 0: DMA Channel 24 is using primary data structure. 1: DMA Channel 24 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 24. #define SI32_DMACTRL_A_CHALTSET_CH24_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTSET_CH24_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH24_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH24_SHIFT) #define SI32_DMACTRL_A_CHALTSET_CH25_MASK 0x02000000 #define SI32_DMACTRL_A_CHALTSET_CH25_SHIFT 25 // Read: 0: DMA Channel 25 is using primary data structure. 1: DMA Channel 25 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 25. #define SI32_DMACTRL_A_CHALTSET_CH25_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTSET_CH25_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH25_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH25_SHIFT) #define SI32_DMACTRL_A_CHALTSET_CH26_MASK 0x04000000 #define SI32_DMACTRL_A_CHALTSET_CH26_SHIFT 26 // Read: 0: DMA Channel 26 is using primary data structure. 1: DMA Channel 26 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 26. #define SI32_DMACTRL_A_CHALTSET_CH26_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTSET_CH26_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH26_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH26_SHIFT) #define SI32_DMACTRL_A_CHALTSET_CH27_MASK 0x08000000 #define SI32_DMACTRL_A_CHALTSET_CH27_SHIFT 27 // Read: 0: DMA Channel 27 is using primary data structure. 1: DMA Channel 27 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 27. #define SI32_DMACTRL_A_CHALTSET_CH27_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTSET_CH27_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH27_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH27_SHIFT) #define SI32_DMACTRL_A_CHALTSET_CH28_MASK 0x10000000 #define SI32_DMACTRL_A_CHALTSET_CH28_SHIFT 28 // Read: 0: DMA Channel 28 is using primary data structure. 1: DMA Channel 28 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 28. #define SI32_DMACTRL_A_CHALTSET_CH28_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTSET_CH28_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH28_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH28_SHIFT) #define SI32_DMACTRL_A_CHALTSET_CH29_MASK 0x20000000 #define SI32_DMACTRL_A_CHALTSET_CH29_SHIFT 29 // Read: 0: DMA Channel 29 is using primary data structure. 1: DMA Channel 29 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 29. #define SI32_DMACTRL_A_CHALTSET_CH29_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTSET_CH29_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH29_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH29_SHIFT) #define SI32_DMACTRL_A_CHALTSET_CH30_MASK 0x40000000 #define SI32_DMACTRL_A_CHALTSET_CH30_SHIFT 30 // Read: 0: DMA Channel 30 is using primary data structure. 1: DMA Channel 30 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 30. #define SI32_DMACTRL_A_CHALTSET_CH30_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTSET_CH30_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH30_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH30_SHIFT) #define SI32_DMACTRL_A_CHALTSET_CH31_MASK 0x80000000 #define SI32_DMACTRL_A_CHALTSET_CH31_SHIFT 31 // Read: 0: DMA Channel 31 is using primary data structure. 1: DMA Channel 31 is // using alternate data structure. Write: 0: No effect (use CHALTCLR to clear). 1: // Use the alternate data structure for DMA Channel 31. #define SI32_DMACTRL_A_CHALTSET_CH31_ENABLED_VALUE 1U #define SI32_DMACTRL_A_CHALTSET_CH31_ENABLED_U32 \ (SI32_DMACTRL_A_CHALTSET_CH31_ENABLED_VALUE << SI32_DMACTRL_A_CHALTSET_CH31_SHIFT) struct SI32_DMACTRL_A_CHALTCLR_Struct { union { struct { // Channel 0 Alternate Disable volatile uint32_t CH0: 1; // Channel 1 Alternate Disable volatile uint32_t CH1: 1; // Channel 2 Alternate Disable volatile uint32_t CH2: 1; // Channel 3 Alternate Disable volatile uint32_t CH3: 1; // Channel 4 Alternate Disable volatile uint32_t CH4: 1; // Channel 5 Alternate Disable volatile uint32_t CH5: 1; // Channel 6 Alternate Disable volatile uint32_t CH6: 1; // Channel 7 Alternate Disable volatile uint32_t CH7: 1; // Channel 8 Alternate Disable volatile uint32_t CH8: 1; // Channel 9 Alternate Disable volatile uint32_t CH9: 1; // Channel 10 Alternate Disable volatile uint32_t CH10: 1; // Channel 11 Alternate Disable volatile uint32_t CH11: 1; // Channel 12 Alternate Disable volatile uint32_t CH12: 1; // Channel 13 Alternate Disable volatile uint32_t CH13: 1; // Channel 14 Alternate Disable volatile uint32_t CH14: 1; // Channel 15 Alternate Disable volatile uint32_t CH15: 1; // Channel 16 Alternate Disable volatile uint32_t CH16: 1; // Channel 17 Alternate Disable volatile uint32_t CH17: 1; // Channel 18 Alternate Disable volatile uint32_t CH18: 1; // Channel 19 Alternate Disable volatile uint32_t CH19: 1; // Channel 20 Alternate Disable volatile uint32_t CH20: 1; // Channel 21 Alternate Disable volatile uint32_t CH21: 1; // Channel 22 Alternate Disable volatile uint32_t CH22: 1; // Channel 23 Alternate Disable volatile uint32_t CH23: 1; // Channel 24 Alternate Disable volatile uint32_t CH24: 1; // Channel 25 Alternate Disable volatile uint32_t CH25: 1; // Channel 26 Alternate Disable volatile uint32_t CH26: 1; // Channel 27 Alternate Disable volatile uint32_t CH27: 1; // Channel 28 Alternate Disable volatile uint32_t CH28: 1; // Channel 29 Alternate Disable volatile uint32_t CH29: 1; // Channel 30 Alternate Disable volatile uint32_t CH30: 1; // Channel 31 Alternate Disable volatile uint32_t CH31: 1; }; volatile uint32_t U32; }; }; #define SI32_DMACTRL_A_CHALTCLR_CH0_MASK 0x00000001 #define SI32_DMACTRL_A_CHALTCLR_CH0_SHIFT 0 // Use the primary data structure for DMA Channel 0. #define SI32_DMACTRL_A_CHALTCLR_CH0_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTCLR_CH0_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH0_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH0_SHIFT) #define SI32_DMACTRL_A_CHALTCLR_CH1_MASK 0x00000002 #define SI32_DMACTRL_A_CHALTCLR_CH1_SHIFT 1 // Use the primary data structure for DMA Channel 1. #define SI32_DMACTRL_A_CHALTCLR_CH1_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTCLR_CH1_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH1_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH1_SHIFT) #define SI32_DMACTRL_A_CHALTCLR_CH2_MASK 0x00000004 #define SI32_DMACTRL_A_CHALTCLR_CH2_SHIFT 2 // Use the primary data structure for DMA Channel 2. #define SI32_DMACTRL_A_CHALTCLR_CH2_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTCLR_CH2_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH2_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH2_SHIFT) #define SI32_DMACTRL_A_CHALTCLR_CH3_MASK 0x00000008 #define SI32_DMACTRL_A_CHALTCLR_CH3_SHIFT 3 // Use the primary data structure for DMA Channel 3. #define SI32_DMACTRL_A_CHALTCLR_CH3_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTCLR_CH3_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH3_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH3_SHIFT) #define SI32_DMACTRL_A_CHALTCLR_CH4_MASK 0x00000010 #define SI32_DMACTRL_A_CHALTCLR_CH4_SHIFT 4 // Use the primary data structure for DMA Channel 4. #define SI32_DMACTRL_A_CHALTCLR_CH4_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTCLR_CH4_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH4_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH4_SHIFT) #define SI32_DMACTRL_A_CHALTCLR_CH5_MASK 0x00000020 #define SI32_DMACTRL_A_CHALTCLR_CH5_SHIFT 5 // Use the primary data structure for DMA Channel 5. #define SI32_DMACTRL_A_CHALTCLR_CH5_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTCLR_CH5_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH5_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH5_SHIFT) #define SI32_DMACTRL_A_CHALTCLR_CH6_MASK 0x00000040 #define SI32_DMACTRL_A_CHALTCLR_CH6_SHIFT 6 // Use the primary data structure for DMA Channel 6. #define SI32_DMACTRL_A_CHALTCLR_CH6_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTCLR_CH6_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH6_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH6_SHIFT) #define SI32_DMACTRL_A_CHALTCLR_CH7_MASK 0x00000080 #define SI32_DMACTRL_A_CHALTCLR_CH7_SHIFT 7 // Use the primary data structure for DMA Channel 7. #define SI32_DMACTRL_A_CHALTCLR_CH7_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTCLR_CH7_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH7_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH7_SHIFT) #define SI32_DMACTRL_A_CHALTCLR_CH8_MASK 0x00000100 #define SI32_DMACTRL_A_CHALTCLR_CH8_SHIFT 8 // Use the primary data structure for DMA Channel 8. #define SI32_DMACTRL_A_CHALTCLR_CH8_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTCLR_CH8_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH8_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH8_SHIFT) #define SI32_DMACTRL_A_CHALTCLR_CH9_MASK 0x00000200 #define SI32_DMACTRL_A_CHALTCLR_CH9_SHIFT 9 // Use the primary data structure for DMA Channel 9. #define SI32_DMACTRL_A_CHALTCLR_CH9_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTCLR_CH9_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH9_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH9_SHIFT) #define SI32_DMACTRL_A_CHALTCLR_CH10_MASK 0x00000400 #define SI32_DMACTRL_A_CHALTCLR_CH10_SHIFT 10 // Use the primary data structure for DMA Channel 10. #define SI32_DMACTRL_A_CHALTCLR_CH10_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTCLR_CH10_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH10_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH10_SHIFT) #define SI32_DMACTRL_A_CHALTCLR_CH11_MASK 0x00000800 #define SI32_DMACTRL_A_CHALTCLR_CH11_SHIFT 11 // Use the primary data structure for DMA Channel 11. #define SI32_DMACTRL_A_CHALTCLR_CH11_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTCLR_CH11_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH11_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH11_SHIFT) #define SI32_DMACTRL_A_CHALTCLR_CH12_MASK 0x00001000 #define SI32_DMACTRL_A_CHALTCLR_CH12_SHIFT 12 // Use the primary data structure for DMA Channel 12. #define SI32_DMACTRL_A_CHALTCLR_CH12_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTCLR_CH12_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH12_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH12_SHIFT) #define SI32_DMACTRL_A_CHALTCLR_CH13_MASK 0x00002000 #define SI32_DMACTRL_A_CHALTCLR_CH13_SHIFT 13 // Use the primary data structure for DMA Channel 13. #define SI32_DMACTRL_A_CHALTCLR_CH13_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTCLR_CH13_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH13_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH13_SHIFT) #define SI32_DMACTRL_A_CHALTCLR_CH14_MASK 0x00004000 #define SI32_DMACTRL_A_CHALTCLR_CH14_SHIFT 14 // Use the primary data structure for DMA Channel 14. #define SI32_DMACTRL_A_CHALTCLR_CH14_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTCLR_CH14_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH14_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH14_SHIFT) #define SI32_DMACTRL_A_CHALTCLR_CH15_MASK 0x00008000 #define SI32_DMACTRL_A_CHALTCLR_CH15_SHIFT 15 // Use the primary data structure for DMA Channel 15. #define SI32_DMACTRL_A_CHALTCLR_CH15_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTCLR_CH15_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH15_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH15_SHIFT) #define SI32_DMACTRL_A_CHALTCLR_CH16_MASK 0x00010000 #define SI32_DMACTRL_A_CHALTCLR_CH16_SHIFT 16 // Use the primary data structure for DMA Channel 16. #define SI32_DMACTRL_A_CHALTCLR_CH16_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTCLR_CH16_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH16_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH16_SHIFT) #define SI32_DMACTRL_A_CHALTCLR_CH17_MASK 0x00020000 #define SI32_DMACTRL_A_CHALTCLR_CH17_SHIFT 17 // Use the primary data structure for DMA Channel 17. #define SI32_DMACTRL_A_CHALTCLR_CH17_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTCLR_CH17_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH17_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH17_SHIFT) #define SI32_DMACTRL_A_CHALTCLR_CH18_MASK 0x00040000 #define SI32_DMACTRL_A_CHALTCLR_CH18_SHIFT 18 // Use the primary data structure for DMA Channel 18. #define SI32_DMACTRL_A_CHALTCLR_CH18_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTCLR_CH18_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH18_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH18_SHIFT) #define SI32_DMACTRL_A_CHALTCLR_CH19_MASK 0x00080000 #define SI32_DMACTRL_A_CHALTCLR_CH19_SHIFT 19 // Use the primary data structure for DMA Channel 19. #define SI32_DMACTRL_A_CHALTCLR_CH19_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTCLR_CH19_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH19_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH19_SHIFT) #define SI32_DMACTRL_A_CHALTCLR_CH20_MASK 0x00100000 #define SI32_DMACTRL_A_CHALTCLR_CH20_SHIFT 20 // Use the primary data structure for DMA Channel 20. #define SI32_DMACTRL_A_CHALTCLR_CH20_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTCLR_CH20_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH20_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH20_SHIFT) #define SI32_DMACTRL_A_CHALTCLR_CH21_MASK 0x00200000 #define SI32_DMACTRL_A_CHALTCLR_CH21_SHIFT 21 // Use the primary data structure for DMA Channel 21. #define SI32_DMACTRL_A_CHALTCLR_CH21_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTCLR_CH21_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH21_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH21_SHIFT) #define SI32_DMACTRL_A_CHALTCLR_CH22_MASK 0x00400000 #define SI32_DMACTRL_A_CHALTCLR_CH22_SHIFT 22 // Use the primary data structure for DMA Channel 22. #define SI32_DMACTRL_A_CHALTCLR_CH22_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTCLR_CH22_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH22_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH22_SHIFT) #define SI32_DMACTRL_A_CHALTCLR_CH23_MASK 0x00800000 #define SI32_DMACTRL_A_CHALTCLR_CH23_SHIFT 23 // Use the primary data structure for DMA Channel 23. #define SI32_DMACTRL_A_CHALTCLR_CH23_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTCLR_CH23_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH23_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH23_SHIFT) #define SI32_DMACTRL_A_CHALTCLR_CH24_MASK 0x01000000 #define SI32_DMACTRL_A_CHALTCLR_CH24_SHIFT 24 // Use the primary data structure for DMA Channel 24. #define SI32_DMACTRL_A_CHALTCLR_CH24_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTCLR_CH24_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH24_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH24_SHIFT) #define SI32_DMACTRL_A_CHALTCLR_CH25_MASK 0x02000000 #define SI32_DMACTRL_A_CHALTCLR_CH25_SHIFT 25 // Use the primary data structure for DMA Channel 25. #define SI32_DMACTRL_A_CHALTCLR_CH25_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTCLR_CH25_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH25_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH25_SHIFT) #define SI32_DMACTRL_A_CHALTCLR_CH26_MASK 0x04000000 #define SI32_DMACTRL_A_CHALTCLR_CH26_SHIFT 26 // Use the primary data structure for DMA Channel 26. #define SI32_DMACTRL_A_CHALTCLR_CH26_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTCLR_CH26_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH26_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH26_SHIFT) #define SI32_DMACTRL_A_CHALTCLR_CH27_MASK 0x08000000 #define SI32_DMACTRL_A_CHALTCLR_CH27_SHIFT 27 // Use the primary data structure for DMA Channel 27. #define SI32_DMACTRL_A_CHALTCLR_CH27_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTCLR_CH27_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH27_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH27_SHIFT) #define SI32_DMACTRL_A_CHALTCLR_CH28_MASK 0x10000000 #define SI32_DMACTRL_A_CHALTCLR_CH28_SHIFT 28 // Use the primary data structure for DMA Channel 28. #define SI32_DMACTRL_A_CHALTCLR_CH28_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTCLR_CH28_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH28_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH28_SHIFT) #define SI32_DMACTRL_A_CHALTCLR_CH29_MASK 0x20000000 #define SI32_DMACTRL_A_CHALTCLR_CH29_SHIFT 29 // Use the primary data structure for DMA Channel 29. #define SI32_DMACTRL_A_CHALTCLR_CH29_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTCLR_CH29_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH29_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH29_SHIFT) #define SI32_DMACTRL_A_CHALTCLR_CH30_MASK 0x40000000 #define SI32_DMACTRL_A_CHALTCLR_CH30_SHIFT 30 // Use the primary data structure for DMA Channel 30. #define SI32_DMACTRL_A_CHALTCLR_CH30_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHALTCLR_CH30_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH30_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH30_SHIFT) #define SI32_DMACTRL_A_CHALTCLR_CH31_MASK 0x80000000 #define SI32_DMACTRL_A_CHALTCLR_CH31_SHIFT 31 // Use the primary data structure for DMA Channel 31. #define SI32_DMACTRL_A_CHALTCLR_CH31_DISABLED_VALUE 1U #define SI32_DMACTRL_A_CHALTCLR_CH31_DISABLED_U32 \ (SI32_DMACTRL_A_CHALTCLR_CH31_DISABLED_VALUE << SI32_DMACTRL_A_CHALTCLR_CH31_SHIFT) struct SI32_DMACTRL_A_CHHPSET_Struct { union { struct { // Channel 0 High Priority Enable volatile uint32_t CH0: 1; // Channel 1 High Priority Enable volatile uint32_t CH1: 1; // Channel 2 High Priority Enable volatile uint32_t CH2: 1; // Channel 3 High Priority Enable volatile uint32_t CH3: 1; // Channel 4 High Priority Enable volatile uint32_t CH4: 1; // Channel 5 High Priority Enable volatile uint32_t CH5: 1; // Channel 6 High Priority Enable volatile uint32_t CH6: 1; // Channel 7 High Priority Enable volatile uint32_t CH7: 1; // Channel 8 High Priority Enable volatile uint32_t CH8: 1; // Channel 9 High Priority Enable volatile uint32_t CH9: 1; // Channel 10 High Priority Enable volatile uint32_t CH10: 1; // Channel 11 High Priority Enable volatile uint32_t CH11: 1; // Channel 12 High Priority Enable volatile uint32_t CH12: 1; // Channel 13 High Priority Enable volatile uint32_t CH13: 1; // Channel 14 High Priority Enable volatile uint32_t CH14: 1; // Channel 15 High Priority Enable volatile uint32_t CH15: 1; // Channel 16 High Priority Enable volatile uint32_t CH16: 1; // Channel 17 High Priority Enable volatile uint32_t CH17: 1; // Channel 18 High Priority Enable volatile uint32_t CH18: 1; // Channel 19 High Priority Enable volatile uint32_t CH19: 1; // Channel 20 High Priority Enable volatile uint32_t CH20: 1; // Channel 21 High Priority Enable volatile uint32_t CH21: 1; // Channel 22 High Priority Enable volatile uint32_t CH22: 1; // Channel 23 High Priority Enable volatile uint32_t CH23: 1; // Channel 24 High Priority Enable volatile uint32_t CH24: 1; // Channel 25 High Priority Enable volatile uint32_t CH25: 1; // Channel 26 High Priority Enable volatile uint32_t CH26: 1; // Channel 27 High Priority Enable volatile uint32_t CH27: 1; // Channel 28 High Priority Enable volatile uint32_t CH28: 1; // Channel 29 High Priority Enable volatile uint32_t CH29: 1; // Channel 30 High Priority Enable volatile uint32_t CH30: 1; // Channel 31 High Priority Enable volatile uint32_t CH31: 1; }; volatile uint32_t U32; }; }; #define SI32_DMACTRL_A_CHHPSET_CH0_MASK 0x00000001 #define SI32_DMACTRL_A_CHHPSET_CH0_SHIFT 0 // Read: 0: DMA Channel 0 is using the default priority level. 1: DMA Channel 0 is // using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 0. #define SI32_DMACTRL_A_CHHPSET_CH0_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPSET_CH0_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH0_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH0_SHIFT) #define SI32_DMACTRL_A_CHHPSET_CH1_MASK 0x00000002 #define SI32_DMACTRL_A_CHHPSET_CH1_SHIFT 1 // Read: 0: DMA Channel 1 is using the default priority level. 1: DMA Channel 1 is // using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 1. #define SI32_DMACTRL_A_CHHPSET_CH1_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPSET_CH1_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH1_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH1_SHIFT) #define SI32_DMACTRL_A_CHHPSET_CH2_MASK 0x00000004 #define SI32_DMACTRL_A_CHHPSET_CH2_SHIFT 2 // Read: 0: DMA Channel 2 is using the default priority level. 1: DMA Channel 2 is // using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 2. #define SI32_DMACTRL_A_CHHPSET_CH2_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPSET_CH2_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH2_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH2_SHIFT) #define SI32_DMACTRL_A_CHHPSET_CH3_MASK 0x00000008 #define SI32_DMACTRL_A_CHHPSET_CH3_SHIFT 3 // Read: 0: DMA Channel 3 is using the default priority level. 1: DMA Channel 3 is // using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 3. #define SI32_DMACTRL_A_CHHPSET_CH3_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPSET_CH3_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH3_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH3_SHIFT) #define SI32_DMACTRL_A_CHHPSET_CH4_MASK 0x00000010 #define SI32_DMACTRL_A_CHHPSET_CH4_SHIFT 4 // Read: 0: DMA Channel 4 is using the default priority level. 1: DMA Channel 4 is // using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 4. #define SI32_DMACTRL_A_CHHPSET_CH4_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPSET_CH4_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH4_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH4_SHIFT) #define SI32_DMACTRL_A_CHHPSET_CH5_MASK 0x00000020 #define SI32_DMACTRL_A_CHHPSET_CH5_SHIFT 5 // Read: 0: DMA Channel 5 is using the default priority level. 1: DMA Channel 5 is // using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 5. #define SI32_DMACTRL_A_CHHPSET_CH5_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPSET_CH5_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH5_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH5_SHIFT) #define SI32_DMACTRL_A_CHHPSET_CH6_MASK 0x00000040 #define SI32_DMACTRL_A_CHHPSET_CH6_SHIFT 6 // Read: 0: DMA Channel 6 is using the default priority level. 1: DMA Channel 6 is // using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 6. #define SI32_DMACTRL_A_CHHPSET_CH6_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPSET_CH6_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH6_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH6_SHIFT) #define SI32_DMACTRL_A_CHHPSET_CH7_MASK 0x00000080 #define SI32_DMACTRL_A_CHHPSET_CH7_SHIFT 7 // Read: 0: DMA Channel 7 is using the default priority level. 1: DMA Channel 7 is // using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 7. #define SI32_DMACTRL_A_CHHPSET_CH7_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPSET_CH7_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH7_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH7_SHIFT) #define SI32_DMACTRL_A_CHHPSET_CH8_MASK 0x00000100 #define SI32_DMACTRL_A_CHHPSET_CH8_SHIFT 8 // Read: 0: DMA Channel 8 is using the default priority level. 1: DMA Channel 8 is // using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 8. #define SI32_DMACTRL_A_CHHPSET_CH8_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPSET_CH8_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH8_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH8_SHIFT) #define SI32_DMACTRL_A_CHHPSET_CH9_MASK 0x00000200 #define SI32_DMACTRL_A_CHHPSET_CH9_SHIFT 9 // Read: 0: DMA Channel 9 is using the default priority level. 1: DMA Channel 9 is // using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 9. #define SI32_DMACTRL_A_CHHPSET_CH9_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPSET_CH9_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH9_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH9_SHIFT) #define SI32_DMACTRL_A_CHHPSET_CH10_MASK 0x00000400 #define SI32_DMACTRL_A_CHHPSET_CH10_SHIFT 10 // Read: 0: DMA Channel 10 is using the default priority level. 1: DMA Channel 10 // is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 10. #define SI32_DMACTRL_A_CHHPSET_CH10_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPSET_CH10_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH10_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH10_SHIFT) #define SI32_DMACTRL_A_CHHPSET_CH11_MASK 0x00000800 #define SI32_DMACTRL_A_CHHPSET_CH11_SHIFT 11 // Read: 0: DMA Channel 11 is using the default priority level. 1: DMA Channel 11 // is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 11. #define SI32_DMACTRL_A_CHHPSET_CH11_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPSET_CH11_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH11_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH11_SHIFT) #define SI32_DMACTRL_A_CHHPSET_CH12_MASK 0x00001000 #define SI32_DMACTRL_A_CHHPSET_CH12_SHIFT 12 // Read: 0: DMA Channel 12 is using the default priority level. 1: DMA Channel 12 // is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 12. #define SI32_DMACTRL_A_CHHPSET_CH12_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPSET_CH12_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH12_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH12_SHIFT) #define SI32_DMACTRL_A_CHHPSET_CH13_MASK 0x00002000 #define SI32_DMACTRL_A_CHHPSET_CH13_SHIFT 13 // Read: 0: DMA Channel 13 is using the default priority level. 1: DMA Channel 13 // is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 13. #define SI32_DMACTRL_A_CHHPSET_CH13_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPSET_CH13_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH13_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH13_SHIFT) #define SI32_DMACTRL_A_CHHPSET_CH14_MASK 0x00004000 #define SI32_DMACTRL_A_CHHPSET_CH14_SHIFT 14 // Read: 0: DMA Channel 14 is using the default priority level. 1: DMA Channel 14 // is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 14. #define SI32_DMACTRL_A_CHHPSET_CH14_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPSET_CH14_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH14_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH14_SHIFT) #define SI32_DMACTRL_A_CHHPSET_CH15_MASK 0x00008000 #define SI32_DMACTRL_A_CHHPSET_CH15_SHIFT 15 // Read: 0: DMA Channel 15 is using the default priority level. 1: DMA Channel 15 // is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 15. #define SI32_DMACTRL_A_CHHPSET_CH15_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPSET_CH15_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH15_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH15_SHIFT) #define SI32_DMACTRL_A_CHHPSET_CH16_MASK 0x00010000 #define SI32_DMACTRL_A_CHHPSET_CH16_SHIFT 16 // Read: 0: DMA Channel 16 is using the default priority level. 1: DMA Channel 16 // is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 16. #define SI32_DMACTRL_A_CHHPSET_CH16_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPSET_CH16_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH16_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH16_SHIFT) #define SI32_DMACTRL_A_CHHPSET_CH17_MASK 0x00020000 #define SI32_DMACTRL_A_CHHPSET_CH17_SHIFT 17 // Read: 0: DMA Channel 17 is using the default priority level. 1: DMA Channel 17 // is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 17. #define SI32_DMACTRL_A_CHHPSET_CH17_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPSET_CH17_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH17_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH17_SHIFT) #define SI32_DMACTRL_A_CHHPSET_CH18_MASK 0x00040000 #define SI32_DMACTRL_A_CHHPSET_CH18_SHIFT 18 // Read: 0: DMA Channel 18 is using the default priority level. 1: DMA Channel 18 // is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 18. #define SI32_DMACTRL_A_CHHPSET_CH18_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPSET_CH18_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH18_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH18_SHIFT) #define SI32_DMACTRL_A_CHHPSET_CH19_MASK 0x00080000 #define SI32_DMACTRL_A_CHHPSET_CH19_SHIFT 19 // Read: 0: DMA Channel 19 is using the default priority level. 1: DMA Channel 19 // is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 19. #define SI32_DMACTRL_A_CHHPSET_CH19_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPSET_CH19_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH19_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH19_SHIFT) #define SI32_DMACTRL_A_CHHPSET_CH20_MASK 0x00100000 #define SI32_DMACTRL_A_CHHPSET_CH20_SHIFT 20 // Read: 0: DMA Channel 20 is using the default priority level. 1: DMA Channel 20 // is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 20. #define SI32_DMACTRL_A_CHHPSET_CH20_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPSET_CH20_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH20_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH20_SHIFT) #define SI32_DMACTRL_A_CHHPSET_CH21_MASK 0x00200000 #define SI32_DMACTRL_A_CHHPSET_CH21_SHIFT 21 // Read: 0: DMA Channel 21 is using the default priority level. 1: DMA Channel 21 // is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 21. #define SI32_DMACTRL_A_CHHPSET_CH21_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPSET_CH21_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH21_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH21_SHIFT) #define SI32_DMACTRL_A_CHHPSET_CH22_MASK 0x00400000 #define SI32_DMACTRL_A_CHHPSET_CH22_SHIFT 22 // Read: 0: DMA Channel 22 is using the default priority level. 1: DMA Channel 22 // is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 22. #define SI32_DMACTRL_A_CHHPSET_CH22_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPSET_CH22_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH22_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH22_SHIFT) #define SI32_DMACTRL_A_CHHPSET_CH23_MASK 0x00800000 #define SI32_DMACTRL_A_CHHPSET_CH23_SHIFT 23 // Read: 0: DMA Channel 23 is using the default priority level. 1: DMA Channel 23 // is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 23. #define SI32_DMACTRL_A_CHHPSET_CH23_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPSET_CH23_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH23_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH23_SHIFT) #define SI32_DMACTRL_A_CHHPSET_CH24_MASK 0x01000000 #define SI32_DMACTRL_A_CHHPSET_CH24_SHIFT 24 // Read: 0: DMA Channel 24 is using the default priority level. 1: DMA Channel 24 // is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 24. #define SI32_DMACTRL_A_CHHPSET_CH24_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPSET_CH24_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH24_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH24_SHIFT) #define SI32_DMACTRL_A_CHHPSET_CH25_MASK 0x02000000 #define SI32_DMACTRL_A_CHHPSET_CH25_SHIFT 25 // Read: 0: DMA Channel 25 is using the default priority level. 1: DMA Channel 25 // is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 25. #define SI32_DMACTRL_A_CHHPSET_CH25_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPSET_CH25_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH25_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH25_SHIFT) #define SI32_DMACTRL_A_CHHPSET_CH26_MASK 0x04000000 #define SI32_DMACTRL_A_CHHPSET_CH26_SHIFT 26 // Read: 0: DMA Channel 26 is using the default priority level. 1: DMA Channel 26 // is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 26. #define SI32_DMACTRL_A_CHHPSET_CH26_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPSET_CH26_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH26_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH26_SHIFT) #define SI32_DMACTRL_A_CHHPSET_CH27_MASK 0x08000000 #define SI32_DMACTRL_A_CHHPSET_CH27_SHIFT 27 // Read: 0: DMA Channel 27 is using the default priority level. 1: DMA Channel 27 // is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 27. #define SI32_DMACTRL_A_CHHPSET_CH27_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPSET_CH27_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH27_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH27_SHIFT) #define SI32_DMACTRL_A_CHHPSET_CH28_MASK 0x10000000 #define SI32_DMACTRL_A_CHHPSET_CH28_SHIFT 28 // Read: 0: DMA Channel 28 is using the default priority level. 1: DMA Channel 28 // is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 28. #define SI32_DMACTRL_A_CHHPSET_CH28_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPSET_CH28_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH28_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH28_SHIFT) #define SI32_DMACTRL_A_CHHPSET_CH29_MASK 0x20000000 #define SI32_DMACTRL_A_CHHPSET_CH29_SHIFT 29 // Read: 0: DMA Channel 29 is using the default priority level. 1: DMA Channel 29 // is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 29. #define SI32_DMACTRL_A_CHHPSET_CH29_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPSET_CH29_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH29_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH29_SHIFT) #define SI32_DMACTRL_A_CHHPSET_CH30_MASK 0x40000000 #define SI32_DMACTRL_A_CHHPSET_CH30_SHIFT 30 // Read: 0: DMA Channel 30 is using the default priority level. 1: DMA Channel 30 // is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 30. #define SI32_DMACTRL_A_CHHPSET_CH30_ENABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPSET_CH30_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH30_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH30_SHIFT) #define SI32_DMACTRL_A_CHHPSET_CH31_MASK 0x80000000 #define SI32_DMACTRL_A_CHHPSET_CH31_SHIFT 31 // Read: 0: DMA Channel 31 is using the default priority level. 1: DMA Channel 31 // is using the high priority level. Write: 0: No effect (use CHHPCLR to clear). 1: // Use the high priority level for DMA Channel 31. #define SI32_DMACTRL_A_CHHPSET_CH31_ENABLED_VALUE 1U #define SI32_DMACTRL_A_CHHPSET_CH31_ENABLED_U32 \ (SI32_DMACTRL_A_CHHPSET_CH31_ENABLED_VALUE << SI32_DMACTRL_A_CHHPSET_CH31_SHIFT) struct SI32_DMACTRL_A_CHHPCLR_Struct { union { struct { // Channel 0 High Priority Disable volatile uint32_t CH0: 1; // Channel 1 High Priority Disable volatile uint32_t CH1: 1; // Channel 2 High Priority Disable volatile uint32_t CH2: 1; // Channel 3 High Priority Disable volatile uint32_t CH3: 1; // Channel 4 High Priority Disable volatile uint32_t CH4: 1; // Channel 5 High Priority Disable volatile uint32_t CH5: 1; // Channel 6 High Priority Disable volatile uint32_t CH6: 1; // Channel 7 High Priority Disable volatile uint32_t CH7: 1; // Channel 8 High Priority Disable volatile uint32_t CH8: 1; // Channel 9 High Priority Disable volatile uint32_t CH9: 1; // Channel 10 High Priority Disable volatile uint32_t CH10: 1; // Channel 11 High Priority Disable volatile uint32_t CH11: 1; // Channel 12 High Priority Disable volatile uint32_t CH12: 1; // Channel 13 High Priority Disable volatile uint32_t CH13: 1; // Channel 14 High Priority Disable volatile uint32_t CH14: 1; // Channel 15 High Priority Disable volatile uint32_t CH15: 1; // Channel 16 High Priority Disable volatile uint32_t CH16: 1; // Channel 17 High Priority Disable volatile uint32_t CH17: 1; // Channel 18 High Priority Disable volatile uint32_t CH18: 1; // Channel 19 High Priority Disable volatile uint32_t CH19: 1; // Channel 20 High Priority Disable volatile uint32_t CH20: 1; // Channel 21 High Priority Disable volatile uint32_t CH21: 1; // Channel 22 High Priority Disable volatile uint32_t CH22: 1; // Channel 23 High Priority Disable volatile uint32_t CH23: 1; // Channel 24 High Priority Disable volatile uint32_t CH24: 1; // Channel 25 High Priority Disable volatile uint32_t CH25: 1; // Channel 26 High Priority Disable volatile uint32_t CH26: 1; // Channel 27 High Priority Disable volatile uint32_t CH27: 1; // Channel 28 High Priority Disable volatile uint32_t CH28: 1; // Channel 29 High Priority Disable volatile uint32_t CH29: 1; // Channel 30 High Priority Disable volatile uint32_t CH30: 1; // Channel 31 High Priority Disable volatile uint32_t CH31: 1; }; volatile uint32_t U32; }; }; #define SI32_DMACTRL_A_CHHPCLR_CH0_MASK 0x00000001 #define SI32_DMACTRL_A_CHHPCLR_CH0_SHIFT 0 // Use the high default level for DMA Channel 0. #define SI32_DMACTRL_A_CHHPCLR_CH0_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPCLR_CH0_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH0_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH0_SHIFT) #define SI32_DMACTRL_A_CHHPCLR_CH1_MASK 0x00000002 #define SI32_DMACTRL_A_CHHPCLR_CH1_SHIFT 1 // Use the high default level for DMA Channel 1. #define SI32_DMACTRL_A_CHHPCLR_CH1_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPCLR_CH1_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH1_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH1_SHIFT) #define SI32_DMACTRL_A_CHHPCLR_CH2_MASK 0x00000004 #define SI32_DMACTRL_A_CHHPCLR_CH2_SHIFT 2 // Use the high default level for DMA Channel 2. #define SI32_DMACTRL_A_CHHPCLR_CH2_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPCLR_CH2_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH2_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH2_SHIFT) #define SI32_DMACTRL_A_CHHPCLR_CH3_MASK 0x00000008 #define SI32_DMACTRL_A_CHHPCLR_CH3_SHIFT 3 // Use the high default level for DMA Channel 3. #define SI32_DMACTRL_A_CHHPCLR_CH3_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPCLR_CH3_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH3_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH3_SHIFT) #define SI32_DMACTRL_A_CHHPCLR_CH4_MASK 0x00000010 #define SI32_DMACTRL_A_CHHPCLR_CH4_SHIFT 4 // Use the high default level for DMA Channel 4. #define SI32_DMACTRL_A_CHHPCLR_CH4_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPCLR_CH4_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH4_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH4_SHIFT) #define SI32_DMACTRL_A_CHHPCLR_CH5_MASK 0x00000020 #define SI32_DMACTRL_A_CHHPCLR_CH5_SHIFT 5 // Use the high default level for DMA Channel 5. #define SI32_DMACTRL_A_CHHPCLR_CH5_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPCLR_CH5_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH5_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH5_SHIFT) #define SI32_DMACTRL_A_CHHPCLR_CH6_MASK 0x00000040 #define SI32_DMACTRL_A_CHHPCLR_CH6_SHIFT 6 // Use the high default level for DMA Channel 6. #define SI32_DMACTRL_A_CHHPCLR_CH6_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPCLR_CH6_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH6_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH6_SHIFT) #define SI32_DMACTRL_A_CHHPCLR_CH7_MASK 0x00000080 #define SI32_DMACTRL_A_CHHPCLR_CH7_SHIFT 7 // Use the high default level for DMA Channel 7. #define SI32_DMACTRL_A_CHHPCLR_CH7_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPCLR_CH7_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH7_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH7_SHIFT) #define SI32_DMACTRL_A_CHHPCLR_CH8_MASK 0x00000100 #define SI32_DMACTRL_A_CHHPCLR_CH8_SHIFT 8 // Use the high default level for DMA Channel 8. #define SI32_DMACTRL_A_CHHPCLR_CH8_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPCLR_CH8_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH8_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH8_SHIFT) #define SI32_DMACTRL_A_CHHPCLR_CH9_MASK 0x00000200 #define SI32_DMACTRL_A_CHHPCLR_CH9_SHIFT 9 // Use the high default level for DMA Channel 9. #define SI32_DMACTRL_A_CHHPCLR_CH9_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPCLR_CH9_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH9_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH9_SHIFT) #define SI32_DMACTRL_A_CHHPCLR_CH10_MASK 0x00000400 #define SI32_DMACTRL_A_CHHPCLR_CH10_SHIFT 10 // Use the high default level for DMA Channel 10. #define SI32_DMACTRL_A_CHHPCLR_CH10_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPCLR_CH10_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH10_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH10_SHIFT) #define SI32_DMACTRL_A_CHHPCLR_CH11_MASK 0x00000800 #define SI32_DMACTRL_A_CHHPCLR_CH11_SHIFT 11 // Use the high default level for DMA Channel 11. #define SI32_DMACTRL_A_CHHPCLR_CH11_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPCLR_CH11_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH11_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH11_SHIFT) #define SI32_DMACTRL_A_CHHPCLR_CH12_MASK 0x00001000 #define SI32_DMACTRL_A_CHHPCLR_CH12_SHIFT 12 // Use the high default level for DMA Channel 12. #define SI32_DMACTRL_A_CHHPCLR_CH12_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPCLR_CH12_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH12_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH12_SHIFT) #define SI32_DMACTRL_A_CHHPCLR_CH13_MASK 0x00002000 #define SI32_DMACTRL_A_CHHPCLR_CH13_SHIFT 13 // Use the high default level for DMA Channel 13. #define SI32_DMACTRL_A_CHHPCLR_CH13_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPCLR_CH13_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH13_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH13_SHIFT) #define SI32_DMACTRL_A_CHHPCLR_CH14_MASK 0x00004000 #define SI32_DMACTRL_A_CHHPCLR_CH14_SHIFT 14 // Use the high default level for DMA Channel 14. #define SI32_DMACTRL_A_CHHPCLR_CH14_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPCLR_CH14_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH14_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH14_SHIFT) #define SI32_DMACTRL_A_CHHPCLR_CH15_MASK 0x00008000 #define SI32_DMACTRL_A_CHHPCLR_CH15_SHIFT 15 // Use the high default level for DMA Channel 15. #define SI32_DMACTRL_A_CHHPCLR_CH15_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPCLR_CH15_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH15_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH15_SHIFT) #define SI32_DMACTRL_A_CHHPCLR_CH16_MASK 0x00010000 #define SI32_DMACTRL_A_CHHPCLR_CH16_SHIFT 16 // Use the high default level for DMA Channel 16. #define SI32_DMACTRL_A_CHHPCLR_CH16_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPCLR_CH16_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH16_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH16_SHIFT) #define SI32_DMACTRL_A_CHHPCLR_CH17_MASK 0x00020000 #define SI32_DMACTRL_A_CHHPCLR_CH17_SHIFT 17 // Use the high default level for DMA Channel 17. #define SI32_DMACTRL_A_CHHPCLR_CH17_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPCLR_CH17_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH17_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH17_SHIFT) #define SI32_DMACTRL_A_CHHPCLR_CH18_MASK 0x00040000 #define SI32_DMACTRL_A_CHHPCLR_CH18_SHIFT 18 // Use the high default level for DMA Channel 18. #define SI32_DMACTRL_A_CHHPCLR_CH18_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPCLR_CH18_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH18_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH18_SHIFT) #define SI32_DMACTRL_A_CHHPCLR_CH19_MASK 0x00080000 #define SI32_DMACTRL_A_CHHPCLR_CH19_SHIFT 19 // Use the high default level for DMA Channel 19. #define SI32_DMACTRL_A_CHHPCLR_CH19_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPCLR_CH19_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH19_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH19_SHIFT) #define SI32_DMACTRL_A_CHHPCLR_CH20_MASK 0x00100000 #define SI32_DMACTRL_A_CHHPCLR_CH20_SHIFT 20 // Use the high default level for DMA Channel 20. #define SI32_DMACTRL_A_CHHPCLR_CH20_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPCLR_CH20_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH20_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH20_SHIFT) #define SI32_DMACTRL_A_CHHPCLR_CH21_MASK 0x00200000 #define SI32_DMACTRL_A_CHHPCLR_CH21_SHIFT 21 // Use the high default level for DMA Channel 21. #define SI32_DMACTRL_A_CHHPCLR_CH21_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPCLR_CH21_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH21_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH21_SHIFT) #define SI32_DMACTRL_A_CHHPCLR_CH22_MASK 0x00400000 #define SI32_DMACTRL_A_CHHPCLR_CH22_SHIFT 22 // Use the high default level for DMA Channel 22. #define SI32_DMACTRL_A_CHHPCLR_CH22_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPCLR_CH22_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH22_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH22_SHIFT) #define SI32_DMACTRL_A_CHHPCLR_CH23_MASK 0x00800000 #define SI32_DMACTRL_A_CHHPCLR_CH23_SHIFT 23 // Use the high default level for DMA Channel 23. #define SI32_DMACTRL_A_CHHPCLR_CH23_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPCLR_CH23_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH23_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH23_SHIFT) #define SI32_DMACTRL_A_CHHPCLR_CH24_MASK 0x01000000 #define SI32_DMACTRL_A_CHHPCLR_CH24_SHIFT 24 // Use the high default level for DMA Channel 24. #define SI32_DMACTRL_A_CHHPCLR_CH24_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPCLR_CH24_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH24_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH24_SHIFT) #define SI32_DMACTRL_A_CHHPCLR_CH25_MASK 0x02000000 #define SI32_DMACTRL_A_CHHPCLR_CH25_SHIFT 25 // Use the high default level for DMA Channel 25. #define SI32_DMACTRL_A_CHHPCLR_CH25_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPCLR_CH25_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH25_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH25_SHIFT) #define SI32_DMACTRL_A_CHHPCLR_CH26_MASK 0x04000000 #define SI32_DMACTRL_A_CHHPCLR_CH26_SHIFT 26 // Use the high default level for DMA Channel 26. #define SI32_DMACTRL_A_CHHPCLR_CH26_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPCLR_CH26_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH26_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH26_SHIFT) #define SI32_DMACTRL_A_CHHPCLR_CH27_MASK 0x08000000 #define SI32_DMACTRL_A_CHHPCLR_CH27_SHIFT 27 // Use the high default level for DMA Channel 27. #define SI32_DMACTRL_A_CHHPCLR_CH27_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPCLR_CH27_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH27_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH27_SHIFT) #define SI32_DMACTRL_A_CHHPCLR_CH28_MASK 0x10000000 #define SI32_DMACTRL_A_CHHPCLR_CH28_SHIFT 28 // Use the high default level for DMA Channel 28. #define SI32_DMACTRL_A_CHHPCLR_CH28_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPCLR_CH28_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH28_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH28_SHIFT) #define SI32_DMACTRL_A_CHHPCLR_CH29_MASK 0x20000000 #define SI32_DMACTRL_A_CHHPCLR_CH29_SHIFT 29 // Use the high default level for DMA Channel 29. #define SI32_DMACTRL_A_CHHPCLR_CH29_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPCLR_CH29_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH29_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH29_SHIFT) #define SI32_DMACTRL_A_CHHPCLR_CH30_MASK 0x40000000 #define SI32_DMACTRL_A_CHHPCLR_CH30_SHIFT 30 // Use the high default level for DMA Channel 30. #define SI32_DMACTRL_A_CHHPCLR_CH30_DISABLED_VALUE 1 #define SI32_DMACTRL_A_CHHPCLR_CH30_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH30_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH30_SHIFT) #define SI32_DMACTRL_A_CHHPCLR_CH31_MASK 0x80000000 #define SI32_DMACTRL_A_CHHPCLR_CH31_SHIFT 31 // Use the high default level for DMA Channel 31. #define SI32_DMACTRL_A_CHHPCLR_CH31_DISABLED_VALUE 1U #define SI32_DMACTRL_A_CHHPCLR_CH31_DISABLED_U32 \ (SI32_DMACTRL_A_CHHPCLR_CH31_DISABLED_VALUE << SI32_DMACTRL_A_CHHPCLR_CH31_SHIFT) struct SI32_DMACTRL_A_BERRCLR_Struct { union { struct { // DMA Bus Error Clear volatile uint32_t ERROR: 1; uint32_t reserved0: 31; }; volatile uint32_t U32; }; }; #define SI32_DMACTRL_A_BERRCLR_ERROR_MASK 0x00000001 #define SI32_DMACTRL_A_BERRCLR_ERROR_SHIFT 0 // Read: 0: DMA error did not occur. 1: DMA error occurred since the last time // ERROR was cleared. Write: 0: No effect. 1: Clear the DMA error flag. #define SI32_DMACTRL_A_BERRCLR_ERROR_CLEAR_VALUE 1 #define SI32_DMACTRL_A_BERRCLR_ERROR_CLEAR_U32 \ (SI32_DMACTRL_A_BERRCLR_ERROR_CLEAR_VALUE << SI32_DMACTRL_A_BERRCLR_ERROR_SHIFT) typedef struct SI32_DMACTRL_A_Struct { struct SI32_DMACTRL_A_STATUS_Struct STATUS ; // Base Address + 0x0 struct SI32_DMACTRL_A_CONFIG_Struct CONFIG ; // Base Address + 0x4 struct SI32_DMACTRL_A_BASEPTR_Struct BASEPTR ; // Base Address + 0x8 struct SI32_DMACTRL_A_ABASEPTR_Struct ABASEPTR ; // Base Address + 0xc struct SI32_DMACTRL_A_CHSTATUS_Struct CHSTATUS ; // Base Address + 0x10 struct SI32_DMACTRL_A_CHSWRCN_Struct CHSWRCN ; // Base Address + 0x14 uint32_t reserved0; uint32_t reserved1; struct SI32_DMACTRL_A_CHREQMSET_Struct CHREQMSET ; // Base Address + 0x20 struct SI32_DMACTRL_A_CHREQMCLR_Struct CHREQMCLR ; // Base Address + 0x24 struct SI32_DMACTRL_A_CHENSET_Struct CHENSET ; // Base Address + 0x28 struct SI32_DMACTRL_A_CHENCLR_Struct CHENCLR ; // Base Address + 0x2c struct SI32_DMACTRL_A_CHALTSET_Struct CHALTSET ; // Base Address + 0x30 struct SI32_DMACTRL_A_CHALTCLR_Struct CHALTCLR ; // Base Address + 0x34 struct SI32_DMACTRL_A_CHHPSET_Struct CHHPSET ; // Base Address + 0x38 struct SI32_DMACTRL_A_CHHPCLR_Struct CHHPCLR ; // Base Address + 0x3c uint32_t reserved2[3]; struct SI32_DMACTRL_A_BERRCLR_Struct BERRCLR ; // Base Address + 0x4c } SI32_DMACTRL_A_Type; #ifdef __cplusplus } #endif #endif // __SI32_DMACTRL_A_REGISTERS_H__ //-eof--------------------------------------------------------------------------