/* * Copyright 1997-2016 Freescale Semiconductor, Inc. * Copyright 2016-2024 NXP * * SPDX-License-Identifier: BSD-3-Clause */ /*! * @file S32Z2_GTM_gtm_cls1.h * @version 2.3 * @date 2024-05-03 * @brief Peripheral Access Layer for S32Z2_GTM_gtm_cls1 * * This file contains register definitions and macros for easy access to their * bit fields. * * This file assumes LITTLE endian system. */ /** * @page misra_violations MISRA-C:2012 violations * * @section [global] * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced * The SoC header defines typedef for all modules. * * @section [global] * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced * The SoC header defines macros for all modules and registers. * * @section [global] * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro * These are generated macros used for accessing the bit-fields from registers. * * @section [global] * Violates MISRA 2012 Required Rule 5.1, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.2, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.4, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.5, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler * This type qualifier is needed to ensure correct I/O access and addressing. */ /* Prevention from multiple including the same memory map */ #if !defined(S32Z2_GTM_gtm_cls1_H_) /* Check if memory map has not been already included */ #define S32Z2_GTM_gtm_cls1_H_ #include "S32Z2_COMMON.h" /* ---------------------------------------------------------------------------- -- GTM_gtm_cls1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup GTM_gtm_cls1_Peripheral_Access_Layer GTM_gtm_cls1 Peripheral Access Layer * @{ */ /** GTM_gtm_cls1 - Size of Registers Arrays */ #define GTM_gtm_cls1_CDTM1_DTM4_CH4_DTV_COUNT 4u #define GTM_gtm_cls1_CDTM1_DTM5_CH4_DTV_COUNT 4u #define GTM_gtm_cls1_MCS1_MEM_COUNT 3072u /** GTM_gtm_cls1 - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[1664]; __IO uint32_t MON_STATUS; /**< MON status register, offset: 0x680 */ __IO uint32_t MON_ACTIVITY_0; /**< MON activity register 0, offset: 0x684 */ uint8_t RESERVED_1[4]; __IO uint32_t MON_ACTIVITY_MCS0; /**< MON activity register for MCS [j], offset: 0x68C */ __IO uint32_t MON_ACTIVITY_MCS1; /**< MON activity register for MCS [j], offset: 0x690 */ __IO uint32_t MON_ACTIVITY_MCS2; /**< MON activity register for MCS [j], offset: 0x694 */ __IO uint32_t MON_ACTIVITY_MCS3; /**< MON activity register for MCS [j], offset: 0x698 */ uint8_t RESERVED_2[36]; __IO uint32_t CMP_EN; /**< CMP comparator enable register, offset: 0x6C0 */ __IO uint32_t CMP_IRQ_NOTIFY; /**< CMP event notification register, offset: 0x6C4 */ __IO uint32_t CMP_IRQ_EN; /**< CMP interrupt enable register, offset: 0x6C8 */ __IO uint32_t CMP_IRQ_FORCINT; /**< CMP interrupt force register, offset: 0x6CC */ __IO uint32_t CMP_IRQ_MODE; /**< CMP interrupt mode configuration register, offset: 0x6D0 */ __IO uint32_t CMP_EIRQ_EN; /**< CMP error interrupt enable register, offset: 0x6D4 */ uint8_t RESERVED_3[296]; __IO uint32_t TIM1_CH0_GPR0; /**< TIM[i] channel [x] general purpose 0 register, offset: 0x800 */ __IO uint32_t TIM1_CH0_GPR1; /**< TIM[i] channel [x] general purpose 0 register, offset: 0x804 */ __I uint32_t TIM1_CH0_CNT; /**< TIM[i] channel [x] SMU counter register, offset: 0x808 */ __I uint32_t TIM1_CH0_ECNT; /**< TIM[i] channel [x] SMU edge counter register, offset: 0x80C */ __IO uint32_t TIM1_CH0_CNTS; /**< TIM[i] channel [x] SMU shadow counter register, offset: 0x810 */ __IO uint32_t TIM1_CH0_TDUC; /**< TIM[i] channel [x] TDU counter register, offset: 0x814 */ __IO uint32_t TIM1_CH0_TDUV; /**< TIM[i] channel [x] TDU control register, offset: 0x818 */ __IO uint32_t TIM1_CH0_FLT_RE; /**< TIM[i] channel [x] filter parameter 0 register, offset: 0x81C */ __IO uint32_t TIM1_CH0_FLT_FE; /**< TIM[i] channel [x] filter parameter 1 register, offset: 0x820 */ __IO uint32_t TIM1_CH0_CTRL; /**< TIM[i] channel [x] control register, offset: 0x824 */ __IO uint32_t TIM1_CH0_ECTRL; /**< TIM[i] channel [x] extended control register, offset: 0x828 */ __IO uint32_t TIM1_CH0_IRQ_NOTIFY; /**< TIM[i] channel [x] interrupt notification register, offset: 0x82C */ __IO uint32_t TIM1_CH0_IRQ_EN; /**< TIM[i] channel [x] interrupt enable register, offset: 0x830 */ __IO uint32_t TIM1_CH0_IRQ_FORCINT; /**< TIM[i] channel [x] force interrupt register, offset: 0x834 */ __IO uint32_t TIM1_CH0_IRQ_MODE; /**< TIM[i] channel [x] interrupt mode configuration register, offset: 0x838 */ __IO uint32_t TIM1_CH0_EIRQ_EN; /**< TIM[i] channel [x] error interrupt enable register, offset: 0x83C */ uint8_t RESERVED_4[64]; __IO uint32_t TIM1_CH1_GPR0; /**< TIM[i] channel [x] general purpose 0 register, offset: 0x880 */ __IO uint32_t TIM1_CH1_GPR1; /**< TIM[i] channel [x] general purpose 0 register, offset: 0x884 */ __I uint32_t TIM1_CH1_CNT; /**< TIM[i] channel [x] SMU counter register, offset: 0x888 */ __I uint32_t TIM1_CH1_ECNT; /**< TIM[i] channel [x] SMU edge counter register, offset: 0x88C */ __IO uint32_t TIM1_CH1_CNTS; /**< TIM[i] channel [x] SMU shadow counter register, offset: 0x890 */ __IO uint32_t TIM1_CH1_TDUC; /**< TIM[i] channel [x] TDU counter register, offset: 0x894 */ __IO uint32_t TIM1_CH1_TDUV; /**< TIM[i] channel [x] TDU control register, offset: 0x898 */ __IO uint32_t TIM1_CH1_FLT_RE; /**< TIM[i] channel [x] filter parameter 0 register, offset: 0x89C */ __IO uint32_t TIM1_CH1_FLT_FE; /**< TIM[i] channel [x] filter parameter 1 register, offset: 0x8A0 */ __IO uint32_t TIM1_CH1_CTRL; /**< TIM[i] channel [x] control register, offset: 0x8A4 */ __IO uint32_t TIM1_CH1_ECTRL; /**< TIM[i] channel [x] extended control register, offset: 0x8A8 */ __IO uint32_t TIM1_CH1_IRQ_NOTIFY; /**< TIM[i] channel [x] interrupt notification register, offset: 0x8AC */ __IO uint32_t TIM1_CH1_IRQ_EN; /**< TIM[i] channel [x] interrupt enable register, offset: 0x8B0 */ __IO uint32_t TIM1_CH1_IRQ_FORCINT; /**< TIM[i] channel [x] force interrupt register, offset: 0x8B4 */ __IO uint32_t TIM1_CH1_IRQ_MODE; /**< TIM[i] channel [x] interrupt mode configuration register, offset: 0x8B8 */ __IO uint32_t TIM1_CH1_EIRQ_EN; /**< TIM[i] channel [x] error interrupt enable register, offset: 0x8BC */ uint8_t RESERVED_5[64]; __IO uint32_t TIM1_CH2_GPR0; /**< TIM[i] channel [x] general purpose 0 register, offset: 0x900 */ __IO uint32_t TIM1_CH2_GPR1; /**< TIM[i] channel [x] general purpose 0 register, offset: 0x904 */ __I uint32_t TIM1_CH2_CNT; /**< TIM[i] channel [x] SMU counter register, offset: 0x908 */ __I uint32_t TIM1_CH2_ECNT; /**< TIM[i] channel [x] SMU edge counter register, offset: 0x90C */ __IO uint32_t TIM1_CH2_CNTS; /**< TIM[i] channel [x] SMU shadow counter register, offset: 0x910 */ __IO uint32_t TIM1_CH2_TDUC; /**< TIM[i] channel [x] TDU counter register, offset: 0x914 */ __IO uint32_t TIM1_CH2_TDUV; /**< TIM[i] channel [x] TDU control register, offset: 0x918 */ __IO uint32_t TIM1_CH2_FLT_RE; /**< TIM[i] channel [x] filter parameter 0 register, offset: 0x91C */ __IO uint32_t TIM1_CH2_FLT_FE; /**< TIM[i] channel [x] filter parameter 1 register, offset: 0x920 */ __IO uint32_t TIM1_CH2_CTRL; /**< TIM[i] channel [x] control register, offset: 0x924 */ __IO uint32_t TIM1_CH2_ECTRL; /**< TIM[i] channel [x] extended control register, offset: 0x928 */ __IO uint32_t TIM1_CH2_IRQ_NOTIFY; /**< TIM[i] channel [x] interrupt notification register, offset: 0x92C */ __IO uint32_t TIM1_CH2_IRQ_EN; /**< TIM[i] channel [x] interrupt enable register, offset: 0x930 */ __IO uint32_t TIM1_CH2_IRQ_FORCINT; /**< TIM[i] channel [x] force interrupt register, offset: 0x934 */ __IO uint32_t TIM1_CH2_IRQ_MODE; /**< TIM[i] channel [x] interrupt mode configuration register, offset: 0x938 */ __IO uint32_t TIM1_CH2_EIRQ_EN; /**< TIM[i] channel [x] error interrupt enable register, offset: 0x93C */ uint8_t RESERVED_6[64]; __IO uint32_t TIM1_CH3_GPR0; /**< TIM[i] channel [x] general purpose 0 register, offset: 0x980 */ __IO uint32_t TIM1_CH3_GPR1; /**< TIM[i] channel [x] general purpose 0 register, offset: 0x984 */ __I uint32_t TIM1_CH3_CNT; /**< TIM[i] channel [x] SMU counter register, offset: 0x988 */ __I uint32_t TIM1_CH3_ECNT; /**< TIM[i] channel [x] SMU edge counter register, offset: 0x98C */ __IO uint32_t TIM1_CH3_CNTS; /**< TIM[i] channel [x] SMU shadow counter register, offset: 0x990 */ __IO uint32_t TIM1_CH3_TDUC; /**< TIM[i] channel [x] TDU counter register, offset: 0x994 */ __IO uint32_t TIM1_CH3_TDUV; /**< TIM[i] channel [x] TDU control register, offset: 0x998 */ __IO uint32_t TIM1_CH3_FLT_RE; /**< TIM[i] channel [x] filter parameter 0 register, offset: 0x99C */ __IO uint32_t TIM1_CH3_FLT_FE; /**< TIM[i] channel [x] filter parameter 1 register, offset: 0x9A0 */ __IO uint32_t TIM1_CH3_CTRL; /**< TIM[i] channel [x] control register, offset: 0x9A4 */ __IO uint32_t TIM1_CH3_ECTRL; /**< TIM[i] channel [x] extended control register, offset: 0x9A8 */ __IO uint32_t TIM1_CH3_IRQ_NOTIFY; /**< TIM[i] channel [x] interrupt notification register, offset: 0x9AC */ __IO uint32_t TIM1_CH3_IRQ_EN; /**< TIM[i] channel [x] interrupt enable register, offset: 0x9B0 */ __IO uint32_t TIM1_CH3_IRQ_FORCINT; /**< TIM[i] channel [x] force interrupt register, offset: 0x9B4 */ __IO uint32_t TIM1_CH3_IRQ_MODE; /**< TIM[i] channel [x] interrupt mode configuration register, offset: 0x9B8 */ __IO uint32_t TIM1_CH3_EIRQ_EN; /**< TIM[i] channel [x] error interrupt enable register, offset: 0x9BC */ uint8_t RESERVED_7[64]; __IO uint32_t TIM1_CH4_GPR0; /**< TIM[i] channel [x] general purpose 0 register, offset: 0xA00 */ __IO uint32_t TIM1_CH4_GPR1; /**< TIM[i] channel [x] general purpose 0 register, offset: 0xA04 */ __I uint32_t TIM1_CH4_CNT; /**< TIM[i] channel [x] SMU counter register, offset: 0xA08 */ __I uint32_t TIM1_CH4_ECNT; /**< TIM[i] channel [x] SMU edge counter register, offset: 0xA0C */ __IO uint32_t TIM1_CH4_CNTS; /**< TIM[i] channel [x] SMU shadow counter register, offset: 0xA10 */ __IO uint32_t TIM1_CH4_TDUC; /**< TIM[i] channel [x] TDU counter register, offset: 0xA14 */ __IO uint32_t TIM1_CH4_TDUV; /**< TIM[i] channel [x] TDU control register, offset: 0xA18 */ __IO uint32_t TIM1_CH4_FLT_RE; /**< TIM[i] channel [x] filter parameter 0 register, offset: 0xA1C */ __IO uint32_t TIM1_CH4_FLT_FE; /**< TIM[i] channel [x] filter parameter 1 register, offset: 0xA20 */ __IO uint32_t TIM1_CH4_CTRL; /**< TIM[i] channel [x] control register, offset: 0xA24 */ __IO uint32_t TIM1_CH4_ECTRL; /**< TIM[i] channel [x] extended control register, offset: 0xA28 */ __IO uint32_t TIM1_CH4_IRQ_NOTIFY; /**< TIM[i] channel [x] interrupt notification register, offset: 0xA2C */ __IO uint32_t TIM1_CH4_IRQ_EN; /**< TIM[i] channel [x] interrupt enable register, offset: 0xA30 */ __IO uint32_t TIM1_CH4_IRQ_FORCINT; /**< TIM[i] channel [x] force interrupt register, offset: 0xA34 */ __IO uint32_t TIM1_CH4_IRQ_MODE; /**< TIM[i] channel [x] interrupt mode configuration register, offset: 0xA38 */ __IO uint32_t TIM1_CH4_EIRQ_EN; /**< TIM[i] channel [x] error interrupt enable register, offset: 0xA3C */ uint8_t RESERVED_8[64]; __IO uint32_t TIM1_CH5_GPR0; /**< TIM[i] channel [x] general purpose 0 register, offset: 0xA80 */ __IO uint32_t TIM1_CH5_GPR1; /**< TIM[i] channel [x] general purpose 0 register, offset: 0xA84 */ __I uint32_t TIM1_CH5_CNT; /**< TIM[i] channel [x] SMU counter register, offset: 0xA88 */ __I uint32_t TIM1_CH5_ECNT; /**< TIM[i] channel [x] SMU edge counter register, offset: 0xA8C */ __IO uint32_t TIM1_CH5_CNTS; /**< TIM[i] channel [x] SMU shadow counter register, offset: 0xA90 */ __IO uint32_t TIM1_CH5_TDUC; /**< TIM[i] channel [x] TDU counter register, offset: 0xA94 */ __IO uint32_t TIM1_CH5_TDUV; /**< TIM[i] channel [x] TDU control register, offset: 0xA98 */ __IO uint32_t TIM1_CH5_FLT_RE; /**< TIM[i] channel [x] filter parameter 0 register, offset: 0xA9C */ __IO uint32_t TIM1_CH5_FLT_FE; /**< TIM[i] channel [x] filter parameter 1 register, offset: 0xAA0 */ __IO uint32_t TIM1_CH5_CTRL; /**< TIM[i] channel [x] control register, offset: 0xAA4 */ __IO uint32_t TIM1_CH5_ECTRL; /**< TIM[i] channel [x] extended control register, offset: 0xAA8 */ __IO uint32_t TIM1_CH5_IRQ_NOTIFY; /**< TIM[i] channel [x] interrupt notification register, offset: 0xAAC */ __IO uint32_t TIM1_CH5_IRQ_EN; /**< TIM[i] channel [x] interrupt enable register, offset: 0xAB0 */ __IO uint32_t TIM1_CH5_IRQ_FORCINT; /**< TIM[i] channel [x] force interrupt register, offset: 0xAB4 */ __IO uint32_t TIM1_CH5_IRQ_MODE; /**< TIM[i] channel [x] interrupt mode configuration register, offset: 0xAB8 */ __IO uint32_t TIM1_CH5_EIRQ_EN; /**< TIM[i] channel [x] error interrupt enable register, offset: 0xABC */ uint8_t RESERVED_9[64]; __IO uint32_t TIM1_CH6_GPR0; /**< TIM[i] channel [x] general purpose 0 register, offset: 0xB00 */ __IO uint32_t TIM1_CH6_GPR1; /**< TIM[i] channel [x] general purpose 0 register, offset: 0xB04 */ __I uint32_t TIM1_CH6_CNT; /**< TIM[i] channel [x] SMU counter register, offset: 0xB08 */ __I uint32_t TIM1_CH6_ECNT; /**< TIM[i] channel [x] SMU edge counter register, offset: 0xB0C */ __IO uint32_t TIM1_CH6_CNTS; /**< TIM[i] channel [x] SMU shadow counter register, offset: 0xB10 */ __IO uint32_t TIM1_CH6_TDUC; /**< TIM[i] channel [x] TDU counter register, offset: 0xB14 */ __IO uint32_t TIM1_CH6_TDUV; /**< TIM[i] channel [x] TDU control register, offset: 0xB18 */ __IO uint32_t TIM1_CH6_FLT_RE; /**< TIM[i] channel [x] filter parameter 0 register, offset: 0xB1C */ __IO uint32_t TIM1_CH6_FLT_FE; /**< TIM[i] channel [x] filter parameter 1 register, offset: 0xB20 */ __IO uint32_t TIM1_CH6_CTRL; /**< TIM[i] channel [x] control register, offset: 0xB24 */ __IO uint32_t TIM1_CH6_ECTRL; /**< TIM[i] channel [x] extended control register, offset: 0xB28 */ __IO uint32_t TIM1_CH6_IRQ_NOTIFY; /**< TIM[i] channel [x] interrupt notification register, offset: 0xB2C */ __IO uint32_t TIM1_CH6_IRQ_EN; /**< TIM[i] channel [x] interrupt enable register, offset: 0xB30 */ __IO uint32_t TIM1_CH6_IRQ_FORCINT; /**< TIM[i] channel [x] force interrupt register, offset: 0xB34 */ __IO uint32_t TIM1_CH6_IRQ_MODE; /**< TIM[i] channel [x] interrupt mode configuration register, offset: 0xB38 */ __IO uint32_t TIM1_CH6_EIRQ_EN; /**< TIM[i] channel [x] error interrupt enable register, offset: 0xB3C */ uint8_t RESERVED_10[64]; __IO uint32_t TIM1_CH7_GPR0; /**< TIM[i] channel [x] general purpose 0 register, offset: 0xB80 */ __IO uint32_t TIM1_CH7_GPR1; /**< TIM[i] channel [x] general purpose 0 register, offset: 0xB84 */ __I uint32_t TIM1_CH7_CNT; /**< TIM[i] channel [x] SMU counter register, offset: 0xB88 */ __I uint32_t TIM1_CH7_ECNT; /**< TIM[i] channel [x] SMU edge counter register, offset: 0xB8C */ __IO uint32_t TIM1_CH7_CNTS; /**< TIM[i] channel [x] SMU shadow counter register, offset: 0xB90 */ __IO uint32_t TIM1_CH7_TDUC; /**< TIM[i] channel [x] TDU counter register, offset: 0xB94 */ __IO uint32_t TIM1_CH7_TDUV; /**< TIM[i] channel [x] TDU control register, offset: 0xB98 */ __IO uint32_t TIM1_CH7_FLT_RE; /**< TIM[i] channel [x] filter parameter 0 register, offset: 0xB9C */ __IO uint32_t TIM1_CH7_FLT_FE; /**< TIM[i] channel [x] filter parameter 1 register, offset: 0xBA0 */ __IO uint32_t TIM1_CH7_CTRL; /**< TIM[i] channel [x] control register, offset: 0xBA4 */ __IO uint32_t TIM1_CH7_ECTRL; /**< TIM[i] channel [x] extended control register, offset: 0xBA8 */ __IO uint32_t TIM1_CH7_IRQ_NOTIFY; /**< TIM[i] channel [x] interrupt notification register, offset: 0xBAC */ __IO uint32_t TIM1_CH7_IRQ_EN; /**< TIM[i] channel [x] interrupt enable register, offset: 0xBB0 */ __IO uint32_t TIM1_CH7_IRQ_FORCINT; /**< TIM[i] channel [x] force interrupt register, offset: 0xBB4 */ __IO uint32_t TIM1_CH7_IRQ_MODE; /**< TIM[i] channel [x] interrupt mode configuration register, offset: 0xBB8 */ __IO uint32_t TIM1_CH7_EIRQ_EN; /**< TIM[i] channel [x] error interrupt enable register, offset: 0xBBC */ uint8_t RESERVED_11[64]; __I uint32_t TIM1_INP_VAL; /**< TIM[i] input value observation register, offset: 0xC00 */ __IO uint32_t TIM1_IN_SRC; /**< TIM[i] AUX IN source selection register, offset: 0xC04 */ __IO uint32_t TIM1_RST; /**< TIM[i] global software reset register, offset: 0xC08 */ uint8_t RESERVED_12[1012]; __IO uint32_t TOM1_CH0_CTRL; /**< TOM[i] channel [x] control register, offset: 0x1000 */ __IO uint32_t TOM1_CH0_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x1004 */ __IO uint32_t TOM1_CH0_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x1008 */ __IO uint32_t TOM1_CH0_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x100C */ __IO uint32_t TOM1_CH0_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x1010 */ __IO uint32_t TOM1_CH0_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x1014 */ __IO uint32_t TOM1_CH0_STAT; /**< TOM[i] channel [x] status register, offset: 0x1018 */ __IO uint32_t TOM1_CH0_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x101C */ __IO uint32_t TOM1_CH0_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x1020 */ __IO uint32_t TOM1_CH0_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x1024 */ __IO uint32_t TOM1_CH0_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x1028 */ uint8_t RESERVED_13[4]; __IO uint32_t TOM1_CH0_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x1030 */ uint8_t RESERVED_14[12]; __IO uint32_t TOM1_CH1_CTRL; /**< TOM[i] channel [x] control register, offset: 0x1040 */ __IO uint32_t TOM1_CH1_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x1044 */ __IO uint32_t TOM1_CH1_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x1048 */ __IO uint32_t TOM1_CH1_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x104C */ __IO uint32_t TOM1_CH1_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x1050 */ __IO uint32_t TOM1_CH1_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x1054 */ __IO uint32_t TOM1_CH1_STAT; /**< TOM[i] channel [x] status register, offset: 0x1058 */ __IO uint32_t TOM1_CH1_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x105C */ __IO uint32_t TOM1_CH1_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x1060 */ __IO uint32_t TOM1_CH1_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x1064 */ __IO uint32_t TOM1_CH1_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x1068 */ uint8_t RESERVED_15[4]; __IO uint32_t TOM1_CH1_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x1070 */ uint8_t RESERVED_16[12]; __IO uint32_t TOM1_CH2_CTRL; /**< TOM[i] channel [x] control register, offset: 0x1080 */ __IO uint32_t TOM1_CH2_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x1084 */ __IO uint32_t TOM1_CH2_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x1088 */ __IO uint32_t TOM1_CH2_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x108C */ __IO uint32_t TOM1_CH2_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x1090 */ __IO uint32_t TOM1_CH2_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x1094 */ __IO uint32_t TOM1_CH2_STAT; /**< TOM[i] channel [x] status register, offset: 0x1098 */ __IO uint32_t TOM1_CH2_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x109C */ __IO uint32_t TOM1_CH2_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x10A0 */ __IO uint32_t TOM1_CH2_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x10A4 */ __IO uint32_t TOM1_CH2_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x10A8 */ uint8_t RESERVED_17[4]; __IO uint32_t TOM1_CH2_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x10B0 */ uint8_t RESERVED_18[12]; __IO uint32_t TOM1_CH3_CTRL; /**< TOM[i] channel [x] control register, offset: 0x10C0 */ __IO uint32_t TOM1_CH3_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x10C4 */ __IO uint32_t TOM1_CH3_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x10C8 */ __IO uint32_t TOM1_CH3_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x10CC */ __IO uint32_t TOM1_CH3_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x10D0 */ __IO uint32_t TOM1_CH3_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x10D4 */ __IO uint32_t TOM1_CH3_STAT; /**< TOM[i] channel [x] status register, offset: 0x10D8 */ __IO uint32_t TOM1_CH3_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x10DC */ __IO uint32_t TOM1_CH3_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x10E0 */ __IO uint32_t TOM1_CH3_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x10E4 */ __IO uint32_t TOM1_CH3_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x10E8 */ uint8_t RESERVED_19[4]; __IO uint32_t TOM1_CH3_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x10F0 */ uint8_t RESERVED_20[12]; __IO uint32_t TOM1_CH4_CTRL; /**< TOM[i] channel [x] control register, offset: 0x1100 */ __IO uint32_t TOM1_CH4_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x1104 */ __IO uint32_t TOM1_CH4_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x1108 */ __IO uint32_t TOM1_CH4_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x110C */ __IO uint32_t TOM1_CH4_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x1110 */ __IO uint32_t TOM1_CH4_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x1114 */ __IO uint32_t TOM1_CH4_STAT; /**< TOM[i] channel [x] status register, offset: 0x1118 */ __IO uint32_t TOM1_CH4_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x111C */ __IO uint32_t TOM1_CH4_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x1120 */ __IO uint32_t TOM1_CH4_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x1124 */ __IO uint32_t TOM1_CH4_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x1128 */ uint8_t RESERVED_21[4]; __IO uint32_t TOM1_CH4_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x1130 */ uint8_t RESERVED_22[12]; __IO uint32_t TOM1_CH5_CTRL; /**< TOM[i] channel [x] control register, offset: 0x1140 */ __IO uint32_t TOM1_CH5_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x1144 */ __IO uint32_t TOM1_CH5_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x1148 */ __IO uint32_t TOM1_CH5_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x114C */ __IO uint32_t TOM1_CH5_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x1150 */ __IO uint32_t TOM1_CH5_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x1154 */ __IO uint32_t TOM1_CH5_STAT; /**< TOM[i] channel [x] status register, offset: 0x1158 */ __IO uint32_t TOM1_CH5_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x115C */ __IO uint32_t TOM1_CH5_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x1160 */ __IO uint32_t TOM1_CH5_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x1164 */ __IO uint32_t TOM1_CH5_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x1168 */ uint8_t RESERVED_23[4]; __IO uint32_t TOM1_CH5_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x1170 */ uint8_t RESERVED_24[12]; __IO uint32_t TOM1_CH6_CTRL; /**< TOM[i] channel [x] control register, offset: 0x1180 */ __IO uint32_t TOM1_CH6_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x1184 */ __IO uint32_t TOM1_CH6_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x1188 */ __IO uint32_t TOM1_CH6_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x118C */ __IO uint32_t TOM1_CH6_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x1190 */ __IO uint32_t TOM1_CH6_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x1194 */ __IO uint32_t TOM1_CH6_STAT; /**< TOM[i] channel [x] status register, offset: 0x1198 */ __IO uint32_t TOM1_CH6_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x119C */ __IO uint32_t TOM1_CH6_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x11A0 */ __IO uint32_t TOM1_CH6_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x11A4 */ __IO uint32_t TOM1_CH6_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x11A8 */ uint8_t RESERVED_25[4]; __IO uint32_t TOM1_CH6_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x11B0 */ uint8_t RESERVED_26[12]; __IO uint32_t TOM1_CH7_CTRL; /**< TOM[i] channel [x] control register, offset: 0x11C0 */ __IO uint32_t TOM1_CH7_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x11C4 */ __IO uint32_t TOM1_CH7_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x11C8 */ __IO uint32_t TOM1_CH7_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x11CC */ __IO uint32_t TOM1_CH7_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x11D0 */ __IO uint32_t TOM1_CH7_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x11D4 */ __IO uint32_t TOM1_CH7_STAT; /**< TOM[i] channel [x] status register, offset: 0x11D8 */ __IO uint32_t TOM1_CH7_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x11DC */ __IO uint32_t TOM1_CH7_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x11E0 */ __IO uint32_t TOM1_CH7_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x11E4 */ __IO uint32_t TOM1_CH7_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x11E8 */ uint8_t RESERVED_27[4]; __IO uint32_t TOM1_CH7_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x11F0 */ uint8_t RESERVED_28[12]; __IO uint32_t TOM1_CH8_CTRL; /**< TOM[i] channel [x] control register, offset: 0x1200 */ __IO uint32_t TOM1_CH8_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x1204 */ __IO uint32_t TOM1_CH8_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x1208 */ __IO uint32_t TOM1_CH8_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x120C */ __IO uint32_t TOM1_CH8_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x1210 */ __IO uint32_t TOM1_CH8_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x1214 */ __IO uint32_t TOM1_CH8_STAT; /**< TOM[i] channel [x] status register, offset: 0x1218 */ __IO uint32_t TOM1_CH8_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x121C */ __IO uint32_t TOM1_CH8_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x1220 */ __IO uint32_t TOM1_CH8_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x1224 */ __IO uint32_t TOM1_CH8_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x1228 */ uint8_t RESERVED_29[4]; __IO uint32_t TOM1_CH8_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x1230 */ uint8_t RESERVED_30[12]; __IO uint32_t TOM1_CH9_CTRL; /**< TOM[i] channel [x] control register, offset: 0x1240 */ __IO uint32_t TOM1_CH9_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x1244 */ __IO uint32_t TOM1_CH9_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x1248 */ __IO uint32_t TOM1_CH9_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x124C */ __IO uint32_t TOM1_CH9_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x1250 */ __IO uint32_t TOM1_CH9_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x1254 */ __IO uint32_t TOM1_CH9_STAT; /**< TOM[i] channel [x] status register, offset: 0x1258 */ __IO uint32_t TOM1_CH9_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x125C */ __IO uint32_t TOM1_CH9_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x1260 */ __IO uint32_t TOM1_CH9_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x1264 */ __IO uint32_t TOM1_CH9_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x1268 */ uint8_t RESERVED_31[4]; __IO uint32_t TOM1_CH9_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x1270 */ uint8_t RESERVED_32[12]; __IO uint32_t TOM1_CH10_CTRL; /**< TOM[i] channel [x] control register, offset: 0x1280 */ __IO uint32_t TOM1_CH10_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x1284 */ __IO uint32_t TOM1_CH10_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x1288 */ __IO uint32_t TOM1_CH10_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x128C */ __IO uint32_t TOM1_CH10_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x1290 */ __IO uint32_t TOM1_CH10_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x1294 */ __IO uint32_t TOM1_CH10_STAT; /**< TOM[i] channel [x] status register, offset: 0x1298 */ __IO uint32_t TOM1_CH10_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x129C */ __IO uint32_t TOM1_CH10_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x12A0 */ __IO uint32_t TOM1_CH10_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x12A4 */ __IO uint32_t TOM1_CH10_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x12A8 */ uint8_t RESERVED_33[4]; __IO uint32_t TOM1_CH10_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x12B0 */ uint8_t RESERVED_34[12]; __IO uint32_t TOM1_CH11_CTRL; /**< TOM[i] channel [x] control register, offset: 0x12C0 */ __IO uint32_t TOM1_CH11_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x12C4 */ __IO uint32_t TOM1_CH11_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x12C8 */ __IO uint32_t TOM1_CH11_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x12CC */ __IO uint32_t TOM1_CH11_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x12D0 */ __IO uint32_t TOM1_CH11_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x12D4 */ __IO uint32_t TOM1_CH11_STAT; /**< TOM[i] channel [x] status register, offset: 0x12D8 */ __IO uint32_t TOM1_CH11_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x12DC */ __IO uint32_t TOM1_CH11_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x12E0 */ __IO uint32_t TOM1_CH11_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x12E4 */ __IO uint32_t TOM1_CH11_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x12E8 */ uint8_t RESERVED_35[4]; __IO uint32_t TOM1_CH11_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x12F0 */ uint8_t RESERVED_36[12]; __IO uint32_t TOM1_CH12_CTRL; /**< TOM[i] channel [x] control register, offset: 0x1300 */ __IO uint32_t TOM1_CH12_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x1304 */ __IO uint32_t TOM1_CH12_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x1308 */ __IO uint32_t TOM1_CH12_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x130C */ __IO uint32_t TOM1_CH12_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x1310 */ __IO uint32_t TOM1_CH12_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x1314 */ __IO uint32_t TOM1_CH12_STAT; /**< TOM[i] channel [x] status register, offset: 0x1318 */ __IO uint32_t TOM1_CH12_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x131C */ __IO uint32_t TOM1_CH12_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x1320 */ __IO uint32_t TOM1_CH12_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x1324 */ __IO uint32_t TOM1_CH12_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x1328 */ uint8_t RESERVED_37[4]; __IO uint32_t TOM1_CH12_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x1330 */ uint8_t RESERVED_38[12]; __IO uint32_t TOM1_CH13_CTRL; /**< TOM[i] channel [x] control register, offset: 0x1340 */ __IO uint32_t TOM1_CH13_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x1344 */ __IO uint32_t TOM1_CH13_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x1348 */ __IO uint32_t TOM1_CH13_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x134C */ __IO uint32_t TOM1_CH13_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x1350 */ __IO uint32_t TOM1_CH13_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x1354 */ __IO uint32_t TOM1_CH13_STAT; /**< TOM[i] channel [x] status register, offset: 0x1358 */ __IO uint32_t TOM1_CH13_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x135C */ __IO uint32_t TOM1_CH13_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x1360 */ __IO uint32_t TOM1_CH13_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x1364 */ __IO uint32_t TOM1_CH13_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x1368 */ uint8_t RESERVED_39[4]; __IO uint32_t TOM1_CH13_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x1370 */ uint8_t RESERVED_40[12]; __IO uint32_t TOM1_CH14_CTRL; /**< TOM[i] channel [x] control register, offset: 0x1380 */ __IO uint32_t TOM1_CH14_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x1384 */ __IO uint32_t TOM1_CH14_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x1388 */ __IO uint32_t TOM1_CH14_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x138C */ __IO uint32_t TOM1_CH14_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x1390 */ __IO uint32_t TOM1_CH14_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x1394 */ __IO uint32_t TOM1_CH14_STAT; /**< TOM[i] channel [x] status register, offset: 0x1398 */ __IO uint32_t TOM1_CH14_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x139C */ __IO uint32_t TOM1_CH14_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x13A0 */ __IO uint32_t TOM1_CH14_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x13A4 */ __IO uint32_t TOM1_CH14_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x13A8 */ uint8_t RESERVED_41[4]; __IO uint32_t TOM1_CH14_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x13B0 */ uint8_t RESERVED_42[12]; __IO uint32_t TOM1_CH15_CTRL; /**< TOM[i] channel [x] control register, offset: 0x13C0 */ __IO uint32_t TOM1_CH15_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x13C4 */ __IO uint32_t TOM1_CH15_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x13C8 */ __IO uint32_t TOM1_CH15_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x13CC */ __IO uint32_t TOM1_CH15_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x13D0 */ __IO uint32_t TOM1_CH15_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x13D4 */ __IO uint32_t TOM1_CH15_STAT; /**< TOM[i] channel [x] status register, offset: 0x13D8 */ __IO uint32_t TOM1_CH15_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x13DC */ __IO uint32_t TOM1_CH15_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x13E0 */ __IO uint32_t TOM1_CH15_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x13E4 */ __IO uint32_t TOM1_CH15_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x13E8 */ uint8_t RESERVED_43[4]; __IO uint32_t TOM1_CH15_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x13F0 */ uint8_t RESERVED_44[60]; __IO uint32_t TOM1_TGC0_GLB_CTRL; /**< TOM[i] TGC [g] global control register, offset: 0x1430 */ __IO uint32_t TOM1_TGC0_ACT_TB; /**< TOM[i] TGC [g] action time base register, offset: 0x1434 */ __IO uint32_t TOM1_TGC0_FUPD_CTRL; /**< TOM[i] TGC [g] force update control register, offset: 0x1438 */ __IO uint32_t TOM1_TGC0_INT_TRIG; /**< TOM[i] TGC [g] internal trigger control register, offset: 0x143C */ uint8_t RESERVED_45[48]; __IO uint32_t TOM1_TGC0_ENDIS_CTRL; /**< TOM[i] TGC [g] enable/disable control register, offset: 0x1470 */ __IO uint32_t TOM1_TGC0_ENDIS_STAT; /**< TOM[i] TGC [g] enable/disable status register, offset: 0x1474 */ __IO uint32_t TOM1_TGC0_OUTEN_CTRL; /**< TOM[i] TGC [g] output enable control register, offset: 0x1478 */ __IO uint32_t TOM1_TGC0_OUTEN_STAT; /**< TOM[i] TGC [g] output enable status register, offset: 0x147C */ uint8_t RESERVED_46[48]; __IO uint32_t TOM1_TGC1_GLB_CTRL; /**< TOM[i] TGC [g] global control register, offset: 0x14B0 */ __IO uint32_t TOM1_TGC1_ACT_TB; /**< TOM[i] TGC [g] action time base register, offset: 0x14B4 */ __IO uint32_t TOM1_TGC1_FUPD_CTRL; /**< TOM[i] TGC [g] force update control register, offset: 0x14B8 */ __IO uint32_t TOM1_TGC1_INT_TRIG; /**< TOM[i] TGC [g] internal trigger control register, offset: 0x14BC */ uint8_t RESERVED_47[48]; __IO uint32_t TOM1_TGC1_ENDIS_CTRL; /**< TOM[i] TGC [g] enable/disable control register, offset: 0x14F0 */ __IO uint32_t TOM1_TGC1_ENDIS_STAT; /**< TOM[i] TGC [g] enable/disable status register, offset: 0x14F4 */ __IO uint32_t TOM1_TGC1_OUTEN_CTRL; /**< TOM[i] TGC [g] output enable control register, offset: 0x14F8 */ __IO uint32_t TOM1_TGC1_OUTEN_STAT; /**< TOM[i] TGC [g] output enable status register, offset: 0x14FC */ uint8_t RESERVED_48[768]; __IO uint32_t ATOM1_CH0_RDADDR; /**< ATOM[i] channel[x] ARU read address register, offset: 0x1800 */ __IO uint32_t ATOM1_CH0_CTRL; /**< ATOM[i] channel [x] control register, offset: 0x1804 */ __IO uint32_t ATOM1_CH0_SR0; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1808 */ __IO uint32_t ATOM1_CH0_SR1; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x180C */ __IO uint32_t ATOM1_CH0_CM0; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1810 */ __IO uint32_t ATOM1_CH0_CM1; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1814 */ __IO uint32_t ATOM1_CH0_CN0; /**< ATOM[i] channel [x] CCU0 counter register, offset: 0x1818 */ __IO uint32_t ATOM1_CH0_STAT; /**< ATOM[i] channel [x] status register, offset: 0x181C */ __IO uint32_t ATOM1_CH0_IRQ_NOTIFY; /**< ATOM[i] channel [x] interrupt notification register, offset: 0x1820 */ __IO uint32_t ATOM1_CH0_IRQ_EN; /**< ATOM[i] channel [x] interrupt enable register, offset: 0x1824 */ __IO uint32_t ATOM1_CH0_IRQ_FORCINT; /**< ATOM[i] channel [x] software interrupt generation, offset: 0x1828 */ __IO uint32_t ATOM1_CH0_IRQ_MODE; /**< ATOM[i] channel [x] interrupt mode configuration register, offset: 0x182C */ __IO uint32_t ATOM1_CH0_CTRL2; /**< ATOM[i] channel [x] control2 register, offset: 0x1830 */ __IO uint32_t ATOM1_CH0_CTRL_SR; /**< ATOM[i] channel [x] control shadow register, offset: 0x1834 */ uint8_t RESERVED_49[72]; __IO uint32_t ATOM1_CH1_RDADDR; /**< ATOM[i] channel[x] ARU read address register, offset: 0x1880 */ __IO uint32_t ATOM1_CH1_CTRL; /**< ATOM[i] channel [x] control register, offset: 0x1884 */ __IO uint32_t ATOM1_CH1_SR0; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1888 */ __IO uint32_t ATOM1_CH1_SR1; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x188C */ __IO uint32_t ATOM1_CH1_CM0; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1890 */ __IO uint32_t ATOM1_CH1_CM1; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1894 */ __IO uint32_t ATOM1_CH1_CN0; /**< ATOM[i] channel [x] CCU0 counter register, offset: 0x1898 */ __IO uint32_t ATOM1_CH1_STAT; /**< ATOM[i] channel [x] status register, offset: 0x189C */ __IO uint32_t ATOM1_CH1_IRQ_NOTIFY; /**< ATOM[i] channel [x] interrupt notification register, offset: 0x18A0 */ __IO uint32_t ATOM1_CH1_IRQ_EN; /**< ATOM[i] channel [x] interrupt enable register, offset: 0x18A4 */ __IO uint32_t ATOM1_CH1_IRQ_FORCINT; /**< ATOM[i] channel [x] software interrupt generation, offset: 0x18A8 */ __IO uint32_t ATOM1_CH1_IRQ_MODE; /**< ATOM[i] channel [x] interrupt mode configuration register, offset: 0x18AC */ __IO uint32_t ATOM1_CH1_CTRL2; /**< ATOM[i] channel [x] control2 register, offset: 0x18B0 */ __IO uint32_t ATOM1_CH1_CTRL_SR; /**< ATOM[i] channel [x] control shadow register, offset: 0x18B4 */ uint8_t RESERVED_50[72]; __IO uint32_t ATOM1_CH2_RDADDR; /**< ATOM[i] channel[x] ARU read address register, offset: 0x1900 */ __IO uint32_t ATOM1_CH2_CTRL; /**< ATOM[i] channel [x] control register, offset: 0x1904 */ __IO uint32_t ATOM1_CH2_SR0; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1908 */ __IO uint32_t ATOM1_CH2_SR1; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x190C */ __IO uint32_t ATOM1_CH2_CM0; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1910 */ __IO uint32_t ATOM1_CH2_CM1; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1914 */ __IO uint32_t ATOM1_CH2_CN0; /**< ATOM[i] channel [x] CCU0 counter register, offset: 0x1918 */ __IO uint32_t ATOM1_CH2_STAT; /**< ATOM[i] channel [x] status register, offset: 0x191C */ __IO uint32_t ATOM1_CH2_IRQ_NOTIFY; /**< ATOM[i] channel [x] interrupt notification register, offset: 0x1920 */ __IO uint32_t ATOM1_CH2_IRQ_EN; /**< ATOM[i] channel [x] interrupt enable register, offset: 0x1924 */ __IO uint32_t ATOM1_CH2_IRQ_FORCINT; /**< ATOM[i] channel [x] software interrupt generation, offset: 0x1928 */ __IO uint32_t ATOM1_CH2_IRQ_MODE; /**< ATOM[i] channel [x] interrupt mode configuration register, offset: 0x192C */ __IO uint32_t ATOM1_CH2_CTRL2; /**< ATOM[i] channel [x] control2 register, offset: 0x1930 */ __IO uint32_t ATOM1_CH2_CTRL_SR; /**< ATOM[i] channel [x] control shadow register, offset: 0x1934 */ uint8_t RESERVED_51[72]; __IO uint32_t ATOM1_CH3_RDADDR; /**< ATOM[i] channel[x] ARU read address register, offset: 0x1980 */ __IO uint32_t ATOM1_CH3_CTRL; /**< ATOM[i] channel [x] control register, offset: 0x1984 */ __IO uint32_t ATOM1_CH3_SR0; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1988 */ __IO uint32_t ATOM1_CH3_SR1; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x198C */ __IO uint32_t ATOM1_CH3_CM0; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1990 */ __IO uint32_t ATOM1_CH3_CM1; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1994 */ __IO uint32_t ATOM1_CH3_CN0; /**< ATOM[i] channel [x] CCU0 counter register, offset: 0x1998 */ __IO uint32_t ATOM1_CH3_STAT; /**< ATOM[i] channel [x] status register, offset: 0x199C */ __IO uint32_t ATOM1_CH3_IRQ_NOTIFY; /**< ATOM[i] channel [x] interrupt notification register, offset: 0x19A0 */ __IO uint32_t ATOM1_CH3_IRQ_EN; /**< ATOM[i] channel [x] interrupt enable register, offset: 0x19A4 */ __IO uint32_t ATOM1_CH3_IRQ_FORCINT; /**< ATOM[i] channel [x] software interrupt generation, offset: 0x19A8 */ __IO uint32_t ATOM1_CH3_IRQ_MODE; /**< ATOM[i] channel [x] interrupt mode configuration register, offset: 0x19AC */ __IO uint32_t ATOM1_CH3_CTRL2; /**< ATOM[i] channel [x] control2 register, offset: 0x19B0 */ __IO uint32_t ATOM1_CH3_CTRL_SR; /**< ATOM[i] channel [x] control shadow register, offset: 0x19B4 */ uint8_t RESERVED_52[72]; __IO uint32_t ATOM1_CH4_RDADDR; /**< ATOM[i] channel[x] ARU read address register, offset: 0x1A00 */ __IO uint32_t ATOM1_CH4_CTRL; /**< ATOM[i] channel [x] control register, offset: 0x1A04 */ __IO uint32_t ATOM1_CH4_SR0; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1A08 */ __IO uint32_t ATOM1_CH4_SR1; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1A0C */ __IO uint32_t ATOM1_CH4_CM0; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1A10 */ __IO uint32_t ATOM1_CH4_CM1; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1A14 */ __IO uint32_t ATOM1_CH4_CN0; /**< ATOM[i] channel [x] CCU0 counter register, offset: 0x1A18 */ __IO uint32_t ATOM1_CH4_STAT; /**< ATOM[i] channel [x] status register, offset: 0x1A1C */ __IO uint32_t ATOM1_CH4_IRQ_NOTIFY; /**< ATOM[i] channel [x] interrupt notification register, offset: 0x1A20 */ __IO uint32_t ATOM1_CH4_IRQ_EN; /**< ATOM[i] channel [x] interrupt enable register, offset: 0x1A24 */ __IO uint32_t ATOM1_CH4_IRQ_FORCINT; /**< ATOM[i] channel [x] software interrupt generation, offset: 0x1A28 */ __IO uint32_t ATOM1_CH4_IRQ_MODE; /**< ATOM[i] channel [x] interrupt mode configuration register, offset: 0x1A2C */ __IO uint32_t ATOM1_CH4_CTRL2; /**< ATOM[i] channel [x] control2 register, offset: 0x1A30 */ __IO uint32_t ATOM1_CH4_CTRL_SR; /**< ATOM[i] channel [x] control shadow register, offset: 0x1A34 */ uint8_t RESERVED_53[72]; __IO uint32_t ATOM1_CH5_RDADDR; /**< ATOM[i] channel[x] ARU read address register, offset: 0x1A80 */ __IO uint32_t ATOM1_CH5_CTRL; /**< ATOM[i] channel [x] control register, offset: 0x1A84 */ __IO uint32_t ATOM1_CH5_SR0; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1A88 */ __IO uint32_t ATOM1_CH5_SR1; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1A8C */ __IO uint32_t ATOM1_CH5_CM0; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1A90 */ __IO uint32_t ATOM1_CH5_CM1; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1A94 */ __IO uint32_t ATOM1_CH5_CN0; /**< ATOM[i] channel [x] CCU0 counter register, offset: 0x1A98 */ __IO uint32_t ATOM1_CH5_STAT; /**< ATOM[i] channel [x] status register, offset: 0x1A9C */ __IO uint32_t ATOM1_CH5_IRQ_NOTIFY; /**< ATOM[i] channel [x] interrupt notification register, offset: 0x1AA0 */ __IO uint32_t ATOM1_CH5_IRQ_EN; /**< ATOM[i] channel [x] interrupt enable register, offset: 0x1AA4 */ __IO uint32_t ATOM1_CH5_IRQ_FORCINT; /**< ATOM[i] channel [x] software interrupt generation, offset: 0x1AA8 */ __IO uint32_t ATOM1_CH5_IRQ_MODE; /**< ATOM[i] channel [x] interrupt mode configuration register, offset: 0x1AAC */ __IO uint32_t ATOM1_CH5_CTRL2; /**< ATOM[i] channel [x] control2 register, offset: 0x1AB0 */ __IO uint32_t ATOM1_CH5_CTRL_SR; /**< ATOM[i] channel [x] control shadow register, offset: 0x1AB4 */ uint8_t RESERVED_54[72]; __IO uint32_t ATOM1_CH6_RDADDR; /**< ATOM[i] channel[x] ARU read address register, offset: 0x1B00 */ __IO uint32_t ATOM1_CH6_CTRL; /**< ATOM[i] channel [x] control register, offset: 0x1B04 */ __IO uint32_t ATOM1_CH6_SR0; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1B08 */ __IO uint32_t ATOM1_CH6_SR1; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1B0C */ __IO uint32_t ATOM1_CH6_CM0; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1B10 */ __IO uint32_t ATOM1_CH6_CM1; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1B14 */ __IO uint32_t ATOM1_CH6_CN0; /**< ATOM[i] channel [x] CCU0 counter register, offset: 0x1B18 */ __IO uint32_t ATOM1_CH6_STAT; /**< ATOM[i] channel [x] status register, offset: 0x1B1C */ __IO uint32_t ATOM1_CH6_IRQ_NOTIFY; /**< ATOM[i] channel [x] interrupt notification register, offset: 0x1B20 */ __IO uint32_t ATOM1_CH6_IRQ_EN; /**< ATOM[i] channel [x] interrupt enable register, offset: 0x1B24 */ __IO uint32_t ATOM1_CH6_IRQ_FORCINT; /**< ATOM[i] channel [x] software interrupt generation, offset: 0x1B28 */ __IO uint32_t ATOM1_CH6_IRQ_MODE; /**< ATOM[i] channel [x] interrupt mode configuration register, offset: 0x1B2C */ __IO uint32_t ATOM1_CH6_CTRL2; /**< ATOM[i] channel [x] control2 register, offset: 0x1B30 */ __IO uint32_t ATOM1_CH6_CTRL_SR; /**< ATOM[i] channel [x] control shadow register, offset: 0x1B34 */ uint8_t RESERVED_55[72]; __IO uint32_t ATOM1_CH7_RDADDR; /**< ATOM[i] channel[x] ARU read address register, offset: 0x1B80 */ __IO uint32_t ATOM1_CH7_CTRL; /**< ATOM[i] channel [x] control register, offset: 0x1B84 */ __IO uint32_t ATOM1_CH7_SR0; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1B88 */ __IO uint32_t ATOM1_CH7_SR1; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1B8C */ __IO uint32_t ATOM1_CH7_CM0; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1B90 */ __IO uint32_t ATOM1_CH7_CM1; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1B94 */ __IO uint32_t ATOM1_CH7_CN0; /**< ATOM[i] channel [x] CCU0 counter register, offset: 0x1B98 */ __IO uint32_t ATOM1_CH7_STAT; /**< ATOM[i] channel [x] status register, offset: 0x1B9C */ __IO uint32_t ATOM1_CH7_IRQ_NOTIFY; /**< ATOM[i] channel [x] interrupt notification register, offset: 0x1BA0 */ __IO uint32_t ATOM1_CH7_IRQ_EN; /**< ATOM[i] channel [x] interrupt enable register, offset: 0x1BA4 */ __IO uint32_t ATOM1_CH7_IRQ_FORCINT; /**< ATOM[i] channel [x] software interrupt generation, offset: 0x1BA8 */ __IO uint32_t ATOM1_CH7_IRQ_MODE; /**< ATOM[i] channel [x] interrupt mode configuration register, offset: 0x1BAC */ __IO uint32_t ATOM1_CH7_CTRL2; /**< ATOM[i] channel [x] control2 register, offset: 0x1BB0 */ __IO uint32_t ATOM1_CH7_CTRL_SR; /**< ATOM[i] channel [x] control shadow register, offset: 0x1BB4 */ uint8_t RESERVED_56[136]; __IO uint32_t ATOM1_AGC_GLB_CTRL; /**< ATOM[i] AGC global control register, offset: 0x1C40 */ __IO uint32_t ATOM1_AGC_ENDIS_CTRL; /**< ATOM[i] AGC enable/disable control register, offset: 0x1C44 */ __IO uint32_t ATOM1_AGC_ENDIS_STAT; /**< ATOM[i] AGC enable/disable status register, offset: 0x1C48 */ __IO uint32_t ATOM1_AGC_ACT_TB; /**< ATOM[i] AGC action time base register, offset: 0x1C4C */ __IO uint32_t ATOM1_AGC_OUTEN_CTRL; /**< ATOM[i] AGC output enable control register, offset: 0x1C50 */ __IO uint32_t ATOM1_AGC_OUTEN_STAT; /**< ATOM[i] AGC output enable status register, offset: 0x1C54 */ __IO uint32_t ATOM1_AGC_FUPD_CTRL; /**< ATOM[i] AGC force update control register, offset: 0x1C58 */ __IO uint32_t ATOM1_AGC_INT_TRIG; /**< ATOM[i] AGC internal trigger control register, offset: 0x1C5C */ uint8_t RESERVED_57[928]; __IO uint32_t MCS1_CH0_R0; /**< MCS[i] channel x general purpose register [y], offset: 0x2000 */ __IO uint32_t MCS1_CH0_R1; /**< MCS[i] channel x general purpose register [y], offset: 0x2004 */ __IO uint32_t MCS1_CH0_R2; /**< MCS[i] channel x general purpose register [y], offset: 0x2008 */ __IO uint32_t MCS1_CH0_R3; /**< MCS[i] channel x general purpose register [y], offset: 0x200C */ __IO uint32_t MCS1_CH0_R4; /**< MCS[i] channel x general purpose register [y], offset: 0x2010 */ __IO uint32_t MCS1_CH0_R5; /**< MCS[i] channel x general purpose register [y], offset: 0x2014 */ __IO uint32_t MCS1_CH0_R6; /**< MCS[i] channel x general purpose register [y], offset: 0x2018 */ __IO uint32_t MCS1_CH0_R7; /**< MCS[i] channel x general purpose register [y], offset: 0x201C */ __IO uint32_t MCS1_CH0_CTRL; /**< MCS[i] channel x control register, offset: 0x2020 */ __I uint32_t MCS1_CH0_ACB; /**< MCS[i] channel x ARU control Bit register, offset: 0x2024 */ uint8_t RESERVED_58[20]; __I uint32_t MCS1_CH0_MHB; /**< MCS[i] channel x memory high byte register, offset: 0x203C */ uint8_t RESERVED_59[160]; __IO uint32_t MCS1_CH0_PC; /**< MCS[i] channel x program counter register, offset: 0x20E0 */ __IO uint32_t MCS1_CH0_IRQ_NOTIFY; /**< MCS[i] channel x interrupt notification register, offset: 0x20E4 */ __IO uint32_t MCS1_CH0_IRQ_EN; /**< MCS[i] channel x interrupt enable register, offset: 0x20E8 */ __IO uint32_t MCS1_CH0_IRQ_FORCINT; /**< MCS[i] channel x force interrupt register, offset: 0x20EC */ __IO uint32_t MCS1_CH0_IRQ_MODE; /**< MCS[i] channel x IRQ mode configuration register, offset: 0x20F0 */ __IO uint32_t MCS1_CH0_EIRQ_EN; /**< MCS[i] channel x error interrupt enable register, offset: 0x20F4 */ uint8_t RESERVED_60[8]; __IO uint32_t MCS1_CH1_R0; /**< MCS[i] channel x general purpose register [y], offset: 0x2100 */ __IO uint32_t MCS1_CH1_R1; /**< MCS[i] channel x general purpose register [y], offset: 0x2104 */ __IO uint32_t MCS1_CH1_R2; /**< MCS[i] channel x general purpose register [y], offset: 0x2108 */ __IO uint32_t MCS1_CH1_R3; /**< MCS[i] channel x general purpose register [y], offset: 0x210C */ __IO uint32_t MCS1_CH1_R4; /**< MCS[i] channel x general purpose register [y], offset: 0x2110 */ __IO uint32_t MCS1_CH1_R5; /**< MCS[i] channel x general purpose register [y], offset: 0x2114 */ __IO uint32_t MCS1_CH1_R6; /**< MCS[i] channel x general purpose register [y], offset: 0x2118 */ __IO uint32_t MCS1_CH1_R7; /**< MCS[i] channel x general purpose register [y], offset: 0x211C */ __IO uint32_t MCS1_CH1_CTRL; /**< MCS[i] channel x control register, offset: 0x2120 */ __I uint32_t MCS1_CH1_ACB; /**< MCS[i] channel x ARU control Bit register, offset: 0x2124 */ uint8_t RESERVED_61[20]; __I uint32_t MCS1_CH1_MHB; /**< MCS[i] channel x memory high byte register, offset: 0x213C */ uint8_t RESERVED_62[160]; __IO uint32_t MCS1_CH1_PC; /**< MCS[i] channel x program counter register, offset: 0x21E0 */ __IO uint32_t MCS1_CH1_IRQ_NOTIFY; /**< MCS[i] channel x interrupt notification register, offset: 0x21E4 */ __IO uint32_t MCS1_CH1_IRQ_EN; /**< MCS[i] channel x interrupt enable register, offset: 0x21E8 */ __IO uint32_t MCS1_CH1_IRQ_FORCINT; /**< MCS[i] channel x force interrupt register, offset: 0x21EC */ __IO uint32_t MCS1_CH1_IRQ_MODE; /**< MCS[i] channel x IRQ mode configuration register, offset: 0x21F0 */ __IO uint32_t MCS1_CH1_EIRQ_EN; /**< MCS[i] channel x error interrupt enable register, offset: 0x21F4 */ uint8_t RESERVED_63[8]; __IO uint32_t MCS1_CH2_R0; /**< MCS[i] channel x general purpose register [y], offset: 0x2200 */ __IO uint32_t MCS1_CH2_R1; /**< MCS[i] channel x general purpose register [y], offset: 0x2204 */ __IO uint32_t MCS1_CH2_R2; /**< MCS[i] channel x general purpose register [y], offset: 0x2208 */ __IO uint32_t MCS1_CH2_R3; /**< MCS[i] channel x general purpose register [y], offset: 0x220C */ __IO uint32_t MCS1_CH2_R4; /**< MCS[i] channel x general purpose register [y], offset: 0x2210 */ __IO uint32_t MCS1_CH2_R5; /**< MCS[i] channel x general purpose register [y], offset: 0x2214 */ __IO uint32_t MCS1_CH2_R6; /**< MCS[i] channel x general purpose register [y], offset: 0x2218 */ __IO uint32_t MCS1_CH2_R7; /**< MCS[i] channel x general purpose register [y], offset: 0x221C */ __IO uint32_t MCS1_CH2_CTRL; /**< MCS[i] channel x control register, offset: 0x2220 */ __I uint32_t MCS1_CH2_ACB; /**< MCS[i] channel x ARU control Bit register, offset: 0x2224 */ uint8_t RESERVED_64[20]; __I uint32_t MCS1_CH2_MHB; /**< MCS[i] channel x memory high byte register, offset: 0x223C */ uint8_t RESERVED_65[160]; __IO uint32_t MCS1_CH2_PC; /**< MCS[i] channel x program counter register, offset: 0x22E0 */ __IO uint32_t MCS1_CH2_IRQ_NOTIFY; /**< MCS[i] channel x interrupt notification register, offset: 0x22E4 */ __IO uint32_t MCS1_CH2_IRQ_EN; /**< MCS[i] channel x interrupt enable register, offset: 0x22E8 */ __IO uint32_t MCS1_CH2_IRQ_FORCINT; /**< MCS[i] channel x force interrupt register, offset: 0x22EC */ __IO uint32_t MCS1_CH2_IRQ_MODE; /**< MCS[i] channel x IRQ mode configuration register, offset: 0x22F0 */ __IO uint32_t MCS1_CH2_EIRQ_EN; /**< MCS[i] channel x error interrupt enable register, offset: 0x22F4 */ uint8_t RESERVED_66[8]; __IO uint32_t MCS1_CH3_R0; /**< MCS[i] channel x general purpose register [y], offset: 0x2300 */ __IO uint32_t MCS1_CH3_R1; /**< MCS[i] channel x general purpose register [y], offset: 0x2304 */ __IO uint32_t MCS1_CH3_R2; /**< MCS[i] channel x general purpose register [y], offset: 0x2308 */ __IO uint32_t MCS1_CH3_R3; /**< MCS[i] channel x general purpose register [y], offset: 0x230C */ __IO uint32_t MCS1_CH3_R4; /**< MCS[i] channel x general purpose register [y], offset: 0x2310 */ __IO uint32_t MCS1_CH3_R5; /**< MCS[i] channel x general purpose register [y], offset: 0x2314 */ __IO uint32_t MCS1_CH3_R6; /**< MCS[i] channel x general purpose register [y], offset: 0x2318 */ __IO uint32_t MCS1_CH3_R7; /**< MCS[i] channel x general purpose register [y], offset: 0x231C */ __IO uint32_t MCS1_CH3_CTRL; /**< MCS[i] channel x control register, offset: 0x2320 */ __I uint32_t MCS1_CH3_ACB; /**< MCS[i] channel x ARU control Bit register, offset: 0x2324 */ uint8_t RESERVED_67[20]; __I uint32_t MCS1_CH3_MHB; /**< MCS[i] channel x memory high byte register, offset: 0x233C */ uint8_t RESERVED_68[160]; __IO uint32_t MCS1_CH3_PC; /**< MCS[i] channel x program counter register, offset: 0x23E0 */ __IO uint32_t MCS1_CH3_IRQ_NOTIFY; /**< MCS[i] channel x interrupt notification register, offset: 0x23E4 */ __IO uint32_t MCS1_CH3_IRQ_EN; /**< MCS[i] channel x interrupt enable register, offset: 0x23E8 */ __IO uint32_t MCS1_CH3_IRQ_FORCINT; /**< MCS[i] channel x force interrupt register, offset: 0x23EC */ __IO uint32_t MCS1_CH3_IRQ_MODE; /**< MCS[i] channel x IRQ mode configuration register, offset: 0x23F0 */ __IO uint32_t MCS1_CH3_EIRQ_EN; /**< MCS[i] channel x error interrupt enable register, offset: 0x23F4 */ uint8_t RESERVED_69[8]; __IO uint32_t MCS1_CH4_R0; /**< MCS[i] channel x general purpose register [y], offset: 0x2400 */ __IO uint32_t MCS1_CH4_R1; /**< MCS[i] channel x general purpose register [y], offset: 0x2404 */ __IO uint32_t MCS1_CH4_R2; /**< MCS[i] channel x general purpose register [y], offset: 0x2408 */ __IO uint32_t MCS1_CH4_R3; /**< MCS[i] channel x general purpose register [y], offset: 0x240C */ __IO uint32_t MCS1_CH4_R4; /**< MCS[i] channel x general purpose register [y], offset: 0x2410 */ __IO uint32_t MCS1_CH4_R5; /**< MCS[i] channel x general purpose register [y], offset: 0x2414 */ __IO uint32_t MCS1_CH4_R6; /**< MCS[i] channel x general purpose register [y], offset: 0x2418 */ __IO uint32_t MCS1_CH4_R7; /**< MCS[i] channel x general purpose register [y], offset: 0x241C */ __IO uint32_t MCS1_CH4_CTRL; /**< MCS[i] channel x control register, offset: 0x2420 */ __I uint32_t MCS1_CH4_ACB; /**< MCS[i] channel x ARU control Bit register, offset: 0x2424 */ uint8_t RESERVED_70[20]; __I uint32_t MCS1_CH4_MHB; /**< MCS[i] channel x memory high byte register, offset: 0x243C */ uint8_t RESERVED_71[160]; __IO uint32_t MCS1_CH4_PC; /**< MCS[i] channel x program counter register, offset: 0x24E0 */ __IO uint32_t MCS1_CH4_IRQ_NOTIFY; /**< MCS[i] channel x interrupt notification register, offset: 0x24E4 */ __IO uint32_t MCS1_CH4_IRQ_EN; /**< MCS[i] channel x interrupt enable register, offset: 0x24E8 */ __IO uint32_t MCS1_CH4_IRQ_FORCINT; /**< MCS[i] channel x force interrupt register, offset: 0x24EC */ __IO uint32_t MCS1_CH4_IRQ_MODE; /**< MCS[i] channel x IRQ mode configuration register, offset: 0x24F0 */ __IO uint32_t MCS1_CH4_EIRQ_EN; /**< MCS[i] channel x error interrupt enable register, offset: 0x24F4 */ uint8_t RESERVED_72[8]; __IO uint32_t MCS1_CH5_R0; /**< MCS[i] channel x general purpose register [y], offset: 0x2500 */ __IO uint32_t MCS1_CH5_R1; /**< MCS[i] channel x general purpose register [y], offset: 0x2504 */ __IO uint32_t MCS1_CH5_R2; /**< MCS[i] channel x general purpose register [y], offset: 0x2508 */ __IO uint32_t MCS1_CH5_R3; /**< MCS[i] channel x general purpose register [y], offset: 0x250C */ __IO uint32_t MCS1_CH5_R4; /**< MCS[i] channel x general purpose register [y], offset: 0x2510 */ __IO uint32_t MCS1_CH5_R5; /**< MCS[i] channel x general purpose register [y], offset: 0x2514 */ __IO uint32_t MCS1_CH5_R6; /**< MCS[i] channel x general purpose register [y], offset: 0x2518 */ __IO uint32_t MCS1_CH5_R7; /**< MCS[i] channel x general purpose register [y], offset: 0x251C */ __IO uint32_t MCS1_CH5_CTRL; /**< MCS[i] channel x control register, offset: 0x2520 */ __I uint32_t MCS1_CH5_ACB; /**< MCS[i] channel x ARU control Bit register, offset: 0x2524 */ uint8_t RESERVED_73[20]; __I uint32_t MCS1_CH5_MHB; /**< MCS[i] channel x memory high byte register, offset: 0x253C */ uint8_t RESERVED_74[160]; __IO uint32_t MCS1_CH5_PC; /**< MCS[i] channel x program counter register, offset: 0x25E0 */ __IO uint32_t MCS1_CH5_IRQ_NOTIFY; /**< MCS[i] channel x interrupt notification register, offset: 0x25E4 */ __IO uint32_t MCS1_CH5_IRQ_EN; /**< MCS[i] channel x interrupt enable register, offset: 0x25E8 */ __IO uint32_t MCS1_CH5_IRQ_FORCINT; /**< MCS[i] channel x force interrupt register, offset: 0x25EC */ __IO uint32_t MCS1_CH5_IRQ_MODE; /**< MCS[i] channel x IRQ mode configuration register, offset: 0x25F0 */ __IO uint32_t MCS1_CH5_EIRQ_EN; /**< MCS[i] channel x error interrupt enable register, offset: 0x25F4 */ uint8_t RESERVED_75[8]; __IO uint32_t MCS1_CH6_R0; /**< MCS[i] channel x general purpose register [y], offset: 0x2600 */ __IO uint32_t MCS1_CH6_R1; /**< MCS[i] channel x general purpose register [y], offset: 0x2604 */ __IO uint32_t MCS1_CH6_R2; /**< MCS[i] channel x general purpose register [y], offset: 0x2608 */ __IO uint32_t MCS1_CH6_R3; /**< MCS[i] channel x general purpose register [y], offset: 0x260C */ __IO uint32_t MCS1_CH6_R4; /**< MCS[i] channel x general purpose register [y], offset: 0x2610 */ __IO uint32_t MCS1_CH6_R5; /**< MCS[i] channel x general purpose register [y], offset: 0x2614 */ __IO uint32_t MCS1_CH6_R6; /**< MCS[i] channel x general purpose register [y], offset: 0x2618 */ __IO uint32_t MCS1_CH6_R7; /**< MCS[i] channel x general purpose register [y], offset: 0x261C */ __IO uint32_t MCS1_CH6_CTRL; /**< MCS[i] channel x control register, offset: 0x2620 */ __I uint32_t MCS1_CH6_ACB; /**< MCS[i] channel x ARU control Bit register, offset: 0x2624 */ uint8_t RESERVED_76[20]; __I uint32_t MCS1_CH6_MHB; /**< MCS[i] channel x memory high byte register, offset: 0x263C */ uint8_t RESERVED_77[160]; __IO uint32_t MCS1_CH6_PC; /**< MCS[i] channel x program counter register, offset: 0x26E0 */ __IO uint32_t MCS1_CH6_IRQ_NOTIFY; /**< MCS[i] channel x interrupt notification register, offset: 0x26E4 */ __IO uint32_t MCS1_CH6_IRQ_EN; /**< MCS[i] channel x interrupt enable register, offset: 0x26E8 */ __IO uint32_t MCS1_CH6_IRQ_FORCINT; /**< MCS[i] channel x force interrupt register, offset: 0x26EC */ __IO uint32_t MCS1_CH6_IRQ_MODE; /**< MCS[i] channel x IRQ mode configuration register, offset: 0x26F0 */ __IO uint32_t MCS1_CH6_EIRQ_EN; /**< MCS[i] channel x error interrupt enable register, offset: 0x26F4 */ uint8_t RESERVED_78[8]; __IO uint32_t MCS1_CH7_R0; /**< MCS[i] channel x general purpose register [y], offset: 0x2700 */ __IO uint32_t MCS1_CH7_R1; /**< MCS[i] channel x general purpose register [y], offset: 0x2704 */ __IO uint32_t MCS1_CH7_R2; /**< MCS[i] channel x general purpose register [y], offset: 0x2708 */ __IO uint32_t MCS1_CH7_R3; /**< MCS[i] channel x general purpose register [y], offset: 0x270C */ __IO uint32_t MCS1_CH7_R4; /**< MCS[i] channel x general purpose register [y], offset: 0x2710 */ __IO uint32_t MCS1_CH7_R5; /**< MCS[i] channel x general purpose register [y], offset: 0x2714 */ __IO uint32_t MCS1_CH7_R6; /**< MCS[i] channel x general purpose register [y], offset: 0x2718 */ __IO uint32_t MCS1_CH7_R7; /**< MCS[i] channel x general purpose register [y], offset: 0x271C */ __IO uint32_t MCS1_CH7_CTRL; /**< MCS[i] channel x control register, offset: 0x2720 */ __I uint32_t MCS1_CH7_ACB; /**< MCS[i] channel x ARU control Bit register, offset: 0x2724 */ uint8_t RESERVED_79[20]; __I uint32_t MCS1_CH7_MHB; /**< MCS[i] channel x memory high byte register, offset: 0x273C */ uint8_t RESERVED_80[160]; __IO uint32_t MCS1_CH7_PC; /**< MCS[i] channel x program counter register, offset: 0x27E0 */ __IO uint32_t MCS1_CH7_IRQ_NOTIFY; /**< MCS[i] channel x interrupt notification register, offset: 0x27E4 */ __IO uint32_t MCS1_CH7_IRQ_EN; /**< MCS[i] channel x interrupt enable register, offset: 0x27E8 */ __IO uint32_t MCS1_CH7_IRQ_FORCINT; /**< MCS[i] channel x force interrupt register, offset: 0x27EC */ __IO uint32_t MCS1_CH7_IRQ_MODE; /**< MCS[i] channel x IRQ mode configuration register, offset: 0x27F0 */ __IO uint32_t MCS1_CH7_EIRQ_EN; /**< MCS[i] channel x error interrupt enable register, offset: 0x27F4 */ uint8_t RESERVED_81[1584]; __IO uint32_t MCS1_CTRG; /**< MCS[i] clear trigger control register, offset: 0x2E28 */ __IO uint32_t MCS1_STRG; /**< MCS[i] set trigger control register, offset: 0x2E2C */ uint8_t RESERVED_82[208]; __IO uint32_t MCS1_CTRL_STAT; /**< MCS[i] control and status register, offset: 0x2F00 */ __IO uint32_t MCS1_RESET; /**< MCS[i] reset register, offset: 0x2F04 */ __IO uint32_t MCS1_CAT; /**< MCS[i] cancel ARU transfer instruction, offset: 0x2F08 */ __IO uint32_t MCS1_CWT; /**< MCS[i] cancel waiting instruction, offset: 0x2F0C */ __IO uint32_t MCS1_ERR; /**< MCS[i] error register, offset: 0x2F10 */ uint8_t RESERVED_83[8]; __IO uint32_t MCS1_REG_PROT; /**< MCS[i] write protection register, offset: 0x2F1C */ __IO uint32_t MCS1_SINT_IRQ_NOTIFY; /**< MCS[i] shared interrupt notification register, offset: 0x2F20 */ __IO uint32_t MCS1_SINT_IRQ_EN; /**< MCS[i] shared interrupt enable register, offset: 0x2F24 */ __IO uint32_t MCS1_SINT_IRQ_FORCINT; /**< MCS[i] force shared interrupt register, offset: 0x2F28 */ __IO uint32_t MCS1_SINT_IRQ_MODE; /**< MCS[i] shared interrupt mode configuration register, offset: 0x2F2C */ uint8_t RESERVED_84[16]; __IO uint32_t MCS1_HBP0_CTRL; /**< MCS[i] hardware break point h control register, offset: 0x2F40 */ __IO uint32_t MCS1_HBP0_PATTERN; /**< MCS[i] hardware break point pattern register, offset: 0x2F44 */ __IO uint32_t MCS1_HBP0_STATUS; /**< MCS[i] hardware break point status register, offset: 0x2F48 */ __IO uint32_t MCS1_HBP0_IRQ_NOTIFY; /**< MCS[i] hardware break point interrupt notification register, offset: 0x2F4C */ __IO uint32_t MCS1_HBP0_IRQ_EN; /**< MCS[i] hardware break point interrupt enable register, offset: 0x2F50 */ __IO uint32_t MCS1_HBP0_IRQ_FORCINT; /**< MCS[i] force hardware break point interrupt register, offset: 0x2F54 */ __IO uint32_t MCS1_HBP0_IRQ_MODE; /**< MCS[i] break point h interrupt mode configuration register, offset: 0x2F58 */ uint8_t RESERVED_85[4]; __IO uint32_t MCS1_HBP1_CTRL; /**< MCS[i] hardware break point h control register, offset: 0x2F60 */ __IO uint32_t MCS1_HBP1_PATTERN; /**< MCS[i] hardware break point pattern register, offset: 0x2F64 */ __IO uint32_t MCS1_HBP1_STATUS; /**< MCS[i] hardware break point status register, offset: 0x2F68 */ __IO uint32_t MCS1_HBP1_IRQ_NOTIFY; /**< MCS[i] hardware break point interrupt notification register, offset: 0x2F6C */ __IO uint32_t MCS1_HBP1_IRQ_EN; /**< MCS[i] hardware break point interrupt enable register, offset: 0x2F70 */ __IO uint32_t MCS1_HBP1_IRQ_FORCINT; /**< MCS[i] force hardware break point interrupt register, offset: 0x2F74 */ __IO uint32_t MCS1_HBP1_IRQ_MODE; /**< MCS[i] break point h interrupt mode configuration register, offset: 0x2F78 */ uint8_t RESERVED_86[132]; __IO uint32_t TIO1_G0_CH0_CTRL; /**< TIO[i] group [g] channel [c] control register, offset: 0x3000 */ __IO uint32_t TIO1_G0_CH0_IRQ_NOTIFY; /**< TIO[i] channel [c] interrupt notification register, offset: 0x3004 */ __IO uint32_t TIO1_G0_CH0_IRQ_EN; /**< TIO[i] channel [c] interrupt enable register, offset: 0x3008 */ __IO uint32_t TIO1_G0_CH0_IRQ_FORCINT; /**< TIO[i] channel [c] force interrupt register, offset: 0x300C */ __IO uint32_t TIO1_G0_CH0_IRQ_MODE; /**< TIO[i] channel [c] IRQ mode configuration register, offset: 0x3010 */ __IO uint32_t TIO1_G0_CH0_CTRL2; /**< TIO[i] group [g] channel [c] control register, offset: 0x3014 */ uint8_t RESERVED_87[8]; __IO uint32_t TIO1_G0_CH0_SINST; /**< TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x3020 */ __IO uint32_t TIO1_G0_CH0_SCMD; /**< TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x3024 */ __IO uint32_t TIO1_G0_CH0_SOP; /**< TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ), offset: 0x3028 */ uint8_t RESERVED_88[4]; __IO uint32_t TIO1_G0_CH0_OINST; /**< TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00-, offset: 0x3030 */ __IO uint32_t TIO1_G0_CH0_OCMD; /**< TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00-, offset: 0x3034 */ __IO uint32_t TIO1_G0_CH0_OOP; /**< TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-), offset: 0x3038 */ __I uint32_t TIO1_G0_CH0_SHIFTCNT; /**< TIO[i] channel [c] resource shift count register, offset: 0x303C */ __IO uint32_t TIO1_G0_CH1_CTRL; /**< TIO[i] group [g] channel [c] control register, offset: 0x3040 */ __IO uint32_t TIO1_G0_CH1_IRQ_NOTIFY; /**< TIO[i] channel [c] interrupt notification register, offset: 0x3044 */ __IO uint32_t TIO1_G0_CH1_IRQ_EN; /**< TIO[i] channel [c] interrupt enable register, offset: 0x3048 */ __IO uint32_t TIO1_G0_CH1_IRQ_FORCINT; /**< TIO[i] channel [c] force interrupt register, offset: 0x304C */ __IO uint32_t TIO1_G0_CH1_IRQ_MODE; /**< TIO[i] channel [c] IRQ mode configuration register, offset: 0x3050 */ __IO uint32_t TIO1_G0_CH1_CTRL2; /**< TIO[i] group [g] channel [c] control register, offset: 0x3054 */ uint8_t RESERVED_89[8]; __IO uint32_t TIO1_G0_CH1_SINST; /**< TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x3060 */ __IO uint32_t TIO1_G0_CH1_SCMD; /**< TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x3064 */ __IO uint32_t TIO1_G0_CH1_SOP; /**< TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ), offset: 0x3068 */ uint8_t RESERVED_90[4]; __IO uint32_t TIO1_G0_CH1_OINST; /**< TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00-, offset: 0x3070 */ __IO uint32_t TIO1_G0_CH1_OCMD; /**< TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00-, offset: 0x3074 */ __IO uint32_t TIO1_G0_CH1_OOP; /**< TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-), offset: 0x3078 */ __I uint32_t TIO1_G0_CH1_SHIFTCNT; /**< TIO[i] channel [c] resource shift count register, offset: 0x307C */ __IO uint32_t TIO1_G0_CH2_CTRL; /**< TIO[i] group [g] channel [c] control register, offset: 0x3080 */ __IO uint32_t TIO1_G0_CH2_IRQ_NOTIFY; /**< TIO[i] channel [c] interrupt notification register, offset: 0x3084 */ __IO uint32_t TIO1_G0_CH2_IRQ_EN; /**< TIO[i] channel [c] interrupt enable register, offset: 0x3088 */ __IO uint32_t TIO1_G0_CH2_IRQ_FORCINT; /**< TIO[i] channel [c] force interrupt register, offset: 0x308C */ __IO uint32_t TIO1_G0_CH2_IRQ_MODE; /**< TIO[i] channel [c] IRQ mode configuration register, offset: 0x3090 */ __IO uint32_t TIO1_G0_CH2_CTRL2; /**< TIO[i] group [g] channel [c] control register, offset: 0x3094 */ uint8_t RESERVED_91[8]; __IO uint32_t TIO1_G0_CH2_SINST; /**< TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x30A0 */ __IO uint32_t TIO1_G0_CH2_SCMD; /**< TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x30A4 */ __IO uint32_t TIO1_G0_CH2_SOP; /**< TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ), offset: 0x30A8 */ uint8_t RESERVED_92[4]; __IO uint32_t TIO1_G0_CH2_OINST; /**< TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00-, offset: 0x30B0 */ __IO uint32_t TIO1_G0_CH2_OCMD; /**< TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00-, offset: 0x30B4 */ __IO uint32_t TIO1_G0_CH2_OOP; /**< TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-), offset: 0x30B8 */ __I uint32_t TIO1_G0_CH2_SHIFTCNT; /**< TIO[i] channel [c] resource shift count register, offset: 0x30BC */ __IO uint32_t TIO1_G0_CH3_CTRL; /**< TIO[i] group [g] channel [c] control register, offset: 0x30C0 */ __IO uint32_t TIO1_G0_CH3_IRQ_NOTIFY; /**< TIO[i] channel [c] interrupt notification register, offset: 0x30C4 */ __IO uint32_t TIO1_G0_CH3_IRQ_EN; /**< TIO[i] channel [c] interrupt enable register, offset: 0x30C8 */ __IO uint32_t TIO1_G0_CH3_IRQ_FORCINT; /**< TIO[i] channel [c] force interrupt register, offset: 0x30CC */ __IO uint32_t TIO1_G0_CH3_IRQ_MODE; /**< TIO[i] channel [c] IRQ mode configuration register, offset: 0x30D0 */ __IO uint32_t TIO1_G0_CH3_CTRL2; /**< TIO[i] group [g] channel [c] control register, offset: 0x30D4 */ uint8_t RESERVED_93[8]; __IO uint32_t TIO1_G0_CH3_SINST; /**< TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x30E0 */ __IO uint32_t TIO1_G0_CH3_SCMD; /**< TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x30E4 */ __IO uint32_t TIO1_G0_CH3_SOP; /**< TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ), offset: 0x30E8 */ uint8_t RESERVED_94[4]; __IO uint32_t TIO1_G0_CH3_OINST; /**< TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00-, offset: 0x30F0 */ __IO uint32_t TIO1_G0_CH3_OCMD; /**< TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00-, offset: 0x30F4 */ __IO uint32_t TIO1_G0_CH3_OOP; /**< TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-), offset: 0x30F8 */ __I uint32_t TIO1_G0_CH3_SHIFTCNT; /**< TIO[i] channel [c] resource shift count register, offset: 0x30FC */ __IO uint32_t TIO1_G0_CH4_CTRL; /**< TIO[i] group [g] channel [c] control register, offset: 0x3100 */ __IO uint32_t TIO1_G0_CH4_IRQ_NOTIFY; /**< TIO[i] channel [c] interrupt notification register, offset: 0x3104 */ __IO uint32_t TIO1_G0_CH4_IRQ_EN; /**< TIO[i] channel [c] interrupt enable register, offset: 0x3108 */ __IO uint32_t TIO1_G0_CH4_IRQ_FORCINT; /**< TIO[i] channel [c] force interrupt register, offset: 0x310C */ __IO uint32_t TIO1_G0_CH4_IRQ_MODE; /**< TIO[i] channel [c] IRQ mode configuration register, offset: 0x3110 */ __IO uint32_t TIO1_G0_CH4_CTRL2; /**< TIO[i] group [g] channel [c] control register, offset: 0x3114 */ uint8_t RESERVED_95[8]; __IO uint32_t TIO1_G0_CH4_SINST; /**< TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x3120 */ __IO uint32_t TIO1_G0_CH4_SCMD; /**< TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x3124 */ __IO uint32_t TIO1_G0_CH4_SOP; /**< TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ), offset: 0x3128 */ uint8_t RESERVED_96[4]; __IO uint32_t TIO1_G0_CH4_OINST; /**< TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00-, offset: 0x3130 */ __IO uint32_t TIO1_G0_CH4_OCMD; /**< TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00-, offset: 0x3134 */ __IO uint32_t TIO1_G0_CH4_OOP; /**< TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-), offset: 0x3138 */ __I uint32_t TIO1_G0_CH4_SHIFTCNT; /**< TIO[i] channel [c] resource shift count register, offset: 0x313C */ __IO uint32_t TIO1_G0_CH5_CTRL; /**< TIO[i] group [g] channel [c] control register, offset: 0x3140 */ __IO uint32_t TIO1_G0_CH5_IRQ_NOTIFY; /**< TIO[i] channel [c] interrupt notification register, offset: 0x3144 */ __IO uint32_t TIO1_G0_CH5_IRQ_EN; /**< TIO[i] channel [c] interrupt enable register, offset: 0x3148 */ __IO uint32_t TIO1_G0_CH5_IRQ_FORCINT; /**< TIO[i] channel [c] force interrupt register, offset: 0x314C */ __IO uint32_t TIO1_G0_CH5_IRQ_MODE; /**< TIO[i] channel [c] IRQ mode configuration register, offset: 0x3150 */ __IO uint32_t TIO1_G0_CH5_CTRL2; /**< TIO[i] group [g] channel [c] control register, offset: 0x3154 */ uint8_t RESERVED_97[8]; __IO uint32_t TIO1_G0_CH5_SINST; /**< TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x3160 */ __IO uint32_t TIO1_G0_CH5_SCMD; /**< TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x3164 */ __IO uint32_t TIO1_G0_CH5_SOP; /**< TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ), offset: 0x3168 */ uint8_t RESERVED_98[4]; __IO uint32_t TIO1_G0_CH5_OINST; /**< TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00-, offset: 0x3170 */ __IO uint32_t TIO1_G0_CH5_OCMD; /**< TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00-, offset: 0x3174 */ __IO uint32_t TIO1_G0_CH5_OOP; /**< TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-), offset: 0x3178 */ __I uint32_t TIO1_G0_CH5_SHIFTCNT; /**< TIO[i] channel [c] resource shift count register, offset: 0x317C */ __IO uint32_t TIO1_G0_CH6_CTRL; /**< TIO[i] group [g] channel [c] control register, offset: 0x3180 */ __IO uint32_t TIO1_G0_CH6_IRQ_NOTIFY; /**< TIO[i] channel [c] interrupt notification register, offset: 0x3184 */ __IO uint32_t TIO1_G0_CH6_IRQ_EN; /**< TIO[i] channel [c] interrupt enable register, offset: 0x3188 */ __IO uint32_t TIO1_G0_CH6_IRQ_FORCINT; /**< TIO[i] channel [c] force interrupt register, offset: 0x318C */ __IO uint32_t TIO1_G0_CH6_IRQ_MODE; /**< TIO[i] channel [c] IRQ mode configuration register, offset: 0x3190 */ __IO uint32_t TIO1_G0_CH6_CTRL2; /**< TIO[i] group [g] channel [c] control register, offset: 0x3194 */ uint8_t RESERVED_99[8]; __IO uint32_t TIO1_G0_CH6_SINST; /**< TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x31A0 */ __IO uint32_t TIO1_G0_CH6_SCMD; /**< TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x31A4 */ __IO uint32_t TIO1_G0_CH6_SOP; /**< TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ), offset: 0x31A8 */ uint8_t RESERVED_100[4]; __IO uint32_t TIO1_G0_CH6_OINST; /**< TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00-, offset: 0x31B0 */ __IO uint32_t TIO1_G0_CH6_OCMD; /**< TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00-, offset: 0x31B4 */ __IO uint32_t TIO1_G0_CH6_OOP; /**< TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-), offset: 0x31B8 */ __I uint32_t TIO1_G0_CH6_SHIFTCNT; /**< TIO[i] channel [c] resource shift count register, offset: 0x31BC */ __IO uint32_t TIO1_G0_CH7_CTRL; /**< TIO[i] group [g] channel [c] control register, offset: 0x31C0 */ __IO uint32_t TIO1_G0_CH7_IRQ_NOTIFY; /**< TIO[i] channel [c] interrupt notification register, offset: 0x31C4 */ __IO uint32_t TIO1_G0_CH7_IRQ_EN; /**< TIO[i] channel [c] interrupt enable register, offset: 0x31C8 */ __IO uint32_t TIO1_G0_CH7_IRQ_FORCINT; /**< TIO[i] channel [c] force interrupt register, offset: 0x31CC */ __IO uint32_t TIO1_G0_CH7_IRQ_MODE; /**< TIO[i] channel [c] IRQ mode configuration register, offset: 0x31D0 */ __IO uint32_t TIO1_G0_CH7_CTRL2; /**< TIO[i] group [g] channel [c] control register, offset: 0x31D4 */ uint8_t RESERVED_101[8]; __IO uint32_t TIO1_G0_CH7_SINST; /**< TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x31E0 */ __IO uint32_t TIO1_G0_CH7_SCMD; /**< TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x31E4 */ __IO uint32_t TIO1_G0_CH7_SOP; /**< TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ), offset: 0x31E8 */ uint8_t RESERVED_102[4]; __IO uint32_t TIO1_G0_CH7_OINST; /**< TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00-, offset: 0x31F0 */ __IO uint32_t TIO1_G0_CH7_OCMD; /**< TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00-, offset: 0x31F4 */ __IO uint32_t TIO1_G0_CH7_OOP; /**< TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-), offset: 0x31F8 */ __I uint32_t TIO1_G0_CH7_SHIFTCNT; /**< TIO[i] channel [c] resource shift count register, offset: 0x31FC */ __IO uint32_t TIO1_G0_ISEL0_CTRL1; /**< TIO[i] input selection register 1, offset: 0x3200 */ __IO uint32_t TIO1_G0_ISEL0_CTRL2; /**< TIO[i] input selection register 2, offset: 0x3204 */ uint8_t RESERVED_103[24]; __IO uint32_t TIO1_G0_ISEL1_CTRL1; /**< TIO[i] input selection register 1, offset: 0x3220 */ __IO uint32_t TIO1_G0_ISEL1_CTRL2; /**< TIO[i] input selection register 2, offset: 0x3224 */ uint8_t RESERVED_104[24]; __IO uint32_t TIO1_G0_OP_USAGE; /**< TIO[i] operand usage selection register, offset: 0x3240 */ uint8_t RESERVED_105[2492]; __IO uint32_t TIO1_S; /**< TIO[i] signal sampling register, offset: 0x3C00 */ __IO uint32_t TIO1_O; /**< TIO[i] output register, offset: 0x3C04 */ __IO uint32_t TIO1_ENDIS; /**< TIO[i] enable/disable register, offset: 0x3C08 */ __IO uint32_t TIO1_INVERT; /**< TIO[i] signal invert register, offset: 0x3C0C */ __IO uint32_t TIO1_INPUT_MODE; /**< TIO[i] input mode register, offset: 0x3C10 */ __IO uint32_t TIO1_CYCLIC_MODE; /**< TIO[i] cyclic mode register, offset: 0x3C14 */ __IO uint32_t TIO1_TRIG_OUT_GATE_EN; /**< TIO[i] enable Trigger Output, output gating register, offset: 0x3C18 */ __IO uint32_t TIO1_PLTRIG_OUT_GATE_EN; /**< TIO[i] enable PL_TRIG_OUT output gating register, offset: 0x3C1C */ uint8_t RESERVED_106[32]; __IO uint32_t TIO1_CS; /**< TIO[i] clear signal sampling register, offset: 0x3C40 */ __IO uint32_t TIO1_CO; /**< TIO[i] clear output register, offset: 0x3C44 */ __IO uint32_t TIO1_CENDIS; /**< TIO[i] disable register, offset: 0x3C48 */ __IO uint32_t TIO1_CINVERT; /**< TIO[i] clear signal invert register, offset: 0x3C4C */ __IO uint32_t TIO1_CINPUT_MODE; /**< TIO[i] disable input mode register, offset: 0x3C50 */ __IO uint32_t TIO1_CCYCLIC_MODE; /**< TIO[i] disable cyclic mode register, offset: 0x3C54 */ __IO uint32_t TIO1_CTRIG_OUT_GATE_EN; /**< TIO[i] clear Trigger Output, output gating register, offset: 0x3C58 */ __IO uint32_t TIO1_CPLTRIG_OUT_GATE_EN; /**< TIO[i] clear PL_TRIG_OUT output gating register, offset: 0x3C5C */ uint8_t RESERVED_107[32]; __IO uint32_t TIO1_SS; /**< TIO[i] set signal sampling register, offset: 0x3C80 */ __IO uint32_t TIO1_SO; /**< TIO[i] set output register, offset: 0x3C84 */ __IO uint32_t TIO1_SENDIS; /**< TIO[i] enable register, offset: 0x3C88 */ __IO uint32_t TIO1_SINVERT; /**< TIO[i] set signal invert register, offset: 0x3C8C */ __IO uint32_t TIO1_SINPUT_MODE; /**< TIO[i] enable input mode register, offset: 0x3C90 */ __IO uint32_t TIO1_SCYCLIC_MODE; /**< TIO[i] enable cyclic mode register, offset: 0x3C94 */ __IO uint32_t TIO1_STRIG_OUT_GATE_EN; /**< TIO[i] set Trigger Output, output gating register, offset: 0x3C98 */ __IO uint32_t TIO1_SPLTRIG_OUT_GATE_EN; /**< TIO[i] set PL_TRIG_OUT output gating register, offset: 0x3C9C */ uint8_t RESERVED_108[32]; __IO uint32_t TIO1_IS; /**< TIO[i] invert signal sampling register, offset: 0x3CC0 */ __IO uint32_t TIO1_IO; /**< TIO[i] invert output register, offset: 0x3CC4 */ __IO uint32_t TIO1_IENDIS; /**< TIO[i] toggle enable/disable register, offset: 0x3CC8 */ __IO uint32_t TIO1_IINVERT; /**< TIO[i] toggle signal invert register, offset: 0x3CCC */ __IO uint32_t TIO1_IINPUT_MODE; /**< TIO[i] enable input mode register, offset: 0x3CD0 */ __IO uint32_t TIO1_ICYCLIC_MODE; /**< TIO[i] enable cyclic mode register, offset: 0x3CD4 */ uint8_t RESERVED_109[40]; __IO uint32_t TIO1_FUPD; /**< TIO[i] force update register, offset: 0x3D00 */ __I uint32_t TIO1_HW_CONF; /**< TIO[i] configuration register, offset: 0x3D04 */ __IO uint32_t TIO1_RSEL_CTRL1; /**< TIO[i] resource selection control register 1, offset: 0x3D08 */ __IO uint32_t TIO1_RSEL_CTRL2; /**< TIO[i] resource selection control register 2, offset: 0x3D0C */ __IO uint32_t TIO1_PL_SWRST; /**< TIO[i] software reset for TIO Plus functionality, offset: 0x3D10 */ uint8_t RESERVED_110[748]; __IO uint32_t CCM1_ARP0_CTRL; /**< CCM[i] Address Range Protector [a] Control Register, offset: 0x4000 */ __IO uint32_t CCM1_ARP0_PROT; /**< CCM[i] Address Range Protector [a] Protection Register, offset: 0x4004 */ __IO uint32_t CCM1_ARP1_CTRL; /**< CCM[i] Address Range Protector [a] Control Register, offset: 0x4008 */ __IO uint32_t CCM1_ARP1_PROT; /**< CCM[i] Address Range Protector [a] Protection Register, offset: 0x400C */ __IO uint32_t CCM1_ARP2_CTRL; /**< CCM[i] Address Range Protector [a] Control Register, offset: 0x4010 */ __IO uint32_t CCM1_ARP2_PROT; /**< CCM[i] Address Range Protector [a] Protection Register, offset: 0x4014 */ __IO uint32_t CCM1_ARP3_CTRL; /**< CCM[i] Address Range Protector [a] Control Register, offset: 0x4018 */ __IO uint32_t CCM1_ARP3_PROT; /**< CCM[i] Address Range Protector [a] Protection Register, offset: 0x401C */ __IO uint32_t CCM1_ARP4_CTRL; /**< CCM[i] Address Range Protector [a] Control Register, offset: 0x4020 */ __IO uint32_t CCM1_ARP4_PROT; /**< CCM[i] Address Range Protector [a] Protection Register, offset: 0x4024 */ __IO uint32_t CCM1_ARP5_CTRL; /**< CCM[i] Address Range Protector [a] Control Register, offset: 0x4028 */ __IO uint32_t CCM1_ARP5_PROT; /**< CCM[i] Address Range Protector [a] Protection Register, offset: 0x402C */ __IO uint32_t CCM1_ARP6_CTRL; /**< CCM[i] Address Range Protector [a] Control Register, offset: 0x4030 */ __IO uint32_t CCM1_ARP6_PROT; /**< CCM[i] Address Range Protector [a] Protection Register, offset: 0x4034 */ __IO uint32_t CCM1_ARP7_CTRL; /**< CCM[i] Address Range Protector [a] Control Register, offset: 0x4038 */ __IO uint32_t CCM1_ARP7_PROT; /**< CCM[i] Address Range Protector [a] Protection Register, offset: 0x403C */ __IO uint32_t CCM1_ARP8_CTRL; /**< CCM[i] Address Range Protector [a] Control Register, offset: 0x4040 */ __IO uint32_t CCM1_ARP8_PROT; /**< CCM[i] Address Range Protector [a] Protection Register, offset: 0x4044 */ __IO uint32_t CCM1_ARP9_CTRL; /**< CCM[i] Address Range Protector [a] Control Register, offset: 0x4048 */ __IO uint32_t CCM1_ARP9_PROT; /**< CCM[i] Address Range Protector [a] Protection Register, offset: 0x404C */ uint8_t RESERVED_111[380]; __I uint32_t CCM1_TIO_G0_OUT; /**< CCM[i] TIO Group 0,1 Output Register, offset: 0x41CC */ uint8_t RESERVED_112[4]; __I uint32_t CCM1_HW_CONF2; /**< CCM[i] 2. Hardware Configuration Register, offset: 0x41D4 */ __IO uint32_t CCM1_AEIM_STA; /**< CCM[i] MCS Bus Master Status Register, offset: 0x41D8 */ __I uint32_t CCM1_HW_CONF; /**< CCM[i] Hardware Configuration Register, offset: 0x41DC */ __IO uint32_t CCM1_TIM_AUX_IN_SRC; /**< CCM[i] TIM AUX Input Source Register, offset: 0x41E0 */ __IO uint32_t CCM1_EXT_CAP_EN; /**< CCM[i] External Capture Enable Register, offset: 0x41E4 */ __I uint32_t CCM1_TOM_OUT; /**< CCM[i] TOM Output Register, offset: 0x41E8 */ __I uint32_t CCM1_ATOM_OUT; /**< CCM[i] ATOM Output Register, offset: 0x41EC */ __IO uint32_t CCM1_CMU_CLK_CFG; /**< CCM[i] CMU Clock Configuration Register, offset: 0x41F0 */ __IO uint32_t CCM1_CMU_FXCLK_CFG; /**< CCM[i] CMU Fixed Clock Configuration Register, offset: 0x41F4 */ __IO uint32_t CCM1_CFG; /**< CCM[i] Configuration Register, offset: 0x41F8 */ __IO uint32_t CCM1_PROT; /**< CCM[i] Protection Register, offset: 0x41FC */ uint8_t RESERVED_113[768]; __IO uint32_t CDTM1_DTM4_CTRL; /**< CDTM[i]_DTM[d] global configuration and control register, offset: 0x4500 */ __IO uint32_t CDTM1_DTM4_CH_CTRL1; /**< CDTM[i]_DTM[d] channel control register 1, offset: 0x4504 */ __IO uint32_t CDTM1_DTM4_CH_CTRL2; /**< CDTM[i]_DTM[d] channel control register 2, offset: 0x4508 */ __IO uint32_t CDTM1_DTM4_CH_CTRL2_SR; /**< CDTM[i] DTM[j] channel control register 2 shadow, offset: 0x450C */ __IO uint32_t CDTM1_DTM4_PS_CTRL; /**< CDTM[i]_DTM[d] phase shift unit configuration and control register, offset: 0x4510 */ __IO uint32_t CDTM1_DTM4_CH_DTV[GTM_gtm_cls1_CDTM1_DTM4_CH4_DTV_COUNT]; /**< CDTM[i]_DTM[d] channel [x] dead time reload values, array offset: 0x4514, array step: 0x4 */ __IO uint32_t CDTM1_DTM4_CH_SR; /**< CDTM[i]_DTM[d] channel shadow register, offset: 0x4524 */ __IO uint32_t CDTM1_DTM4_CH_CTRL3; /**< CDTM[i]_DTM[d] channel control register 3, offset: 0x4528 */ __IO uint32_t CDTM1_DTM4_CTRL2; /**< CDTM[i]_DTM[d] global configuration and control register 2, offset: 0x452C */ __IO uint32_t CDTM1_DTM4_CH0_DTV_SR; /**< CDTM[i]_DTM[d] channel [x] dead time shadow values, offset: 0x4530 */ __IO uint32_t CDTM1_DTM4_CH1_DTV_SR; /**< CDTM[i]_DTM[d] channel [x] dead time shadow values, offset: 0x4534 */ __IO uint32_t CDTM1_DTM4_CH2_DTV_SR; /**< CDTM[i]_DTM[d] channel [x] dead time shadow values, offset: 0x4538 */ __IO uint32_t CDTM1_DTM4_CH3_DTV_SR; /**< CDTM[i]_DTM[d] channel [x] dead time shadow values, offset: 0x453C */ __IO uint32_t CDTM1_DTM5_CTRL; /**< CDTM[i]_DTM[d] global configuration and control register, offset: 0x4540 */ __IO uint32_t CDTM1_DTM5_CH_CTRL1; /**< CDTM[i]_DTM[d] channel control register 1, offset: 0x4544 */ __IO uint32_t CDTM1_DTM5_CH_CTRL2; /**< CDTM[i]_DTM[d] channel control register 2, offset: 0x4548 */ __IO uint32_t CDTM1_DTM5_CH_CTRL2_SR; /**< CDTM[i] DTM[j] channel control register 2 shadow, offset: 0x454C */ __IO uint32_t CDTM1_DTM5_PS_CTRL; /**< CDTM[i]_DTM[d] phase shift unit configuration and control register, offset: 0x4550 */ __IO uint32_t CDTM1_DTM5_CH_DTV[GTM_gtm_cls1_CDTM1_DTM5_CH4_DTV_COUNT]; /**< CDTM[i]_DTM[d] channel [x] dead time reload values, array offset: 0x4554, array step: 0x4 */ __IO uint32_t CDTM1_DTM5_CH_SR; /**< CDTM[i]_DTM[d] channel shadow register, offset: 0x4564 */ __IO uint32_t CDTM1_DTM5_CH_CTRL3; /**< CDTM[i]_DTM[d] channel control register 3, offset: 0x4568 */ __IO uint32_t CDTM1_DTM5_CTRL2; /**< CDTM[i]_DTM[d] global configuration and control register 2, offset: 0x456C */ __IO uint32_t CDTM1_DTM5_CH0_DTV_SR; /**< CDTM[i]_DTM[d] channel [x] dead time shadow values, offset: 0x4570 */ __IO uint32_t CDTM1_DTM5_CH1_DTV_SR; /**< CDTM[i]_DTM[d] channel [x] dead time shadow values, offset: 0x4574 */ __IO uint32_t CDTM1_DTM5_CH2_DTV_SR; /**< CDTM[i]_DTM[d] channel [x] dead time shadow values, offset: 0x4578 */ __IO uint32_t CDTM1_DTM5_CH3_DTV_SR; /**< CDTM[i]_DTM[d] channel [x] dead time shadow values, offset: 0x457C */ uint8_t RESERVED_114[1664]; __IO uint32_t SPE1_CTRL_STAT; /**< SPE[i] Control Status Register, offset: 0x4C00 */ __IO uint32_t SPE1_PAT; /**< SPE[i] Input Pattern Definition Register, offset: 0x4C04 */ __IO uint32_t SPE1_OUT_PAT0; /**< SPE[i] Output Definition Register, offset: 0x4C08 */ __IO uint32_t SPE1_OUT_PAT1; /**< SPE[i] Output Definition Register, offset: 0x4C0C */ __IO uint32_t SPE1_OUT_PAT2; /**< SPE[i] Output Definition Register, offset: 0x4C10 */ __IO uint32_t SPE1_OUT_PAT3; /**< SPE[i] Output Definition Register, offset: 0x4C14 */ __IO uint32_t SPE1_OUT_PAT4; /**< SPE[i] Output Definition Register, offset: 0x4C18 */ __IO uint32_t SPE1_OUT_PAT5; /**< SPE[i] Output Definition Register, offset: 0x4C1C */ __IO uint32_t SPE1_OUT_PAT6; /**< SPE[i] Output Definition Register, offset: 0x4C20 */ __IO uint32_t SPE1_OUT_PAT7; /**< SPE[i] Output Definition Register, offset: 0x4C24 */ __IO uint32_t SPE1_OUT_CTRL; /**< SPE[i] Output Control Register, offset: 0x4C28 */ __IO uint32_t SPE1_IRQ_NOTIFY; /**< SPE[i] Interrupt Notification Register, offset: 0x4C2C */ __IO uint32_t SPE1_IRQ_EN; /**< SPE[i] Interrupt Enable Register, offset: 0x4C30 */ __IO uint32_t SPE1_IRQ_FORCINT; /**< SPE[i] Interrupt Generation By Software, offset: 0x4C34 */ __IO uint32_t SPE1_IRQ_MODE; /**< SPE[i] Interrupt Mode Configuration Register, offset: 0x4C38 */ __IO uint32_t SPE1_EIRQ_EN; /**< SPE[i] Error Interrupt Enable Register, offset: 0x4C3C */ __IO uint32_t SPE1_REV_CNT; /**< SPE[i] Input Revolution Counter, offset: 0x4C40 */ __IO uint32_t SPE1_REV_CMP; /**< SPE[i] Revolution Counter Compare Value, offset: 0x4C44 */ __IO uint32_t SPE1_CTRL_STAT2; /**< SPE[i] Control Status Register 2, offset: 0x4C48 */ __IO uint32_t SPE1_CMD; /**< SPE[i] Command Register, offset: 0x4C4C */ uint8_t RESERVED_115[944]; __I uint32_t AXIM1_FREE; /**< AXIM[i] slot allocation status., offset: 0x5000 */ __I uint32_t AXIM1_REQUEST; /**< AXIM[i] slot request (allocation)., offset: 0x5004 */ __IO uint32_t AXIM1_RELEASE; /**< AXIM[i] slot release (de-allocation)., offset: 0x5008 */ uint8_t RESERVED_116[20]; __IO uint32_t AXIM1_SLOT0_ADDR_LOW; /**< AXIM[i] slot[s] address bits 31:0 of AXI transaction., offset: 0x5020 */ uint8_t RESERVED_117[4]; __IO uint32_t AXIM1_SLOT0_DATA_LOW; /**< AXIM[i] slot[s] data bits 31:0 of AXI transaction., offset: 0x5028 */ uint8_t RESERVED_118[4]; __IO uint32_t AXIM1_SLOT0_CFG1; /**< AXIM[i] slot [s] configuration 1, offset: 0x5030 */ __IO uint32_t AXIM1_SLOT0_CFG2; /**< AXIM[i] slot[s] configuration 2, offset: 0x5034 */ __I uint32_t AXIM1_SLOT0_STATUS; /**< AXIM[i] slot[s] status, offset: 0x5038 */ uint8_t RESERVED_119[4]; __IO uint32_t AXIM1_SLOT1_ADDR_LOW; /**< AXIM[i] slot[s] address bits 31:0 of AXI transaction., offset: 0x5040 */ uint8_t RESERVED_120[4]; __IO uint32_t AXIM1_SLOT1_DATA_LOW; /**< AXIM[i] slot[s] data bits 31:0 of AXI transaction., offset: 0x5048 */ uint8_t RESERVED_121[4]; __IO uint32_t AXIM1_SLOT1_CFG1; /**< AXIM[i] slot [s] configuration 1, offset: 0x5050 */ __IO uint32_t AXIM1_SLOT1_CFG2; /**< AXIM[i] slot[s] configuration 2, offset: 0x5054 */ __I uint32_t AXIM1_SLOT1_STATUS; /**< AXIM[i] slot[s] status, offset: 0x5058 */ uint8_t RESERVED_122[4]; __IO uint32_t AXIM1_SLOT2_ADDR_LOW; /**< AXIM[i] slot[s] address bits 31:0 of AXI transaction., offset: 0x5060 */ uint8_t RESERVED_123[4]; __IO uint32_t AXIM1_SLOT2_DATA_LOW; /**< AXIM[i] slot[s] data bits 31:0 of AXI transaction., offset: 0x5068 */ uint8_t RESERVED_124[4]; __IO uint32_t AXIM1_SLOT2_CFG1; /**< AXIM[i] slot [s] configuration 1, offset: 0x5070 */ __IO uint32_t AXIM1_SLOT2_CFG2; /**< AXIM[i] slot[s] configuration 2, offset: 0x5074 */ __I uint32_t AXIM1_SLOT2_STATUS; /**< AXIM[i] slot[s] status, offset: 0x5078 */ uint8_t RESERVED_125[4]; __IO uint32_t AXIM1_SLOT3_ADDR_LOW; /**< AXIM[i] slot[s] address bits 31:0 of AXI transaction., offset: 0x5080 */ uint8_t RESERVED_126[4]; __IO uint32_t AXIM1_SLOT3_DATA_LOW; /**< AXIM[i] slot[s] data bits 31:0 of AXI transaction., offset: 0x5088 */ uint8_t RESERVED_127[4]; __IO uint32_t AXIM1_SLOT3_CFG1; /**< AXIM[i] slot [s] configuration 1, offset: 0x5090 */ __IO uint32_t AXIM1_SLOT3_CFG2; /**< AXIM[i] slot[s] configuration 2, offset: 0x5094 */ __I uint32_t AXIM1_SLOT3_STATUS; /**< AXIM[i] slot[s] status, offset: 0x5098 */ uint8_t RESERVED_128[44900]; __IO uint32_t MCS1_MEM[GTM_gtm_cls1_MCS1_MEM_COUNT]; /**< MCS[i] memory region, array offset: 0x10000, array step: 0x4 */ } GTM_gtm_cls1_Type, *GTM_gtm_cls1_MemMapPtr; /** Number of instances of the GTM_gtm_cls1 module. */ #define GTM_gtm_cls1_INSTANCE_COUNT (1u) /* GTM_gtm_cls1 - Peripheral instance base addresses */ /** Peripheral GTM_gtm_cls1 base address */ #define IP_GTM_gtm_cls1_BASE (0x73020000u) /** Peripheral GTM_gtm_cls1 base pointer */ #define IP_GTM_gtm_cls1 ((GTM_gtm_cls1_Type *)IP_GTM_gtm_cls1_BASE) /** Array initializer of GTM_gtm_cls1 peripheral base addresses */ #define IP_GTM_gtm_cls1_BASE_ADDRS { IP_GTM_gtm_cls1_BASE } /** Array initializer of GTM_gtm_cls1 peripheral base pointers */ #define IP_GTM_gtm_cls1_BASE_PTRS { IP_GTM_gtm_cls1 } /* ---------------------------------------------------------------------------- -- GTM_gtm_cls1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GTM_gtm_cls1_Register_Masks GTM_gtm_cls1 Register Masks * @{ */ /*! @name MON_STATUS - MON status register */ /*! @{ */ #define GTM_gtm_cls1_MON_STATUS_ACT_CMU0_MASK (0x1U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU0_SHIFT (0U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU0_WIDTH (1U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_STATUS_ACT_CMU0_SHIFT)) & GTM_gtm_cls1_MON_STATUS_ACT_CMU0_MASK) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU1_MASK (0x2U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU1_SHIFT (1U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU1_WIDTH (1U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_STATUS_ACT_CMU1_SHIFT)) & GTM_gtm_cls1_MON_STATUS_ACT_CMU1_MASK) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU2_MASK (0x4U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU2_SHIFT (2U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU2_WIDTH (1U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_STATUS_ACT_CMU2_SHIFT)) & GTM_gtm_cls1_MON_STATUS_ACT_CMU2_MASK) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU3_MASK (0x8U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU3_SHIFT (3U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU3_WIDTH (1U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_STATUS_ACT_CMU3_SHIFT)) & GTM_gtm_cls1_MON_STATUS_ACT_CMU3_MASK) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU4_MASK (0x10U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU4_SHIFT (4U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU4_WIDTH (1U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_STATUS_ACT_CMU4_SHIFT)) & GTM_gtm_cls1_MON_STATUS_ACT_CMU4_MASK) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU5_MASK (0x20U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU5_SHIFT (5U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU5_WIDTH (1U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_STATUS_ACT_CMU5_SHIFT)) & GTM_gtm_cls1_MON_STATUS_ACT_CMU5_MASK) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU6_MASK (0x40U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU6_SHIFT (6U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU6_WIDTH (1U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_STATUS_ACT_CMU6_SHIFT)) & GTM_gtm_cls1_MON_STATUS_ACT_CMU6_MASK) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU7_MASK (0x80U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU7_SHIFT (7U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU7_WIDTH (1U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_STATUS_ACT_CMU7_SHIFT)) & GTM_gtm_cls1_MON_STATUS_ACT_CMU7_MASK) #define GTM_gtm_cls1_MON_STATUS_ACT_CMUFX0_MASK (0x100U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMUFX0_SHIFT (8U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMUFX0_WIDTH (1U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMUFX0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_STATUS_ACT_CMUFX0_SHIFT)) & GTM_gtm_cls1_MON_STATUS_ACT_CMUFX0_MASK) #define GTM_gtm_cls1_MON_STATUS_ACT_CMUFX1_MASK (0x200U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMUFX1_SHIFT (9U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMUFX1_WIDTH (1U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMUFX1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_STATUS_ACT_CMUFX1_SHIFT)) & GTM_gtm_cls1_MON_STATUS_ACT_CMUFX1_MASK) #define GTM_gtm_cls1_MON_STATUS_ACT_CMUFX2_MASK (0x400U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMUFX2_SHIFT (10U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMUFX2_WIDTH (1U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMUFX2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_STATUS_ACT_CMUFX2_SHIFT)) & GTM_gtm_cls1_MON_STATUS_ACT_CMUFX2_MASK) #define GTM_gtm_cls1_MON_STATUS_ACT_CMUFX3_MASK (0x800U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMUFX3_SHIFT (11U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMUFX3_WIDTH (1U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMUFX3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_STATUS_ACT_CMUFX3_SHIFT)) & GTM_gtm_cls1_MON_STATUS_ACT_CMUFX3_MASK) #define GTM_gtm_cls1_MON_STATUS_ACT_CMUFX4_MASK (0x1000U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMUFX4_SHIFT (12U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMUFX4_WIDTH (1U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMUFX4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_STATUS_ACT_CMUFX4_SHIFT)) & GTM_gtm_cls1_MON_STATUS_ACT_CMUFX4_MASK) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU8_MASK (0x4000U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU8_SHIFT (14U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU8_WIDTH (1U) #define GTM_gtm_cls1_MON_STATUS_ACT_CMU8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_STATUS_ACT_CMU8_SHIFT)) & GTM_gtm_cls1_MON_STATUS_ACT_CMU8_MASK) #define GTM_gtm_cls1_MON_STATUS_CMP_ERR_MASK (0x10000U) #define GTM_gtm_cls1_MON_STATUS_CMP_ERR_SHIFT (16U) #define GTM_gtm_cls1_MON_STATUS_CMP_ERR_WIDTH (1U) #define GTM_gtm_cls1_MON_STATUS_CMP_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_STATUS_CMP_ERR_SHIFT)) & GTM_gtm_cls1_MON_STATUS_CMP_ERR_MASK) #define GTM_gtm_cls1_MON_STATUS_MCS0_ERR_MASK (0x100000U) #define GTM_gtm_cls1_MON_STATUS_MCS0_ERR_SHIFT (20U) #define GTM_gtm_cls1_MON_STATUS_MCS0_ERR_WIDTH (1U) #define GTM_gtm_cls1_MON_STATUS_MCS0_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_STATUS_MCS0_ERR_SHIFT)) & GTM_gtm_cls1_MON_STATUS_MCS0_ERR_MASK) #define GTM_gtm_cls1_MON_STATUS_MCS1_ERR_MASK (0x200000U) #define GTM_gtm_cls1_MON_STATUS_MCS1_ERR_SHIFT (21U) #define GTM_gtm_cls1_MON_STATUS_MCS1_ERR_WIDTH (1U) #define GTM_gtm_cls1_MON_STATUS_MCS1_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_STATUS_MCS1_ERR_SHIFT)) & GTM_gtm_cls1_MON_STATUS_MCS1_ERR_MASK) #define GTM_gtm_cls1_MON_STATUS_MCS2_ERR_MASK (0x400000U) #define GTM_gtm_cls1_MON_STATUS_MCS2_ERR_SHIFT (22U) #define GTM_gtm_cls1_MON_STATUS_MCS2_ERR_WIDTH (1U) #define GTM_gtm_cls1_MON_STATUS_MCS2_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_STATUS_MCS2_ERR_SHIFT)) & GTM_gtm_cls1_MON_STATUS_MCS2_ERR_MASK) #define GTM_gtm_cls1_MON_STATUS_MCS3_ERR_MASK (0x800000U) #define GTM_gtm_cls1_MON_STATUS_MCS3_ERR_SHIFT (23U) #define GTM_gtm_cls1_MON_STATUS_MCS3_ERR_WIDTH (1U) #define GTM_gtm_cls1_MON_STATUS_MCS3_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_STATUS_MCS3_ERR_SHIFT)) & GTM_gtm_cls1_MON_STATUS_MCS3_ERR_MASK) /*! @} */ /*! @name MON_ACTIVITY_0 - MON activity register 0 */ /*! @{ */ #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_0_MASK (0x1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_0_SHIFT (0U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_0_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_0_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_0_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_1_MASK (0x2U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_1_SHIFT (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_1_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_1_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_1_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_2_MASK (0x4U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_2_SHIFT (2U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_2_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_2_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_2_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_3_MASK (0x8U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_3_SHIFT (3U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_3_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_3_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_3_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_4_MASK (0x10U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_4_SHIFT (4U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_4_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_4_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_4_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_5_MASK (0x20U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_5_SHIFT (5U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_5_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_5_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_5_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_6_MASK (0x40U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_6_SHIFT (6U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_6_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_6_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_6_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_7_MASK (0x80U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_7_SHIFT (7U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_7_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_7_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_0_7_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_0_MASK (0x100U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_0_SHIFT (8U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_0_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_0_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_0_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_1_MASK (0x200U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_1_SHIFT (9U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_1_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_1_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_1_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_2_MASK (0x400U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_2_SHIFT (10U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_2_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_2_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_2_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_3_MASK (0x800U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_3_SHIFT (11U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_3_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_3_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_3_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_4_MASK (0x1000U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_4_SHIFT (12U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_4_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_4_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_4_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_5_MASK (0x2000U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_5_SHIFT (13U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_5_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_5_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_5_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_6_MASK (0x4000U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_6_SHIFT (14U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_6_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_6_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_6_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_7_MASK (0x8000U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_7_SHIFT (15U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_7_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_7_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_1_7_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_0_MASK (0x10000U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_0_SHIFT (16U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_0_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_0_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_0_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_1_MASK (0x20000U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_1_SHIFT (17U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_1_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_1_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_1_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_2_MASK (0x40000U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_2_SHIFT (18U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_2_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_2_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_2_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_3_MASK (0x80000U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_3_SHIFT (19U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_3_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_3_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_3_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_4_MASK (0x100000U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_4_SHIFT (20U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_4_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_4_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_4_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_5_MASK (0x200000U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_5_SHIFT (21U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_5_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_5_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_5_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_6_MASK (0x400000U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_6_SHIFT (22U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_6_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_6_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_6_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_7_MASK (0x800000U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_7_SHIFT (23U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_7_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_7_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_2_7_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_0_MASK (0x1000000U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_0_SHIFT (24U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_0_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_0_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_0_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_1_MASK (0x2000000U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_1_SHIFT (25U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_1_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_1_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_1_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_2_MASK (0x4000000U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_2_SHIFT (26U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_2_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_2_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_2_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_3_MASK (0x8000000U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_3_SHIFT (27U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_3_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_3_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_3_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_4_MASK (0x10000000U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_4_SHIFT (28U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_4_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_4_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_4_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_5_MASK (0x20000000U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_5_SHIFT (29U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_5_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_5_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_5_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_6_MASK (0x40000000U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_6_SHIFT (30U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_6_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_6_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_6_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_7_MASK (0x80000000U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_7_SHIFT (31U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_7_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_7_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_0_MCA_3_7_MASK) /*! @} */ /*! @name MON_ACTIVITY_MCS0 - MON activity register for MCS [j] */ /*! @{ */ #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_0_MASK (0x1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_0_SHIFT (0U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_0_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_0_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_0_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_1_MASK (0x2U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_1_SHIFT (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_1_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_1_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_1_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_2_MASK (0x4U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_2_SHIFT (2U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_2_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_2_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_2_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_3_MASK (0x8U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_3_SHIFT (3U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_3_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_3_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_3_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_4_MASK (0x10U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_4_SHIFT (4U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_4_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_4_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_4_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_5_MASK (0x20U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_5_SHIFT (5U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_5_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_5_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_5_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_6_MASK (0x40U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_6_SHIFT (6U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_6_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_6_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_6_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_7_MASK (0x80U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_7_SHIFT (7U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_7_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_7_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS0_MCA_7_MASK) /*! @} */ /*! @name MON_ACTIVITY_MCS1 - MON activity register for MCS [j] */ /*! @{ */ #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_0_MASK (0x1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_0_SHIFT (0U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_0_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_0_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_0_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_1_MASK (0x2U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_1_SHIFT (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_1_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_1_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_1_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_2_MASK (0x4U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_2_SHIFT (2U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_2_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_2_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_2_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_3_MASK (0x8U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_3_SHIFT (3U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_3_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_3_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_3_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_4_MASK (0x10U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_4_SHIFT (4U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_4_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_4_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_4_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_5_MASK (0x20U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_5_SHIFT (5U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_5_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_5_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_5_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_6_MASK (0x40U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_6_SHIFT (6U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_6_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_6_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_6_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_7_MASK (0x80U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_7_SHIFT (7U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_7_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_7_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS1_MCA_7_MASK) /*! @} */ /*! @name MON_ACTIVITY_MCS2 - MON activity register for MCS [j] */ /*! @{ */ #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_0_MASK (0x1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_0_SHIFT (0U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_0_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_0_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_0_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_1_MASK (0x2U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_1_SHIFT (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_1_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_1_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_1_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_2_MASK (0x4U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_2_SHIFT (2U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_2_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_2_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_2_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_3_MASK (0x8U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_3_SHIFT (3U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_3_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_3_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_3_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_4_MASK (0x10U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_4_SHIFT (4U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_4_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_4_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_4_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_5_MASK (0x20U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_5_SHIFT (5U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_5_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_5_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_5_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_6_MASK (0x40U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_6_SHIFT (6U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_6_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_6_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_6_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_7_MASK (0x80U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_7_SHIFT (7U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_7_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_7_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS2_MCA_7_MASK) /*! @} */ /*! @name MON_ACTIVITY_MCS3 - MON activity register for MCS [j] */ /*! @{ */ #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_0_MASK (0x1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_0_SHIFT (0U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_0_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_0_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_0_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_1_MASK (0x2U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_1_SHIFT (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_1_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_1_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_1_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_2_MASK (0x4U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_2_SHIFT (2U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_2_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_2_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_2_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_3_MASK (0x8U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_3_SHIFT (3U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_3_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_3_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_3_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_4_MASK (0x10U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_4_SHIFT (4U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_4_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_4_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_4_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_5_MASK (0x20U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_5_SHIFT (5U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_5_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_5_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_5_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_6_MASK (0x40U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_6_SHIFT (6U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_6_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_6_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_6_MASK) #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_7_MASK (0x80U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_7_SHIFT (7U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_7_WIDTH (1U) #define GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_7_SHIFT)) & GTM_gtm_cls1_MON_ACTIVITY_MCS3_MCA_7_MASK) /*! @} */ /*! @name CMP_EN - CMP comparator enable register */ /*! @{ */ #define GTM_gtm_cls1_CMP_EN_ABWC0_EN_MASK (0x1U) #define GTM_gtm_cls1_CMP_EN_ABWC0_EN_SHIFT (0U) #define GTM_gtm_cls1_CMP_EN_ABWC0_EN_WIDTH (1U) #define GTM_gtm_cls1_CMP_EN_ABWC0_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EN_ABWC0_EN_SHIFT)) & GTM_gtm_cls1_CMP_EN_ABWC0_EN_MASK) #define GTM_gtm_cls1_CMP_EN_ABWC1_EN_MASK (0x2U) #define GTM_gtm_cls1_CMP_EN_ABWC1_EN_SHIFT (1U) #define GTM_gtm_cls1_CMP_EN_ABWC1_EN_WIDTH (1U) #define GTM_gtm_cls1_CMP_EN_ABWC1_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EN_ABWC1_EN_SHIFT)) & GTM_gtm_cls1_CMP_EN_ABWC1_EN_MASK) #define GTM_gtm_cls1_CMP_EN_ABWC2_EN_MASK (0x4U) #define GTM_gtm_cls1_CMP_EN_ABWC2_EN_SHIFT (2U) #define GTM_gtm_cls1_CMP_EN_ABWC2_EN_WIDTH (1U) #define GTM_gtm_cls1_CMP_EN_ABWC2_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EN_ABWC2_EN_SHIFT)) & GTM_gtm_cls1_CMP_EN_ABWC2_EN_MASK) #define GTM_gtm_cls1_CMP_EN_ABWC3_EN_MASK (0x8U) #define GTM_gtm_cls1_CMP_EN_ABWC3_EN_SHIFT (3U) #define GTM_gtm_cls1_CMP_EN_ABWC3_EN_WIDTH (1U) #define GTM_gtm_cls1_CMP_EN_ABWC3_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EN_ABWC3_EN_SHIFT)) & GTM_gtm_cls1_CMP_EN_ABWC3_EN_MASK) #define GTM_gtm_cls1_CMP_EN_ABWC4_EN_MASK (0x10U) #define GTM_gtm_cls1_CMP_EN_ABWC4_EN_SHIFT (4U) #define GTM_gtm_cls1_CMP_EN_ABWC4_EN_WIDTH (1U) #define GTM_gtm_cls1_CMP_EN_ABWC4_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EN_ABWC4_EN_SHIFT)) & GTM_gtm_cls1_CMP_EN_ABWC4_EN_MASK) #define GTM_gtm_cls1_CMP_EN_ABWC5_EN_MASK (0x20U) #define GTM_gtm_cls1_CMP_EN_ABWC5_EN_SHIFT (5U) #define GTM_gtm_cls1_CMP_EN_ABWC5_EN_WIDTH (1U) #define GTM_gtm_cls1_CMP_EN_ABWC5_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EN_ABWC5_EN_SHIFT)) & GTM_gtm_cls1_CMP_EN_ABWC5_EN_MASK) #define GTM_gtm_cls1_CMP_EN_ABWC6_EN_MASK (0x40U) #define GTM_gtm_cls1_CMP_EN_ABWC6_EN_SHIFT (6U) #define GTM_gtm_cls1_CMP_EN_ABWC6_EN_WIDTH (1U) #define GTM_gtm_cls1_CMP_EN_ABWC6_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EN_ABWC6_EN_SHIFT)) & GTM_gtm_cls1_CMP_EN_ABWC6_EN_MASK) #define GTM_gtm_cls1_CMP_EN_ABWC7_EN_MASK (0x80U) #define GTM_gtm_cls1_CMP_EN_ABWC7_EN_SHIFT (7U) #define GTM_gtm_cls1_CMP_EN_ABWC7_EN_WIDTH (1U) #define GTM_gtm_cls1_CMP_EN_ABWC7_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EN_ABWC7_EN_SHIFT)) & GTM_gtm_cls1_CMP_EN_ABWC7_EN_MASK) #define GTM_gtm_cls1_CMP_EN_ABWC8_EN_MASK (0x100U) #define GTM_gtm_cls1_CMP_EN_ABWC8_EN_SHIFT (8U) #define GTM_gtm_cls1_CMP_EN_ABWC8_EN_WIDTH (1U) #define GTM_gtm_cls1_CMP_EN_ABWC8_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EN_ABWC8_EN_SHIFT)) & GTM_gtm_cls1_CMP_EN_ABWC8_EN_MASK) #define GTM_gtm_cls1_CMP_EN_ABWC9_EN_MASK (0x200U) #define GTM_gtm_cls1_CMP_EN_ABWC9_EN_SHIFT (9U) #define GTM_gtm_cls1_CMP_EN_ABWC9_EN_WIDTH (1U) #define GTM_gtm_cls1_CMP_EN_ABWC9_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EN_ABWC9_EN_SHIFT)) & GTM_gtm_cls1_CMP_EN_ABWC9_EN_MASK) #define GTM_gtm_cls1_CMP_EN_ABWC10_EN_MASK (0x400U) #define GTM_gtm_cls1_CMP_EN_ABWC10_EN_SHIFT (10U) #define GTM_gtm_cls1_CMP_EN_ABWC10_EN_WIDTH (1U) #define GTM_gtm_cls1_CMP_EN_ABWC10_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EN_ABWC10_EN_SHIFT)) & GTM_gtm_cls1_CMP_EN_ABWC10_EN_MASK) #define GTM_gtm_cls1_CMP_EN_ABWC11_EN_MASK (0x800U) #define GTM_gtm_cls1_CMP_EN_ABWC11_EN_SHIFT (11U) #define GTM_gtm_cls1_CMP_EN_ABWC11_EN_WIDTH (1U) #define GTM_gtm_cls1_CMP_EN_ABWC11_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EN_ABWC11_EN_SHIFT)) & GTM_gtm_cls1_CMP_EN_ABWC11_EN_MASK) #define GTM_gtm_cls1_CMP_EN_TBWC0_EN_MASK (0x1000U) #define GTM_gtm_cls1_CMP_EN_TBWC0_EN_SHIFT (12U) #define GTM_gtm_cls1_CMP_EN_TBWC0_EN_WIDTH (1U) #define GTM_gtm_cls1_CMP_EN_TBWC0_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EN_TBWC0_EN_SHIFT)) & GTM_gtm_cls1_CMP_EN_TBWC0_EN_MASK) #define GTM_gtm_cls1_CMP_EN_TBWC1_EN_MASK (0x2000U) #define GTM_gtm_cls1_CMP_EN_TBWC1_EN_SHIFT (13U) #define GTM_gtm_cls1_CMP_EN_TBWC1_EN_WIDTH (1U) #define GTM_gtm_cls1_CMP_EN_TBWC1_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EN_TBWC1_EN_SHIFT)) & GTM_gtm_cls1_CMP_EN_TBWC1_EN_MASK) #define GTM_gtm_cls1_CMP_EN_TBWC2_EN_MASK (0x4000U) #define GTM_gtm_cls1_CMP_EN_TBWC2_EN_SHIFT (14U) #define GTM_gtm_cls1_CMP_EN_TBWC2_EN_WIDTH (1U) #define GTM_gtm_cls1_CMP_EN_TBWC2_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EN_TBWC2_EN_SHIFT)) & GTM_gtm_cls1_CMP_EN_TBWC2_EN_MASK) #define GTM_gtm_cls1_CMP_EN_TBWC3_EN_MASK (0x8000U) #define GTM_gtm_cls1_CMP_EN_TBWC3_EN_SHIFT (15U) #define GTM_gtm_cls1_CMP_EN_TBWC3_EN_WIDTH (1U) #define GTM_gtm_cls1_CMP_EN_TBWC3_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EN_TBWC3_EN_SHIFT)) & GTM_gtm_cls1_CMP_EN_TBWC3_EN_MASK) #define GTM_gtm_cls1_CMP_EN_TBWC4_EN_MASK (0x10000U) #define GTM_gtm_cls1_CMP_EN_TBWC4_EN_SHIFT (16U) #define GTM_gtm_cls1_CMP_EN_TBWC4_EN_WIDTH (1U) #define GTM_gtm_cls1_CMP_EN_TBWC4_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EN_TBWC4_EN_SHIFT)) & GTM_gtm_cls1_CMP_EN_TBWC4_EN_MASK) #define GTM_gtm_cls1_CMP_EN_TBWC5_EN_MASK (0x20000U) #define GTM_gtm_cls1_CMP_EN_TBWC5_EN_SHIFT (17U) #define GTM_gtm_cls1_CMP_EN_TBWC5_EN_WIDTH (1U) #define GTM_gtm_cls1_CMP_EN_TBWC5_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EN_TBWC5_EN_SHIFT)) & GTM_gtm_cls1_CMP_EN_TBWC5_EN_MASK) #define GTM_gtm_cls1_CMP_EN_TBWC6_EN_MASK (0x40000U) #define GTM_gtm_cls1_CMP_EN_TBWC6_EN_SHIFT (18U) #define GTM_gtm_cls1_CMP_EN_TBWC6_EN_WIDTH (1U) #define GTM_gtm_cls1_CMP_EN_TBWC6_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EN_TBWC6_EN_SHIFT)) & GTM_gtm_cls1_CMP_EN_TBWC6_EN_MASK) #define GTM_gtm_cls1_CMP_EN_TBWC7_EN_MASK (0x80000U) #define GTM_gtm_cls1_CMP_EN_TBWC7_EN_SHIFT (19U) #define GTM_gtm_cls1_CMP_EN_TBWC7_EN_WIDTH (1U) #define GTM_gtm_cls1_CMP_EN_TBWC7_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EN_TBWC7_EN_SHIFT)) & GTM_gtm_cls1_CMP_EN_TBWC7_EN_MASK) #define GTM_gtm_cls1_CMP_EN_TBWC8_EN_MASK (0x100000U) #define GTM_gtm_cls1_CMP_EN_TBWC8_EN_SHIFT (20U) #define GTM_gtm_cls1_CMP_EN_TBWC8_EN_WIDTH (1U) #define GTM_gtm_cls1_CMP_EN_TBWC8_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EN_TBWC8_EN_SHIFT)) & GTM_gtm_cls1_CMP_EN_TBWC8_EN_MASK) #define GTM_gtm_cls1_CMP_EN_TBWC9_EN_MASK (0x200000U) #define GTM_gtm_cls1_CMP_EN_TBWC9_EN_SHIFT (21U) #define GTM_gtm_cls1_CMP_EN_TBWC9_EN_WIDTH (1U) #define GTM_gtm_cls1_CMP_EN_TBWC9_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EN_TBWC9_EN_SHIFT)) & GTM_gtm_cls1_CMP_EN_TBWC9_EN_MASK) #define GTM_gtm_cls1_CMP_EN_TBWC10_EN_MASK (0x400000U) #define GTM_gtm_cls1_CMP_EN_TBWC10_EN_SHIFT (22U) #define GTM_gtm_cls1_CMP_EN_TBWC10_EN_WIDTH (1U) #define GTM_gtm_cls1_CMP_EN_TBWC10_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EN_TBWC10_EN_SHIFT)) & GTM_gtm_cls1_CMP_EN_TBWC10_EN_MASK) #define GTM_gtm_cls1_CMP_EN_TBWC11_EN_MASK (0x800000U) #define GTM_gtm_cls1_CMP_EN_TBWC11_EN_SHIFT (23U) #define GTM_gtm_cls1_CMP_EN_TBWC11_EN_WIDTH (1U) #define GTM_gtm_cls1_CMP_EN_TBWC11_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EN_TBWC11_EN_SHIFT)) & GTM_gtm_cls1_CMP_EN_TBWC11_EN_MASK) /*! @} */ /*! @name CMP_IRQ_NOTIFY - CMP event notification register */ /*! @{ */ #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC0_MASK (0x1U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC0_SHIFT (0U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC0_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC0_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC0_MASK) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC1_MASK (0x2U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC1_SHIFT (1U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC1_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC1_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC1_MASK) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC2_MASK (0x4U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC2_SHIFT (2U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC2_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC2_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC2_MASK) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC3_MASK (0x8U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC3_SHIFT (3U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC3_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC3_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC3_MASK) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC4_MASK (0x10U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC4_SHIFT (4U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC4_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC4_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC4_MASK) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC5_MASK (0x20U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC5_SHIFT (5U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC5_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC5_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC5_MASK) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC6_MASK (0x40U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC6_SHIFT (6U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC6_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC6_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC6_MASK) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC7_MASK (0x80U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC7_SHIFT (7U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC7_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC7_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC7_MASK) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC8_MASK (0x100U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC8_SHIFT (8U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC8_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC8_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC8_MASK) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC9_MASK (0x200U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC9_SHIFT (9U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC9_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC9_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC9_MASK) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC10_MASK (0x400U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC10_SHIFT (10U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC10_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC10_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC10_MASK) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC11_MASK (0x800U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC11_SHIFT (11U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC11_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC11_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_NOTIFY_ABWC11_MASK) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC0_MASK (0x1000U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC0_SHIFT (12U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC0_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC0_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC0_MASK) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC1_MASK (0x2000U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC1_SHIFT (13U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC1_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC1_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC1_MASK) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC2_MASK (0x4000U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC2_SHIFT (14U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC2_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC2_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC2_MASK) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC3_MASK (0x8000U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC3_SHIFT (15U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC3_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC3_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC3_MASK) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC4_MASK (0x10000U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC4_SHIFT (16U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC4_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC4_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC4_MASK) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC5_MASK (0x20000U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC5_SHIFT (17U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC5_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC5_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC5_MASK) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC6_MASK (0x40000U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC6_SHIFT (18U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC6_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC6_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC6_MASK) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC7_MASK (0x80000U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC7_SHIFT (19U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC7_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC7_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC7_MASK) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC8_MASK (0x100000U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC8_SHIFT (20U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC8_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC8_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC8_MASK) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC9_MASK (0x200000U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC9_SHIFT (21U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC9_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC9_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC9_MASK) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC10_MASK (0x400000U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC10_SHIFT (22U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC10_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC10_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC10_MASK) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC11_MASK (0x800000U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC11_SHIFT (23U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC11_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC11_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_NOTIFY_TBWC11_MASK) /*! @} */ /*! @name CMP_IRQ_EN - CMP interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC0_EN_IRQ_MASK (0x1U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC0_EN_IRQ_SHIFT (0U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC0_EN_IRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC0_EN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_EN_ABWC0_EN_IRQ_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_EN_ABWC0_EN_IRQ_MASK) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC1_EN_IRQ_MASK (0x2U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC1_EN_IRQ_SHIFT (1U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC1_EN_IRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC1_EN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_EN_ABWC1_EN_IRQ_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_EN_ABWC1_EN_IRQ_MASK) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC2_EN_IRQ_MASK (0x4U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC2_EN_IRQ_SHIFT (2U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC2_EN_IRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC2_EN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_EN_ABWC2_EN_IRQ_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_EN_ABWC2_EN_IRQ_MASK) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC3_EN_IRQ_MASK (0x8U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC3_EN_IRQ_SHIFT (3U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC3_EN_IRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC3_EN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_EN_ABWC3_EN_IRQ_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_EN_ABWC3_EN_IRQ_MASK) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC4_EN_IRQ_MASK (0x10U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC4_EN_IRQ_SHIFT (4U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC4_EN_IRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC4_EN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_EN_ABWC4_EN_IRQ_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_EN_ABWC4_EN_IRQ_MASK) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC5_EN_IRQ_MASK (0x20U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC5_EN_IRQ_SHIFT (5U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC5_EN_IRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC5_EN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_EN_ABWC5_EN_IRQ_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_EN_ABWC5_EN_IRQ_MASK) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC6_EN_IRQ_MASK (0x40U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC6_EN_IRQ_SHIFT (6U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC6_EN_IRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC6_EN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_EN_ABWC6_EN_IRQ_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_EN_ABWC6_EN_IRQ_MASK) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC7_EN_IRQ_MASK (0x80U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC7_EN_IRQ_SHIFT (7U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC7_EN_IRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC7_EN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_EN_ABWC7_EN_IRQ_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_EN_ABWC7_EN_IRQ_MASK) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC8_EN_IRQ_MASK (0x100U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC8_EN_IRQ_SHIFT (8U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC8_EN_IRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC8_EN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_EN_ABWC8_EN_IRQ_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_EN_ABWC8_EN_IRQ_MASK) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC9_EN_IRQ_MASK (0x200U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC9_EN_IRQ_SHIFT (9U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC9_EN_IRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC9_EN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_EN_ABWC9_EN_IRQ_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_EN_ABWC9_EN_IRQ_MASK) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC10_EN_IRQ_MASK (0x400U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC10_EN_IRQ_SHIFT (10U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC10_EN_IRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC10_EN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_EN_ABWC10_EN_IRQ_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_EN_ABWC10_EN_IRQ_MASK) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC11_EN_IRQ_MASK (0x800U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC11_EN_IRQ_SHIFT (11U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC11_EN_IRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_EN_ABWC11_EN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_EN_ABWC11_EN_IRQ_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_EN_ABWC11_EN_IRQ_MASK) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC0_EN_IRQ_MASK (0x1000U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC0_EN_IRQ_SHIFT (12U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC0_EN_IRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC0_EN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_EN_TBWC0_EN_IRQ_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_EN_TBWC0_EN_IRQ_MASK) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC1_EN_IRQ_MASK (0x2000U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC1_EN_IRQ_SHIFT (13U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC1_EN_IRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC1_EN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_EN_TBWC1_EN_IRQ_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_EN_TBWC1_EN_IRQ_MASK) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC2_EN_IRQ_MASK (0x4000U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC2_EN_IRQ_SHIFT (14U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC2_EN_IRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC2_EN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_EN_TBWC2_EN_IRQ_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_EN_TBWC2_EN_IRQ_MASK) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC3_EN_IRQ_MASK (0x8000U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC3_EN_IRQ_SHIFT (15U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC3_EN_IRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC3_EN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_EN_TBWC3_EN_IRQ_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_EN_TBWC3_EN_IRQ_MASK) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC4_EN_IRQ_MASK (0x10000U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC4_EN_IRQ_SHIFT (16U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC4_EN_IRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC4_EN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_EN_TBWC4_EN_IRQ_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_EN_TBWC4_EN_IRQ_MASK) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC5_EN_IRQ_MASK (0x20000U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC5_EN_IRQ_SHIFT (17U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC5_EN_IRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC5_EN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_EN_TBWC5_EN_IRQ_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_EN_TBWC5_EN_IRQ_MASK) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC6_EN_IRQ_MASK (0x40000U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC6_EN_IRQ_SHIFT (18U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC6_EN_IRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC6_EN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_EN_TBWC6_EN_IRQ_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_EN_TBWC6_EN_IRQ_MASK) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC7_EN_IRQ_MASK (0x80000U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC7_EN_IRQ_SHIFT (19U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC7_EN_IRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC7_EN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_EN_TBWC7_EN_IRQ_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_EN_TBWC7_EN_IRQ_MASK) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC8_EN_IRQ_MASK (0x100000U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC8_EN_IRQ_SHIFT (20U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC8_EN_IRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC8_EN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_EN_TBWC8_EN_IRQ_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_EN_TBWC8_EN_IRQ_MASK) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC9_EN_IRQ_MASK (0x200000U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC9_EN_IRQ_SHIFT (21U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC9_EN_IRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC9_EN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_EN_TBWC9_EN_IRQ_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_EN_TBWC9_EN_IRQ_MASK) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC10_EN_IRQ_MASK (0x400000U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC10_EN_IRQ_SHIFT (22U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC10_EN_IRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC10_EN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_EN_TBWC10_EN_IRQ_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_EN_TBWC10_EN_IRQ_MASK) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC11_EN_IRQ_MASK (0x800000U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC11_EN_IRQ_SHIFT (23U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC11_EN_IRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_EN_TBWC11_EN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_EN_TBWC11_EN_IRQ_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_EN_TBWC11_EN_IRQ_MASK) /*! @} */ /*! @name CMP_IRQ_FORCINT - CMP interrupt force register */ /*! @{ */ #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC0_MASK (0x1U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC0_SHIFT (0U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC0_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC0_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC0_MASK) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC1_MASK (0x2U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC1_SHIFT (1U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC1_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC1_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC1_MASK) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC2_MASK (0x4U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC2_SHIFT (2U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC2_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC2_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC2_MASK) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC3_MASK (0x8U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC3_SHIFT (3U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC3_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC3_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC3_MASK) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC4_MASK (0x10U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC4_SHIFT (4U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC4_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC4_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC4_MASK) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC5_MASK (0x20U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC5_SHIFT (5U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC5_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC5_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC5_MASK) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC6_MASK (0x40U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC6_SHIFT (6U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC6_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC6_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC6_MASK) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC7_MASK (0x80U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC7_SHIFT (7U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC7_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC7_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC7_MASK) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC8_MASK (0x100U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC8_SHIFT (8U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC8_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC8_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC8_MASK) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC9_MASK (0x200U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC9_SHIFT (9U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC9_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC9_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC9_MASK) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC10_MASK (0x400U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC10_SHIFT (10U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC10_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC10_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC10_MASK) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC11_MASK (0x800U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC11_SHIFT (11U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC11_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC11_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_ABWC11_MASK) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC0_MASK (0x1000U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC0_SHIFT (12U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC0_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC0_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC0_MASK) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC1_MASK (0x2000U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC1_SHIFT (13U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC1_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC1_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC1_MASK) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC2_MASK (0x4000U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC2_SHIFT (14U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC2_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC2_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC2_MASK) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC3_MASK (0x8000U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC3_SHIFT (15U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC3_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC3_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC3_MASK) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC4_MASK (0x10000U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC4_SHIFT (16U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC4_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC4_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC4_MASK) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC5_MASK (0x20000U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC5_SHIFT (17U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC5_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC5_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC5_MASK) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC6_MASK (0x40000U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC6_SHIFT (18U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC6_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC6_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC6_MASK) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC7_MASK (0x80000U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC7_SHIFT (19U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC7_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC7_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC7_MASK) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC8_MASK (0x100000U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC8_SHIFT (20U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC8_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC8_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC8_MASK) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC9_MASK (0x200000U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC9_SHIFT (21U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC9_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC9_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC9_MASK) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC10_MASK (0x400000U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC10_SHIFT (22U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC10_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC10_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC10_MASK) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC11_MASK (0x800000U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC11_SHIFT (23U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC11_WIDTH (1U) #define GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC11_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_FORCINT_TRG_TBWC11_MASK) /*! @} */ /*! @name CMP_IRQ_MODE - CMP interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_CMP_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_CMP_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_CMP_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_CMP_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_CMP_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name CMP_EIRQ_EN - CMP error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC0_EN_EIRQ_MASK (0x1U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC0_EN_EIRQ_SHIFT (0U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC0_EN_EIRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC0_EN_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EIRQ_EN_ABWC0_EN_EIRQ_SHIFT)) & GTM_gtm_cls1_CMP_EIRQ_EN_ABWC0_EN_EIRQ_MASK) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC1_EN_EIRQ_MASK (0x2U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC1_EN_EIRQ_SHIFT (1U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC1_EN_EIRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC1_EN_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EIRQ_EN_ABWC1_EN_EIRQ_SHIFT)) & GTM_gtm_cls1_CMP_EIRQ_EN_ABWC1_EN_EIRQ_MASK) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC2_EN_EIRQ_MASK (0x4U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC2_EN_EIRQ_SHIFT (2U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC2_EN_EIRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC2_EN_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EIRQ_EN_ABWC2_EN_EIRQ_SHIFT)) & GTM_gtm_cls1_CMP_EIRQ_EN_ABWC2_EN_EIRQ_MASK) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC3_EN_EIRQ_MASK (0x8U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC3_EN_EIRQ_SHIFT (3U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC3_EN_EIRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC3_EN_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EIRQ_EN_ABWC3_EN_EIRQ_SHIFT)) & GTM_gtm_cls1_CMP_EIRQ_EN_ABWC3_EN_EIRQ_MASK) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC4_EN_EIRQ_MASK (0x10U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC4_EN_EIRQ_SHIFT (4U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC4_EN_EIRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC4_EN_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EIRQ_EN_ABWC4_EN_EIRQ_SHIFT)) & GTM_gtm_cls1_CMP_EIRQ_EN_ABWC4_EN_EIRQ_MASK) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC5_EN_EIRQ_MASK (0x20U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC5_EN_EIRQ_SHIFT (5U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC5_EN_EIRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC5_EN_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EIRQ_EN_ABWC5_EN_EIRQ_SHIFT)) & GTM_gtm_cls1_CMP_EIRQ_EN_ABWC5_EN_EIRQ_MASK) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC6_EN_EIRQ_MASK (0x40U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC6_EN_EIRQ_SHIFT (6U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC6_EN_EIRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC6_EN_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EIRQ_EN_ABWC6_EN_EIRQ_SHIFT)) & GTM_gtm_cls1_CMP_EIRQ_EN_ABWC6_EN_EIRQ_MASK) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC7_EN_EIRQ_MASK (0x80U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC7_EN_EIRQ_SHIFT (7U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC7_EN_EIRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC7_EN_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EIRQ_EN_ABWC7_EN_EIRQ_SHIFT)) & GTM_gtm_cls1_CMP_EIRQ_EN_ABWC7_EN_EIRQ_MASK) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC8_EN_EIRQ_MASK (0x100U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC8_EN_EIRQ_SHIFT (8U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC8_EN_EIRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC8_EN_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EIRQ_EN_ABWC8_EN_EIRQ_SHIFT)) & GTM_gtm_cls1_CMP_EIRQ_EN_ABWC8_EN_EIRQ_MASK) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC9_EN_EIRQ_MASK (0x200U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC9_EN_EIRQ_SHIFT (9U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC9_EN_EIRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC9_EN_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EIRQ_EN_ABWC9_EN_EIRQ_SHIFT)) & GTM_gtm_cls1_CMP_EIRQ_EN_ABWC9_EN_EIRQ_MASK) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC10_EN_EIRQ_MASK (0x400U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC10_EN_EIRQ_SHIFT (10U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC10_EN_EIRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC10_EN_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EIRQ_EN_ABWC10_EN_EIRQ_SHIFT)) & GTM_gtm_cls1_CMP_EIRQ_EN_ABWC10_EN_EIRQ_MASK) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC11_EN_EIRQ_MASK (0x800U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC11_EN_EIRQ_SHIFT (11U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC11_EN_EIRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_EIRQ_EN_ABWC11_EN_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EIRQ_EN_ABWC11_EN_EIRQ_SHIFT)) & GTM_gtm_cls1_CMP_EIRQ_EN_ABWC11_EN_EIRQ_MASK) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC0_EN_EIRQ_MASK (0x1000U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC0_EN_EIRQ_SHIFT (12U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC0_EN_EIRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC0_EN_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EIRQ_EN_TBWC0_EN_EIRQ_SHIFT)) & GTM_gtm_cls1_CMP_EIRQ_EN_TBWC0_EN_EIRQ_MASK) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC1_EN_EIRQ_MASK (0x2000U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC1_EN_EIRQ_SHIFT (13U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC1_EN_EIRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC1_EN_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EIRQ_EN_TBWC1_EN_EIRQ_SHIFT)) & GTM_gtm_cls1_CMP_EIRQ_EN_TBWC1_EN_EIRQ_MASK) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC2_EN_EIRQ_MASK (0x4000U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC2_EN_EIRQ_SHIFT (14U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC2_EN_EIRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC2_EN_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EIRQ_EN_TBWC2_EN_EIRQ_SHIFT)) & GTM_gtm_cls1_CMP_EIRQ_EN_TBWC2_EN_EIRQ_MASK) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC3_EN_EIRQ_MASK (0x8000U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC3_EN_EIRQ_SHIFT (15U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC3_EN_EIRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC3_EN_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EIRQ_EN_TBWC3_EN_EIRQ_SHIFT)) & GTM_gtm_cls1_CMP_EIRQ_EN_TBWC3_EN_EIRQ_MASK) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC4_EN_EIRQ_MASK (0x10000U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC4_EN_EIRQ_SHIFT (16U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC4_EN_EIRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC4_EN_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EIRQ_EN_TBWC4_EN_EIRQ_SHIFT)) & GTM_gtm_cls1_CMP_EIRQ_EN_TBWC4_EN_EIRQ_MASK) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC5_EN_EIRQ_MASK (0x20000U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC5_EN_EIRQ_SHIFT (17U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC5_EN_EIRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC5_EN_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EIRQ_EN_TBWC5_EN_EIRQ_SHIFT)) & GTM_gtm_cls1_CMP_EIRQ_EN_TBWC5_EN_EIRQ_MASK) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC6_EN_EIRQ_MASK (0x40000U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC6_EN_EIRQ_SHIFT (18U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC6_EN_EIRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC6_EN_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EIRQ_EN_TBWC6_EN_EIRQ_SHIFT)) & GTM_gtm_cls1_CMP_EIRQ_EN_TBWC6_EN_EIRQ_MASK) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC7_EN_EIRQ_MASK (0x80000U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC7_EN_EIRQ_SHIFT (19U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC7_EN_EIRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC7_EN_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EIRQ_EN_TBWC7_EN_EIRQ_SHIFT)) & GTM_gtm_cls1_CMP_EIRQ_EN_TBWC7_EN_EIRQ_MASK) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC8_EN_EIRQ_MASK (0x100000U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC8_EN_EIRQ_SHIFT (20U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC8_EN_EIRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC8_EN_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EIRQ_EN_TBWC8_EN_EIRQ_SHIFT)) & GTM_gtm_cls1_CMP_EIRQ_EN_TBWC8_EN_EIRQ_MASK) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC9_EN_EIRQ_MASK (0x200000U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC9_EN_EIRQ_SHIFT (21U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC9_EN_EIRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC9_EN_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EIRQ_EN_TBWC9_EN_EIRQ_SHIFT)) & GTM_gtm_cls1_CMP_EIRQ_EN_TBWC9_EN_EIRQ_MASK) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC10_EN_EIRQ_MASK (0x400000U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC10_EN_EIRQ_SHIFT (22U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC10_EN_EIRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC10_EN_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EIRQ_EN_TBWC10_EN_EIRQ_SHIFT)) & GTM_gtm_cls1_CMP_EIRQ_EN_TBWC10_EN_EIRQ_MASK) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC11_EN_EIRQ_MASK (0x800000U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC11_EN_EIRQ_SHIFT (23U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC11_EN_EIRQ_WIDTH (1U) #define GTM_gtm_cls1_CMP_EIRQ_EN_TBWC11_EN_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CMP_EIRQ_EN_TBWC11_EN_EIRQ_SHIFT)) & GTM_gtm_cls1_CMP_EIRQ_EN_TBWC11_EN_EIRQ_MASK) /*! @} */ /*! @name TIM1_CH0_GPR0 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH0_GPR0_GPR0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH0_GPR0_GPR0_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH0_GPR0_GPR0_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH0_GPR0_GPR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_GPR0_GPR0_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_GPR0_GPR0_MASK) #define GTM_gtm_cls1_TIM1_CH0_GPR0_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls1_TIM1_CH0_GPR0_ECNT_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH0_GPR0_ECNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH0_GPR0_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_GPR0_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_GPR0_ECNT_MASK) /*! @} */ /*! @name TIM1_CH0_GPR1 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH0_GPR1_GPR1_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH0_GPR1_GPR1_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH0_GPR1_GPR1_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH0_GPR1_GPR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_GPR1_GPR1_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_GPR1_GPR1_MASK) #define GTM_gtm_cls1_TIM1_CH0_GPR1_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls1_TIM1_CH0_GPR1_ECNT_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH0_GPR1_ECNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH0_GPR1_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_GPR1_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_GPR1_ECNT_MASK) /*! @} */ /*! @name TIM1_CH0_CNT - TIM[i] channel [x] SMU counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH0_CNT_CNT_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH0_CNT_CNT_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH0_CNT_CNT_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH0_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_CNT_CNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_CNT_CNT_MASK) /*! @} */ /*! @name TIM1_CH0_ECNT - TIM[i] channel [x] SMU edge counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH0_ECNT_ECNT_MASK (0xFFFFU) #define GTM_gtm_cls1_TIM1_CH0_ECNT_ECNT_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH0_ECNT_ECNT_WIDTH (16U) #define GTM_gtm_cls1_TIM1_CH0_ECNT_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_ECNT_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_ECNT_ECNT_MASK) /*! @} */ /*! @name TIM1_CH0_CNTS - TIM[i] channel [x] SMU shadow counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH0_CNTS_CNTS_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH0_CNTS_CNTS_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH0_CNTS_CNTS_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH0_CNTS_CNTS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_CNTS_CNTS_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_CNTS_CNTS_MASK) #define GTM_gtm_cls1_TIM1_CH0_CNTS_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls1_TIM1_CH0_CNTS_ECNT_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH0_CNTS_ECNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH0_CNTS_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_CNTS_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_CNTS_ECNT_MASK) /*! @} */ /*! @name TIM1_CH0_TDUC - TIM[i] channel [x] TDU counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH0_TDUC_TO_CNT_MASK (0xFFU) #define GTM_gtm_cls1_TIM1_CH0_TDUC_TO_CNT_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH0_TDUC_TO_CNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH0_TDUC_TO_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_TDUC_TO_CNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_TDUC_TO_CNT_MASK) #define GTM_gtm_cls1_TIM1_CH0_TDUC_TO_CNT1_MASK (0xFF00U) #define GTM_gtm_cls1_TIM1_CH0_TDUC_TO_CNT1_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH0_TDUC_TO_CNT1_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH0_TDUC_TO_CNT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_TDUC_TO_CNT1_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_TDUC_TO_CNT1_MASK) #define GTM_gtm_cls1_TIM1_CH0_TDUC_TO_CNT2_MASK (0xFF0000U) #define GTM_gtm_cls1_TIM1_CH0_TDUC_TO_CNT2_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH0_TDUC_TO_CNT2_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH0_TDUC_TO_CNT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_TDUC_TO_CNT2_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_TDUC_TO_CNT2_MASK) /*! @} */ /*! @name TIM1_CH0_TDUV - TIM[i] channel [x] TDU control register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH0_TDUV_TOV_MASK (0xFFU) #define GTM_gtm_cls1_TIM1_CH0_TDUV_TOV_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH0_TDUV_TOV_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH0_TDUV_TOV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_TDUV_TOV_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_TDUV_TOV_MASK) #define GTM_gtm_cls1_TIM1_CH0_TDUV_TOV1_MASK (0xFF00U) #define GTM_gtm_cls1_TIM1_CH0_TDUV_TOV1_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH0_TDUV_TOV1_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH0_TDUV_TOV1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_TDUV_TOV1_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_TDUV_TOV1_MASK) #define GTM_gtm_cls1_TIM1_CH0_TDUV_TOV2_MASK (0xFF0000U) #define GTM_gtm_cls1_TIM1_CH0_TDUV_TOV2_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH0_TDUV_TOV2_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH0_TDUV_TOV2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_TDUV_TOV2_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_TDUV_TOV2_MASK) #define GTM_gtm_cls1_TIM1_CH0_TDUV_SLICING_MASK (0x3000000U) #define GTM_gtm_cls1_TIM1_CH0_TDUV_SLICING_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH0_TDUV_SLICING_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH0_TDUV_SLICING(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_TDUV_SLICING_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_TDUV_SLICING_MASK) #define GTM_gtm_cls1_TIM1_CH0_TDUV_TCS_USE_SAMPLE_EVT_MASK (0x4000000U) #define GTM_gtm_cls1_TIM1_CH0_TDUV_TCS_USE_SAMPLE_EVT_SHIFT (26U) #define GTM_gtm_cls1_TIM1_CH0_TDUV_TCS_USE_SAMPLE_EVT_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_TDUV_TCS_USE_SAMPLE_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_TDUV_TCS_USE_SAMPLE_EVT_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_TDUV_TCS_USE_SAMPLE_EVT_MASK) #define GTM_gtm_cls1_TIM1_CH0_TDUV_TDU_SAME_CNT_CLK_MASK (0x8000000U) #define GTM_gtm_cls1_TIM1_CH0_TDUV_TDU_SAME_CNT_CLK_SHIFT (27U) #define GTM_gtm_cls1_TIM1_CH0_TDUV_TDU_SAME_CNT_CLK_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_TDUV_TDU_SAME_CNT_CLK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_TDUV_TDU_SAME_CNT_CLK_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_TDUV_TDU_SAME_CNT_CLK_MASK) #define GTM_gtm_cls1_TIM1_CH0_TDUV_TCS_MASK (0x70000000U) #define GTM_gtm_cls1_TIM1_CH0_TDUV_TCS_SHIFT (28U) #define GTM_gtm_cls1_TIM1_CH0_TDUV_TCS_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH0_TDUV_TCS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_TDUV_TCS_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_TDUV_TCS_MASK) /*! @} */ /*! @name TIM1_CH0_FLT_RE - TIM[i] channel [x] filter parameter 0 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH0_FLT_RE_FLT_RE_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH0_FLT_RE_FLT_RE_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH0_FLT_RE_FLT_RE_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH0_FLT_RE_FLT_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_FLT_RE_FLT_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_FLT_RE_FLT_RE_MASK) /*! @} */ /*! @name TIM1_CH0_FLT_FE - TIM[i] channel [x] filter parameter 1 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH0_FLT_FE_FLT_FE_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH0_FLT_FE_FLT_FE_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH0_FLT_FE_FLT_FE_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH0_FLT_FE_FLT_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_FLT_FE_FLT_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_FLT_FE_FLT_FE_MASK) /*! @} */ /*! @name TIM1_CH0_CTRL - TIM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH0_CTRL_TIM_EN_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_TIM_EN_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_TIM_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_TIM_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_CTRL_TIM_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_CTRL_TIM_EN_MASK) #define GTM_gtm_cls1_TIM1_CH0_CTRL_TIM_MODE_MASK (0xEU) #define GTM_gtm_cls1_TIM1_CH0_CTRL_TIM_MODE_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_TIM_MODE_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_TIM_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_CTRL_TIM_MODE_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_CTRL_TIM_MODE_MASK) #define GTM_gtm_cls1_TIM1_CH0_CTRL_OSM_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_OSM_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_CTRL_OSM_MASK) #define GTM_gtm_cls1_TIM1_CH0_CTRL_ARU_EN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_ARU_EN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_CTRL_ARU_EN_MASK) #define GTM_gtm_cls1_TIM1_CH0_CTRL_CICTRL_MASK (0x40U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_CICTRL_SHIFT (6U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_CICTRL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_CICTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_CTRL_CICTRL_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_CTRL_CICTRL_MASK) #define GTM_gtm_cls1_TIM1_CH0_CTRL_GPR0_SEL_MASK (0x300U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_GPR0_SEL_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_GPR0_SEL_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_GPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_CTRL_GPR0_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_CTRL_GPR0_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH0_CTRL_GPR1_SEL_MASK (0xC00U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_GPR1_SEL_SHIFT (10U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_GPR1_SEL_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_GPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_CTRL_GPR1_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_CTRL_GPR1_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH0_CTRL_CNTS_SEL_MASK (0x1000U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_CNTS_SEL_SHIFT (12U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_CNTS_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_CNTS_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_CTRL_CNTS_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_CTRL_CNTS_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH0_CTRL_DSL_MASK (0x2000U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_DSL_SHIFT (13U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_DSL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_CTRL_DSL_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_CTRL_DSL_MASK) #define GTM_gtm_cls1_TIM1_CH0_CTRL_ISL_MASK (0x4000U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_ISL_SHIFT (14U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_ISL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_ISL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_CTRL_ISL_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_CTRL_ISL_MASK) #define GTM_gtm_cls1_TIM1_CH0_CTRL_ECNT_RESET_MASK (0x8000U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_ECNT_RESET_SHIFT (15U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_ECNT_RESET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_ECNT_RESET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_CTRL_ECNT_RESET_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_CTRL_ECNT_RESET_MASK) #define GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_EN_MASK (0x10000U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_EN_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_EN_MASK) #define GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_CNT_FRQ_MASK (0x60000U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_CNT_FRQ_SHIFT (17U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_CNT_FRQ_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_CNT_FRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_CNT_FRQ_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_CNT_FRQ_MASK) #define GTM_gtm_cls1_TIM1_CH0_CTRL_EXT_CAP_EN_MASK (0x80000U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_EXT_CAP_EN_SHIFT (19U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_EXT_CAP_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_EXT_CAP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_CTRL_EXT_CAP_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_CTRL_EXT_CAP_EN_MASK) #define GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_MODE_RE_MASK (0x100000U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_MODE_RE_SHIFT (20U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_MODE_RE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_MODE_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_MODE_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_MODE_RE_MASK) #define GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_CTR_RE_MASK (0x200000U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_CTR_RE_SHIFT (21U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_CTR_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_CTR_RE_MASK) #define GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_MODE_FE_MASK (0x400000U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_MODE_FE_SHIFT (22U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_MODE_FE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_MODE_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_MODE_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_MODE_FE_MASK) #define GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_CTR_FE_MASK (0x800000U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_CTR_FE_SHIFT (23U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_CTR_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_CTRL_FLT_CTR_FE_MASK) #define GTM_gtm_cls1_TIM1_CH0_CTRL_CLK_SEL_MASK (0x7000000U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_CLK_SEL_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_CLK_SEL_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_CTRL_CLK_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_CTRL_CLK_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH0_CTRL_FR_ECNT_OFL_MASK (0x8000000U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_FR_ECNT_OFL_SHIFT (27U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_FR_ECNT_OFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_FR_ECNT_OFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_CTRL_FR_ECNT_OFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_CTRL_FR_ECNT_OFL_MASK) #define GTM_gtm_cls1_TIM1_CH0_CTRL_EGPR0_SEL_MASK (0x10000000U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_EGPR0_SEL_SHIFT (28U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_EGPR0_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_EGPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_CTRL_EGPR0_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_CTRL_EGPR0_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH0_CTRL_EGPR1_SEL_MASK (0x20000000U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_EGPR1_SEL_SHIFT (29U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_EGPR1_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_EGPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_CTRL_EGPR1_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_CTRL_EGPR1_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH0_CTRL_TOCTRL_MASK (0xC0000000U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_TOCTRL_SHIFT (30U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_TOCTRL_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH0_CTRL_TOCTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_CTRL_TOCTRL_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_CTRL_TOCTRL_MASK) /*! @} */ /*! @name TIM1_CH0_ECTRL - TIM[i] channel [x] extended control register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH0_ECTRL_EXT_CAP_SRC_MASK (0xFU) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_EXT_CAP_SRC_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_EXT_CAP_SRC_WIDTH (4U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_EXT_CAP_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_ECTRL_EXT_CAP_SRC_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_ECTRL_EXT_CAP_SRC_MASK) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_USE_PREV_TDU_IN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_USE_PREV_TDU_IN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_USE_PREV_TDU_IN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_USE_PREV_TDU_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_ECTRL_USE_PREV_TDU_IN_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_ECTRL_USE_PREV_TDU_IN_MASK) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_TODET_IRQ_SRC_MASK (0xC0U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_TODET_IRQ_SRC_SHIFT (6U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_TODET_IRQ_SRC_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_TODET_IRQ_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_ECTRL_TODET_IRQ_SRC_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_ECTRL_TODET_IRQ_SRC_MASK) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_TDU_START_MASK (0x700U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_TDU_START_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_TDU_START_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_TDU_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_ECTRL_TDU_START_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_ECTRL_TDU_START_MASK) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_TDU_STOP_MASK (0x7000U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_TDU_STOP_SHIFT (12U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_TDU_STOP_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_TDU_STOP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_ECTRL_TDU_STOP_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_ECTRL_TDU_STOP_MASK) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_TDU_RESYNC_MASK (0xF0000U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_TDU_RESYNC_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_TDU_RESYNC_WIDTH (4U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_TDU_RESYNC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_ECTRL_TDU_RESYNC_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_ECTRL_TDU_RESYNC_MASK) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_USE_LUT_MASK (0xC00000U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_USE_LUT_SHIFT (22U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_USE_LUT_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_USE_LUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_ECTRL_USE_LUT_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_ECTRL_USE_LUT_MASK) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_EFLT_CTR_RE_MASK (0x1000000U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_EFLT_CTR_RE_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_EFLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_EFLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_ECTRL_EFLT_CTR_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_ECTRL_EFLT_CTR_RE_MASK) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_EFLT_CTR_FE_MASK (0x2000000U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_EFLT_CTR_FE_SHIFT (25U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_EFLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_EFLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_ECTRL_EFLT_CTR_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_ECTRL_EFLT_CTR_FE_MASK) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_SWAP_CAPTURE_MASK (0x10000000U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_SWAP_CAPTURE_SHIFT (28U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_SWAP_CAPTURE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_SWAP_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_ECTRL_SWAP_CAPTURE_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_ECTRL_SWAP_CAPTURE_MASK) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_IMM_START_MASK (0x20000000U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_IMM_START_SHIFT (29U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_IMM_START_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_IMM_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_ECTRL_IMM_START_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_ECTRL_IMM_START_MASK) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_ECLK_SEL_MASK (0x40000000U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_ECLK_SEL_SHIFT (30U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_ECLK_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_ECLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_ECTRL_ECLK_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_ECTRL_ECLK_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_USE_PREV_CH_IN_MASK (0x80000000U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_USE_PREV_CH_IN_SHIFT (31U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_USE_PREV_CH_IN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_ECTRL_USE_PREV_CH_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_ECTRL_USE_PREV_CH_IN_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_ECTRL_USE_PREV_CH_IN_MASK) /*! @} */ /*! @name TIM1_CH0_IRQ_NOTIFY - TIM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_NEWVAL_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_NEWVAL_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_NEWVAL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_NEWVAL_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_NEWVAL_MASK) #define GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_ECNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_ECNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_CNTOFL_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_CNTOFL_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_CNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_CNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_CNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_GPROFL_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_GPROFL_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_GPROFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_GPROFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_GPROFL_MASK) #define GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_TODET_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_TODET_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_TODET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_TODET_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_TODET_MASK) #define GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_GLITCHDET_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_IRQ_NOTIFY_GLITCHDET_MASK) /*! @} */ /*! @name TIM1_CH0_IRQ_EN - TIM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH0_IRQ_EN_NEWVAL_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_EN_NEWVAL_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_EN_NEWVAL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_EN_NEWVAL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_IRQ_EN_NEWVAL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_IRQ_EN_NEWVAL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH0_IRQ_EN_ECNTOFL_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_EN_ECNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_EN_ECNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_IRQ_EN_ECNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH0_IRQ_EN_CNTOFL_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_EN_CNTOFL_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_EN_CNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_EN_CNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_IRQ_EN_CNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_IRQ_EN_CNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH0_IRQ_EN_GPROFL_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_EN_GPROFL_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_EN_GPROFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_EN_GPROFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_IRQ_EN_GPROFL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_IRQ_EN_GPROFL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH0_IRQ_EN_TODET_IRQ_EN_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_EN_TODET_IRQ_EN_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_EN_TODET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_EN_TODET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_IRQ_EN_TODET_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_IRQ_EN_TODET_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH0_IRQ_EN_GLITCHDET_IRQ_EN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_EN_GLITCHDET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_EN_GLITCHDET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_IRQ_EN_GLITCHDET_IRQ_EN_MASK) /*! @} */ /*! @name TIM1_CH0_IRQ_FORCINT - TIM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_NEWVAL_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_NEWVAL_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_NEWVAL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_NEWVAL_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_NEWVAL_MASK) #define GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_ECNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_ECNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_CNTOFL_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_CNTOFL_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_CNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_CNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_CNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_GPROFL_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_GPROFL_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_GPROFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_GPROFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_GPROFL_MASK) #define GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_TODET_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_TODET_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_TODET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_TODET_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_TODET_MASK) #define GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_GLITCHDET_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_IRQ_FORCINT_TRG_GLITCHDET_MASK) /*! @} */ /*! @name TIM1_CH0_IRQ_MODE - TIM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH0_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH0_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TIM1_CH0_EIRQ_EN - TIM[i] channel [x] error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_NEWVAL_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_NEWVAL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_NEWVAL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_NEWVAL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_ECNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_ECNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_CNTOFL_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_CNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_CNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_CNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_GPROFL_EIRQ_EN_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_GPROFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_GPROFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_GPROFL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_TODET_EIRQ_EN_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_TODET_EIRQ_EN_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_TODET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_TODET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_TODET_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_TODET_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_GLITCHDET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_GLITCHDET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH0_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK) /*! @} */ /*! @name TIM1_CH1_GPR0 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH1_GPR0_GPR0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH1_GPR0_GPR0_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH1_GPR0_GPR0_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH1_GPR0_GPR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_GPR0_GPR0_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_GPR0_GPR0_MASK) #define GTM_gtm_cls1_TIM1_CH1_GPR0_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls1_TIM1_CH1_GPR0_ECNT_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH1_GPR0_ECNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH1_GPR0_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_GPR0_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_GPR0_ECNT_MASK) /*! @} */ /*! @name TIM1_CH1_GPR1 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH1_GPR1_GPR1_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH1_GPR1_GPR1_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH1_GPR1_GPR1_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH1_GPR1_GPR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_GPR1_GPR1_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_GPR1_GPR1_MASK) #define GTM_gtm_cls1_TIM1_CH1_GPR1_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls1_TIM1_CH1_GPR1_ECNT_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH1_GPR1_ECNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH1_GPR1_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_GPR1_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_GPR1_ECNT_MASK) /*! @} */ /*! @name TIM1_CH1_CNT - TIM[i] channel [x] SMU counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH1_CNT_CNT_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH1_CNT_CNT_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH1_CNT_CNT_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH1_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_CNT_CNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_CNT_CNT_MASK) /*! @} */ /*! @name TIM1_CH1_ECNT - TIM[i] channel [x] SMU edge counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH1_ECNT_ECNT_MASK (0xFFFFU) #define GTM_gtm_cls1_TIM1_CH1_ECNT_ECNT_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH1_ECNT_ECNT_WIDTH (16U) #define GTM_gtm_cls1_TIM1_CH1_ECNT_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_ECNT_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_ECNT_ECNT_MASK) /*! @} */ /*! @name TIM1_CH1_CNTS - TIM[i] channel [x] SMU shadow counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH1_CNTS_CNTS_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH1_CNTS_CNTS_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH1_CNTS_CNTS_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH1_CNTS_CNTS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_CNTS_CNTS_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_CNTS_CNTS_MASK) #define GTM_gtm_cls1_TIM1_CH1_CNTS_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls1_TIM1_CH1_CNTS_ECNT_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH1_CNTS_ECNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH1_CNTS_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_CNTS_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_CNTS_ECNT_MASK) /*! @} */ /*! @name TIM1_CH1_TDUC - TIM[i] channel [x] TDU counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH1_TDUC_TO_CNT_MASK (0xFFU) #define GTM_gtm_cls1_TIM1_CH1_TDUC_TO_CNT_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH1_TDUC_TO_CNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH1_TDUC_TO_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_TDUC_TO_CNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_TDUC_TO_CNT_MASK) #define GTM_gtm_cls1_TIM1_CH1_TDUC_TO_CNT1_MASK (0xFF00U) #define GTM_gtm_cls1_TIM1_CH1_TDUC_TO_CNT1_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH1_TDUC_TO_CNT1_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH1_TDUC_TO_CNT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_TDUC_TO_CNT1_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_TDUC_TO_CNT1_MASK) #define GTM_gtm_cls1_TIM1_CH1_TDUC_TO_CNT2_MASK (0xFF0000U) #define GTM_gtm_cls1_TIM1_CH1_TDUC_TO_CNT2_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH1_TDUC_TO_CNT2_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH1_TDUC_TO_CNT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_TDUC_TO_CNT2_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_TDUC_TO_CNT2_MASK) /*! @} */ /*! @name TIM1_CH1_TDUV - TIM[i] channel [x] TDU control register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH1_TDUV_TOV_MASK (0xFFU) #define GTM_gtm_cls1_TIM1_CH1_TDUV_TOV_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH1_TDUV_TOV_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH1_TDUV_TOV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_TDUV_TOV_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_TDUV_TOV_MASK) #define GTM_gtm_cls1_TIM1_CH1_TDUV_TOV1_MASK (0xFF00U) #define GTM_gtm_cls1_TIM1_CH1_TDUV_TOV1_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH1_TDUV_TOV1_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH1_TDUV_TOV1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_TDUV_TOV1_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_TDUV_TOV1_MASK) #define GTM_gtm_cls1_TIM1_CH1_TDUV_TOV2_MASK (0xFF0000U) #define GTM_gtm_cls1_TIM1_CH1_TDUV_TOV2_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH1_TDUV_TOV2_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH1_TDUV_TOV2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_TDUV_TOV2_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_TDUV_TOV2_MASK) #define GTM_gtm_cls1_TIM1_CH1_TDUV_SLICING_MASK (0x3000000U) #define GTM_gtm_cls1_TIM1_CH1_TDUV_SLICING_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH1_TDUV_SLICING_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH1_TDUV_SLICING(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_TDUV_SLICING_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_TDUV_SLICING_MASK) #define GTM_gtm_cls1_TIM1_CH1_TDUV_TCS_USE_SAMPLE_EVT_MASK (0x4000000U) #define GTM_gtm_cls1_TIM1_CH1_TDUV_TCS_USE_SAMPLE_EVT_SHIFT (26U) #define GTM_gtm_cls1_TIM1_CH1_TDUV_TCS_USE_SAMPLE_EVT_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_TDUV_TCS_USE_SAMPLE_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_TDUV_TCS_USE_SAMPLE_EVT_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_TDUV_TCS_USE_SAMPLE_EVT_MASK) #define GTM_gtm_cls1_TIM1_CH1_TDUV_TDU_SAME_CNT_CLK_MASK (0x8000000U) #define GTM_gtm_cls1_TIM1_CH1_TDUV_TDU_SAME_CNT_CLK_SHIFT (27U) #define GTM_gtm_cls1_TIM1_CH1_TDUV_TDU_SAME_CNT_CLK_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_TDUV_TDU_SAME_CNT_CLK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_TDUV_TDU_SAME_CNT_CLK_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_TDUV_TDU_SAME_CNT_CLK_MASK) #define GTM_gtm_cls1_TIM1_CH1_TDUV_TCS_MASK (0x70000000U) #define GTM_gtm_cls1_TIM1_CH1_TDUV_TCS_SHIFT (28U) #define GTM_gtm_cls1_TIM1_CH1_TDUV_TCS_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH1_TDUV_TCS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_TDUV_TCS_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_TDUV_TCS_MASK) /*! @} */ /*! @name TIM1_CH1_FLT_RE - TIM[i] channel [x] filter parameter 0 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH1_FLT_RE_FLT_RE_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH1_FLT_RE_FLT_RE_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH1_FLT_RE_FLT_RE_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH1_FLT_RE_FLT_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_FLT_RE_FLT_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_FLT_RE_FLT_RE_MASK) /*! @} */ /*! @name TIM1_CH1_FLT_FE - TIM[i] channel [x] filter parameter 1 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH1_FLT_FE_FLT_FE_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH1_FLT_FE_FLT_FE_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH1_FLT_FE_FLT_FE_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH1_FLT_FE_FLT_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_FLT_FE_FLT_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_FLT_FE_FLT_FE_MASK) /*! @} */ /*! @name TIM1_CH1_CTRL - TIM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH1_CTRL_TIM_EN_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_TIM_EN_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_TIM_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_TIM_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_CTRL_TIM_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_CTRL_TIM_EN_MASK) #define GTM_gtm_cls1_TIM1_CH1_CTRL_TIM_MODE_MASK (0xEU) #define GTM_gtm_cls1_TIM1_CH1_CTRL_TIM_MODE_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_TIM_MODE_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_TIM_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_CTRL_TIM_MODE_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_CTRL_TIM_MODE_MASK) #define GTM_gtm_cls1_TIM1_CH1_CTRL_OSM_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_OSM_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_CTRL_OSM_MASK) #define GTM_gtm_cls1_TIM1_CH1_CTRL_ARU_EN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_ARU_EN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_CTRL_ARU_EN_MASK) #define GTM_gtm_cls1_TIM1_CH1_CTRL_CICTRL_MASK (0x40U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_CICTRL_SHIFT (6U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_CICTRL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_CICTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_CTRL_CICTRL_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_CTRL_CICTRL_MASK) #define GTM_gtm_cls1_TIM1_CH1_CTRL_GPR0_SEL_MASK (0x300U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_GPR0_SEL_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_GPR0_SEL_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_GPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_CTRL_GPR0_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_CTRL_GPR0_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH1_CTRL_GPR1_SEL_MASK (0xC00U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_GPR1_SEL_SHIFT (10U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_GPR1_SEL_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_GPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_CTRL_GPR1_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_CTRL_GPR1_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH1_CTRL_CNTS_SEL_MASK (0x1000U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_CNTS_SEL_SHIFT (12U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_CNTS_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_CNTS_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_CTRL_CNTS_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_CTRL_CNTS_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH1_CTRL_DSL_MASK (0x2000U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_DSL_SHIFT (13U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_DSL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_CTRL_DSL_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_CTRL_DSL_MASK) #define GTM_gtm_cls1_TIM1_CH1_CTRL_ISL_MASK (0x4000U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_ISL_SHIFT (14U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_ISL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_ISL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_CTRL_ISL_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_CTRL_ISL_MASK) #define GTM_gtm_cls1_TIM1_CH1_CTRL_ECNT_RESET_MASK (0x8000U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_ECNT_RESET_SHIFT (15U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_ECNT_RESET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_ECNT_RESET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_CTRL_ECNT_RESET_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_CTRL_ECNT_RESET_MASK) #define GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_EN_MASK (0x10000U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_EN_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_EN_MASK) #define GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_CNT_FRQ_MASK (0x60000U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_CNT_FRQ_SHIFT (17U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_CNT_FRQ_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_CNT_FRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_CNT_FRQ_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_CNT_FRQ_MASK) #define GTM_gtm_cls1_TIM1_CH1_CTRL_EXT_CAP_EN_MASK (0x80000U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_EXT_CAP_EN_SHIFT (19U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_EXT_CAP_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_EXT_CAP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_CTRL_EXT_CAP_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_CTRL_EXT_CAP_EN_MASK) #define GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_MODE_RE_MASK (0x100000U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_MODE_RE_SHIFT (20U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_MODE_RE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_MODE_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_MODE_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_MODE_RE_MASK) #define GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_CTR_RE_MASK (0x200000U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_CTR_RE_SHIFT (21U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_CTR_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_CTR_RE_MASK) #define GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_MODE_FE_MASK (0x400000U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_MODE_FE_SHIFT (22U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_MODE_FE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_MODE_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_MODE_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_MODE_FE_MASK) #define GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_CTR_FE_MASK (0x800000U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_CTR_FE_SHIFT (23U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_CTR_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_CTRL_FLT_CTR_FE_MASK) #define GTM_gtm_cls1_TIM1_CH1_CTRL_CLK_SEL_MASK (0x7000000U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_CLK_SEL_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_CLK_SEL_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_CTRL_CLK_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_CTRL_CLK_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH1_CTRL_FR_ECNT_OFL_MASK (0x8000000U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_FR_ECNT_OFL_SHIFT (27U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_FR_ECNT_OFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_FR_ECNT_OFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_CTRL_FR_ECNT_OFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_CTRL_FR_ECNT_OFL_MASK) #define GTM_gtm_cls1_TIM1_CH1_CTRL_EGPR0_SEL_MASK (0x10000000U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_EGPR0_SEL_SHIFT (28U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_EGPR0_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_EGPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_CTRL_EGPR0_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_CTRL_EGPR0_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH1_CTRL_EGPR1_SEL_MASK (0x20000000U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_EGPR1_SEL_SHIFT (29U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_EGPR1_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_EGPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_CTRL_EGPR1_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_CTRL_EGPR1_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH1_CTRL_TOCTRL_MASK (0xC0000000U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_TOCTRL_SHIFT (30U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_TOCTRL_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH1_CTRL_TOCTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_CTRL_TOCTRL_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_CTRL_TOCTRL_MASK) /*! @} */ /*! @name TIM1_CH1_ECTRL - TIM[i] channel [x] extended control register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH1_ECTRL_EXT_CAP_SRC_MASK (0xFU) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_EXT_CAP_SRC_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_EXT_CAP_SRC_WIDTH (4U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_EXT_CAP_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_ECTRL_EXT_CAP_SRC_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_ECTRL_EXT_CAP_SRC_MASK) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_USE_PREV_TDU_IN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_USE_PREV_TDU_IN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_USE_PREV_TDU_IN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_USE_PREV_TDU_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_ECTRL_USE_PREV_TDU_IN_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_ECTRL_USE_PREV_TDU_IN_MASK) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_TODET_IRQ_SRC_MASK (0xC0U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_TODET_IRQ_SRC_SHIFT (6U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_TODET_IRQ_SRC_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_TODET_IRQ_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_ECTRL_TODET_IRQ_SRC_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_ECTRL_TODET_IRQ_SRC_MASK) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_TDU_START_MASK (0x700U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_TDU_START_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_TDU_START_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_TDU_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_ECTRL_TDU_START_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_ECTRL_TDU_START_MASK) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_TDU_STOP_MASK (0x7000U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_TDU_STOP_SHIFT (12U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_TDU_STOP_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_TDU_STOP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_ECTRL_TDU_STOP_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_ECTRL_TDU_STOP_MASK) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_TDU_RESYNC_MASK (0xF0000U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_TDU_RESYNC_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_TDU_RESYNC_WIDTH (4U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_TDU_RESYNC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_ECTRL_TDU_RESYNC_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_ECTRL_TDU_RESYNC_MASK) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_USE_LUT_MASK (0xC00000U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_USE_LUT_SHIFT (22U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_USE_LUT_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_USE_LUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_ECTRL_USE_LUT_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_ECTRL_USE_LUT_MASK) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_EFLT_CTR_RE_MASK (0x1000000U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_EFLT_CTR_RE_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_EFLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_EFLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_ECTRL_EFLT_CTR_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_ECTRL_EFLT_CTR_RE_MASK) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_EFLT_CTR_FE_MASK (0x2000000U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_EFLT_CTR_FE_SHIFT (25U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_EFLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_EFLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_ECTRL_EFLT_CTR_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_ECTRL_EFLT_CTR_FE_MASK) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_SWAP_CAPTURE_MASK (0x10000000U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_SWAP_CAPTURE_SHIFT (28U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_SWAP_CAPTURE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_SWAP_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_ECTRL_SWAP_CAPTURE_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_ECTRL_SWAP_CAPTURE_MASK) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_IMM_START_MASK (0x20000000U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_IMM_START_SHIFT (29U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_IMM_START_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_IMM_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_ECTRL_IMM_START_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_ECTRL_IMM_START_MASK) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_ECLK_SEL_MASK (0x40000000U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_ECLK_SEL_SHIFT (30U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_ECLK_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_ECLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_ECTRL_ECLK_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_ECTRL_ECLK_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_USE_PREV_CH_IN_MASK (0x80000000U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_USE_PREV_CH_IN_SHIFT (31U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_USE_PREV_CH_IN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_ECTRL_USE_PREV_CH_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_ECTRL_USE_PREV_CH_IN_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_ECTRL_USE_PREV_CH_IN_MASK) /*! @} */ /*! @name TIM1_CH1_IRQ_NOTIFY - TIM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_NEWVAL_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_NEWVAL_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_NEWVAL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_NEWVAL_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_NEWVAL_MASK) #define GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_ECNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_ECNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_CNTOFL_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_CNTOFL_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_CNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_CNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_CNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_GPROFL_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_GPROFL_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_GPROFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_GPROFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_GPROFL_MASK) #define GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_TODET_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_TODET_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_TODET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_TODET_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_TODET_MASK) #define GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_GLITCHDET_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_IRQ_NOTIFY_GLITCHDET_MASK) /*! @} */ /*! @name TIM1_CH1_IRQ_EN - TIM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH1_IRQ_EN_NEWVAL_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_EN_NEWVAL_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_EN_NEWVAL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_EN_NEWVAL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_IRQ_EN_NEWVAL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_IRQ_EN_NEWVAL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH1_IRQ_EN_ECNTOFL_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_EN_ECNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_EN_ECNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_IRQ_EN_ECNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH1_IRQ_EN_CNTOFL_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_EN_CNTOFL_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_EN_CNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_EN_CNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_IRQ_EN_CNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_IRQ_EN_CNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH1_IRQ_EN_GPROFL_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_EN_GPROFL_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_EN_GPROFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_EN_GPROFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_IRQ_EN_GPROFL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_IRQ_EN_GPROFL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH1_IRQ_EN_TODET_IRQ_EN_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_EN_TODET_IRQ_EN_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_EN_TODET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_EN_TODET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_IRQ_EN_TODET_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_IRQ_EN_TODET_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH1_IRQ_EN_GLITCHDET_IRQ_EN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_EN_GLITCHDET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_EN_GLITCHDET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_IRQ_EN_GLITCHDET_IRQ_EN_MASK) /*! @} */ /*! @name TIM1_CH1_IRQ_FORCINT - TIM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_NEWVAL_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_NEWVAL_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_NEWVAL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_NEWVAL_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_NEWVAL_MASK) #define GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_ECNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_ECNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_CNTOFL_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_CNTOFL_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_CNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_CNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_CNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_GPROFL_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_GPROFL_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_GPROFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_GPROFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_GPROFL_MASK) #define GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_TODET_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_TODET_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_TODET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_TODET_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_TODET_MASK) #define GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_GLITCHDET_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_IRQ_FORCINT_TRG_GLITCHDET_MASK) /*! @} */ /*! @name TIM1_CH1_IRQ_MODE - TIM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH1_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH1_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TIM1_CH1_EIRQ_EN - TIM[i] channel [x] error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_NEWVAL_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_NEWVAL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_NEWVAL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_NEWVAL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_ECNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_ECNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_CNTOFL_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_CNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_CNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_CNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_GPROFL_EIRQ_EN_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_GPROFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_GPROFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_GPROFL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_TODET_EIRQ_EN_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_TODET_EIRQ_EN_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_TODET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_TODET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_TODET_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_TODET_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_GLITCHDET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_GLITCHDET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH1_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK) /*! @} */ /*! @name TIM1_CH2_GPR0 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH2_GPR0_GPR0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH2_GPR0_GPR0_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH2_GPR0_GPR0_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH2_GPR0_GPR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_GPR0_GPR0_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_GPR0_GPR0_MASK) #define GTM_gtm_cls1_TIM1_CH2_GPR0_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls1_TIM1_CH2_GPR0_ECNT_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH2_GPR0_ECNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH2_GPR0_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_GPR0_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_GPR0_ECNT_MASK) /*! @} */ /*! @name TIM1_CH2_GPR1 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH2_GPR1_GPR1_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH2_GPR1_GPR1_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH2_GPR1_GPR1_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH2_GPR1_GPR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_GPR1_GPR1_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_GPR1_GPR1_MASK) #define GTM_gtm_cls1_TIM1_CH2_GPR1_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls1_TIM1_CH2_GPR1_ECNT_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH2_GPR1_ECNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH2_GPR1_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_GPR1_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_GPR1_ECNT_MASK) /*! @} */ /*! @name TIM1_CH2_CNT - TIM[i] channel [x] SMU counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH2_CNT_CNT_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH2_CNT_CNT_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH2_CNT_CNT_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH2_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_CNT_CNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_CNT_CNT_MASK) /*! @} */ /*! @name TIM1_CH2_ECNT - TIM[i] channel [x] SMU edge counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH2_ECNT_ECNT_MASK (0xFFFFU) #define GTM_gtm_cls1_TIM1_CH2_ECNT_ECNT_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH2_ECNT_ECNT_WIDTH (16U) #define GTM_gtm_cls1_TIM1_CH2_ECNT_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_ECNT_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_ECNT_ECNT_MASK) /*! @} */ /*! @name TIM1_CH2_CNTS - TIM[i] channel [x] SMU shadow counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH2_CNTS_CNTS_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH2_CNTS_CNTS_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH2_CNTS_CNTS_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH2_CNTS_CNTS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_CNTS_CNTS_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_CNTS_CNTS_MASK) #define GTM_gtm_cls1_TIM1_CH2_CNTS_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls1_TIM1_CH2_CNTS_ECNT_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH2_CNTS_ECNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH2_CNTS_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_CNTS_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_CNTS_ECNT_MASK) /*! @} */ /*! @name TIM1_CH2_TDUC - TIM[i] channel [x] TDU counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH2_TDUC_TO_CNT_MASK (0xFFU) #define GTM_gtm_cls1_TIM1_CH2_TDUC_TO_CNT_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH2_TDUC_TO_CNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH2_TDUC_TO_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_TDUC_TO_CNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_TDUC_TO_CNT_MASK) #define GTM_gtm_cls1_TIM1_CH2_TDUC_TO_CNT1_MASK (0xFF00U) #define GTM_gtm_cls1_TIM1_CH2_TDUC_TO_CNT1_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH2_TDUC_TO_CNT1_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH2_TDUC_TO_CNT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_TDUC_TO_CNT1_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_TDUC_TO_CNT1_MASK) #define GTM_gtm_cls1_TIM1_CH2_TDUC_TO_CNT2_MASK (0xFF0000U) #define GTM_gtm_cls1_TIM1_CH2_TDUC_TO_CNT2_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH2_TDUC_TO_CNT2_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH2_TDUC_TO_CNT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_TDUC_TO_CNT2_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_TDUC_TO_CNT2_MASK) /*! @} */ /*! @name TIM1_CH2_TDUV - TIM[i] channel [x] TDU control register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH2_TDUV_TOV_MASK (0xFFU) #define GTM_gtm_cls1_TIM1_CH2_TDUV_TOV_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH2_TDUV_TOV_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH2_TDUV_TOV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_TDUV_TOV_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_TDUV_TOV_MASK) #define GTM_gtm_cls1_TIM1_CH2_TDUV_TOV1_MASK (0xFF00U) #define GTM_gtm_cls1_TIM1_CH2_TDUV_TOV1_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH2_TDUV_TOV1_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH2_TDUV_TOV1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_TDUV_TOV1_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_TDUV_TOV1_MASK) #define GTM_gtm_cls1_TIM1_CH2_TDUV_TOV2_MASK (0xFF0000U) #define GTM_gtm_cls1_TIM1_CH2_TDUV_TOV2_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH2_TDUV_TOV2_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH2_TDUV_TOV2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_TDUV_TOV2_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_TDUV_TOV2_MASK) #define GTM_gtm_cls1_TIM1_CH2_TDUV_SLICING_MASK (0x3000000U) #define GTM_gtm_cls1_TIM1_CH2_TDUV_SLICING_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH2_TDUV_SLICING_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH2_TDUV_SLICING(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_TDUV_SLICING_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_TDUV_SLICING_MASK) #define GTM_gtm_cls1_TIM1_CH2_TDUV_TCS_USE_SAMPLE_EVT_MASK (0x4000000U) #define GTM_gtm_cls1_TIM1_CH2_TDUV_TCS_USE_SAMPLE_EVT_SHIFT (26U) #define GTM_gtm_cls1_TIM1_CH2_TDUV_TCS_USE_SAMPLE_EVT_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_TDUV_TCS_USE_SAMPLE_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_TDUV_TCS_USE_SAMPLE_EVT_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_TDUV_TCS_USE_SAMPLE_EVT_MASK) #define GTM_gtm_cls1_TIM1_CH2_TDUV_TDU_SAME_CNT_CLK_MASK (0x8000000U) #define GTM_gtm_cls1_TIM1_CH2_TDUV_TDU_SAME_CNT_CLK_SHIFT (27U) #define GTM_gtm_cls1_TIM1_CH2_TDUV_TDU_SAME_CNT_CLK_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_TDUV_TDU_SAME_CNT_CLK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_TDUV_TDU_SAME_CNT_CLK_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_TDUV_TDU_SAME_CNT_CLK_MASK) #define GTM_gtm_cls1_TIM1_CH2_TDUV_TCS_MASK (0x70000000U) #define GTM_gtm_cls1_TIM1_CH2_TDUV_TCS_SHIFT (28U) #define GTM_gtm_cls1_TIM1_CH2_TDUV_TCS_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH2_TDUV_TCS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_TDUV_TCS_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_TDUV_TCS_MASK) /*! @} */ /*! @name TIM1_CH2_FLT_RE - TIM[i] channel [x] filter parameter 0 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH2_FLT_RE_FLT_RE_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH2_FLT_RE_FLT_RE_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH2_FLT_RE_FLT_RE_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH2_FLT_RE_FLT_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_FLT_RE_FLT_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_FLT_RE_FLT_RE_MASK) /*! @} */ /*! @name TIM1_CH2_FLT_FE - TIM[i] channel [x] filter parameter 1 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH2_FLT_FE_FLT_FE_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH2_FLT_FE_FLT_FE_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH2_FLT_FE_FLT_FE_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH2_FLT_FE_FLT_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_FLT_FE_FLT_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_FLT_FE_FLT_FE_MASK) /*! @} */ /*! @name TIM1_CH2_CTRL - TIM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH2_CTRL_TIM_EN_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_TIM_EN_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_TIM_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_TIM_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_CTRL_TIM_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_CTRL_TIM_EN_MASK) #define GTM_gtm_cls1_TIM1_CH2_CTRL_TIM_MODE_MASK (0xEU) #define GTM_gtm_cls1_TIM1_CH2_CTRL_TIM_MODE_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_TIM_MODE_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_TIM_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_CTRL_TIM_MODE_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_CTRL_TIM_MODE_MASK) #define GTM_gtm_cls1_TIM1_CH2_CTRL_OSM_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_OSM_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_CTRL_OSM_MASK) #define GTM_gtm_cls1_TIM1_CH2_CTRL_ARU_EN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_ARU_EN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_CTRL_ARU_EN_MASK) #define GTM_gtm_cls1_TIM1_CH2_CTRL_CICTRL_MASK (0x40U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_CICTRL_SHIFT (6U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_CICTRL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_CICTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_CTRL_CICTRL_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_CTRL_CICTRL_MASK) #define GTM_gtm_cls1_TIM1_CH2_CTRL_GPR0_SEL_MASK (0x300U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_GPR0_SEL_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_GPR0_SEL_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_GPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_CTRL_GPR0_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_CTRL_GPR0_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH2_CTRL_GPR1_SEL_MASK (0xC00U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_GPR1_SEL_SHIFT (10U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_GPR1_SEL_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_GPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_CTRL_GPR1_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_CTRL_GPR1_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH2_CTRL_CNTS_SEL_MASK (0x1000U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_CNTS_SEL_SHIFT (12U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_CNTS_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_CNTS_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_CTRL_CNTS_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_CTRL_CNTS_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH2_CTRL_DSL_MASK (0x2000U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_DSL_SHIFT (13U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_DSL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_CTRL_DSL_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_CTRL_DSL_MASK) #define GTM_gtm_cls1_TIM1_CH2_CTRL_ISL_MASK (0x4000U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_ISL_SHIFT (14U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_ISL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_ISL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_CTRL_ISL_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_CTRL_ISL_MASK) #define GTM_gtm_cls1_TIM1_CH2_CTRL_ECNT_RESET_MASK (0x8000U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_ECNT_RESET_SHIFT (15U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_ECNT_RESET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_ECNT_RESET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_CTRL_ECNT_RESET_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_CTRL_ECNT_RESET_MASK) #define GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_EN_MASK (0x10000U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_EN_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_EN_MASK) #define GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_CNT_FRQ_MASK (0x60000U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_CNT_FRQ_SHIFT (17U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_CNT_FRQ_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_CNT_FRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_CNT_FRQ_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_CNT_FRQ_MASK) #define GTM_gtm_cls1_TIM1_CH2_CTRL_EXT_CAP_EN_MASK (0x80000U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_EXT_CAP_EN_SHIFT (19U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_EXT_CAP_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_EXT_CAP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_CTRL_EXT_CAP_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_CTRL_EXT_CAP_EN_MASK) #define GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_MODE_RE_MASK (0x100000U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_MODE_RE_SHIFT (20U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_MODE_RE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_MODE_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_MODE_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_MODE_RE_MASK) #define GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_CTR_RE_MASK (0x200000U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_CTR_RE_SHIFT (21U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_CTR_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_CTR_RE_MASK) #define GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_MODE_FE_MASK (0x400000U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_MODE_FE_SHIFT (22U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_MODE_FE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_MODE_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_MODE_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_MODE_FE_MASK) #define GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_CTR_FE_MASK (0x800000U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_CTR_FE_SHIFT (23U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_CTR_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_CTRL_FLT_CTR_FE_MASK) #define GTM_gtm_cls1_TIM1_CH2_CTRL_CLK_SEL_MASK (0x7000000U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_CLK_SEL_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_CLK_SEL_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_CTRL_CLK_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_CTRL_CLK_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH2_CTRL_FR_ECNT_OFL_MASK (0x8000000U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_FR_ECNT_OFL_SHIFT (27U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_FR_ECNT_OFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_FR_ECNT_OFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_CTRL_FR_ECNT_OFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_CTRL_FR_ECNT_OFL_MASK) #define GTM_gtm_cls1_TIM1_CH2_CTRL_EGPR0_SEL_MASK (0x10000000U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_EGPR0_SEL_SHIFT (28U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_EGPR0_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_EGPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_CTRL_EGPR0_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_CTRL_EGPR0_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH2_CTRL_EGPR1_SEL_MASK (0x20000000U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_EGPR1_SEL_SHIFT (29U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_EGPR1_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_EGPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_CTRL_EGPR1_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_CTRL_EGPR1_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH2_CTRL_TOCTRL_MASK (0xC0000000U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_TOCTRL_SHIFT (30U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_TOCTRL_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH2_CTRL_TOCTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_CTRL_TOCTRL_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_CTRL_TOCTRL_MASK) /*! @} */ /*! @name TIM1_CH2_ECTRL - TIM[i] channel [x] extended control register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH2_ECTRL_EXT_CAP_SRC_MASK (0xFU) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_EXT_CAP_SRC_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_EXT_CAP_SRC_WIDTH (4U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_EXT_CAP_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_ECTRL_EXT_CAP_SRC_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_ECTRL_EXT_CAP_SRC_MASK) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_USE_PREV_TDU_IN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_USE_PREV_TDU_IN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_USE_PREV_TDU_IN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_USE_PREV_TDU_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_ECTRL_USE_PREV_TDU_IN_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_ECTRL_USE_PREV_TDU_IN_MASK) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_TODET_IRQ_SRC_MASK (0xC0U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_TODET_IRQ_SRC_SHIFT (6U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_TODET_IRQ_SRC_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_TODET_IRQ_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_ECTRL_TODET_IRQ_SRC_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_ECTRL_TODET_IRQ_SRC_MASK) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_TDU_START_MASK (0x700U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_TDU_START_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_TDU_START_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_TDU_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_ECTRL_TDU_START_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_ECTRL_TDU_START_MASK) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_TDU_STOP_MASK (0x7000U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_TDU_STOP_SHIFT (12U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_TDU_STOP_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_TDU_STOP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_ECTRL_TDU_STOP_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_ECTRL_TDU_STOP_MASK) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_TDU_RESYNC_MASK (0xF0000U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_TDU_RESYNC_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_TDU_RESYNC_WIDTH (4U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_TDU_RESYNC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_ECTRL_TDU_RESYNC_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_ECTRL_TDU_RESYNC_MASK) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_USE_LUT_MASK (0xC00000U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_USE_LUT_SHIFT (22U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_USE_LUT_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_USE_LUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_ECTRL_USE_LUT_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_ECTRL_USE_LUT_MASK) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_EFLT_CTR_RE_MASK (0x1000000U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_EFLT_CTR_RE_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_EFLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_EFLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_ECTRL_EFLT_CTR_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_ECTRL_EFLT_CTR_RE_MASK) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_EFLT_CTR_FE_MASK (0x2000000U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_EFLT_CTR_FE_SHIFT (25U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_EFLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_EFLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_ECTRL_EFLT_CTR_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_ECTRL_EFLT_CTR_FE_MASK) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_SWAP_CAPTURE_MASK (0x10000000U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_SWAP_CAPTURE_SHIFT (28U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_SWAP_CAPTURE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_SWAP_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_ECTRL_SWAP_CAPTURE_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_ECTRL_SWAP_CAPTURE_MASK) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_IMM_START_MASK (0x20000000U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_IMM_START_SHIFT (29U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_IMM_START_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_IMM_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_ECTRL_IMM_START_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_ECTRL_IMM_START_MASK) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_ECLK_SEL_MASK (0x40000000U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_ECLK_SEL_SHIFT (30U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_ECLK_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_ECLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_ECTRL_ECLK_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_ECTRL_ECLK_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_USE_PREV_CH_IN_MASK (0x80000000U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_USE_PREV_CH_IN_SHIFT (31U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_USE_PREV_CH_IN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_ECTRL_USE_PREV_CH_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_ECTRL_USE_PREV_CH_IN_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_ECTRL_USE_PREV_CH_IN_MASK) /*! @} */ /*! @name TIM1_CH2_IRQ_NOTIFY - TIM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_NEWVAL_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_NEWVAL_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_NEWVAL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_NEWVAL_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_NEWVAL_MASK) #define GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_ECNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_ECNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_CNTOFL_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_CNTOFL_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_CNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_CNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_CNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_GPROFL_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_GPROFL_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_GPROFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_GPROFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_GPROFL_MASK) #define GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_TODET_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_TODET_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_TODET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_TODET_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_TODET_MASK) #define GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_GLITCHDET_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_IRQ_NOTIFY_GLITCHDET_MASK) /*! @} */ /*! @name TIM1_CH2_IRQ_EN - TIM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH2_IRQ_EN_NEWVAL_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_EN_NEWVAL_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_EN_NEWVAL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_EN_NEWVAL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_IRQ_EN_NEWVAL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_IRQ_EN_NEWVAL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH2_IRQ_EN_ECNTOFL_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_EN_ECNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_EN_ECNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_IRQ_EN_ECNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH2_IRQ_EN_CNTOFL_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_EN_CNTOFL_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_EN_CNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_EN_CNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_IRQ_EN_CNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_IRQ_EN_CNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH2_IRQ_EN_GPROFL_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_EN_GPROFL_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_EN_GPROFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_EN_GPROFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_IRQ_EN_GPROFL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_IRQ_EN_GPROFL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH2_IRQ_EN_TODET_IRQ_EN_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_EN_TODET_IRQ_EN_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_EN_TODET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_EN_TODET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_IRQ_EN_TODET_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_IRQ_EN_TODET_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH2_IRQ_EN_GLITCHDET_IRQ_EN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_EN_GLITCHDET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_EN_GLITCHDET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_IRQ_EN_GLITCHDET_IRQ_EN_MASK) /*! @} */ /*! @name TIM1_CH2_IRQ_FORCINT - TIM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_NEWVAL_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_NEWVAL_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_NEWVAL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_NEWVAL_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_NEWVAL_MASK) #define GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_ECNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_ECNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_CNTOFL_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_CNTOFL_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_CNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_CNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_CNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_GPROFL_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_GPROFL_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_GPROFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_GPROFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_GPROFL_MASK) #define GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_TODET_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_TODET_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_TODET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_TODET_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_TODET_MASK) #define GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_GLITCHDET_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_IRQ_FORCINT_TRG_GLITCHDET_MASK) /*! @} */ /*! @name TIM1_CH2_IRQ_MODE - TIM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH2_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH2_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TIM1_CH2_EIRQ_EN - TIM[i] channel [x] error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_NEWVAL_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_NEWVAL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_NEWVAL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_NEWVAL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_ECNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_ECNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_CNTOFL_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_CNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_CNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_CNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_GPROFL_EIRQ_EN_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_GPROFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_GPROFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_GPROFL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_TODET_EIRQ_EN_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_TODET_EIRQ_EN_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_TODET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_TODET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_TODET_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_TODET_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_GLITCHDET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_GLITCHDET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH2_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK) /*! @} */ /*! @name TIM1_CH3_GPR0 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH3_GPR0_GPR0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH3_GPR0_GPR0_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH3_GPR0_GPR0_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH3_GPR0_GPR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_GPR0_GPR0_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_GPR0_GPR0_MASK) #define GTM_gtm_cls1_TIM1_CH3_GPR0_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls1_TIM1_CH3_GPR0_ECNT_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH3_GPR0_ECNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH3_GPR0_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_GPR0_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_GPR0_ECNT_MASK) /*! @} */ /*! @name TIM1_CH3_GPR1 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH3_GPR1_GPR1_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH3_GPR1_GPR1_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH3_GPR1_GPR1_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH3_GPR1_GPR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_GPR1_GPR1_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_GPR1_GPR1_MASK) #define GTM_gtm_cls1_TIM1_CH3_GPR1_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls1_TIM1_CH3_GPR1_ECNT_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH3_GPR1_ECNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH3_GPR1_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_GPR1_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_GPR1_ECNT_MASK) /*! @} */ /*! @name TIM1_CH3_CNT - TIM[i] channel [x] SMU counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH3_CNT_CNT_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH3_CNT_CNT_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH3_CNT_CNT_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH3_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_CNT_CNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_CNT_CNT_MASK) /*! @} */ /*! @name TIM1_CH3_ECNT - TIM[i] channel [x] SMU edge counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH3_ECNT_ECNT_MASK (0xFFFFU) #define GTM_gtm_cls1_TIM1_CH3_ECNT_ECNT_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH3_ECNT_ECNT_WIDTH (16U) #define GTM_gtm_cls1_TIM1_CH3_ECNT_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_ECNT_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_ECNT_ECNT_MASK) /*! @} */ /*! @name TIM1_CH3_CNTS - TIM[i] channel [x] SMU shadow counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH3_CNTS_CNTS_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH3_CNTS_CNTS_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH3_CNTS_CNTS_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH3_CNTS_CNTS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_CNTS_CNTS_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_CNTS_CNTS_MASK) #define GTM_gtm_cls1_TIM1_CH3_CNTS_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls1_TIM1_CH3_CNTS_ECNT_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH3_CNTS_ECNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH3_CNTS_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_CNTS_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_CNTS_ECNT_MASK) /*! @} */ /*! @name TIM1_CH3_TDUC - TIM[i] channel [x] TDU counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH3_TDUC_TO_CNT_MASK (0xFFU) #define GTM_gtm_cls1_TIM1_CH3_TDUC_TO_CNT_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH3_TDUC_TO_CNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH3_TDUC_TO_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_TDUC_TO_CNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_TDUC_TO_CNT_MASK) #define GTM_gtm_cls1_TIM1_CH3_TDUC_TO_CNT1_MASK (0xFF00U) #define GTM_gtm_cls1_TIM1_CH3_TDUC_TO_CNT1_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH3_TDUC_TO_CNT1_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH3_TDUC_TO_CNT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_TDUC_TO_CNT1_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_TDUC_TO_CNT1_MASK) #define GTM_gtm_cls1_TIM1_CH3_TDUC_TO_CNT2_MASK (0xFF0000U) #define GTM_gtm_cls1_TIM1_CH3_TDUC_TO_CNT2_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH3_TDUC_TO_CNT2_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH3_TDUC_TO_CNT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_TDUC_TO_CNT2_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_TDUC_TO_CNT2_MASK) /*! @} */ /*! @name TIM1_CH3_TDUV - TIM[i] channel [x] TDU control register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH3_TDUV_TOV_MASK (0xFFU) #define GTM_gtm_cls1_TIM1_CH3_TDUV_TOV_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH3_TDUV_TOV_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH3_TDUV_TOV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_TDUV_TOV_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_TDUV_TOV_MASK) #define GTM_gtm_cls1_TIM1_CH3_TDUV_TOV1_MASK (0xFF00U) #define GTM_gtm_cls1_TIM1_CH3_TDUV_TOV1_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH3_TDUV_TOV1_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH3_TDUV_TOV1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_TDUV_TOV1_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_TDUV_TOV1_MASK) #define GTM_gtm_cls1_TIM1_CH3_TDUV_TOV2_MASK (0xFF0000U) #define GTM_gtm_cls1_TIM1_CH3_TDUV_TOV2_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH3_TDUV_TOV2_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH3_TDUV_TOV2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_TDUV_TOV2_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_TDUV_TOV2_MASK) #define GTM_gtm_cls1_TIM1_CH3_TDUV_SLICING_MASK (0x3000000U) #define GTM_gtm_cls1_TIM1_CH3_TDUV_SLICING_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH3_TDUV_SLICING_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH3_TDUV_SLICING(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_TDUV_SLICING_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_TDUV_SLICING_MASK) #define GTM_gtm_cls1_TIM1_CH3_TDUV_TCS_USE_SAMPLE_EVT_MASK (0x4000000U) #define GTM_gtm_cls1_TIM1_CH3_TDUV_TCS_USE_SAMPLE_EVT_SHIFT (26U) #define GTM_gtm_cls1_TIM1_CH3_TDUV_TCS_USE_SAMPLE_EVT_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_TDUV_TCS_USE_SAMPLE_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_TDUV_TCS_USE_SAMPLE_EVT_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_TDUV_TCS_USE_SAMPLE_EVT_MASK) #define GTM_gtm_cls1_TIM1_CH3_TDUV_TDU_SAME_CNT_CLK_MASK (0x8000000U) #define GTM_gtm_cls1_TIM1_CH3_TDUV_TDU_SAME_CNT_CLK_SHIFT (27U) #define GTM_gtm_cls1_TIM1_CH3_TDUV_TDU_SAME_CNT_CLK_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_TDUV_TDU_SAME_CNT_CLK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_TDUV_TDU_SAME_CNT_CLK_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_TDUV_TDU_SAME_CNT_CLK_MASK) #define GTM_gtm_cls1_TIM1_CH3_TDUV_TCS_MASK (0x70000000U) #define GTM_gtm_cls1_TIM1_CH3_TDUV_TCS_SHIFT (28U) #define GTM_gtm_cls1_TIM1_CH3_TDUV_TCS_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH3_TDUV_TCS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_TDUV_TCS_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_TDUV_TCS_MASK) /*! @} */ /*! @name TIM1_CH3_FLT_RE - TIM[i] channel [x] filter parameter 0 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH3_FLT_RE_FLT_RE_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH3_FLT_RE_FLT_RE_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH3_FLT_RE_FLT_RE_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH3_FLT_RE_FLT_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_FLT_RE_FLT_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_FLT_RE_FLT_RE_MASK) /*! @} */ /*! @name TIM1_CH3_FLT_FE - TIM[i] channel [x] filter parameter 1 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH3_FLT_FE_FLT_FE_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH3_FLT_FE_FLT_FE_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH3_FLT_FE_FLT_FE_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH3_FLT_FE_FLT_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_FLT_FE_FLT_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_FLT_FE_FLT_FE_MASK) /*! @} */ /*! @name TIM1_CH3_CTRL - TIM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH3_CTRL_TIM_EN_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_TIM_EN_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_TIM_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_TIM_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_CTRL_TIM_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_CTRL_TIM_EN_MASK) #define GTM_gtm_cls1_TIM1_CH3_CTRL_TIM_MODE_MASK (0xEU) #define GTM_gtm_cls1_TIM1_CH3_CTRL_TIM_MODE_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_TIM_MODE_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_TIM_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_CTRL_TIM_MODE_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_CTRL_TIM_MODE_MASK) #define GTM_gtm_cls1_TIM1_CH3_CTRL_OSM_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_OSM_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_CTRL_OSM_MASK) #define GTM_gtm_cls1_TIM1_CH3_CTRL_ARU_EN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_ARU_EN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_CTRL_ARU_EN_MASK) #define GTM_gtm_cls1_TIM1_CH3_CTRL_CICTRL_MASK (0x40U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_CICTRL_SHIFT (6U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_CICTRL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_CICTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_CTRL_CICTRL_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_CTRL_CICTRL_MASK) #define GTM_gtm_cls1_TIM1_CH3_CTRL_GPR0_SEL_MASK (0x300U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_GPR0_SEL_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_GPR0_SEL_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_GPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_CTRL_GPR0_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_CTRL_GPR0_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH3_CTRL_GPR1_SEL_MASK (0xC00U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_GPR1_SEL_SHIFT (10U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_GPR1_SEL_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_GPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_CTRL_GPR1_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_CTRL_GPR1_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH3_CTRL_CNTS_SEL_MASK (0x1000U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_CNTS_SEL_SHIFT (12U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_CNTS_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_CNTS_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_CTRL_CNTS_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_CTRL_CNTS_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH3_CTRL_DSL_MASK (0x2000U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_DSL_SHIFT (13U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_DSL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_CTRL_DSL_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_CTRL_DSL_MASK) #define GTM_gtm_cls1_TIM1_CH3_CTRL_ISL_MASK (0x4000U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_ISL_SHIFT (14U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_ISL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_ISL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_CTRL_ISL_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_CTRL_ISL_MASK) #define GTM_gtm_cls1_TIM1_CH3_CTRL_ECNT_RESET_MASK (0x8000U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_ECNT_RESET_SHIFT (15U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_ECNT_RESET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_ECNT_RESET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_CTRL_ECNT_RESET_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_CTRL_ECNT_RESET_MASK) #define GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_EN_MASK (0x10000U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_EN_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_EN_MASK) #define GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_CNT_FRQ_MASK (0x60000U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_CNT_FRQ_SHIFT (17U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_CNT_FRQ_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_CNT_FRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_CNT_FRQ_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_CNT_FRQ_MASK) #define GTM_gtm_cls1_TIM1_CH3_CTRL_EXT_CAP_EN_MASK (0x80000U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_EXT_CAP_EN_SHIFT (19U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_EXT_CAP_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_EXT_CAP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_CTRL_EXT_CAP_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_CTRL_EXT_CAP_EN_MASK) #define GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_MODE_RE_MASK (0x100000U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_MODE_RE_SHIFT (20U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_MODE_RE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_MODE_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_MODE_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_MODE_RE_MASK) #define GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_CTR_RE_MASK (0x200000U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_CTR_RE_SHIFT (21U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_CTR_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_CTR_RE_MASK) #define GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_MODE_FE_MASK (0x400000U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_MODE_FE_SHIFT (22U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_MODE_FE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_MODE_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_MODE_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_MODE_FE_MASK) #define GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_CTR_FE_MASK (0x800000U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_CTR_FE_SHIFT (23U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_CTR_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_CTRL_FLT_CTR_FE_MASK) #define GTM_gtm_cls1_TIM1_CH3_CTRL_CLK_SEL_MASK (0x7000000U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_CLK_SEL_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_CLK_SEL_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_CTRL_CLK_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_CTRL_CLK_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH3_CTRL_FR_ECNT_OFL_MASK (0x8000000U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_FR_ECNT_OFL_SHIFT (27U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_FR_ECNT_OFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_FR_ECNT_OFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_CTRL_FR_ECNT_OFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_CTRL_FR_ECNT_OFL_MASK) #define GTM_gtm_cls1_TIM1_CH3_CTRL_EGPR0_SEL_MASK (0x10000000U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_EGPR0_SEL_SHIFT (28U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_EGPR0_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_EGPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_CTRL_EGPR0_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_CTRL_EGPR0_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH3_CTRL_EGPR1_SEL_MASK (0x20000000U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_EGPR1_SEL_SHIFT (29U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_EGPR1_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_EGPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_CTRL_EGPR1_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_CTRL_EGPR1_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH3_CTRL_TOCTRL_MASK (0xC0000000U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_TOCTRL_SHIFT (30U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_TOCTRL_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH3_CTRL_TOCTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_CTRL_TOCTRL_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_CTRL_TOCTRL_MASK) /*! @} */ /*! @name TIM1_CH3_ECTRL - TIM[i] channel [x] extended control register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH3_ECTRL_EXT_CAP_SRC_MASK (0xFU) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_EXT_CAP_SRC_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_EXT_CAP_SRC_WIDTH (4U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_EXT_CAP_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_ECTRL_EXT_CAP_SRC_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_ECTRL_EXT_CAP_SRC_MASK) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_USE_PREV_TDU_IN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_USE_PREV_TDU_IN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_USE_PREV_TDU_IN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_USE_PREV_TDU_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_ECTRL_USE_PREV_TDU_IN_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_ECTRL_USE_PREV_TDU_IN_MASK) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_TODET_IRQ_SRC_MASK (0xC0U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_TODET_IRQ_SRC_SHIFT (6U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_TODET_IRQ_SRC_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_TODET_IRQ_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_ECTRL_TODET_IRQ_SRC_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_ECTRL_TODET_IRQ_SRC_MASK) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_TDU_START_MASK (0x700U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_TDU_START_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_TDU_START_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_TDU_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_ECTRL_TDU_START_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_ECTRL_TDU_START_MASK) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_TDU_STOP_MASK (0x7000U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_TDU_STOP_SHIFT (12U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_TDU_STOP_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_TDU_STOP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_ECTRL_TDU_STOP_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_ECTRL_TDU_STOP_MASK) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_TDU_RESYNC_MASK (0xF0000U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_TDU_RESYNC_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_TDU_RESYNC_WIDTH (4U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_TDU_RESYNC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_ECTRL_TDU_RESYNC_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_ECTRL_TDU_RESYNC_MASK) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_USE_LUT_MASK (0xC00000U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_USE_LUT_SHIFT (22U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_USE_LUT_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_USE_LUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_ECTRL_USE_LUT_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_ECTRL_USE_LUT_MASK) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_EFLT_CTR_RE_MASK (0x1000000U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_EFLT_CTR_RE_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_EFLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_EFLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_ECTRL_EFLT_CTR_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_ECTRL_EFLT_CTR_RE_MASK) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_EFLT_CTR_FE_MASK (0x2000000U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_EFLT_CTR_FE_SHIFT (25U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_EFLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_EFLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_ECTRL_EFLT_CTR_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_ECTRL_EFLT_CTR_FE_MASK) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_SWAP_CAPTURE_MASK (0x10000000U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_SWAP_CAPTURE_SHIFT (28U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_SWAP_CAPTURE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_SWAP_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_ECTRL_SWAP_CAPTURE_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_ECTRL_SWAP_CAPTURE_MASK) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_IMM_START_MASK (0x20000000U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_IMM_START_SHIFT (29U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_IMM_START_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_IMM_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_ECTRL_IMM_START_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_ECTRL_IMM_START_MASK) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_ECLK_SEL_MASK (0x40000000U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_ECLK_SEL_SHIFT (30U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_ECLK_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_ECLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_ECTRL_ECLK_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_ECTRL_ECLK_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_USE_PREV_CH_IN_MASK (0x80000000U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_USE_PREV_CH_IN_SHIFT (31U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_USE_PREV_CH_IN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_ECTRL_USE_PREV_CH_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_ECTRL_USE_PREV_CH_IN_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_ECTRL_USE_PREV_CH_IN_MASK) /*! @} */ /*! @name TIM1_CH3_IRQ_NOTIFY - TIM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_NEWVAL_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_NEWVAL_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_NEWVAL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_NEWVAL_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_NEWVAL_MASK) #define GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_ECNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_ECNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_CNTOFL_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_CNTOFL_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_CNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_CNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_CNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_GPROFL_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_GPROFL_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_GPROFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_GPROFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_GPROFL_MASK) #define GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_TODET_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_TODET_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_TODET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_TODET_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_TODET_MASK) #define GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_GLITCHDET_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_IRQ_NOTIFY_GLITCHDET_MASK) /*! @} */ /*! @name TIM1_CH3_IRQ_EN - TIM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH3_IRQ_EN_NEWVAL_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_EN_NEWVAL_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_EN_NEWVAL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_EN_NEWVAL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_IRQ_EN_NEWVAL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_IRQ_EN_NEWVAL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH3_IRQ_EN_ECNTOFL_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_EN_ECNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_EN_ECNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_IRQ_EN_ECNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH3_IRQ_EN_CNTOFL_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_EN_CNTOFL_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_EN_CNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_EN_CNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_IRQ_EN_CNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_IRQ_EN_CNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH3_IRQ_EN_GPROFL_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_EN_GPROFL_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_EN_GPROFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_EN_GPROFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_IRQ_EN_GPROFL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_IRQ_EN_GPROFL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH3_IRQ_EN_TODET_IRQ_EN_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_EN_TODET_IRQ_EN_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_EN_TODET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_EN_TODET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_IRQ_EN_TODET_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_IRQ_EN_TODET_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH3_IRQ_EN_GLITCHDET_IRQ_EN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_EN_GLITCHDET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_EN_GLITCHDET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_IRQ_EN_GLITCHDET_IRQ_EN_MASK) /*! @} */ /*! @name TIM1_CH3_IRQ_FORCINT - TIM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_NEWVAL_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_NEWVAL_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_NEWVAL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_NEWVAL_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_NEWVAL_MASK) #define GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_ECNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_ECNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_CNTOFL_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_CNTOFL_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_CNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_CNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_CNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_GPROFL_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_GPROFL_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_GPROFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_GPROFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_GPROFL_MASK) #define GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_TODET_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_TODET_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_TODET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_TODET_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_TODET_MASK) #define GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_GLITCHDET_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_IRQ_FORCINT_TRG_GLITCHDET_MASK) /*! @} */ /*! @name TIM1_CH3_IRQ_MODE - TIM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH3_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH3_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TIM1_CH3_EIRQ_EN - TIM[i] channel [x] error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_NEWVAL_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_NEWVAL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_NEWVAL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_NEWVAL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_ECNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_ECNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_CNTOFL_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_CNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_CNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_CNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_GPROFL_EIRQ_EN_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_GPROFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_GPROFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_GPROFL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_TODET_EIRQ_EN_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_TODET_EIRQ_EN_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_TODET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_TODET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_TODET_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_TODET_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_GLITCHDET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_GLITCHDET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH3_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK) /*! @} */ /*! @name TIM1_CH4_GPR0 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH4_GPR0_GPR0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH4_GPR0_GPR0_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH4_GPR0_GPR0_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH4_GPR0_GPR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_GPR0_GPR0_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_GPR0_GPR0_MASK) #define GTM_gtm_cls1_TIM1_CH4_GPR0_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls1_TIM1_CH4_GPR0_ECNT_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH4_GPR0_ECNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH4_GPR0_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_GPR0_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_GPR0_ECNT_MASK) /*! @} */ /*! @name TIM1_CH4_GPR1 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH4_GPR1_GPR1_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH4_GPR1_GPR1_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH4_GPR1_GPR1_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH4_GPR1_GPR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_GPR1_GPR1_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_GPR1_GPR1_MASK) #define GTM_gtm_cls1_TIM1_CH4_GPR1_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls1_TIM1_CH4_GPR1_ECNT_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH4_GPR1_ECNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH4_GPR1_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_GPR1_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_GPR1_ECNT_MASK) /*! @} */ /*! @name TIM1_CH4_CNT - TIM[i] channel [x] SMU counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH4_CNT_CNT_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH4_CNT_CNT_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH4_CNT_CNT_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH4_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_CNT_CNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_CNT_CNT_MASK) /*! @} */ /*! @name TIM1_CH4_ECNT - TIM[i] channel [x] SMU edge counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH4_ECNT_ECNT_MASK (0xFFFFU) #define GTM_gtm_cls1_TIM1_CH4_ECNT_ECNT_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH4_ECNT_ECNT_WIDTH (16U) #define GTM_gtm_cls1_TIM1_CH4_ECNT_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_ECNT_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_ECNT_ECNT_MASK) /*! @} */ /*! @name TIM1_CH4_CNTS - TIM[i] channel [x] SMU shadow counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH4_CNTS_CNTS_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH4_CNTS_CNTS_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH4_CNTS_CNTS_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH4_CNTS_CNTS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_CNTS_CNTS_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_CNTS_CNTS_MASK) #define GTM_gtm_cls1_TIM1_CH4_CNTS_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls1_TIM1_CH4_CNTS_ECNT_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH4_CNTS_ECNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH4_CNTS_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_CNTS_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_CNTS_ECNT_MASK) /*! @} */ /*! @name TIM1_CH4_TDUC - TIM[i] channel [x] TDU counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH4_TDUC_TO_CNT_MASK (0xFFU) #define GTM_gtm_cls1_TIM1_CH4_TDUC_TO_CNT_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH4_TDUC_TO_CNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH4_TDUC_TO_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_TDUC_TO_CNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_TDUC_TO_CNT_MASK) #define GTM_gtm_cls1_TIM1_CH4_TDUC_TO_CNT1_MASK (0xFF00U) #define GTM_gtm_cls1_TIM1_CH4_TDUC_TO_CNT1_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH4_TDUC_TO_CNT1_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH4_TDUC_TO_CNT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_TDUC_TO_CNT1_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_TDUC_TO_CNT1_MASK) #define GTM_gtm_cls1_TIM1_CH4_TDUC_TO_CNT2_MASK (0xFF0000U) #define GTM_gtm_cls1_TIM1_CH4_TDUC_TO_CNT2_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH4_TDUC_TO_CNT2_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH4_TDUC_TO_CNT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_TDUC_TO_CNT2_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_TDUC_TO_CNT2_MASK) /*! @} */ /*! @name TIM1_CH4_TDUV - TIM[i] channel [x] TDU control register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH4_TDUV_TOV_MASK (0xFFU) #define GTM_gtm_cls1_TIM1_CH4_TDUV_TOV_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH4_TDUV_TOV_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH4_TDUV_TOV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_TDUV_TOV_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_TDUV_TOV_MASK) #define GTM_gtm_cls1_TIM1_CH4_TDUV_TOV1_MASK (0xFF00U) #define GTM_gtm_cls1_TIM1_CH4_TDUV_TOV1_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH4_TDUV_TOV1_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH4_TDUV_TOV1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_TDUV_TOV1_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_TDUV_TOV1_MASK) #define GTM_gtm_cls1_TIM1_CH4_TDUV_TOV2_MASK (0xFF0000U) #define GTM_gtm_cls1_TIM1_CH4_TDUV_TOV2_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH4_TDUV_TOV2_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH4_TDUV_TOV2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_TDUV_TOV2_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_TDUV_TOV2_MASK) #define GTM_gtm_cls1_TIM1_CH4_TDUV_SLICING_MASK (0x3000000U) #define GTM_gtm_cls1_TIM1_CH4_TDUV_SLICING_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH4_TDUV_SLICING_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH4_TDUV_SLICING(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_TDUV_SLICING_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_TDUV_SLICING_MASK) #define GTM_gtm_cls1_TIM1_CH4_TDUV_TCS_USE_SAMPLE_EVT_MASK (0x4000000U) #define GTM_gtm_cls1_TIM1_CH4_TDUV_TCS_USE_SAMPLE_EVT_SHIFT (26U) #define GTM_gtm_cls1_TIM1_CH4_TDUV_TCS_USE_SAMPLE_EVT_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_TDUV_TCS_USE_SAMPLE_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_TDUV_TCS_USE_SAMPLE_EVT_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_TDUV_TCS_USE_SAMPLE_EVT_MASK) #define GTM_gtm_cls1_TIM1_CH4_TDUV_TDU_SAME_CNT_CLK_MASK (0x8000000U) #define GTM_gtm_cls1_TIM1_CH4_TDUV_TDU_SAME_CNT_CLK_SHIFT (27U) #define GTM_gtm_cls1_TIM1_CH4_TDUV_TDU_SAME_CNT_CLK_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_TDUV_TDU_SAME_CNT_CLK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_TDUV_TDU_SAME_CNT_CLK_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_TDUV_TDU_SAME_CNT_CLK_MASK) #define GTM_gtm_cls1_TIM1_CH4_TDUV_TCS_MASK (0x70000000U) #define GTM_gtm_cls1_TIM1_CH4_TDUV_TCS_SHIFT (28U) #define GTM_gtm_cls1_TIM1_CH4_TDUV_TCS_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH4_TDUV_TCS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_TDUV_TCS_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_TDUV_TCS_MASK) /*! @} */ /*! @name TIM1_CH4_FLT_RE - TIM[i] channel [x] filter parameter 0 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH4_FLT_RE_FLT_RE_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH4_FLT_RE_FLT_RE_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH4_FLT_RE_FLT_RE_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH4_FLT_RE_FLT_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_FLT_RE_FLT_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_FLT_RE_FLT_RE_MASK) /*! @} */ /*! @name TIM1_CH4_FLT_FE - TIM[i] channel [x] filter parameter 1 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH4_FLT_FE_FLT_FE_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH4_FLT_FE_FLT_FE_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH4_FLT_FE_FLT_FE_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH4_FLT_FE_FLT_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_FLT_FE_FLT_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_FLT_FE_FLT_FE_MASK) /*! @} */ /*! @name TIM1_CH4_CTRL - TIM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH4_CTRL_TIM_EN_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_TIM_EN_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_TIM_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_TIM_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_CTRL_TIM_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_CTRL_TIM_EN_MASK) #define GTM_gtm_cls1_TIM1_CH4_CTRL_TIM_MODE_MASK (0xEU) #define GTM_gtm_cls1_TIM1_CH4_CTRL_TIM_MODE_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_TIM_MODE_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_TIM_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_CTRL_TIM_MODE_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_CTRL_TIM_MODE_MASK) #define GTM_gtm_cls1_TIM1_CH4_CTRL_OSM_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_OSM_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_CTRL_OSM_MASK) #define GTM_gtm_cls1_TIM1_CH4_CTRL_ARU_EN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_ARU_EN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_CTRL_ARU_EN_MASK) #define GTM_gtm_cls1_TIM1_CH4_CTRL_CICTRL_MASK (0x40U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_CICTRL_SHIFT (6U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_CICTRL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_CICTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_CTRL_CICTRL_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_CTRL_CICTRL_MASK) #define GTM_gtm_cls1_TIM1_CH4_CTRL_GPR0_SEL_MASK (0x300U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_GPR0_SEL_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_GPR0_SEL_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_GPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_CTRL_GPR0_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_CTRL_GPR0_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH4_CTRL_GPR1_SEL_MASK (0xC00U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_GPR1_SEL_SHIFT (10U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_GPR1_SEL_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_GPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_CTRL_GPR1_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_CTRL_GPR1_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH4_CTRL_CNTS_SEL_MASK (0x1000U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_CNTS_SEL_SHIFT (12U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_CNTS_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_CNTS_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_CTRL_CNTS_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_CTRL_CNTS_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH4_CTRL_DSL_MASK (0x2000U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_DSL_SHIFT (13U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_DSL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_CTRL_DSL_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_CTRL_DSL_MASK) #define GTM_gtm_cls1_TIM1_CH4_CTRL_ISL_MASK (0x4000U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_ISL_SHIFT (14U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_ISL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_ISL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_CTRL_ISL_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_CTRL_ISL_MASK) #define GTM_gtm_cls1_TIM1_CH4_CTRL_ECNT_RESET_MASK (0x8000U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_ECNT_RESET_SHIFT (15U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_ECNT_RESET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_ECNT_RESET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_CTRL_ECNT_RESET_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_CTRL_ECNT_RESET_MASK) #define GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_EN_MASK (0x10000U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_EN_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_EN_MASK) #define GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_CNT_FRQ_MASK (0x60000U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_CNT_FRQ_SHIFT (17U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_CNT_FRQ_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_CNT_FRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_CNT_FRQ_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_CNT_FRQ_MASK) #define GTM_gtm_cls1_TIM1_CH4_CTRL_EXT_CAP_EN_MASK (0x80000U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_EXT_CAP_EN_SHIFT (19U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_EXT_CAP_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_EXT_CAP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_CTRL_EXT_CAP_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_CTRL_EXT_CAP_EN_MASK) #define GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_MODE_RE_MASK (0x100000U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_MODE_RE_SHIFT (20U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_MODE_RE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_MODE_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_MODE_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_MODE_RE_MASK) #define GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_CTR_RE_MASK (0x200000U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_CTR_RE_SHIFT (21U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_CTR_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_CTR_RE_MASK) #define GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_MODE_FE_MASK (0x400000U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_MODE_FE_SHIFT (22U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_MODE_FE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_MODE_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_MODE_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_MODE_FE_MASK) #define GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_CTR_FE_MASK (0x800000U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_CTR_FE_SHIFT (23U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_CTR_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_CTRL_FLT_CTR_FE_MASK) #define GTM_gtm_cls1_TIM1_CH4_CTRL_CLK_SEL_MASK (0x7000000U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_CLK_SEL_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_CLK_SEL_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_CTRL_CLK_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_CTRL_CLK_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH4_CTRL_FR_ECNT_OFL_MASK (0x8000000U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_FR_ECNT_OFL_SHIFT (27U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_FR_ECNT_OFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_FR_ECNT_OFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_CTRL_FR_ECNT_OFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_CTRL_FR_ECNT_OFL_MASK) #define GTM_gtm_cls1_TIM1_CH4_CTRL_EGPR0_SEL_MASK (0x10000000U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_EGPR0_SEL_SHIFT (28U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_EGPR0_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_EGPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_CTRL_EGPR0_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_CTRL_EGPR0_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH4_CTRL_EGPR1_SEL_MASK (0x20000000U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_EGPR1_SEL_SHIFT (29U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_EGPR1_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_EGPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_CTRL_EGPR1_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_CTRL_EGPR1_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH4_CTRL_TOCTRL_MASK (0xC0000000U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_TOCTRL_SHIFT (30U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_TOCTRL_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH4_CTRL_TOCTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_CTRL_TOCTRL_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_CTRL_TOCTRL_MASK) /*! @} */ /*! @name TIM1_CH4_ECTRL - TIM[i] channel [x] extended control register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH4_ECTRL_EXT_CAP_SRC_MASK (0xFU) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_EXT_CAP_SRC_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_EXT_CAP_SRC_WIDTH (4U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_EXT_CAP_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_ECTRL_EXT_CAP_SRC_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_ECTRL_EXT_CAP_SRC_MASK) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_USE_PREV_TDU_IN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_USE_PREV_TDU_IN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_USE_PREV_TDU_IN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_USE_PREV_TDU_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_ECTRL_USE_PREV_TDU_IN_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_ECTRL_USE_PREV_TDU_IN_MASK) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_TODET_IRQ_SRC_MASK (0xC0U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_TODET_IRQ_SRC_SHIFT (6U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_TODET_IRQ_SRC_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_TODET_IRQ_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_ECTRL_TODET_IRQ_SRC_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_ECTRL_TODET_IRQ_SRC_MASK) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_TDU_START_MASK (0x700U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_TDU_START_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_TDU_START_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_TDU_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_ECTRL_TDU_START_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_ECTRL_TDU_START_MASK) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_TDU_STOP_MASK (0x7000U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_TDU_STOP_SHIFT (12U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_TDU_STOP_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_TDU_STOP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_ECTRL_TDU_STOP_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_ECTRL_TDU_STOP_MASK) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_TDU_RESYNC_MASK (0xF0000U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_TDU_RESYNC_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_TDU_RESYNC_WIDTH (4U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_TDU_RESYNC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_ECTRL_TDU_RESYNC_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_ECTRL_TDU_RESYNC_MASK) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_USE_LUT_MASK (0xC00000U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_USE_LUT_SHIFT (22U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_USE_LUT_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_USE_LUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_ECTRL_USE_LUT_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_ECTRL_USE_LUT_MASK) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_EFLT_CTR_RE_MASK (0x1000000U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_EFLT_CTR_RE_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_EFLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_EFLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_ECTRL_EFLT_CTR_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_ECTRL_EFLT_CTR_RE_MASK) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_EFLT_CTR_FE_MASK (0x2000000U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_EFLT_CTR_FE_SHIFT (25U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_EFLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_EFLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_ECTRL_EFLT_CTR_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_ECTRL_EFLT_CTR_FE_MASK) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_SWAP_CAPTURE_MASK (0x10000000U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_SWAP_CAPTURE_SHIFT (28U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_SWAP_CAPTURE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_SWAP_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_ECTRL_SWAP_CAPTURE_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_ECTRL_SWAP_CAPTURE_MASK) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_IMM_START_MASK (0x20000000U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_IMM_START_SHIFT (29U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_IMM_START_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_IMM_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_ECTRL_IMM_START_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_ECTRL_IMM_START_MASK) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_ECLK_SEL_MASK (0x40000000U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_ECLK_SEL_SHIFT (30U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_ECLK_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_ECLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_ECTRL_ECLK_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_ECTRL_ECLK_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_USE_PREV_CH_IN_MASK (0x80000000U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_USE_PREV_CH_IN_SHIFT (31U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_USE_PREV_CH_IN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_ECTRL_USE_PREV_CH_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_ECTRL_USE_PREV_CH_IN_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_ECTRL_USE_PREV_CH_IN_MASK) /*! @} */ /*! @name TIM1_CH4_IRQ_NOTIFY - TIM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_NEWVAL_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_NEWVAL_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_NEWVAL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_NEWVAL_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_NEWVAL_MASK) #define GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_ECNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_ECNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_CNTOFL_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_CNTOFL_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_CNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_CNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_CNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_GPROFL_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_GPROFL_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_GPROFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_GPROFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_GPROFL_MASK) #define GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_TODET_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_TODET_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_TODET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_TODET_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_TODET_MASK) #define GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_GLITCHDET_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_IRQ_NOTIFY_GLITCHDET_MASK) /*! @} */ /*! @name TIM1_CH4_IRQ_EN - TIM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH4_IRQ_EN_NEWVAL_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_EN_NEWVAL_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_EN_NEWVAL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_EN_NEWVAL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_IRQ_EN_NEWVAL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_IRQ_EN_NEWVAL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH4_IRQ_EN_ECNTOFL_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_EN_ECNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_EN_ECNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_IRQ_EN_ECNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH4_IRQ_EN_CNTOFL_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_EN_CNTOFL_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_EN_CNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_EN_CNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_IRQ_EN_CNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_IRQ_EN_CNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH4_IRQ_EN_GPROFL_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_EN_GPROFL_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_EN_GPROFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_EN_GPROFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_IRQ_EN_GPROFL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_IRQ_EN_GPROFL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH4_IRQ_EN_TODET_IRQ_EN_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_EN_TODET_IRQ_EN_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_EN_TODET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_EN_TODET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_IRQ_EN_TODET_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_IRQ_EN_TODET_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH4_IRQ_EN_GLITCHDET_IRQ_EN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_EN_GLITCHDET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_EN_GLITCHDET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_IRQ_EN_GLITCHDET_IRQ_EN_MASK) /*! @} */ /*! @name TIM1_CH4_IRQ_FORCINT - TIM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_NEWVAL_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_NEWVAL_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_NEWVAL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_NEWVAL_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_NEWVAL_MASK) #define GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_ECNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_ECNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_CNTOFL_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_CNTOFL_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_CNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_CNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_CNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_GPROFL_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_GPROFL_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_GPROFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_GPROFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_GPROFL_MASK) #define GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_TODET_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_TODET_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_TODET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_TODET_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_TODET_MASK) #define GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_GLITCHDET_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_IRQ_FORCINT_TRG_GLITCHDET_MASK) /*! @} */ /*! @name TIM1_CH4_IRQ_MODE - TIM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH4_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH4_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TIM1_CH4_EIRQ_EN - TIM[i] channel [x] error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_NEWVAL_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_NEWVAL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_NEWVAL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_NEWVAL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_ECNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_ECNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_CNTOFL_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_CNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_CNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_CNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_GPROFL_EIRQ_EN_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_GPROFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_GPROFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_GPROFL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_TODET_EIRQ_EN_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_TODET_EIRQ_EN_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_TODET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_TODET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_TODET_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_TODET_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_GLITCHDET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_GLITCHDET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH4_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK) /*! @} */ /*! @name TIM1_CH5_GPR0 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH5_GPR0_GPR0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH5_GPR0_GPR0_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH5_GPR0_GPR0_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH5_GPR0_GPR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_GPR0_GPR0_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_GPR0_GPR0_MASK) #define GTM_gtm_cls1_TIM1_CH5_GPR0_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls1_TIM1_CH5_GPR0_ECNT_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH5_GPR0_ECNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH5_GPR0_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_GPR0_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_GPR0_ECNT_MASK) /*! @} */ /*! @name TIM1_CH5_GPR1 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH5_GPR1_GPR1_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH5_GPR1_GPR1_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH5_GPR1_GPR1_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH5_GPR1_GPR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_GPR1_GPR1_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_GPR1_GPR1_MASK) #define GTM_gtm_cls1_TIM1_CH5_GPR1_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls1_TIM1_CH5_GPR1_ECNT_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH5_GPR1_ECNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH5_GPR1_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_GPR1_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_GPR1_ECNT_MASK) /*! @} */ /*! @name TIM1_CH5_CNT - TIM[i] channel [x] SMU counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH5_CNT_CNT_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH5_CNT_CNT_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH5_CNT_CNT_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH5_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_CNT_CNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_CNT_CNT_MASK) /*! @} */ /*! @name TIM1_CH5_ECNT - TIM[i] channel [x] SMU edge counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH5_ECNT_ECNT_MASK (0xFFFFU) #define GTM_gtm_cls1_TIM1_CH5_ECNT_ECNT_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH5_ECNT_ECNT_WIDTH (16U) #define GTM_gtm_cls1_TIM1_CH5_ECNT_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_ECNT_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_ECNT_ECNT_MASK) /*! @} */ /*! @name TIM1_CH5_CNTS - TIM[i] channel [x] SMU shadow counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH5_CNTS_CNTS_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH5_CNTS_CNTS_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH5_CNTS_CNTS_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH5_CNTS_CNTS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_CNTS_CNTS_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_CNTS_CNTS_MASK) #define GTM_gtm_cls1_TIM1_CH5_CNTS_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls1_TIM1_CH5_CNTS_ECNT_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH5_CNTS_ECNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH5_CNTS_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_CNTS_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_CNTS_ECNT_MASK) /*! @} */ /*! @name TIM1_CH5_TDUC - TIM[i] channel [x] TDU counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH5_TDUC_TO_CNT_MASK (0xFFU) #define GTM_gtm_cls1_TIM1_CH5_TDUC_TO_CNT_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH5_TDUC_TO_CNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH5_TDUC_TO_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_TDUC_TO_CNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_TDUC_TO_CNT_MASK) #define GTM_gtm_cls1_TIM1_CH5_TDUC_TO_CNT1_MASK (0xFF00U) #define GTM_gtm_cls1_TIM1_CH5_TDUC_TO_CNT1_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH5_TDUC_TO_CNT1_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH5_TDUC_TO_CNT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_TDUC_TO_CNT1_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_TDUC_TO_CNT1_MASK) #define GTM_gtm_cls1_TIM1_CH5_TDUC_TO_CNT2_MASK (0xFF0000U) #define GTM_gtm_cls1_TIM1_CH5_TDUC_TO_CNT2_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH5_TDUC_TO_CNT2_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH5_TDUC_TO_CNT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_TDUC_TO_CNT2_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_TDUC_TO_CNT2_MASK) /*! @} */ /*! @name TIM1_CH5_TDUV - TIM[i] channel [x] TDU control register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH5_TDUV_TOV_MASK (0xFFU) #define GTM_gtm_cls1_TIM1_CH5_TDUV_TOV_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH5_TDUV_TOV_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH5_TDUV_TOV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_TDUV_TOV_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_TDUV_TOV_MASK) #define GTM_gtm_cls1_TIM1_CH5_TDUV_TOV1_MASK (0xFF00U) #define GTM_gtm_cls1_TIM1_CH5_TDUV_TOV1_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH5_TDUV_TOV1_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH5_TDUV_TOV1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_TDUV_TOV1_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_TDUV_TOV1_MASK) #define GTM_gtm_cls1_TIM1_CH5_TDUV_TOV2_MASK (0xFF0000U) #define GTM_gtm_cls1_TIM1_CH5_TDUV_TOV2_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH5_TDUV_TOV2_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH5_TDUV_TOV2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_TDUV_TOV2_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_TDUV_TOV2_MASK) #define GTM_gtm_cls1_TIM1_CH5_TDUV_SLICING_MASK (0x3000000U) #define GTM_gtm_cls1_TIM1_CH5_TDUV_SLICING_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH5_TDUV_SLICING_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH5_TDUV_SLICING(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_TDUV_SLICING_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_TDUV_SLICING_MASK) #define GTM_gtm_cls1_TIM1_CH5_TDUV_TCS_USE_SAMPLE_EVT_MASK (0x4000000U) #define GTM_gtm_cls1_TIM1_CH5_TDUV_TCS_USE_SAMPLE_EVT_SHIFT (26U) #define GTM_gtm_cls1_TIM1_CH5_TDUV_TCS_USE_SAMPLE_EVT_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_TDUV_TCS_USE_SAMPLE_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_TDUV_TCS_USE_SAMPLE_EVT_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_TDUV_TCS_USE_SAMPLE_EVT_MASK) #define GTM_gtm_cls1_TIM1_CH5_TDUV_TDU_SAME_CNT_CLK_MASK (0x8000000U) #define GTM_gtm_cls1_TIM1_CH5_TDUV_TDU_SAME_CNT_CLK_SHIFT (27U) #define GTM_gtm_cls1_TIM1_CH5_TDUV_TDU_SAME_CNT_CLK_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_TDUV_TDU_SAME_CNT_CLK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_TDUV_TDU_SAME_CNT_CLK_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_TDUV_TDU_SAME_CNT_CLK_MASK) #define GTM_gtm_cls1_TIM1_CH5_TDUV_TCS_MASK (0x70000000U) #define GTM_gtm_cls1_TIM1_CH5_TDUV_TCS_SHIFT (28U) #define GTM_gtm_cls1_TIM1_CH5_TDUV_TCS_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH5_TDUV_TCS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_TDUV_TCS_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_TDUV_TCS_MASK) /*! @} */ /*! @name TIM1_CH5_FLT_RE - TIM[i] channel [x] filter parameter 0 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH5_FLT_RE_FLT_RE_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH5_FLT_RE_FLT_RE_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH5_FLT_RE_FLT_RE_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH5_FLT_RE_FLT_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_FLT_RE_FLT_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_FLT_RE_FLT_RE_MASK) /*! @} */ /*! @name TIM1_CH5_FLT_FE - TIM[i] channel [x] filter parameter 1 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH5_FLT_FE_FLT_FE_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH5_FLT_FE_FLT_FE_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH5_FLT_FE_FLT_FE_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH5_FLT_FE_FLT_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_FLT_FE_FLT_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_FLT_FE_FLT_FE_MASK) /*! @} */ /*! @name TIM1_CH5_CTRL - TIM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH5_CTRL_TIM_EN_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_TIM_EN_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_TIM_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_TIM_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_CTRL_TIM_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_CTRL_TIM_EN_MASK) #define GTM_gtm_cls1_TIM1_CH5_CTRL_TIM_MODE_MASK (0xEU) #define GTM_gtm_cls1_TIM1_CH5_CTRL_TIM_MODE_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_TIM_MODE_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_TIM_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_CTRL_TIM_MODE_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_CTRL_TIM_MODE_MASK) #define GTM_gtm_cls1_TIM1_CH5_CTRL_OSM_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_OSM_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_CTRL_OSM_MASK) #define GTM_gtm_cls1_TIM1_CH5_CTRL_ARU_EN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_ARU_EN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_CTRL_ARU_EN_MASK) #define GTM_gtm_cls1_TIM1_CH5_CTRL_CICTRL_MASK (0x40U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_CICTRL_SHIFT (6U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_CICTRL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_CICTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_CTRL_CICTRL_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_CTRL_CICTRL_MASK) #define GTM_gtm_cls1_TIM1_CH5_CTRL_GPR0_SEL_MASK (0x300U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_GPR0_SEL_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_GPR0_SEL_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_GPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_CTRL_GPR0_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_CTRL_GPR0_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH5_CTRL_GPR1_SEL_MASK (0xC00U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_GPR1_SEL_SHIFT (10U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_GPR1_SEL_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_GPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_CTRL_GPR1_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_CTRL_GPR1_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH5_CTRL_CNTS_SEL_MASK (0x1000U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_CNTS_SEL_SHIFT (12U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_CNTS_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_CNTS_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_CTRL_CNTS_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_CTRL_CNTS_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH5_CTRL_DSL_MASK (0x2000U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_DSL_SHIFT (13U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_DSL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_CTRL_DSL_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_CTRL_DSL_MASK) #define GTM_gtm_cls1_TIM1_CH5_CTRL_ISL_MASK (0x4000U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_ISL_SHIFT (14U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_ISL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_ISL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_CTRL_ISL_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_CTRL_ISL_MASK) #define GTM_gtm_cls1_TIM1_CH5_CTRL_ECNT_RESET_MASK (0x8000U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_ECNT_RESET_SHIFT (15U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_ECNT_RESET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_ECNT_RESET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_CTRL_ECNT_RESET_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_CTRL_ECNT_RESET_MASK) #define GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_EN_MASK (0x10000U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_EN_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_EN_MASK) #define GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_CNT_FRQ_MASK (0x60000U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_CNT_FRQ_SHIFT (17U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_CNT_FRQ_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_CNT_FRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_CNT_FRQ_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_CNT_FRQ_MASK) #define GTM_gtm_cls1_TIM1_CH5_CTRL_EXT_CAP_EN_MASK (0x80000U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_EXT_CAP_EN_SHIFT (19U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_EXT_CAP_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_EXT_CAP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_CTRL_EXT_CAP_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_CTRL_EXT_CAP_EN_MASK) #define GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_MODE_RE_MASK (0x100000U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_MODE_RE_SHIFT (20U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_MODE_RE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_MODE_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_MODE_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_MODE_RE_MASK) #define GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_CTR_RE_MASK (0x200000U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_CTR_RE_SHIFT (21U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_CTR_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_CTR_RE_MASK) #define GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_MODE_FE_MASK (0x400000U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_MODE_FE_SHIFT (22U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_MODE_FE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_MODE_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_MODE_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_MODE_FE_MASK) #define GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_CTR_FE_MASK (0x800000U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_CTR_FE_SHIFT (23U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_CTR_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_CTRL_FLT_CTR_FE_MASK) #define GTM_gtm_cls1_TIM1_CH5_CTRL_CLK_SEL_MASK (0x7000000U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_CLK_SEL_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_CLK_SEL_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_CTRL_CLK_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_CTRL_CLK_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH5_CTRL_FR_ECNT_OFL_MASK (0x8000000U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_FR_ECNT_OFL_SHIFT (27U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_FR_ECNT_OFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_FR_ECNT_OFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_CTRL_FR_ECNT_OFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_CTRL_FR_ECNT_OFL_MASK) #define GTM_gtm_cls1_TIM1_CH5_CTRL_EGPR0_SEL_MASK (0x10000000U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_EGPR0_SEL_SHIFT (28U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_EGPR0_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_EGPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_CTRL_EGPR0_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_CTRL_EGPR0_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH5_CTRL_EGPR1_SEL_MASK (0x20000000U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_EGPR1_SEL_SHIFT (29U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_EGPR1_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_EGPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_CTRL_EGPR1_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_CTRL_EGPR1_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH5_CTRL_TOCTRL_MASK (0xC0000000U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_TOCTRL_SHIFT (30U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_TOCTRL_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH5_CTRL_TOCTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_CTRL_TOCTRL_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_CTRL_TOCTRL_MASK) /*! @} */ /*! @name TIM1_CH5_ECTRL - TIM[i] channel [x] extended control register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH5_ECTRL_EXT_CAP_SRC_MASK (0xFU) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_EXT_CAP_SRC_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_EXT_CAP_SRC_WIDTH (4U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_EXT_CAP_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_ECTRL_EXT_CAP_SRC_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_ECTRL_EXT_CAP_SRC_MASK) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_USE_PREV_TDU_IN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_USE_PREV_TDU_IN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_USE_PREV_TDU_IN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_USE_PREV_TDU_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_ECTRL_USE_PREV_TDU_IN_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_ECTRL_USE_PREV_TDU_IN_MASK) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_TODET_IRQ_SRC_MASK (0xC0U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_TODET_IRQ_SRC_SHIFT (6U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_TODET_IRQ_SRC_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_TODET_IRQ_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_ECTRL_TODET_IRQ_SRC_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_ECTRL_TODET_IRQ_SRC_MASK) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_TDU_START_MASK (0x700U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_TDU_START_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_TDU_START_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_TDU_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_ECTRL_TDU_START_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_ECTRL_TDU_START_MASK) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_TDU_STOP_MASK (0x7000U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_TDU_STOP_SHIFT (12U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_TDU_STOP_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_TDU_STOP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_ECTRL_TDU_STOP_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_ECTRL_TDU_STOP_MASK) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_TDU_RESYNC_MASK (0xF0000U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_TDU_RESYNC_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_TDU_RESYNC_WIDTH (4U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_TDU_RESYNC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_ECTRL_TDU_RESYNC_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_ECTRL_TDU_RESYNC_MASK) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_USE_LUT_MASK (0xC00000U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_USE_LUT_SHIFT (22U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_USE_LUT_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_USE_LUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_ECTRL_USE_LUT_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_ECTRL_USE_LUT_MASK) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_EFLT_CTR_RE_MASK (0x1000000U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_EFLT_CTR_RE_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_EFLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_EFLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_ECTRL_EFLT_CTR_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_ECTRL_EFLT_CTR_RE_MASK) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_EFLT_CTR_FE_MASK (0x2000000U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_EFLT_CTR_FE_SHIFT (25U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_EFLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_EFLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_ECTRL_EFLT_CTR_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_ECTRL_EFLT_CTR_FE_MASK) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_SWAP_CAPTURE_MASK (0x10000000U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_SWAP_CAPTURE_SHIFT (28U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_SWAP_CAPTURE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_SWAP_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_ECTRL_SWAP_CAPTURE_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_ECTRL_SWAP_CAPTURE_MASK) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_IMM_START_MASK (0x20000000U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_IMM_START_SHIFT (29U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_IMM_START_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_IMM_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_ECTRL_IMM_START_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_ECTRL_IMM_START_MASK) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_ECLK_SEL_MASK (0x40000000U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_ECLK_SEL_SHIFT (30U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_ECLK_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_ECLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_ECTRL_ECLK_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_ECTRL_ECLK_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_USE_PREV_CH_IN_MASK (0x80000000U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_USE_PREV_CH_IN_SHIFT (31U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_USE_PREV_CH_IN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_ECTRL_USE_PREV_CH_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_ECTRL_USE_PREV_CH_IN_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_ECTRL_USE_PREV_CH_IN_MASK) /*! @} */ /*! @name TIM1_CH5_IRQ_NOTIFY - TIM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_NEWVAL_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_NEWVAL_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_NEWVAL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_NEWVAL_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_NEWVAL_MASK) #define GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_ECNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_ECNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_CNTOFL_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_CNTOFL_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_CNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_CNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_CNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_GPROFL_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_GPROFL_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_GPROFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_GPROFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_GPROFL_MASK) #define GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_TODET_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_TODET_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_TODET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_TODET_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_TODET_MASK) #define GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_GLITCHDET_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_IRQ_NOTIFY_GLITCHDET_MASK) /*! @} */ /*! @name TIM1_CH5_IRQ_EN - TIM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH5_IRQ_EN_NEWVAL_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_EN_NEWVAL_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_EN_NEWVAL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_EN_NEWVAL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_IRQ_EN_NEWVAL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_IRQ_EN_NEWVAL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH5_IRQ_EN_ECNTOFL_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_EN_ECNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_EN_ECNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_IRQ_EN_ECNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH5_IRQ_EN_CNTOFL_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_EN_CNTOFL_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_EN_CNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_EN_CNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_IRQ_EN_CNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_IRQ_EN_CNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH5_IRQ_EN_GPROFL_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_EN_GPROFL_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_EN_GPROFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_EN_GPROFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_IRQ_EN_GPROFL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_IRQ_EN_GPROFL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH5_IRQ_EN_TODET_IRQ_EN_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_EN_TODET_IRQ_EN_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_EN_TODET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_EN_TODET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_IRQ_EN_TODET_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_IRQ_EN_TODET_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH5_IRQ_EN_GLITCHDET_IRQ_EN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_EN_GLITCHDET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_EN_GLITCHDET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_IRQ_EN_GLITCHDET_IRQ_EN_MASK) /*! @} */ /*! @name TIM1_CH5_IRQ_FORCINT - TIM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_NEWVAL_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_NEWVAL_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_NEWVAL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_NEWVAL_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_NEWVAL_MASK) #define GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_ECNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_ECNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_CNTOFL_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_CNTOFL_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_CNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_CNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_CNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_GPROFL_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_GPROFL_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_GPROFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_GPROFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_GPROFL_MASK) #define GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_TODET_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_TODET_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_TODET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_TODET_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_TODET_MASK) #define GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_GLITCHDET_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_IRQ_FORCINT_TRG_GLITCHDET_MASK) /*! @} */ /*! @name TIM1_CH5_IRQ_MODE - TIM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH5_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH5_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TIM1_CH5_EIRQ_EN - TIM[i] channel [x] error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_NEWVAL_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_NEWVAL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_NEWVAL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_NEWVAL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_ECNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_ECNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_CNTOFL_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_CNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_CNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_CNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_GPROFL_EIRQ_EN_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_GPROFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_GPROFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_GPROFL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_TODET_EIRQ_EN_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_TODET_EIRQ_EN_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_TODET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_TODET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_TODET_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_TODET_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_GLITCHDET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_GLITCHDET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH5_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK) /*! @} */ /*! @name TIM1_CH6_GPR0 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH6_GPR0_GPR0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH6_GPR0_GPR0_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH6_GPR0_GPR0_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH6_GPR0_GPR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_GPR0_GPR0_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_GPR0_GPR0_MASK) #define GTM_gtm_cls1_TIM1_CH6_GPR0_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls1_TIM1_CH6_GPR0_ECNT_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH6_GPR0_ECNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH6_GPR0_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_GPR0_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_GPR0_ECNT_MASK) /*! @} */ /*! @name TIM1_CH6_GPR1 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH6_GPR1_GPR1_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH6_GPR1_GPR1_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH6_GPR1_GPR1_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH6_GPR1_GPR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_GPR1_GPR1_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_GPR1_GPR1_MASK) #define GTM_gtm_cls1_TIM1_CH6_GPR1_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls1_TIM1_CH6_GPR1_ECNT_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH6_GPR1_ECNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH6_GPR1_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_GPR1_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_GPR1_ECNT_MASK) /*! @} */ /*! @name TIM1_CH6_CNT - TIM[i] channel [x] SMU counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH6_CNT_CNT_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH6_CNT_CNT_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH6_CNT_CNT_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH6_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_CNT_CNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_CNT_CNT_MASK) /*! @} */ /*! @name TIM1_CH6_ECNT - TIM[i] channel [x] SMU edge counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH6_ECNT_ECNT_MASK (0xFFFFU) #define GTM_gtm_cls1_TIM1_CH6_ECNT_ECNT_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH6_ECNT_ECNT_WIDTH (16U) #define GTM_gtm_cls1_TIM1_CH6_ECNT_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_ECNT_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_ECNT_ECNT_MASK) /*! @} */ /*! @name TIM1_CH6_CNTS - TIM[i] channel [x] SMU shadow counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH6_CNTS_CNTS_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH6_CNTS_CNTS_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH6_CNTS_CNTS_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH6_CNTS_CNTS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_CNTS_CNTS_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_CNTS_CNTS_MASK) #define GTM_gtm_cls1_TIM1_CH6_CNTS_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls1_TIM1_CH6_CNTS_ECNT_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH6_CNTS_ECNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH6_CNTS_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_CNTS_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_CNTS_ECNT_MASK) /*! @} */ /*! @name TIM1_CH6_TDUC - TIM[i] channel [x] TDU counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH6_TDUC_TO_CNT_MASK (0xFFU) #define GTM_gtm_cls1_TIM1_CH6_TDUC_TO_CNT_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH6_TDUC_TO_CNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH6_TDUC_TO_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_TDUC_TO_CNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_TDUC_TO_CNT_MASK) #define GTM_gtm_cls1_TIM1_CH6_TDUC_TO_CNT1_MASK (0xFF00U) #define GTM_gtm_cls1_TIM1_CH6_TDUC_TO_CNT1_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH6_TDUC_TO_CNT1_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH6_TDUC_TO_CNT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_TDUC_TO_CNT1_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_TDUC_TO_CNT1_MASK) #define GTM_gtm_cls1_TIM1_CH6_TDUC_TO_CNT2_MASK (0xFF0000U) #define GTM_gtm_cls1_TIM1_CH6_TDUC_TO_CNT2_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH6_TDUC_TO_CNT2_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH6_TDUC_TO_CNT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_TDUC_TO_CNT2_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_TDUC_TO_CNT2_MASK) /*! @} */ /*! @name TIM1_CH6_TDUV - TIM[i] channel [x] TDU control register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH6_TDUV_TOV_MASK (0xFFU) #define GTM_gtm_cls1_TIM1_CH6_TDUV_TOV_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH6_TDUV_TOV_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH6_TDUV_TOV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_TDUV_TOV_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_TDUV_TOV_MASK) #define GTM_gtm_cls1_TIM1_CH6_TDUV_TOV1_MASK (0xFF00U) #define GTM_gtm_cls1_TIM1_CH6_TDUV_TOV1_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH6_TDUV_TOV1_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH6_TDUV_TOV1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_TDUV_TOV1_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_TDUV_TOV1_MASK) #define GTM_gtm_cls1_TIM1_CH6_TDUV_TOV2_MASK (0xFF0000U) #define GTM_gtm_cls1_TIM1_CH6_TDUV_TOV2_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH6_TDUV_TOV2_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH6_TDUV_TOV2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_TDUV_TOV2_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_TDUV_TOV2_MASK) #define GTM_gtm_cls1_TIM1_CH6_TDUV_SLICING_MASK (0x3000000U) #define GTM_gtm_cls1_TIM1_CH6_TDUV_SLICING_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH6_TDUV_SLICING_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH6_TDUV_SLICING(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_TDUV_SLICING_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_TDUV_SLICING_MASK) #define GTM_gtm_cls1_TIM1_CH6_TDUV_TCS_USE_SAMPLE_EVT_MASK (0x4000000U) #define GTM_gtm_cls1_TIM1_CH6_TDUV_TCS_USE_SAMPLE_EVT_SHIFT (26U) #define GTM_gtm_cls1_TIM1_CH6_TDUV_TCS_USE_SAMPLE_EVT_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_TDUV_TCS_USE_SAMPLE_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_TDUV_TCS_USE_SAMPLE_EVT_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_TDUV_TCS_USE_SAMPLE_EVT_MASK) #define GTM_gtm_cls1_TIM1_CH6_TDUV_TDU_SAME_CNT_CLK_MASK (0x8000000U) #define GTM_gtm_cls1_TIM1_CH6_TDUV_TDU_SAME_CNT_CLK_SHIFT (27U) #define GTM_gtm_cls1_TIM1_CH6_TDUV_TDU_SAME_CNT_CLK_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_TDUV_TDU_SAME_CNT_CLK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_TDUV_TDU_SAME_CNT_CLK_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_TDUV_TDU_SAME_CNT_CLK_MASK) #define GTM_gtm_cls1_TIM1_CH6_TDUV_TCS_MASK (0x70000000U) #define GTM_gtm_cls1_TIM1_CH6_TDUV_TCS_SHIFT (28U) #define GTM_gtm_cls1_TIM1_CH6_TDUV_TCS_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH6_TDUV_TCS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_TDUV_TCS_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_TDUV_TCS_MASK) /*! @} */ /*! @name TIM1_CH6_FLT_RE - TIM[i] channel [x] filter parameter 0 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH6_FLT_RE_FLT_RE_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH6_FLT_RE_FLT_RE_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH6_FLT_RE_FLT_RE_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH6_FLT_RE_FLT_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_FLT_RE_FLT_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_FLT_RE_FLT_RE_MASK) /*! @} */ /*! @name TIM1_CH6_FLT_FE - TIM[i] channel [x] filter parameter 1 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH6_FLT_FE_FLT_FE_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH6_FLT_FE_FLT_FE_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH6_FLT_FE_FLT_FE_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH6_FLT_FE_FLT_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_FLT_FE_FLT_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_FLT_FE_FLT_FE_MASK) /*! @} */ /*! @name TIM1_CH6_CTRL - TIM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH6_CTRL_TIM_EN_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_TIM_EN_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_TIM_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_TIM_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_CTRL_TIM_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_CTRL_TIM_EN_MASK) #define GTM_gtm_cls1_TIM1_CH6_CTRL_TIM_MODE_MASK (0xEU) #define GTM_gtm_cls1_TIM1_CH6_CTRL_TIM_MODE_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_TIM_MODE_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_TIM_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_CTRL_TIM_MODE_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_CTRL_TIM_MODE_MASK) #define GTM_gtm_cls1_TIM1_CH6_CTRL_OSM_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_OSM_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_CTRL_OSM_MASK) #define GTM_gtm_cls1_TIM1_CH6_CTRL_ARU_EN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_ARU_EN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_CTRL_ARU_EN_MASK) #define GTM_gtm_cls1_TIM1_CH6_CTRL_CICTRL_MASK (0x40U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_CICTRL_SHIFT (6U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_CICTRL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_CICTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_CTRL_CICTRL_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_CTRL_CICTRL_MASK) #define GTM_gtm_cls1_TIM1_CH6_CTRL_GPR0_SEL_MASK (0x300U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_GPR0_SEL_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_GPR0_SEL_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_GPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_CTRL_GPR0_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_CTRL_GPR0_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH6_CTRL_GPR1_SEL_MASK (0xC00U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_GPR1_SEL_SHIFT (10U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_GPR1_SEL_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_GPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_CTRL_GPR1_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_CTRL_GPR1_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH6_CTRL_CNTS_SEL_MASK (0x1000U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_CNTS_SEL_SHIFT (12U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_CNTS_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_CNTS_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_CTRL_CNTS_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_CTRL_CNTS_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH6_CTRL_DSL_MASK (0x2000U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_DSL_SHIFT (13U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_DSL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_CTRL_DSL_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_CTRL_DSL_MASK) #define GTM_gtm_cls1_TIM1_CH6_CTRL_ISL_MASK (0x4000U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_ISL_SHIFT (14U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_ISL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_ISL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_CTRL_ISL_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_CTRL_ISL_MASK) #define GTM_gtm_cls1_TIM1_CH6_CTRL_ECNT_RESET_MASK (0x8000U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_ECNT_RESET_SHIFT (15U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_ECNT_RESET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_ECNT_RESET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_CTRL_ECNT_RESET_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_CTRL_ECNT_RESET_MASK) #define GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_EN_MASK (0x10000U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_EN_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_EN_MASK) #define GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_CNT_FRQ_MASK (0x60000U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_CNT_FRQ_SHIFT (17U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_CNT_FRQ_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_CNT_FRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_CNT_FRQ_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_CNT_FRQ_MASK) #define GTM_gtm_cls1_TIM1_CH6_CTRL_EXT_CAP_EN_MASK (0x80000U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_EXT_CAP_EN_SHIFT (19U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_EXT_CAP_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_EXT_CAP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_CTRL_EXT_CAP_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_CTRL_EXT_CAP_EN_MASK) #define GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_MODE_RE_MASK (0x100000U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_MODE_RE_SHIFT (20U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_MODE_RE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_MODE_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_MODE_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_MODE_RE_MASK) #define GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_CTR_RE_MASK (0x200000U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_CTR_RE_SHIFT (21U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_CTR_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_CTR_RE_MASK) #define GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_MODE_FE_MASK (0x400000U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_MODE_FE_SHIFT (22U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_MODE_FE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_MODE_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_MODE_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_MODE_FE_MASK) #define GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_CTR_FE_MASK (0x800000U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_CTR_FE_SHIFT (23U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_CTR_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_CTRL_FLT_CTR_FE_MASK) #define GTM_gtm_cls1_TIM1_CH6_CTRL_CLK_SEL_MASK (0x7000000U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_CLK_SEL_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_CLK_SEL_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_CTRL_CLK_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_CTRL_CLK_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH6_CTRL_FR_ECNT_OFL_MASK (0x8000000U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_FR_ECNT_OFL_SHIFT (27U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_FR_ECNT_OFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_FR_ECNT_OFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_CTRL_FR_ECNT_OFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_CTRL_FR_ECNT_OFL_MASK) #define GTM_gtm_cls1_TIM1_CH6_CTRL_EGPR0_SEL_MASK (0x10000000U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_EGPR0_SEL_SHIFT (28U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_EGPR0_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_EGPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_CTRL_EGPR0_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_CTRL_EGPR0_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH6_CTRL_EGPR1_SEL_MASK (0x20000000U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_EGPR1_SEL_SHIFT (29U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_EGPR1_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_EGPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_CTRL_EGPR1_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_CTRL_EGPR1_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH6_CTRL_TOCTRL_MASK (0xC0000000U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_TOCTRL_SHIFT (30U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_TOCTRL_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH6_CTRL_TOCTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_CTRL_TOCTRL_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_CTRL_TOCTRL_MASK) /*! @} */ /*! @name TIM1_CH6_ECTRL - TIM[i] channel [x] extended control register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH6_ECTRL_EXT_CAP_SRC_MASK (0xFU) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_EXT_CAP_SRC_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_EXT_CAP_SRC_WIDTH (4U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_EXT_CAP_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_ECTRL_EXT_CAP_SRC_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_ECTRL_EXT_CAP_SRC_MASK) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_USE_PREV_TDU_IN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_USE_PREV_TDU_IN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_USE_PREV_TDU_IN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_USE_PREV_TDU_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_ECTRL_USE_PREV_TDU_IN_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_ECTRL_USE_PREV_TDU_IN_MASK) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_TODET_IRQ_SRC_MASK (0xC0U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_TODET_IRQ_SRC_SHIFT (6U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_TODET_IRQ_SRC_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_TODET_IRQ_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_ECTRL_TODET_IRQ_SRC_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_ECTRL_TODET_IRQ_SRC_MASK) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_TDU_START_MASK (0x700U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_TDU_START_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_TDU_START_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_TDU_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_ECTRL_TDU_START_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_ECTRL_TDU_START_MASK) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_TDU_STOP_MASK (0x7000U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_TDU_STOP_SHIFT (12U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_TDU_STOP_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_TDU_STOP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_ECTRL_TDU_STOP_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_ECTRL_TDU_STOP_MASK) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_TDU_RESYNC_MASK (0xF0000U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_TDU_RESYNC_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_TDU_RESYNC_WIDTH (4U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_TDU_RESYNC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_ECTRL_TDU_RESYNC_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_ECTRL_TDU_RESYNC_MASK) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_USE_LUT_MASK (0xC00000U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_USE_LUT_SHIFT (22U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_USE_LUT_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_USE_LUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_ECTRL_USE_LUT_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_ECTRL_USE_LUT_MASK) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_EFLT_CTR_RE_MASK (0x1000000U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_EFLT_CTR_RE_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_EFLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_EFLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_ECTRL_EFLT_CTR_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_ECTRL_EFLT_CTR_RE_MASK) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_EFLT_CTR_FE_MASK (0x2000000U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_EFLT_CTR_FE_SHIFT (25U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_EFLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_EFLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_ECTRL_EFLT_CTR_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_ECTRL_EFLT_CTR_FE_MASK) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_SWAP_CAPTURE_MASK (0x10000000U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_SWAP_CAPTURE_SHIFT (28U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_SWAP_CAPTURE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_SWAP_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_ECTRL_SWAP_CAPTURE_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_ECTRL_SWAP_CAPTURE_MASK) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_IMM_START_MASK (0x20000000U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_IMM_START_SHIFT (29U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_IMM_START_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_IMM_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_ECTRL_IMM_START_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_ECTRL_IMM_START_MASK) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_ECLK_SEL_MASK (0x40000000U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_ECLK_SEL_SHIFT (30U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_ECLK_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_ECLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_ECTRL_ECLK_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_ECTRL_ECLK_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_USE_PREV_CH_IN_MASK (0x80000000U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_USE_PREV_CH_IN_SHIFT (31U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_USE_PREV_CH_IN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_ECTRL_USE_PREV_CH_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_ECTRL_USE_PREV_CH_IN_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_ECTRL_USE_PREV_CH_IN_MASK) /*! @} */ /*! @name TIM1_CH6_IRQ_NOTIFY - TIM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_NEWVAL_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_NEWVAL_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_NEWVAL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_NEWVAL_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_NEWVAL_MASK) #define GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_ECNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_ECNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_CNTOFL_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_CNTOFL_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_CNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_CNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_CNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_GPROFL_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_GPROFL_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_GPROFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_GPROFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_GPROFL_MASK) #define GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_TODET_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_TODET_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_TODET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_TODET_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_TODET_MASK) #define GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_GLITCHDET_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_IRQ_NOTIFY_GLITCHDET_MASK) /*! @} */ /*! @name TIM1_CH6_IRQ_EN - TIM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH6_IRQ_EN_NEWVAL_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_EN_NEWVAL_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_EN_NEWVAL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_EN_NEWVAL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_IRQ_EN_NEWVAL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_IRQ_EN_NEWVAL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH6_IRQ_EN_ECNTOFL_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_EN_ECNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_EN_ECNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_IRQ_EN_ECNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH6_IRQ_EN_CNTOFL_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_EN_CNTOFL_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_EN_CNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_EN_CNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_IRQ_EN_CNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_IRQ_EN_CNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH6_IRQ_EN_GPROFL_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_EN_GPROFL_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_EN_GPROFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_EN_GPROFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_IRQ_EN_GPROFL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_IRQ_EN_GPROFL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH6_IRQ_EN_TODET_IRQ_EN_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_EN_TODET_IRQ_EN_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_EN_TODET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_EN_TODET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_IRQ_EN_TODET_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_IRQ_EN_TODET_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH6_IRQ_EN_GLITCHDET_IRQ_EN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_EN_GLITCHDET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_EN_GLITCHDET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_IRQ_EN_GLITCHDET_IRQ_EN_MASK) /*! @} */ /*! @name TIM1_CH6_IRQ_FORCINT - TIM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_NEWVAL_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_NEWVAL_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_NEWVAL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_NEWVAL_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_NEWVAL_MASK) #define GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_ECNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_ECNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_CNTOFL_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_CNTOFL_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_CNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_CNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_CNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_GPROFL_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_GPROFL_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_GPROFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_GPROFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_GPROFL_MASK) #define GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_TODET_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_TODET_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_TODET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_TODET_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_TODET_MASK) #define GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_GLITCHDET_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_IRQ_FORCINT_TRG_GLITCHDET_MASK) /*! @} */ /*! @name TIM1_CH6_IRQ_MODE - TIM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH6_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH6_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TIM1_CH6_EIRQ_EN - TIM[i] channel [x] error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_NEWVAL_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_NEWVAL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_NEWVAL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_NEWVAL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_ECNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_ECNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_CNTOFL_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_CNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_CNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_CNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_GPROFL_EIRQ_EN_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_GPROFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_GPROFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_GPROFL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_TODET_EIRQ_EN_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_TODET_EIRQ_EN_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_TODET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_TODET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_TODET_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_TODET_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_GLITCHDET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_GLITCHDET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH6_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK) /*! @} */ /*! @name TIM1_CH7_GPR0 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH7_GPR0_GPR0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH7_GPR0_GPR0_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH7_GPR0_GPR0_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH7_GPR0_GPR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_GPR0_GPR0_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_GPR0_GPR0_MASK) #define GTM_gtm_cls1_TIM1_CH7_GPR0_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls1_TIM1_CH7_GPR0_ECNT_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH7_GPR0_ECNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH7_GPR0_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_GPR0_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_GPR0_ECNT_MASK) /*! @} */ /*! @name TIM1_CH7_GPR1 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH7_GPR1_GPR1_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH7_GPR1_GPR1_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH7_GPR1_GPR1_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH7_GPR1_GPR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_GPR1_GPR1_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_GPR1_GPR1_MASK) #define GTM_gtm_cls1_TIM1_CH7_GPR1_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls1_TIM1_CH7_GPR1_ECNT_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH7_GPR1_ECNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH7_GPR1_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_GPR1_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_GPR1_ECNT_MASK) /*! @} */ /*! @name TIM1_CH7_CNT - TIM[i] channel [x] SMU counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH7_CNT_CNT_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH7_CNT_CNT_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH7_CNT_CNT_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH7_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_CNT_CNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_CNT_CNT_MASK) /*! @} */ /*! @name TIM1_CH7_ECNT - TIM[i] channel [x] SMU edge counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH7_ECNT_ECNT_MASK (0xFFFFU) #define GTM_gtm_cls1_TIM1_CH7_ECNT_ECNT_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH7_ECNT_ECNT_WIDTH (16U) #define GTM_gtm_cls1_TIM1_CH7_ECNT_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_ECNT_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_ECNT_ECNT_MASK) /*! @} */ /*! @name TIM1_CH7_CNTS - TIM[i] channel [x] SMU shadow counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH7_CNTS_CNTS_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH7_CNTS_CNTS_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH7_CNTS_CNTS_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH7_CNTS_CNTS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_CNTS_CNTS_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_CNTS_CNTS_MASK) #define GTM_gtm_cls1_TIM1_CH7_CNTS_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls1_TIM1_CH7_CNTS_ECNT_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH7_CNTS_ECNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH7_CNTS_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_CNTS_ECNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_CNTS_ECNT_MASK) /*! @} */ /*! @name TIM1_CH7_TDUC - TIM[i] channel [x] TDU counter register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH7_TDUC_TO_CNT_MASK (0xFFU) #define GTM_gtm_cls1_TIM1_CH7_TDUC_TO_CNT_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH7_TDUC_TO_CNT_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH7_TDUC_TO_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_TDUC_TO_CNT_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_TDUC_TO_CNT_MASK) #define GTM_gtm_cls1_TIM1_CH7_TDUC_TO_CNT1_MASK (0xFF00U) #define GTM_gtm_cls1_TIM1_CH7_TDUC_TO_CNT1_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH7_TDUC_TO_CNT1_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH7_TDUC_TO_CNT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_TDUC_TO_CNT1_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_TDUC_TO_CNT1_MASK) #define GTM_gtm_cls1_TIM1_CH7_TDUC_TO_CNT2_MASK (0xFF0000U) #define GTM_gtm_cls1_TIM1_CH7_TDUC_TO_CNT2_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH7_TDUC_TO_CNT2_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH7_TDUC_TO_CNT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_TDUC_TO_CNT2_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_TDUC_TO_CNT2_MASK) /*! @} */ /*! @name TIM1_CH7_TDUV - TIM[i] channel [x] TDU control register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH7_TDUV_TOV_MASK (0xFFU) #define GTM_gtm_cls1_TIM1_CH7_TDUV_TOV_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH7_TDUV_TOV_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH7_TDUV_TOV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_TDUV_TOV_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_TDUV_TOV_MASK) #define GTM_gtm_cls1_TIM1_CH7_TDUV_TOV1_MASK (0xFF00U) #define GTM_gtm_cls1_TIM1_CH7_TDUV_TOV1_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH7_TDUV_TOV1_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH7_TDUV_TOV1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_TDUV_TOV1_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_TDUV_TOV1_MASK) #define GTM_gtm_cls1_TIM1_CH7_TDUV_TOV2_MASK (0xFF0000U) #define GTM_gtm_cls1_TIM1_CH7_TDUV_TOV2_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH7_TDUV_TOV2_WIDTH (8U) #define GTM_gtm_cls1_TIM1_CH7_TDUV_TOV2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_TDUV_TOV2_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_TDUV_TOV2_MASK) #define GTM_gtm_cls1_TIM1_CH7_TDUV_SLICING_MASK (0x3000000U) #define GTM_gtm_cls1_TIM1_CH7_TDUV_SLICING_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH7_TDUV_SLICING_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH7_TDUV_SLICING(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_TDUV_SLICING_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_TDUV_SLICING_MASK) #define GTM_gtm_cls1_TIM1_CH7_TDUV_TCS_USE_SAMPLE_EVT_MASK (0x4000000U) #define GTM_gtm_cls1_TIM1_CH7_TDUV_TCS_USE_SAMPLE_EVT_SHIFT (26U) #define GTM_gtm_cls1_TIM1_CH7_TDUV_TCS_USE_SAMPLE_EVT_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_TDUV_TCS_USE_SAMPLE_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_TDUV_TCS_USE_SAMPLE_EVT_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_TDUV_TCS_USE_SAMPLE_EVT_MASK) #define GTM_gtm_cls1_TIM1_CH7_TDUV_TDU_SAME_CNT_CLK_MASK (0x8000000U) #define GTM_gtm_cls1_TIM1_CH7_TDUV_TDU_SAME_CNT_CLK_SHIFT (27U) #define GTM_gtm_cls1_TIM1_CH7_TDUV_TDU_SAME_CNT_CLK_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_TDUV_TDU_SAME_CNT_CLK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_TDUV_TDU_SAME_CNT_CLK_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_TDUV_TDU_SAME_CNT_CLK_MASK) #define GTM_gtm_cls1_TIM1_CH7_TDUV_TCS_MASK (0x70000000U) #define GTM_gtm_cls1_TIM1_CH7_TDUV_TCS_SHIFT (28U) #define GTM_gtm_cls1_TIM1_CH7_TDUV_TCS_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH7_TDUV_TCS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_TDUV_TCS_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_TDUV_TCS_MASK) /*! @} */ /*! @name TIM1_CH7_FLT_RE - TIM[i] channel [x] filter parameter 0 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH7_FLT_RE_FLT_RE_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH7_FLT_RE_FLT_RE_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH7_FLT_RE_FLT_RE_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH7_FLT_RE_FLT_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_FLT_RE_FLT_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_FLT_RE_FLT_RE_MASK) /*! @} */ /*! @name TIM1_CH7_FLT_FE - TIM[i] channel [x] filter parameter 1 register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH7_FLT_FE_FLT_FE_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIM1_CH7_FLT_FE_FLT_FE_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH7_FLT_FE_FLT_FE_WIDTH (24U) #define GTM_gtm_cls1_TIM1_CH7_FLT_FE_FLT_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_FLT_FE_FLT_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_FLT_FE_FLT_FE_MASK) /*! @} */ /*! @name TIM1_CH7_CTRL - TIM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH7_CTRL_TIM_EN_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_TIM_EN_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_TIM_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_TIM_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_CTRL_TIM_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_CTRL_TIM_EN_MASK) #define GTM_gtm_cls1_TIM1_CH7_CTRL_TIM_MODE_MASK (0xEU) #define GTM_gtm_cls1_TIM1_CH7_CTRL_TIM_MODE_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_TIM_MODE_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_TIM_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_CTRL_TIM_MODE_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_CTRL_TIM_MODE_MASK) #define GTM_gtm_cls1_TIM1_CH7_CTRL_OSM_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_OSM_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_CTRL_OSM_MASK) #define GTM_gtm_cls1_TIM1_CH7_CTRL_ARU_EN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_ARU_EN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_CTRL_ARU_EN_MASK) #define GTM_gtm_cls1_TIM1_CH7_CTRL_CICTRL_MASK (0x40U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_CICTRL_SHIFT (6U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_CICTRL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_CICTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_CTRL_CICTRL_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_CTRL_CICTRL_MASK) #define GTM_gtm_cls1_TIM1_CH7_CTRL_GPR0_SEL_MASK (0x300U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_GPR0_SEL_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_GPR0_SEL_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_GPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_CTRL_GPR0_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_CTRL_GPR0_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH7_CTRL_GPR1_SEL_MASK (0xC00U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_GPR1_SEL_SHIFT (10U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_GPR1_SEL_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_GPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_CTRL_GPR1_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_CTRL_GPR1_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH7_CTRL_CNTS_SEL_MASK (0x1000U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_CNTS_SEL_SHIFT (12U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_CNTS_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_CNTS_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_CTRL_CNTS_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_CTRL_CNTS_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH7_CTRL_DSL_MASK (0x2000U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_DSL_SHIFT (13U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_DSL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_CTRL_DSL_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_CTRL_DSL_MASK) #define GTM_gtm_cls1_TIM1_CH7_CTRL_ISL_MASK (0x4000U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_ISL_SHIFT (14U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_ISL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_ISL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_CTRL_ISL_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_CTRL_ISL_MASK) #define GTM_gtm_cls1_TIM1_CH7_CTRL_ECNT_RESET_MASK (0x8000U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_ECNT_RESET_SHIFT (15U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_ECNT_RESET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_ECNT_RESET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_CTRL_ECNT_RESET_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_CTRL_ECNT_RESET_MASK) #define GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_EN_MASK (0x10000U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_EN_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_EN_MASK) #define GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_CNT_FRQ_MASK (0x60000U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_CNT_FRQ_SHIFT (17U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_CNT_FRQ_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_CNT_FRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_CNT_FRQ_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_CNT_FRQ_MASK) #define GTM_gtm_cls1_TIM1_CH7_CTRL_EXT_CAP_EN_MASK (0x80000U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_EXT_CAP_EN_SHIFT (19U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_EXT_CAP_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_EXT_CAP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_CTRL_EXT_CAP_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_CTRL_EXT_CAP_EN_MASK) #define GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_MODE_RE_MASK (0x100000U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_MODE_RE_SHIFT (20U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_MODE_RE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_MODE_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_MODE_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_MODE_RE_MASK) #define GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_CTR_RE_MASK (0x200000U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_CTR_RE_SHIFT (21U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_CTR_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_CTR_RE_MASK) #define GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_MODE_FE_MASK (0x400000U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_MODE_FE_SHIFT (22U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_MODE_FE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_MODE_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_MODE_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_MODE_FE_MASK) #define GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_CTR_FE_MASK (0x800000U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_CTR_FE_SHIFT (23U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_CTR_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_CTRL_FLT_CTR_FE_MASK) #define GTM_gtm_cls1_TIM1_CH7_CTRL_CLK_SEL_MASK (0x7000000U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_CLK_SEL_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_CLK_SEL_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_CTRL_CLK_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_CTRL_CLK_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH7_CTRL_FR_ECNT_OFL_MASK (0x8000000U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_FR_ECNT_OFL_SHIFT (27U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_FR_ECNT_OFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_FR_ECNT_OFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_CTRL_FR_ECNT_OFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_CTRL_FR_ECNT_OFL_MASK) #define GTM_gtm_cls1_TIM1_CH7_CTRL_EGPR0_SEL_MASK (0x10000000U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_EGPR0_SEL_SHIFT (28U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_EGPR0_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_EGPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_CTRL_EGPR0_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_CTRL_EGPR0_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH7_CTRL_EGPR1_SEL_MASK (0x20000000U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_EGPR1_SEL_SHIFT (29U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_EGPR1_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_EGPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_CTRL_EGPR1_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_CTRL_EGPR1_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH7_CTRL_TOCTRL_MASK (0xC0000000U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_TOCTRL_SHIFT (30U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_TOCTRL_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH7_CTRL_TOCTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_CTRL_TOCTRL_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_CTRL_TOCTRL_MASK) /*! @} */ /*! @name TIM1_CH7_ECTRL - TIM[i] channel [x] extended control register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH7_ECTRL_EXT_CAP_SRC_MASK (0xFU) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_EXT_CAP_SRC_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_EXT_CAP_SRC_WIDTH (4U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_EXT_CAP_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_ECTRL_EXT_CAP_SRC_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_ECTRL_EXT_CAP_SRC_MASK) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_USE_PREV_TDU_IN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_USE_PREV_TDU_IN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_USE_PREV_TDU_IN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_USE_PREV_TDU_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_ECTRL_USE_PREV_TDU_IN_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_ECTRL_USE_PREV_TDU_IN_MASK) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_TODET_IRQ_SRC_MASK (0xC0U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_TODET_IRQ_SRC_SHIFT (6U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_TODET_IRQ_SRC_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_TODET_IRQ_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_ECTRL_TODET_IRQ_SRC_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_ECTRL_TODET_IRQ_SRC_MASK) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_TDU_START_MASK (0x700U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_TDU_START_SHIFT (8U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_TDU_START_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_TDU_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_ECTRL_TDU_START_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_ECTRL_TDU_START_MASK) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_TDU_STOP_MASK (0x7000U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_TDU_STOP_SHIFT (12U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_TDU_STOP_WIDTH (3U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_TDU_STOP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_ECTRL_TDU_STOP_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_ECTRL_TDU_STOP_MASK) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_TDU_RESYNC_MASK (0xF0000U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_TDU_RESYNC_SHIFT (16U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_TDU_RESYNC_WIDTH (4U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_TDU_RESYNC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_ECTRL_TDU_RESYNC_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_ECTRL_TDU_RESYNC_MASK) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_USE_LUT_MASK (0xC00000U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_USE_LUT_SHIFT (22U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_USE_LUT_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_USE_LUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_ECTRL_USE_LUT_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_ECTRL_USE_LUT_MASK) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_EFLT_CTR_RE_MASK (0x1000000U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_EFLT_CTR_RE_SHIFT (24U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_EFLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_EFLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_ECTRL_EFLT_CTR_RE_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_ECTRL_EFLT_CTR_RE_MASK) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_EFLT_CTR_FE_MASK (0x2000000U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_EFLT_CTR_FE_SHIFT (25U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_EFLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_EFLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_ECTRL_EFLT_CTR_FE_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_ECTRL_EFLT_CTR_FE_MASK) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_SWAP_CAPTURE_MASK (0x10000000U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_SWAP_CAPTURE_SHIFT (28U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_SWAP_CAPTURE_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_SWAP_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_ECTRL_SWAP_CAPTURE_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_ECTRL_SWAP_CAPTURE_MASK) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_IMM_START_MASK (0x20000000U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_IMM_START_SHIFT (29U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_IMM_START_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_IMM_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_ECTRL_IMM_START_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_ECTRL_IMM_START_MASK) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_ECLK_SEL_MASK (0x40000000U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_ECLK_SEL_SHIFT (30U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_ECLK_SEL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_ECLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_ECTRL_ECLK_SEL_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_ECTRL_ECLK_SEL_MASK) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_USE_PREV_CH_IN_MASK (0x80000000U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_USE_PREV_CH_IN_SHIFT (31U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_USE_PREV_CH_IN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_ECTRL_USE_PREV_CH_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_ECTRL_USE_PREV_CH_IN_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_ECTRL_USE_PREV_CH_IN_MASK) /*! @} */ /*! @name TIM1_CH7_IRQ_NOTIFY - TIM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_NEWVAL_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_NEWVAL_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_NEWVAL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_NEWVAL_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_NEWVAL_MASK) #define GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_ECNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_ECNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_CNTOFL_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_CNTOFL_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_CNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_CNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_CNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_GPROFL_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_GPROFL_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_GPROFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_GPROFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_GPROFL_MASK) #define GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_TODET_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_TODET_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_TODET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_TODET_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_TODET_MASK) #define GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_GLITCHDET_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_IRQ_NOTIFY_GLITCHDET_MASK) /*! @} */ /*! @name TIM1_CH7_IRQ_EN - TIM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH7_IRQ_EN_NEWVAL_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_EN_NEWVAL_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_EN_NEWVAL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_EN_NEWVAL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_IRQ_EN_NEWVAL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_IRQ_EN_NEWVAL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH7_IRQ_EN_ECNTOFL_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_EN_ECNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_EN_ECNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_IRQ_EN_ECNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH7_IRQ_EN_CNTOFL_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_EN_CNTOFL_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_EN_CNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_EN_CNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_IRQ_EN_CNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_IRQ_EN_CNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH7_IRQ_EN_GPROFL_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_EN_GPROFL_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_EN_GPROFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_EN_GPROFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_IRQ_EN_GPROFL_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_IRQ_EN_GPROFL_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH7_IRQ_EN_TODET_IRQ_EN_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_EN_TODET_IRQ_EN_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_EN_TODET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_EN_TODET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_IRQ_EN_TODET_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_IRQ_EN_TODET_IRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH7_IRQ_EN_GLITCHDET_IRQ_EN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_EN_GLITCHDET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_EN_GLITCHDET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_IRQ_EN_GLITCHDET_IRQ_EN_MASK) /*! @} */ /*! @name TIM1_CH7_IRQ_FORCINT - TIM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_NEWVAL_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_NEWVAL_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_NEWVAL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_NEWVAL_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_NEWVAL_MASK) #define GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_ECNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_ECNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_CNTOFL_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_CNTOFL_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_CNTOFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_CNTOFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_CNTOFL_MASK) #define GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_GPROFL_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_GPROFL_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_GPROFL_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_GPROFL_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_GPROFL_MASK) #define GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_TODET_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_TODET_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_TODET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_TODET_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_TODET_MASK) #define GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_GLITCHDET_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_IRQ_FORCINT_TRG_GLITCHDET_MASK) /*! @} */ /*! @name TIM1_CH7_IRQ_MODE - TIM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH7_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TIM1_CH7_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TIM1_CH7_EIRQ_EN - TIM[i] channel [x] error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_NEWVAL_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_NEWVAL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_NEWVAL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_NEWVAL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_ECNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_ECNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_CNTOFL_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_CNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_CNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_CNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_GPROFL_EIRQ_EN_MASK (0x8U) #define GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT (3U) #define GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_GPROFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_GPROFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_GPROFL_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_TODET_EIRQ_EN_MASK (0x10U) #define GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_TODET_EIRQ_EN_SHIFT (4U) #define GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_TODET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_TODET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_TODET_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_TODET_EIRQ_EN_MASK) #define GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK (0x20U) #define GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT (5U) #define GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_GLITCHDET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_GLITCHDET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_TIM1_CH7_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK) /*! @} */ /*! @name TIM1_INP_VAL - TIM[i] input value observation register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT0_MASK (0x1U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT0_SHIFT (0U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT0_WIDTH (1U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_INP_VAL_F_OUT0_SHIFT)) & GTM_gtm_cls1_TIM1_INP_VAL_F_OUT0_MASK) #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT1_MASK (0x2U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT1_SHIFT (1U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT1_WIDTH (1U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_INP_VAL_F_OUT1_SHIFT)) & GTM_gtm_cls1_TIM1_INP_VAL_F_OUT1_MASK) #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT2_MASK (0x4U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT2_SHIFT (2U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT2_WIDTH (1U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_INP_VAL_F_OUT2_SHIFT)) & GTM_gtm_cls1_TIM1_INP_VAL_F_OUT2_MASK) #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT3_MASK (0x8U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT3_SHIFT (3U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT3_WIDTH (1U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_INP_VAL_F_OUT3_SHIFT)) & GTM_gtm_cls1_TIM1_INP_VAL_F_OUT3_MASK) #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT4_MASK (0x10U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT4_SHIFT (4U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT4_WIDTH (1U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_INP_VAL_F_OUT4_SHIFT)) & GTM_gtm_cls1_TIM1_INP_VAL_F_OUT4_MASK) #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT5_MASK (0x20U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT5_SHIFT (5U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT5_WIDTH (1U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_INP_VAL_F_OUT5_SHIFT)) & GTM_gtm_cls1_TIM1_INP_VAL_F_OUT5_MASK) #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT6_MASK (0x40U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT6_SHIFT (6U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT6_WIDTH (1U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_INP_VAL_F_OUT6_SHIFT)) & GTM_gtm_cls1_TIM1_INP_VAL_F_OUT6_MASK) #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT7_MASK (0x80U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT7_SHIFT (7U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT7_WIDTH (1U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_OUT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_INP_VAL_F_OUT7_SHIFT)) & GTM_gtm_cls1_TIM1_INP_VAL_F_OUT7_MASK) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN0_MASK (0x100U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN0_SHIFT (8U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN0_WIDTH (1U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_INP_VAL_F_IN0_SHIFT)) & GTM_gtm_cls1_TIM1_INP_VAL_F_IN0_MASK) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN1_MASK (0x200U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN1_SHIFT (9U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN1_WIDTH (1U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_INP_VAL_F_IN1_SHIFT)) & GTM_gtm_cls1_TIM1_INP_VAL_F_IN1_MASK) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN2_MASK (0x400U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN2_SHIFT (10U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN2_WIDTH (1U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_INP_VAL_F_IN2_SHIFT)) & GTM_gtm_cls1_TIM1_INP_VAL_F_IN2_MASK) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN3_MASK (0x800U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN3_SHIFT (11U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN3_WIDTH (1U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_INP_VAL_F_IN3_SHIFT)) & GTM_gtm_cls1_TIM1_INP_VAL_F_IN3_MASK) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN4_MASK (0x1000U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN4_SHIFT (12U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN4_WIDTH (1U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_INP_VAL_F_IN4_SHIFT)) & GTM_gtm_cls1_TIM1_INP_VAL_F_IN4_MASK) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN5_MASK (0x2000U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN5_SHIFT (13U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN5_WIDTH (1U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_INP_VAL_F_IN5_SHIFT)) & GTM_gtm_cls1_TIM1_INP_VAL_F_IN5_MASK) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN6_MASK (0x4000U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN6_SHIFT (14U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN6_WIDTH (1U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_INP_VAL_F_IN6_SHIFT)) & GTM_gtm_cls1_TIM1_INP_VAL_F_IN6_MASK) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN7_MASK (0x8000U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN7_SHIFT (15U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN7_WIDTH (1U) #define GTM_gtm_cls1_TIM1_INP_VAL_F_IN7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_INP_VAL_F_IN7_SHIFT)) & GTM_gtm_cls1_TIM1_INP_VAL_F_IN7_MASK) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN0_MASK (0x10000U) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN0_SHIFT (16U) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN0_WIDTH (1U) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN0_SHIFT)) & GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN0_MASK) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN1_MASK (0x20000U) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN1_SHIFT (17U) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN1_WIDTH (1U) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN1_SHIFT)) & GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN1_MASK) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN2_MASK (0x40000U) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN2_SHIFT (18U) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN2_WIDTH (1U) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN2_SHIFT)) & GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN2_MASK) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN3_MASK (0x80000U) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN3_SHIFT (19U) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN3_WIDTH (1U) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN3_SHIFT)) & GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN3_MASK) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN4_MASK (0x100000U) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN4_SHIFT (20U) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN4_WIDTH (1U) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN4_SHIFT)) & GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN4_MASK) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN5_MASK (0x200000U) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN5_SHIFT (21U) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN5_WIDTH (1U) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN5_SHIFT)) & GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN5_MASK) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN6_MASK (0x400000U) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN6_SHIFT (22U) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN6_WIDTH (1U) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN6_SHIFT)) & GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN6_MASK) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN7_MASK (0x800000U) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN7_SHIFT (23U) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN7_WIDTH (1U) #define GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN7_SHIFT)) & GTM_gtm_cls1_TIM1_INP_VAL_TIM_IN7_MASK) /*! @} */ /*! @name TIM1_IN_SRC - TIM[i] AUX IN source selection register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_0_MASK (0x3U) #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_0_SHIFT (0U) #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_0_WIDTH (2U) #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_IN_SRC_VAL_0_SHIFT)) & GTM_gtm_cls1_TIM1_IN_SRC_VAL_0_MASK) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_0_MASK (0xCU) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_0_SHIFT (2U) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_0_WIDTH (2U) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_IN_SRC_MODE_0_SHIFT)) & GTM_gtm_cls1_TIM1_IN_SRC_MODE_0_MASK) #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_1_MASK (0x30U) #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_1_SHIFT (4U) #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_1_WIDTH (2U) #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_IN_SRC_VAL_1_SHIFT)) & GTM_gtm_cls1_TIM1_IN_SRC_VAL_1_MASK) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_1_MASK (0xC0U) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_1_SHIFT (6U) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_1_WIDTH (2U) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_IN_SRC_MODE_1_SHIFT)) & GTM_gtm_cls1_TIM1_IN_SRC_MODE_1_MASK) #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_2_MASK (0x300U) #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_2_SHIFT (8U) #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_2_WIDTH (2U) #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_IN_SRC_VAL_2_SHIFT)) & GTM_gtm_cls1_TIM1_IN_SRC_VAL_2_MASK) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_2_MASK (0xC00U) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_2_SHIFT (10U) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_2_WIDTH (2U) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_IN_SRC_MODE_2_SHIFT)) & GTM_gtm_cls1_TIM1_IN_SRC_MODE_2_MASK) #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_3_MASK (0x3000U) #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_3_SHIFT (12U) #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_3_WIDTH (2U) #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_IN_SRC_VAL_3_SHIFT)) & GTM_gtm_cls1_TIM1_IN_SRC_VAL_3_MASK) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_3_MASK (0xC000U) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_3_SHIFT (14U) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_3_WIDTH (2U) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_IN_SRC_MODE_3_SHIFT)) & GTM_gtm_cls1_TIM1_IN_SRC_MODE_3_MASK) #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_4_MASK (0x30000U) #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_4_SHIFT (16U) #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_4_WIDTH (2U) #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_IN_SRC_VAL_4_SHIFT)) & GTM_gtm_cls1_TIM1_IN_SRC_VAL_4_MASK) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_4_MASK (0xC0000U) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_4_SHIFT (18U) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_4_WIDTH (2U) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_IN_SRC_MODE_4_SHIFT)) & GTM_gtm_cls1_TIM1_IN_SRC_MODE_4_MASK) #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_5_MASK (0x300000U) #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_5_SHIFT (20U) #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_5_WIDTH (2U) #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_IN_SRC_VAL_5_SHIFT)) & GTM_gtm_cls1_TIM1_IN_SRC_VAL_5_MASK) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_5_MASK (0xC00000U) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_5_SHIFT (22U) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_5_WIDTH (2U) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_IN_SRC_MODE_5_SHIFT)) & GTM_gtm_cls1_TIM1_IN_SRC_MODE_5_MASK) #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_6_MASK (0x3000000U) #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_6_SHIFT (24U) #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_6_WIDTH (2U) #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_IN_SRC_VAL_6_SHIFT)) & GTM_gtm_cls1_TIM1_IN_SRC_VAL_6_MASK) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_6_MASK (0xC000000U) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_6_SHIFT (26U) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_6_WIDTH (2U) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_IN_SRC_MODE_6_SHIFT)) & GTM_gtm_cls1_TIM1_IN_SRC_MODE_6_MASK) #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_7_MASK (0x30000000U) #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_7_SHIFT (28U) #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_7_WIDTH (2U) #define GTM_gtm_cls1_TIM1_IN_SRC_VAL_7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_IN_SRC_VAL_7_SHIFT)) & GTM_gtm_cls1_TIM1_IN_SRC_VAL_7_MASK) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_7_MASK (0xC0000000U) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_7_SHIFT (30U) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_7_WIDTH (2U) #define GTM_gtm_cls1_TIM1_IN_SRC_MODE_7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_IN_SRC_MODE_7_SHIFT)) & GTM_gtm_cls1_TIM1_IN_SRC_MODE_7_MASK) /*! @} */ /*! @name TIM1_RST - TIM[i] global software reset register */ /*! @{ */ #define GTM_gtm_cls1_TIM1_RST_RST_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIM1_RST_RST_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIM1_RST_RST_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIM1_RST_RST_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_RST_RST_CH0_SHIFT)) & GTM_gtm_cls1_TIM1_RST_RST_CH0_MASK) #define GTM_gtm_cls1_TIM1_RST_RST_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIM1_RST_RST_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIM1_RST_RST_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIM1_RST_RST_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_RST_RST_CH1_SHIFT)) & GTM_gtm_cls1_TIM1_RST_RST_CH1_MASK) #define GTM_gtm_cls1_TIM1_RST_RST_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIM1_RST_RST_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIM1_RST_RST_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIM1_RST_RST_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_RST_RST_CH2_SHIFT)) & GTM_gtm_cls1_TIM1_RST_RST_CH2_MASK) #define GTM_gtm_cls1_TIM1_RST_RST_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIM1_RST_RST_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIM1_RST_RST_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIM1_RST_RST_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_RST_RST_CH3_SHIFT)) & GTM_gtm_cls1_TIM1_RST_RST_CH3_MASK) #define GTM_gtm_cls1_TIM1_RST_RST_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIM1_RST_RST_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIM1_RST_RST_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIM1_RST_RST_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_RST_RST_CH4_SHIFT)) & GTM_gtm_cls1_TIM1_RST_RST_CH4_MASK) #define GTM_gtm_cls1_TIM1_RST_RST_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIM1_RST_RST_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIM1_RST_RST_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIM1_RST_RST_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_RST_RST_CH5_SHIFT)) & GTM_gtm_cls1_TIM1_RST_RST_CH5_MASK) #define GTM_gtm_cls1_TIM1_RST_RST_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIM1_RST_RST_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIM1_RST_RST_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIM1_RST_RST_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_RST_RST_CH6_SHIFT)) & GTM_gtm_cls1_TIM1_RST_RST_CH6_MASK) #define GTM_gtm_cls1_TIM1_RST_RST_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIM1_RST_RST_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIM1_RST_RST_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIM1_RST_RST_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIM1_RST_RST_CH7_SHIFT)) & GTM_gtm_cls1_TIM1_RST_RST_CH7_MASK) /*! @} */ /*! @name TOM1_CH0_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH0_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH0_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH0_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH0_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH0_CTRL_SL_SHIFT)) & GTM_gtm_cls1_TOM1_CH0_CTRL_SL_MASK) #define GTM_gtm_cls1_TOM1_CH0_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH0_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls1_TOM1_CH0_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls1_TOM1_CH0_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH0_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls1_TOM1_CH0_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls1_TOM1_CH0_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH0_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH0_CTRL_UDMODE_MASK) #define GTM_gtm_cls1_TOM1_CH0_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH0_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls1_TOM1_CH0_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls1_TOM1_CH0_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH0_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH0_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH0_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH0_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH0_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH0_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH0_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH0_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH0_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH0_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH0_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH0_CTRL_SPE_TRIG_MASK (0x2000000U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_SPE_TRIG_SHIFT (25U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_SPE_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_SPE_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH0_CTRL_SPE_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH0_CTRL_SPE_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH0_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH0_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_TOM1_CH0_CTRL_OSM_MASK) #define GTM_gtm_cls1_TOM1_CH0_CTRL_SPEM_MASK (0x10000000U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_SPEM_SHIFT (28U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_SPEM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_SPEM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH0_CTRL_SPEM_SHIFT)) & GTM_gtm_cls1_TOM1_CH0_CTRL_SPEM_MASK) #define GTM_gtm_cls1_TOM1_CH0_CTRL_GCM_MASK (0x20000000U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_GCM_SHIFT (29U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_GCM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_GCM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH0_CTRL_GCM_SHIFT)) & GTM_gtm_cls1_TOM1_CH0_CTRL_GCM_MASK) #define GTM_gtm_cls1_TOM1_CH0_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH0_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls1_TOM1_CH0_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM1_CH0_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH0_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH0_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH0_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH0_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH0_SR0_SR0_SHIFT)) & GTM_gtm_cls1_TOM1_CH0_SR0_SR0_MASK) /*! @} */ /*! @name TOM1_CH0_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH0_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH0_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH0_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH0_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH0_SR1_SR1_SHIFT)) & GTM_gtm_cls1_TOM1_CH0_SR1_SR1_MASK) /*! @} */ /*! @name TOM1_CH0_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH0_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH0_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH0_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH0_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH0_CM0_CM0_SHIFT)) & GTM_gtm_cls1_TOM1_CH0_CM0_CM0_MASK) /*! @} */ /*! @name TOM1_CH0_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH0_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH0_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH0_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH0_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH0_CM1_CM1_SHIFT)) & GTM_gtm_cls1_TOM1_CH0_CM1_CM1_MASK) /*! @} */ /*! @name TOM1_CH0_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH0_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH0_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH0_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH0_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH0_CN0_CN0_SHIFT)) & GTM_gtm_cls1_TOM1_CH0_CN0_CN0_MASK) /*! @} */ /*! @name TOM1_CH0_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH0_STAT_OL_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH0_STAT_OL_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH0_STAT_OL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH0_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH0_STAT_OL_SHIFT)) & GTM_gtm_cls1_TOM1_CH0_STAT_OL_MASK) #define GTM_gtm_cls1_TOM1_CH0_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls1_TOM1_CH0_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls1_TOM1_CH0_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH0_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH0_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls1_TOM1_CH0_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM1_CH0_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH0_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH0_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH0_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH0_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH0_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH0_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH0_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH0_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH0_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH0_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH0_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH0_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH0_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH0_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH0_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH0_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH0_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH0_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH0_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls1_TOM1_CH0_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH0_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH0_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH0_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH0_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH0_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM1_CH0_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH0_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH0_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH0_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH0_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH0_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH0_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH0_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH0_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH0_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH0_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH0_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH0_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH0_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH0_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TOM1_CH0_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH0_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH0_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH0_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH0_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM1_CH0_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH0_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH0_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH0_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls1_TOM1_CH0_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH0_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH0_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH0_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM1_CH1_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH1_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH1_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH1_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH1_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH1_CTRL_SL_SHIFT)) & GTM_gtm_cls1_TOM1_CH1_CTRL_SL_MASK) #define GTM_gtm_cls1_TOM1_CH1_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH1_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls1_TOM1_CH1_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls1_TOM1_CH1_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH1_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls1_TOM1_CH1_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls1_TOM1_CH1_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH1_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH1_CTRL_UDMODE_MASK) #define GTM_gtm_cls1_TOM1_CH1_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH1_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls1_TOM1_CH1_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls1_TOM1_CH1_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH1_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH1_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH1_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH1_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH1_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH1_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH1_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH1_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH1_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH1_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH1_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH1_CTRL_SPE_TRIG_MASK (0x2000000U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_SPE_TRIG_SHIFT (25U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_SPE_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_SPE_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH1_CTRL_SPE_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH1_CTRL_SPE_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH1_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH1_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_TOM1_CH1_CTRL_OSM_MASK) #define GTM_gtm_cls1_TOM1_CH1_CTRL_SPEM_MASK (0x10000000U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_SPEM_SHIFT (28U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_SPEM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_SPEM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH1_CTRL_SPEM_SHIFT)) & GTM_gtm_cls1_TOM1_CH1_CTRL_SPEM_MASK) #define GTM_gtm_cls1_TOM1_CH1_CTRL_GCM_MASK (0x20000000U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_GCM_SHIFT (29U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_GCM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_GCM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH1_CTRL_GCM_SHIFT)) & GTM_gtm_cls1_TOM1_CH1_CTRL_GCM_MASK) #define GTM_gtm_cls1_TOM1_CH1_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH1_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls1_TOM1_CH1_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM1_CH1_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH1_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH1_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH1_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH1_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH1_SR0_SR0_SHIFT)) & GTM_gtm_cls1_TOM1_CH1_SR0_SR0_MASK) /*! @} */ /*! @name TOM1_CH1_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH1_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH1_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH1_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH1_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH1_SR1_SR1_SHIFT)) & GTM_gtm_cls1_TOM1_CH1_SR1_SR1_MASK) /*! @} */ /*! @name TOM1_CH1_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH1_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH1_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH1_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH1_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH1_CM0_CM0_SHIFT)) & GTM_gtm_cls1_TOM1_CH1_CM0_CM0_MASK) /*! @} */ /*! @name TOM1_CH1_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH1_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH1_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH1_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH1_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH1_CM1_CM1_SHIFT)) & GTM_gtm_cls1_TOM1_CH1_CM1_CM1_MASK) /*! @} */ /*! @name TOM1_CH1_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH1_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH1_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH1_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH1_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH1_CN0_CN0_SHIFT)) & GTM_gtm_cls1_TOM1_CH1_CN0_CN0_MASK) /*! @} */ /*! @name TOM1_CH1_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH1_STAT_OL_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH1_STAT_OL_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH1_STAT_OL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH1_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH1_STAT_OL_SHIFT)) & GTM_gtm_cls1_TOM1_CH1_STAT_OL_MASK) #define GTM_gtm_cls1_TOM1_CH1_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls1_TOM1_CH1_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls1_TOM1_CH1_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH1_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH1_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls1_TOM1_CH1_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM1_CH1_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH1_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH1_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH1_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH1_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH1_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH1_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH1_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH1_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH1_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH1_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH1_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH1_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH1_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH1_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH1_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH1_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH1_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH1_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH1_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls1_TOM1_CH1_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH1_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH1_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH1_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH1_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH1_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM1_CH1_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH1_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH1_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH1_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH1_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH1_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH1_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH1_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH1_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH1_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH1_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH1_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH1_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH1_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH1_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TOM1_CH1_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH1_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH1_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH1_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH1_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM1_CH1_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH1_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH1_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH1_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls1_TOM1_CH1_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH1_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH1_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH1_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM1_CH2_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH2_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH2_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH2_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH2_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH2_CTRL_SL_SHIFT)) & GTM_gtm_cls1_TOM1_CH2_CTRL_SL_MASK) #define GTM_gtm_cls1_TOM1_CH2_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH2_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls1_TOM1_CH2_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls1_TOM1_CH2_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH2_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls1_TOM1_CH2_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls1_TOM1_CH2_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH2_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH2_CTRL_UDMODE_MASK) #define GTM_gtm_cls1_TOM1_CH2_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH2_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls1_TOM1_CH2_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls1_TOM1_CH2_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH2_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH2_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH2_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH2_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH2_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH2_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH2_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH2_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH2_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH2_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH2_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH2_CTRL_SPE_TRIG_MASK (0x2000000U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_SPE_TRIG_SHIFT (25U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_SPE_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_SPE_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH2_CTRL_SPE_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH2_CTRL_SPE_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH2_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH2_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_TOM1_CH2_CTRL_OSM_MASK) #define GTM_gtm_cls1_TOM1_CH2_CTRL_SPEM_MASK (0x10000000U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_SPEM_SHIFT (28U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_SPEM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_SPEM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH2_CTRL_SPEM_SHIFT)) & GTM_gtm_cls1_TOM1_CH2_CTRL_SPEM_MASK) #define GTM_gtm_cls1_TOM1_CH2_CTRL_GCM_MASK (0x20000000U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_GCM_SHIFT (29U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_GCM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_GCM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH2_CTRL_GCM_SHIFT)) & GTM_gtm_cls1_TOM1_CH2_CTRL_GCM_MASK) #define GTM_gtm_cls1_TOM1_CH2_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH2_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls1_TOM1_CH2_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM1_CH2_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH2_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH2_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH2_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH2_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH2_SR0_SR0_SHIFT)) & GTM_gtm_cls1_TOM1_CH2_SR0_SR0_MASK) /*! @} */ /*! @name TOM1_CH2_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH2_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH2_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH2_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH2_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH2_SR1_SR1_SHIFT)) & GTM_gtm_cls1_TOM1_CH2_SR1_SR1_MASK) /*! @} */ /*! @name TOM1_CH2_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH2_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH2_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH2_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH2_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH2_CM0_CM0_SHIFT)) & GTM_gtm_cls1_TOM1_CH2_CM0_CM0_MASK) /*! @} */ /*! @name TOM1_CH2_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH2_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH2_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH2_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH2_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH2_CM1_CM1_SHIFT)) & GTM_gtm_cls1_TOM1_CH2_CM1_CM1_MASK) /*! @} */ /*! @name TOM1_CH2_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH2_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH2_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH2_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH2_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH2_CN0_CN0_SHIFT)) & GTM_gtm_cls1_TOM1_CH2_CN0_CN0_MASK) /*! @} */ /*! @name TOM1_CH2_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH2_STAT_OL_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH2_STAT_OL_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH2_STAT_OL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH2_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH2_STAT_OL_SHIFT)) & GTM_gtm_cls1_TOM1_CH2_STAT_OL_MASK) #define GTM_gtm_cls1_TOM1_CH2_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls1_TOM1_CH2_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls1_TOM1_CH2_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH2_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH2_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls1_TOM1_CH2_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM1_CH2_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH2_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH2_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH2_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH2_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH2_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH2_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH2_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH2_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH2_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH2_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH2_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH2_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH2_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH2_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH2_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH2_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH2_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH2_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH2_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls1_TOM1_CH2_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH2_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH2_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH2_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH2_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH2_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM1_CH2_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH2_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH2_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH2_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH2_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH2_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH2_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH2_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH2_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH2_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH2_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH2_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH2_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH2_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH2_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TOM1_CH2_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH2_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH2_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH2_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH2_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM1_CH2_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH2_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH2_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH2_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls1_TOM1_CH2_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH2_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH2_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH2_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM1_CH3_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH3_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH3_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH3_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH3_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH3_CTRL_SL_SHIFT)) & GTM_gtm_cls1_TOM1_CH3_CTRL_SL_MASK) #define GTM_gtm_cls1_TOM1_CH3_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH3_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls1_TOM1_CH3_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls1_TOM1_CH3_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH3_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls1_TOM1_CH3_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls1_TOM1_CH3_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH3_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH3_CTRL_UDMODE_MASK) #define GTM_gtm_cls1_TOM1_CH3_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH3_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls1_TOM1_CH3_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls1_TOM1_CH3_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH3_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH3_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH3_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH3_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH3_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH3_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH3_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH3_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH3_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH3_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH3_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH3_CTRL_SPE_TRIG_MASK (0x2000000U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_SPE_TRIG_SHIFT (25U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_SPE_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_SPE_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH3_CTRL_SPE_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH3_CTRL_SPE_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH3_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH3_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_TOM1_CH3_CTRL_OSM_MASK) #define GTM_gtm_cls1_TOM1_CH3_CTRL_SPEM_MASK (0x10000000U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_SPEM_SHIFT (28U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_SPEM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_SPEM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH3_CTRL_SPEM_SHIFT)) & GTM_gtm_cls1_TOM1_CH3_CTRL_SPEM_MASK) #define GTM_gtm_cls1_TOM1_CH3_CTRL_GCM_MASK (0x20000000U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_GCM_SHIFT (29U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_GCM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_GCM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH3_CTRL_GCM_SHIFT)) & GTM_gtm_cls1_TOM1_CH3_CTRL_GCM_MASK) #define GTM_gtm_cls1_TOM1_CH3_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH3_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls1_TOM1_CH3_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM1_CH3_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH3_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH3_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH3_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH3_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH3_SR0_SR0_SHIFT)) & GTM_gtm_cls1_TOM1_CH3_SR0_SR0_MASK) /*! @} */ /*! @name TOM1_CH3_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH3_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH3_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH3_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH3_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH3_SR1_SR1_SHIFT)) & GTM_gtm_cls1_TOM1_CH3_SR1_SR1_MASK) /*! @} */ /*! @name TOM1_CH3_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH3_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH3_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH3_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH3_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH3_CM0_CM0_SHIFT)) & GTM_gtm_cls1_TOM1_CH3_CM0_CM0_MASK) /*! @} */ /*! @name TOM1_CH3_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH3_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH3_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH3_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH3_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH3_CM1_CM1_SHIFT)) & GTM_gtm_cls1_TOM1_CH3_CM1_CM1_MASK) /*! @} */ /*! @name TOM1_CH3_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH3_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH3_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH3_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH3_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH3_CN0_CN0_SHIFT)) & GTM_gtm_cls1_TOM1_CH3_CN0_CN0_MASK) /*! @} */ /*! @name TOM1_CH3_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH3_STAT_OL_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH3_STAT_OL_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH3_STAT_OL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH3_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH3_STAT_OL_SHIFT)) & GTM_gtm_cls1_TOM1_CH3_STAT_OL_MASK) #define GTM_gtm_cls1_TOM1_CH3_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls1_TOM1_CH3_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls1_TOM1_CH3_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH3_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH3_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls1_TOM1_CH3_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM1_CH3_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH3_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH3_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH3_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH3_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH3_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH3_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH3_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH3_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH3_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH3_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH3_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH3_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH3_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH3_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH3_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH3_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH3_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH3_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH3_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls1_TOM1_CH3_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH3_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH3_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH3_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH3_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH3_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM1_CH3_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH3_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH3_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH3_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH3_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH3_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH3_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH3_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH3_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH3_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH3_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH3_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH3_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH3_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH3_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TOM1_CH3_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH3_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH3_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH3_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH3_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM1_CH3_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH3_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH3_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH3_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls1_TOM1_CH3_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH3_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH3_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH3_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM1_CH4_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH4_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH4_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH4_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH4_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH4_CTRL_SL_SHIFT)) & GTM_gtm_cls1_TOM1_CH4_CTRL_SL_MASK) #define GTM_gtm_cls1_TOM1_CH4_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH4_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls1_TOM1_CH4_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls1_TOM1_CH4_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH4_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls1_TOM1_CH4_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls1_TOM1_CH4_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH4_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH4_CTRL_UDMODE_MASK) #define GTM_gtm_cls1_TOM1_CH4_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH4_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls1_TOM1_CH4_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls1_TOM1_CH4_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH4_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH4_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH4_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH4_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH4_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH4_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH4_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH4_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH4_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH4_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH4_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH4_CTRL_SPE_TRIG_MASK (0x2000000U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_SPE_TRIG_SHIFT (25U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_SPE_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_SPE_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH4_CTRL_SPE_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH4_CTRL_SPE_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH4_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH4_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_TOM1_CH4_CTRL_OSM_MASK) #define GTM_gtm_cls1_TOM1_CH4_CTRL_SPEM_MASK (0x10000000U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_SPEM_SHIFT (28U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_SPEM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_SPEM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH4_CTRL_SPEM_SHIFT)) & GTM_gtm_cls1_TOM1_CH4_CTRL_SPEM_MASK) #define GTM_gtm_cls1_TOM1_CH4_CTRL_GCM_MASK (0x20000000U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_GCM_SHIFT (29U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_GCM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_GCM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH4_CTRL_GCM_SHIFT)) & GTM_gtm_cls1_TOM1_CH4_CTRL_GCM_MASK) #define GTM_gtm_cls1_TOM1_CH4_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH4_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls1_TOM1_CH4_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM1_CH4_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH4_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH4_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH4_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH4_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH4_SR0_SR0_SHIFT)) & GTM_gtm_cls1_TOM1_CH4_SR0_SR0_MASK) /*! @} */ /*! @name TOM1_CH4_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH4_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH4_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH4_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH4_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH4_SR1_SR1_SHIFT)) & GTM_gtm_cls1_TOM1_CH4_SR1_SR1_MASK) /*! @} */ /*! @name TOM1_CH4_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH4_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH4_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH4_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH4_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH4_CM0_CM0_SHIFT)) & GTM_gtm_cls1_TOM1_CH4_CM0_CM0_MASK) /*! @} */ /*! @name TOM1_CH4_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH4_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH4_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH4_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH4_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH4_CM1_CM1_SHIFT)) & GTM_gtm_cls1_TOM1_CH4_CM1_CM1_MASK) /*! @} */ /*! @name TOM1_CH4_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH4_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH4_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH4_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH4_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH4_CN0_CN0_SHIFT)) & GTM_gtm_cls1_TOM1_CH4_CN0_CN0_MASK) /*! @} */ /*! @name TOM1_CH4_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH4_STAT_OL_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH4_STAT_OL_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH4_STAT_OL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH4_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH4_STAT_OL_SHIFT)) & GTM_gtm_cls1_TOM1_CH4_STAT_OL_MASK) #define GTM_gtm_cls1_TOM1_CH4_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls1_TOM1_CH4_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls1_TOM1_CH4_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH4_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH4_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls1_TOM1_CH4_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM1_CH4_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH4_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH4_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH4_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH4_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH4_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH4_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH4_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH4_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH4_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH4_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH4_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH4_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH4_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH4_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH4_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH4_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH4_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH4_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH4_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls1_TOM1_CH4_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH4_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH4_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH4_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH4_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH4_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM1_CH4_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH4_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH4_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH4_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH4_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH4_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH4_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH4_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH4_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH4_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH4_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH4_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH4_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH4_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH4_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TOM1_CH4_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH4_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH4_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH4_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH4_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM1_CH4_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH4_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH4_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH4_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls1_TOM1_CH4_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH4_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH4_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH4_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM1_CH5_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH5_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH5_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH5_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH5_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH5_CTRL_SL_SHIFT)) & GTM_gtm_cls1_TOM1_CH5_CTRL_SL_MASK) #define GTM_gtm_cls1_TOM1_CH5_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH5_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls1_TOM1_CH5_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls1_TOM1_CH5_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH5_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls1_TOM1_CH5_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls1_TOM1_CH5_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH5_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH5_CTRL_UDMODE_MASK) #define GTM_gtm_cls1_TOM1_CH5_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH5_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls1_TOM1_CH5_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls1_TOM1_CH5_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH5_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH5_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH5_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH5_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH5_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH5_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH5_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH5_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH5_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH5_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH5_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH5_CTRL_SPE_TRIG_MASK (0x2000000U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_SPE_TRIG_SHIFT (25U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_SPE_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_SPE_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH5_CTRL_SPE_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH5_CTRL_SPE_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH5_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH5_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_TOM1_CH5_CTRL_OSM_MASK) #define GTM_gtm_cls1_TOM1_CH5_CTRL_SPEM_MASK (0x10000000U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_SPEM_SHIFT (28U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_SPEM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_SPEM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH5_CTRL_SPEM_SHIFT)) & GTM_gtm_cls1_TOM1_CH5_CTRL_SPEM_MASK) #define GTM_gtm_cls1_TOM1_CH5_CTRL_GCM_MASK (0x20000000U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_GCM_SHIFT (29U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_GCM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_GCM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH5_CTRL_GCM_SHIFT)) & GTM_gtm_cls1_TOM1_CH5_CTRL_GCM_MASK) #define GTM_gtm_cls1_TOM1_CH5_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH5_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls1_TOM1_CH5_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM1_CH5_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH5_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH5_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH5_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH5_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH5_SR0_SR0_SHIFT)) & GTM_gtm_cls1_TOM1_CH5_SR0_SR0_MASK) /*! @} */ /*! @name TOM1_CH5_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH5_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH5_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH5_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH5_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH5_SR1_SR1_SHIFT)) & GTM_gtm_cls1_TOM1_CH5_SR1_SR1_MASK) /*! @} */ /*! @name TOM1_CH5_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH5_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH5_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH5_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH5_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH5_CM0_CM0_SHIFT)) & GTM_gtm_cls1_TOM1_CH5_CM0_CM0_MASK) /*! @} */ /*! @name TOM1_CH5_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH5_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH5_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH5_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH5_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH5_CM1_CM1_SHIFT)) & GTM_gtm_cls1_TOM1_CH5_CM1_CM1_MASK) /*! @} */ /*! @name TOM1_CH5_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH5_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH5_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH5_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH5_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH5_CN0_CN0_SHIFT)) & GTM_gtm_cls1_TOM1_CH5_CN0_CN0_MASK) /*! @} */ /*! @name TOM1_CH5_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH5_STAT_OL_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH5_STAT_OL_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH5_STAT_OL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH5_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH5_STAT_OL_SHIFT)) & GTM_gtm_cls1_TOM1_CH5_STAT_OL_MASK) #define GTM_gtm_cls1_TOM1_CH5_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls1_TOM1_CH5_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls1_TOM1_CH5_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH5_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH5_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls1_TOM1_CH5_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM1_CH5_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH5_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH5_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH5_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH5_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH5_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH5_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH5_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH5_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH5_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH5_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH5_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH5_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH5_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH5_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH5_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH5_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH5_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH5_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH5_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls1_TOM1_CH5_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH5_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH5_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH5_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH5_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH5_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM1_CH5_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH5_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH5_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH5_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH5_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH5_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH5_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH5_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH5_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH5_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH5_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH5_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH5_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH5_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH5_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TOM1_CH5_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH5_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH5_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH5_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH5_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM1_CH5_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH5_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH5_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH5_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls1_TOM1_CH5_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH5_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH5_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH5_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM1_CH6_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH6_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH6_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH6_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH6_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH6_CTRL_SL_SHIFT)) & GTM_gtm_cls1_TOM1_CH6_CTRL_SL_MASK) #define GTM_gtm_cls1_TOM1_CH6_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH6_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls1_TOM1_CH6_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls1_TOM1_CH6_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH6_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls1_TOM1_CH6_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls1_TOM1_CH6_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH6_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH6_CTRL_UDMODE_MASK) #define GTM_gtm_cls1_TOM1_CH6_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH6_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls1_TOM1_CH6_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls1_TOM1_CH6_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH6_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH6_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH6_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH6_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH6_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH6_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH6_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH6_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH6_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH6_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH6_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH6_CTRL_SPE_TRIG_MASK (0x2000000U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_SPE_TRIG_SHIFT (25U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_SPE_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_SPE_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH6_CTRL_SPE_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH6_CTRL_SPE_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH6_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH6_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_TOM1_CH6_CTRL_OSM_MASK) #define GTM_gtm_cls1_TOM1_CH6_CTRL_SPEM_MASK (0x10000000U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_SPEM_SHIFT (28U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_SPEM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_SPEM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH6_CTRL_SPEM_SHIFT)) & GTM_gtm_cls1_TOM1_CH6_CTRL_SPEM_MASK) #define GTM_gtm_cls1_TOM1_CH6_CTRL_GCM_MASK (0x20000000U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_GCM_SHIFT (29U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_GCM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_GCM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH6_CTRL_GCM_SHIFT)) & GTM_gtm_cls1_TOM1_CH6_CTRL_GCM_MASK) #define GTM_gtm_cls1_TOM1_CH6_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH6_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls1_TOM1_CH6_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM1_CH6_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH6_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH6_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH6_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH6_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH6_SR0_SR0_SHIFT)) & GTM_gtm_cls1_TOM1_CH6_SR0_SR0_MASK) /*! @} */ /*! @name TOM1_CH6_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH6_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH6_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH6_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH6_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH6_SR1_SR1_SHIFT)) & GTM_gtm_cls1_TOM1_CH6_SR1_SR1_MASK) /*! @} */ /*! @name TOM1_CH6_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH6_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH6_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH6_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH6_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH6_CM0_CM0_SHIFT)) & GTM_gtm_cls1_TOM1_CH6_CM0_CM0_MASK) /*! @} */ /*! @name TOM1_CH6_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH6_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH6_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH6_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH6_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH6_CM1_CM1_SHIFT)) & GTM_gtm_cls1_TOM1_CH6_CM1_CM1_MASK) /*! @} */ /*! @name TOM1_CH6_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH6_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH6_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH6_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH6_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH6_CN0_CN0_SHIFT)) & GTM_gtm_cls1_TOM1_CH6_CN0_CN0_MASK) /*! @} */ /*! @name TOM1_CH6_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH6_STAT_OL_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH6_STAT_OL_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH6_STAT_OL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH6_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH6_STAT_OL_SHIFT)) & GTM_gtm_cls1_TOM1_CH6_STAT_OL_MASK) #define GTM_gtm_cls1_TOM1_CH6_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls1_TOM1_CH6_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls1_TOM1_CH6_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH6_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH6_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls1_TOM1_CH6_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM1_CH6_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH6_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH6_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH6_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH6_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH6_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH6_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH6_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH6_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH6_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH6_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH6_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH6_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH6_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH6_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH6_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH6_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH6_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH6_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH6_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls1_TOM1_CH6_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH6_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH6_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH6_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH6_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH6_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM1_CH6_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH6_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH6_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH6_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH6_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH6_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH6_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH6_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH6_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH6_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH6_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH6_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH6_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH6_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH6_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TOM1_CH6_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH6_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH6_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH6_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH6_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM1_CH6_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH6_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH6_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH6_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls1_TOM1_CH6_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH6_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH6_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH6_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM1_CH7_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH7_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH7_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH7_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH7_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH7_CTRL_SL_SHIFT)) & GTM_gtm_cls1_TOM1_CH7_CTRL_SL_MASK) #define GTM_gtm_cls1_TOM1_CH7_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH7_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls1_TOM1_CH7_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls1_TOM1_CH7_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH7_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls1_TOM1_CH7_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls1_TOM1_CH7_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH7_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH7_CTRL_UDMODE_MASK) #define GTM_gtm_cls1_TOM1_CH7_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH7_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls1_TOM1_CH7_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls1_TOM1_CH7_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH7_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH7_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH7_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH7_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH7_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH7_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH7_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH7_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH7_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH7_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH7_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH7_CTRL_SPE_TRIG_MASK (0x2000000U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_SPE_TRIG_SHIFT (25U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_SPE_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_SPE_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH7_CTRL_SPE_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH7_CTRL_SPE_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH7_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH7_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_TOM1_CH7_CTRL_OSM_MASK) #define GTM_gtm_cls1_TOM1_CH7_CTRL_SPEM_MASK (0x10000000U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_SPEM_SHIFT (28U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_SPEM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_SPEM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH7_CTRL_SPEM_SHIFT)) & GTM_gtm_cls1_TOM1_CH7_CTRL_SPEM_MASK) #define GTM_gtm_cls1_TOM1_CH7_CTRL_GCM_MASK (0x20000000U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_GCM_SHIFT (29U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_GCM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_GCM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH7_CTRL_GCM_SHIFT)) & GTM_gtm_cls1_TOM1_CH7_CTRL_GCM_MASK) #define GTM_gtm_cls1_TOM1_CH7_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH7_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls1_TOM1_CH7_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM1_CH7_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH7_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH7_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH7_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH7_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH7_SR0_SR0_SHIFT)) & GTM_gtm_cls1_TOM1_CH7_SR0_SR0_MASK) /*! @} */ /*! @name TOM1_CH7_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH7_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH7_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH7_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH7_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH7_SR1_SR1_SHIFT)) & GTM_gtm_cls1_TOM1_CH7_SR1_SR1_MASK) /*! @} */ /*! @name TOM1_CH7_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH7_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH7_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH7_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH7_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH7_CM0_CM0_SHIFT)) & GTM_gtm_cls1_TOM1_CH7_CM0_CM0_MASK) /*! @} */ /*! @name TOM1_CH7_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH7_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH7_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH7_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH7_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH7_CM1_CM1_SHIFT)) & GTM_gtm_cls1_TOM1_CH7_CM1_CM1_MASK) /*! @} */ /*! @name TOM1_CH7_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH7_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH7_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH7_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH7_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH7_CN0_CN0_SHIFT)) & GTM_gtm_cls1_TOM1_CH7_CN0_CN0_MASK) /*! @} */ /*! @name TOM1_CH7_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH7_STAT_OL_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH7_STAT_OL_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH7_STAT_OL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH7_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH7_STAT_OL_SHIFT)) & GTM_gtm_cls1_TOM1_CH7_STAT_OL_MASK) #define GTM_gtm_cls1_TOM1_CH7_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls1_TOM1_CH7_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls1_TOM1_CH7_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH7_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH7_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls1_TOM1_CH7_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM1_CH7_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH7_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH7_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH7_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH7_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH7_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH7_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH7_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH7_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH7_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH7_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH7_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH7_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH7_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH7_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH7_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH7_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH7_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH7_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH7_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls1_TOM1_CH7_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH7_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH7_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH7_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH7_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH7_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM1_CH7_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH7_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH7_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH7_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH7_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH7_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH7_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH7_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH7_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH7_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH7_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH7_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH7_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH7_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH7_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TOM1_CH7_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH7_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH7_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH7_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH7_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM1_CH7_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH7_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH7_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH7_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls1_TOM1_CH7_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH7_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH7_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH7_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM1_CH8_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH8_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH8_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH8_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH8_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH8_CTRL_SL_SHIFT)) & GTM_gtm_cls1_TOM1_CH8_CTRL_SL_MASK) #define GTM_gtm_cls1_TOM1_CH8_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH8_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls1_TOM1_CH8_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls1_TOM1_CH8_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH8_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls1_TOM1_CH8_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls1_TOM1_CH8_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH8_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH8_CTRL_UDMODE_MASK) #define GTM_gtm_cls1_TOM1_CH8_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH8_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls1_TOM1_CH8_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls1_TOM1_CH8_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH8_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH8_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH8_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH8_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH8_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH8_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH8_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH8_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH8_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH8_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH8_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH8_CTRL_SPE_TRIG_MASK (0x2000000U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_SPE_TRIG_SHIFT (25U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_SPE_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_SPE_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH8_CTRL_SPE_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH8_CTRL_SPE_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH8_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH8_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_TOM1_CH8_CTRL_OSM_MASK) #define GTM_gtm_cls1_TOM1_CH8_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH8_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls1_TOM1_CH8_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM1_CH8_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH8_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH8_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH8_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH8_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH8_SR0_SR0_SHIFT)) & GTM_gtm_cls1_TOM1_CH8_SR0_SR0_MASK) /*! @} */ /*! @name TOM1_CH8_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH8_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH8_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH8_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH8_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH8_SR1_SR1_SHIFT)) & GTM_gtm_cls1_TOM1_CH8_SR1_SR1_MASK) /*! @} */ /*! @name TOM1_CH8_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH8_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH8_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH8_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH8_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH8_CM0_CM0_SHIFT)) & GTM_gtm_cls1_TOM1_CH8_CM0_CM0_MASK) /*! @} */ /*! @name TOM1_CH8_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH8_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH8_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH8_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH8_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH8_CM1_CM1_SHIFT)) & GTM_gtm_cls1_TOM1_CH8_CM1_CM1_MASK) /*! @} */ /*! @name TOM1_CH8_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH8_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH8_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH8_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH8_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH8_CN0_CN0_SHIFT)) & GTM_gtm_cls1_TOM1_CH8_CN0_CN0_MASK) /*! @} */ /*! @name TOM1_CH8_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH8_STAT_OL_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH8_STAT_OL_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH8_STAT_OL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH8_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH8_STAT_OL_SHIFT)) & GTM_gtm_cls1_TOM1_CH8_STAT_OL_MASK) #define GTM_gtm_cls1_TOM1_CH8_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls1_TOM1_CH8_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls1_TOM1_CH8_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH8_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH8_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls1_TOM1_CH8_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM1_CH8_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH8_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH8_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH8_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH8_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH8_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH8_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH8_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH8_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH8_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH8_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH8_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH8_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH8_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH8_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH8_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH8_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH8_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH8_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH8_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls1_TOM1_CH8_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH8_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH8_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH8_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH8_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH8_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM1_CH8_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH8_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH8_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH8_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH8_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH8_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH8_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH8_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH8_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH8_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH8_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH8_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH8_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH8_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH8_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TOM1_CH8_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH8_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH8_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH8_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH8_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM1_CH8_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH8_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH8_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH8_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls1_TOM1_CH8_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH8_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH8_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH8_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM1_CH9_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH9_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH9_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH9_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH9_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH9_CTRL_SL_SHIFT)) & GTM_gtm_cls1_TOM1_CH9_CTRL_SL_MASK) #define GTM_gtm_cls1_TOM1_CH9_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH9_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls1_TOM1_CH9_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls1_TOM1_CH9_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH9_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls1_TOM1_CH9_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls1_TOM1_CH9_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH9_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH9_CTRL_UDMODE_MASK) #define GTM_gtm_cls1_TOM1_CH9_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH9_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls1_TOM1_CH9_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls1_TOM1_CH9_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH9_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH9_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH9_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH9_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH9_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH9_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH9_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH9_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH9_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH9_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH9_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH9_CTRL_SPE_TRIG_MASK (0x2000000U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_SPE_TRIG_SHIFT (25U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_SPE_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_SPE_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH9_CTRL_SPE_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH9_CTRL_SPE_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH9_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH9_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_TOM1_CH9_CTRL_OSM_MASK) #define GTM_gtm_cls1_TOM1_CH9_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH9_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls1_TOM1_CH9_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM1_CH9_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH9_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH9_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH9_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH9_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH9_SR0_SR0_SHIFT)) & GTM_gtm_cls1_TOM1_CH9_SR0_SR0_MASK) /*! @} */ /*! @name TOM1_CH9_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH9_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH9_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH9_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH9_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH9_SR1_SR1_SHIFT)) & GTM_gtm_cls1_TOM1_CH9_SR1_SR1_MASK) /*! @} */ /*! @name TOM1_CH9_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH9_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH9_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH9_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH9_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH9_CM0_CM0_SHIFT)) & GTM_gtm_cls1_TOM1_CH9_CM0_CM0_MASK) /*! @} */ /*! @name TOM1_CH9_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH9_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH9_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH9_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH9_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH9_CM1_CM1_SHIFT)) & GTM_gtm_cls1_TOM1_CH9_CM1_CM1_MASK) /*! @} */ /*! @name TOM1_CH9_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH9_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH9_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH9_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH9_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH9_CN0_CN0_SHIFT)) & GTM_gtm_cls1_TOM1_CH9_CN0_CN0_MASK) /*! @} */ /*! @name TOM1_CH9_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH9_STAT_OL_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH9_STAT_OL_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH9_STAT_OL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH9_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH9_STAT_OL_SHIFT)) & GTM_gtm_cls1_TOM1_CH9_STAT_OL_MASK) #define GTM_gtm_cls1_TOM1_CH9_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls1_TOM1_CH9_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls1_TOM1_CH9_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH9_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH9_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls1_TOM1_CH9_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM1_CH9_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH9_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH9_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH9_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH9_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH9_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH9_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH9_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH9_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH9_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH9_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH9_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH9_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH9_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH9_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH9_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH9_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH9_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH9_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH9_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls1_TOM1_CH9_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH9_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH9_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH9_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH9_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH9_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM1_CH9_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH9_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH9_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH9_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH9_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH9_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH9_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH9_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH9_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH9_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH9_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH9_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH9_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH9_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH9_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TOM1_CH9_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH9_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH9_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH9_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH9_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM1_CH9_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH9_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH9_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH9_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls1_TOM1_CH9_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH9_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH9_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH9_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM1_CH10_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH10_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH10_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH10_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH10_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH10_CTRL_SL_SHIFT)) & GTM_gtm_cls1_TOM1_CH10_CTRL_SL_MASK) #define GTM_gtm_cls1_TOM1_CH10_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH10_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls1_TOM1_CH10_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls1_TOM1_CH10_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH10_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls1_TOM1_CH10_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls1_TOM1_CH10_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH10_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH10_CTRL_UDMODE_MASK) #define GTM_gtm_cls1_TOM1_CH10_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH10_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls1_TOM1_CH10_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls1_TOM1_CH10_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH10_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH10_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH10_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH10_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH10_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH10_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH10_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH10_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH10_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH10_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH10_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH10_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH10_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_TOM1_CH10_CTRL_OSM_MASK) #define GTM_gtm_cls1_TOM1_CH10_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH10_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls1_TOM1_CH10_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM1_CH10_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH10_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH10_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH10_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH10_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH10_SR0_SR0_SHIFT)) & GTM_gtm_cls1_TOM1_CH10_SR0_SR0_MASK) /*! @} */ /*! @name TOM1_CH10_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH10_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH10_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH10_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH10_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH10_SR1_SR1_SHIFT)) & GTM_gtm_cls1_TOM1_CH10_SR1_SR1_MASK) /*! @} */ /*! @name TOM1_CH10_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH10_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH10_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH10_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH10_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH10_CM0_CM0_SHIFT)) & GTM_gtm_cls1_TOM1_CH10_CM0_CM0_MASK) /*! @} */ /*! @name TOM1_CH10_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH10_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH10_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH10_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH10_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH10_CM1_CM1_SHIFT)) & GTM_gtm_cls1_TOM1_CH10_CM1_CM1_MASK) /*! @} */ /*! @name TOM1_CH10_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH10_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH10_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH10_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH10_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH10_CN0_CN0_SHIFT)) & GTM_gtm_cls1_TOM1_CH10_CN0_CN0_MASK) /*! @} */ /*! @name TOM1_CH10_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH10_STAT_OL_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH10_STAT_OL_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH10_STAT_OL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH10_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH10_STAT_OL_SHIFT)) & GTM_gtm_cls1_TOM1_CH10_STAT_OL_MASK) #define GTM_gtm_cls1_TOM1_CH10_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls1_TOM1_CH10_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls1_TOM1_CH10_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH10_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH10_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls1_TOM1_CH10_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM1_CH10_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH10_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH10_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH10_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH10_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH10_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH10_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH10_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH10_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH10_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH10_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH10_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH10_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH10_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH10_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH10_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH10_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH10_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH10_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH10_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls1_TOM1_CH10_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH10_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH10_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH10_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH10_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH10_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM1_CH10_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH10_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH10_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH10_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH10_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH10_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH10_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH10_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH10_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH10_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH10_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH10_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH10_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH10_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH10_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TOM1_CH10_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH10_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH10_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH10_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH10_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM1_CH10_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH10_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH10_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH10_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls1_TOM1_CH10_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH10_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH10_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH10_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM1_CH11_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH11_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH11_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH11_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH11_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH11_CTRL_SL_SHIFT)) & GTM_gtm_cls1_TOM1_CH11_CTRL_SL_MASK) #define GTM_gtm_cls1_TOM1_CH11_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH11_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls1_TOM1_CH11_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls1_TOM1_CH11_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH11_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls1_TOM1_CH11_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls1_TOM1_CH11_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH11_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH11_CTRL_UDMODE_MASK) #define GTM_gtm_cls1_TOM1_CH11_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH11_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls1_TOM1_CH11_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls1_TOM1_CH11_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH11_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH11_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH11_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH11_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH11_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH11_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH11_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH11_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH11_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH11_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH11_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH11_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH11_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_TOM1_CH11_CTRL_OSM_MASK) #define GTM_gtm_cls1_TOM1_CH11_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH11_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls1_TOM1_CH11_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM1_CH11_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH11_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH11_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH11_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH11_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH11_SR0_SR0_SHIFT)) & GTM_gtm_cls1_TOM1_CH11_SR0_SR0_MASK) /*! @} */ /*! @name TOM1_CH11_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH11_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH11_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH11_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH11_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH11_SR1_SR1_SHIFT)) & GTM_gtm_cls1_TOM1_CH11_SR1_SR1_MASK) /*! @} */ /*! @name TOM1_CH11_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH11_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH11_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH11_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH11_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH11_CM0_CM0_SHIFT)) & GTM_gtm_cls1_TOM1_CH11_CM0_CM0_MASK) /*! @} */ /*! @name TOM1_CH11_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH11_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH11_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH11_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH11_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH11_CM1_CM1_SHIFT)) & GTM_gtm_cls1_TOM1_CH11_CM1_CM1_MASK) /*! @} */ /*! @name TOM1_CH11_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH11_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH11_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH11_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH11_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH11_CN0_CN0_SHIFT)) & GTM_gtm_cls1_TOM1_CH11_CN0_CN0_MASK) /*! @} */ /*! @name TOM1_CH11_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH11_STAT_OL_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH11_STAT_OL_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH11_STAT_OL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH11_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH11_STAT_OL_SHIFT)) & GTM_gtm_cls1_TOM1_CH11_STAT_OL_MASK) #define GTM_gtm_cls1_TOM1_CH11_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls1_TOM1_CH11_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls1_TOM1_CH11_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH11_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH11_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls1_TOM1_CH11_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM1_CH11_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH11_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH11_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH11_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH11_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH11_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH11_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH11_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH11_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH11_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH11_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH11_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH11_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH11_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH11_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH11_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH11_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH11_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH11_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH11_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls1_TOM1_CH11_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH11_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH11_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH11_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH11_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH11_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM1_CH11_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH11_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH11_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH11_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH11_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH11_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH11_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH11_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH11_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH11_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH11_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH11_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH11_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH11_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH11_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TOM1_CH11_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH11_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH11_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH11_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH11_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM1_CH11_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH11_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH11_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH11_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls1_TOM1_CH11_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH11_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH11_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH11_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM1_CH12_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH12_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH12_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH12_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH12_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH12_CTRL_SL_SHIFT)) & GTM_gtm_cls1_TOM1_CH12_CTRL_SL_MASK) #define GTM_gtm_cls1_TOM1_CH12_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH12_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls1_TOM1_CH12_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls1_TOM1_CH12_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH12_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls1_TOM1_CH12_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls1_TOM1_CH12_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH12_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH12_CTRL_UDMODE_MASK) #define GTM_gtm_cls1_TOM1_CH12_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH12_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls1_TOM1_CH12_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls1_TOM1_CH12_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH12_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH12_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH12_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH12_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH12_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH12_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH12_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH12_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH12_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH12_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH12_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH12_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH12_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_TOM1_CH12_CTRL_OSM_MASK) #define GTM_gtm_cls1_TOM1_CH12_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH12_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls1_TOM1_CH12_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM1_CH12_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH12_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH12_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH12_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH12_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH12_SR0_SR0_SHIFT)) & GTM_gtm_cls1_TOM1_CH12_SR0_SR0_MASK) /*! @} */ /*! @name TOM1_CH12_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH12_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH12_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH12_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH12_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH12_SR1_SR1_SHIFT)) & GTM_gtm_cls1_TOM1_CH12_SR1_SR1_MASK) /*! @} */ /*! @name TOM1_CH12_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH12_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH12_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH12_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH12_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH12_CM0_CM0_SHIFT)) & GTM_gtm_cls1_TOM1_CH12_CM0_CM0_MASK) /*! @} */ /*! @name TOM1_CH12_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH12_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH12_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH12_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH12_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH12_CM1_CM1_SHIFT)) & GTM_gtm_cls1_TOM1_CH12_CM1_CM1_MASK) /*! @} */ /*! @name TOM1_CH12_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH12_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH12_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH12_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH12_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH12_CN0_CN0_SHIFT)) & GTM_gtm_cls1_TOM1_CH12_CN0_CN0_MASK) /*! @} */ /*! @name TOM1_CH12_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH12_STAT_OL_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH12_STAT_OL_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH12_STAT_OL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH12_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH12_STAT_OL_SHIFT)) & GTM_gtm_cls1_TOM1_CH12_STAT_OL_MASK) #define GTM_gtm_cls1_TOM1_CH12_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls1_TOM1_CH12_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls1_TOM1_CH12_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH12_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH12_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls1_TOM1_CH12_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM1_CH12_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH12_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH12_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH12_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH12_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH12_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH12_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH12_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH12_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH12_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH12_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH12_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH12_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH12_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH12_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH12_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH12_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH12_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH12_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH12_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls1_TOM1_CH12_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH12_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH12_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH12_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH12_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH12_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM1_CH12_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH12_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH12_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH12_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH12_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH12_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH12_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH12_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH12_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH12_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH12_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH12_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH12_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH12_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH12_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TOM1_CH12_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH12_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH12_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH12_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH12_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM1_CH12_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH12_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH12_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH12_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls1_TOM1_CH12_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH12_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH12_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH12_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM1_CH13_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH13_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH13_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH13_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH13_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH13_CTRL_SL_SHIFT)) & GTM_gtm_cls1_TOM1_CH13_CTRL_SL_MASK) #define GTM_gtm_cls1_TOM1_CH13_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH13_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls1_TOM1_CH13_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls1_TOM1_CH13_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH13_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls1_TOM1_CH13_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls1_TOM1_CH13_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH13_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH13_CTRL_UDMODE_MASK) #define GTM_gtm_cls1_TOM1_CH13_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH13_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls1_TOM1_CH13_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls1_TOM1_CH13_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH13_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH13_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH13_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH13_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH13_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH13_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH13_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH13_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH13_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH13_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH13_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH13_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH13_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_TOM1_CH13_CTRL_OSM_MASK) #define GTM_gtm_cls1_TOM1_CH13_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH13_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls1_TOM1_CH13_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM1_CH13_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH13_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH13_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH13_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH13_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH13_SR0_SR0_SHIFT)) & GTM_gtm_cls1_TOM1_CH13_SR0_SR0_MASK) /*! @} */ /*! @name TOM1_CH13_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH13_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH13_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH13_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH13_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH13_SR1_SR1_SHIFT)) & GTM_gtm_cls1_TOM1_CH13_SR1_SR1_MASK) /*! @} */ /*! @name TOM1_CH13_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH13_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH13_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH13_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH13_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH13_CM0_CM0_SHIFT)) & GTM_gtm_cls1_TOM1_CH13_CM0_CM0_MASK) /*! @} */ /*! @name TOM1_CH13_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH13_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH13_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH13_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH13_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH13_CM1_CM1_SHIFT)) & GTM_gtm_cls1_TOM1_CH13_CM1_CM1_MASK) /*! @} */ /*! @name TOM1_CH13_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH13_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH13_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH13_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH13_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH13_CN0_CN0_SHIFT)) & GTM_gtm_cls1_TOM1_CH13_CN0_CN0_MASK) /*! @} */ /*! @name TOM1_CH13_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH13_STAT_OL_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH13_STAT_OL_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH13_STAT_OL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH13_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH13_STAT_OL_SHIFT)) & GTM_gtm_cls1_TOM1_CH13_STAT_OL_MASK) #define GTM_gtm_cls1_TOM1_CH13_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls1_TOM1_CH13_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls1_TOM1_CH13_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH13_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH13_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls1_TOM1_CH13_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM1_CH13_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH13_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH13_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH13_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH13_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH13_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH13_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH13_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH13_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH13_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH13_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH13_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH13_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH13_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH13_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH13_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH13_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH13_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH13_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH13_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls1_TOM1_CH13_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH13_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH13_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH13_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH13_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH13_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM1_CH13_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH13_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH13_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH13_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH13_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH13_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH13_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH13_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH13_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH13_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH13_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH13_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH13_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH13_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH13_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TOM1_CH13_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH13_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH13_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH13_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH13_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM1_CH13_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH13_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH13_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH13_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls1_TOM1_CH13_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH13_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH13_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH13_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM1_CH14_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH14_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH14_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH14_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH14_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH14_CTRL_SL_SHIFT)) & GTM_gtm_cls1_TOM1_CH14_CTRL_SL_MASK) #define GTM_gtm_cls1_TOM1_CH14_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH14_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls1_TOM1_CH14_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls1_TOM1_CH14_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH14_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls1_TOM1_CH14_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls1_TOM1_CH14_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH14_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH14_CTRL_UDMODE_MASK) #define GTM_gtm_cls1_TOM1_CH14_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH14_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls1_TOM1_CH14_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls1_TOM1_CH14_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH14_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH14_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH14_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH14_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH14_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH14_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH14_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH14_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH14_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH14_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH14_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH14_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH14_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_TOM1_CH14_CTRL_OSM_MASK) #define GTM_gtm_cls1_TOM1_CH14_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH14_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls1_TOM1_CH14_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM1_CH14_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH14_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH14_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH14_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH14_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH14_SR0_SR0_SHIFT)) & GTM_gtm_cls1_TOM1_CH14_SR0_SR0_MASK) /*! @} */ /*! @name TOM1_CH14_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH14_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH14_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH14_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH14_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH14_SR1_SR1_SHIFT)) & GTM_gtm_cls1_TOM1_CH14_SR1_SR1_MASK) /*! @} */ /*! @name TOM1_CH14_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH14_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH14_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH14_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH14_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH14_CM0_CM0_SHIFT)) & GTM_gtm_cls1_TOM1_CH14_CM0_CM0_MASK) /*! @} */ /*! @name TOM1_CH14_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH14_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH14_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH14_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH14_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH14_CM1_CM1_SHIFT)) & GTM_gtm_cls1_TOM1_CH14_CM1_CM1_MASK) /*! @} */ /*! @name TOM1_CH14_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH14_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH14_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH14_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH14_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH14_CN0_CN0_SHIFT)) & GTM_gtm_cls1_TOM1_CH14_CN0_CN0_MASK) /*! @} */ /*! @name TOM1_CH14_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH14_STAT_OL_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH14_STAT_OL_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH14_STAT_OL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH14_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH14_STAT_OL_SHIFT)) & GTM_gtm_cls1_TOM1_CH14_STAT_OL_MASK) #define GTM_gtm_cls1_TOM1_CH14_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls1_TOM1_CH14_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls1_TOM1_CH14_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH14_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH14_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls1_TOM1_CH14_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM1_CH14_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH14_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH14_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH14_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH14_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH14_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH14_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH14_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH14_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH14_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH14_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH14_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH14_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH14_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH14_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH14_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH14_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH14_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH14_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH14_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls1_TOM1_CH14_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH14_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH14_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH14_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH14_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH14_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM1_CH14_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH14_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH14_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH14_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH14_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH14_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH14_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH14_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH14_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH14_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH14_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH14_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH14_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH14_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH14_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TOM1_CH14_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH14_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH14_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH14_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH14_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM1_CH14_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH14_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH14_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH14_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls1_TOM1_CH14_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH14_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH14_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH14_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM1_CH15_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH15_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH15_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH15_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH15_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH15_CTRL_SL_SHIFT)) & GTM_gtm_cls1_TOM1_CH15_CTRL_SL_MASK) #define GTM_gtm_cls1_TOM1_CH15_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH15_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls1_TOM1_CH15_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls1_TOM1_CH15_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH15_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls1_TOM1_CH15_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls1_TOM1_CH15_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH15_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH15_CTRL_UDMODE_MASK) #define GTM_gtm_cls1_TOM1_CH15_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH15_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls1_TOM1_CH15_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls1_TOM1_CH15_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH15_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH15_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH15_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH15_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_CH15_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls1_TOM1_CH15_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH15_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH15_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH15_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH15_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls1_TOM1_CH15_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls1_TOM1_CH15_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH15_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_TOM1_CH15_CTRL_OSM_MASK) #define GTM_gtm_cls1_TOM1_CH15_CTRL_BITREV_MASK (0x8000000U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_BITREV_SHIFT (27U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_BITREV_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_BITREV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH15_CTRL_BITREV_SHIFT)) & GTM_gtm_cls1_TOM1_CH15_CTRL_BITREV_MASK) #define GTM_gtm_cls1_TOM1_CH15_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH15_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls1_TOM1_CH15_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM1_CH15_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH15_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH15_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH15_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH15_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH15_SR0_SR0_SHIFT)) & GTM_gtm_cls1_TOM1_CH15_SR0_SR0_MASK) /*! @} */ /*! @name TOM1_CH15_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH15_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH15_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH15_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH15_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH15_SR1_SR1_SHIFT)) & GTM_gtm_cls1_TOM1_CH15_SR1_SR1_MASK) /*! @} */ /*! @name TOM1_CH15_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH15_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH15_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH15_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH15_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH15_CM0_CM0_SHIFT)) & GTM_gtm_cls1_TOM1_CH15_CM0_CM0_MASK) /*! @} */ /*! @name TOM1_CH15_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH15_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH15_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH15_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH15_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH15_CM1_CM1_SHIFT)) & GTM_gtm_cls1_TOM1_CH15_CM1_CM1_MASK) /*! @} */ /*! @name TOM1_CH15_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH15_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls1_TOM1_CH15_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH15_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls1_TOM1_CH15_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH15_CN0_CN0_SHIFT)) & GTM_gtm_cls1_TOM1_CH15_CN0_CN0_MASK) /*! @} */ /*! @name TOM1_CH15_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH15_STAT_OL_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH15_STAT_OL_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH15_STAT_OL_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH15_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH15_STAT_OL_SHIFT)) & GTM_gtm_cls1_TOM1_CH15_STAT_OL_MASK) #define GTM_gtm_cls1_TOM1_CH15_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls1_TOM1_CH15_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls1_TOM1_CH15_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH15_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH15_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls1_TOM1_CH15_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM1_CH15_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH15_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH15_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH15_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH15_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH15_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH15_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH15_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH15_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH15_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH15_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH15_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH15_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH15_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH15_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH15_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH15_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH15_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH15_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH15_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls1_TOM1_CH15_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH15_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH15_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH15_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH15_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TOM1_CH15_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM1_CH15_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH15_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_TOM1_CH15_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH15_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH15_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH15_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH15_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls1_TOM1_CH15_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_TOM1_CH15_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_TOM1_CH15_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH15_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH15_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls1_TOM1_CH15_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM1_CH15_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH15_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TOM1_CH15_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TOM1_CH15_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TOM1_CH15_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH15_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TOM1_CH15_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM1_CH15_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_CH15_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH15_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH15_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls1_TOM1_CH15_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls1_TOM1_CH15_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_CH15_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls1_TOM1_CH15_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM1_TGC0_GLB_CTRL - TOM[i] TGC [g] global control register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_HOST_TRIG_MASK (0x1U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_HOST_TRIG_SHIFT (0U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_HOST_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_HOST_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_HOST_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_HOST_TRIG_MASK) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH0_MASK (0x100U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH0_SHIFT (8U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH0_WIDTH (1U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH0_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH0_MASK) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH1_MASK (0x200U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH1_SHIFT (9U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH1_WIDTH (1U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH1_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH1_MASK) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH2_MASK (0x400U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH2_SHIFT (10U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH2_WIDTH (1U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH2_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH2_MASK) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH3_MASK (0x800U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH3_SHIFT (11U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH3_WIDTH (1U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH3_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH3_MASK) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH4_MASK (0x1000U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH4_SHIFT (12U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH4_WIDTH (1U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH4_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH4_MASK) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH5_MASK (0x2000U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH5_SHIFT (13U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH5_WIDTH (1U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH5_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH5_MASK) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH6_MASK (0x4000U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH6_SHIFT (14U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH6_WIDTH (1U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH6_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH6_MASK) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH7_MASK (0x8000U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH7_SHIFT (15U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH7_WIDTH (1U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH7_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_RST_CH7_MASK) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL0_MASK (0x30000U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL0_SHIFT (16U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL0_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL0_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL0_MASK) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL1_MASK (0xC0000U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL1_SHIFT (18U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL1_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL1_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL1_MASK) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL2_MASK (0x300000U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL2_SHIFT (20U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL2_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL2_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL2_MASK) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL3_MASK (0xC00000U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL3_SHIFT (22U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL3_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL3_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL3_MASK) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL4_MASK (0x3000000U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL4_SHIFT (24U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL4_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL4_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL4_MASK) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL5_MASK (0xC000000U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL5_SHIFT (26U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL5_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL5_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL5_MASK) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL6_MASK (0x30000000U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL6_SHIFT (28U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL6_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL6_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL6_MASK) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL7_MASK (0xC0000000U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL7_SHIFT (30U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL7_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL7_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_GLB_CTRL_UPEN_CTRL7_MASK) /*! @} */ /*! @name TOM1_TGC0_ACT_TB - TOM[i] TGC [g] action time base register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_TGC0_ACT_TB_ACT_TB_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TOM1_TGC0_ACT_TB_ACT_TB_SHIFT (0U) #define GTM_gtm_cls1_TOM1_TGC0_ACT_TB_ACT_TB_WIDTH (24U) #define GTM_gtm_cls1_TOM1_TGC0_ACT_TB_ACT_TB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_ACT_TB_ACT_TB_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_ACT_TB_ACT_TB_MASK) #define GTM_gtm_cls1_TOM1_TGC0_ACT_TB_TB_TRIG_MASK (0x1000000U) #define GTM_gtm_cls1_TOM1_TGC0_ACT_TB_TB_TRIG_SHIFT (24U) #define GTM_gtm_cls1_TOM1_TGC0_ACT_TB_TB_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_TGC0_ACT_TB_TB_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_ACT_TB_TB_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_ACT_TB_TB_TRIG_MASK) #define GTM_gtm_cls1_TOM1_TGC0_ACT_TB_TBU_SEL_MASK (0x6000000U) #define GTM_gtm_cls1_TOM1_TGC0_ACT_TB_TBU_SEL_SHIFT (25U) #define GTM_gtm_cls1_TOM1_TGC0_ACT_TB_TBU_SEL_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_ACT_TB_TBU_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_ACT_TB_TBU_SEL_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_ACT_TB_TBU_SEL_MASK) /*! @} */ /*! @name TOM1_TGC0_FUPD_CTRL - TOM[i] TGC [g] force update control register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL0_MASK (0x3U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL0_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL0_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL0_MASK) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL1_MASK (0xCU) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL1_SHIFT (2U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL1_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL1_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL1_MASK) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL2_MASK (0x30U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL2_SHIFT (4U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL2_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL2_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL2_MASK) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL3_MASK (0xC0U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL3_SHIFT (6U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL3_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL3_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL3_MASK) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL4_MASK (0x300U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL4_SHIFT (8U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL4_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL4_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL4_MASK) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL5_MASK (0xC00U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL5_SHIFT (10U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL5_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL5_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL5_MASK) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL6_MASK (0x3000U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL6_SHIFT (12U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL6_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL6_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL6_MASK) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL7_MASK (0xC000U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL7_SHIFT (14U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL7_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL7_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_FUPD_CTRL7_MASK) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH0_MASK (0x30000U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH0_SHIFT (16U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH0_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH0_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH0_MASK) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH1_MASK (0xC0000U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH1_SHIFT (18U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH1_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH1_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH1_MASK) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH2_MASK (0x300000U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH2_SHIFT (20U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH2_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH2_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH2_MASK) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH3_MASK (0xC00000U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH3_SHIFT (22U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH3_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH3_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH3_MASK) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH4_MASK (0x3000000U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH4_SHIFT (24U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH4_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH4_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH4_MASK) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH5_MASK (0xC000000U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH5_SHIFT (26U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH5_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH5_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH5_MASK) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH6_MASK (0x30000000U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH6_SHIFT (28U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH6_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH6_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH6_MASK) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH7_MASK (0xC0000000U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH7_SHIFT (30U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH7_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH7_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_FUPD_CTRL_RSTCN0_CH7_MASK) /*! @} */ /*! @name TOM1_TGC0_INT_TRIG - TOM[i] TGC [g] internal trigger control register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG0_MASK (0x3U) #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG0_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG0_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG0_MASK) #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG1_MASK (0xCU) #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG1_SHIFT (2U) #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG1_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG1_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG1_MASK) #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG2_MASK (0x30U) #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG2_SHIFT (4U) #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG2_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG2_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG2_MASK) #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG3_MASK (0xC0U) #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG3_SHIFT (6U) #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG3_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG3_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG3_MASK) #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG4_MASK (0x300U) #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG4_SHIFT (8U) #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG4_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG4_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG4_MASK) #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG5_MASK (0xC00U) #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG5_SHIFT (10U) #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG5_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG5_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG5_MASK) #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG6_MASK (0x3000U) #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG6_SHIFT (12U) #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG6_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG6_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG6_MASK) #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG7_MASK (0xC000U) #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG7_SHIFT (14U) #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG7_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG7_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_INT_TRIG_INT_TRIG7_MASK) /*! @} */ /*! @name TOM1_TGC0_ENDIS_CTRL - TOM[i] TGC [g] enable/disable control register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL0_MASK (0x3U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL0_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL0_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL0_MASK) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL1_MASK (0xCU) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL1_SHIFT (2U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL1_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL1_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL1_MASK) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL2_MASK (0x30U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL2_SHIFT (4U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL2_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL2_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL2_MASK) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL3_MASK (0xC0U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL3_SHIFT (6U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL3_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL3_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL3_MASK) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL4_MASK (0x300U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL4_SHIFT (8U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL4_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL4_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL4_MASK) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL5_MASK (0xC00U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL5_SHIFT (10U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL5_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL5_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL5_MASK) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL6_MASK (0x3000U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL6_SHIFT (12U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL6_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL6_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL6_MASK) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL7_MASK (0xC000U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL7_SHIFT (14U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL7_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL7_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_ENDIS_CTRL_ENDIS_CTRL7_MASK) /*! @} */ /*! @name TOM1_TGC0_ENDIS_STAT - TOM[i] TGC [g] enable/disable status register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT0_MASK (0x3U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT0_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT0_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT0_MASK) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT1_MASK (0xCU) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT1_SHIFT (2U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT1_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT1_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT1_MASK) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT2_MASK (0x30U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT2_SHIFT (4U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT2_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT2_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT2_MASK) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT3_MASK (0xC0U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT3_SHIFT (6U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT3_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT3_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT3_MASK) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT4_MASK (0x300U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT4_SHIFT (8U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT4_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT4_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT4_MASK) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT5_MASK (0xC00U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT5_SHIFT (10U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT5_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT5_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT5_MASK) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT6_MASK (0x3000U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT6_SHIFT (12U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT6_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT6_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT6_MASK) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT7_MASK (0xC000U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT7_SHIFT (14U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT7_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT7_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_ENDIS_STAT_ENDIS_STAT7_MASK) /*! @} */ /*! @name TOM1_TGC0_OUTEN_CTRL - TOM[i] TGC [g] output enable control register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL0_MASK (0x3U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL0_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL0_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL0_MASK) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL1_MASK (0xCU) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL1_SHIFT (2U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL1_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL1_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL1_MASK) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL2_MASK (0x30U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL2_SHIFT (4U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL2_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL2_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL2_MASK) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL3_MASK (0xC0U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL3_SHIFT (6U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL3_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL3_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL3_MASK) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL4_MASK (0x300U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL4_SHIFT (8U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL4_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL4_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL4_MASK) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL5_MASK (0xC00U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL5_SHIFT (10U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL5_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL5_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL5_MASK) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL6_MASK (0x3000U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL6_SHIFT (12U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL6_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL6_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL6_MASK) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL7_MASK (0xC000U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL7_SHIFT (14U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL7_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL7_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_OUTEN_CTRL_OUTEN_CTRL7_MASK) /*! @} */ /*! @name TOM1_TGC0_OUTEN_STAT - TOM[i] TGC [g] output enable status register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT0_MASK (0x3U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT0_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT0_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT0_MASK) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT1_MASK (0xCU) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT1_SHIFT (2U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT1_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT1_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT1_MASK) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT2_MASK (0x30U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT2_SHIFT (4U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT2_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT2_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT2_MASK) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT3_MASK (0xC0U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT3_SHIFT (6U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT3_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT3_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT3_MASK) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT4_MASK (0x300U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT4_SHIFT (8U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT4_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT4_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT4_MASK) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT5_MASK (0xC00U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT5_SHIFT (10U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT5_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT5_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT5_MASK) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT6_MASK (0x3000U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT6_SHIFT (12U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT6_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT6_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT6_MASK) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT7_MASK (0xC000U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT7_SHIFT (14U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT7_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT7_SHIFT)) & GTM_gtm_cls1_TOM1_TGC0_OUTEN_STAT_OUTEN_STAT7_MASK) /*! @} */ /*! @name TOM1_TGC1_GLB_CTRL - TOM[i] TGC [g] global control register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_HOST_TRIG_MASK (0x1U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_HOST_TRIG_SHIFT (0U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_HOST_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_HOST_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_HOST_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_HOST_TRIG_MASK) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH0_MASK (0x100U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH0_SHIFT (8U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH0_WIDTH (1U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH0_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH0_MASK) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH1_MASK (0x200U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH1_SHIFT (9U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH1_WIDTH (1U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH1_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH1_MASK) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH2_MASK (0x400U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH2_SHIFT (10U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH2_WIDTH (1U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH2_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH2_MASK) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH3_MASK (0x800U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH3_SHIFT (11U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH3_WIDTH (1U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH3_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH3_MASK) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH4_MASK (0x1000U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH4_SHIFT (12U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH4_WIDTH (1U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH4_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH4_MASK) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH5_MASK (0x2000U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH5_SHIFT (13U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH5_WIDTH (1U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH5_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH5_MASK) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH6_MASK (0x4000U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH6_SHIFT (14U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH6_WIDTH (1U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH6_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH6_MASK) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH7_MASK (0x8000U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH7_SHIFT (15U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH7_WIDTH (1U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH7_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_RST_CH7_MASK) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL0_MASK (0x30000U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL0_SHIFT (16U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL0_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL0_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL0_MASK) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL1_MASK (0xC0000U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL1_SHIFT (18U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL1_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL1_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL1_MASK) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL2_MASK (0x300000U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL2_SHIFT (20U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL2_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL2_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL2_MASK) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL3_MASK (0xC00000U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL3_SHIFT (22U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL3_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL3_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL3_MASK) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL4_MASK (0x3000000U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL4_SHIFT (24U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL4_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL4_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL4_MASK) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL5_MASK (0xC000000U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL5_SHIFT (26U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL5_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL5_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL5_MASK) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL6_MASK (0x30000000U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL6_SHIFT (28U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL6_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL6_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL6_MASK) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL7_MASK (0xC0000000U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL7_SHIFT (30U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL7_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL7_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_GLB_CTRL_UPEN_CTRL7_MASK) /*! @} */ /*! @name TOM1_TGC1_ACT_TB - TOM[i] TGC [g] action time base register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_TGC1_ACT_TB_ACT_TB_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TOM1_TGC1_ACT_TB_ACT_TB_SHIFT (0U) #define GTM_gtm_cls1_TOM1_TGC1_ACT_TB_ACT_TB_WIDTH (24U) #define GTM_gtm_cls1_TOM1_TGC1_ACT_TB_ACT_TB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_ACT_TB_ACT_TB_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_ACT_TB_ACT_TB_MASK) #define GTM_gtm_cls1_TOM1_TGC1_ACT_TB_TB_TRIG_MASK (0x1000000U) #define GTM_gtm_cls1_TOM1_TGC1_ACT_TB_TB_TRIG_SHIFT (24U) #define GTM_gtm_cls1_TOM1_TGC1_ACT_TB_TB_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TOM1_TGC1_ACT_TB_TB_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_ACT_TB_TB_TRIG_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_ACT_TB_TB_TRIG_MASK) #define GTM_gtm_cls1_TOM1_TGC1_ACT_TB_TBU_SEL_MASK (0x6000000U) #define GTM_gtm_cls1_TOM1_TGC1_ACT_TB_TBU_SEL_SHIFT (25U) #define GTM_gtm_cls1_TOM1_TGC1_ACT_TB_TBU_SEL_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_ACT_TB_TBU_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_ACT_TB_TBU_SEL_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_ACT_TB_TBU_SEL_MASK) /*! @} */ /*! @name TOM1_TGC1_FUPD_CTRL - TOM[i] TGC [g] force update control register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL0_MASK (0x3U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL0_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL0_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL0_MASK) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL1_MASK (0xCU) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL1_SHIFT (2U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL1_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL1_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL1_MASK) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL2_MASK (0x30U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL2_SHIFT (4U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL2_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL2_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL2_MASK) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL3_MASK (0xC0U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL3_SHIFT (6U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL3_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL3_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL3_MASK) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL4_MASK (0x300U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL4_SHIFT (8U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL4_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL4_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL4_MASK) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL5_MASK (0xC00U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL5_SHIFT (10U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL5_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL5_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL5_MASK) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL6_MASK (0x3000U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL6_SHIFT (12U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL6_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL6_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL6_MASK) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL7_MASK (0xC000U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL7_SHIFT (14U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL7_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL7_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_FUPD_CTRL7_MASK) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH0_MASK (0x30000U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH0_SHIFT (16U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH0_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH0_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH0_MASK) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH1_MASK (0xC0000U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH1_SHIFT (18U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH1_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH1_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH1_MASK) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH2_MASK (0x300000U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH2_SHIFT (20U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH2_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH2_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH2_MASK) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH3_MASK (0xC00000U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH3_SHIFT (22U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH3_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH3_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH3_MASK) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH4_MASK (0x3000000U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH4_SHIFT (24U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH4_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH4_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH4_MASK) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH5_MASK (0xC000000U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH5_SHIFT (26U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH5_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH5_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH5_MASK) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH6_MASK (0x30000000U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH6_SHIFT (28U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH6_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH6_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH6_MASK) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH7_MASK (0xC0000000U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH7_SHIFT (30U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH7_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH7_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_FUPD_CTRL_RSTCN0_CH7_MASK) /*! @} */ /*! @name TOM1_TGC1_INT_TRIG - TOM[i] TGC [g] internal trigger control register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG0_MASK (0x3U) #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG0_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG0_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG0_MASK) #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG1_MASK (0xCU) #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG1_SHIFT (2U) #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG1_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG1_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG1_MASK) #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG2_MASK (0x30U) #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG2_SHIFT (4U) #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG2_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG2_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG2_MASK) #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG3_MASK (0xC0U) #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG3_SHIFT (6U) #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG3_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG3_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG3_MASK) #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG4_MASK (0x300U) #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG4_SHIFT (8U) #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG4_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG4_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG4_MASK) #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG5_MASK (0xC00U) #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG5_SHIFT (10U) #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG5_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG5_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG5_MASK) #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG6_MASK (0x3000U) #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG6_SHIFT (12U) #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG6_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG6_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG6_MASK) #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG7_MASK (0xC000U) #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG7_SHIFT (14U) #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG7_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG7_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_INT_TRIG_INT_TRIG7_MASK) /*! @} */ /*! @name TOM1_TGC1_ENDIS_CTRL - TOM[i] TGC [g] enable/disable control register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL0_MASK (0x3U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL0_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL0_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL0_MASK) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL1_MASK (0xCU) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL1_SHIFT (2U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL1_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL1_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL1_MASK) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL2_MASK (0x30U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL2_SHIFT (4U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL2_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL2_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL2_MASK) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL3_MASK (0xC0U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL3_SHIFT (6U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL3_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL3_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL3_MASK) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL4_MASK (0x300U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL4_SHIFT (8U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL4_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL4_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL4_MASK) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL5_MASK (0xC00U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL5_SHIFT (10U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL5_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL5_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL5_MASK) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL6_MASK (0x3000U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL6_SHIFT (12U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL6_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL6_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL6_MASK) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL7_MASK (0xC000U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL7_SHIFT (14U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL7_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL7_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_ENDIS_CTRL_ENDIS_CTRL7_MASK) /*! @} */ /*! @name TOM1_TGC1_ENDIS_STAT - TOM[i] TGC [g] enable/disable status register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT0_MASK (0x3U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT0_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT0_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT0_MASK) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT1_MASK (0xCU) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT1_SHIFT (2U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT1_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT1_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT1_MASK) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT2_MASK (0x30U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT2_SHIFT (4U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT2_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT2_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT2_MASK) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT3_MASK (0xC0U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT3_SHIFT (6U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT3_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT3_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT3_MASK) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT4_MASK (0x300U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT4_SHIFT (8U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT4_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT4_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT4_MASK) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT5_MASK (0xC00U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT5_SHIFT (10U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT5_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT5_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT5_MASK) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT6_MASK (0x3000U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT6_SHIFT (12U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT6_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT6_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT6_MASK) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT7_MASK (0xC000U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT7_SHIFT (14U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT7_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT7_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_ENDIS_STAT_ENDIS_STAT7_MASK) /*! @} */ /*! @name TOM1_TGC1_OUTEN_CTRL - TOM[i] TGC [g] output enable control register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL0_MASK (0x3U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL0_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL0_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL0_MASK) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL1_MASK (0xCU) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL1_SHIFT (2U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL1_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL1_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL1_MASK) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL2_MASK (0x30U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL2_SHIFT (4U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL2_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL2_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL2_MASK) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL3_MASK (0xC0U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL3_SHIFT (6U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL3_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL3_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL3_MASK) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL4_MASK (0x300U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL4_SHIFT (8U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL4_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL4_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL4_MASK) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL5_MASK (0xC00U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL5_SHIFT (10U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL5_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL5_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL5_MASK) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL6_MASK (0x3000U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL6_SHIFT (12U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL6_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL6_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL6_MASK) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL7_MASK (0xC000U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL7_SHIFT (14U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL7_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL7_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_OUTEN_CTRL_OUTEN_CTRL7_MASK) /*! @} */ /*! @name TOM1_TGC1_OUTEN_STAT - TOM[i] TGC [g] output enable status register */ /*! @{ */ #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT0_MASK (0x3U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT0_SHIFT (0U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT0_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT0_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT0_MASK) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT1_MASK (0xCU) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT1_SHIFT (2U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT1_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT1_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT1_MASK) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT2_MASK (0x30U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT2_SHIFT (4U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT2_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT2_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT2_MASK) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT3_MASK (0xC0U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT3_SHIFT (6U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT3_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT3_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT3_MASK) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT4_MASK (0x300U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT4_SHIFT (8U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT4_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT4_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT4_MASK) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT5_MASK (0xC00U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT5_SHIFT (10U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT5_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT5_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT5_MASK) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT6_MASK (0x3000U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT6_SHIFT (12U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT6_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT6_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT6_MASK) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT7_MASK (0xC000U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT7_SHIFT (14U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT7_WIDTH (2U) #define GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT7_SHIFT)) & GTM_gtm_cls1_TOM1_TGC1_OUTEN_STAT_OUTEN_STAT7_MASK) /*! @} */ /*! @name ATOM1_CH0_RDADDR - ATOM[i] channel[x] ARU read address register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH0_RDADDR_RDADDR0_MASK (0x1FFU) #define GTM_gtm_cls1_ATOM1_CH0_RDADDR_RDADDR0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH0_RDADDR_RDADDR0_WIDTH (9U) #define GTM_gtm_cls1_ATOM1_CH0_RDADDR_RDADDR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_RDADDR_RDADDR0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_RDADDR_RDADDR0_MASK) #define GTM_gtm_cls1_ATOM1_CH0_RDADDR_RDADDR1_MASK (0x1FF0000U) #define GTM_gtm_cls1_ATOM1_CH0_RDADDR_RDADDR1_SHIFT (16U) #define GTM_gtm_cls1_ATOM1_CH0_RDADDR_RDADDR1_WIDTH (9U) #define GTM_gtm_cls1_ATOM1_CH0_RDADDR_RDADDR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_RDADDR_RDADDR1_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_RDADDR_RDADDR1_MASK) /*! @} */ /*! @name ATOM1_CH0_CTRL - ATOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH0_CTRL_MODE_MASK (0x3U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_MODE_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_MODE_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_CTRL_MODE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_CTRL_MODE_MASK) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_TB12_SEL_MASK (0x4U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_TB12_SEL_SHIFT (2U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_TB12_SEL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_TB12_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_CTRL_TB12_SEL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_CTRL_TB12_SEL_MASK) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_ARU_EN_MASK (0x8U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_ARU_EN_SHIFT (3U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_CTRL_ARU_EN_MASK) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_ACB_MASK (0x1F0U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_ACB_SHIFT (4U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_ACB_WIDTH (5U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_ACB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_CTRL_ACB_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_CTRL_ACB_MASK) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_CMP_CTRL_MASK (0x200U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_CMP_CTRL_SHIFT (9U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_CMP_CTRL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_CMP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_CTRL_CMP_CTRL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_CTRL_CMP_CTRL_MASK) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_EUPM_MASK (0x400U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_EUPM_SHIFT (10U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_EUPM_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_EUPM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_CTRL_EUPM_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_CTRL_EUPM_MASK) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_CTRL_SL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_CTRL_SL_MASK) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_WR_REQ_MASK (0x10000U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_WR_REQ_SHIFT (16U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_WR_REQ_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_WR_REQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_CTRL_WR_REQ_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_CTRL_WR_REQ_MASK) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_CTRL_UDMODE_MASK) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_SLA_MASK (0x2000000U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_SLA_SHIFT (25U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_SLA_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_SLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_CTRL_SLA_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_CTRL_SLA_MASK) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_CTRL_OSM_MASK) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_ABM_MASK (0x8000000U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_ABM_SHIFT (27U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_ABM_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_ABM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_CTRL_ABM_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_CTRL_ABM_MASK) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_EXT_FUPD_MASK (0x20000000U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_EXT_FUPD_SHIFT (29U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_EXT_FUPD_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_EXT_FUPD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_CTRL_EXT_FUPD_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_CTRL_EXT_FUPD_MASK) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_SOMB_MASK (0x40000000U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_SOMB_SHIFT (30U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_SOMB_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_SOMB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_CTRL_SOMB_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_CTRL_SOMB_MASK) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_CTRL_FREEZE_MASK) /*! @} */ /*! @name ATOM1_CH0_SR0 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH0_SR0_SR0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH0_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH0_SR0_SR0_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH0_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_SR0_SR0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_SR0_SR0_MASK) /*! @} */ /*! @name ATOM1_CH0_SR1 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH0_SR1_SR1_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH0_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH0_SR1_SR1_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH0_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_SR1_SR1_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_SR1_SR1_MASK) /*! @} */ /*! @name ATOM1_CH0_CM0 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH0_CM0_CM0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH0_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH0_CM0_CM0_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH0_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_CM0_CM0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_CM0_CM0_MASK) /*! @} */ /*! @name ATOM1_CH0_CM1 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH0_CM1_CM1_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH0_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH0_CM1_CM1_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH0_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_CM1_CM1_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_CM1_CM1_MASK) /*! @} */ /*! @name ATOM1_CH0_CN0 - ATOM[i] channel [x] CCU0 counter register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH0_CN0_CN0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH0_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH0_CN0_CN0_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH0_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_CN0_CN0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_CN0_CN0_MASK) /*! @} */ /*! @name ATOM1_CH0_STAT - ATOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH0_STAT_OL_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH0_STAT_OL_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH0_STAT_OL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH0_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_STAT_OL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_STAT_OL_MASK) #define GTM_gtm_cls1_ATOM1_CH0_STAT_ACBI_MASK (0x1F0000U) #define GTM_gtm_cls1_ATOM1_CH0_STAT_ACBI_SHIFT (16U) #define GTM_gtm_cls1_ATOM1_CH0_STAT_ACBI_WIDTH (5U) #define GTM_gtm_cls1_ATOM1_CH0_STAT_ACBI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_STAT_ACBI_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_STAT_ACBI_MASK) #define GTM_gtm_cls1_ATOM1_CH0_STAT_DV_MASK (0x200000U) #define GTM_gtm_cls1_ATOM1_CH0_STAT_DV_SHIFT (21U) #define GTM_gtm_cls1_ATOM1_CH0_STAT_DV_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH0_STAT_DV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_STAT_DV_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_STAT_DV_MASK) #define GTM_gtm_cls1_ATOM1_CH0_STAT_WRF_MASK (0x400000U) #define GTM_gtm_cls1_ATOM1_CH0_STAT_WRF_SHIFT (22U) #define GTM_gtm_cls1_ATOM1_CH0_STAT_WRF_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH0_STAT_WRF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_STAT_WRF_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_STAT_WRF_MASK) #define GTM_gtm_cls1_ATOM1_CH0_STAT_DR_MASK (0x800000U) #define GTM_gtm_cls1_ATOM1_CH0_STAT_DR_SHIFT (23U) #define GTM_gtm_cls1_ATOM1_CH0_STAT_DR_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH0_STAT_DR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_STAT_DR_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_STAT_DR_MASK) #define GTM_gtm_cls1_ATOM1_CH0_STAT_ACBO_MASK (0x1F000000U) #define GTM_gtm_cls1_ATOM1_CH0_STAT_ACBO_SHIFT (24U) #define GTM_gtm_cls1_ATOM1_CH0_STAT_ACBO_WIDTH (5U) #define GTM_gtm_cls1_ATOM1_CH0_STAT_ACBO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_STAT_ACBO_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_STAT_ACBO_MASK) #define GTM_gtm_cls1_ATOM1_CH0_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls1_ATOM1_CH0_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls1_ATOM1_CH0_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH0_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_STAT_OSM_RTF_MASK) /*! @} */ /*! @name ATOM1_CH0_IRQ_NOTIFY - ATOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH0_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH0_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH0_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH0_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls1_ATOM1_CH0_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_ATOM1_CH0_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_ATOM1_CH0_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH0_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name ATOM1_CH0_IRQ_EN - ATOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH0_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH0_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH0_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH0_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls1_ATOM1_CH0_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_ATOM1_CH0_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_ATOM1_CH0_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH0_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name ATOM1_CH0_IRQ_FORCINT - ATOM[i] channel [x] software interrupt generation */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH0_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH0_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH0_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH0_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls1_ATOM1_CH0_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_ATOM1_CH0_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_ATOM1_CH0_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH0_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name ATOM1_CH0_IRQ_MODE - ATOM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH0_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_ATOM1_CH0_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH0_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_CH0_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name ATOM1_CH0_CTRL2 - ATOM[i] channel [x] control2 register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH0_CTRL2_HRES_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL2_HRES_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL2_HRES_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL2_HRES(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_CTRL2_HRES_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_CTRL2_HRES_MASK) /*! @} */ /*! @name ATOM1_CH0_CTRL_SR - ATOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH0_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls1_ATOM1_CH0_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH0_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls1_ATOM1_CH0_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name ATOM1_CH1_RDADDR - ATOM[i] channel[x] ARU read address register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH1_RDADDR_RDADDR0_MASK (0x1FFU) #define GTM_gtm_cls1_ATOM1_CH1_RDADDR_RDADDR0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH1_RDADDR_RDADDR0_WIDTH (9U) #define GTM_gtm_cls1_ATOM1_CH1_RDADDR_RDADDR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_RDADDR_RDADDR0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_RDADDR_RDADDR0_MASK) #define GTM_gtm_cls1_ATOM1_CH1_RDADDR_RDADDR1_MASK (0x1FF0000U) #define GTM_gtm_cls1_ATOM1_CH1_RDADDR_RDADDR1_SHIFT (16U) #define GTM_gtm_cls1_ATOM1_CH1_RDADDR_RDADDR1_WIDTH (9U) #define GTM_gtm_cls1_ATOM1_CH1_RDADDR_RDADDR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_RDADDR_RDADDR1_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_RDADDR_RDADDR1_MASK) /*! @} */ /*! @name ATOM1_CH1_CTRL - ATOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH1_CTRL_MODE_MASK (0x3U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_MODE_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_MODE_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_CTRL_MODE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_CTRL_MODE_MASK) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_TB12_SEL_MASK (0x4U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_TB12_SEL_SHIFT (2U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_TB12_SEL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_TB12_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_CTRL_TB12_SEL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_CTRL_TB12_SEL_MASK) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_ARU_EN_MASK (0x8U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_ARU_EN_SHIFT (3U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_CTRL_ARU_EN_MASK) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_ACB_MASK (0x1F0U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_ACB_SHIFT (4U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_ACB_WIDTH (5U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_ACB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_CTRL_ACB_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_CTRL_ACB_MASK) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_CMP_CTRL_MASK (0x200U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_CMP_CTRL_SHIFT (9U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_CMP_CTRL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_CMP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_CTRL_CMP_CTRL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_CTRL_CMP_CTRL_MASK) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_EUPM_MASK (0x400U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_EUPM_SHIFT (10U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_EUPM_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_EUPM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_CTRL_EUPM_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_CTRL_EUPM_MASK) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_CTRL_SL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_CTRL_SL_MASK) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_WR_REQ_MASK (0x10000U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_WR_REQ_SHIFT (16U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_WR_REQ_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_WR_REQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_CTRL_WR_REQ_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_CTRL_WR_REQ_MASK) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_CTRL_UDMODE_MASK) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_SLA_MASK (0x2000000U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_SLA_SHIFT (25U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_SLA_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_SLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_CTRL_SLA_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_CTRL_SLA_MASK) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_CTRL_OSM_MASK) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_ABM_MASK (0x8000000U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_ABM_SHIFT (27U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_ABM_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_ABM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_CTRL_ABM_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_CTRL_ABM_MASK) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_EXT_FUPD_MASK (0x20000000U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_EXT_FUPD_SHIFT (29U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_EXT_FUPD_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_EXT_FUPD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_CTRL_EXT_FUPD_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_CTRL_EXT_FUPD_MASK) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_SOMB_MASK (0x40000000U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_SOMB_SHIFT (30U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_SOMB_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_SOMB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_CTRL_SOMB_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_CTRL_SOMB_MASK) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_CTRL_FREEZE_MASK) /*! @} */ /*! @name ATOM1_CH1_SR0 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH1_SR0_SR0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH1_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH1_SR0_SR0_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH1_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_SR0_SR0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_SR0_SR0_MASK) /*! @} */ /*! @name ATOM1_CH1_SR1 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH1_SR1_SR1_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH1_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH1_SR1_SR1_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH1_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_SR1_SR1_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_SR1_SR1_MASK) /*! @} */ /*! @name ATOM1_CH1_CM0 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH1_CM0_CM0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH1_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH1_CM0_CM0_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH1_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_CM0_CM0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_CM0_CM0_MASK) /*! @} */ /*! @name ATOM1_CH1_CM1 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH1_CM1_CM1_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH1_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH1_CM1_CM1_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH1_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_CM1_CM1_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_CM1_CM1_MASK) /*! @} */ /*! @name ATOM1_CH1_CN0 - ATOM[i] channel [x] CCU0 counter register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH1_CN0_CN0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH1_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH1_CN0_CN0_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH1_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_CN0_CN0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_CN0_CN0_MASK) /*! @} */ /*! @name ATOM1_CH1_STAT - ATOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH1_STAT_OL_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH1_STAT_OL_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH1_STAT_OL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH1_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_STAT_OL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_STAT_OL_MASK) #define GTM_gtm_cls1_ATOM1_CH1_STAT_ACBI_MASK (0x1F0000U) #define GTM_gtm_cls1_ATOM1_CH1_STAT_ACBI_SHIFT (16U) #define GTM_gtm_cls1_ATOM1_CH1_STAT_ACBI_WIDTH (5U) #define GTM_gtm_cls1_ATOM1_CH1_STAT_ACBI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_STAT_ACBI_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_STAT_ACBI_MASK) #define GTM_gtm_cls1_ATOM1_CH1_STAT_DV_MASK (0x200000U) #define GTM_gtm_cls1_ATOM1_CH1_STAT_DV_SHIFT (21U) #define GTM_gtm_cls1_ATOM1_CH1_STAT_DV_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH1_STAT_DV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_STAT_DV_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_STAT_DV_MASK) #define GTM_gtm_cls1_ATOM1_CH1_STAT_WRF_MASK (0x400000U) #define GTM_gtm_cls1_ATOM1_CH1_STAT_WRF_SHIFT (22U) #define GTM_gtm_cls1_ATOM1_CH1_STAT_WRF_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH1_STAT_WRF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_STAT_WRF_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_STAT_WRF_MASK) #define GTM_gtm_cls1_ATOM1_CH1_STAT_DR_MASK (0x800000U) #define GTM_gtm_cls1_ATOM1_CH1_STAT_DR_SHIFT (23U) #define GTM_gtm_cls1_ATOM1_CH1_STAT_DR_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH1_STAT_DR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_STAT_DR_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_STAT_DR_MASK) #define GTM_gtm_cls1_ATOM1_CH1_STAT_ACBO_MASK (0x1F000000U) #define GTM_gtm_cls1_ATOM1_CH1_STAT_ACBO_SHIFT (24U) #define GTM_gtm_cls1_ATOM1_CH1_STAT_ACBO_WIDTH (5U) #define GTM_gtm_cls1_ATOM1_CH1_STAT_ACBO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_STAT_ACBO_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_STAT_ACBO_MASK) #define GTM_gtm_cls1_ATOM1_CH1_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls1_ATOM1_CH1_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls1_ATOM1_CH1_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH1_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_STAT_OSM_RTF_MASK) /*! @} */ /*! @name ATOM1_CH1_IRQ_NOTIFY - ATOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH1_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH1_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH1_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH1_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls1_ATOM1_CH1_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_ATOM1_CH1_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_ATOM1_CH1_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH1_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name ATOM1_CH1_IRQ_EN - ATOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH1_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH1_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH1_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH1_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls1_ATOM1_CH1_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_ATOM1_CH1_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_ATOM1_CH1_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH1_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name ATOM1_CH1_IRQ_FORCINT - ATOM[i] channel [x] software interrupt generation */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH1_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH1_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH1_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH1_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls1_ATOM1_CH1_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_ATOM1_CH1_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_ATOM1_CH1_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH1_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name ATOM1_CH1_IRQ_MODE - ATOM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH1_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_ATOM1_CH1_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH1_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_CH1_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name ATOM1_CH1_CTRL2 - ATOM[i] channel [x] control2 register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH1_CTRL2_HRES_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL2_HRES_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL2_HRES_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL2_HRES(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_CTRL2_HRES_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_CTRL2_HRES_MASK) /*! @} */ /*! @name ATOM1_CH1_CTRL_SR - ATOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH1_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls1_ATOM1_CH1_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH1_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls1_ATOM1_CH1_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name ATOM1_CH2_RDADDR - ATOM[i] channel[x] ARU read address register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH2_RDADDR_RDADDR0_MASK (0x1FFU) #define GTM_gtm_cls1_ATOM1_CH2_RDADDR_RDADDR0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH2_RDADDR_RDADDR0_WIDTH (9U) #define GTM_gtm_cls1_ATOM1_CH2_RDADDR_RDADDR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_RDADDR_RDADDR0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_RDADDR_RDADDR0_MASK) #define GTM_gtm_cls1_ATOM1_CH2_RDADDR_RDADDR1_MASK (0x1FF0000U) #define GTM_gtm_cls1_ATOM1_CH2_RDADDR_RDADDR1_SHIFT (16U) #define GTM_gtm_cls1_ATOM1_CH2_RDADDR_RDADDR1_WIDTH (9U) #define GTM_gtm_cls1_ATOM1_CH2_RDADDR_RDADDR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_RDADDR_RDADDR1_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_RDADDR_RDADDR1_MASK) /*! @} */ /*! @name ATOM1_CH2_CTRL - ATOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH2_CTRL_MODE_MASK (0x3U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_MODE_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_MODE_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_CTRL_MODE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_CTRL_MODE_MASK) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_TB12_SEL_MASK (0x4U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_TB12_SEL_SHIFT (2U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_TB12_SEL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_TB12_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_CTRL_TB12_SEL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_CTRL_TB12_SEL_MASK) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_ARU_EN_MASK (0x8U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_ARU_EN_SHIFT (3U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_CTRL_ARU_EN_MASK) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_ACB_MASK (0x1F0U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_ACB_SHIFT (4U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_ACB_WIDTH (5U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_ACB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_CTRL_ACB_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_CTRL_ACB_MASK) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_CMP_CTRL_MASK (0x200U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_CMP_CTRL_SHIFT (9U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_CMP_CTRL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_CMP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_CTRL_CMP_CTRL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_CTRL_CMP_CTRL_MASK) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_EUPM_MASK (0x400U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_EUPM_SHIFT (10U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_EUPM_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_EUPM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_CTRL_EUPM_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_CTRL_EUPM_MASK) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_CTRL_SL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_CTRL_SL_MASK) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_WR_REQ_MASK (0x10000U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_WR_REQ_SHIFT (16U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_WR_REQ_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_WR_REQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_CTRL_WR_REQ_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_CTRL_WR_REQ_MASK) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_CTRL_UDMODE_MASK) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_SLA_MASK (0x2000000U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_SLA_SHIFT (25U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_SLA_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_SLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_CTRL_SLA_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_CTRL_SLA_MASK) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_CTRL_OSM_MASK) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_ABM_MASK (0x8000000U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_ABM_SHIFT (27U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_ABM_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_ABM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_CTRL_ABM_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_CTRL_ABM_MASK) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_EXT_FUPD_MASK (0x20000000U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_EXT_FUPD_SHIFT (29U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_EXT_FUPD_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_EXT_FUPD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_CTRL_EXT_FUPD_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_CTRL_EXT_FUPD_MASK) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_SOMB_MASK (0x40000000U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_SOMB_SHIFT (30U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_SOMB_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_SOMB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_CTRL_SOMB_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_CTRL_SOMB_MASK) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_CTRL_FREEZE_MASK) /*! @} */ /*! @name ATOM1_CH2_SR0 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH2_SR0_SR0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH2_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH2_SR0_SR0_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH2_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_SR0_SR0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_SR0_SR0_MASK) /*! @} */ /*! @name ATOM1_CH2_SR1 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH2_SR1_SR1_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH2_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH2_SR1_SR1_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH2_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_SR1_SR1_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_SR1_SR1_MASK) /*! @} */ /*! @name ATOM1_CH2_CM0 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH2_CM0_CM0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH2_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH2_CM0_CM0_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH2_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_CM0_CM0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_CM0_CM0_MASK) /*! @} */ /*! @name ATOM1_CH2_CM1 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH2_CM1_CM1_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH2_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH2_CM1_CM1_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH2_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_CM1_CM1_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_CM1_CM1_MASK) /*! @} */ /*! @name ATOM1_CH2_CN0 - ATOM[i] channel [x] CCU0 counter register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH2_CN0_CN0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH2_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH2_CN0_CN0_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH2_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_CN0_CN0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_CN0_CN0_MASK) /*! @} */ /*! @name ATOM1_CH2_STAT - ATOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH2_STAT_OL_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH2_STAT_OL_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH2_STAT_OL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH2_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_STAT_OL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_STAT_OL_MASK) #define GTM_gtm_cls1_ATOM1_CH2_STAT_ACBI_MASK (0x1F0000U) #define GTM_gtm_cls1_ATOM1_CH2_STAT_ACBI_SHIFT (16U) #define GTM_gtm_cls1_ATOM1_CH2_STAT_ACBI_WIDTH (5U) #define GTM_gtm_cls1_ATOM1_CH2_STAT_ACBI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_STAT_ACBI_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_STAT_ACBI_MASK) #define GTM_gtm_cls1_ATOM1_CH2_STAT_DV_MASK (0x200000U) #define GTM_gtm_cls1_ATOM1_CH2_STAT_DV_SHIFT (21U) #define GTM_gtm_cls1_ATOM1_CH2_STAT_DV_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH2_STAT_DV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_STAT_DV_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_STAT_DV_MASK) #define GTM_gtm_cls1_ATOM1_CH2_STAT_WRF_MASK (0x400000U) #define GTM_gtm_cls1_ATOM1_CH2_STAT_WRF_SHIFT (22U) #define GTM_gtm_cls1_ATOM1_CH2_STAT_WRF_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH2_STAT_WRF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_STAT_WRF_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_STAT_WRF_MASK) #define GTM_gtm_cls1_ATOM1_CH2_STAT_DR_MASK (0x800000U) #define GTM_gtm_cls1_ATOM1_CH2_STAT_DR_SHIFT (23U) #define GTM_gtm_cls1_ATOM1_CH2_STAT_DR_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH2_STAT_DR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_STAT_DR_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_STAT_DR_MASK) #define GTM_gtm_cls1_ATOM1_CH2_STAT_ACBO_MASK (0x1F000000U) #define GTM_gtm_cls1_ATOM1_CH2_STAT_ACBO_SHIFT (24U) #define GTM_gtm_cls1_ATOM1_CH2_STAT_ACBO_WIDTH (5U) #define GTM_gtm_cls1_ATOM1_CH2_STAT_ACBO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_STAT_ACBO_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_STAT_ACBO_MASK) #define GTM_gtm_cls1_ATOM1_CH2_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls1_ATOM1_CH2_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls1_ATOM1_CH2_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH2_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_STAT_OSM_RTF_MASK) /*! @} */ /*! @name ATOM1_CH2_IRQ_NOTIFY - ATOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH2_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH2_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH2_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH2_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls1_ATOM1_CH2_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_ATOM1_CH2_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_ATOM1_CH2_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH2_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name ATOM1_CH2_IRQ_EN - ATOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH2_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH2_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH2_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH2_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls1_ATOM1_CH2_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_ATOM1_CH2_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_ATOM1_CH2_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH2_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name ATOM1_CH2_IRQ_FORCINT - ATOM[i] channel [x] software interrupt generation */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH2_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH2_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH2_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH2_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls1_ATOM1_CH2_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_ATOM1_CH2_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_ATOM1_CH2_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH2_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name ATOM1_CH2_IRQ_MODE - ATOM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH2_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_ATOM1_CH2_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH2_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_CH2_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name ATOM1_CH2_CTRL2 - ATOM[i] channel [x] control2 register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH2_CTRL2_HRES_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL2_HRES_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL2_HRES_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL2_HRES(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_CTRL2_HRES_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_CTRL2_HRES_MASK) /*! @} */ /*! @name ATOM1_CH2_CTRL_SR - ATOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH2_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls1_ATOM1_CH2_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH2_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls1_ATOM1_CH2_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name ATOM1_CH3_RDADDR - ATOM[i] channel[x] ARU read address register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH3_RDADDR_RDADDR0_MASK (0x1FFU) #define GTM_gtm_cls1_ATOM1_CH3_RDADDR_RDADDR0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH3_RDADDR_RDADDR0_WIDTH (9U) #define GTM_gtm_cls1_ATOM1_CH3_RDADDR_RDADDR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_RDADDR_RDADDR0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_RDADDR_RDADDR0_MASK) #define GTM_gtm_cls1_ATOM1_CH3_RDADDR_RDADDR1_MASK (0x1FF0000U) #define GTM_gtm_cls1_ATOM1_CH3_RDADDR_RDADDR1_SHIFT (16U) #define GTM_gtm_cls1_ATOM1_CH3_RDADDR_RDADDR1_WIDTH (9U) #define GTM_gtm_cls1_ATOM1_CH3_RDADDR_RDADDR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_RDADDR_RDADDR1_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_RDADDR_RDADDR1_MASK) /*! @} */ /*! @name ATOM1_CH3_CTRL - ATOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH3_CTRL_MODE_MASK (0x3U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_MODE_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_MODE_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_CTRL_MODE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_CTRL_MODE_MASK) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_TB12_SEL_MASK (0x4U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_TB12_SEL_SHIFT (2U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_TB12_SEL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_TB12_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_CTRL_TB12_SEL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_CTRL_TB12_SEL_MASK) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_ARU_EN_MASK (0x8U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_ARU_EN_SHIFT (3U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_CTRL_ARU_EN_MASK) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_ACB_MASK (0x1F0U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_ACB_SHIFT (4U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_ACB_WIDTH (5U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_ACB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_CTRL_ACB_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_CTRL_ACB_MASK) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_CMP_CTRL_MASK (0x200U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_CMP_CTRL_SHIFT (9U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_CMP_CTRL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_CMP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_CTRL_CMP_CTRL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_CTRL_CMP_CTRL_MASK) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_EUPM_MASK (0x400U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_EUPM_SHIFT (10U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_EUPM_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_EUPM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_CTRL_EUPM_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_CTRL_EUPM_MASK) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_CTRL_SL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_CTRL_SL_MASK) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_WR_REQ_MASK (0x10000U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_WR_REQ_SHIFT (16U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_WR_REQ_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_WR_REQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_CTRL_WR_REQ_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_CTRL_WR_REQ_MASK) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_CTRL_UDMODE_MASK) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_SLA_MASK (0x2000000U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_SLA_SHIFT (25U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_SLA_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_SLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_CTRL_SLA_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_CTRL_SLA_MASK) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_CTRL_OSM_MASK) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_ABM_MASK (0x8000000U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_ABM_SHIFT (27U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_ABM_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_ABM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_CTRL_ABM_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_CTRL_ABM_MASK) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_EXT_FUPD_MASK (0x20000000U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_EXT_FUPD_SHIFT (29U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_EXT_FUPD_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_EXT_FUPD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_CTRL_EXT_FUPD_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_CTRL_EXT_FUPD_MASK) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_SOMB_MASK (0x40000000U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_SOMB_SHIFT (30U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_SOMB_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_SOMB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_CTRL_SOMB_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_CTRL_SOMB_MASK) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_CTRL_FREEZE_MASK) /*! @} */ /*! @name ATOM1_CH3_SR0 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH3_SR0_SR0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH3_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH3_SR0_SR0_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH3_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_SR0_SR0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_SR0_SR0_MASK) /*! @} */ /*! @name ATOM1_CH3_SR1 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH3_SR1_SR1_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH3_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH3_SR1_SR1_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH3_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_SR1_SR1_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_SR1_SR1_MASK) /*! @} */ /*! @name ATOM1_CH3_CM0 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH3_CM0_CM0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH3_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH3_CM0_CM0_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH3_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_CM0_CM0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_CM0_CM0_MASK) /*! @} */ /*! @name ATOM1_CH3_CM1 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH3_CM1_CM1_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH3_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH3_CM1_CM1_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH3_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_CM1_CM1_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_CM1_CM1_MASK) /*! @} */ /*! @name ATOM1_CH3_CN0 - ATOM[i] channel [x] CCU0 counter register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH3_CN0_CN0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH3_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH3_CN0_CN0_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH3_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_CN0_CN0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_CN0_CN0_MASK) /*! @} */ /*! @name ATOM1_CH3_STAT - ATOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH3_STAT_OL_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH3_STAT_OL_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH3_STAT_OL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH3_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_STAT_OL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_STAT_OL_MASK) #define GTM_gtm_cls1_ATOM1_CH3_STAT_ACBI_MASK (0x1F0000U) #define GTM_gtm_cls1_ATOM1_CH3_STAT_ACBI_SHIFT (16U) #define GTM_gtm_cls1_ATOM1_CH3_STAT_ACBI_WIDTH (5U) #define GTM_gtm_cls1_ATOM1_CH3_STAT_ACBI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_STAT_ACBI_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_STAT_ACBI_MASK) #define GTM_gtm_cls1_ATOM1_CH3_STAT_DV_MASK (0x200000U) #define GTM_gtm_cls1_ATOM1_CH3_STAT_DV_SHIFT (21U) #define GTM_gtm_cls1_ATOM1_CH3_STAT_DV_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH3_STAT_DV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_STAT_DV_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_STAT_DV_MASK) #define GTM_gtm_cls1_ATOM1_CH3_STAT_WRF_MASK (0x400000U) #define GTM_gtm_cls1_ATOM1_CH3_STAT_WRF_SHIFT (22U) #define GTM_gtm_cls1_ATOM1_CH3_STAT_WRF_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH3_STAT_WRF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_STAT_WRF_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_STAT_WRF_MASK) #define GTM_gtm_cls1_ATOM1_CH3_STAT_DR_MASK (0x800000U) #define GTM_gtm_cls1_ATOM1_CH3_STAT_DR_SHIFT (23U) #define GTM_gtm_cls1_ATOM1_CH3_STAT_DR_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH3_STAT_DR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_STAT_DR_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_STAT_DR_MASK) #define GTM_gtm_cls1_ATOM1_CH3_STAT_ACBO_MASK (0x1F000000U) #define GTM_gtm_cls1_ATOM1_CH3_STAT_ACBO_SHIFT (24U) #define GTM_gtm_cls1_ATOM1_CH3_STAT_ACBO_WIDTH (5U) #define GTM_gtm_cls1_ATOM1_CH3_STAT_ACBO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_STAT_ACBO_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_STAT_ACBO_MASK) #define GTM_gtm_cls1_ATOM1_CH3_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls1_ATOM1_CH3_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls1_ATOM1_CH3_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH3_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_STAT_OSM_RTF_MASK) /*! @} */ /*! @name ATOM1_CH3_IRQ_NOTIFY - ATOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH3_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH3_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH3_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH3_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls1_ATOM1_CH3_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_ATOM1_CH3_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_ATOM1_CH3_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH3_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name ATOM1_CH3_IRQ_EN - ATOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH3_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH3_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH3_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH3_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls1_ATOM1_CH3_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_ATOM1_CH3_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_ATOM1_CH3_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH3_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name ATOM1_CH3_IRQ_FORCINT - ATOM[i] channel [x] software interrupt generation */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH3_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH3_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH3_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH3_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls1_ATOM1_CH3_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_ATOM1_CH3_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_ATOM1_CH3_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH3_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name ATOM1_CH3_IRQ_MODE - ATOM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH3_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_ATOM1_CH3_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH3_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_CH3_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name ATOM1_CH3_CTRL2 - ATOM[i] channel [x] control2 register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH3_CTRL2_HRES_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL2_HRES_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL2_HRES_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL2_HRES(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_CTRL2_HRES_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_CTRL2_HRES_MASK) /*! @} */ /*! @name ATOM1_CH3_CTRL_SR - ATOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH3_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls1_ATOM1_CH3_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH3_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls1_ATOM1_CH3_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name ATOM1_CH4_RDADDR - ATOM[i] channel[x] ARU read address register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH4_RDADDR_RDADDR0_MASK (0x1FFU) #define GTM_gtm_cls1_ATOM1_CH4_RDADDR_RDADDR0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH4_RDADDR_RDADDR0_WIDTH (9U) #define GTM_gtm_cls1_ATOM1_CH4_RDADDR_RDADDR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_RDADDR_RDADDR0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_RDADDR_RDADDR0_MASK) #define GTM_gtm_cls1_ATOM1_CH4_RDADDR_RDADDR1_MASK (0x1FF0000U) #define GTM_gtm_cls1_ATOM1_CH4_RDADDR_RDADDR1_SHIFT (16U) #define GTM_gtm_cls1_ATOM1_CH4_RDADDR_RDADDR1_WIDTH (9U) #define GTM_gtm_cls1_ATOM1_CH4_RDADDR_RDADDR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_RDADDR_RDADDR1_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_RDADDR_RDADDR1_MASK) /*! @} */ /*! @name ATOM1_CH4_CTRL - ATOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH4_CTRL_MODE_MASK (0x3U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_MODE_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_MODE_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_CTRL_MODE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_CTRL_MODE_MASK) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_TB12_SEL_MASK (0x4U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_TB12_SEL_SHIFT (2U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_TB12_SEL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_TB12_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_CTRL_TB12_SEL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_CTRL_TB12_SEL_MASK) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_ARU_EN_MASK (0x8U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_ARU_EN_SHIFT (3U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_CTRL_ARU_EN_MASK) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_ACB_MASK (0x1F0U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_ACB_SHIFT (4U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_ACB_WIDTH (5U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_ACB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_CTRL_ACB_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_CTRL_ACB_MASK) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_CMP_CTRL_MASK (0x200U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_CMP_CTRL_SHIFT (9U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_CMP_CTRL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_CMP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_CTRL_CMP_CTRL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_CTRL_CMP_CTRL_MASK) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_EUPM_MASK (0x400U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_EUPM_SHIFT (10U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_EUPM_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_EUPM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_CTRL_EUPM_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_CTRL_EUPM_MASK) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_CTRL_SL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_CTRL_SL_MASK) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_WR_REQ_MASK (0x10000U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_WR_REQ_SHIFT (16U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_WR_REQ_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_WR_REQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_CTRL_WR_REQ_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_CTRL_WR_REQ_MASK) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_CTRL_UDMODE_MASK) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_SLA_MASK (0x2000000U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_SLA_SHIFT (25U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_SLA_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_SLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_CTRL_SLA_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_CTRL_SLA_MASK) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_CTRL_OSM_MASK) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_ABM_MASK (0x8000000U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_ABM_SHIFT (27U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_ABM_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_ABM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_CTRL_ABM_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_CTRL_ABM_MASK) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_EXT_FUPD_MASK (0x20000000U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_EXT_FUPD_SHIFT (29U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_EXT_FUPD_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_EXT_FUPD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_CTRL_EXT_FUPD_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_CTRL_EXT_FUPD_MASK) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_SOMB_MASK (0x40000000U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_SOMB_SHIFT (30U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_SOMB_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_SOMB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_CTRL_SOMB_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_CTRL_SOMB_MASK) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_CTRL_FREEZE_MASK) /*! @} */ /*! @name ATOM1_CH4_SR0 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH4_SR0_SR0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH4_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH4_SR0_SR0_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH4_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_SR0_SR0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_SR0_SR0_MASK) /*! @} */ /*! @name ATOM1_CH4_SR1 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH4_SR1_SR1_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH4_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH4_SR1_SR1_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH4_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_SR1_SR1_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_SR1_SR1_MASK) /*! @} */ /*! @name ATOM1_CH4_CM0 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH4_CM0_CM0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH4_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH4_CM0_CM0_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH4_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_CM0_CM0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_CM0_CM0_MASK) /*! @} */ /*! @name ATOM1_CH4_CM1 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH4_CM1_CM1_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH4_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH4_CM1_CM1_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH4_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_CM1_CM1_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_CM1_CM1_MASK) /*! @} */ /*! @name ATOM1_CH4_CN0 - ATOM[i] channel [x] CCU0 counter register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH4_CN0_CN0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH4_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH4_CN0_CN0_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH4_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_CN0_CN0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_CN0_CN0_MASK) /*! @} */ /*! @name ATOM1_CH4_STAT - ATOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH4_STAT_OL_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH4_STAT_OL_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH4_STAT_OL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH4_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_STAT_OL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_STAT_OL_MASK) #define GTM_gtm_cls1_ATOM1_CH4_STAT_ACBI_MASK (0x1F0000U) #define GTM_gtm_cls1_ATOM1_CH4_STAT_ACBI_SHIFT (16U) #define GTM_gtm_cls1_ATOM1_CH4_STAT_ACBI_WIDTH (5U) #define GTM_gtm_cls1_ATOM1_CH4_STAT_ACBI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_STAT_ACBI_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_STAT_ACBI_MASK) #define GTM_gtm_cls1_ATOM1_CH4_STAT_DV_MASK (0x200000U) #define GTM_gtm_cls1_ATOM1_CH4_STAT_DV_SHIFT (21U) #define GTM_gtm_cls1_ATOM1_CH4_STAT_DV_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH4_STAT_DV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_STAT_DV_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_STAT_DV_MASK) #define GTM_gtm_cls1_ATOM1_CH4_STAT_WRF_MASK (0x400000U) #define GTM_gtm_cls1_ATOM1_CH4_STAT_WRF_SHIFT (22U) #define GTM_gtm_cls1_ATOM1_CH4_STAT_WRF_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH4_STAT_WRF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_STAT_WRF_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_STAT_WRF_MASK) #define GTM_gtm_cls1_ATOM1_CH4_STAT_DR_MASK (0x800000U) #define GTM_gtm_cls1_ATOM1_CH4_STAT_DR_SHIFT (23U) #define GTM_gtm_cls1_ATOM1_CH4_STAT_DR_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH4_STAT_DR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_STAT_DR_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_STAT_DR_MASK) #define GTM_gtm_cls1_ATOM1_CH4_STAT_ACBO_MASK (0x1F000000U) #define GTM_gtm_cls1_ATOM1_CH4_STAT_ACBO_SHIFT (24U) #define GTM_gtm_cls1_ATOM1_CH4_STAT_ACBO_WIDTH (5U) #define GTM_gtm_cls1_ATOM1_CH4_STAT_ACBO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_STAT_ACBO_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_STAT_ACBO_MASK) #define GTM_gtm_cls1_ATOM1_CH4_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls1_ATOM1_CH4_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls1_ATOM1_CH4_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH4_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_STAT_OSM_RTF_MASK) /*! @} */ /*! @name ATOM1_CH4_IRQ_NOTIFY - ATOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH4_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH4_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH4_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH4_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls1_ATOM1_CH4_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_ATOM1_CH4_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_ATOM1_CH4_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH4_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name ATOM1_CH4_IRQ_EN - ATOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH4_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH4_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH4_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH4_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls1_ATOM1_CH4_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_ATOM1_CH4_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_ATOM1_CH4_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH4_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name ATOM1_CH4_IRQ_FORCINT - ATOM[i] channel [x] software interrupt generation */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH4_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH4_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH4_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH4_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls1_ATOM1_CH4_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_ATOM1_CH4_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_ATOM1_CH4_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH4_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name ATOM1_CH4_IRQ_MODE - ATOM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH4_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_ATOM1_CH4_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH4_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_CH4_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name ATOM1_CH4_CTRL2 - ATOM[i] channel [x] control2 register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH4_CTRL2_HRES_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL2_HRES_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL2_HRES_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL2_HRES(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_CTRL2_HRES_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_CTRL2_HRES_MASK) /*! @} */ /*! @name ATOM1_CH4_CTRL_SR - ATOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH4_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls1_ATOM1_CH4_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH4_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls1_ATOM1_CH4_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name ATOM1_CH5_RDADDR - ATOM[i] channel[x] ARU read address register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH5_RDADDR_RDADDR0_MASK (0x1FFU) #define GTM_gtm_cls1_ATOM1_CH5_RDADDR_RDADDR0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH5_RDADDR_RDADDR0_WIDTH (9U) #define GTM_gtm_cls1_ATOM1_CH5_RDADDR_RDADDR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_RDADDR_RDADDR0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_RDADDR_RDADDR0_MASK) #define GTM_gtm_cls1_ATOM1_CH5_RDADDR_RDADDR1_MASK (0x1FF0000U) #define GTM_gtm_cls1_ATOM1_CH5_RDADDR_RDADDR1_SHIFT (16U) #define GTM_gtm_cls1_ATOM1_CH5_RDADDR_RDADDR1_WIDTH (9U) #define GTM_gtm_cls1_ATOM1_CH5_RDADDR_RDADDR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_RDADDR_RDADDR1_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_RDADDR_RDADDR1_MASK) /*! @} */ /*! @name ATOM1_CH5_CTRL - ATOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH5_CTRL_MODE_MASK (0x3U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_MODE_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_MODE_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_CTRL_MODE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_CTRL_MODE_MASK) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_TB12_SEL_MASK (0x4U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_TB12_SEL_SHIFT (2U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_TB12_SEL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_TB12_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_CTRL_TB12_SEL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_CTRL_TB12_SEL_MASK) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_ARU_EN_MASK (0x8U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_ARU_EN_SHIFT (3U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_CTRL_ARU_EN_MASK) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_ACB_MASK (0x1F0U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_ACB_SHIFT (4U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_ACB_WIDTH (5U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_ACB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_CTRL_ACB_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_CTRL_ACB_MASK) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_CMP_CTRL_MASK (0x200U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_CMP_CTRL_SHIFT (9U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_CMP_CTRL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_CMP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_CTRL_CMP_CTRL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_CTRL_CMP_CTRL_MASK) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_EUPM_MASK (0x400U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_EUPM_SHIFT (10U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_EUPM_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_EUPM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_CTRL_EUPM_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_CTRL_EUPM_MASK) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_CTRL_SL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_CTRL_SL_MASK) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_WR_REQ_MASK (0x10000U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_WR_REQ_SHIFT (16U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_WR_REQ_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_WR_REQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_CTRL_WR_REQ_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_CTRL_WR_REQ_MASK) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_CTRL_UDMODE_MASK) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_SLA_MASK (0x2000000U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_SLA_SHIFT (25U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_SLA_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_SLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_CTRL_SLA_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_CTRL_SLA_MASK) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_CTRL_OSM_MASK) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_ABM_MASK (0x8000000U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_ABM_SHIFT (27U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_ABM_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_ABM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_CTRL_ABM_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_CTRL_ABM_MASK) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_EXT_FUPD_MASK (0x20000000U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_EXT_FUPD_SHIFT (29U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_EXT_FUPD_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_EXT_FUPD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_CTRL_EXT_FUPD_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_CTRL_EXT_FUPD_MASK) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_SOMB_MASK (0x40000000U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_SOMB_SHIFT (30U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_SOMB_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_SOMB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_CTRL_SOMB_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_CTRL_SOMB_MASK) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_CTRL_FREEZE_MASK) /*! @} */ /*! @name ATOM1_CH5_SR0 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH5_SR0_SR0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH5_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH5_SR0_SR0_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH5_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_SR0_SR0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_SR0_SR0_MASK) /*! @} */ /*! @name ATOM1_CH5_SR1 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH5_SR1_SR1_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH5_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH5_SR1_SR1_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH5_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_SR1_SR1_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_SR1_SR1_MASK) /*! @} */ /*! @name ATOM1_CH5_CM0 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH5_CM0_CM0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH5_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH5_CM0_CM0_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH5_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_CM0_CM0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_CM0_CM0_MASK) /*! @} */ /*! @name ATOM1_CH5_CM1 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH5_CM1_CM1_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH5_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH5_CM1_CM1_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH5_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_CM1_CM1_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_CM1_CM1_MASK) /*! @} */ /*! @name ATOM1_CH5_CN0 - ATOM[i] channel [x] CCU0 counter register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH5_CN0_CN0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH5_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH5_CN0_CN0_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH5_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_CN0_CN0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_CN0_CN0_MASK) /*! @} */ /*! @name ATOM1_CH5_STAT - ATOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH5_STAT_OL_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH5_STAT_OL_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH5_STAT_OL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH5_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_STAT_OL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_STAT_OL_MASK) #define GTM_gtm_cls1_ATOM1_CH5_STAT_ACBI_MASK (0x1F0000U) #define GTM_gtm_cls1_ATOM1_CH5_STAT_ACBI_SHIFT (16U) #define GTM_gtm_cls1_ATOM1_CH5_STAT_ACBI_WIDTH (5U) #define GTM_gtm_cls1_ATOM1_CH5_STAT_ACBI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_STAT_ACBI_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_STAT_ACBI_MASK) #define GTM_gtm_cls1_ATOM1_CH5_STAT_DV_MASK (0x200000U) #define GTM_gtm_cls1_ATOM1_CH5_STAT_DV_SHIFT (21U) #define GTM_gtm_cls1_ATOM1_CH5_STAT_DV_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH5_STAT_DV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_STAT_DV_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_STAT_DV_MASK) #define GTM_gtm_cls1_ATOM1_CH5_STAT_WRF_MASK (0x400000U) #define GTM_gtm_cls1_ATOM1_CH5_STAT_WRF_SHIFT (22U) #define GTM_gtm_cls1_ATOM1_CH5_STAT_WRF_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH5_STAT_WRF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_STAT_WRF_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_STAT_WRF_MASK) #define GTM_gtm_cls1_ATOM1_CH5_STAT_DR_MASK (0x800000U) #define GTM_gtm_cls1_ATOM1_CH5_STAT_DR_SHIFT (23U) #define GTM_gtm_cls1_ATOM1_CH5_STAT_DR_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH5_STAT_DR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_STAT_DR_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_STAT_DR_MASK) #define GTM_gtm_cls1_ATOM1_CH5_STAT_ACBO_MASK (0x1F000000U) #define GTM_gtm_cls1_ATOM1_CH5_STAT_ACBO_SHIFT (24U) #define GTM_gtm_cls1_ATOM1_CH5_STAT_ACBO_WIDTH (5U) #define GTM_gtm_cls1_ATOM1_CH5_STAT_ACBO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_STAT_ACBO_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_STAT_ACBO_MASK) #define GTM_gtm_cls1_ATOM1_CH5_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls1_ATOM1_CH5_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls1_ATOM1_CH5_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH5_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_STAT_OSM_RTF_MASK) /*! @} */ /*! @name ATOM1_CH5_IRQ_NOTIFY - ATOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH5_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH5_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH5_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH5_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls1_ATOM1_CH5_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_ATOM1_CH5_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_ATOM1_CH5_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH5_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name ATOM1_CH5_IRQ_EN - ATOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH5_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH5_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH5_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH5_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls1_ATOM1_CH5_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_ATOM1_CH5_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_ATOM1_CH5_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH5_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name ATOM1_CH5_IRQ_FORCINT - ATOM[i] channel [x] software interrupt generation */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH5_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH5_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH5_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH5_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls1_ATOM1_CH5_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_ATOM1_CH5_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_ATOM1_CH5_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH5_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name ATOM1_CH5_IRQ_MODE - ATOM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH5_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_ATOM1_CH5_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH5_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_CH5_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name ATOM1_CH5_CTRL2 - ATOM[i] channel [x] control2 register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH5_CTRL2_HRES_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL2_HRES_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL2_HRES_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL2_HRES(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_CTRL2_HRES_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_CTRL2_HRES_MASK) /*! @} */ /*! @name ATOM1_CH5_CTRL_SR - ATOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH5_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls1_ATOM1_CH5_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH5_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls1_ATOM1_CH5_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name ATOM1_CH6_RDADDR - ATOM[i] channel[x] ARU read address register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH6_RDADDR_RDADDR0_MASK (0x1FFU) #define GTM_gtm_cls1_ATOM1_CH6_RDADDR_RDADDR0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH6_RDADDR_RDADDR0_WIDTH (9U) #define GTM_gtm_cls1_ATOM1_CH6_RDADDR_RDADDR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_RDADDR_RDADDR0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_RDADDR_RDADDR0_MASK) #define GTM_gtm_cls1_ATOM1_CH6_RDADDR_RDADDR1_MASK (0x1FF0000U) #define GTM_gtm_cls1_ATOM1_CH6_RDADDR_RDADDR1_SHIFT (16U) #define GTM_gtm_cls1_ATOM1_CH6_RDADDR_RDADDR1_WIDTH (9U) #define GTM_gtm_cls1_ATOM1_CH6_RDADDR_RDADDR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_RDADDR_RDADDR1_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_RDADDR_RDADDR1_MASK) /*! @} */ /*! @name ATOM1_CH6_CTRL - ATOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH6_CTRL_MODE_MASK (0x3U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_MODE_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_MODE_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_CTRL_MODE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_CTRL_MODE_MASK) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_TB12_SEL_MASK (0x4U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_TB12_SEL_SHIFT (2U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_TB12_SEL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_TB12_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_CTRL_TB12_SEL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_CTRL_TB12_SEL_MASK) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_ARU_EN_MASK (0x8U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_ARU_EN_SHIFT (3U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_CTRL_ARU_EN_MASK) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_ACB_MASK (0x1F0U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_ACB_SHIFT (4U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_ACB_WIDTH (5U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_ACB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_CTRL_ACB_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_CTRL_ACB_MASK) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_CMP_CTRL_MASK (0x200U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_CMP_CTRL_SHIFT (9U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_CMP_CTRL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_CMP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_CTRL_CMP_CTRL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_CTRL_CMP_CTRL_MASK) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_EUPM_MASK (0x400U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_EUPM_SHIFT (10U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_EUPM_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_EUPM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_CTRL_EUPM_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_CTRL_EUPM_MASK) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_CTRL_SL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_CTRL_SL_MASK) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_WR_REQ_MASK (0x10000U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_WR_REQ_SHIFT (16U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_WR_REQ_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_WR_REQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_CTRL_WR_REQ_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_CTRL_WR_REQ_MASK) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_CTRL_UDMODE_MASK) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_SLA_MASK (0x2000000U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_SLA_SHIFT (25U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_SLA_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_SLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_CTRL_SLA_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_CTRL_SLA_MASK) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_CTRL_OSM_MASK) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_ABM_MASK (0x8000000U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_ABM_SHIFT (27U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_ABM_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_ABM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_CTRL_ABM_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_CTRL_ABM_MASK) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_EXT_FUPD_MASK (0x20000000U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_EXT_FUPD_SHIFT (29U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_EXT_FUPD_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_EXT_FUPD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_CTRL_EXT_FUPD_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_CTRL_EXT_FUPD_MASK) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_SOMB_MASK (0x40000000U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_SOMB_SHIFT (30U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_SOMB_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_SOMB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_CTRL_SOMB_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_CTRL_SOMB_MASK) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_CTRL_FREEZE_MASK) /*! @} */ /*! @name ATOM1_CH6_SR0 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH6_SR0_SR0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH6_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH6_SR0_SR0_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH6_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_SR0_SR0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_SR0_SR0_MASK) /*! @} */ /*! @name ATOM1_CH6_SR1 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH6_SR1_SR1_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH6_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH6_SR1_SR1_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH6_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_SR1_SR1_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_SR1_SR1_MASK) /*! @} */ /*! @name ATOM1_CH6_CM0 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH6_CM0_CM0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH6_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH6_CM0_CM0_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH6_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_CM0_CM0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_CM0_CM0_MASK) /*! @} */ /*! @name ATOM1_CH6_CM1 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH6_CM1_CM1_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH6_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH6_CM1_CM1_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH6_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_CM1_CM1_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_CM1_CM1_MASK) /*! @} */ /*! @name ATOM1_CH6_CN0 - ATOM[i] channel [x] CCU0 counter register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH6_CN0_CN0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH6_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH6_CN0_CN0_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH6_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_CN0_CN0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_CN0_CN0_MASK) /*! @} */ /*! @name ATOM1_CH6_STAT - ATOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH6_STAT_OL_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH6_STAT_OL_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH6_STAT_OL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH6_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_STAT_OL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_STAT_OL_MASK) #define GTM_gtm_cls1_ATOM1_CH6_STAT_ACBI_MASK (0x1F0000U) #define GTM_gtm_cls1_ATOM1_CH6_STAT_ACBI_SHIFT (16U) #define GTM_gtm_cls1_ATOM1_CH6_STAT_ACBI_WIDTH (5U) #define GTM_gtm_cls1_ATOM1_CH6_STAT_ACBI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_STAT_ACBI_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_STAT_ACBI_MASK) #define GTM_gtm_cls1_ATOM1_CH6_STAT_DV_MASK (0x200000U) #define GTM_gtm_cls1_ATOM1_CH6_STAT_DV_SHIFT (21U) #define GTM_gtm_cls1_ATOM1_CH6_STAT_DV_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH6_STAT_DV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_STAT_DV_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_STAT_DV_MASK) #define GTM_gtm_cls1_ATOM1_CH6_STAT_WRF_MASK (0x400000U) #define GTM_gtm_cls1_ATOM1_CH6_STAT_WRF_SHIFT (22U) #define GTM_gtm_cls1_ATOM1_CH6_STAT_WRF_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH6_STAT_WRF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_STAT_WRF_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_STAT_WRF_MASK) #define GTM_gtm_cls1_ATOM1_CH6_STAT_DR_MASK (0x800000U) #define GTM_gtm_cls1_ATOM1_CH6_STAT_DR_SHIFT (23U) #define GTM_gtm_cls1_ATOM1_CH6_STAT_DR_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH6_STAT_DR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_STAT_DR_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_STAT_DR_MASK) #define GTM_gtm_cls1_ATOM1_CH6_STAT_ACBO_MASK (0x1F000000U) #define GTM_gtm_cls1_ATOM1_CH6_STAT_ACBO_SHIFT (24U) #define GTM_gtm_cls1_ATOM1_CH6_STAT_ACBO_WIDTH (5U) #define GTM_gtm_cls1_ATOM1_CH6_STAT_ACBO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_STAT_ACBO_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_STAT_ACBO_MASK) #define GTM_gtm_cls1_ATOM1_CH6_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls1_ATOM1_CH6_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls1_ATOM1_CH6_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH6_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_STAT_OSM_RTF_MASK) /*! @} */ /*! @name ATOM1_CH6_IRQ_NOTIFY - ATOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH6_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH6_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH6_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH6_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls1_ATOM1_CH6_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_ATOM1_CH6_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_ATOM1_CH6_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH6_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name ATOM1_CH6_IRQ_EN - ATOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH6_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH6_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH6_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH6_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls1_ATOM1_CH6_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_ATOM1_CH6_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_ATOM1_CH6_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH6_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name ATOM1_CH6_IRQ_FORCINT - ATOM[i] channel [x] software interrupt generation */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH6_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH6_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH6_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH6_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls1_ATOM1_CH6_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_ATOM1_CH6_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_ATOM1_CH6_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH6_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name ATOM1_CH6_IRQ_MODE - ATOM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH6_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_ATOM1_CH6_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH6_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_CH6_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name ATOM1_CH6_CTRL2 - ATOM[i] channel [x] control2 register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH6_CTRL2_HRES_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL2_HRES_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL2_HRES_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL2_HRES(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_CTRL2_HRES_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_CTRL2_HRES_MASK) /*! @} */ /*! @name ATOM1_CH6_CTRL_SR - ATOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH6_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls1_ATOM1_CH6_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH6_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls1_ATOM1_CH6_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name ATOM1_CH7_RDADDR - ATOM[i] channel[x] ARU read address register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH7_RDADDR_RDADDR0_MASK (0x1FFU) #define GTM_gtm_cls1_ATOM1_CH7_RDADDR_RDADDR0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH7_RDADDR_RDADDR0_WIDTH (9U) #define GTM_gtm_cls1_ATOM1_CH7_RDADDR_RDADDR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_RDADDR_RDADDR0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_RDADDR_RDADDR0_MASK) #define GTM_gtm_cls1_ATOM1_CH7_RDADDR_RDADDR1_MASK (0x1FF0000U) #define GTM_gtm_cls1_ATOM1_CH7_RDADDR_RDADDR1_SHIFT (16U) #define GTM_gtm_cls1_ATOM1_CH7_RDADDR_RDADDR1_WIDTH (9U) #define GTM_gtm_cls1_ATOM1_CH7_RDADDR_RDADDR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_RDADDR_RDADDR1_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_RDADDR_RDADDR1_MASK) /*! @} */ /*! @name ATOM1_CH7_CTRL - ATOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH7_CTRL_MODE_MASK (0x3U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_MODE_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_MODE_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_CTRL_MODE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_CTRL_MODE_MASK) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_TB12_SEL_MASK (0x4U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_TB12_SEL_SHIFT (2U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_TB12_SEL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_TB12_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_CTRL_TB12_SEL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_CTRL_TB12_SEL_MASK) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_ARU_EN_MASK (0x8U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_ARU_EN_SHIFT (3U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_CTRL_ARU_EN_MASK) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_ACB_MASK (0x1F0U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_ACB_SHIFT (4U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_ACB_WIDTH (5U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_ACB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_CTRL_ACB_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_CTRL_ACB_MASK) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_CMP_CTRL_MASK (0x200U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_CMP_CTRL_SHIFT (9U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_CMP_CTRL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_CMP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_CTRL_CMP_CTRL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_CTRL_CMP_CTRL_MASK) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_EUPM_MASK (0x400U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_EUPM_SHIFT (10U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_EUPM_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_EUPM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_CTRL_EUPM_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_CTRL_EUPM_MASK) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_CTRL_SL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_CTRL_SL_MASK) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_WR_REQ_MASK (0x10000U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_WR_REQ_SHIFT (16U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_WR_REQ_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_WR_REQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_CTRL_WR_REQ_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_CTRL_WR_REQ_MASK) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_CTRL_UDMODE_MASK) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_SLA_MASK (0x2000000U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_SLA_SHIFT (25U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_SLA_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_SLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_CTRL_SLA_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_CTRL_SLA_MASK) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_CTRL_OSM_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_CTRL_OSM_MASK) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_ABM_MASK (0x8000000U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_ABM_SHIFT (27U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_ABM_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_ABM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_CTRL_ABM_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_CTRL_ABM_MASK) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_EXT_FUPD_MASK (0x20000000U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_EXT_FUPD_SHIFT (29U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_EXT_FUPD_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_EXT_FUPD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_CTRL_EXT_FUPD_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_CTRL_EXT_FUPD_MASK) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_SOMB_MASK (0x40000000U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_SOMB_SHIFT (30U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_SOMB_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_SOMB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_CTRL_SOMB_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_CTRL_SOMB_MASK) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_CTRL_FREEZE_MASK) /*! @} */ /*! @name ATOM1_CH7_SR0 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH7_SR0_SR0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH7_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH7_SR0_SR0_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH7_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_SR0_SR0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_SR0_SR0_MASK) /*! @} */ /*! @name ATOM1_CH7_SR1 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH7_SR1_SR1_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH7_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH7_SR1_SR1_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH7_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_SR1_SR1_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_SR1_SR1_MASK) /*! @} */ /*! @name ATOM1_CH7_CM0 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH7_CM0_CM0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH7_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH7_CM0_CM0_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH7_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_CM0_CM0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_CM0_CM0_MASK) /*! @} */ /*! @name ATOM1_CH7_CM1 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH7_CM1_CM1_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH7_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH7_CM1_CM1_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH7_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_CM1_CM1_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_CM1_CM1_MASK) /*! @} */ /*! @name ATOM1_CH7_CN0 - ATOM[i] channel [x] CCU0 counter register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH7_CN0_CN0_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_CH7_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH7_CN0_CN0_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_CH7_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_CN0_CN0_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_CN0_CN0_MASK) /*! @} */ /*! @name ATOM1_CH7_STAT - ATOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH7_STAT_OL_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH7_STAT_OL_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH7_STAT_OL_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH7_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_STAT_OL_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_STAT_OL_MASK) #define GTM_gtm_cls1_ATOM1_CH7_STAT_ACBI_MASK (0x1F0000U) #define GTM_gtm_cls1_ATOM1_CH7_STAT_ACBI_SHIFT (16U) #define GTM_gtm_cls1_ATOM1_CH7_STAT_ACBI_WIDTH (5U) #define GTM_gtm_cls1_ATOM1_CH7_STAT_ACBI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_STAT_ACBI_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_STAT_ACBI_MASK) #define GTM_gtm_cls1_ATOM1_CH7_STAT_DV_MASK (0x200000U) #define GTM_gtm_cls1_ATOM1_CH7_STAT_DV_SHIFT (21U) #define GTM_gtm_cls1_ATOM1_CH7_STAT_DV_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH7_STAT_DV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_STAT_DV_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_STAT_DV_MASK) #define GTM_gtm_cls1_ATOM1_CH7_STAT_WRF_MASK (0x400000U) #define GTM_gtm_cls1_ATOM1_CH7_STAT_WRF_SHIFT (22U) #define GTM_gtm_cls1_ATOM1_CH7_STAT_WRF_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH7_STAT_WRF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_STAT_WRF_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_STAT_WRF_MASK) #define GTM_gtm_cls1_ATOM1_CH7_STAT_DR_MASK (0x800000U) #define GTM_gtm_cls1_ATOM1_CH7_STAT_DR_SHIFT (23U) #define GTM_gtm_cls1_ATOM1_CH7_STAT_DR_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH7_STAT_DR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_STAT_DR_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_STAT_DR_MASK) #define GTM_gtm_cls1_ATOM1_CH7_STAT_ACBO_MASK (0x1F000000U) #define GTM_gtm_cls1_ATOM1_CH7_STAT_ACBO_SHIFT (24U) #define GTM_gtm_cls1_ATOM1_CH7_STAT_ACBO_WIDTH (5U) #define GTM_gtm_cls1_ATOM1_CH7_STAT_ACBO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_STAT_ACBO_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_STAT_ACBO_MASK) #define GTM_gtm_cls1_ATOM1_CH7_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls1_ATOM1_CH7_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls1_ATOM1_CH7_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH7_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_STAT_OSM_RTF_MASK) /*! @} */ /*! @name ATOM1_CH7_IRQ_NOTIFY - ATOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH7_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH7_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH7_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH7_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls1_ATOM1_CH7_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_ATOM1_CH7_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_ATOM1_CH7_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH7_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name ATOM1_CH7_IRQ_EN - ATOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH7_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH7_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH7_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH7_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls1_ATOM1_CH7_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_ATOM1_CH7_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_ATOM1_CH7_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH7_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name ATOM1_CH7_IRQ_FORCINT - ATOM[i] channel [x] software interrupt generation */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH7_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH7_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH7_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH7_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls1_ATOM1_CH7_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls1_ATOM1_CH7_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls1_ATOM1_CH7_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH7_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name ATOM1_CH7_IRQ_MODE - ATOM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH7_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_ATOM1_CH7_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH7_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_CH7_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name ATOM1_CH7_CTRL2 - ATOM[i] channel [x] control2 register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH7_CTRL2_HRES_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL2_HRES_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL2_HRES_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL2_HRES(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_CTRL2_HRES_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_CTRL2_HRES_MASK) /*! @} */ /*! @name ATOM1_CH7_CTRL_SR - ATOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_CH7_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls1_ATOM1_CH7_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_CH7_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls1_ATOM1_CH7_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name ATOM1_AGC_GLB_CTRL - ATOM[i] AGC global control register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_HOST_TRIG_MASK (0x1U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_HOST_TRIG_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_HOST_TRIG_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_HOST_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_HOST_TRIG_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_HOST_TRIG_MASK) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH0_MASK (0x100U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH0_SHIFT (8U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH0_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH0_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH0_MASK) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH1_MASK (0x200U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH1_SHIFT (9U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH1_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH1_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH1_MASK) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH2_MASK (0x400U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH2_SHIFT (10U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH2_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH2_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH2_MASK) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH3_MASK (0x800U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH3_SHIFT (11U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH3_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH3_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH3_MASK) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH4_MASK (0x1000U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH4_SHIFT (12U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH4_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH4_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH4_MASK) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH5_MASK (0x2000U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH5_SHIFT (13U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH5_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH5_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH5_MASK) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH6_MASK (0x4000U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH6_SHIFT (14U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH6_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH6_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH6_MASK) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH7_MASK (0x8000U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH7_SHIFT (15U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH7_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH7_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_RST_CH7_MASK) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL0_MASK (0x30000U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL0_SHIFT (16U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL0_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL0_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL0_MASK) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL1_MASK (0xC0000U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL1_SHIFT (18U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL1_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL1_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL1_MASK) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL2_MASK (0x300000U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL2_SHIFT (20U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL2_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL2_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL2_MASK) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL3_MASK (0xC00000U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL3_SHIFT (22U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL3_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL3_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL3_MASK) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL4_MASK (0x3000000U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL4_SHIFT (24U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL4_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL4_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL4_MASK) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL5_MASK (0xC000000U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL5_SHIFT (26U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL5_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL5_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL5_MASK) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL6_MASK (0x30000000U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL6_SHIFT (28U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL6_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL6_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL6_MASK) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL7_MASK (0xC0000000U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL7_SHIFT (30U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL7_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL7_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_GLB_CTRL_UPEN_CTRL7_MASK) /*! @} */ /*! @name ATOM1_AGC_ENDIS_CTRL - ATOM[i] AGC enable/disable control register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL0_MASK (0x3U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL0_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL0_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL0_MASK) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL1_MASK (0xCU) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL1_SHIFT (2U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL1_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL1_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL1_MASK) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL2_MASK (0x30U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL2_SHIFT (4U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL2_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL2_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL2_MASK) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL3_MASK (0xC0U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL3_SHIFT (6U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL3_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL3_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL3_MASK) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL4_MASK (0x300U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL4_SHIFT (8U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL4_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL4_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL4_MASK) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL5_MASK (0xC00U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL5_SHIFT (10U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL5_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL5_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL5_MASK) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL6_MASK (0x3000U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL6_SHIFT (12U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL6_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL6_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL6_MASK) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL7_MASK (0xC000U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL7_SHIFT (14U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL7_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL7_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_ENDIS_CTRL_ENDIS_CTRL7_MASK) /*! @} */ /*! @name ATOM1_AGC_ENDIS_STAT - ATOM[i] AGC enable/disable status register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT0_MASK (0x3U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT0_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT0_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT0_MASK) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT1_MASK (0xCU) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT1_SHIFT (2U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT1_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT1_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT1_MASK) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT2_MASK (0x30U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT2_SHIFT (4U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT2_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT2_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT2_MASK) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT3_MASK (0xC0U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT3_SHIFT (6U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT3_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT3_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT3_MASK) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT4_MASK (0x300U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT4_SHIFT (8U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT4_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT4_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT4_MASK) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT5_MASK (0xC00U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT5_SHIFT (10U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT5_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT5_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT5_MASK) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT6_MASK (0x3000U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT6_SHIFT (12U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT6_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT6_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT6_MASK) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT7_MASK (0xC000U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT7_SHIFT (14U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT7_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT7_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_ENDIS_STAT_ENDIS_STAT7_MASK) /*! @} */ /*! @name ATOM1_AGC_ACT_TB - ATOM[i] AGC action time base register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_AGC_ACT_TB_ACT_TB_MASK (0xFFFFFFU) #define GTM_gtm_cls1_ATOM1_AGC_ACT_TB_ACT_TB_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_AGC_ACT_TB_ACT_TB_WIDTH (24U) #define GTM_gtm_cls1_ATOM1_AGC_ACT_TB_ACT_TB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_ACT_TB_ACT_TB_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_ACT_TB_ACT_TB_MASK) #define GTM_gtm_cls1_ATOM1_AGC_ACT_TB_TB_TRIG_MASK (0x1000000U) #define GTM_gtm_cls1_ATOM1_AGC_ACT_TB_TB_TRIG_SHIFT (24U) #define GTM_gtm_cls1_ATOM1_AGC_ACT_TB_TB_TRIG_WIDTH (1U) #define GTM_gtm_cls1_ATOM1_AGC_ACT_TB_TB_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_ACT_TB_TB_TRIG_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_ACT_TB_TB_TRIG_MASK) #define GTM_gtm_cls1_ATOM1_AGC_ACT_TB_TBU_SEL_MASK (0x6000000U) #define GTM_gtm_cls1_ATOM1_AGC_ACT_TB_TBU_SEL_SHIFT (25U) #define GTM_gtm_cls1_ATOM1_AGC_ACT_TB_TBU_SEL_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_ACT_TB_TBU_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_ACT_TB_TBU_SEL_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_ACT_TB_TBU_SEL_MASK) /*! @} */ /*! @name ATOM1_AGC_OUTEN_CTRL - ATOM[i] AGC output enable control register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL0_MASK (0x3U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL0_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL0_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL0_MASK) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL1_MASK (0xCU) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL1_SHIFT (2U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL1_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL1_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL1_MASK) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL2_MASK (0x30U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL2_SHIFT (4U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL2_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL2_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL2_MASK) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL3_MASK (0xC0U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL3_SHIFT (6U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL3_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL3_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL3_MASK) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL4_MASK (0x300U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL4_SHIFT (8U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL4_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL4_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL4_MASK) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL5_MASK (0xC00U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL5_SHIFT (10U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL5_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL5_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL5_MASK) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL6_MASK (0x3000U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL6_SHIFT (12U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL6_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL6_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL6_MASK) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL7_MASK (0xC000U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL7_SHIFT (14U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL7_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL7_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_OUTEN_CTRL_OUTEN_CTRL7_MASK) /*! @} */ /*! @name ATOM1_AGC_OUTEN_STAT - ATOM[i] AGC output enable status register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT0_MASK (0x3U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT0_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT0_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT0_MASK) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT1_MASK (0xCU) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT1_SHIFT (2U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT1_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT1_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT1_MASK) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT2_MASK (0x30U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT2_SHIFT (4U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT2_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT2_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT2_MASK) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT3_MASK (0xC0U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT3_SHIFT (6U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT3_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT3_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT3_MASK) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT4_MASK (0x300U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT4_SHIFT (8U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT4_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT4_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT4_MASK) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT5_MASK (0xC00U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT5_SHIFT (10U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT5_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT5_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT5_MASK) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT6_MASK (0x3000U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT6_SHIFT (12U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT6_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT6_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT6_MASK) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT7_MASK (0xC000U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT7_SHIFT (14U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT7_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT7_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_OUTEN_STAT_OUTEN_STAT7_MASK) /*! @} */ /*! @name ATOM1_AGC_FUPD_CTRL - ATOM[i] AGC force update control register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL0_MASK (0x3U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL0_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL0_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL0_MASK) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL1_MASK (0xCU) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL1_SHIFT (2U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL1_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL1_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL1_MASK) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL2_MASK (0x30U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL2_SHIFT (4U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL2_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL2_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL2_MASK) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL3_MASK (0xC0U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL3_SHIFT (6U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL3_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL3_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL3_MASK) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL4_MASK (0x300U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL4_SHIFT (8U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL4_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL4_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL4_MASK) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL5_MASK (0xC00U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL5_SHIFT (10U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL5_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL5_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL5_MASK) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL6_MASK (0x3000U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL6_SHIFT (12U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL6_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL6_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL6_MASK) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL7_MASK (0xC000U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL7_SHIFT (14U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL7_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL7_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_FUPD_CTRL7_MASK) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH0_MASK (0x30000U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH0_SHIFT (16U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH0_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH0_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH0_MASK) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH1_MASK (0xC0000U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH1_SHIFT (18U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH1_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH1_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH1_MASK) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH2_MASK (0x300000U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH2_SHIFT (20U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH2_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH2_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH2_MASK) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH3_MASK (0xC00000U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH3_SHIFT (22U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH3_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH3_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH3_MASK) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH4_MASK (0x3000000U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH4_SHIFT (24U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH4_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH4_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH4_MASK) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH5_MASK (0xC000000U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH5_SHIFT (26U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH5_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH5_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH5_MASK) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH6_MASK (0x30000000U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH6_SHIFT (28U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH6_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH6_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH6_MASK) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH7_MASK (0xC0000000U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH7_SHIFT (30U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH7_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH7_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_FUPD_CTRL_RSTCN0_CH7_MASK) /*! @} */ /*! @name ATOM1_AGC_INT_TRIG - ATOM[i] AGC internal trigger control register */ /*! @{ */ #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG0_MASK (0x3U) #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG0_SHIFT (0U) #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG0_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG0_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG0_MASK) #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG1_MASK (0xCU) #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG1_SHIFT (2U) #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG1_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG1_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG1_MASK) #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG2_MASK (0x30U) #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG2_SHIFT (4U) #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG2_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG2_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG2_MASK) #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG3_MASK (0xC0U) #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG3_SHIFT (6U) #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG3_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG3_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG3_MASK) #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG4_MASK (0x300U) #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG4_SHIFT (8U) #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG4_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG4_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG4_MASK) #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG5_MASK (0xC00U) #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG5_SHIFT (10U) #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG5_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG5_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG5_MASK) #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG6_MASK (0x3000U) #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG6_SHIFT (12U) #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG6_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG6_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG6_MASK) #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG7_MASK (0xC000U) #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG7_SHIFT (14U) #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG7_WIDTH (2U) #define GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG7_SHIFT)) & GTM_gtm_cls1_ATOM1_AGC_INT_TRIG_INT_TRIG7_MASK) /*! @} */ /*! @name MCS1_CH0_R0 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH0_R0_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH0_R0_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH0_R0_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH0_R0_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_R0_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_R0_DATA_MASK) /*! @} */ /*! @name MCS1_CH0_R1 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH0_R1_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH0_R1_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH0_R1_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH0_R1_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_R1_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_R1_DATA_MASK) /*! @} */ /*! @name MCS1_CH0_R2 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH0_R2_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH0_R2_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH0_R2_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH0_R2_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_R2_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_R2_DATA_MASK) /*! @} */ /*! @name MCS1_CH0_R3 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH0_R3_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH0_R3_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH0_R3_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH0_R3_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_R3_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_R3_DATA_MASK) /*! @} */ /*! @name MCS1_CH0_R4 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH0_R4_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH0_R4_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH0_R4_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH0_R4_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_R4_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_R4_DATA_MASK) /*! @} */ /*! @name MCS1_CH0_R5 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH0_R5_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH0_R5_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH0_R5_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH0_R5_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_R5_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_R5_DATA_MASK) /*! @} */ /*! @name MCS1_CH0_R6 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH0_R6_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH0_R6_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH0_R6_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH0_R6_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_R6_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_R6_DATA_MASK) /*! @} */ /*! @name MCS1_CH0_R7 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH0_R7_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH0_R7_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH0_R7_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH0_R7_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_R7_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_R7_DATA_MASK) /*! @} */ /*! @name MCS1_CH0_CTRL - MCS[i] channel x control register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH0_CTRL_EN_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH0_CTRL_EN_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH0_CTRL_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH0_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_CTRL_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_CTRL_EN_MASK) #define GTM_gtm_cls1_MCS1_CH0_CTRL_IRQ_MASK (0x2U) #define GTM_gtm_cls1_MCS1_CH0_CTRL_IRQ_SHIFT (1U) #define GTM_gtm_cls1_MCS1_CH0_CTRL_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH0_CTRL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_CTRL_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_CTRL_IRQ_MASK) #define GTM_gtm_cls1_MCS1_CH0_CTRL_ERR_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH0_CTRL_ERR_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH0_CTRL_ERR_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH0_CTRL_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_CTRL_ERR_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_CTRL_ERR_MASK) #define GTM_gtm_cls1_MCS1_CH0_CTRL_CY_MASK (0x10U) #define GTM_gtm_cls1_MCS1_CH0_CTRL_CY_SHIFT (4U) #define GTM_gtm_cls1_MCS1_CH0_CTRL_CY_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH0_CTRL_CY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_CTRL_CY_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_CTRL_CY_MASK) #define GTM_gtm_cls1_MCS1_CH0_CTRL_Z_MASK (0x20U) #define GTM_gtm_cls1_MCS1_CH0_CTRL_Z_SHIFT (5U) #define GTM_gtm_cls1_MCS1_CH0_CTRL_Z_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH0_CTRL_Z(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_CTRL_Z_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_CTRL_Z_MASK) #define GTM_gtm_cls1_MCS1_CH0_CTRL_V_MASK (0x40U) #define GTM_gtm_cls1_MCS1_CH0_CTRL_V_SHIFT (6U) #define GTM_gtm_cls1_MCS1_CH0_CTRL_V_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH0_CTRL_V(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_CTRL_V_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_CTRL_V_MASK) #define GTM_gtm_cls1_MCS1_CH0_CTRL_N_MASK (0x80U) #define GTM_gtm_cls1_MCS1_CH0_CTRL_N_SHIFT (7U) #define GTM_gtm_cls1_MCS1_CH0_CTRL_N_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH0_CTRL_N(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_CTRL_N_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_CTRL_N_MASK) #define GTM_gtm_cls1_MCS1_CH0_CTRL_CAT_MASK (0x100U) #define GTM_gtm_cls1_MCS1_CH0_CTRL_CAT_SHIFT (8U) #define GTM_gtm_cls1_MCS1_CH0_CTRL_CAT_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH0_CTRL_CAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_CTRL_CAT_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_CTRL_CAT_MASK) #define GTM_gtm_cls1_MCS1_CH0_CTRL_CWT_MASK (0x200U) #define GTM_gtm_cls1_MCS1_CH0_CTRL_CWT_SHIFT (9U) #define GTM_gtm_cls1_MCS1_CH0_CTRL_CWT_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH0_CTRL_CWT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_CTRL_CWT_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_CTRL_CWT_MASK) #define GTM_gtm_cls1_MCS1_CH0_CTRL_SAT_MASK (0x400U) #define GTM_gtm_cls1_MCS1_CH0_CTRL_SAT_SHIFT (10U) #define GTM_gtm_cls1_MCS1_CH0_CTRL_SAT_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH0_CTRL_SAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_CTRL_SAT_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_CTRL_SAT_MASK) /*! @} */ /*! @name MCS1_CH0_ACB - MCS[i] channel x ARU control Bit register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH0_ACB_ACB0_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH0_ACB_ACB0_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH0_ACB_ACB0_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH0_ACB_ACB0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_ACB_ACB0_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_ACB_ACB0_MASK) #define GTM_gtm_cls1_MCS1_CH0_ACB_ACB1_MASK (0x2U) #define GTM_gtm_cls1_MCS1_CH0_ACB_ACB1_SHIFT (1U) #define GTM_gtm_cls1_MCS1_CH0_ACB_ACB1_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH0_ACB_ACB1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_ACB_ACB1_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_ACB_ACB1_MASK) #define GTM_gtm_cls1_MCS1_CH0_ACB_ACB2_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH0_ACB_ACB2_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH0_ACB_ACB2_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH0_ACB_ACB2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_ACB_ACB2_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_ACB_ACB2_MASK) #define GTM_gtm_cls1_MCS1_CH0_ACB_ACB3_MASK (0x8U) #define GTM_gtm_cls1_MCS1_CH0_ACB_ACB3_SHIFT (3U) #define GTM_gtm_cls1_MCS1_CH0_ACB_ACB3_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH0_ACB_ACB3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_ACB_ACB3_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_ACB_ACB3_MASK) #define GTM_gtm_cls1_MCS1_CH0_ACB_ACB4_MASK (0x10U) #define GTM_gtm_cls1_MCS1_CH0_ACB_ACB4_SHIFT (4U) #define GTM_gtm_cls1_MCS1_CH0_ACB_ACB4_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH0_ACB_ACB4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_ACB_ACB4_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_ACB_ACB4_MASK) /*! @} */ /*! @name MCS1_CH0_MHB - MCS[i] channel x memory high byte register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH0_MHB_DATA_MASK (0xFFU) #define GTM_gtm_cls1_MCS1_CH0_MHB_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH0_MHB_DATA_WIDTH (8U) #define GTM_gtm_cls1_MCS1_CH0_MHB_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_MHB_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_MHB_DATA_MASK) /*! @} */ /*! @name MCS1_CH0_PC - MCS[i] channel x program counter register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH0_PC_PC_MASK (0xFFFFU) #define GTM_gtm_cls1_MCS1_CH0_PC_PC_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH0_PC_PC_WIDTH (16U) #define GTM_gtm_cls1_MCS1_CH0_PC_PC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_PC_PC_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_PC_PC_MASK) /*! @} */ /*! @name MCS1_CH0_IRQ_NOTIFY - MCS[i] channel x interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH0_IRQ_NOTIFY_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH0_IRQ_NOTIFY_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH0_IRQ_NOTIFY_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH0_IRQ_NOTIFY_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_IRQ_NOTIFY_MCS_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_IRQ_NOTIFY_MCS_IRQ_MASK) #define GTM_gtm_cls1_MCS1_CH0_IRQ_NOTIFY_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH0_IRQ_NOTIFY_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH0_IRQ_NOTIFY_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH0_IRQ_NOTIFY_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_IRQ_NOTIFY_ERR_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_IRQ_NOTIFY_ERR_IRQ_MASK) /*! @} */ /*! @name MCS1_CH0_IRQ_EN - MCS[i] channel x interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH0_IRQ_EN_MCS_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH0_IRQ_EN_MCS_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH0_IRQ_EN_MCS_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH0_IRQ_EN_MCS_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_IRQ_EN_MCS_IRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_IRQ_EN_MCS_IRQ_EN_MASK) #define GTM_gtm_cls1_MCS1_CH0_IRQ_EN_ERR_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH0_IRQ_EN_ERR_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH0_IRQ_EN_ERR_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH0_IRQ_EN_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_IRQ_EN_ERR_IRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_IRQ_EN_ERR_IRQ_EN_MASK) /*! @} */ /*! @name MCS1_CH0_IRQ_FORCINT - MCS[i] channel x force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH0_IRQ_FORCINT_TRG_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH0_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH0_IRQ_FORCINT_TRG_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH0_IRQ_FORCINT_TRG_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_IRQ_FORCINT_TRG_MCS_IRQ_MASK) #define GTM_gtm_cls1_MCS1_CH0_IRQ_FORCINT_TRG_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH0_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH0_IRQ_FORCINT_TRG_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH0_IRQ_FORCINT_TRG_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_IRQ_FORCINT_TRG_ERR_IRQ_MASK) /*! @} */ /*! @name MCS1_CH0_IRQ_MODE - MCS[i] channel x IRQ mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH0_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_MCS1_CH0_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH0_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_MCS1_CH0_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name MCS1_CH0_EIRQ_EN - MCS[i] channel x error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH0_EIRQ_EN_MCS_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH0_EIRQ_EN_MCS_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH0_EIRQ_EN_MCS_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH0_EIRQ_EN_MCS_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_EIRQ_EN_MCS_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_EIRQ_EN_MCS_EIRQ_EN_MASK) #define GTM_gtm_cls1_MCS1_CH0_EIRQ_EN_ERR_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH0_EIRQ_EN_ERR_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH0_EIRQ_EN_ERR_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH0_EIRQ_EN_ERR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH0_EIRQ_EN_ERR_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH0_EIRQ_EN_ERR_EIRQ_EN_MASK) /*! @} */ /*! @name MCS1_CH1_R0 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH1_R0_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH1_R0_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH1_R0_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH1_R0_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_R0_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_R0_DATA_MASK) /*! @} */ /*! @name MCS1_CH1_R1 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH1_R1_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH1_R1_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH1_R1_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH1_R1_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_R1_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_R1_DATA_MASK) /*! @} */ /*! @name MCS1_CH1_R2 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH1_R2_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH1_R2_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH1_R2_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH1_R2_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_R2_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_R2_DATA_MASK) /*! @} */ /*! @name MCS1_CH1_R3 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH1_R3_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH1_R3_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH1_R3_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH1_R3_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_R3_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_R3_DATA_MASK) /*! @} */ /*! @name MCS1_CH1_R4 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH1_R4_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH1_R4_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH1_R4_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH1_R4_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_R4_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_R4_DATA_MASK) /*! @} */ /*! @name MCS1_CH1_R5 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH1_R5_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH1_R5_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH1_R5_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH1_R5_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_R5_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_R5_DATA_MASK) /*! @} */ /*! @name MCS1_CH1_R6 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH1_R6_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH1_R6_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH1_R6_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH1_R6_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_R6_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_R6_DATA_MASK) /*! @} */ /*! @name MCS1_CH1_R7 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH1_R7_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH1_R7_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH1_R7_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH1_R7_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_R7_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_R7_DATA_MASK) /*! @} */ /*! @name MCS1_CH1_CTRL - MCS[i] channel x control register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH1_CTRL_EN_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH1_CTRL_EN_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH1_CTRL_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH1_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_CTRL_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_CTRL_EN_MASK) #define GTM_gtm_cls1_MCS1_CH1_CTRL_IRQ_MASK (0x2U) #define GTM_gtm_cls1_MCS1_CH1_CTRL_IRQ_SHIFT (1U) #define GTM_gtm_cls1_MCS1_CH1_CTRL_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH1_CTRL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_CTRL_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_CTRL_IRQ_MASK) #define GTM_gtm_cls1_MCS1_CH1_CTRL_ERR_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH1_CTRL_ERR_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH1_CTRL_ERR_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH1_CTRL_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_CTRL_ERR_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_CTRL_ERR_MASK) #define GTM_gtm_cls1_MCS1_CH1_CTRL_CY_MASK (0x10U) #define GTM_gtm_cls1_MCS1_CH1_CTRL_CY_SHIFT (4U) #define GTM_gtm_cls1_MCS1_CH1_CTRL_CY_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH1_CTRL_CY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_CTRL_CY_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_CTRL_CY_MASK) #define GTM_gtm_cls1_MCS1_CH1_CTRL_Z_MASK (0x20U) #define GTM_gtm_cls1_MCS1_CH1_CTRL_Z_SHIFT (5U) #define GTM_gtm_cls1_MCS1_CH1_CTRL_Z_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH1_CTRL_Z(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_CTRL_Z_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_CTRL_Z_MASK) #define GTM_gtm_cls1_MCS1_CH1_CTRL_V_MASK (0x40U) #define GTM_gtm_cls1_MCS1_CH1_CTRL_V_SHIFT (6U) #define GTM_gtm_cls1_MCS1_CH1_CTRL_V_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH1_CTRL_V(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_CTRL_V_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_CTRL_V_MASK) #define GTM_gtm_cls1_MCS1_CH1_CTRL_N_MASK (0x80U) #define GTM_gtm_cls1_MCS1_CH1_CTRL_N_SHIFT (7U) #define GTM_gtm_cls1_MCS1_CH1_CTRL_N_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH1_CTRL_N(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_CTRL_N_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_CTRL_N_MASK) #define GTM_gtm_cls1_MCS1_CH1_CTRL_CAT_MASK (0x100U) #define GTM_gtm_cls1_MCS1_CH1_CTRL_CAT_SHIFT (8U) #define GTM_gtm_cls1_MCS1_CH1_CTRL_CAT_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH1_CTRL_CAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_CTRL_CAT_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_CTRL_CAT_MASK) #define GTM_gtm_cls1_MCS1_CH1_CTRL_CWT_MASK (0x200U) #define GTM_gtm_cls1_MCS1_CH1_CTRL_CWT_SHIFT (9U) #define GTM_gtm_cls1_MCS1_CH1_CTRL_CWT_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH1_CTRL_CWT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_CTRL_CWT_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_CTRL_CWT_MASK) #define GTM_gtm_cls1_MCS1_CH1_CTRL_SAT_MASK (0x400U) #define GTM_gtm_cls1_MCS1_CH1_CTRL_SAT_SHIFT (10U) #define GTM_gtm_cls1_MCS1_CH1_CTRL_SAT_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH1_CTRL_SAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_CTRL_SAT_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_CTRL_SAT_MASK) /*! @} */ /*! @name MCS1_CH1_ACB - MCS[i] channel x ARU control Bit register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH1_ACB_ACB0_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH1_ACB_ACB0_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH1_ACB_ACB0_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH1_ACB_ACB0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_ACB_ACB0_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_ACB_ACB0_MASK) #define GTM_gtm_cls1_MCS1_CH1_ACB_ACB1_MASK (0x2U) #define GTM_gtm_cls1_MCS1_CH1_ACB_ACB1_SHIFT (1U) #define GTM_gtm_cls1_MCS1_CH1_ACB_ACB1_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH1_ACB_ACB1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_ACB_ACB1_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_ACB_ACB1_MASK) #define GTM_gtm_cls1_MCS1_CH1_ACB_ACB2_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH1_ACB_ACB2_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH1_ACB_ACB2_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH1_ACB_ACB2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_ACB_ACB2_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_ACB_ACB2_MASK) #define GTM_gtm_cls1_MCS1_CH1_ACB_ACB3_MASK (0x8U) #define GTM_gtm_cls1_MCS1_CH1_ACB_ACB3_SHIFT (3U) #define GTM_gtm_cls1_MCS1_CH1_ACB_ACB3_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH1_ACB_ACB3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_ACB_ACB3_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_ACB_ACB3_MASK) #define GTM_gtm_cls1_MCS1_CH1_ACB_ACB4_MASK (0x10U) #define GTM_gtm_cls1_MCS1_CH1_ACB_ACB4_SHIFT (4U) #define GTM_gtm_cls1_MCS1_CH1_ACB_ACB4_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH1_ACB_ACB4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_ACB_ACB4_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_ACB_ACB4_MASK) /*! @} */ /*! @name MCS1_CH1_MHB - MCS[i] channel x memory high byte register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH1_MHB_DATA_MASK (0xFFU) #define GTM_gtm_cls1_MCS1_CH1_MHB_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH1_MHB_DATA_WIDTH (8U) #define GTM_gtm_cls1_MCS1_CH1_MHB_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_MHB_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_MHB_DATA_MASK) /*! @} */ /*! @name MCS1_CH1_PC - MCS[i] channel x program counter register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH1_PC_PC_MASK (0xFFFFU) #define GTM_gtm_cls1_MCS1_CH1_PC_PC_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH1_PC_PC_WIDTH (16U) #define GTM_gtm_cls1_MCS1_CH1_PC_PC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_PC_PC_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_PC_PC_MASK) /*! @} */ /*! @name MCS1_CH1_IRQ_NOTIFY - MCS[i] channel x interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH1_IRQ_NOTIFY_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH1_IRQ_NOTIFY_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH1_IRQ_NOTIFY_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH1_IRQ_NOTIFY_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_IRQ_NOTIFY_MCS_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_IRQ_NOTIFY_MCS_IRQ_MASK) #define GTM_gtm_cls1_MCS1_CH1_IRQ_NOTIFY_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH1_IRQ_NOTIFY_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH1_IRQ_NOTIFY_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH1_IRQ_NOTIFY_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_IRQ_NOTIFY_ERR_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_IRQ_NOTIFY_ERR_IRQ_MASK) /*! @} */ /*! @name MCS1_CH1_IRQ_EN - MCS[i] channel x interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH1_IRQ_EN_MCS_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH1_IRQ_EN_MCS_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH1_IRQ_EN_MCS_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH1_IRQ_EN_MCS_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_IRQ_EN_MCS_IRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_IRQ_EN_MCS_IRQ_EN_MASK) #define GTM_gtm_cls1_MCS1_CH1_IRQ_EN_ERR_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH1_IRQ_EN_ERR_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH1_IRQ_EN_ERR_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH1_IRQ_EN_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_IRQ_EN_ERR_IRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_IRQ_EN_ERR_IRQ_EN_MASK) /*! @} */ /*! @name MCS1_CH1_IRQ_FORCINT - MCS[i] channel x force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH1_IRQ_FORCINT_TRG_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH1_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH1_IRQ_FORCINT_TRG_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH1_IRQ_FORCINT_TRG_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_IRQ_FORCINT_TRG_MCS_IRQ_MASK) #define GTM_gtm_cls1_MCS1_CH1_IRQ_FORCINT_TRG_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH1_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH1_IRQ_FORCINT_TRG_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH1_IRQ_FORCINT_TRG_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_IRQ_FORCINT_TRG_ERR_IRQ_MASK) /*! @} */ /*! @name MCS1_CH1_IRQ_MODE - MCS[i] channel x IRQ mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH1_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_MCS1_CH1_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH1_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_MCS1_CH1_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name MCS1_CH1_EIRQ_EN - MCS[i] channel x error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH1_EIRQ_EN_MCS_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH1_EIRQ_EN_MCS_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH1_EIRQ_EN_MCS_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH1_EIRQ_EN_MCS_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_EIRQ_EN_MCS_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_EIRQ_EN_MCS_EIRQ_EN_MASK) #define GTM_gtm_cls1_MCS1_CH1_EIRQ_EN_ERR_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH1_EIRQ_EN_ERR_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH1_EIRQ_EN_ERR_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH1_EIRQ_EN_ERR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH1_EIRQ_EN_ERR_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH1_EIRQ_EN_ERR_EIRQ_EN_MASK) /*! @} */ /*! @name MCS1_CH2_R0 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH2_R0_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH2_R0_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH2_R0_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH2_R0_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_R0_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_R0_DATA_MASK) /*! @} */ /*! @name MCS1_CH2_R1 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH2_R1_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH2_R1_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH2_R1_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH2_R1_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_R1_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_R1_DATA_MASK) /*! @} */ /*! @name MCS1_CH2_R2 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH2_R2_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH2_R2_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH2_R2_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH2_R2_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_R2_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_R2_DATA_MASK) /*! @} */ /*! @name MCS1_CH2_R3 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH2_R3_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH2_R3_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH2_R3_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH2_R3_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_R3_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_R3_DATA_MASK) /*! @} */ /*! @name MCS1_CH2_R4 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH2_R4_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH2_R4_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH2_R4_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH2_R4_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_R4_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_R4_DATA_MASK) /*! @} */ /*! @name MCS1_CH2_R5 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH2_R5_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH2_R5_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH2_R5_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH2_R5_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_R5_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_R5_DATA_MASK) /*! @} */ /*! @name MCS1_CH2_R6 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH2_R6_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH2_R6_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH2_R6_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH2_R6_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_R6_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_R6_DATA_MASK) /*! @} */ /*! @name MCS1_CH2_R7 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH2_R7_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH2_R7_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH2_R7_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH2_R7_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_R7_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_R7_DATA_MASK) /*! @} */ /*! @name MCS1_CH2_CTRL - MCS[i] channel x control register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH2_CTRL_EN_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH2_CTRL_EN_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH2_CTRL_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH2_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_CTRL_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_CTRL_EN_MASK) #define GTM_gtm_cls1_MCS1_CH2_CTRL_IRQ_MASK (0x2U) #define GTM_gtm_cls1_MCS1_CH2_CTRL_IRQ_SHIFT (1U) #define GTM_gtm_cls1_MCS1_CH2_CTRL_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH2_CTRL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_CTRL_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_CTRL_IRQ_MASK) #define GTM_gtm_cls1_MCS1_CH2_CTRL_ERR_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH2_CTRL_ERR_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH2_CTRL_ERR_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH2_CTRL_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_CTRL_ERR_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_CTRL_ERR_MASK) #define GTM_gtm_cls1_MCS1_CH2_CTRL_CY_MASK (0x10U) #define GTM_gtm_cls1_MCS1_CH2_CTRL_CY_SHIFT (4U) #define GTM_gtm_cls1_MCS1_CH2_CTRL_CY_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH2_CTRL_CY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_CTRL_CY_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_CTRL_CY_MASK) #define GTM_gtm_cls1_MCS1_CH2_CTRL_Z_MASK (0x20U) #define GTM_gtm_cls1_MCS1_CH2_CTRL_Z_SHIFT (5U) #define GTM_gtm_cls1_MCS1_CH2_CTRL_Z_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH2_CTRL_Z(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_CTRL_Z_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_CTRL_Z_MASK) #define GTM_gtm_cls1_MCS1_CH2_CTRL_V_MASK (0x40U) #define GTM_gtm_cls1_MCS1_CH2_CTRL_V_SHIFT (6U) #define GTM_gtm_cls1_MCS1_CH2_CTRL_V_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH2_CTRL_V(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_CTRL_V_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_CTRL_V_MASK) #define GTM_gtm_cls1_MCS1_CH2_CTRL_N_MASK (0x80U) #define GTM_gtm_cls1_MCS1_CH2_CTRL_N_SHIFT (7U) #define GTM_gtm_cls1_MCS1_CH2_CTRL_N_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH2_CTRL_N(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_CTRL_N_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_CTRL_N_MASK) #define GTM_gtm_cls1_MCS1_CH2_CTRL_CAT_MASK (0x100U) #define GTM_gtm_cls1_MCS1_CH2_CTRL_CAT_SHIFT (8U) #define GTM_gtm_cls1_MCS1_CH2_CTRL_CAT_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH2_CTRL_CAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_CTRL_CAT_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_CTRL_CAT_MASK) #define GTM_gtm_cls1_MCS1_CH2_CTRL_CWT_MASK (0x200U) #define GTM_gtm_cls1_MCS1_CH2_CTRL_CWT_SHIFT (9U) #define GTM_gtm_cls1_MCS1_CH2_CTRL_CWT_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH2_CTRL_CWT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_CTRL_CWT_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_CTRL_CWT_MASK) #define GTM_gtm_cls1_MCS1_CH2_CTRL_SAT_MASK (0x400U) #define GTM_gtm_cls1_MCS1_CH2_CTRL_SAT_SHIFT (10U) #define GTM_gtm_cls1_MCS1_CH2_CTRL_SAT_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH2_CTRL_SAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_CTRL_SAT_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_CTRL_SAT_MASK) /*! @} */ /*! @name MCS1_CH2_ACB - MCS[i] channel x ARU control Bit register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH2_ACB_ACB0_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH2_ACB_ACB0_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH2_ACB_ACB0_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH2_ACB_ACB0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_ACB_ACB0_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_ACB_ACB0_MASK) #define GTM_gtm_cls1_MCS1_CH2_ACB_ACB1_MASK (0x2U) #define GTM_gtm_cls1_MCS1_CH2_ACB_ACB1_SHIFT (1U) #define GTM_gtm_cls1_MCS1_CH2_ACB_ACB1_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH2_ACB_ACB1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_ACB_ACB1_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_ACB_ACB1_MASK) #define GTM_gtm_cls1_MCS1_CH2_ACB_ACB2_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH2_ACB_ACB2_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH2_ACB_ACB2_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH2_ACB_ACB2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_ACB_ACB2_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_ACB_ACB2_MASK) #define GTM_gtm_cls1_MCS1_CH2_ACB_ACB3_MASK (0x8U) #define GTM_gtm_cls1_MCS1_CH2_ACB_ACB3_SHIFT (3U) #define GTM_gtm_cls1_MCS1_CH2_ACB_ACB3_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH2_ACB_ACB3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_ACB_ACB3_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_ACB_ACB3_MASK) #define GTM_gtm_cls1_MCS1_CH2_ACB_ACB4_MASK (0x10U) #define GTM_gtm_cls1_MCS1_CH2_ACB_ACB4_SHIFT (4U) #define GTM_gtm_cls1_MCS1_CH2_ACB_ACB4_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH2_ACB_ACB4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_ACB_ACB4_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_ACB_ACB4_MASK) /*! @} */ /*! @name MCS1_CH2_MHB - MCS[i] channel x memory high byte register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH2_MHB_DATA_MASK (0xFFU) #define GTM_gtm_cls1_MCS1_CH2_MHB_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH2_MHB_DATA_WIDTH (8U) #define GTM_gtm_cls1_MCS1_CH2_MHB_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_MHB_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_MHB_DATA_MASK) /*! @} */ /*! @name MCS1_CH2_PC - MCS[i] channel x program counter register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH2_PC_PC_MASK (0xFFFFU) #define GTM_gtm_cls1_MCS1_CH2_PC_PC_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH2_PC_PC_WIDTH (16U) #define GTM_gtm_cls1_MCS1_CH2_PC_PC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_PC_PC_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_PC_PC_MASK) /*! @} */ /*! @name MCS1_CH2_IRQ_NOTIFY - MCS[i] channel x interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH2_IRQ_NOTIFY_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH2_IRQ_NOTIFY_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH2_IRQ_NOTIFY_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH2_IRQ_NOTIFY_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_IRQ_NOTIFY_MCS_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_IRQ_NOTIFY_MCS_IRQ_MASK) #define GTM_gtm_cls1_MCS1_CH2_IRQ_NOTIFY_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH2_IRQ_NOTIFY_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH2_IRQ_NOTIFY_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH2_IRQ_NOTIFY_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_IRQ_NOTIFY_ERR_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_IRQ_NOTIFY_ERR_IRQ_MASK) /*! @} */ /*! @name MCS1_CH2_IRQ_EN - MCS[i] channel x interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH2_IRQ_EN_MCS_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH2_IRQ_EN_MCS_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH2_IRQ_EN_MCS_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH2_IRQ_EN_MCS_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_IRQ_EN_MCS_IRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_IRQ_EN_MCS_IRQ_EN_MASK) #define GTM_gtm_cls1_MCS1_CH2_IRQ_EN_ERR_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH2_IRQ_EN_ERR_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH2_IRQ_EN_ERR_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH2_IRQ_EN_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_IRQ_EN_ERR_IRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_IRQ_EN_ERR_IRQ_EN_MASK) /*! @} */ /*! @name MCS1_CH2_IRQ_FORCINT - MCS[i] channel x force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH2_IRQ_FORCINT_TRG_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH2_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH2_IRQ_FORCINT_TRG_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH2_IRQ_FORCINT_TRG_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_IRQ_FORCINT_TRG_MCS_IRQ_MASK) #define GTM_gtm_cls1_MCS1_CH2_IRQ_FORCINT_TRG_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH2_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH2_IRQ_FORCINT_TRG_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH2_IRQ_FORCINT_TRG_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_IRQ_FORCINT_TRG_ERR_IRQ_MASK) /*! @} */ /*! @name MCS1_CH2_IRQ_MODE - MCS[i] channel x IRQ mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH2_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_MCS1_CH2_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH2_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_MCS1_CH2_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name MCS1_CH2_EIRQ_EN - MCS[i] channel x error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH2_EIRQ_EN_MCS_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH2_EIRQ_EN_MCS_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH2_EIRQ_EN_MCS_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH2_EIRQ_EN_MCS_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_EIRQ_EN_MCS_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_EIRQ_EN_MCS_EIRQ_EN_MASK) #define GTM_gtm_cls1_MCS1_CH2_EIRQ_EN_ERR_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH2_EIRQ_EN_ERR_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH2_EIRQ_EN_ERR_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH2_EIRQ_EN_ERR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH2_EIRQ_EN_ERR_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH2_EIRQ_EN_ERR_EIRQ_EN_MASK) /*! @} */ /*! @name MCS1_CH3_R0 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH3_R0_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH3_R0_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH3_R0_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH3_R0_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_R0_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_R0_DATA_MASK) /*! @} */ /*! @name MCS1_CH3_R1 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH3_R1_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH3_R1_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH3_R1_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH3_R1_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_R1_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_R1_DATA_MASK) /*! @} */ /*! @name MCS1_CH3_R2 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH3_R2_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH3_R2_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH3_R2_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH3_R2_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_R2_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_R2_DATA_MASK) /*! @} */ /*! @name MCS1_CH3_R3 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH3_R3_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH3_R3_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH3_R3_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH3_R3_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_R3_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_R3_DATA_MASK) /*! @} */ /*! @name MCS1_CH3_R4 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH3_R4_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH3_R4_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH3_R4_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH3_R4_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_R4_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_R4_DATA_MASK) /*! @} */ /*! @name MCS1_CH3_R5 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH3_R5_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH3_R5_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH3_R5_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH3_R5_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_R5_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_R5_DATA_MASK) /*! @} */ /*! @name MCS1_CH3_R6 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH3_R6_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH3_R6_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH3_R6_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH3_R6_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_R6_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_R6_DATA_MASK) /*! @} */ /*! @name MCS1_CH3_R7 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH3_R7_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH3_R7_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH3_R7_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH3_R7_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_R7_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_R7_DATA_MASK) /*! @} */ /*! @name MCS1_CH3_CTRL - MCS[i] channel x control register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH3_CTRL_EN_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH3_CTRL_EN_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH3_CTRL_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH3_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_CTRL_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_CTRL_EN_MASK) #define GTM_gtm_cls1_MCS1_CH3_CTRL_IRQ_MASK (0x2U) #define GTM_gtm_cls1_MCS1_CH3_CTRL_IRQ_SHIFT (1U) #define GTM_gtm_cls1_MCS1_CH3_CTRL_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH3_CTRL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_CTRL_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_CTRL_IRQ_MASK) #define GTM_gtm_cls1_MCS1_CH3_CTRL_ERR_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH3_CTRL_ERR_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH3_CTRL_ERR_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH3_CTRL_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_CTRL_ERR_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_CTRL_ERR_MASK) #define GTM_gtm_cls1_MCS1_CH3_CTRL_CY_MASK (0x10U) #define GTM_gtm_cls1_MCS1_CH3_CTRL_CY_SHIFT (4U) #define GTM_gtm_cls1_MCS1_CH3_CTRL_CY_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH3_CTRL_CY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_CTRL_CY_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_CTRL_CY_MASK) #define GTM_gtm_cls1_MCS1_CH3_CTRL_Z_MASK (0x20U) #define GTM_gtm_cls1_MCS1_CH3_CTRL_Z_SHIFT (5U) #define GTM_gtm_cls1_MCS1_CH3_CTRL_Z_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH3_CTRL_Z(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_CTRL_Z_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_CTRL_Z_MASK) #define GTM_gtm_cls1_MCS1_CH3_CTRL_V_MASK (0x40U) #define GTM_gtm_cls1_MCS1_CH3_CTRL_V_SHIFT (6U) #define GTM_gtm_cls1_MCS1_CH3_CTRL_V_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH3_CTRL_V(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_CTRL_V_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_CTRL_V_MASK) #define GTM_gtm_cls1_MCS1_CH3_CTRL_N_MASK (0x80U) #define GTM_gtm_cls1_MCS1_CH3_CTRL_N_SHIFT (7U) #define GTM_gtm_cls1_MCS1_CH3_CTRL_N_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH3_CTRL_N(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_CTRL_N_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_CTRL_N_MASK) #define GTM_gtm_cls1_MCS1_CH3_CTRL_CAT_MASK (0x100U) #define GTM_gtm_cls1_MCS1_CH3_CTRL_CAT_SHIFT (8U) #define GTM_gtm_cls1_MCS1_CH3_CTRL_CAT_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH3_CTRL_CAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_CTRL_CAT_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_CTRL_CAT_MASK) #define GTM_gtm_cls1_MCS1_CH3_CTRL_CWT_MASK (0x200U) #define GTM_gtm_cls1_MCS1_CH3_CTRL_CWT_SHIFT (9U) #define GTM_gtm_cls1_MCS1_CH3_CTRL_CWT_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH3_CTRL_CWT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_CTRL_CWT_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_CTRL_CWT_MASK) #define GTM_gtm_cls1_MCS1_CH3_CTRL_SAT_MASK (0x400U) #define GTM_gtm_cls1_MCS1_CH3_CTRL_SAT_SHIFT (10U) #define GTM_gtm_cls1_MCS1_CH3_CTRL_SAT_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH3_CTRL_SAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_CTRL_SAT_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_CTRL_SAT_MASK) /*! @} */ /*! @name MCS1_CH3_ACB - MCS[i] channel x ARU control Bit register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH3_ACB_ACB0_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH3_ACB_ACB0_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH3_ACB_ACB0_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH3_ACB_ACB0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_ACB_ACB0_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_ACB_ACB0_MASK) #define GTM_gtm_cls1_MCS1_CH3_ACB_ACB1_MASK (0x2U) #define GTM_gtm_cls1_MCS1_CH3_ACB_ACB1_SHIFT (1U) #define GTM_gtm_cls1_MCS1_CH3_ACB_ACB1_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH3_ACB_ACB1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_ACB_ACB1_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_ACB_ACB1_MASK) #define GTM_gtm_cls1_MCS1_CH3_ACB_ACB2_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH3_ACB_ACB2_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH3_ACB_ACB2_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH3_ACB_ACB2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_ACB_ACB2_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_ACB_ACB2_MASK) #define GTM_gtm_cls1_MCS1_CH3_ACB_ACB3_MASK (0x8U) #define GTM_gtm_cls1_MCS1_CH3_ACB_ACB3_SHIFT (3U) #define GTM_gtm_cls1_MCS1_CH3_ACB_ACB3_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH3_ACB_ACB3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_ACB_ACB3_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_ACB_ACB3_MASK) #define GTM_gtm_cls1_MCS1_CH3_ACB_ACB4_MASK (0x10U) #define GTM_gtm_cls1_MCS1_CH3_ACB_ACB4_SHIFT (4U) #define GTM_gtm_cls1_MCS1_CH3_ACB_ACB4_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH3_ACB_ACB4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_ACB_ACB4_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_ACB_ACB4_MASK) /*! @} */ /*! @name MCS1_CH3_MHB - MCS[i] channel x memory high byte register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH3_MHB_DATA_MASK (0xFFU) #define GTM_gtm_cls1_MCS1_CH3_MHB_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH3_MHB_DATA_WIDTH (8U) #define GTM_gtm_cls1_MCS1_CH3_MHB_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_MHB_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_MHB_DATA_MASK) /*! @} */ /*! @name MCS1_CH3_PC - MCS[i] channel x program counter register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH3_PC_PC_MASK (0xFFFFU) #define GTM_gtm_cls1_MCS1_CH3_PC_PC_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH3_PC_PC_WIDTH (16U) #define GTM_gtm_cls1_MCS1_CH3_PC_PC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_PC_PC_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_PC_PC_MASK) /*! @} */ /*! @name MCS1_CH3_IRQ_NOTIFY - MCS[i] channel x interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH3_IRQ_NOTIFY_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH3_IRQ_NOTIFY_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH3_IRQ_NOTIFY_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH3_IRQ_NOTIFY_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_IRQ_NOTIFY_MCS_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_IRQ_NOTIFY_MCS_IRQ_MASK) #define GTM_gtm_cls1_MCS1_CH3_IRQ_NOTIFY_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH3_IRQ_NOTIFY_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH3_IRQ_NOTIFY_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH3_IRQ_NOTIFY_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_IRQ_NOTIFY_ERR_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_IRQ_NOTIFY_ERR_IRQ_MASK) /*! @} */ /*! @name MCS1_CH3_IRQ_EN - MCS[i] channel x interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH3_IRQ_EN_MCS_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH3_IRQ_EN_MCS_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH3_IRQ_EN_MCS_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH3_IRQ_EN_MCS_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_IRQ_EN_MCS_IRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_IRQ_EN_MCS_IRQ_EN_MASK) #define GTM_gtm_cls1_MCS1_CH3_IRQ_EN_ERR_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH3_IRQ_EN_ERR_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH3_IRQ_EN_ERR_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH3_IRQ_EN_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_IRQ_EN_ERR_IRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_IRQ_EN_ERR_IRQ_EN_MASK) /*! @} */ /*! @name MCS1_CH3_IRQ_FORCINT - MCS[i] channel x force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH3_IRQ_FORCINT_TRG_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH3_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH3_IRQ_FORCINT_TRG_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH3_IRQ_FORCINT_TRG_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_IRQ_FORCINT_TRG_MCS_IRQ_MASK) #define GTM_gtm_cls1_MCS1_CH3_IRQ_FORCINT_TRG_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH3_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH3_IRQ_FORCINT_TRG_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH3_IRQ_FORCINT_TRG_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_IRQ_FORCINT_TRG_ERR_IRQ_MASK) /*! @} */ /*! @name MCS1_CH3_IRQ_MODE - MCS[i] channel x IRQ mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH3_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_MCS1_CH3_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH3_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_MCS1_CH3_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name MCS1_CH3_EIRQ_EN - MCS[i] channel x error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH3_EIRQ_EN_MCS_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH3_EIRQ_EN_MCS_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH3_EIRQ_EN_MCS_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH3_EIRQ_EN_MCS_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_EIRQ_EN_MCS_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_EIRQ_EN_MCS_EIRQ_EN_MASK) #define GTM_gtm_cls1_MCS1_CH3_EIRQ_EN_ERR_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH3_EIRQ_EN_ERR_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH3_EIRQ_EN_ERR_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH3_EIRQ_EN_ERR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH3_EIRQ_EN_ERR_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH3_EIRQ_EN_ERR_EIRQ_EN_MASK) /*! @} */ /*! @name MCS1_CH4_R0 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH4_R0_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH4_R0_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH4_R0_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH4_R0_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_R0_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_R0_DATA_MASK) /*! @} */ /*! @name MCS1_CH4_R1 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH4_R1_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH4_R1_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH4_R1_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH4_R1_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_R1_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_R1_DATA_MASK) /*! @} */ /*! @name MCS1_CH4_R2 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH4_R2_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH4_R2_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH4_R2_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH4_R2_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_R2_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_R2_DATA_MASK) /*! @} */ /*! @name MCS1_CH4_R3 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH4_R3_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH4_R3_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH4_R3_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH4_R3_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_R3_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_R3_DATA_MASK) /*! @} */ /*! @name MCS1_CH4_R4 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH4_R4_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH4_R4_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH4_R4_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH4_R4_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_R4_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_R4_DATA_MASK) /*! @} */ /*! @name MCS1_CH4_R5 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH4_R5_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH4_R5_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH4_R5_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH4_R5_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_R5_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_R5_DATA_MASK) /*! @} */ /*! @name MCS1_CH4_R6 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH4_R6_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH4_R6_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH4_R6_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH4_R6_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_R6_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_R6_DATA_MASK) /*! @} */ /*! @name MCS1_CH4_R7 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH4_R7_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH4_R7_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH4_R7_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH4_R7_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_R7_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_R7_DATA_MASK) /*! @} */ /*! @name MCS1_CH4_CTRL - MCS[i] channel x control register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH4_CTRL_EN_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH4_CTRL_EN_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH4_CTRL_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH4_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_CTRL_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_CTRL_EN_MASK) #define GTM_gtm_cls1_MCS1_CH4_CTRL_IRQ_MASK (0x2U) #define GTM_gtm_cls1_MCS1_CH4_CTRL_IRQ_SHIFT (1U) #define GTM_gtm_cls1_MCS1_CH4_CTRL_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH4_CTRL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_CTRL_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_CTRL_IRQ_MASK) #define GTM_gtm_cls1_MCS1_CH4_CTRL_ERR_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH4_CTRL_ERR_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH4_CTRL_ERR_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH4_CTRL_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_CTRL_ERR_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_CTRL_ERR_MASK) #define GTM_gtm_cls1_MCS1_CH4_CTRL_CY_MASK (0x10U) #define GTM_gtm_cls1_MCS1_CH4_CTRL_CY_SHIFT (4U) #define GTM_gtm_cls1_MCS1_CH4_CTRL_CY_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH4_CTRL_CY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_CTRL_CY_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_CTRL_CY_MASK) #define GTM_gtm_cls1_MCS1_CH4_CTRL_Z_MASK (0x20U) #define GTM_gtm_cls1_MCS1_CH4_CTRL_Z_SHIFT (5U) #define GTM_gtm_cls1_MCS1_CH4_CTRL_Z_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH4_CTRL_Z(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_CTRL_Z_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_CTRL_Z_MASK) #define GTM_gtm_cls1_MCS1_CH4_CTRL_V_MASK (0x40U) #define GTM_gtm_cls1_MCS1_CH4_CTRL_V_SHIFT (6U) #define GTM_gtm_cls1_MCS1_CH4_CTRL_V_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH4_CTRL_V(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_CTRL_V_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_CTRL_V_MASK) #define GTM_gtm_cls1_MCS1_CH4_CTRL_N_MASK (0x80U) #define GTM_gtm_cls1_MCS1_CH4_CTRL_N_SHIFT (7U) #define GTM_gtm_cls1_MCS1_CH4_CTRL_N_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH4_CTRL_N(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_CTRL_N_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_CTRL_N_MASK) #define GTM_gtm_cls1_MCS1_CH4_CTRL_CAT_MASK (0x100U) #define GTM_gtm_cls1_MCS1_CH4_CTRL_CAT_SHIFT (8U) #define GTM_gtm_cls1_MCS1_CH4_CTRL_CAT_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH4_CTRL_CAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_CTRL_CAT_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_CTRL_CAT_MASK) #define GTM_gtm_cls1_MCS1_CH4_CTRL_CWT_MASK (0x200U) #define GTM_gtm_cls1_MCS1_CH4_CTRL_CWT_SHIFT (9U) #define GTM_gtm_cls1_MCS1_CH4_CTRL_CWT_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH4_CTRL_CWT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_CTRL_CWT_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_CTRL_CWT_MASK) #define GTM_gtm_cls1_MCS1_CH4_CTRL_SAT_MASK (0x400U) #define GTM_gtm_cls1_MCS1_CH4_CTRL_SAT_SHIFT (10U) #define GTM_gtm_cls1_MCS1_CH4_CTRL_SAT_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH4_CTRL_SAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_CTRL_SAT_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_CTRL_SAT_MASK) /*! @} */ /*! @name MCS1_CH4_ACB - MCS[i] channel x ARU control Bit register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH4_ACB_ACB0_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH4_ACB_ACB0_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH4_ACB_ACB0_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH4_ACB_ACB0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_ACB_ACB0_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_ACB_ACB0_MASK) #define GTM_gtm_cls1_MCS1_CH4_ACB_ACB1_MASK (0x2U) #define GTM_gtm_cls1_MCS1_CH4_ACB_ACB1_SHIFT (1U) #define GTM_gtm_cls1_MCS1_CH4_ACB_ACB1_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH4_ACB_ACB1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_ACB_ACB1_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_ACB_ACB1_MASK) #define GTM_gtm_cls1_MCS1_CH4_ACB_ACB2_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH4_ACB_ACB2_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH4_ACB_ACB2_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH4_ACB_ACB2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_ACB_ACB2_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_ACB_ACB2_MASK) #define GTM_gtm_cls1_MCS1_CH4_ACB_ACB3_MASK (0x8U) #define GTM_gtm_cls1_MCS1_CH4_ACB_ACB3_SHIFT (3U) #define GTM_gtm_cls1_MCS1_CH4_ACB_ACB3_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH4_ACB_ACB3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_ACB_ACB3_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_ACB_ACB3_MASK) #define GTM_gtm_cls1_MCS1_CH4_ACB_ACB4_MASK (0x10U) #define GTM_gtm_cls1_MCS1_CH4_ACB_ACB4_SHIFT (4U) #define GTM_gtm_cls1_MCS1_CH4_ACB_ACB4_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH4_ACB_ACB4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_ACB_ACB4_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_ACB_ACB4_MASK) /*! @} */ /*! @name MCS1_CH4_MHB - MCS[i] channel x memory high byte register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH4_MHB_DATA_MASK (0xFFU) #define GTM_gtm_cls1_MCS1_CH4_MHB_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH4_MHB_DATA_WIDTH (8U) #define GTM_gtm_cls1_MCS1_CH4_MHB_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_MHB_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_MHB_DATA_MASK) /*! @} */ /*! @name MCS1_CH4_PC - MCS[i] channel x program counter register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH4_PC_PC_MASK (0xFFFFU) #define GTM_gtm_cls1_MCS1_CH4_PC_PC_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH4_PC_PC_WIDTH (16U) #define GTM_gtm_cls1_MCS1_CH4_PC_PC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_PC_PC_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_PC_PC_MASK) /*! @} */ /*! @name MCS1_CH4_IRQ_NOTIFY - MCS[i] channel x interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH4_IRQ_NOTIFY_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH4_IRQ_NOTIFY_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH4_IRQ_NOTIFY_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH4_IRQ_NOTIFY_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_IRQ_NOTIFY_MCS_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_IRQ_NOTIFY_MCS_IRQ_MASK) #define GTM_gtm_cls1_MCS1_CH4_IRQ_NOTIFY_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH4_IRQ_NOTIFY_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH4_IRQ_NOTIFY_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH4_IRQ_NOTIFY_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_IRQ_NOTIFY_ERR_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_IRQ_NOTIFY_ERR_IRQ_MASK) /*! @} */ /*! @name MCS1_CH4_IRQ_EN - MCS[i] channel x interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH4_IRQ_EN_MCS_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH4_IRQ_EN_MCS_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH4_IRQ_EN_MCS_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH4_IRQ_EN_MCS_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_IRQ_EN_MCS_IRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_IRQ_EN_MCS_IRQ_EN_MASK) #define GTM_gtm_cls1_MCS1_CH4_IRQ_EN_ERR_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH4_IRQ_EN_ERR_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH4_IRQ_EN_ERR_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH4_IRQ_EN_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_IRQ_EN_ERR_IRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_IRQ_EN_ERR_IRQ_EN_MASK) /*! @} */ /*! @name MCS1_CH4_IRQ_FORCINT - MCS[i] channel x force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH4_IRQ_FORCINT_TRG_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH4_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH4_IRQ_FORCINT_TRG_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH4_IRQ_FORCINT_TRG_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_IRQ_FORCINT_TRG_MCS_IRQ_MASK) #define GTM_gtm_cls1_MCS1_CH4_IRQ_FORCINT_TRG_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH4_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH4_IRQ_FORCINT_TRG_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH4_IRQ_FORCINT_TRG_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_IRQ_FORCINT_TRG_ERR_IRQ_MASK) /*! @} */ /*! @name MCS1_CH4_IRQ_MODE - MCS[i] channel x IRQ mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH4_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_MCS1_CH4_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH4_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_MCS1_CH4_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name MCS1_CH4_EIRQ_EN - MCS[i] channel x error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH4_EIRQ_EN_MCS_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH4_EIRQ_EN_MCS_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH4_EIRQ_EN_MCS_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH4_EIRQ_EN_MCS_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_EIRQ_EN_MCS_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_EIRQ_EN_MCS_EIRQ_EN_MASK) #define GTM_gtm_cls1_MCS1_CH4_EIRQ_EN_ERR_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH4_EIRQ_EN_ERR_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH4_EIRQ_EN_ERR_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH4_EIRQ_EN_ERR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH4_EIRQ_EN_ERR_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH4_EIRQ_EN_ERR_EIRQ_EN_MASK) /*! @} */ /*! @name MCS1_CH5_R0 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH5_R0_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH5_R0_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH5_R0_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH5_R0_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_R0_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_R0_DATA_MASK) /*! @} */ /*! @name MCS1_CH5_R1 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH5_R1_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH5_R1_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH5_R1_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH5_R1_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_R1_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_R1_DATA_MASK) /*! @} */ /*! @name MCS1_CH5_R2 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH5_R2_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH5_R2_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH5_R2_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH5_R2_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_R2_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_R2_DATA_MASK) /*! @} */ /*! @name MCS1_CH5_R3 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH5_R3_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH5_R3_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH5_R3_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH5_R3_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_R3_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_R3_DATA_MASK) /*! @} */ /*! @name MCS1_CH5_R4 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH5_R4_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH5_R4_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH5_R4_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH5_R4_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_R4_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_R4_DATA_MASK) /*! @} */ /*! @name MCS1_CH5_R5 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH5_R5_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH5_R5_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH5_R5_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH5_R5_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_R5_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_R5_DATA_MASK) /*! @} */ /*! @name MCS1_CH5_R6 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH5_R6_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH5_R6_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH5_R6_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH5_R6_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_R6_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_R6_DATA_MASK) /*! @} */ /*! @name MCS1_CH5_R7 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH5_R7_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH5_R7_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH5_R7_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH5_R7_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_R7_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_R7_DATA_MASK) /*! @} */ /*! @name MCS1_CH5_CTRL - MCS[i] channel x control register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH5_CTRL_EN_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH5_CTRL_EN_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH5_CTRL_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH5_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_CTRL_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_CTRL_EN_MASK) #define GTM_gtm_cls1_MCS1_CH5_CTRL_IRQ_MASK (0x2U) #define GTM_gtm_cls1_MCS1_CH5_CTRL_IRQ_SHIFT (1U) #define GTM_gtm_cls1_MCS1_CH5_CTRL_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH5_CTRL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_CTRL_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_CTRL_IRQ_MASK) #define GTM_gtm_cls1_MCS1_CH5_CTRL_ERR_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH5_CTRL_ERR_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH5_CTRL_ERR_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH5_CTRL_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_CTRL_ERR_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_CTRL_ERR_MASK) #define GTM_gtm_cls1_MCS1_CH5_CTRL_CY_MASK (0x10U) #define GTM_gtm_cls1_MCS1_CH5_CTRL_CY_SHIFT (4U) #define GTM_gtm_cls1_MCS1_CH5_CTRL_CY_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH5_CTRL_CY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_CTRL_CY_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_CTRL_CY_MASK) #define GTM_gtm_cls1_MCS1_CH5_CTRL_Z_MASK (0x20U) #define GTM_gtm_cls1_MCS1_CH5_CTRL_Z_SHIFT (5U) #define GTM_gtm_cls1_MCS1_CH5_CTRL_Z_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH5_CTRL_Z(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_CTRL_Z_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_CTRL_Z_MASK) #define GTM_gtm_cls1_MCS1_CH5_CTRL_V_MASK (0x40U) #define GTM_gtm_cls1_MCS1_CH5_CTRL_V_SHIFT (6U) #define GTM_gtm_cls1_MCS1_CH5_CTRL_V_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH5_CTRL_V(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_CTRL_V_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_CTRL_V_MASK) #define GTM_gtm_cls1_MCS1_CH5_CTRL_N_MASK (0x80U) #define GTM_gtm_cls1_MCS1_CH5_CTRL_N_SHIFT (7U) #define GTM_gtm_cls1_MCS1_CH5_CTRL_N_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH5_CTRL_N(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_CTRL_N_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_CTRL_N_MASK) #define GTM_gtm_cls1_MCS1_CH5_CTRL_CAT_MASK (0x100U) #define GTM_gtm_cls1_MCS1_CH5_CTRL_CAT_SHIFT (8U) #define GTM_gtm_cls1_MCS1_CH5_CTRL_CAT_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH5_CTRL_CAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_CTRL_CAT_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_CTRL_CAT_MASK) #define GTM_gtm_cls1_MCS1_CH5_CTRL_CWT_MASK (0x200U) #define GTM_gtm_cls1_MCS1_CH5_CTRL_CWT_SHIFT (9U) #define GTM_gtm_cls1_MCS1_CH5_CTRL_CWT_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH5_CTRL_CWT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_CTRL_CWT_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_CTRL_CWT_MASK) #define GTM_gtm_cls1_MCS1_CH5_CTRL_SAT_MASK (0x400U) #define GTM_gtm_cls1_MCS1_CH5_CTRL_SAT_SHIFT (10U) #define GTM_gtm_cls1_MCS1_CH5_CTRL_SAT_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH5_CTRL_SAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_CTRL_SAT_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_CTRL_SAT_MASK) /*! @} */ /*! @name MCS1_CH5_ACB - MCS[i] channel x ARU control Bit register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH5_ACB_ACB0_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH5_ACB_ACB0_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH5_ACB_ACB0_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH5_ACB_ACB0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_ACB_ACB0_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_ACB_ACB0_MASK) #define GTM_gtm_cls1_MCS1_CH5_ACB_ACB1_MASK (0x2U) #define GTM_gtm_cls1_MCS1_CH5_ACB_ACB1_SHIFT (1U) #define GTM_gtm_cls1_MCS1_CH5_ACB_ACB1_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH5_ACB_ACB1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_ACB_ACB1_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_ACB_ACB1_MASK) #define GTM_gtm_cls1_MCS1_CH5_ACB_ACB2_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH5_ACB_ACB2_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH5_ACB_ACB2_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH5_ACB_ACB2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_ACB_ACB2_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_ACB_ACB2_MASK) #define GTM_gtm_cls1_MCS1_CH5_ACB_ACB3_MASK (0x8U) #define GTM_gtm_cls1_MCS1_CH5_ACB_ACB3_SHIFT (3U) #define GTM_gtm_cls1_MCS1_CH5_ACB_ACB3_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH5_ACB_ACB3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_ACB_ACB3_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_ACB_ACB3_MASK) #define GTM_gtm_cls1_MCS1_CH5_ACB_ACB4_MASK (0x10U) #define GTM_gtm_cls1_MCS1_CH5_ACB_ACB4_SHIFT (4U) #define GTM_gtm_cls1_MCS1_CH5_ACB_ACB4_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH5_ACB_ACB4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_ACB_ACB4_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_ACB_ACB4_MASK) /*! @} */ /*! @name MCS1_CH5_MHB - MCS[i] channel x memory high byte register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH5_MHB_DATA_MASK (0xFFU) #define GTM_gtm_cls1_MCS1_CH5_MHB_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH5_MHB_DATA_WIDTH (8U) #define GTM_gtm_cls1_MCS1_CH5_MHB_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_MHB_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_MHB_DATA_MASK) /*! @} */ /*! @name MCS1_CH5_PC - MCS[i] channel x program counter register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH5_PC_PC_MASK (0xFFFFU) #define GTM_gtm_cls1_MCS1_CH5_PC_PC_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH5_PC_PC_WIDTH (16U) #define GTM_gtm_cls1_MCS1_CH5_PC_PC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_PC_PC_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_PC_PC_MASK) /*! @} */ /*! @name MCS1_CH5_IRQ_NOTIFY - MCS[i] channel x interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH5_IRQ_NOTIFY_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH5_IRQ_NOTIFY_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH5_IRQ_NOTIFY_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH5_IRQ_NOTIFY_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_IRQ_NOTIFY_MCS_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_IRQ_NOTIFY_MCS_IRQ_MASK) #define GTM_gtm_cls1_MCS1_CH5_IRQ_NOTIFY_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH5_IRQ_NOTIFY_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH5_IRQ_NOTIFY_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH5_IRQ_NOTIFY_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_IRQ_NOTIFY_ERR_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_IRQ_NOTIFY_ERR_IRQ_MASK) /*! @} */ /*! @name MCS1_CH5_IRQ_EN - MCS[i] channel x interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH5_IRQ_EN_MCS_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH5_IRQ_EN_MCS_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH5_IRQ_EN_MCS_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH5_IRQ_EN_MCS_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_IRQ_EN_MCS_IRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_IRQ_EN_MCS_IRQ_EN_MASK) #define GTM_gtm_cls1_MCS1_CH5_IRQ_EN_ERR_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH5_IRQ_EN_ERR_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH5_IRQ_EN_ERR_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH5_IRQ_EN_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_IRQ_EN_ERR_IRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_IRQ_EN_ERR_IRQ_EN_MASK) /*! @} */ /*! @name MCS1_CH5_IRQ_FORCINT - MCS[i] channel x force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH5_IRQ_FORCINT_TRG_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH5_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH5_IRQ_FORCINT_TRG_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH5_IRQ_FORCINT_TRG_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_IRQ_FORCINT_TRG_MCS_IRQ_MASK) #define GTM_gtm_cls1_MCS1_CH5_IRQ_FORCINT_TRG_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH5_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH5_IRQ_FORCINT_TRG_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH5_IRQ_FORCINT_TRG_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_IRQ_FORCINT_TRG_ERR_IRQ_MASK) /*! @} */ /*! @name MCS1_CH5_IRQ_MODE - MCS[i] channel x IRQ mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH5_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_MCS1_CH5_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH5_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_MCS1_CH5_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name MCS1_CH5_EIRQ_EN - MCS[i] channel x error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH5_EIRQ_EN_MCS_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH5_EIRQ_EN_MCS_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH5_EIRQ_EN_MCS_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH5_EIRQ_EN_MCS_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_EIRQ_EN_MCS_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_EIRQ_EN_MCS_EIRQ_EN_MASK) #define GTM_gtm_cls1_MCS1_CH5_EIRQ_EN_ERR_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH5_EIRQ_EN_ERR_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH5_EIRQ_EN_ERR_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH5_EIRQ_EN_ERR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH5_EIRQ_EN_ERR_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH5_EIRQ_EN_ERR_EIRQ_EN_MASK) /*! @} */ /*! @name MCS1_CH6_R0 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH6_R0_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH6_R0_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH6_R0_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH6_R0_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_R0_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_R0_DATA_MASK) /*! @} */ /*! @name MCS1_CH6_R1 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH6_R1_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH6_R1_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH6_R1_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH6_R1_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_R1_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_R1_DATA_MASK) /*! @} */ /*! @name MCS1_CH6_R2 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH6_R2_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH6_R2_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH6_R2_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH6_R2_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_R2_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_R2_DATA_MASK) /*! @} */ /*! @name MCS1_CH6_R3 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH6_R3_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH6_R3_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH6_R3_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH6_R3_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_R3_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_R3_DATA_MASK) /*! @} */ /*! @name MCS1_CH6_R4 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH6_R4_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH6_R4_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH6_R4_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH6_R4_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_R4_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_R4_DATA_MASK) /*! @} */ /*! @name MCS1_CH6_R5 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH6_R5_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH6_R5_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH6_R5_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH6_R5_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_R5_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_R5_DATA_MASK) /*! @} */ /*! @name MCS1_CH6_R6 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH6_R6_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH6_R6_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH6_R6_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH6_R6_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_R6_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_R6_DATA_MASK) /*! @} */ /*! @name MCS1_CH6_R7 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH6_R7_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH6_R7_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH6_R7_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH6_R7_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_R7_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_R7_DATA_MASK) /*! @} */ /*! @name MCS1_CH6_CTRL - MCS[i] channel x control register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH6_CTRL_EN_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH6_CTRL_EN_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH6_CTRL_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH6_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_CTRL_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_CTRL_EN_MASK) #define GTM_gtm_cls1_MCS1_CH6_CTRL_IRQ_MASK (0x2U) #define GTM_gtm_cls1_MCS1_CH6_CTRL_IRQ_SHIFT (1U) #define GTM_gtm_cls1_MCS1_CH6_CTRL_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH6_CTRL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_CTRL_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_CTRL_IRQ_MASK) #define GTM_gtm_cls1_MCS1_CH6_CTRL_ERR_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH6_CTRL_ERR_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH6_CTRL_ERR_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH6_CTRL_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_CTRL_ERR_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_CTRL_ERR_MASK) #define GTM_gtm_cls1_MCS1_CH6_CTRL_CY_MASK (0x10U) #define GTM_gtm_cls1_MCS1_CH6_CTRL_CY_SHIFT (4U) #define GTM_gtm_cls1_MCS1_CH6_CTRL_CY_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH6_CTRL_CY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_CTRL_CY_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_CTRL_CY_MASK) #define GTM_gtm_cls1_MCS1_CH6_CTRL_Z_MASK (0x20U) #define GTM_gtm_cls1_MCS1_CH6_CTRL_Z_SHIFT (5U) #define GTM_gtm_cls1_MCS1_CH6_CTRL_Z_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH6_CTRL_Z(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_CTRL_Z_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_CTRL_Z_MASK) #define GTM_gtm_cls1_MCS1_CH6_CTRL_V_MASK (0x40U) #define GTM_gtm_cls1_MCS1_CH6_CTRL_V_SHIFT (6U) #define GTM_gtm_cls1_MCS1_CH6_CTRL_V_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH6_CTRL_V(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_CTRL_V_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_CTRL_V_MASK) #define GTM_gtm_cls1_MCS1_CH6_CTRL_N_MASK (0x80U) #define GTM_gtm_cls1_MCS1_CH6_CTRL_N_SHIFT (7U) #define GTM_gtm_cls1_MCS1_CH6_CTRL_N_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH6_CTRL_N(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_CTRL_N_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_CTRL_N_MASK) #define GTM_gtm_cls1_MCS1_CH6_CTRL_CAT_MASK (0x100U) #define GTM_gtm_cls1_MCS1_CH6_CTRL_CAT_SHIFT (8U) #define GTM_gtm_cls1_MCS1_CH6_CTRL_CAT_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH6_CTRL_CAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_CTRL_CAT_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_CTRL_CAT_MASK) #define GTM_gtm_cls1_MCS1_CH6_CTRL_CWT_MASK (0x200U) #define GTM_gtm_cls1_MCS1_CH6_CTRL_CWT_SHIFT (9U) #define GTM_gtm_cls1_MCS1_CH6_CTRL_CWT_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH6_CTRL_CWT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_CTRL_CWT_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_CTRL_CWT_MASK) #define GTM_gtm_cls1_MCS1_CH6_CTRL_SAT_MASK (0x400U) #define GTM_gtm_cls1_MCS1_CH6_CTRL_SAT_SHIFT (10U) #define GTM_gtm_cls1_MCS1_CH6_CTRL_SAT_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH6_CTRL_SAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_CTRL_SAT_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_CTRL_SAT_MASK) /*! @} */ /*! @name MCS1_CH6_ACB - MCS[i] channel x ARU control Bit register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH6_ACB_ACB0_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH6_ACB_ACB0_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH6_ACB_ACB0_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH6_ACB_ACB0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_ACB_ACB0_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_ACB_ACB0_MASK) #define GTM_gtm_cls1_MCS1_CH6_ACB_ACB1_MASK (0x2U) #define GTM_gtm_cls1_MCS1_CH6_ACB_ACB1_SHIFT (1U) #define GTM_gtm_cls1_MCS1_CH6_ACB_ACB1_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH6_ACB_ACB1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_ACB_ACB1_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_ACB_ACB1_MASK) #define GTM_gtm_cls1_MCS1_CH6_ACB_ACB2_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH6_ACB_ACB2_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH6_ACB_ACB2_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH6_ACB_ACB2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_ACB_ACB2_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_ACB_ACB2_MASK) #define GTM_gtm_cls1_MCS1_CH6_ACB_ACB3_MASK (0x8U) #define GTM_gtm_cls1_MCS1_CH6_ACB_ACB3_SHIFT (3U) #define GTM_gtm_cls1_MCS1_CH6_ACB_ACB3_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH6_ACB_ACB3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_ACB_ACB3_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_ACB_ACB3_MASK) #define GTM_gtm_cls1_MCS1_CH6_ACB_ACB4_MASK (0x10U) #define GTM_gtm_cls1_MCS1_CH6_ACB_ACB4_SHIFT (4U) #define GTM_gtm_cls1_MCS1_CH6_ACB_ACB4_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH6_ACB_ACB4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_ACB_ACB4_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_ACB_ACB4_MASK) /*! @} */ /*! @name MCS1_CH6_MHB - MCS[i] channel x memory high byte register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH6_MHB_DATA_MASK (0xFFU) #define GTM_gtm_cls1_MCS1_CH6_MHB_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH6_MHB_DATA_WIDTH (8U) #define GTM_gtm_cls1_MCS1_CH6_MHB_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_MHB_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_MHB_DATA_MASK) /*! @} */ /*! @name MCS1_CH6_PC - MCS[i] channel x program counter register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH6_PC_PC_MASK (0xFFFFU) #define GTM_gtm_cls1_MCS1_CH6_PC_PC_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH6_PC_PC_WIDTH (16U) #define GTM_gtm_cls1_MCS1_CH6_PC_PC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_PC_PC_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_PC_PC_MASK) /*! @} */ /*! @name MCS1_CH6_IRQ_NOTIFY - MCS[i] channel x interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH6_IRQ_NOTIFY_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH6_IRQ_NOTIFY_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH6_IRQ_NOTIFY_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH6_IRQ_NOTIFY_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_IRQ_NOTIFY_MCS_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_IRQ_NOTIFY_MCS_IRQ_MASK) #define GTM_gtm_cls1_MCS1_CH6_IRQ_NOTIFY_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH6_IRQ_NOTIFY_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH6_IRQ_NOTIFY_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH6_IRQ_NOTIFY_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_IRQ_NOTIFY_ERR_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_IRQ_NOTIFY_ERR_IRQ_MASK) /*! @} */ /*! @name MCS1_CH6_IRQ_EN - MCS[i] channel x interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH6_IRQ_EN_MCS_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH6_IRQ_EN_MCS_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH6_IRQ_EN_MCS_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH6_IRQ_EN_MCS_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_IRQ_EN_MCS_IRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_IRQ_EN_MCS_IRQ_EN_MASK) #define GTM_gtm_cls1_MCS1_CH6_IRQ_EN_ERR_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH6_IRQ_EN_ERR_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH6_IRQ_EN_ERR_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH6_IRQ_EN_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_IRQ_EN_ERR_IRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_IRQ_EN_ERR_IRQ_EN_MASK) /*! @} */ /*! @name MCS1_CH6_IRQ_FORCINT - MCS[i] channel x force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH6_IRQ_FORCINT_TRG_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH6_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH6_IRQ_FORCINT_TRG_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH6_IRQ_FORCINT_TRG_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_IRQ_FORCINT_TRG_MCS_IRQ_MASK) #define GTM_gtm_cls1_MCS1_CH6_IRQ_FORCINT_TRG_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH6_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH6_IRQ_FORCINT_TRG_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH6_IRQ_FORCINT_TRG_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_IRQ_FORCINT_TRG_ERR_IRQ_MASK) /*! @} */ /*! @name MCS1_CH6_IRQ_MODE - MCS[i] channel x IRQ mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH6_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_MCS1_CH6_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH6_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_MCS1_CH6_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name MCS1_CH6_EIRQ_EN - MCS[i] channel x error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH6_EIRQ_EN_MCS_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH6_EIRQ_EN_MCS_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH6_EIRQ_EN_MCS_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH6_EIRQ_EN_MCS_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_EIRQ_EN_MCS_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_EIRQ_EN_MCS_EIRQ_EN_MASK) #define GTM_gtm_cls1_MCS1_CH6_EIRQ_EN_ERR_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH6_EIRQ_EN_ERR_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH6_EIRQ_EN_ERR_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH6_EIRQ_EN_ERR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH6_EIRQ_EN_ERR_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH6_EIRQ_EN_ERR_EIRQ_EN_MASK) /*! @} */ /*! @name MCS1_CH7_R0 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH7_R0_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH7_R0_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH7_R0_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH7_R0_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_R0_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_R0_DATA_MASK) /*! @} */ /*! @name MCS1_CH7_R1 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH7_R1_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH7_R1_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH7_R1_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH7_R1_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_R1_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_R1_DATA_MASK) /*! @} */ /*! @name MCS1_CH7_R2 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH7_R2_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH7_R2_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH7_R2_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH7_R2_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_R2_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_R2_DATA_MASK) /*! @} */ /*! @name MCS1_CH7_R3 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH7_R3_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH7_R3_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH7_R3_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH7_R3_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_R3_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_R3_DATA_MASK) /*! @} */ /*! @name MCS1_CH7_R4 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH7_R4_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH7_R4_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH7_R4_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH7_R4_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_R4_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_R4_DATA_MASK) /*! @} */ /*! @name MCS1_CH7_R5 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH7_R5_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH7_R5_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH7_R5_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH7_R5_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_R5_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_R5_DATA_MASK) /*! @} */ /*! @name MCS1_CH7_R6 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH7_R6_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH7_R6_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH7_R6_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH7_R6_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_R6_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_R6_DATA_MASK) /*! @} */ /*! @name MCS1_CH7_R7 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH7_R7_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls1_MCS1_CH7_R7_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH7_R7_DATA_WIDTH (24U) #define GTM_gtm_cls1_MCS1_CH7_R7_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_R7_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_R7_DATA_MASK) /*! @} */ /*! @name MCS1_CH7_CTRL - MCS[i] channel x control register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH7_CTRL_EN_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH7_CTRL_EN_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH7_CTRL_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH7_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_CTRL_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_CTRL_EN_MASK) #define GTM_gtm_cls1_MCS1_CH7_CTRL_IRQ_MASK (0x2U) #define GTM_gtm_cls1_MCS1_CH7_CTRL_IRQ_SHIFT (1U) #define GTM_gtm_cls1_MCS1_CH7_CTRL_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH7_CTRL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_CTRL_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_CTRL_IRQ_MASK) #define GTM_gtm_cls1_MCS1_CH7_CTRL_ERR_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH7_CTRL_ERR_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH7_CTRL_ERR_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH7_CTRL_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_CTRL_ERR_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_CTRL_ERR_MASK) #define GTM_gtm_cls1_MCS1_CH7_CTRL_CY_MASK (0x10U) #define GTM_gtm_cls1_MCS1_CH7_CTRL_CY_SHIFT (4U) #define GTM_gtm_cls1_MCS1_CH7_CTRL_CY_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH7_CTRL_CY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_CTRL_CY_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_CTRL_CY_MASK) #define GTM_gtm_cls1_MCS1_CH7_CTRL_Z_MASK (0x20U) #define GTM_gtm_cls1_MCS1_CH7_CTRL_Z_SHIFT (5U) #define GTM_gtm_cls1_MCS1_CH7_CTRL_Z_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH7_CTRL_Z(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_CTRL_Z_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_CTRL_Z_MASK) #define GTM_gtm_cls1_MCS1_CH7_CTRL_V_MASK (0x40U) #define GTM_gtm_cls1_MCS1_CH7_CTRL_V_SHIFT (6U) #define GTM_gtm_cls1_MCS1_CH7_CTRL_V_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH7_CTRL_V(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_CTRL_V_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_CTRL_V_MASK) #define GTM_gtm_cls1_MCS1_CH7_CTRL_N_MASK (0x80U) #define GTM_gtm_cls1_MCS1_CH7_CTRL_N_SHIFT (7U) #define GTM_gtm_cls1_MCS1_CH7_CTRL_N_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH7_CTRL_N(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_CTRL_N_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_CTRL_N_MASK) #define GTM_gtm_cls1_MCS1_CH7_CTRL_CAT_MASK (0x100U) #define GTM_gtm_cls1_MCS1_CH7_CTRL_CAT_SHIFT (8U) #define GTM_gtm_cls1_MCS1_CH7_CTRL_CAT_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH7_CTRL_CAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_CTRL_CAT_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_CTRL_CAT_MASK) #define GTM_gtm_cls1_MCS1_CH7_CTRL_CWT_MASK (0x200U) #define GTM_gtm_cls1_MCS1_CH7_CTRL_CWT_SHIFT (9U) #define GTM_gtm_cls1_MCS1_CH7_CTRL_CWT_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH7_CTRL_CWT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_CTRL_CWT_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_CTRL_CWT_MASK) #define GTM_gtm_cls1_MCS1_CH7_CTRL_SAT_MASK (0x400U) #define GTM_gtm_cls1_MCS1_CH7_CTRL_SAT_SHIFT (10U) #define GTM_gtm_cls1_MCS1_CH7_CTRL_SAT_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH7_CTRL_SAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_CTRL_SAT_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_CTRL_SAT_MASK) /*! @} */ /*! @name MCS1_CH7_ACB - MCS[i] channel x ARU control Bit register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH7_ACB_ACB0_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH7_ACB_ACB0_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH7_ACB_ACB0_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH7_ACB_ACB0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_ACB_ACB0_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_ACB_ACB0_MASK) #define GTM_gtm_cls1_MCS1_CH7_ACB_ACB1_MASK (0x2U) #define GTM_gtm_cls1_MCS1_CH7_ACB_ACB1_SHIFT (1U) #define GTM_gtm_cls1_MCS1_CH7_ACB_ACB1_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH7_ACB_ACB1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_ACB_ACB1_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_ACB_ACB1_MASK) #define GTM_gtm_cls1_MCS1_CH7_ACB_ACB2_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH7_ACB_ACB2_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH7_ACB_ACB2_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH7_ACB_ACB2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_ACB_ACB2_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_ACB_ACB2_MASK) #define GTM_gtm_cls1_MCS1_CH7_ACB_ACB3_MASK (0x8U) #define GTM_gtm_cls1_MCS1_CH7_ACB_ACB3_SHIFT (3U) #define GTM_gtm_cls1_MCS1_CH7_ACB_ACB3_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH7_ACB_ACB3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_ACB_ACB3_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_ACB_ACB3_MASK) #define GTM_gtm_cls1_MCS1_CH7_ACB_ACB4_MASK (0x10U) #define GTM_gtm_cls1_MCS1_CH7_ACB_ACB4_SHIFT (4U) #define GTM_gtm_cls1_MCS1_CH7_ACB_ACB4_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH7_ACB_ACB4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_ACB_ACB4_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_ACB_ACB4_MASK) /*! @} */ /*! @name MCS1_CH7_MHB - MCS[i] channel x memory high byte register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH7_MHB_DATA_MASK (0xFFU) #define GTM_gtm_cls1_MCS1_CH7_MHB_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH7_MHB_DATA_WIDTH (8U) #define GTM_gtm_cls1_MCS1_CH7_MHB_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_MHB_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_MHB_DATA_MASK) /*! @} */ /*! @name MCS1_CH7_PC - MCS[i] channel x program counter register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH7_PC_PC_MASK (0xFFFFU) #define GTM_gtm_cls1_MCS1_CH7_PC_PC_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH7_PC_PC_WIDTH (16U) #define GTM_gtm_cls1_MCS1_CH7_PC_PC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_PC_PC_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_PC_PC_MASK) /*! @} */ /*! @name MCS1_CH7_IRQ_NOTIFY - MCS[i] channel x interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH7_IRQ_NOTIFY_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH7_IRQ_NOTIFY_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH7_IRQ_NOTIFY_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH7_IRQ_NOTIFY_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_IRQ_NOTIFY_MCS_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_IRQ_NOTIFY_MCS_IRQ_MASK) #define GTM_gtm_cls1_MCS1_CH7_IRQ_NOTIFY_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH7_IRQ_NOTIFY_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH7_IRQ_NOTIFY_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH7_IRQ_NOTIFY_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_IRQ_NOTIFY_ERR_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_IRQ_NOTIFY_ERR_IRQ_MASK) /*! @} */ /*! @name MCS1_CH7_IRQ_EN - MCS[i] channel x interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH7_IRQ_EN_MCS_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH7_IRQ_EN_MCS_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH7_IRQ_EN_MCS_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH7_IRQ_EN_MCS_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_IRQ_EN_MCS_IRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_IRQ_EN_MCS_IRQ_EN_MASK) #define GTM_gtm_cls1_MCS1_CH7_IRQ_EN_ERR_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH7_IRQ_EN_ERR_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH7_IRQ_EN_ERR_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH7_IRQ_EN_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_IRQ_EN_ERR_IRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_IRQ_EN_ERR_IRQ_EN_MASK) /*! @} */ /*! @name MCS1_CH7_IRQ_FORCINT - MCS[i] channel x force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH7_IRQ_FORCINT_TRG_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH7_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH7_IRQ_FORCINT_TRG_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH7_IRQ_FORCINT_TRG_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_IRQ_FORCINT_TRG_MCS_IRQ_MASK) #define GTM_gtm_cls1_MCS1_CH7_IRQ_FORCINT_TRG_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH7_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH7_IRQ_FORCINT_TRG_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH7_IRQ_FORCINT_TRG_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_IRQ_FORCINT_TRG_ERR_IRQ_MASK) /*! @} */ /*! @name MCS1_CH7_IRQ_MODE - MCS[i] channel x IRQ mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH7_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_MCS1_CH7_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH7_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_MCS1_CH7_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name MCS1_CH7_EIRQ_EN - MCS[i] channel x error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CH7_EIRQ_EN_MCS_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CH7_EIRQ_EN_MCS_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CH7_EIRQ_EN_MCS_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH7_EIRQ_EN_MCS_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_EIRQ_EN_MCS_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_EIRQ_EN_MCS_EIRQ_EN_MASK) #define GTM_gtm_cls1_MCS1_CH7_EIRQ_EN_ERR_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CH7_EIRQ_EN_ERR_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CH7_EIRQ_EN_ERR_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CH7_EIRQ_EN_ERR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CH7_EIRQ_EN_ERR_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_CH7_EIRQ_EN_ERR_EIRQ_EN_MASK) /*! @} */ /*! @name MCS1_CTRG - MCS[i] clear trigger control register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CTRG_TRG0_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CTRG_TRG0_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CTRG_TRG0_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CTRG_TRG0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CTRG_TRG0_SHIFT)) & GTM_gtm_cls1_MCS1_CTRG_TRG0_MASK) #define GTM_gtm_cls1_MCS1_CTRG_TRG1_MASK (0x2U) #define GTM_gtm_cls1_MCS1_CTRG_TRG1_SHIFT (1U) #define GTM_gtm_cls1_MCS1_CTRG_TRG1_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CTRG_TRG1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CTRG_TRG1_SHIFT)) & GTM_gtm_cls1_MCS1_CTRG_TRG1_MASK) #define GTM_gtm_cls1_MCS1_CTRG_TRG2_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CTRG_TRG2_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CTRG_TRG2_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CTRG_TRG2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CTRG_TRG2_SHIFT)) & GTM_gtm_cls1_MCS1_CTRG_TRG2_MASK) #define GTM_gtm_cls1_MCS1_CTRG_TRG3_MASK (0x8U) #define GTM_gtm_cls1_MCS1_CTRG_TRG3_SHIFT (3U) #define GTM_gtm_cls1_MCS1_CTRG_TRG3_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CTRG_TRG3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CTRG_TRG3_SHIFT)) & GTM_gtm_cls1_MCS1_CTRG_TRG3_MASK) #define GTM_gtm_cls1_MCS1_CTRG_TRG4_MASK (0x10U) #define GTM_gtm_cls1_MCS1_CTRG_TRG4_SHIFT (4U) #define GTM_gtm_cls1_MCS1_CTRG_TRG4_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CTRG_TRG4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CTRG_TRG4_SHIFT)) & GTM_gtm_cls1_MCS1_CTRG_TRG4_MASK) #define GTM_gtm_cls1_MCS1_CTRG_TRG5_MASK (0x20U) #define GTM_gtm_cls1_MCS1_CTRG_TRG5_SHIFT (5U) #define GTM_gtm_cls1_MCS1_CTRG_TRG5_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CTRG_TRG5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CTRG_TRG5_SHIFT)) & GTM_gtm_cls1_MCS1_CTRG_TRG5_MASK) #define GTM_gtm_cls1_MCS1_CTRG_TRG6_MASK (0x40U) #define GTM_gtm_cls1_MCS1_CTRG_TRG6_SHIFT (6U) #define GTM_gtm_cls1_MCS1_CTRG_TRG6_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CTRG_TRG6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CTRG_TRG6_SHIFT)) & GTM_gtm_cls1_MCS1_CTRG_TRG6_MASK) #define GTM_gtm_cls1_MCS1_CTRG_TRG7_MASK (0x80U) #define GTM_gtm_cls1_MCS1_CTRG_TRG7_SHIFT (7U) #define GTM_gtm_cls1_MCS1_CTRG_TRG7_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CTRG_TRG7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CTRG_TRG7_SHIFT)) & GTM_gtm_cls1_MCS1_CTRG_TRG7_MASK) #define GTM_gtm_cls1_MCS1_CTRG_TRG8_MASK (0x100U) #define GTM_gtm_cls1_MCS1_CTRG_TRG8_SHIFT (8U) #define GTM_gtm_cls1_MCS1_CTRG_TRG8_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CTRG_TRG8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CTRG_TRG8_SHIFT)) & GTM_gtm_cls1_MCS1_CTRG_TRG8_MASK) #define GTM_gtm_cls1_MCS1_CTRG_TRG9_MASK (0x200U) #define GTM_gtm_cls1_MCS1_CTRG_TRG9_SHIFT (9U) #define GTM_gtm_cls1_MCS1_CTRG_TRG9_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CTRG_TRG9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CTRG_TRG9_SHIFT)) & GTM_gtm_cls1_MCS1_CTRG_TRG9_MASK) #define GTM_gtm_cls1_MCS1_CTRG_TRG10_MASK (0x400U) #define GTM_gtm_cls1_MCS1_CTRG_TRG10_SHIFT (10U) #define GTM_gtm_cls1_MCS1_CTRG_TRG10_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CTRG_TRG10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CTRG_TRG10_SHIFT)) & GTM_gtm_cls1_MCS1_CTRG_TRG10_MASK) #define GTM_gtm_cls1_MCS1_CTRG_TRG11_MASK (0x800U) #define GTM_gtm_cls1_MCS1_CTRG_TRG11_SHIFT (11U) #define GTM_gtm_cls1_MCS1_CTRG_TRG11_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CTRG_TRG11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CTRG_TRG11_SHIFT)) & GTM_gtm_cls1_MCS1_CTRG_TRG11_MASK) #define GTM_gtm_cls1_MCS1_CTRG_TRG12_MASK (0x1000U) #define GTM_gtm_cls1_MCS1_CTRG_TRG12_SHIFT (12U) #define GTM_gtm_cls1_MCS1_CTRG_TRG12_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CTRG_TRG12(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CTRG_TRG12_SHIFT)) & GTM_gtm_cls1_MCS1_CTRG_TRG12_MASK) #define GTM_gtm_cls1_MCS1_CTRG_TRG13_MASK (0x2000U) #define GTM_gtm_cls1_MCS1_CTRG_TRG13_SHIFT (13U) #define GTM_gtm_cls1_MCS1_CTRG_TRG13_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CTRG_TRG13(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CTRG_TRG13_SHIFT)) & GTM_gtm_cls1_MCS1_CTRG_TRG13_MASK) #define GTM_gtm_cls1_MCS1_CTRG_TRG14_MASK (0x4000U) #define GTM_gtm_cls1_MCS1_CTRG_TRG14_SHIFT (14U) #define GTM_gtm_cls1_MCS1_CTRG_TRG14_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CTRG_TRG14(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CTRG_TRG14_SHIFT)) & GTM_gtm_cls1_MCS1_CTRG_TRG14_MASK) #define GTM_gtm_cls1_MCS1_CTRG_TRG15_MASK (0x8000U) #define GTM_gtm_cls1_MCS1_CTRG_TRG15_SHIFT (15U) #define GTM_gtm_cls1_MCS1_CTRG_TRG15_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CTRG_TRG15(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CTRG_TRG15_SHIFT)) & GTM_gtm_cls1_MCS1_CTRG_TRG15_MASK) #define GTM_gtm_cls1_MCS1_CTRG_TRG16_MASK (0x10000U) #define GTM_gtm_cls1_MCS1_CTRG_TRG16_SHIFT (16U) #define GTM_gtm_cls1_MCS1_CTRG_TRG16_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CTRG_TRG16(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CTRG_TRG16_SHIFT)) & GTM_gtm_cls1_MCS1_CTRG_TRG16_MASK) #define GTM_gtm_cls1_MCS1_CTRG_TRG17_MASK (0x20000U) #define GTM_gtm_cls1_MCS1_CTRG_TRG17_SHIFT (17U) #define GTM_gtm_cls1_MCS1_CTRG_TRG17_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CTRG_TRG17(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CTRG_TRG17_SHIFT)) & GTM_gtm_cls1_MCS1_CTRG_TRG17_MASK) #define GTM_gtm_cls1_MCS1_CTRG_TRG18_MASK (0x40000U) #define GTM_gtm_cls1_MCS1_CTRG_TRG18_SHIFT (18U) #define GTM_gtm_cls1_MCS1_CTRG_TRG18_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CTRG_TRG18(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CTRG_TRG18_SHIFT)) & GTM_gtm_cls1_MCS1_CTRG_TRG18_MASK) #define GTM_gtm_cls1_MCS1_CTRG_TRG19_MASK (0x80000U) #define GTM_gtm_cls1_MCS1_CTRG_TRG19_SHIFT (19U) #define GTM_gtm_cls1_MCS1_CTRG_TRG19_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CTRG_TRG19(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CTRG_TRG19_SHIFT)) & GTM_gtm_cls1_MCS1_CTRG_TRG19_MASK) #define GTM_gtm_cls1_MCS1_CTRG_TRG20_MASK (0x100000U) #define GTM_gtm_cls1_MCS1_CTRG_TRG20_SHIFT (20U) #define GTM_gtm_cls1_MCS1_CTRG_TRG20_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CTRG_TRG20(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CTRG_TRG20_SHIFT)) & GTM_gtm_cls1_MCS1_CTRG_TRG20_MASK) #define GTM_gtm_cls1_MCS1_CTRG_TRG21_MASK (0x200000U) #define GTM_gtm_cls1_MCS1_CTRG_TRG21_SHIFT (21U) #define GTM_gtm_cls1_MCS1_CTRG_TRG21_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CTRG_TRG21(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CTRG_TRG21_SHIFT)) & GTM_gtm_cls1_MCS1_CTRG_TRG21_MASK) #define GTM_gtm_cls1_MCS1_CTRG_TRG22_MASK (0x400000U) #define GTM_gtm_cls1_MCS1_CTRG_TRG22_SHIFT (22U) #define GTM_gtm_cls1_MCS1_CTRG_TRG22_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CTRG_TRG22(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CTRG_TRG22_SHIFT)) & GTM_gtm_cls1_MCS1_CTRG_TRG22_MASK) #define GTM_gtm_cls1_MCS1_CTRG_TRG23_MASK (0x800000U) #define GTM_gtm_cls1_MCS1_CTRG_TRG23_SHIFT (23U) #define GTM_gtm_cls1_MCS1_CTRG_TRG23_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CTRG_TRG23(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CTRG_TRG23_SHIFT)) & GTM_gtm_cls1_MCS1_CTRG_TRG23_MASK) /*! @} */ /*! @name MCS1_STRG - MCS[i] set trigger control register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_STRG_TRG0_MASK (0x1U) #define GTM_gtm_cls1_MCS1_STRG_TRG0_SHIFT (0U) #define GTM_gtm_cls1_MCS1_STRG_TRG0_WIDTH (1U) #define GTM_gtm_cls1_MCS1_STRG_TRG0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_STRG_TRG0_SHIFT)) & GTM_gtm_cls1_MCS1_STRG_TRG0_MASK) #define GTM_gtm_cls1_MCS1_STRG_TRG1_MASK (0x2U) #define GTM_gtm_cls1_MCS1_STRG_TRG1_SHIFT (1U) #define GTM_gtm_cls1_MCS1_STRG_TRG1_WIDTH (1U) #define GTM_gtm_cls1_MCS1_STRG_TRG1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_STRG_TRG1_SHIFT)) & GTM_gtm_cls1_MCS1_STRG_TRG1_MASK) #define GTM_gtm_cls1_MCS1_STRG_TRG2_MASK (0x4U) #define GTM_gtm_cls1_MCS1_STRG_TRG2_SHIFT (2U) #define GTM_gtm_cls1_MCS1_STRG_TRG2_WIDTH (1U) #define GTM_gtm_cls1_MCS1_STRG_TRG2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_STRG_TRG2_SHIFT)) & GTM_gtm_cls1_MCS1_STRG_TRG2_MASK) #define GTM_gtm_cls1_MCS1_STRG_TRG3_MASK (0x8U) #define GTM_gtm_cls1_MCS1_STRG_TRG3_SHIFT (3U) #define GTM_gtm_cls1_MCS1_STRG_TRG3_WIDTH (1U) #define GTM_gtm_cls1_MCS1_STRG_TRG3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_STRG_TRG3_SHIFT)) & GTM_gtm_cls1_MCS1_STRG_TRG3_MASK) #define GTM_gtm_cls1_MCS1_STRG_TRG4_MASK (0x10U) #define GTM_gtm_cls1_MCS1_STRG_TRG4_SHIFT (4U) #define GTM_gtm_cls1_MCS1_STRG_TRG4_WIDTH (1U) #define GTM_gtm_cls1_MCS1_STRG_TRG4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_STRG_TRG4_SHIFT)) & GTM_gtm_cls1_MCS1_STRG_TRG4_MASK) #define GTM_gtm_cls1_MCS1_STRG_TRG5_MASK (0x20U) #define GTM_gtm_cls1_MCS1_STRG_TRG5_SHIFT (5U) #define GTM_gtm_cls1_MCS1_STRG_TRG5_WIDTH (1U) #define GTM_gtm_cls1_MCS1_STRG_TRG5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_STRG_TRG5_SHIFT)) & GTM_gtm_cls1_MCS1_STRG_TRG5_MASK) #define GTM_gtm_cls1_MCS1_STRG_TRG6_MASK (0x40U) #define GTM_gtm_cls1_MCS1_STRG_TRG6_SHIFT (6U) #define GTM_gtm_cls1_MCS1_STRG_TRG6_WIDTH (1U) #define GTM_gtm_cls1_MCS1_STRG_TRG6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_STRG_TRG6_SHIFT)) & GTM_gtm_cls1_MCS1_STRG_TRG6_MASK) #define GTM_gtm_cls1_MCS1_STRG_TRG7_MASK (0x80U) #define GTM_gtm_cls1_MCS1_STRG_TRG7_SHIFT (7U) #define GTM_gtm_cls1_MCS1_STRG_TRG7_WIDTH (1U) #define GTM_gtm_cls1_MCS1_STRG_TRG7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_STRG_TRG7_SHIFT)) & GTM_gtm_cls1_MCS1_STRG_TRG7_MASK) #define GTM_gtm_cls1_MCS1_STRG_TRG8_MASK (0x100U) #define GTM_gtm_cls1_MCS1_STRG_TRG8_SHIFT (8U) #define GTM_gtm_cls1_MCS1_STRG_TRG8_WIDTH (1U) #define GTM_gtm_cls1_MCS1_STRG_TRG8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_STRG_TRG8_SHIFT)) & GTM_gtm_cls1_MCS1_STRG_TRG8_MASK) #define GTM_gtm_cls1_MCS1_STRG_TRG9_MASK (0x200U) #define GTM_gtm_cls1_MCS1_STRG_TRG9_SHIFT (9U) #define GTM_gtm_cls1_MCS1_STRG_TRG9_WIDTH (1U) #define GTM_gtm_cls1_MCS1_STRG_TRG9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_STRG_TRG9_SHIFT)) & GTM_gtm_cls1_MCS1_STRG_TRG9_MASK) #define GTM_gtm_cls1_MCS1_STRG_TRG10_MASK (0x400U) #define GTM_gtm_cls1_MCS1_STRG_TRG10_SHIFT (10U) #define GTM_gtm_cls1_MCS1_STRG_TRG10_WIDTH (1U) #define GTM_gtm_cls1_MCS1_STRG_TRG10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_STRG_TRG10_SHIFT)) & GTM_gtm_cls1_MCS1_STRG_TRG10_MASK) #define GTM_gtm_cls1_MCS1_STRG_TRG11_MASK (0x800U) #define GTM_gtm_cls1_MCS1_STRG_TRG11_SHIFT (11U) #define GTM_gtm_cls1_MCS1_STRG_TRG11_WIDTH (1U) #define GTM_gtm_cls1_MCS1_STRG_TRG11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_STRG_TRG11_SHIFT)) & GTM_gtm_cls1_MCS1_STRG_TRG11_MASK) #define GTM_gtm_cls1_MCS1_STRG_TRG12_MASK (0x1000U) #define GTM_gtm_cls1_MCS1_STRG_TRG12_SHIFT (12U) #define GTM_gtm_cls1_MCS1_STRG_TRG12_WIDTH (1U) #define GTM_gtm_cls1_MCS1_STRG_TRG12(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_STRG_TRG12_SHIFT)) & GTM_gtm_cls1_MCS1_STRG_TRG12_MASK) #define GTM_gtm_cls1_MCS1_STRG_TRG13_MASK (0x2000U) #define GTM_gtm_cls1_MCS1_STRG_TRG13_SHIFT (13U) #define GTM_gtm_cls1_MCS1_STRG_TRG13_WIDTH (1U) #define GTM_gtm_cls1_MCS1_STRG_TRG13(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_STRG_TRG13_SHIFT)) & GTM_gtm_cls1_MCS1_STRG_TRG13_MASK) #define GTM_gtm_cls1_MCS1_STRG_TRG14_MASK (0x4000U) #define GTM_gtm_cls1_MCS1_STRG_TRG14_SHIFT (14U) #define GTM_gtm_cls1_MCS1_STRG_TRG14_WIDTH (1U) #define GTM_gtm_cls1_MCS1_STRG_TRG14(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_STRG_TRG14_SHIFT)) & GTM_gtm_cls1_MCS1_STRG_TRG14_MASK) #define GTM_gtm_cls1_MCS1_STRG_TRG15_MASK (0x8000U) #define GTM_gtm_cls1_MCS1_STRG_TRG15_SHIFT (15U) #define GTM_gtm_cls1_MCS1_STRG_TRG15_WIDTH (1U) #define GTM_gtm_cls1_MCS1_STRG_TRG15(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_STRG_TRG15_SHIFT)) & GTM_gtm_cls1_MCS1_STRG_TRG15_MASK) #define GTM_gtm_cls1_MCS1_STRG_TRG16_MASK (0x10000U) #define GTM_gtm_cls1_MCS1_STRG_TRG16_SHIFT (16U) #define GTM_gtm_cls1_MCS1_STRG_TRG16_WIDTH (1U) #define GTM_gtm_cls1_MCS1_STRG_TRG16(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_STRG_TRG16_SHIFT)) & GTM_gtm_cls1_MCS1_STRG_TRG16_MASK) #define GTM_gtm_cls1_MCS1_STRG_TRG17_MASK (0x20000U) #define GTM_gtm_cls1_MCS1_STRG_TRG17_SHIFT (17U) #define GTM_gtm_cls1_MCS1_STRG_TRG17_WIDTH (1U) #define GTM_gtm_cls1_MCS1_STRG_TRG17(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_STRG_TRG17_SHIFT)) & GTM_gtm_cls1_MCS1_STRG_TRG17_MASK) #define GTM_gtm_cls1_MCS1_STRG_TRG18_MASK (0x40000U) #define GTM_gtm_cls1_MCS1_STRG_TRG18_SHIFT (18U) #define GTM_gtm_cls1_MCS1_STRG_TRG18_WIDTH (1U) #define GTM_gtm_cls1_MCS1_STRG_TRG18(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_STRG_TRG18_SHIFT)) & GTM_gtm_cls1_MCS1_STRG_TRG18_MASK) #define GTM_gtm_cls1_MCS1_STRG_TRG19_MASK (0x80000U) #define GTM_gtm_cls1_MCS1_STRG_TRG19_SHIFT (19U) #define GTM_gtm_cls1_MCS1_STRG_TRG19_WIDTH (1U) #define GTM_gtm_cls1_MCS1_STRG_TRG19(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_STRG_TRG19_SHIFT)) & GTM_gtm_cls1_MCS1_STRG_TRG19_MASK) #define GTM_gtm_cls1_MCS1_STRG_TRG20_MASK (0x100000U) #define GTM_gtm_cls1_MCS1_STRG_TRG20_SHIFT (20U) #define GTM_gtm_cls1_MCS1_STRG_TRG20_WIDTH (1U) #define GTM_gtm_cls1_MCS1_STRG_TRG20(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_STRG_TRG20_SHIFT)) & GTM_gtm_cls1_MCS1_STRG_TRG20_MASK) #define GTM_gtm_cls1_MCS1_STRG_TRG21_MASK (0x200000U) #define GTM_gtm_cls1_MCS1_STRG_TRG21_SHIFT (21U) #define GTM_gtm_cls1_MCS1_STRG_TRG21_WIDTH (1U) #define GTM_gtm_cls1_MCS1_STRG_TRG21(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_STRG_TRG21_SHIFT)) & GTM_gtm_cls1_MCS1_STRG_TRG21_MASK) #define GTM_gtm_cls1_MCS1_STRG_TRG22_MASK (0x400000U) #define GTM_gtm_cls1_MCS1_STRG_TRG22_SHIFT (22U) #define GTM_gtm_cls1_MCS1_STRG_TRG22_WIDTH (1U) #define GTM_gtm_cls1_MCS1_STRG_TRG22(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_STRG_TRG22_SHIFT)) & GTM_gtm_cls1_MCS1_STRG_TRG22_MASK) #define GTM_gtm_cls1_MCS1_STRG_TRG23_MASK (0x800000U) #define GTM_gtm_cls1_MCS1_STRG_TRG23_SHIFT (23U) #define GTM_gtm_cls1_MCS1_STRG_TRG23_WIDTH (1U) #define GTM_gtm_cls1_MCS1_STRG_TRG23(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_STRG_TRG23_SHIFT)) & GTM_gtm_cls1_MCS1_STRG_TRG23_MASK) /*! @} */ /*! @name MCS1_CTRL_STAT - MCS[i] control and status register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CTRL_STAT_SCD_MODE_MASK (0x3U) #define GTM_gtm_cls1_MCS1_CTRL_STAT_SCD_MODE_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CTRL_STAT_SCD_MODE_WIDTH (2U) #define GTM_gtm_cls1_MCS1_CTRL_STAT_SCD_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CTRL_STAT_SCD_MODE_SHIFT)) & GTM_gtm_cls1_MCS1_CTRL_STAT_SCD_MODE_MASK) #define GTM_gtm_cls1_MCS1_CTRL_STAT_SCD_CH_MASK (0xF00U) #define GTM_gtm_cls1_MCS1_CTRL_STAT_SCD_CH_SHIFT (8U) #define GTM_gtm_cls1_MCS1_CTRL_STAT_SCD_CH_WIDTH (4U) #define GTM_gtm_cls1_MCS1_CTRL_STAT_SCD_CH(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CTRL_STAT_SCD_CH_SHIFT)) & GTM_gtm_cls1_MCS1_CTRL_STAT_SCD_CH_MASK) #define GTM_gtm_cls1_MCS1_CTRL_STAT_RAM_RST_MASK (0x10000U) #define GTM_gtm_cls1_MCS1_CTRL_STAT_RAM_RST_SHIFT (16U) #define GTM_gtm_cls1_MCS1_CTRL_STAT_RAM_RST_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CTRL_STAT_RAM_RST(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CTRL_STAT_RAM_RST_SHIFT)) & GTM_gtm_cls1_MCS1_CTRL_STAT_RAM_RST_MASK) #define GTM_gtm_cls1_MCS1_CTRL_STAT_ERR_SRC_ID_MASK (0x700000U) #define GTM_gtm_cls1_MCS1_CTRL_STAT_ERR_SRC_ID_SHIFT (20U) #define GTM_gtm_cls1_MCS1_CTRL_STAT_ERR_SRC_ID_WIDTH (3U) #define GTM_gtm_cls1_MCS1_CTRL_STAT_ERR_SRC_ID(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CTRL_STAT_ERR_SRC_ID_SHIFT)) & GTM_gtm_cls1_MCS1_CTRL_STAT_ERR_SRC_ID_MASK) #define GTM_gtm_cls1_MCS1_CTRL_STAT_EN_TIM_FOUT_MASK (0x1000000U) #define GTM_gtm_cls1_MCS1_CTRL_STAT_EN_TIM_FOUT_SHIFT (24U) #define GTM_gtm_cls1_MCS1_CTRL_STAT_EN_TIM_FOUT_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CTRL_STAT_EN_TIM_FOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CTRL_STAT_EN_TIM_FOUT_SHIFT)) & GTM_gtm_cls1_MCS1_CTRL_STAT_EN_TIM_FOUT_MASK) #define GTM_gtm_cls1_MCS1_CTRL_STAT_EN_HVD_MASK (0x2000000U) #define GTM_gtm_cls1_MCS1_CTRL_STAT_EN_HVD_SHIFT (25U) #define GTM_gtm_cls1_MCS1_CTRL_STAT_EN_HVD_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CTRL_STAT_EN_HVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CTRL_STAT_EN_HVD_SHIFT)) & GTM_gtm_cls1_MCS1_CTRL_STAT_EN_HVD_MASK) #define GTM_gtm_cls1_MCS1_CTRL_STAT_HLT_AEIM_ERR_MASK (0x4000000U) #define GTM_gtm_cls1_MCS1_CTRL_STAT_HLT_AEIM_ERR_SHIFT (26U) #define GTM_gtm_cls1_MCS1_CTRL_STAT_HLT_AEIM_ERR_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CTRL_STAT_HLT_AEIM_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CTRL_STAT_HLT_AEIM_ERR_SHIFT)) & GTM_gtm_cls1_MCS1_CTRL_STAT_HLT_AEIM_ERR_MASK) /*! @} */ /*! @name MCS1_RESET - MCS[i] reset register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_RESET_RST0_MASK (0x1U) #define GTM_gtm_cls1_MCS1_RESET_RST0_SHIFT (0U) #define GTM_gtm_cls1_MCS1_RESET_RST0_WIDTH (1U) #define GTM_gtm_cls1_MCS1_RESET_RST0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_RESET_RST0_SHIFT)) & GTM_gtm_cls1_MCS1_RESET_RST0_MASK) #define GTM_gtm_cls1_MCS1_RESET_RST1_MASK (0x2U) #define GTM_gtm_cls1_MCS1_RESET_RST1_SHIFT (1U) #define GTM_gtm_cls1_MCS1_RESET_RST1_WIDTH (1U) #define GTM_gtm_cls1_MCS1_RESET_RST1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_RESET_RST1_SHIFT)) & GTM_gtm_cls1_MCS1_RESET_RST1_MASK) #define GTM_gtm_cls1_MCS1_RESET_RST2_MASK (0x4U) #define GTM_gtm_cls1_MCS1_RESET_RST2_SHIFT (2U) #define GTM_gtm_cls1_MCS1_RESET_RST2_WIDTH (1U) #define GTM_gtm_cls1_MCS1_RESET_RST2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_RESET_RST2_SHIFT)) & GTM_gtm_cls1_MCS1_RESET_RST2_MASK) #define GTM_gtm_cls1_MCS1_RESET_RST3_MASK (0x8U) #define GTM_gtm_cls1_MCS1_RESET_RST3_SHIFT (3U) #define GTM_gtm_cls1_MCS1_RESET_RST3_WIDTH (1U) #define GTM_gtm_cls1_MCS1_RESET_RST3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_RESET_RST3_SHIFT)) & GTM_gtm_cls1_MCS1_RESET_RST3_MASK) #define GTM_gtm_cls1_MCS1_RESET_RST4_MASK (0x10U) #define GTM_gtm_cls1_MCS1_RESET_RST4_SHIFT (4U) #define GTM_gtm_cls1_MCS1_RESET_RST4_WIDTH (1U) #define GTM_gtm_cls1_MCS1_RESET_RST4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_RESET_RST4_SHIFT)) & GTM_gtm_cls1_MCS1_RESET_RST4_MASK) #define GTM_gtm_cls1_MCS1_RESET_RST5_MASK (0x20U) #define GTM_gtm_cls1_MCS1_RESET_RST5_SHIFT (5U) #define GTM_gtm_cls1_MCS1_RESET_RST5_WIDTH (1U) #define GTM_gtm_cls1_MCS1_RESET_RST5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_RESET_RST5_SHIFT)) & GTM_gtm_cls1_MCS1_RESET_RST5_MASK) #define GTM_gtm_cls1_MCS1_RESET_RST6_MASK (0x40U) #define GTM_gtm_cls1_MCS1_RESET_RST6_SHIFT (6U) #define GTM_gtm_cls1_MCS1_RESET_RST6_WIDTH (1U) #define GTM_gtm_cls1_MCS1_RESET_RST6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_RESET_RST6_SHIFT)) & GTM_gtm_cls1_MCS1_RESET_RST6_MASK) #define GTM_gtm_cls1_MCS1_RESET_RST7_MASK (0x80U) #define GTM_gtm_cls1_MCS1_RESET_RST7_SHIFT (7U) #define GTM_gtm_cls1_MCS1_RESET_RST7_WIDTH (1U) #define GTM_gtm_cls1_MCS1_RESET_RST7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_RESET_RST7_SHIFT)) & GTM_gtm_cls1_MCS1_RESET_RST7_MASK) /*! @} */ /*! @name MCS1_CAT - MCS[i] cancel ARU transfer instruction */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CAT_CAT0_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CAT_CAT0_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CAT_CAT0_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CAT_CAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CAT_CAT0_SHIFT)) & GTM_gtm_cls1_MCS1_CAT_CAT0_MASK) #define GTM_gtm_cls1_MCS1_CAT_CAT1_MASK (0x2U) #define GTM_gtm_cls1_MCS1_CAT_CAT1_SHIFT (1U) #define GTM_gtm_cls1_MCS1_CAT_CAT1_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CAT_CAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CAT_CAT1_SHIFT)) & GTM_gtm_cls1_MCS1_CAT_CAT1_MASK) #define GTM_gtm_cls1_MCS1_CAT_CAT2_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CAT_CAT2_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CAT_CAT2_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CAT_CAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CAT_CAT2_SHIFT)) & GTM_gtm_cls1_MCS1_CAT_CAT2_MASK) #define GTM_gtm_cls1_MCS1_CAT_CAT3_MASK (0x8U) #define GTM_gtm_cls1_MCS1_CAT_CAT3_SHIFT (3U) #define GTM_gtm_cls1_MCS1_CAT_CAT3_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CAT_CAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CAT_CAT3_SHIFT)) & GTM_gtm_cls1_MCS1_CAT_CAT3_MASK) #define GTM_gtm_cls1_MCS1_CAT_CAT4_MASK (0x10U) #define GTM_gtm_cls1_MCS1_CAT_CAT4_SHIFT (4U) #define GTM_gtm_cls1_MCS1_CAT_CAT4_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CAT_CAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CAT_CAT4_SHIFT)) & GTM_gtm_cls1_MCS1_CAT_CAT4_MASK) #define GTM_gtm_cls1_MCS1_CAT_CAT5_MASK (0x20U) #define GTM_gtm_cls1_MCS1_CAT_CAT5_SHIFT (5U) #define GTM_gtm_cls1_MCS1_CAT_CAT5_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CAT_CAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CAT_CAT5_SHIFT)) & GTM_gtm_cls1_MCS1_CAT_CAT5_MASK) #define GTM_gtm_cls1_MCS1_CAT_CAT6_MASK (0x40U) #define GTM_gtm_cls1_MCS1_CAT_CAT6_SHIFT (6U) #define GTM_gtm_cls1_MCS1_CAT_CAT6_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CAT_CAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CAT_CAT6_SHIFT)) & GTM_gtm_cls1_MCS1_CAT_CAT6_MASK) #define GTM_gtm_cls1_MCS1_CAT_CAT7_MASK (0x80U) #define GTM_gtm_cls1_MCS1_CAT_CAT7_SHIFT (7U) #define GTM_gtm_cls1_MCS1_CAT_CAT7_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CAT_CAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CAT_CAT7_SHIFT)) & GTM_gtm_cls1_MCS1_CAT_CAT7_MASK) /*! @} */ /*! @name MCS1_CWT - MCS[i] cancel waiting instruction */ /*! @{ */ #define GTM_gtm_cls1_MCS1_CWT_CWT0_MASK (0x1U) #define GTM_gtm_cls1_MCS1_CWT_CWT0_SHIFT (0U) #define GTM_gtm_cls1_MCS1_CWT_CWT0_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CWT_CWT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CWT_CWT0_SHIFT)) & GTM_gtm_cls1_MCS1_CWT_CWT0_MASK) #define GTM_gtm_cls1_MCS1_CWT_CWT1_MASK (0x2U) #define GTM_gtm_cls1_MCS1_CWT_CWT1_SHIFT (1U) #define GTM_gtm_cls1_MCS1_CWT_CWT1_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CWT_CWT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CWT_CWT1_SHIFT)) & GTM_gtm_cls1_MCS1_CWT_CWT1_MASK) #define GTM_gtm_cls1_MCS1_CWT_CWT2_MASK (0x4U) #define GTM_gtm_cls1_MCS1_CWT_CWT2_SHIFT (2U) #define GTM_gtm_cls1_MCS1_CWT_CWT2_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CWT_CWT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CWT_CWT2_SHIFT)) & GTM_gtm_cls1_MCS1_CWT_CWT2_MASK) #define GTM_gtm_cls1_MCS1_CWT_CWT3_MASK (0x8U) #define GTM_gtm_cls1_MCS1_CWT_CWT3_SHIFT (3U) #define GTM_gtm_cls1_MCS1_CWT_CWT3_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CWT_CWT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CWT_CWT3_SHIFT)) & GTM_gtm_cls1_MCS1_CWT_CWT3_MASK) #define GTM_gtm_cls1_MCS1_CWT_CWT4_MASK (0x10U) #define GTM_gtm_cls1_MCS1_CWT_CWT4_SHIFT (4U) #define GTM_gtm_cls1_MCS1_CWT_CWT4_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CWT_CWT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CWT_CWT4_SHIFT)) & GTM_gtm_cls1_MCS1_CWT_CWT4_MASK) #define GTM_gtm_cls1_MCS1_CWT_CWT5_MASK (0x20U) #define GTM_gtm_cls1_MCS1_CWT_CWT5_SHIFT (5U) #define GTM_gtm_cls1_MCS1_CWT_CWT5_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CWT_CWT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CWT_CWT5_SHIFT)) & GTM_gtm_cls1_MCS1_CWT_CWT5_MASK) #define GTM_gtm_cls1_MCS1_CWT_CWT6_MASK (0x40U) #define GTM_gtm_cls1_MCS1_CWT_CWT6_SHIFT (6U) #define GTM_gtm_cls1_MCS1_CWT_CWT6_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CWT_CWT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CWT_CWT6_SHIFT)) & GTM_gtm_cls1_MCS1_CWT_CWT6_MASK) #define GTM_gtm_cls1_MCS1_CWT_CWT7_MASK (0x80U) #define GTM_gtm_cls1_MCS1_CWT_CWT7_SHIFT (7U) #define GTM_gtm_cls1_MCS1_CWT_CWT7_WIDTH (1U) #define GTM_gtm_cls1_MCS1_CWT_CWT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_CWT_CWT7_SHIFT)) & GTM_gtm_cls1_MCS1_CWT_CWT7_MASK) /*! @} */ /*! @name MCS1_ERR - MCS[i] error register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_ERR_ERR0_MASK (0x1U) #define GTM_gtm_cls1_MCS1_ERR_ERR0_SHIFT (0U) #define GTM_gtm_cls1_MCS1_ERR_ERR0_WIDTH (1U) #define GTM_gtm_cls1_MCS1_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_ERR_ERR0_SHIFT)) & GTM_gtm_cls1_MCS1_ERR_ERR0_MASK) #define GTM_gtm_cls1_MCS1_ERR_ERR1_MASK (0x2U) #define GTM_gtm_cls1_MCS1_ERR_ERR1_SHIFT (1U) #define GTM_gtm_cls1_MCS1_ERR_ERR1_WIDTH (1U) #define GTM_gtm_cls1_MCS1_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_ERR_ERR1_SHIFT)) & GTM_gtm_cls1_MCS1_ERR_ERR1_MASK) #define GTM_gtm_cls1_MCS1_ERR_ERR2_MASK (0x4U) #define GTM_gtm_cls1_MCS1_ERR_ERR2_SHIFT (2U) #define GTM_gtm_cls1_MCS1_ERR_ERR2_WIDTH (1U) #define GTM_gtm_cls1_MCS1_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_ERR_ERR2_SHIFT)) & GTM_gtm_cls1_MCS1_ERR_ERR2_MASK) #define GTM_gtm_cls1_MCS1_ERR_ERR3_MASK (0x8U) #define GTM_gtm_cls1_MCS1_ERR_ERR3_SHIFT (3U) #define GTM_gtm_cls1_MCS1_ERR_ERR3_WIDTH (1U) #define GTM_gtm_cls1_MCS1_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_ERR_ERR3_SHIFT)) & GTM_gtm_cls1_MCS1_ERR_ERR3_MASK) #define GTM_gtm_cls1_MCS1_ERR_ERR4_MASK (0x10U) #define GTM_gtm_cls1_MCS1_ERR_ERR4_SHIFT (4U) #define GTM_gtm_cls1_MCS1_ERR_ERR4_WIDTH (1U) #define GTM_gtm_cls1_MCS1_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_ERR_ERR4_SHIFT)) & GTM_gtm_cls1_MCS1_ERR_ERR4_MASK) #define GTM_gtm_cls1_MCS1_ERR_ERR5_MASK (0x20U) #define GTM_gtm_cls1_MCS1_ERR_ERR5_SHIFT (5U) #define GTM_gtm_cls1_MCS1_ERR_ERR5_WIDTH (1U) #define GTM_gtm_cls1_MCS1_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_ERR_ERR5_SHIFT)) & GTM_gtm_cls1_MCS1_ERR_ERR5_MASK) #define GTM_gtm_cls1_MCS1_ERR_ERR6_MASK (0x40U) #define GTM_gtm_cls1_MCS1_ERR_ERR6_SHIFT (6U) #define GTM_gtm_cls1_MCS1_ERR_ERR6_WIDTH (1U) #define GTM_gtm_cls1_MCS1_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_ERR_ERR6_SHIFT)) & GTM_gtm_cls1_MCS1_ERR_ERR6_MASK) #define GTM_gtm_cls1_MCS1_ERR_ERR7_MASK (0x80U) #define GTM_gtm_cls1_MCS1_ERR_ERR7_SHIFT (7U) #define GTM_gtm_cls1_MCS1_ERR_ERR7_WIDTH (1U) #define GTM_gtm_cls1_MCS1_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_ERR_ERR7_SHIFT)) & GTM_gtm_cls1_MCS1_ERR_ERR7_MASK) /*! @} */ /*! @name MCS1_REG_PROT - MCS[i] write protection register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT0_MASK (0x3U) #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT0_SHIFT (0U) #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT0_WIDTH (2U) #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_REG_PROT_WPROT0_SHIFT)) & GTM_gtm_cls1_MCS1_REG_PROT_WPROT0_MASK) #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT1_MASK (0xCU) #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT1_SHIFT (2U) #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT1_WIDTH (2U) #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_REG_PROT_WPROT1_SHIFT)) & GTM_gtm_cls1_MCS1_REG_PROT_WPROT1_MASK) #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT2_MASK (0x30U) #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT2_SHIFT (4U) #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT2_WIDTH (2U) #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_REG_PROT_WPROT2_SHIFT)) & GTM_gtm_cls1_MCS1_REG_PROT_WPROT2_MASK) #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT3_MASK (0xC0U) #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT3_SHIFT (6U) #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT3_WIDTH (2U) #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_REG_PROT_WPROT3_SHIFT)) & GTM_gtm_cls1_MCS1_REG_PROT_WPROT3_MASK) #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT4_MASK (0x300U) #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT4_SHIFT (8U) #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT4_WIDTH (2U) #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_REG_PROT_WPROT4_SHIFT)) & GTM_gtm_cls1_MCS1_REG_PROT_WPROT4_MASK) #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT5_MASK (0xC00U) #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT5_SHIFT (10U) #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT5_WIDTH (2U) #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_REG_PROT_WPROT5_SHIFT)) & GTM_gtm_cls1_MCS1_REG_PROT_WPROT5_MASK) #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT6_MASK (0x3000U) #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT6_SHIFT (12U) #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT6_WIDTH (2U) #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_REG_PROT_WPROT6_SHIFT)) & GTM_gtm_cls1_MCS1_REG_PROT_WPROT6_MASK) #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT7_MASK (0xC000U) #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT7_SHIFT (14U) #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT7_WIDTH (2U) #define GTM_gtm_cls1_MCS1_REG_PROT_WPROT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_REG_PROT_WPROT7_SHIFT)) & GTM_gtm_cls1_MCS1_REG_PROT_WPROT7_MASK) /*! @} */ /*! @name MCS1_SINT_IRQ_NOTIFY - MCS[i] shared interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ0_MASK (0x1U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ0_SHIFT (0U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ0_WIDTH (1U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ0_SHIFT)) & GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ0_MASK) #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ1_MASK (0x2U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ1_SHIFT (1U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ1_WIDTH (1U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ1_SHIFT)) & GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ1_MASK) #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ2_MASK (0x4U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ2_SHIFT (2U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ2_WIDTH (1U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ2_SHIFT)) & GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ2_MASK) #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ3_MASK (0x8U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ3_SHIFT (3U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ3_WIDTH (1U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ3_SHIFT)) & GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ3_MASK) #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ4_MASK (0x10U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ4_SHIFT (4U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ4_WIDTH (1U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ4_SHIFT)) & GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ4_MASK) #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ5_MASK (0x20U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ5_SHIFT (5U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ5_WIDTH (1U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ5_SHIFT)) & GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ5_MASK) #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ6_MASK (0x40U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ6_SHIFT (6U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ6_WIDTH (1U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ6_SHIFT)) & GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ6_MASK) #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ7_MASK (0x80U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ7_SHIFT (7U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ7_WIDTH (1U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ7_SHIFT)) & GTM_gtm_cls1_MCS1_SINT_IRQ_NOTIFY_S_IRQ7_MASK) /*! @} */ /*! @name MCS1_SINT_IRQ_EN - MCS[i] shared interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ0_EN_MASK (0x1U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ0_EN_SHIFT (0U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ0_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ0_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ0_EN_SHIFT)) & GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ0_EN_MASK) #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ1_EN_MASK (0x2U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ1_EN_SHIFT (1U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ1_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ1_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ1_EN_SHIFT)) & GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ1_EN_MASK) #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ2_EN_MASK (0x4U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ2_EN_SHIFT (2U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ2_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ2_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ2_EN_SHIFT)) & GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ2_EN_MASK) #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ3_EN_MASK (0x8U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ3_EN_SHIFT (3U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ3_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ3_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ3_EN_SHIFT)) & GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ3_EN_MASK) #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ4_EN_MASK (0x10U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ4_EN_SHIFT (4U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ4_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ4_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ4_EN_SHIFT)) & GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ4_EN_MASK) #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ5_EN_MASK (0x20U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ5_EN_SHIFT (5U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ5_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ5_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ5_EN_SHIFT)) & GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ5_EN_MASK) #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ6_EN_MASK (0x40U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ6_EN_SHIFT (6U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ6_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ6_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ6_EN_SHIFT)) & GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ6_EN_MASK) #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ7_EN_MASK (0x80U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ7_EN_SHIFT (7U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ7_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ7_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ7_EN_SHIFT)) & GTM_gtm_cls1_MCS1_SINT_IRQ_EN_S_IRQ7_EN_MASK) /*! @} */ /*! @name MCS1_SINT_IRQ_FORCINT - MCS[i] force shared interrupt register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ0_MASK (0x1U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ0_SHIFT (0U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ0_WIDTH (1U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ0_SHIFT)) & GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ0_MASK) #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ1_MASK (0x2U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ1_SHIFT (1U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ1_WIDTH (1U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ1_SHIFT)) & GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ1_MASK) #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ2_MASK (0x4U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ2_SHIFT (2U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ2_WIDTH (1U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ2_SHIFT)) & GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ2_MASK) #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ3_MASK (0x8U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ3_SHIFT (3U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ3_WIDTH (1U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ3_SHIFT)) & GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ3_MASK) #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ4_MASK (0x10U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ4_SHIFT (4U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ4_WIDTH (1U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ4_SHIFT)) & GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ4_MASK) #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ5_MASK (0x20U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ5_SHIFT (5U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ5_WIDTH (1U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ5_SHIFT)) & GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ5_MASK) #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ6_MASK (0x40U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ6_SHIFT (6U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ6_WIDTH (1U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ6_SHIFT)) & GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ6_MASK) #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ7_MASK (0x80U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ7_SHIFT (7U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ7_WIDTH (1U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ7_SHIFT)) & GTM_gtm_cls1_MCS1_SINT_IRQ_FORCINT_TRG_S_IRQ7_MASK) /*! @} */ /*! @name MCS1_SINT_IRQ_MODE - MCS[i] shared interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_SINT_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_MCS1_SINT_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_SINT_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_MCS1_SINT_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name MCS1_HBP0_CTRL - MCS[i] hardware break point h control register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH0_MASK (0x1U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH0_SHIFT (0U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH0_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH0_SHIFT)) & GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH0_MASK) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH1_MASK (0x2U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH1_SHIFT (1U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH1_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH1_SHIFT)) & GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH1_MASK) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH2_MASK (0x4U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH2_SHIFT (2U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH2_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH2_SHIFT)) & GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH2_MASK) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH3_MASK (0x8U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH3_SHIFT (3U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH3_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH3_SHIFT)) & GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH3_MASK) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH4_MASK (0x10U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH4_SHIFT (4U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH4_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH4_SHIFT)) & GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH4_MASK) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH5_MASK (0x20U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH5_SHIFT (5U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH5_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH5_SHIFT)) & GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH5_MASK) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH6_MASK (0x40U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH6_SHIFT (6U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH6_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH6_SHIFT)) & GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH6_MASK) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH7_MASK (0x80U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH7_SHIFT (7U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH7_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH7_SHIFT)) & GTM_gtm_cls1_MCS1_HBP0_CTRL_EN_CH7_MASK) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_SCOPE_MASK (0x300U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_SCOPE_SHIFT (8U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_SCOPE_WIDTH (2U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_SCOPE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP0_CTRL_SCOPE_SHIFT)) & GTM_gtm_cls1_MCS1_HBP0_CTRL_SCOPE_MASK) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_TYPE_MASK (0x7000U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_TYPE_SHIFT (12U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_TYPE_WIDTH (3U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP0_CTRL_TYPE_SHIFT)) & GTM_gtm_cls1_MCS1_HBP0_CTRL_TYPE_MASK) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_AND_MASK (0x10000U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_AND_SHIFT (16U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_AND_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_AND(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP0_CTRL_AND_SHIFT)) & GTM_gtm_cls1_MCS1_HBP0_CTRL_AND_MASK) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_NOT_MASK (0x20000U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_NOT_SHIFT (17U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_NOT_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP0_CTRL_NOT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP0_CTRL_NOT_SHIFT)) & GTM_gtm_cls1_MCS1_HBP0_CTRL_NOT_MASK) /*! @} */ /*! @name MCS1_HBP0_PATTERN - MCS[i] hardware break point pattern register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_HBP0_PATTERN_DATA_MASK (0xFFFFFFFFU) #define GTM_gtm_cls1_MCS1_HBP0_PATTERN_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_HBP0_PATTERN_DATA_WIDTH (32U) #define GTM_gtm_cls1_MCS1_HBP0_PATTERN_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP0_PATTERN_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_HBP0_PATTERN_DATA_MASK) /*! @} */ /*! @name MCS1_HBP0_STATUS - MCS[i] hardware break point status register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH0_MASK (0x1U) #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH0_SHIFT (0U) #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH0_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH0_SHIFT)) & GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH0_MASK) #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH1_MASK (0x2U) #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH1_SHIFT (1U) #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH1_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH1_SHIFT)) & GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH1_MASK) #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH2_MASK (0x4U) #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH2_SHIFT (2U) #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH2_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH2_SHIFT)) & GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH2_MASK) #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH3_MASK (0x8U) #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH3_SHIFT (3U) #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH3_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH3_SHIFT)) & GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH3_MASK) #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH4_MASK (0x10U) #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH4_SHIFT (4U) #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH4_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH4_SHIFT)) & GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH4_MASK) #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH5_MASK (0x20U) #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH5_SHIFT (5U) #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH5_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH5_SHIFT)) & GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH5_MASK) #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH6_MASK (0x40U) #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH6_SHIFT (6U) #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH6_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH6_SHIFT)) & GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH6_MASK) #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH7_MASK (0x80U) #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH7_SHIFT (7U) #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH7_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH7_SHIFT)) & GTM_gtm_cls1_MCS1_HBP0_STATUS_HALT_CH7_MASK) /*! @} */ /*! @name MCS1_HBP0_IRQ_NOTIFY - MCS[i] hardware break point interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_HBP0_IRQ_NOTIFY_HBP_IRQ_MASK (0x1U) #define GTM_gtm_cls1_MCS1_HBP0_IRQ_NOTIFY_HBP_IRQ_SHIFT (0U) #define GTM_gtm_cls1_MCS1_HBP0_IRQ_NOTIFY_HBP_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP0_IRQ_NOTIFY_HBP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP0_IRQ_NOTIFY_HBP_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_HBP0_IRQ_NOTIFY_HBP_IRQ_MASK) /*! @} */ /*! @name MCS1_HBP0_IRQ_EN - MCS[i] hardware break point interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_HBP0_IRQ_EN_HBP_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_MCS1_HBP0_IRQ_EN_HBP_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_MCS1_HBP0_IRQ_EN_HBP_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP0_IRQ_EN_HBP_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP0_IRQ_EN_HBP_IRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_HBP0_IRQ_EN_HBP_IRQ_EN_MASK) /*! @} */ /*! @name MCS1_HBP0_IRQ_FORCINT - MCS[i] force hardware break point interrupt register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_HBP0_IRQ_FORCINT_TRG_HBP_IRQ_MASK (0x1U) #define GTM_gtm_cls1_MCS1_HBP0_IRQ_FORCINT_TRG_HBP_IRQ_SHIFT (0U) #define GTM_gtm_cls1_MCS1_HBP0_IRQ_FORCINT_TRG_HBP_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP0_IRQ_FORCINT_TRG_HBP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP0_IRQ_FORCINT_TRG_HBP_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_HBP0_IRQ_FORCINT_TRG_HBP_IRQ_MASK) /*! @} */ /*! @name MCS1_HBP0_IRQ_MODE - MCS[i] break point h interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_HBP0_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_MCS1_HBP0_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_MCS1_HBP0_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_MCS1_HBP0_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP0_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_MCS1_HBP0_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name MCS1_HBP1_CTRL - MCS[i] hardware break point h control register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH0_MASK (0x1U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH0_SHIFT (0U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH0_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH0_SHIFT)) & GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH0_MASK) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH1_MASK (0x2U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH1_SHIFT (1U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH1_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH1_SHIFT)) & GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH1_MASK) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH2_MASK (0x4U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH2_SHIFT (2U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH2_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH2_SHIFT)) & GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH2_MASK) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH3_MASK (0x8U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH3_SHIFT (3U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH3_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH3_SHIFT)) & GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH3_MASK) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH4_MASK (0x10U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH4_SHIFT (4U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH4_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH4_SHIFT)) & GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH4_MASK) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH5_MASK (0x20U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH5_SHIFT (5U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH5_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH5_SHIFT)) & GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH5_MASK) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH6_MASK (0x40U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH6_SHIFT (6U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH6_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH6_SHIFT)) & GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH6_MASK) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH7_MASK (0x80U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH7_SHIFT (7U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH7_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH7_SHIFT)) & GTM_gtm_cls1_MCS1_HBP1_CTRL_EN_CH7_MASK) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_SCOPE_MASK (0x300U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_SCOPE_SHIFT (8U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_SCOPE_WIDTH (2U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_SCOPE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP1_CTRL_SCOPE_SHIFT)) & GTM_gtm_cls1_MCS1_HBP1_CTRL_SCOPE_MASK) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_TYPE_MASK (0x7000U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_TYPE_SHIFT (12U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_TYPE_WIDTH (3U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP1_CTRL_TYPE_SHIFT)) & GTM_gtm_cls1_MCS1_HBP1_CTRL_TYPE_MASK) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_AND_MASK (0x10000U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_AND_SHIFT (16U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_AND_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_AND(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP1_CTRL_AND_SHIFT)) & GTM_gtm_cls1_MCS1_HBP1_CTRL_AND_MASK) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_NOT_MASK (0x20000U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_NOT_SHIFT (17U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_NOT_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP1_CTRL_NOT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP1_CTRL_NOT_SHIFT)) & GTM_gtm_cls1_MCS1_HBP1_CTRL_NOT_MASK) /*! @} */ /*! @name MCS1_HBP1_PATTERN - MCS[i] hardware break point pattern register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_HBP1_PATTERN_DATA_MASK (0xFFFFFFFFU) #define GTM_gtm_cls1_MCS1_HBP1_PATTERN_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_HBP1_PATTERN_DATA_WIDTH (32U) #define GTM_gtm_cls1_MCS1_HBP1_PATTERN_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP1_PATTERN_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_HBP1_PATTERN_DATA_MASK) /*! @} */ /*! @name MCS1_HBP1_STATUS - MCS[i] hardware break point status register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH0_MASK (0x1U) #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH0_SHIFT (0U) #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH0_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH0_SHIFT)) & GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH0_MASK) #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH1_MASK (0x2U) #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH1_SHIFT (1U) #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH1_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH1_SHIFT)) & GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH1_MASK) #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH2_MASK (0x4U) #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH2_SHIFT (2U) #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH2_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH2_SHIFT)) & GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH2_MASK) #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH3_MASK (0x8U) #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH3_SHIFT (3U) #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH3_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH3_SHIFT)) & GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH3_MASK) #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH4_MASK (0x10U) #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH4_SHIFT (4U) #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH4_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH4_SHIFT)) & GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH4_MASK) #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH5_MASK (0x20U) #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH5_SHIFT (5U) #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH5_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH5_SHIFT)) & GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH5_MASK) #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH6_MASK (0x40U) #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH6_SHIFT (6U) #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH6_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH6_SHIFT)) & GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH6_MASK) #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH7_MASK (0x80U) #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH7_SHIFT (7U) #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH7_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH7_SHIFT)) & GTM_gtm_cls1_MCS1_HBP1_STATUS_HALT_CH7_MASK) /*! @} */ /*! @name MCS1_HBP1_IRQ_NOTIFY - MCS[i] hardware break point interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_HBP1_IRQ_NOTIFY_HBP_IRQ_MASK (0x1U) #define GTM_gtm_cls1_MCS1_HBP1_IRQ_NOTIFY_HBP_IRQ_SHIFT (0U) #define GTM_gtm_cls1_MCS1_HBP1_IRQ_NOTIFY_HBP_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP1_IRQ_NOTIFY_HBP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP1_IRQ_NOTIFY_HBP_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_HBP1_IRQ_NOTIFY_HBP_IRQ_MASK) /*! @} */ /*! @name MCS1_HBP1_IRQ_EN - MCS[i] hardware break point interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_HBP1_IRQ_EN_HBP_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_MCS1_HBP1_IRQ_EN_HBP_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_MCS1_HBP1_IRQ_EN_HBP_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP1_IRQ_EN_HBP_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP1_IRQ_EN_HBP_IRQ_EN_SHIFT)) & GTM_gtm_cls1_MCS1_HBP1_IRQ_EN_HBP_IRQ_EN_MASK) /*! @} */ /*! @name MCS1_HBP1_IRQ_FORCINT - MCS[i] force hardware break point interrupt register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_HBP1_IRQ_FORCINT_TRG_HBP_IRQ_MASK (0x1U) #define GTM_gtm_cls1_MCS1_HBP1_IRQ_FORCINT_TRG_HBP_IRQ_SHIFT (0U) #define GTM_gtm_cls1_MCS1_HBP1_IRQ_FORCINT_TRG_HBP_IRQ_WIDTH (1U) #define GTM_gtm_cls1_MCS1_HBP1_IRQ_FORCINT_TRG_HBP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP1_IRQ_FORCINT_TRG_HBP_IRQ_SHIFT)) & GTM_gtm_cls1_MCS1_HBP1_IRQ_FORCINT_TRG_HBP_IRQ_MASK) /*! @} */ /*! @name MCS1_HBP1_IRQ_MODE - MCS[i] break point h interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_MCS1_HBP1_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_MCS1_HBP1_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_MCS1_HBP1_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_MCS1_HBP1_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_HBP1_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_MCS1_HBP1_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TIO1_G0_CH0_CTRL - TIO[i] group [g] channel [c] control register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_S_RE_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_S_RE_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_S_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_S_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_S_FE_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_S_FE_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_S_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_S_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_O_RE_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_O_RE_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_O_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_O_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_O_FE_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_O_FE_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_O_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_O_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_PL_EVT_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_PL_EVT_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_PL_EVT_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (6U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK (0x80U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT (7U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_CYCLIC_INIT_TRIG_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_CYCLIC_INIT_TRIG_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_UPDATE_SRC_MASK (0xF00U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_UPDATE_SRC_SHIFT (8U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_UPDATE_SRC_WIDTH (4U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_UPDATE_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_CTRL_UPDATE_SRC_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_CTRL_UPDATE_SRC_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_S_MODE_MASK (0x3000U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_S_MODE_SHIFT (12U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_S_MODE_WIDTH (2U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_S_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_S_MODE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_S_MODE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_FREEZE_S_EN_MASK (0x4000U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_FREEZE_S_EN_SHIFT (14U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_FREEZE_S_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_FREEZE_S_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_FREEZE_S_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_FREEZE_S_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_CYCLIC_BUFF_MASK (0x8000U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_CYCLIC_BUFF_SHIFT (15U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_CYCLIC_BUFF_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_CYCLIC_BUFF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_CYCLIC_BUFF_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_CYCLIC_BUFF_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_O_MODE_MASK (0x70000U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_O_MODE_SHIFT (16U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_O_MODE_WIDTH (3U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_O_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_O_MODE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_O_MODE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_FREEZE_O_EN_MASK (0x80000U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_FREEZE_O_EN_SHIFT (19U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_FREEZE_O_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_FREEZE_O_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_FREEZE_O_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_FREEZE_O_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_ODIS_MASK (0x100000U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_ODIS_SHIFT (20U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_ODIS_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_ODIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_ODIS_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_ODIS_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_SEL_IN_MASK (0x200000U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_SEL_IN_SHIFT (21U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_SEL_IN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_SEL_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_SEL_IN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_SEL_IN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_O_TRIG_OUT_EN_MASK (0x400000U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_O_TRIG_OUT_EN_SHIFT (22U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_O_TRIG_OUT_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_O_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_O_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_O_TRIG_OUT_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_S_TRIG_OUT_EN_MASK (0x800000U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_S_TRIG_OUT_EN_SHIFT (23U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_S_TRIG_OUT_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_S_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_S_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_S_TRIG_OUT_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_S_RE_MASK (0x1000000U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_S_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_S_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_S_FE_MASK (0x2000000U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT (25U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_S_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_S_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_O_RE_MASK (0x4000000U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT (26U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_O_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_O_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_O_FE_MASK (0x8000000U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT (27U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_O_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_O_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10000000U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT (28U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK (0x20000000U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT (29U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_PL_EVT_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_UPD_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_UPD_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_CTRL_PL_TRIG_OUT_UPD_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH0_IRQ_NOTIFY - TIO[i] channel [c] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_S_RE_IRQ_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_S_RE_IRQ_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_S_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_S_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_S_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_S_FE_IRQ_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_S_FE_IRQ_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_S_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_S_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_S_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_O_RE_IRQ_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_O_RE_IRQ_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_O_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_O_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_O_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_O_FE_IRQ_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_O_FE_IRQ_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_O_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_O_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_O_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_UPDATE_IRQ_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_UPDATE_IRQ_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_UPDATE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_UPDATE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_PL_EVT_IRQ_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_PL_EVT_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_IRQ_NOTIFY_PL_EVT_IRQ_MASK) /*! @} */ /*! @name TIO1_G0_CH0_IRQ_EN - TIO[i] channel [c] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_S_RE_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_S_RE_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_S_RE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_S_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_S_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_S_RE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_S_FE_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_S_FE_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_S_FE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_S_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_S_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_S_FE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_O_RE_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_O_RE_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_O_RE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_O_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_O_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_O_RE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_O_FE_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_O_FE_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_O_FE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_O_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_O_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_O_FE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_UPDATE_IRQ_EN_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_UPDATE_IRQ_EN_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_UPDATE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_UPDATE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_UPDATE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_UPDATE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_PL_EVT_IRQ_EN_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_PL_EVT_IRQ_EN_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_PL_EVT_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_PL_EVT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_PL_EVT_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_IRQ_EN_PL_EVT_IRQ_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH0_IRQ_FORCINT - TIO[i] channel [c] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_S_RE_IRQ_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_S_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_S_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_S_FE_IRQ_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_S_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_S_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_O_RE_IRQ_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_O_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_O_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_O_FE_IRQ_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_O_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_O_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_UPDATE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_PL_EVT_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK) /*! @} */ /*! @name TIO1_G0_CH0_IRQ_MODE - TIO[i] channel [c] IRQ mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TIO1_G0_CH0_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TIO1_G0_CH0_CTRL2 - TIO[i] group [g] channel [c] control register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL2_DUAL_CMP_EN_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL2_DUAL_CMP_EN_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL2_DUAL_CMP_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL2_DUAL_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_CTRL2_DUAL_CMP_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_CTRL2_DUAL_CMP_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL2_DUAL_CMP_MST_EN_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL2_DUAL_CMP_MST_EN_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL2_DUAL_CMP_MST_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_CTRL2_DUAL_CMP_MST_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_CTRL2_DUAL_CMP_MST_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_CTRL2_DUAL_CMP_MST_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH0_SINST - TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH0_SINST_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH0_SINST_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH0_SINST_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH0_SINST_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_SINST_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_SINST_OP_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_SINST_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH0_SINST_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH0_SINST_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH0_SINST_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_SINST_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_SINST_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_SINST_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH0_SINST_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH0_SINST_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_SINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_SINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_SINST_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_SINST_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH0_SINST_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH0_SINST_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_SINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_SINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_SINST_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH0_SCMD - TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH0_SCMD_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH0_SCMD_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH0_SCMD_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH0_SCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_SCMD_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_SCMD_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_SCMD_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH0_SCMD_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH0_SCMD_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_SCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_SCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_SCMD_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_SCMD_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH0_SCMD_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH0_SCMD_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_SCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_SCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_SCMD_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH0_SOP - TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ) */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH0_SOP_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH0_SOP_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH0_SOP_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH0_SOP_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_SOP_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_SOP_OP_MASK) /*! @} */ /*! @name TIO1_G0_CH0_OINST - TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH0_OINST_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH0_OINST_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH0_OINST_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH0_OINST_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_OINST_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_OINST_OP_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_OINST_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH0_OINST_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH0_OINST_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH0_OINST_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_OINST_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_OINST_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_OINST_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH0_OINST_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH0_OINST_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_OINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_OINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_OINST_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_OINST_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH0_OINST_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH0_OINST_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_OINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_OINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_OINST_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH0_OCMD - TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH0_OCMD_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH0_OCMD_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH0_OCMD_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH0_OCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_OCMD_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_OCMD_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_OCMD_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH0_OCMD_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH0_OCMD_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_OCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_OCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_OCMD_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH0_OCMD_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH0_OCMD_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH0_OCMD_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH0_OCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_OCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_OCMD_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH0_OOP - TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-) */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH0_OOP_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH0_OOP_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH0_OOP_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH0_OOP_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_OOP_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_OOP_OP_MASK) /*! @} */ /*! @name TIO1_G0_CH0_SHIFTCNT - TIO[i] channel [c] resource shift count register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH0_SHIFTCNT_CNT_MASK (0x1FU) #define GTM_gtm_cls1_TIO1_G0_CH0_SHIFTCNT_CNT_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH0_SHIFTCNT_CNT_WIDTH (5U) #define GTM_gtm_cls1_TIO1_G0_CH0_SHIFTCNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH0_SHIFTCNT_CNT_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH0_SHIFTCNT_CNT_MASK) /*! @} */ /*! @name TIO1_G0_CH1_CTRL - TIO[i] group [g] channel [c] control register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_S_RE_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_S_RE_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_S_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_S_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_S_FE_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_S_FE_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_S_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_S_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_O_RE_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_O_RE_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_O_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_O_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_O_FE_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_O_FE_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_O_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_O_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_PL_EVT_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_PL_EVT_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_PL_EVT_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (6U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK (0x80U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT (7U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_CYCLIC_INIT_TRIG_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_CYCLIC_INIT_TRIG_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_UPDATE_SRC_MASK (0xF00U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_UPDATE_SRC_SHIFT (8U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_UPDATE_SRC_WIDTH (4U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_UPDATE_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_CTRL_UPDATE_SRC_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_CTRL_UPDATE_SRC_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_S_MODE_MASK (0x3000U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_S_MODE_SHIFT (12U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_S_MODE_WIDTH (2U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_S_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_S_MODE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_S_MODE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_FREEZE_S_EN_MASK (0x4000U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_FREEZE_S_EN_SHIFT (14U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_FREEZE_S_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_FREEZE_S_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_FREEZE_S_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_FREEZE_S_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_CYCLIC_BUFF_MASK (0x8000U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_CYCLIC_BUFF_SHIFT (15U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_CYCLIC_BUFF_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_CYCLIC_BUFF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_CYCLIC_BUFF_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_CYCLIC_BUFF_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_O_MODE_MASK (0x70000U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_O_MODE_SHIFT (16U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_O_MODE_WIDTH (3U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_O_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_O_MODE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_O_MODE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_FREEZE_O_EN_MASK (0x80000U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_FREEZE_O_EN_SHIFT (19U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_FREEZE_O_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_FREEZE_O_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_FREEZE_O_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_FREEZE_O_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_ODIS_MASK (0x100000U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_ODIS_SHIFT (20U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_ODIS_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_ODIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_ODIS_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_ODIS_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_SEL_IN_MASK (0x200000U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_SEL_IN_SHIFT (21U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_SEL_IN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_SEL_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_SEL_IN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_SEL_IN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_O_TRIG_OUT_EN_MASK (0x400000U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_O_TRIG_OUT_EN_SHIFT (22U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_O_TRIG_OUT_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_O_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_O_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_O_TRIG_OUT_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_S_TRIG_OUT_EN_MASK (0x800000U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_S_TRIG_OUT_EN_SHIFT (23U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_S_TRIG_OUT_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_S_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_S_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_S_TRIG_OUT_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_S_RE_MASK (0x1000000U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_S_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_S_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_S_FE_MASK (0x2000000U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT (25U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_S_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_S_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_O_RE_MASK (0x4000000U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT (26U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_O_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_O_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_O_FE_MASK (0x8000000U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT (27U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_O_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_O_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10000000U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT (28U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK (0x20000000U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT (29U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_PL_EVT_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_UPD_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_UPD_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_CTRL_PL_TRIG_OUT_UPD_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH1_IRQ_NOTIFY - TIO[i] channel [c] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_S_RE_IRQ_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_S_RE_IRQ_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_S_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_S_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_S_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_S_FE_IRQ_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_S_FE_IRQ_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_S_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_S_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_S_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_O_RE_IRQ_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_O_RE_IRQ_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_O_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_O_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_O_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_O_FE_IRQ_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_O_FE_IRQ_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_O_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_O_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_O_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_UPDATE_IRQ_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_UPDATE_IRQ_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_UPDATE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_UPDATE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_PL_EVT_IRQ_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_PL_EVT_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_IRQ_NOTIFY_PL_EVT_IRQ_MASK) /*! @} */ /*! @name TIO1_G0_CH1_IRQ_EN - TIO[i] channel [c] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_S_RE_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_S_RE_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_S_RE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_S_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_S_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_S_RE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_S_FE_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_S_FE_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_S_FE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_S_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_S_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_S_FE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_O_RE_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_O_RE_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_O_RE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_O_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_O_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_O_RE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_O_FE_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_O_FE_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_O_FE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_O_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_O_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_O_FE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_UPDATE_IRQ_EN_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_UPDATE_IRQ_EN_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_UPDATE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_UPDATE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_UPDATE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_UPDATE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_PL_EVT_IRQ_EN_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_PL_EVT_IRQ_EN_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_PL_EVT_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_PL_EVT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_PL_EVT_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_IRQ_EN_PL_EVT_IRQ_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH1_IRQ_FORCINT - TIO[i] channel [c] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_S_RE_IRQ_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_S_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_S_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_S_FE_IRQ_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_S_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_S_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_O_RE_IRQ_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_O_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_O_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_O_FE_IRQ_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_O_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_O_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_UPDATE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_PL_EVT_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK) /*! @} */ /*! @name TIO1_G0_CH1_IRQ_MODE - TIO[i] channel [c] IRQ mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TIO1_G0_CH1_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TIO1_G0_CH1_CTRL2 - TIO[i] group [g] channel [c] control register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL2_DUAL_CMP_EN_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL2_DUAL_CMP_EN_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL2_DUAL_CMP_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL2_DUAL_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_CTRL2_DUAL_CMP_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_CTRL2_DUAL_CMP_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL2_DUAL_CMP_MST_EN_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL2_DUAL_CMP_MST_EN_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL2_DUAL_CMP_MST_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_CTRL2_DUAL_CMP_MST_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_CTRL2_DUAL_CMP_MST_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_CTRL2_DUAL_CMP_MST_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH1_SINST - TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH1_SINST_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH1_SINST_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH1_SINST_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH1_SINST_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_SINST_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_SINST_OP_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_SINST_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH1_SINST_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH1_SINST_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH1_SINST_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_SINST_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_SINST_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_SINST_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH1_SINST_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH1_SINST_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_SINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_SINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_SINST_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_SINST_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH1_SINST_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH1_SINST_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_SINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_SINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_SINST_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH1_SCMD - TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH1_SCMD_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH1_SCMD_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH1_SCMD_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH1_SCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_SCMD_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_SCMD_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_SCMD_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH1_SCMD_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH1_SCMD_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_SCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_SCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_SCMD_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_SCMD_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH1_SCMD_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH1_SCMD_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_SCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_SCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_SCMD_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH1_SOP - TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ) */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH1_SOP_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH1_SOP_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH1_SOP_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH1_SOP_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_SOP_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_SOP_OP_MASK) /*! @} */ /*! @name TIO1_G0_CH1_OINST - TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH1_OINST_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH1_OINST_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH1_OINST_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH1_OINST_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_OINST_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_OINST_OP_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_OINST_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH1_OINST_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH1_OINST_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH1_OINST_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_OINST_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_OINST_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_OINST_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH1_OINST_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH1_OINST_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_OINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_OINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_OINST_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_OINST_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH1_OINST_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH1_OINST_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_OINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_OINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_OINST_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH1_OCMD - TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH1_OCMD_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH1_OCMD_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH1_OCMD_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH1_OCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_OCMD_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_OCMD_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_OCMD_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH1_OCMD_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH1_OCMD_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_OCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_OCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_OCMD_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH1_OCMD_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH1_OCMD_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH1_OCMD_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH1_OCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_OCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_OCMD_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH1_OOP - TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-) */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH1_OOP_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH1_OOP_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH1_OOP_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH1_OOP_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_OOP_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_OOP_OP_MASK) /*! @} */ /*! @name TIO1_G0_CH1_SHIFTCNT - TIO[i] channel [c] resource shift count register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH1_SHIFTCNT_CNT_MASK (0x1FU) #define GTM_gtm_cls1_TIO1_G0_CH1_SHIFTCNT_CNT_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH1_SHIFTCNT_CNT_WIDTH (5U) #define GTM_gtm_cls1_TIO1_G0_CH1_SHIFTCNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH1_SHIFTCNT_CNT_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH1_SHIFTCNT_CNT_MASK) /*! @} */ /*! @name TIO1_G0_CH2_CTRL - TIO[i] group [g] channel [c] control register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_S_RE_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_S_RE_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_S_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_S_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_S_FE_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_S_FE_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_S_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_S_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_O_RE_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_O_RE_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_O_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_O_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_O_FE_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_O_FE_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_O_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_O_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_PL_EVT_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_PL_EVT_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_PL_EVT_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (6U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK (0x80U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT (7U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_CYCLIC_INIT_TRIG_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_CYCLIC_INIT_TRIG_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_UPDATE_SRC_MASK (0xF00U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_UPDATE_SRC_SHIFT (8U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_UPDATE_SRC_WIDTH (4U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_UPDATE_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_CTRL_UPDATE_SRC_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_CTRL_UPDATE_SRC_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_S_MODE_MASK (0x3000U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_S_MODE_SHIFT (12U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_S_MODE_WIDTH (2U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_S_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_S_MODE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_S_MODE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_FREEZE_S_EN_MASK (0x4000U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_FREEZE_S_EN_SHIFT (14U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_FREEZE_S_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_FREEZE_S_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_FREEZE_S_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_FREEZE_S_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_CYCLIC_BUFF_MASK (0x8000U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_CYCLIC_BUFF_SHIFT (15U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_CYCLIC_BUFF_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_CYCLIC_BUFF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_CYCLIC_BUFF_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_CYCLIC_BUFF_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_O_MODE_MASK (0x70000U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_O_MODE_SHIFT (16U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_O_MODE_WIDTH (3U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_O_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_O_MODE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_O_MODE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_FREEZE_O_EN_MASK (0x80000U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_FREEZE_O_EN_SHIFT (19U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_FREEZE_O_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_FREEZE_O_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_FREEZE_O_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_FREEZE_O_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_ODIS_MASK (0x100000U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_ODIS_SHIFT (20U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_ODIS_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_ODIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_ODIS_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_ODIS_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_SEL_IN_MASK (0x200000U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_SEL_IN_SHIFT (21U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_SEL_IN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_SEL_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_SEL_IN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_SEL_IN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_O_TRIG_OUT_EN_MASK (0x400000U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_O_TRIG_OUT_EN_SHIFT (22U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_O_TRIG_OUT_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_O_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_O_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_O_TRIG_OUT_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_S_TRIG_OUT_EN_MASK (0x800000U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_S_TRIG_OUT_EN_SHIFT (23U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_S_TRIG_OUT_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_S_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_S_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_S_TRIG_OUT_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_S_RE_MASK (0x1000000U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_S_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_S_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_S_FE_MASK (0x2000000U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT (25U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_S_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_S_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_O_RE_MASK (0x4000000U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT (26U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_O_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_O_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_O_FE_MASK (0x8000000U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT (27U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_O_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_O_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10000000U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT (28U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK (0x20000000U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT (29U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_PL_EVT_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_UPD_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_UPD_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_CTRL_PL_TRIG_OUT_UPD_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH2_IRQ_NOTIFY - TIO[i] channel [c] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_S_RE_IRQ_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_S_RE_IRQ_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_S_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_S_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_S_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_S_FE_IRQ_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_S_FE_IRQ_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_S_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_S_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_S_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_O_RE_IRQ_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_O_RE_IRQ_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_O_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_O_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_O_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_O_FE_IRQ_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_O_FE_IRQ_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_O_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_O_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_O_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_UPDATE_IRQ_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_UPDATE_IRQ_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_UPDATE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_UPDATE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_PL_EVT_IRQ_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_PL_EVT_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_IRQ_NOTIFY_PL_EVT_IRQ_MASK) /*! @} */ /*! @name TIO1_G0_CH2_IRQ_EN - TIO[i] channel [c] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_S_RE_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_S_RE_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_S_RE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_S_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_S_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_S_RE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_S_FE_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_S_FE_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_S_FE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_S_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_S_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_S_FE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_O_RE_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_O_RE_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_O_RE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_O_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_O_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_O_RE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_O_FE_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_O_FE_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_O_FE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_O_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_O_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_O_FE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_UPDATE_IRQ_EN_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_UPDATE_IRQ_EN_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_UPDATE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_UPDATE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_UPDATE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_UPDATE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_PL_EVT_IRQ_EN_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_PL_EVT_IRQ_EN_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_PL_EVT_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_PL_EVT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_PL_EVT_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_IRQ_EN_PL_EVT_IRQ_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH2_IRQ_FORCINT - TIO[i] channel [c] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_S_RE_IRQ_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_S_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_S_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_S_FE_IRQ_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_S_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_S_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_O_RE_IRQ_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_O_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_O_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_O_FE_IRQ_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_O_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_O_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_UPDATE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_PL_EVT_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK) /*! @} */ /*! @name TIO1_G0_CH2_IRQ_MODE - TIO[i] channel [c] IRQ mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TIO1_G0_CH2_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TIO1_G0_CH2_CTRL2 - TIO[i] group [g] channel [c] control register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL2_DUAL_CMP_EN_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL2_DUAL_CMP_EN_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL2_DUAL_CMP_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL2_DUAL_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_CTRL2_DUAL_CMP_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_CTRL2_DUAL_CMP_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL2_DUAL_CMP_MST_EN_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL2_DUAL_CMP_MST_EN_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL2_DUAL_CMP_MST_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_CTRL2_DUAL_CMP_MST_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_CTRL2_DUAL_CMP_MST_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_CTRL2_DUAL_CMP_MST_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH2_SINST - TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH2_SINST_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH2_SINST_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH2_SINST_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH2_SINST_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_SINST_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_SINST_OP_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_SINST_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH2_SINST_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH2_SINST_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH2_SINST_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_SINST_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_SINST_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_SINST_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH2_SINST_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH2_SINST_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_SINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_SINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_SINST_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_SINST_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH2_SINST_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH2_SINST_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_SINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_SINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_SINST_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH2_SCMD - TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH2_SCMD_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH2_SCMD_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH2_SCMD_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH2_SCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_SCMD_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_SCMD_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_SCMD_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH2_SCMD_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH2_SCMD_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_SCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_SCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_SCMD_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_SCMD_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH2_SCMD_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH2_SCMD_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_SCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_SCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_SCMD_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH2_SOP - TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ) */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH2_SOP_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH2_SOP_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH2_SOP_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH2_SOP_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_SOP_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_SOP_OP_MASK) /*! @} */ /*! @name TIO1_G0_CH2_OINST - TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH2_OINST_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH2_OINST_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH2_OINST_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH2_OINST_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_OINST_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_OINST_OP_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_OINST_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH2_OINST_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH2_OINST_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH2_OINST_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_OINST_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_OINST_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_OINST_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH2_OINST_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH2_OINST_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_OINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_OINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_OINST_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_OINST_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH2_OINST_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH2_OINST_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_OINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_OINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_OINST_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH2_OCMD - TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH2_OCMD_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH2_OCMD_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH2_OCMD_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH2_OCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_OCMD_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_OCMD_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_OCMD_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH2_OCMD_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH2_OCMD_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_OCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_OCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_OCMD_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH2_OCMD_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH2_OCMD_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH2_OCMD_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH2_OCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_OCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_OCMD_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH2_OOP - TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-) */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH2_OOP_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH2_OOP_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH2_OOP_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH2_OOP_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_OOP_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_OOP_OP_MASK) /*! @} */ /*! @name TIO1_G0_CH2_SHIFTCNT - TIO[i] channel [c] resource shift count register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH2_SHIFTCNT_CNT_MASK (0x1FU) #define GTM_gtm_cls1_TIO1_G0_CH2_SHIFTCNT_CNT_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH2_SHIFTCNT_CNT_WIDTH (5U) #define GTM_gtm_cls1_TIO1_G0_CH2_SHIFTCNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH2_SHIFTCNT_CNT_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH2_SHIFTCNT_CNT_MASK) /*! @} */ /*! @name TIO1_G0_CH3_CTRL - TIO[i] group [g] channel [c] control register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_S_RE_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_S_RE_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_S_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_S_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_S_FE_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_S_FE_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_S_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_S_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_O_RE_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_O_RE_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_O_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_O_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_O_FE_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_O_FE_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_O_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_O_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_PL_EVT_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_PL_EVT_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_PL_EVT_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (6U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK (0x80U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT (7U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_CYCLIC_INIT_TRIG_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_CYCLIC_INIT_TRIG_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_UPDATE_SRC_MASK (0xF00U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_UPDATE_SRC_SHIFT (8U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_UPDATE_SRC_WIDTH (4U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_UPDATE_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_CTRL_UPDATE_SRC_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_CTRL_UPDATE_SRC_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_S_MODE_MASK (0x3000U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_S_MODE_SHIFT (12U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_S_MODE_WIDTH (2U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_S_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_S_MODE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_S_MODE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_FREEZE_S_EN_MASK (0x4000U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_FREEZE_S_EN_SHIFT (14U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_FREEZE_S_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_FREEZE_S_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_FREEZE_S_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_FREEZE_S_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_CYCLIC_BUFF_MASK (0x8000U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_CYCLIC_BUFF_SHIFT (15U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_CYCLIC_BUFF_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_CYCLIC_BUFF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_CYCLIC_BUFF_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_CYCLIC_BUFF_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_O_MODE_MASK (0x70000U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_O_MODE_SHIFT (16U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_O_MODE_WIDTH (3U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_O_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_O_MODE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_O_MODE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_FREEZE_O_EN_MASK (0x80000U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_FREEZE_O_EN_SHIFT (19U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_FREEZE_O_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_FREEZE_O_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_FREEZE_O_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_FREEZE_O_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_ODIS_MASK (0x100000U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_ODIS_SHIFT (20U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_ODIS_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_ODIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_ODIS_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_ODIS_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_SEL_IN_MASK (0x200000U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_SEL_IN_SHIFT (21U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_SEL_IN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_SEL_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_SEL_IN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_SEL_IN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_O_TRIG_OUT_EN_MASK (0x400000U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_O_TRIG_OUT_EN_SHIFT (22U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_O_TRIG_OUT_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_O_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_O_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_O_TRIG_OUT_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_S_TRIG_OUT_EN_MASK (0x800000U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_S_TRIG_OUT_EN_SHIFT (23U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_S_TRIG_OUT_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_S_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_S_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_S_TRIG_OUT_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_S_RE_MASK (0x1000000U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_S_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_S_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_S_FE_MASK (0x2000000U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT (25U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_S_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_S_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_O_RE_MASK (0x4000000U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT (26U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_O_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_O_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_O_FE_MASK (0x8000000U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT (27U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_O_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_O_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10000000U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT (28U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK (0x20000000U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT (29U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_PL_EVT_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_UPD_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_UPD_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_CTRL_PL_TRIG_OUT_UPD_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH3_IRQ_NOTIFY - TIO[i] channel [c] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_S_RE_IRQ_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_S_RE_IRQ_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_S_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_S_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_S_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_S_FE_IRQ_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_S_FE_IRQ_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_S_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_S_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_S_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_O_RE_IRQ_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_O_RE_IRQ_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_O_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_O_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_O_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_O_FE_IRQ_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_O_FE_IRQ_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_O_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_O_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_O_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_UPDATE_IRQ_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_UPDATE_IRQ_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_UPDATE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_UPDATE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_PL_EVT_IRQ_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_PL_EVT_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_IRQ_NOTIFY_PL_EVT_IRQ_MASK) /*! @} */ /*! @name TIO1_G0_CH3_IRQ_EN - TIO[i] channel [c] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_S_RE_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_S_RE_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_S_RE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_S_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_S_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_S_RE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_S_FE_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_S_FE_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_S_FE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_S_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_S_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_S_FE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_O_RE_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_O_RE_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_O_RE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_O_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_O_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_O_RE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_O_FE_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_O_FE_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_O_FE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_O_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_O_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_O_FE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_UPDATE_IRQ_EN_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_UPDATE_IRQ_EN_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_UPDATE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_UPDATE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_UPDATE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_UPDATE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_PL_EVT_IRQ_EN_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_PL_EVT_IRQ_EN_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_PL_EVT_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_PL_EVT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_PL_EVT_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_IRQ_EN_PL_EVT_IRQ_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH3_IRQ_FORCINT - TIO[i] channel [c] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_S_RE_IRQ_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_S_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_S_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_S_FE_IRQ_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_S_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_S_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_O_RE_IRQ_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_O_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_O_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_O_FE_IRQ_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_O_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_O_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_UPDATE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_PL_EVT_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK) /*! @} */ /*! @name TIO1_G0_CH3_IRQ_MODE - TIO[i] channel [c] IRQ mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TIO1_G0_CH3_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TIO1_G0_CH3_CTRL2 - TIO[i] group [g] channel [c] control register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL2_DUAL_CMP_EN_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL2_DUAL_CMP_EN_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL2_DUAL_CMP_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL2_DUAL_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_CTRL2_DUAL_CMP_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_CTRL2_DUAL_CMP_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL2_DUAL_CMP_MST_EN_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL2_DUAL_CMP_MST_EN_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL2_DUAL_CMP_MST_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_CTRL2_DUAL_CMP_MST_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_CTRL2_DUAL_CMP_MST_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_CTRL2_DUAL_CMP_MST_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH3_SINST - TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH3_SINST_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH3_SINST_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH3_SINST_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH3_SINST_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_SINST_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_SINST_OP_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_SINST_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH3_SINST_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH3_SINST_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH3_SINST_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_SINST_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_SINST_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_SINST_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH3_SINST_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH3_SINST_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_SINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_SINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_SINST_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_SINST_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH3_SINST_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH3_SINST_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_SINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_SINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_SINST_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH3_SCMD - TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH3_SCMD_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH3_SCMD_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH3_SCMD_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH3_SCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_SCMD_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_SCMD_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_SCMD_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH3_SCMD_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH3_SCMD_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_SCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_SCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_SCMD_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_SCMD_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH3_SCMD_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH3_SCMD_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_SCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_SCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_SCMD_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH3_SOP - TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ) */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH3_SOP_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH3_SOP_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH3_SOP_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH3_SOP_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_SOP_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_SOP_OP_MASK) /*! @} */ /*! @name TIO1_G0_CH3_OINST - TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH3_OINST_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH3_OINST_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH3_OINST_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH3_OINST_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_OINST_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_OINST_OP_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_OINST_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH3_OINST_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH3_OINST_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH3_OINST_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_OINST_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_OINST_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_OINST_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH3_OINST_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH3_OINST_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_OINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_OINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_OINST_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_OINST_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH3_OINST_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH3_OINST_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_OINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_OINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_OINST_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH3_OCMD - TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH3_OCMD_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH3_OCMD_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH3_OCMD_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH3_OCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_OCMD_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_OCMD_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_OCMD_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH3_OCMD_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH3_OCMD_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_OCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_OCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_OCMD_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH3_OCMD_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH3_OCMD_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH3_OCMD_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH3_OCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_OCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_OCMD_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH3_OOP - TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-) */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH3_OOP_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH3_OOP_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH3_OOP_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH3_OOP_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_OOP_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_OOP_OP_MASK) /*! @} */ /*! @name TIO1_G0_CH3_SHIFTCNT - TIO[i] channel [c] resource shift count register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH3_SHIFTCNT_CNT_MASK (0x1FU) #define GTM_gtm_cls1_TIO1_G0_CH3_SHIFTCNT_CNT_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH3_SHIFTCNT_CNT_WIDTH (5U) #define GTM_gtm_cls1_TIO1_G0_CH3_SHIFTCNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH3_SHIFTCNT_CNT_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH3_SHIFTCNT_CNT_MASK) /*! @} */ /*! @name TIO1_G0_CH4_CTRL - TIO[i] group [g] channel [c] control register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_S_RE_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_S_RE_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_S_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_S_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_S_FE_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_S_FE_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_S_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_S_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_O_RE_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_O_RE_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_O_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_O_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_O_FE_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_O_FE_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_O_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_O_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_PL_EVT_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_PL_EVT_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_PL_EVT_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (6U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK (0x80U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT (7U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_CYCLIC_INIT_TRIG_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_CYCLIC_INIT_TRIG_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_UPDATE_SRC_MASK (0xF00U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_UPDATE_SRC_SHIFT (8U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_UPDATE_SRC_WIDTH (4U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_UPDATE_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_CTRL_UPDATE_SRC_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_CTRL_UPDATE_SRC_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_S_MODE_MASK (0x3000U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_S_MODE_SHIFT (12U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_S_MODE_WIDTH (2U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_S_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_S_MODE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_S_MODE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_FREEZE_S_EN_MASK (0x4000U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_FREEZE_S_EN_SHIFT (14U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_FREEZE_S_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_FREEZE_S_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_FREEZE_S_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_FREEZE_S_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_CYCLIC_BUFF_MASK (0x8000U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_CYCLIC_BUFF_SHIFT (15U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_CYCLIC_BUFF_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_CYCLIC_BUFF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_CYCLIC_BUFF_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_CYCLIC_BUFF_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_O_MODE_MASK (0x70000U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_O_MODE_SHIFT (16U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_O_MODE_WIDTH (3U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_O_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_O_MODE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_O_MODE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_FREEZE_O_EN_MASK (0x80000U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_FREEZE_O_EN_SHIFT (19U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_FREEZE_O_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_FREEZE_O_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_FREEZE_O_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_FREEZE_O_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_ODIS_MASK (0x100000U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_ODIS_SHIFT (20U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_ODIS_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_ODIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_ODIS_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_ODIS_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_SEL_IN_MASK (0x200000U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_SEL_IN_SHIFT (21U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_SEL_IN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_SEL_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_SEL_IN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_SEL_IN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_O_TRIG_OUT_EN_MASK (0x400000U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_O_TRIG_OUT_EN_SHIFT (22U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_O_TRIG_OUT_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_O_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_O_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_O_TRIG_OUT_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_S_TRIG_OUT_EN_MASK (0x800000U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_S_TRIG_OUT_EN_SHIFT (23U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_S_TRIG_OUT_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_S_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_S_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_S_TRIG_OUT_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_S_RE_MASK (0x1000000U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_S_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_S_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_S_FE_MASK (0x2000000U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT (25U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_S_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_S_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_O_RE_MASK (0x4000000U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT (26U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_O_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_O_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_O_FE_MASK (0x8000000U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT (27U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_O_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_O_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10000000U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT (28U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK (0x20000000U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT (29U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_PL_EVT_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_UPD_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_UPD_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_CTRL_PL_TRIG_OUT_UPD_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH4_IRQ_NOTIFY - TIO[i] channel [c] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_S_RE_IRQ_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_S_RE_IRQ_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_S_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_S_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_S_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_S_FE_IRQ_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_S_FE_IRQ_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_S_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_S_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_S_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_O_RE_IRQ_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_O_RE_IRQ_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_O_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_O_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_O_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_O_FE_IRQ_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_O_FE_IRQ_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_O_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_O_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_O_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_UPDATE_IRQ_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_UPDATE_IRQ_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_UPDATE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_UPDATE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_PL_EVT_IRQ_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_PL_EVT_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_IRQ_NOTIFY_PL_EVT_IRQ_MASK) /*! @} */ /*! @name TIO1_G0_CH4_IRQ_EN - TIO[i] channel [c] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_S_RE_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_S_RE_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_S_RE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_S_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_S_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_S_RE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_S_FE_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_S_FE_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_S_FE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_S_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_S_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_S_FE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_O_RE_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_O_RE_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_O_RE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_O_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_O_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_O_RE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_O_FE_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_O_FE_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_O_FE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_O_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_O_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_O_FE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_UPDATE_IRQ_EN_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_UPDATE_IRQ_EN_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_UPDATE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_UPDATE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_UPDATE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_UPDATE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_PL_EVT_IRQ_EN_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_PL_EVT_IRQ_EN_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_PL_EVT_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_PL_EVT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_PL_EVT_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_IRQ_EN_PL_EVT_IRQ_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH4_IRQ_FORCINT - TIO[i] channel [c] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_S_RE_IRQ_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_S_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_S_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_S_FE_IRQ_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_S_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_S_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_O_RE_IRQ_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_O_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_O_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_O_FE_IRQ_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_O_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_O_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_UPDATE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_PL_EVT_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK) /*! @} */ /*! @name TIO1_G0_CH4_IRQ_MODE - TIO[i] channel [c] IRQ mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TIO1_G0_CH4_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TIO1_G0_CH4_CTRL2 - TIO[i] group [g] channel [c] control register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL2_DUAL_CMP_EN_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL2_DUAL_CMP_EN_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL2_DUAL_CMP_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL2_DUAL_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_CTRL2_DUAL_CMP_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_CTRL2_DUAL_CMP_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL2_DUAL_CMP_MST_EN_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL2_DUAL_CMP_MST_EN_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL2_DUAL_CMP_MST_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_CTRL2_DUAL_CMP_MST_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_CTRL2_DUAL_CMP_MST_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_CTRL2_DUAL_CMP_MST_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH4_SINST - TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH4_SINST_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH4_SINST_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH4_SINST_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH4_SINST_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_SINST_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_SINST_OP_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_SINST_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH4_SINST_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH4_SINST_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH4_SINST_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_SINST_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_SINST_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_SINST_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH4_SINST_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH4_SINST_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_SINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_SINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_SINST_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_SINST_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH4_SINST_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH4_SINST_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_SINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_SINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_SINST_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH4_SCMD - TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH4_SCMD_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH4_SCMD_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH4_SCMD_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH4_SCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_SCMD_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_SCMD_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_SCMD_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH4_SCMD_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH4_SCMD_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_SCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_SCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_SCMD_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_SCMD_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH4_SCMD_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH4_SCMD_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_SCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_SCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_SCMD_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH4_SOP - TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ) */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH4_SOP_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH4_SOP_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH4_SOP_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH4_SOP_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_SOP_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_SOP_OP_MASK) /*! @} */ /*! @name TIO1_G0_CH4_OINST - TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH4_OINST_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH4_OINST_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH4_OINST_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH4_OINST_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_OINST_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_OINST_OP_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_OINST_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH4_OINST_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH4_OINST_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH4_OINST_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_OINST_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_OINST_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_OINST_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH4_OINST_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH4_OINST_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_OINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_OINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_OINST_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_OINST_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH4_OINST_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH4_OINST_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_OINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_OINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_OINST_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH4_OCMD - TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH4_OCMD_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH4_OCMD_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH4_OCMD_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH4_OCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_OCMD_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_OCMD_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_OCMD_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH4_OCMD_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH4_OCMD_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_OCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_OCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_OCMD_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH4_OCMD_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH4_OCMD_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH4_OCMD_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH4_OCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_OCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_OCMD_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH4_OOP - TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-) */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH4_OOP_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH4_OOP_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH4_OOP_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH4_OOP_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_OOP_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_OOP_OP_MASK) /*! @} */ /*! @name TIO1_G0_CH4_SHIFTCNT - TIO[i] channel [c] resource shift count register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH4_SHIFTCNT_CNT_MASK (0x1FU) #define GTM_gtm_cls1_TIO1_G0_CH4_SHIFTCNT_CNT_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH4_SHIFTCNT_CNT_WIDTH (5U) #define GTM_gtm_cls1_TIO1_G0_CH4_SHIFTCNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH4_SHIFTCNT_CNT_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH4_SHIFTCNT_CNT_MASK) /*! @} */ /*! @name TIO1_G0_CH5_CTRL - TIO[i] group [g] channel [c] control register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_S_RE_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_S_RE_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_S_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_S_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_S_FE_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_S_FE_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_S_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_S_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_O_RE_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_O_RE_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_O_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_O_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_O_FE_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_O_FE_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_O_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_O_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_PL_EVT_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_PL_EVT_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_PL_EVT_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (6U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK (0x80U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT (7U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_CYCLIC_INIT_TRIG_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_CYCLIC_INIT_TRIG_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_UPDATE_SRC_MASK (0xF00U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_UPDATE_SRC_SHIFT (8U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_UPDATE_SRC_WIDTH (4U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_UPDATE_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_CTRL_UPDATE_SRC_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_CTRL_UPDATE_SRC_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_S_MODE_MASK (0x3000U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_S_MODE_SHIFT (12U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_S_MODE_WIDTH (2U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_S_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_S_MODE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_S_MODE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_FREEZE_S_EN_MASK (0x4000U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_FREEZE_S_EN_SHIFT (14U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_FREEZE_S_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_FREEZE_S_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_FREEZE_S_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_FREEZE_S_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_CYCLIC_BUFF_MASK (0x8000U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_CYCLIC_BUFF_SHIFT (15U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_CYCLIC_BUFF_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_CYCLIC_BUFF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_CYCLIC_BUFF_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_CYCLIC_BUFF_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_O_MODE_MASK (0x70000U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_O_MODE_SHIFT (16U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_O_MODE_WIDTH (3U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_O_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_O_MODE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_O_MODE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_FREEZE_O_EN_MASK (0x80000U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_FREEZE_O_EN_SHIFT (19U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_FREEZE_O_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_FREEZE_O_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_FREEZE_O_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_FREEZE_O_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_ODIS_MASK (0x100000U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_ODIS_SHIFT (20U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_ODIS_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_ODIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_ODIS_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_ODIS_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_SEL_IN_MASK (0x200000U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_SEL_IN_SHIFT (21U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_SEL_IN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_SEL_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_SEL_IN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_SEL_IN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_O_TRIG_OUT_EN_MASK (0x400000U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_O_TRIG_OUT_EN_SHIFT (22U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_O_TRIG_OUT_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_O_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_O_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_O_TRIG_OUT_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_S_TRIG_OUT_EN_MASK (0x800000U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_S_TRIG_OUT_EN_SHIFT (23U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_S_TRIG_OUT_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_S_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_S_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_S_TRIG_OUT_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_S_RE_MASK (0x1000000U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_S_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_S_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_S_FE_MASK (0x2000000U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT (25U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_S_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_S_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_O_RE_MASK (0x4000000U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT (26U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_O_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_O_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_O_FE_MASK (0x8000000U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT (27U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_O_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_O_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10000000U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT (28U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK (0x20000000U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT (29U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_PL_EVT_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_UPD_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_UPD_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_CTRL_PL_TRIG_OUT_UPD_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH5_IRQ_NOTIFY - TIO[i] channel [c] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_S_RE_IRQ_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_S_RE_IRQ_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_S_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_S_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_S_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_S_FE_IRQ_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_S_FE_IRQ_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_S_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_S_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_S_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_O_RE_IRQ_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_O_RE_IRQ_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_O_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_O_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_O_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_O_FE_IRQ_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_O_FE_IRQ_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_O_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_O_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_O_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_UPDATE_IRQ_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_UPDATE_IRQ_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_UPDATE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_UPDATE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_PL_EVT_IRQ_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_PL_EVT_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_IRQ_NOTIFY_PL_EVT_IRQ_MASK) /*! @} */ /*! @name TIO1_G0_CH5_IRQ_EN - TIO[i] channel [c] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_S_RE_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_S_RE_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_S_RE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_S_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_S_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_S_RE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_S_FE_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_S_FE_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_S_FE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_S_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_S_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_S_FE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_O_RE_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_O_RE_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_O_RE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_O_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_O_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_O_RE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_O_FE_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_O_FE_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_O_FE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_O_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_O_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_O_FE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_UPDATE_IRQ_EN_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_UPDATE_IRQ_EN_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_UPDATE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_UPDATE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_UPDATE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_UPDATE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_PL_EVT_IRQ_EN_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_PL_EVT_IRQ_EN_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_PL_EVT_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_PL_EVT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_PL_EVT_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_IRQ_EN_PL_EVT_IRQ_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH5_IRQ_FORCINT - TIO[i] channel [c] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_S_RE_IRQ_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_S_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_S_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_S_FE_IRQ_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_S_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_S_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_O_RE_IRQ_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_O_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_O_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_O_FE_IRQ_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_O_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_O_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_UPDATE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_PL_EVT_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK) /*! @} */ /*! @name TIO1_G0_CH5_IRQ_MODE - TIO[i] channel [c] IRQ mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TIO1_G0_CH5_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TIO1_G0_CH5_CTRL2 - TIO[i] group [g] channel [c] control register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL2_DUAL_CMP_EN_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL2_DUAL_CMP_EN_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL2_DUAL_CMP_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL2_DUAL_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_CTRL2_DUAL_CMP_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_CTRL2_DUAL_CMP_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL2_DUAL_CMP_MST_EN_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL2_DUAL_CMP_MST_EN_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL2_DUAL_CMP_MST_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_CTRL2_DUAL_CMP_MST_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_CTRL2_DUAL_CMP_MST_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_CTRL2_DUAL_CMP_MST_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH5_SINST - TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH5_SINST_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH5_SINST_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH5_SINST_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH5_SINST_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_SINST_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_SINST_OP_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_SINST_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH5_SINST_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH5_SINST_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH5_SINST_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_SINST_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_SINST_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_SINST_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH5_SINST_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH5_SINST_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_SINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_SINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_SINST_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_SINST_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH5_SINST_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH5_SINST_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_SINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_SINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_SINST_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH5_SCMD - TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH5_SCMD_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH5_SCMD_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH5_SCMD_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH5_SCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_SCMD_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_SCMD_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_SCMD_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH5_SCMD_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH5_SCMD_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_SCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_SCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_SCMD_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_SCMD_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH5_SCMD_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH5_SCMD_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_SCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_SCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_SCMD_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH5_SOP - TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ) */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH5_SOP_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH5_SOP_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH5_SOP_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH5_SOP_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_SOP_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_SOP_OP_MASK) /*! @} */ /*! @name TIO1_G0_CH5_OINST - TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH5_OINST_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH5_OINST_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH5_OINST_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH5_OINST_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_OINST_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_OINST_OP_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_OINST_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH5_OINST_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH5_OINST_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH5_OINST_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_OINST_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_OINST_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_OINST_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH5_OINST_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH5_OINST_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_OINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_OINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_OINST_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_OINST_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH5_OINST_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH5_OINST_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_OINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_OINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_OINST_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH5_OCMD - TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH5_OCMD_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH5_OCMD_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH5_OCMD_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH5_OCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_OCMD_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_OCMD_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_OCMD_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH5_OCMD_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH5_OCMD_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_OCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_OCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_OCMD_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH5_OCMD_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH5_OCMD_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH5_OCMD_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH5_OCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_OCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_OCMD_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH5_OOP - TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-) */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH5_OOP_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH5_OOP_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH5_OOP_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH5_OOP_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_OOP_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_OOP_OP_MASK) /*! @} */ /*! @name TIO1_G0_CH5_SHIFTCNT - TIO[i] channel [c] resource shift count register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH5_SHIFTCNT_CNT_MASK (0x1FU) #define GTM_gtm_cls1_TIO1_G0_CH5_SHIFTCNT_CNT_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH5_SHIFTCNT_CNT_WIDTH (5U) #define GTM_gtm_cls1_TIO1_G0_CH5_SHIFTCNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH5_SHIFTCNT_CNT_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH5_SHIFTCNT_CNT_MASK) /*! @} */ /*! @name TIO1_G0_CH6_CTRL - TIO[i] group [g] channel [c] control register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_S_RE_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_S_RE_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_S_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_S_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_S_FE_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_S_FE_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_S_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_S_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_O_RE_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_O_RE_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_O_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_O_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_O_FE_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_O_FE_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_O_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_O_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_PL_EVT_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_PL_EVT_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_PL_EVT_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (6U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK (0x80U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT (7U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_CYCLIC_INIT_TRIG_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_CYCLIC_INIT_TRIG_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_UPDATE_SRC_MASK (0xF00U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_UPDATE_SRC_SHIFT (8U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_UPDATE_SRC_WIDTH (4U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_UPDATE_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_CTRL_UPDATE_SRC_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_CTRL_UPDATE_SRC_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_S_MODE_MASK (0x3000U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_S_MODE_SHIFT (12U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_S_MODE_WIDTH (2U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_S_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_S_MODE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_S_MODE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_FREEZE_S_EN_MASK (0x4000U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_FREEZE_S_EN_SHIFT (14U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_FREEZE_S_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_FREEZE_S_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_FREEZE_S_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_FREEZE_S_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_CYCLIC_BUFF_MASK (0x8000U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_CYCLIC_BUFF_SHIFT (15U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_CYCLIC_BUFF_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_CYCLIC_BUFF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_CYCLIC_BUFF_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_CYCLIC_BUFF_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_O_MODE_MASK (0x70000U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_O_MODE_SHIFT (16U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_O_MODE_WIDTH (3U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_O_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_O_MODE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_O_MODE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_FREEZE_O_EN_MASK (0x80000U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_FREEZE_O_EN_SHIFT (19U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_FREEZE_O_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_FREEZE_O_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_FREEZE_O_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_FREEZE_O_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_ODIS_MASK (0x100000U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_ODIS_SHIFT (20U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_ODIS_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_ODIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_ODIS_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_ODIS_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_SEL_IN_MASK (0x200000U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_SEL_IN_SHIFT (21U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_SEL_IN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_SEL_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_SEL_IN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_SEL_IN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_O_TRIG_OUT_EN_MASK (0x400000U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_O_TRIG_OUT_EN_SHIFT (22U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_O_TRIG_OUT_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_O_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_O_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_O_TRIG_OUT_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_S_TRIG_OUT_EN_MASK (0x800000U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_S_TRIG_OUT_EN_SHIFT (23U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_S_TRIG_OUT_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_S_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_S_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_S_TRIG_OUT_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_S_RE_MASK (0x1000000U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_S_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_S_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_S_FE_MASK (0x2000000U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT (25U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_S_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_S_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_O_RE_MASK (0x4000000U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT (26U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_O_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_O_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_O_FE_MASK (0x8000000U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT (27U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_O_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_O_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10000000U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT (28U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK (0x20000000U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT (29U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_PL_EVT_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_UPD_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_UPD_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_CTRL_PL_TRIG_OUT_UPD_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH6_IRQ_NOTIFY - TIO[i] channel [c] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_S_RE_IRQ_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_S_RE_IRQ_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_S_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_S_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_S_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_S_FE_IRQ_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_S_FE_IRQ_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_S_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_S_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_S_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_O_RE_IRQ_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_O_RE_IRQ_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_O_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_O_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_O_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_O_FE_IRQ_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_O_FE_IRQ_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_O_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_O_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_O_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_UPDATE_IRQ_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_UPDATE_IRQ_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_UPDATE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_UPDATE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_PL_EVT_IRQ_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_PL_EVT_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_IRQ_NOTIFY_PL_EVT_IRQ_MASK) /*! @} */ /*! @name TIO1_G0_CH6_IRQ_EN - TIO[i] channel [c] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_S_RE_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_S_RE_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_S_RE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_S_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_S_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_S_RE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_S_FE_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_S_FE_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_S_FE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_S_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_S_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_S_FE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_O_RE_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_O_RE_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_O_RE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_O_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_O_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_O_RE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_O_FE_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_O_FE_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_O_FE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_O_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_O_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_O_FE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_UPDATE_IRQ_EN_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_UPDATE_IRQ_EN_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_UPDATE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_UPDATE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_UPDATE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_UPDATE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_PL_EVT_IRQ_EN_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_PL_EVT_IRQ_EN_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_PL_EVT_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_PL_EVT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_PL_EVT_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_IRQ_EN_PL_EVT_IRQ_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH6_IRQ_FORCINT - TIO[i] channel [c] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_S_RE_IRQ_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_S_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_S_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_S_FE_IRQ_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_S_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_S_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_O_RE_IRQ_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_O_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_O_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_O_FE_IRQ_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_O_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_O_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_UPDATE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_PL_EVT_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK) /*! @} */ /*! @name TIO1_G0_CH6_IRQ_MODE - TIO[i] channel [c] IRQ mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TIO1_G0_CH6_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TIO1_G0_CH6_CTRL2 - TIO[i] group [g] channel [c] control register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL2_DUAL_CMP_EN_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL2_DUAL_CMP_EN_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL2_DUAL_CMP_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL2_DUAL_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_CTRL2_DUAL_CMP_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_CTRL2_DUAL_CMP_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL2_DUAL_CMP_MST_EN_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL2_DUAL_CMP_MST_EN_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL2_DUAL_CMP_MST_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_CTRL2_DUAL_CMP_MST_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_CTRL2_DUAL_CMP_MST_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_CTRL2_DUAL_CMP_MST_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH6_SINST - TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH6_SINST_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH6_SINST_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH6_SINST_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH6_SINST_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_SINST_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_SINST_OP_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_SINST_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH6_SINST_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH6_SINST_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH6_SINST_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_SINST_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_SINST_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_SINST_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH6_SINST_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH6_SINST_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_SINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_SINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_SINST_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_SINST_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH6_SINST_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH6_SINST_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_SINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_SINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_SINST_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH6_SCMD - TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH6_SCMD_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH6_SCMD_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH6_SCMD_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH6_SCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_SCMD_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_SCMD_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_SCMD_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH6_SCMD_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH6_SCMD_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_SCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_SCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_SCMD_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_SCMD_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH6_SCMD_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH6_SCMD_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_SCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_SCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_SCMD_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH6_SOP - TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ) */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH6_SOP_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH6_SOP_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH6_SOP_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH6_SOP_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_SOP_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_SOP_OP_MASK) /*! @} */ /*! @name TIO1_G0_CH6_OINST - TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH6_OINST_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH6_OINST_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH6_OINST_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH6_OINST_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_OINST_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_OINST_OP_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_OINST_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH6_OINST_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH6_OINST_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH6_OINST_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_OINST_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_OINST_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_OINST_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH6_OINST_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH6_OINST_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_OINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_OINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_OINST_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_OINST_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH6_OINST_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH6_OINST_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_OINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_OINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_OINST_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH6_OCMD - TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH6_OCMD_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH6_OCMD_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH6_OCMD_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH6_OCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_OCMD_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_OCMD_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_OCMD_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH6_OCMD_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH6_OCMD_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_OCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_OCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_OCMD_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH6_OCMD_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH6_OCMD_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH6_OCMD_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH6_OCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_OCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_OCMD_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH6_OOP - TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-) */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH6_OOP_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH6_OOP_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH6_OOP_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH6_OOP_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_OOP_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_OOP_OP_MASK) /*! @} */ /*! @name TIO1_G0_CH6_SHIFTCNT - TIO[i] channel [c] resource shift count register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH6_SHIFTCNT_CNT_MASK (0x1FU) #define GTM_gtm_cls1_TIO1_G0_CH6_SHIFTCNT_CNT_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH6_SHIFTCNT_CNT_WIDTH (5U) #define GTM_gtm_cls1_TIO1_G0_CH6_SHIFTCNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH6_SHIFTCNT_CNT_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH6_SHIFTCNT_CNT_MASK) /*! @} */ /*! @name TIO1_G0_CH7_CTRL - TIO[i] group [g] channel [c] control register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_S_RE_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_S_RE_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_S_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_S_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_S_FE_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_S_FE_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_S_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_S_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_O_RE_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_O_RE_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_O_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_O_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_O_FE_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_O_FE_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_O_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_O_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_PL_EVT_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_PL_EVT_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_PL_EVT_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (6U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK (0x80U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT (7U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_CYCLIC_INIT_TRIG_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_CYCLIC_INIT_TRIG_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_UPDATE_SRC_MASK (0xF00U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_UPDATE_SRC_SHIFT (8U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_UPDATE_SRC_WIDTH (4U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_UPDATE_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_CTRL_UPDATE_SRC_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_CTRL_UPDATE_SRC_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_S_MODE_MASK (0x3000U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_S_MODE_SHIFT (12U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_S_MODE_WIDTH (2U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_S_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_S_MODE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_S_MODE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_FREEZE_S_EN_MASK (0x4000U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_FREEZE_S_EN_SHIFT (14U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_FREEZE_S_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_FREEZE_S_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_FREEZE_S_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_FREEZE_S_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_CYCLIC_BUFF_MASK (0x8000U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_CYCLIC_BUFF_SHIFT (15U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_CYCLIC_BUFF_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_CYCLIC_BUFF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_CYCLIC_BUFF_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_CYCLIC_BUFF_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_O_MODE_MASK (0x70000U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_O_MODE_SHIFT (16U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_O_MODE_WIDTH (3U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_O_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_O_MODE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_O_MODE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_FREEZE_O_EN_MASK (0x80000U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_FREEZE_O_EN_SHIFT (19U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_FREEZE_O_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_FREEZE_O_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_FREEZE_O_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_FREEZE_O_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_ODIS_MASK (0x100000U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_ODIS_SHIFT (20U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_ODIS_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_ODIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_ODIS_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_ODIS_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_SEL_IN_MASK (0x200000U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_SEL_IN_SHIFT (21U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_SEL_IN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_SEL_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_SEL_IN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_SEL_IN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_O_TRIG_OUT_EN_MASK (0x400000U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_O_TRIG_OUT_EN_SHIFT (22U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_O_TRIG_OUT_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_O_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_O_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_O_TRIG_OUT_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_S_TRIG_OUT_EN_MASK (0x800000U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_S_TRIG_OUT_EN_SHIFT (23U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_S_TRIG_OUT_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_S_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_S_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_S_TRIG_OUT_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_S_RE_MASK (0x1000000U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_S_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_S_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_S_FE_MASK (0x2000000U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT (25U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_S_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_S_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_O_RE_MASK (0x4000000U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT (26U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_O_RE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_O_RE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_O_FE_MASK (0x8000000U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT (27U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_O_FE_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_O_FE_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10000000U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT (28U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK (0x20000000U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT (29U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_PL_EVT_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_UPD_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_UPD_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_CTRL_PL_TRIG_OUT_UPD_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH7_IRQ_NOTIFY - TIO[i] channel [c] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_S_RE_IRQ_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_S_RE_IRQ_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_S_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_S_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_S_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_S_FE_IRQ_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_S_FE_IRQ_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_S_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_S_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_S_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_O_RE_IRQ_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_O_RE_IRQ_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_O_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_O_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_O_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_O_FE_IRQ_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_O_FE_IRQ_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_O_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_O_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_O_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_UPDATE_IRQ_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_UPDATE_IRQ_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_UPDATE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_UPDATE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_PL_EVT_IRQ_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_PL_EVT_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_IRQ_NOTIFY_PL_EVT_IRQ_MASK) /*! @} */ /*! @name TIO1_G0_CH7_IRQ_EN - TIO[i] channel [c] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_S_RE_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_S_RE_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_S_RE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_S_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_S_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_S_RE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_S_FE_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_S_FE_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_S_FE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_S_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_S_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_S_FE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_O_RE_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_O_RE_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_O_RE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_O_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_O_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_O_RE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_O_FE_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_O_FE_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_O_FE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_O_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_O_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_O_FE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_UPDATE_IRQ_EN_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_UPDATE_IRQ_EN_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_UPDATE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_UPDATE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_UPDATE_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_UPDATE_IRQ_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_PL_EVT_IRQ_EN_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_PL_EVT_IRQ_EN_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_PL_EVT_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_PL_EVT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_PL_EVT_IRQ_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_IRQ_EN_PL_EVT_IRQ_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH7_IRQ_FORCINT - TIO[i] channel [c] force interrupt register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_S_RE_IRQ_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_S_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_S_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_S_FE_IRQ_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_S_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_S_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_O_RE_IRQ_MASK (0x4U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT (2U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_O_RE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_O_RE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_O_FE_IRQ_MASK (0x8U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_O_FE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_O_FE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK (0x10U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_UPDATE_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK (0x20U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT (5U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_PL_EVT_IRQ_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK) /*! @} */ /*! @name TIO1_G0_CH7_IRQ_MODE - TIO[i] channel [c] IRQ mode configuration register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_TIO1_G0_CH7_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TIO1_G0_CH7_CTRL2 - TIO[i] group [g] channel [c] control register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL2_DUAL_CMP_EN_MASK (0x1U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL2_DUAL_CMP_EN_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL2_DUAL_CMP_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL2_DUAL_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_CTRL2_DUAL_CMP_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_CTRL2_DUAL_CMP_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL2_DUAL_CMP_MST_EN_MASK (0x2U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL2_DUAL_CMP_MST_EN_SHIFT (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL2_DUAL_CMP_MST_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_CTRL2_DUAL_CMP_MST_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_CTRL2_DUAL_CMP_MST_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_CTRL2_DUAL_CMP_MST_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH7_SINST - TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH7_SINST_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH7_SINST_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH7_SINST_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH7_SINST_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_SINST_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_SINST_OP_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_SINST_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH7_SINST_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH7_SINST_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH7_SINST_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_SINST_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_SINST_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_SINST_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH7_SINST_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH7_SINST_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_SINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_SINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_SINST_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_SINST_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH7_SINST_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH7_SINST_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_SINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_SINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_SINST_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH7_SCMD - TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH7_SCMD_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH7_SCMD_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH7_SCMD_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH7_SCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_SCMD_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_SCMD_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_SCMD_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH7_SCMD_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH7_SCMD_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_SCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_SCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_SCMD_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_SCMD_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH7_SCMD_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH7_SCMD_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_SCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_SCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_SCMD_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH7_SOP - TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ) */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH7_SOP_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH7_SOP_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH7_SOP_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH7_SOP_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_SOP_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_SOP_OP_MASK) /*! @} */ /*! @name TIO1_G0_CH7_OINST - TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH7_OINST_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH7_OINST_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH7_OINST_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH7_OINST_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_OINST_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_OINST_OP_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_OINST_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH7_OINST_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH7_OINST_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH7_OINST_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_OINST_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_OINST_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_OINST_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH7_OINST_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH7_OINST_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_OINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_OINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_OINST_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_OINST_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH7_OINST_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH7_OINST_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_OINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_OINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_OINST_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH7_OCMD - TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00- */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH7_OCMD_CMD_MASK (0x3F000000U) #define GTM_gtm_cls1_TIO1_G0_CH7_OCMD_CMD_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_CH7_OCMD_CMD_WIDTH (6U) #define GTM_gtm_cls1_TIO1_G0_CH7_OCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_OCMD_CMD_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_OCMD_CMD_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_OCMD_DATA_PUSH_EN_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_CH7_OCMD_DATA_PUSH_EN_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_CH7_OCMD_DATA_PUSH_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_OCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_OCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_OCMD_DATA_PUSH_EN_MASK) #define GTM_gtm_cls1_TIO1_G0_CH7_OCMD_INSTR_PULL_EN_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_CH7_OCMD_INSTR_PULL_EN_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_CH7_OCMD_INSTR_PULL_EN_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_CH7_OCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_OCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_OCMD_INSTR_PULL_EN_MASK) /*! @} */ /*! @name TIO1_G0_CH7_OOP - TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-) */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH7_OOP_OP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_TIO1_G0_CH7_OOP_OP_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH7_OOP_OP_WIDTH (24U) #define GTM_gtm_cls1_TIO1_G0_CH7_OOP_OP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_OOP_OP_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_OOP_OP_MASK) /*! @} */ /*! @name TIO1_G0_CH7_SHIFTCNT - TIO[i] channel [c] resource shift count register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_CH7_SHIFTCNT_CNT_MASK (0x1FU) #define GTM_gtm_cls1_TIO1_G0_CH7_SHIFTCNT_CNT_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_CH7_SHIFTCNT_CNT_WIDTH (5U) #define GTM_gtm_cls1_TIO1_G0_CH7_SHIFTCNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_CH7_SHIFTCNT_CNT_SHIFT)) & GTM_gtm_cls1_TIO1_G0_CH7_SHIFTCNT_CNT_MASK) /*! @} */ /*! @name TIO1_G0_ISEL0_CTRL1 - TIO[i] input selection register 1 */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_LUT2_0_MASK (0xFU) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_LUT2_0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_LUT2_0_WIDTH (4U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_LUT2_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_LUT2_0_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_LUT2_0_MASK) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_LUT2_1_MASK (0xF0U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_LUT2_1_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_LUT2_1_WIDTH (4U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_LUT2_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_LUT2_1_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_LUT2_1_MASK) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_LUT2_2_MASK (0xF00U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_LUT2_2_SHIFT (8U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_LUT2_2_WIDTH (4U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_LUT2_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_LUT2_2_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_LUT2_2_MASK) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_LUT2_3_MASK (0xF000U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_LUT2_3_SHIFT (12U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_LUT2_3_WIDTH (4U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_LUT2_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_LUT2_3_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_LUT2_3_MASK) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_OUT_SEL0_MASK (0x10000U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_OUT_SEL0_SHIFT (16U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_OUT_SEL0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_OUT_SEL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_OUT_SEL0_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_OUT_SEL0_MASK) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_OUT_SEL1_MASK (0x20000U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_OUT_SEL1_SHIFT (17U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_OUT_SEL1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_OUT_SEL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_OUT_SEL1_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_OUT_SEL1_MASK) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_OUT_SEL2_MASK (0x40000U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_OUT_SEL2_SHIFT (18U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_OUT_SEL2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_OUT_SEL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_OUT_SEL2_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_OUT_SEL2_MASK) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_OUT_SEL3_MASK (0x80000U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_OUT_SEL3_SHIFT (19U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_OUT_SEL3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_OUT_SEL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_OUT_SEL3_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_OUT_SEL3_MASK) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_WRITE_EN0_MASK (0x1000000U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_WRITE_EN0_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_WRITE_EN0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_WRITE_EN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_WRITE_EN0_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_WRITE_EN0_MASK) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_WRITE_EN1_MASK (0x2000000U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_WRITE_EN1_SHIFT (25U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_WRITE_EN1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_WRITE_EN1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_WRITE_EN1_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_WRITE_EN1_MASK) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_WRITE_EN2_MASK (0x4000000U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_WRITE_EN2_SHIFT (26U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_WRITE_EN2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_WRITE_EN2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_WRITE_EN2_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_WRITE_EN2_MASK) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_WRITE_EN3_MASK (0x8000000U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_WRITE_EN3_SHIFT (27U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_WRITE_EN3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_WRITE_EN3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_WRITE_EN3_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL1_WRITE_EN3_MASK) /*! @} */ /*! @name TIO1_G0_ISEL0_CTRL2 - TIO[i] input selection register 2 */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL2_LUT3_MASK (0xFFU) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL2_LUT3_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL2_LUT3_WIDTH (8U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL2_LUT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL2_LUT3_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL2_LUT3_MASK) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL2_QOUT_SEL_MASK (0x30000U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL2_QOUT_SEL_SHIFT (16U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL2_QOUT_SEL_WIDTH (2U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL2_QOUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL2_QOUT_SEL_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL2_QOUT_SEL_MASK) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL2_LUT3IN_SEL0_MASK (0x100000U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL2_LUT3IN_SEL0_SHIFT (20U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL2_LUT3IN_SEL0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL2_LUT3IN_SEL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL2_LUT3IN_SEL0_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL2_LUT3IN_SEL0_MASK) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL2_LUT3IN_SEL1_MASK (0x200000U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL2_LUT3IN_SEL1_SHIFT (21U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL2_LUT3IN_SEL1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL2_LUT3IN_SEL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL2_LUT3IN_SEL1_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL2_LUT3IN_SEL1_MASK) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL2_LUT3IN_SEL2_MASK (0x400000U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL2_LUT3IN_SEL2_SHIFT (22U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL2_LUT3IN_SEL2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL2_LUT3IN_SEL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL2_LUT3IN_SEL2_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL0_CTRL2_LUT3IN_SEL2_MASK) /*! @} */ /*! @name TIO1_G0_ISEL1_CTRL1 - TIO[i] input selection register 1 */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_LUT2_0_MASK (0xFU) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_LUT2_0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_LUT2_0_WIDTH (4U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_LUT2_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_LUT2_0_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_LUT2_0_MASK) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_LUT2_1_MASK (0xF0U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_LUT2_1_SHIFT (4U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_LUT2_1_WIDTH (4U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_LUT2_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_LUT2_1_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_LUT2_1_MASK) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_LUT2_2_MASK (0xF00U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_LUT2_2_SHIFT (8U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_LUT2_2_WIDTH (4U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_LUT2_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_LUT2_2_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_LUT2_2_MASK) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_LUT2_3_MASK (0xF000U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_LUT2_3_SHIFT (12U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_LUT2_3_WIDTH (4U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_LUT2_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_LUT2_3_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_LUT2_3_MASK) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_OUT_SEL0_MASK (0x10000U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_OUT_SEL0_SHIFT (16U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_OUT_SEL0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_OUT_SEL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_OUT_SEL0_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_OUT_SEL0_MASK) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_OUT_SEL1_MASK (0x20000U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_OUT_SEL1_SHIFT (17U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_OUT_SEL1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_OUT_SEL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_OUT_SEL1_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_OUT_SEL1_MASK) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_OUT_SEL2_MASK (0x40000U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_OUT_SEL2_SHIFT (18U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_OUT_SEL2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_OUT_SEL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_OUT_SEL2_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_OUT_SEL2_MASK) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_OUT_SEL3_MASK (0x80000U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_OUT_SEL3_SHIFT (19U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_OUT_SEL3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_OUT_SEL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_OUT_SEL3_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_OUT_SEL3_MASK) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_WRITE_EN0_MASK (0x1000000U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_WRITE_EN0_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_WRITE_EN0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_WRITE_EN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_WRITE_EN0_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_WRITE_EN0_MASK) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_WRITE_EN1_MASK (0x2000000U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_WRITE_EN1_SHIFT (25U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_WRITE_EN1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_WRITE_EN1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_WRITE_EN1_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_WRITE_EN1_MASK) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_WRITE_EN2_MASK (0x4000000U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_WRITE_EN2_SHIFT (26U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_WRITE_EN2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_WRITE_EN2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_WRITE_EN2_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_WRITE_EN2_MASK) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_WRITE_EN3_MASK (0x8000000U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_WRITE_EN3_SHIFT (27U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_WRITE_EN3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_WRITE_EN3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_WRITE_EN3_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL1_WRITE_EN3_MASK) /*! @} */ /*! @name TIO1_G0_ISEL1_CTRL2 - TIO[i] input selection register 2 */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL2_LUT3_MASK (0xFFU) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL2_LUT3_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL2_LUT3_WIDTH (8U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL2_LUT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL2_LUT3_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL2_LUT3_MASK) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL2_QOUT_SEL_MASK (0x30000U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL2_QOUT_SEL_SHIFT (16U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL2_QOUT_SEL_WIDTH (2U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL2_QOUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL2_QOUT_SEL_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL2_QOUT_SEL_MASK) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL2_LUT3IN_SEL0_MASK (0x100000U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL2_LUT3IN_SEL0_SHIFT (20U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL2_LUT3IN_SEL0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL2_LUT3IN_SEL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL2_LUT3IN_SEL0_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL2_LUT3IN_SEL0_MASK) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL2_LUT3IN_SEL1_MASK (0x200000U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL2_LUT3IN_SEL1_SHIFT (21U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL2_LUT3IN_SEL1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL2_LUT3IN_SEL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL2_LUT3IN_SEL1_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL2_LUT3IN_SEL1_MASK) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL2_LUT3IN_SEL2_MASK (0x400000U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL2_LUT3IN_SEL2_SHIFT (22U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL2_LUT3IN_SEL2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL2_LUT3IN_SEL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL2_LUT3IN_SEL2_SHIFT)) & GTM_gtm_cls1_TIO1_G0_ISEL1_CTRL2_LUT3IN_SEL2_MASK) /*! @} */ /*! @name TIO1_G0_OP_USAGE - TIO[i] operand usage selection register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE0_MASK (0x7U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE0_WIDTH (3U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE0_SHIFT)) & GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE0_MASK) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE1_MASK (0x38U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE1_SHIFT (3U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE1_WIDTH (3U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE1_SHIFT)) & GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE1_MASK) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE2_MASK (0x1C0U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE2_SHIFT (6U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE2_WIDTH (3U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE2_SHIFT)) & GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE2_MASK) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE3_MASK (0xE00U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE3_SHIFT (9U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE3_WIDTH (3U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE3_SHIFT)) & GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE3_MASK) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE4_MASK (0x7000U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE4_SHIFT (12U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE4_WIDTH (3U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE4_SHIFT)) & GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE4_MASK) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE5_MASK (0x38000U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE5_SHIFT (15U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE5_WIDTH (3U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE5_SHIFT)) & GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE5_MASK) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE6_MASK (0x1C0000U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE6_SHIFT (18U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE6_WIDTH (3U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE6_SHIFT)) & GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE6_MASK) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE7_MASK (0xE00000U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE7_SHIFT (21U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE7_WIDTH (3U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE7_SHIFT)) & GTM_gtm_cls1_TIO1_G0_OP_USAGE_MODE7_MASK) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN0_MASK (0x1000000U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN0_SHIFT (24U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN0_SHIFT)) & GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN0_MASK) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN1_MASK (0x2000000U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN1_SHIFT (25U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN1_SHIFT)) & GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN1_MASK) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN2_MASK (0x4000000U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN2_SHIFT (26U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN2_SHIFT)) & GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN2_MASK) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN3_MASK (0x8000000U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN3_SHIFT (27U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN3_SHIFT)) & GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN3_MASK) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN4_MASK (0x10000000U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN4_SHIFT (28U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN4_SHIFT)) & GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN4_MASK) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN5_MASK (0x20000000U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN5_SHIFT (29U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN5_SHIFT)) & GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN5_MASK) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN6_MASK (0x40000000U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN6_SHIFT (30U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN6_SHIFT)) & GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN6_MASK) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN7_MASK (0x80000000U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN7_SHIFT (31U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN7_SHIFT)) & GTM_gtm_cls1_TIO1_G0_OP_USAGE_WRITE_EN7_MASK) /*! @} */ /*! @name TIO1_S - TIO[i] signal sampling register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_S_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_S_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_S_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_S_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_S_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_S_CH0_MASK) #define GTM_gtm_cls1_TIO1_S_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_S_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_S_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_S_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_S_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_S_CH1_MASK) #define GTM_gtm_cls1_TIO1_S_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_S_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_S_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_S_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_S_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_S_CH2_MASK) #define GTM_gtm_cls1_TIO1_S_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_S_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_S_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_S_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_S_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_S_CH3_MASK) #define GTM_gtm_cls1_TIO1_S_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_S_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_S_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_S_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_S_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_S_CH4_MASK) #define GTM_gtm_cls1_TIO1_S_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_S_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_S_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_S_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_S_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_S_CH5_MASK) #define GTM_gtm_cls1_TIO1_S_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_S_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_S_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_S_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_S_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_S_CH6_MASK) #define GTM_gtm_cls1_TIO1_S_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_S_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_S_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_S_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_S_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_S_CH7_MASK) /*! @} */ /*! @name TIO1_O - TIO[i] output register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_O_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_O_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_O_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_O_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_O_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_O_CH0_MASK) #define GTM_gtm_cls1_TIO1_O_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_O_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_O_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_O_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_O_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_O_CH1_MASK) #define GTM_gtm_cls1_TIO1_O_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_O_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_O_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_O_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_O_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_O_CH2_MASK) #define GTM_gtm_cls1_TIO1_O_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_O_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_O_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_O_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_O_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_O_CH3_MASK) #define GTM_gtm_cls1_TIO1_O_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_O_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_O_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_O_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_O_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_O_CH4_MASK) #define GTM_gtm_cls1_TIO1_O_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_O_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_O_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_O_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_O_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_O_CH5_MASK) #define GTM_gtm_cls1_TIO1_O_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_O_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_O_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_O_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_O_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_O_CH6_MASK) #define GTM_gtm_cls1_TIO1_O_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_O_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_O_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_O_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_O_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_O_CH7_MASK) /*! @} */ /*! @name TIO1_ENDIS - TIO[i] enable/disable register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_ENDIS_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_ENDIS_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_ENDIS_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_ENDIS_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_ENDIS_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_ENDIS_CH0_MASK) #define GTM_gtm_cls1_TIO1_ENDIS_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_ENDIS_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_ENDIS_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_ENDIS_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_ENDIS_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_ENDIS_CH1_MASK) #define GTM_gtm_cls1_TIO1_ENDIS_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_ENDIS_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_ENDIS_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_ENDIS_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_ENDIS_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_ENDIS_CH2_MASK) #define GTM_gtm_cls1_TIO1_ENDIS_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_ENDIS_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_ENDIS_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_ENDIS_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_ENDIS_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_ENDIS_CH3_MASK) #define GTM_gtm_cls1_TIO1_ENDIS_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_ENDIS_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_ENDIS_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_ENDIS_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_ENDIS_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_ENDIS_CH4_MASK) #define GTM_gtm_cls1_TIO1_ENDIS_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_ENDIS_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_ENDIS_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_ENDIS_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_ENDIS_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_ENDIS_CH5_MASK) #define GTM_gtm_cls1_TIO1_ENDIS_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_ENDIS_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_ENDIS_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_ENDIS_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_ENDIS_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_ENDIS_CH6_MASK) #define GTM_gtm_cls1_TIO1_ENDIS_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_ENDIS_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_ENDIS_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_ENDIS_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_ENDIS_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_ENDIS_CH7_MASK) /*! @} */ /*! @name TIO1_INVERT - TIO[i] signal invert register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_INVERT_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_INVERT_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_INVERT_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_INVERT_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_INVERT_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_INVERT_CH0_MASK) #define GTM_gtm_cls1_TIO1_INVERT_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_INVERT_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_INVERT_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_INVERT_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_INVERT_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_INVERT_CH1_MASK) #define GTM_gtm_cls1_TIO1_INVERT_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_INVERT_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_INVERT_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_INVERT_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_INVERT_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_INVERT_CH2_MASK) #define GTM_gtm_cls1_TIO1_INVERT_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_INVERT_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_INVERT_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_INVERT_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_INVERT_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_INVERT_CH3_MASK) #define GTM_gtm_cls1_TIO1_INVERT_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_INVERT_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_INVERT_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_INVERT_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_INVERT_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_INVERT_CH4_MASK) #define GTM_gtm_cls1_TIO1_INVERT_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_INVERT_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_INVERT_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_INVERT_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_INVERT_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_INVERT_CH5_MASK) #define GTM_gtm_cls1_TIO1_INVERT_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_INVERT_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_INVERT_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_INVERT_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_INVERT_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_INVERT_CH6_MASK) #define GTM_gtm_cls1_TIO1_INVERT_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_INVERT_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_INVERT_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_INVERT_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_INVERT_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_INVERT_CH7_MASK) /*! @} */ /*! @name TIO1_INPUT_MODE - TIO[i] input mode register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_INPUT_MODE_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_INPUT_MODE_CH0_MASK) #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_INPUT_MODE_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_INPUT_MODE_CH1_MASK) #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_INPUT_MODE_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_INPUT_MODE_CH2_MASK) #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_INPUT_MODE_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_INPUT_MODE_CH3_MASK) #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_INPUT_MODE_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_INPUT_MODE_CH4_MASK) #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_INPUT_MODE_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_INPUT_MODE_CH5_MASK) #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_INPUT_MODE_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_INPUT_MODE_CH6_MASK) #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_INPUT_MODE_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_INPUT_MODE_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_INPUT_MODE_CH7_MASK) /*! @} */ /*! @name TIO1_CYCLIC_MODE - TIO[i] cyclic mode register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH0_MASK) #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH1_MASK) #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH2_MASK) #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH3_MASK) #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH4_MASK) #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH5_MASK) #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH6_MASK) #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_CYCLIC_MODE_CH7_MASK) /*! @} */ /*! @name TIO1_TRIG_OUT_GATE_EN - TIO[i] enable Trigger Output, output gating register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH0_MASK) #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH1_MASK) #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH2_MASK) #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH3_MASK) #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH4_MASK) #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH5_MASK) #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH6_MASK) #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_TRIG_OUT_GATE_EN_CH7_MASK) /*! @} */ /*! @name TIO1_PLTRIG_OUT_GATE_EN - TIO[i] enable PL_TRIG_OUT output gating register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH0_MASK) #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH1_MASK) #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH2_MASK) #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH3_MASK) #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH4_MASK) #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH5_MASK) #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH6_MASK) #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_PLTRIG_OUT_GATE_EN_CH7_MASK) /*! @} */ /*! @name TIO1_CS - TIO[i] clear signal sampling register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_CS_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_CS_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_CS_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CS_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CS_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_CS_CH0_MASK) #define GTM_gtm_cls1_TIO1_CS_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_CS_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_CS_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CS_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CS_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_CS_CH1_MASK) #define GTM_gtm_cls1_TIO1_CS_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_CS_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_CS_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CS_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CS_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_CS_CH2_MASK) #define GTM_gtm_cls1_TIO1_CS_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_CS_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_CS_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CS_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CS_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_CS_CH3_MASK) #define GTM_gtm_cls1_TIO1_CS_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_CS_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_CS_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CS_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CS_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_CS_CH4_MASK) #define GTM_gtm_cls1_TIO1_CS_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_CS_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_CS_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CS_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CS_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_CS_CH5_MASK) #define GTM_gtm_cls1_TIO1_CS_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_CS_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_CS_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CS_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CS_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_CS_CH6_MASK) #define GTM_gtm_cls1_TIO1_CS_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_CS_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_CS_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CS_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CS_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_CS_CH7_MASK) /*! @} */ /*! @name TIO1_CO - TIO[i] clear output register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_CO_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_CO_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_CO_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CO_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CO_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_CO_CH0_MASK) #define GTM_gtm_cls1_TIO1_CO_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_CO_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_CO_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CO_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CO_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_CO_CH1_MASK) #define GTM_gtm_cls1_TIO1_CO_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_CO_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_CO_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CO_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CO_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_CO_CH2_MASK) #define GTM_gtm_cls1_TIO1_CO_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_CO_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_CO_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CO_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CO_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_CO_CH3_MASK) #define GTM_gtm_cls1_TIO1_CO_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_CO_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_CO_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CO_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CO_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_CO_CH4_MASK) #define GTM_gtm_cls1_TIO1_CO_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_CO_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_CO_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CO_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CO_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_CO_CH5_MASK) #define GTM_gtm_cls1_TIO1_CO_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_CO_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_CO_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CO_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CO_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_CO_CH6_MASK) #define GTM_gtm_cls1_TIO1_CO_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_CO_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_CO_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CO_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CO_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_CO_CH7_MASK) /*! @} */ /*! @name TIO1_CENDIS - TIO[i] disable register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_CENDIS_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_CENDIS_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_CENDIS_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CENDIS_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CENDIS_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_CENDIS_CH0_MASK) #define GTM_gtm_cls1_TIO1_CENDIS_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_CENDIS_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_CENDIS_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CENDIS_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CENDIS_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_CENDIS_CH1_MASK) #define GTM_gtm_cls1_TIO1_CENDIS_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_CENDIS_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_CENDIS_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CENDIS_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CENDIS_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_CENDIS_CH2_MASK) #define GTM_gtm_cls1_TIO1_CENDIS_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_CENDIS_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_CENDIS_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CENDIS_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CENDIS_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_CENDIS_CH3_MASK) #define GTM_gtm_cls1_TIO1_CENDIS_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_CENDIS_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_CENDIS_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CENDIS_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CENDIS_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_CENDIS_CH4_MASK) #define GTM_gtm_cls1_TIO1_CENDIS_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_CENDIS_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_CENDIS_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CENDIS_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CENDIS_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_CENDIS_CH5_MASK) #define GTM_gtm_cls1_TIO1_CENDIS_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_CENDIS_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_CENDIS_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CENDIS_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CENDIS_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_CENDIS_CH6_MASK) #define GTM_gtm_cls1_TIO1_CENDIS_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_CENDIS_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_CENDIS_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CENDIS_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CENDIS_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_CENDIS_CH7_MASK) /*! @} */ /*! @name TIO1_CINVERT - TIO[i] clear signal invert register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_CINVERT_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_CINVERT_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_CINVERT_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CINVERT_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CINVERT_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_CINVERT_CH0_MASK) #define GTM_gtm_cls1_TIO1_CINVERT_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_CINVERT_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_CINVERT_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CINVERT_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CINVERT_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_CINVERT_CH1_MASK) #define GTM_gtm_cls1_TIO1_CINVERT_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_CINVERT_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_CINVERT_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CINVERT_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CINVERT_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_CINVERT_CH2_MASK) #define GTM_gtm_cls1_TIO1_CINVERT_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_CINVERT_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_CINVERT_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CINVERT_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CINVERT_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_CINVERT_CH3_MASK) #define GTM_gtm_cls1_TIO1_CINVERT_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_CINVERT_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_CINVERT_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CINVERT_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CINVERT_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_CINVERT_CH4_MASK) #define GTM_gtm_cls1_TIO1_CINVERT_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_CINVERT_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_CINVERT_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CINVERT_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CINVERT_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_CINVERT_CH5_MASK) #define GTM_gtm_cls1_TIO1_CINVERT_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_CINVERT_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_CINVERT_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CINVERT_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CINVERT_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_CINVERT_CH6_MASK) #define GTM_gtm_cls1_TIO1_CINVERT_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_CINVERT_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_CINVERT_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CINVERT_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CINVERT_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_CINVERT_CH7_MASK) /*! @} */ /*! @name TIO1_CINPUT_MODE - TIO[i] disable input mode register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CINPUT_MODE_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_CINPUT_MODE_CH0_MASK) #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CINPUT_MODE_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_CINPUT_MODE_CH1_MASK) #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CINPUT_MODE_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_CINPUT_MODE_CH2_MASK) #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CINPUT_MODE_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_CINPUT_MODE_CH3_MASK) #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CINPUT_MODE_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_CINPUT_MODE_CH4_MASK) #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CINPUT_MODE_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_CINPUT_MODE_CH5_MASK) #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CINPUT_MODE_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_CINPUT_MODE_CH6_MASK) #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CINPUT_MODE_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CINPUT_MODE_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_CINPUT_MODE_CH7_MASK) /*! @} */ /*! @name TIO1_CCYCLIC_MODE - TIO[i] disable cyclic mode register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH0_MASK) #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH1_MASK) #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH2_MASK) #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH3_MASK) #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH4_MASK) #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH5_MASK) #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH6_MASK) #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_CCYCLIC_MODE_CH7_MASK) /*! @} */ /*! @name TIO1_CTRIG_OUT_GATE_EN - TIO[i] clear Trigger Output, output gating register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH0_MASK) #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH1_MASK) #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH2_MASK) #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH3_MASK) #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH4_MASK) #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH5_MASK) #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH6_MASK) #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_CTRIG_OUT_GATE_EN_CH7_MASK) /*! @} */ /*! @name TIO1_CPLTRIG_OUT_GATE_EN - TIO[i] clear PL_TRIG_OUT output gating register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH0_MASK) #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH1_MASK) #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH2_MASK) #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH3_MASK) #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH4_MASK) #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH5_MASK) #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH6_MASK) #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_CPLTRIG_OUT_GATE_EN_CH7_MASK) /*! @} */ /*! @name TIO1_SS - TIO[i] set signal sampling register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_SS_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_SS_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_SS_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SS_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SS_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_SS_CH0_MASK) #define GTM_gtm_cls1_TIO1_SS_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_SS_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_SS_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SS_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SS_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_SS_CH1_MASK) #define GTM_gtm_cls1_TIO1_SS_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_SS_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_SS_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SS_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SS_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_SS_CH2_MASK) #define GTM_gtm_cls1_TIO1_SS_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_SS_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_SS_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SS_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SS_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_SS_CH3_MASK) #define GTM_gtm_cls1_TIO1_SS_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_SS_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_SS_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SS_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SS_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_SS_CH4_MASK) #define GTM_gtm_cls1_TIO1_SS_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_SS_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_SS_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SS_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SS_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_SS_CH5_MASK) #define GTM_gtm_cls1_TIO1_SS_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_SS_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_SS_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SS_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SS_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_SS_CH6_MASK) #define GTM_gtm_cls1_TIO1_SS_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_SS_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_SS_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SS_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SS_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_SS_CH7_MASK) /*! @} */ /*! @name TIO1_SO - TIO[i] set output register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_SO_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_SO_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_SO_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SO_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SO_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_SO_CH0_MASK) #define GTM_gtm_cls1_TIO1_SO_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_SO_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_SO_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SO_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SO_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_SO_CH1_MASK) #define GTM_gtm_cls1_TIO1_SO_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_SO_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_SO_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SO_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SO_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_SO_CH2_MASK) #define GTM_gtm_cls1_TIO1_SO_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_SO_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_SO_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SO_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SO_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_SO_CH3_MASK) #define GTM_gtm_cls1_TIO1_SO_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_SO_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_SO_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SO_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SO_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_SO_CH4_MASK) #define GTM_gtm_cls1_TIO1_SO_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_SO_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_SO_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SO_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SO_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_SO_CH5_MASK) #define GTM_gtm_cls1_TIO1_SO_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_SO_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_SO_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SO_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SO_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_SO_CH6_MASK) #define GTM_gtm_cls1_TIO1_SO_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_SO_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_SO_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SO_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SO_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_SO_CH7_MASK) /*! @} */ /*! @name TIO1_SENDIS - TIO[i] enable register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_SENDIS_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_SENDIS_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_SENDIS_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SENDIS_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SENDIS_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_SENDIS_CH0_MASK) #define GTM_gtm_cls1_TIO1_SENDIS_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_SENDIS_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_SENDIS_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SENDIS_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SENDIS_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_SENDIS_CH1_MASK) #define GTM_gtm_cls1_TIO1_SENDIS_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_SENDIS_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_SENDIS_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SENDIS_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SENDIS_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_SENDIS_CH2_MASK) #define GTM_gtm_cls1_TIO1_SENDIS_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_SENDIS_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_SENDIS_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SENDIS_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SENDIS_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_SENDIS_CH3_MASK) #define GTM_gtm_cls1_TIO1_SENDIS_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_SENDIS_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_SENDIS_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SENDIS_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SENDIS_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_SENDIS_CH4_MASK) #define GTM_gtm_cls1_TIO1_SENDIS_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_SENDIS_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_SENDIS_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SENDIS_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SENDIS_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_SENDIS_CH5_MASK) #define GTM_gtm_cls1_TIO1_SENDIS_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_SENDIS_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_SENDIS_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SENDIS_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SENDIS_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_SENDIS_CH6_MASK) #define GTM_gtm_cls1_TIO1_SENDIS_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_SENDIS_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_SENDIS_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SENDIS_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SENDIS_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_SENDIS_CH7_MASK) /*! @} */ /*! @name TIO1_SINVERT - TIO[i] set signal invert register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_SINVERT_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_SINVERT_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_SINVERT_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SINVERT_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SINVERT_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_SINVERT_CH0_MASK) #define GTM_gtm_cls1_TIO1_SINVERT_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_SINVERT_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_SINVERT_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SINVERT_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SINVERT_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_SINVERT_CH1_MASK) #define GTM_gtm_cls1_TIO1_SINVERT_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_SINVERT_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_SINVERT_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SINVERT_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SINVERT_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_SINVERT_CH2_MASK) #define GTM_gtm_cls1_TIO1_SINVERT_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_SINVERT_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_SINVERT_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SINVERT_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SINVERT_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_SINVERT_CH3_MASK) #define GTM_gtm_cls1_TIO1_SINVERT_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_SINVERT_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_SINVERT_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SINVERT_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SINVERT_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_SINVERT_CH4_MASK) #define GTM_gtm_cls1_TIO1_SINVERT_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_SINVERT_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_SINVERT_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SINVERT_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SINVERT_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_SINVERT_CH5_MASK) #define GTM_gtm_cls1_TIO1_SINVERT_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_SINVERT_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_SINVERT_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SINVERT_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SINVERT_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_SINVERT_CH6_MASK) #define GTM_gtm_cls1_TIO1_SINVERT_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_SINVERT_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_SINVERT_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SINVERT_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SINVERT_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_SINVERT_CH7_MASK) /*! @} */ /*! @name TIO1_SINPUT_MODE - TIO[i] enable input mode register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SINPUT_MODE_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_SINPUT_MODE_CH0_MASK) #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SINPUT_MODE_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_SINPUT_MODE_CH1_MASK) #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SINPUT_MODE_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_SINPUT_MODE_CH2_MASK) #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SINPUT_MODE_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_SINPUT_MODE_CH3_MASK) #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SINPUT_MODE_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_SINPUT_MODE_CH4_MASK) #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SINPUT_MODE_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_SINPUT_MODE_CH5_MASK) #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SINPUT_MODE_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_SINPUT_MODE_CH6_MASK) #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SINPUT_MODE_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SINPUT_MODE_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_SINPUT_MODE_CH7_MASK) /*! @} */ /*! @name TIO1_SCYCLIC_MODE - TIO[i] enable cyclic mode register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH0_MASK) #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH1_MASK) #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH2_MASK) #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH3_MASK) #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH4_MASK) #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH5_MASK) #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH6_MASK) #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_SCYCLIC_MODE_CH7_MASK) /*! @} */ /*! @name TIO1_STRIG_OUT_GATE_EN - TIO[i] set Trigger Output, output gating register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH0_MASK) #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH1_MASK) #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH2_MASK) #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH3_MASK) #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH4_MASK) #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH5_MASK) #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH6_MASK) #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_STRIG_OUT_GATE_EN_CH7_MASK) /*! @} */ /*! @name TIO1_SPLTRIG_OUT_GATE_EN - TIO[i] set PL_TRIG_OUT output gating register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH0_MASK) #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH1_MASK) #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH2_MASK) #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH3_MASK) #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH4_MASK) #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH5_MASK) #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH6_MASK) #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_SPLTRIG_OUT_GATE_EN_CH7_MASK) /*! @} */ /*! @name TIO1_IS - TIO[i] invert signal sampling register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_IS_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_IS_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_IS_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IS_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IS_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_IS_CH0_MASK) #define GTM_gtm_cls1_TIO1_IS_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_IS_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_IS_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IS_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IS_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_IS_CH1_MASK) #define GTM_gtm_cls1_TIO1_IS_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_IS_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_IS_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IS_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IS_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_IS_CH2_MASK) #define GTM_gtm_cls1_TIO1_IS_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_IS_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_IS_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IS_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IS_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_IS_CH3_MASK) #define GTM_gtm_cls1_TIO1_IS_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_IS_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_IS_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IS_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IS_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_IS_CH4_MASK) #define GTM_gtm_cls1_TIO1_IS_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_IS_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_IS_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IS_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IS_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_IS_CH5_MASK) #define GTM_gtm_cls1_TIO1_IS_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_IS_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_IS_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IS_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IS_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_IS_CH6_MASK) #define GTM_gtm_cls1_TIO1_IS_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_IS_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_IS_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IS_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IS_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_IS_CH7_MASK) /*! @} */ /*! @name TIO1_IO - TIO[i] invert output register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_IO_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_IO_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_IO_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IO_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IO_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_IO_CH0_MASK) #define GTM_gtm_cls1_TIO1_IO_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_IO_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_IO_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IO_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IO_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_IO_CH1_MASK) #define GTM_gtm_cls1_TIO1_IO_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_IO_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_IO_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IO_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IO_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_IO_CH2_MASK) #define GTM_gtm_cls1_TIO1_IO_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_IO_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_IO_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IO_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IO_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_IO_CH3_MASK) #define GTM_gtm_cls1_TIO1_IO_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_IO_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_IO_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IO_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IO_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_IO_CH4_MASK) #define GTM_gtm_cls1_TIO1_IO_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_IO_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_IO_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IO_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IO_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_IO_CH5_MASK) #define GTM_gtm_cls1_TIO1_IO_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_IO_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_IO_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IO_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IO_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_IO_CH6_MASK) #define GTM_gtm_cls1_TIO1_IO_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_IO_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_IO_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IO_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IO_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_IO_CH7_MASK) /*! @} */ /*! @name TIO1_IENDIS - TIO[i] toggle enable/disable register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_IENDIS_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_IENDIS_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_IENDIS_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IENDIS_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IENDIS_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_IENDIS_CH0_MASK) #define GTM_gtm_cls1_TIO1_IENDIS_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_IENDIS_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_IENDIS_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IENDIS_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IENDIS_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_IENDIS_CH1_MASK) #define GTM_gtm_cls1_TIO1_IENDIS_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_IENDIS_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_IENDIS_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IENDIS_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IENDIS_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_IENDIS_CH2_MASK) #define GTM_gtm_cls1_TIO1_IENDIS_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_IENDIS_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_IENDIS_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IENDIS_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IENDIS_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_IENDIS_CH3_MASK) #define GTM_gtm_cls1_TIO1_IENDIS_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_IENDIS_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_IENDIS_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IENDIS_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IENDIS_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_IENDIS_CH4_MASK) #define GTM_gtm_cls1_TIO1_IENDIS_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_IENDIS_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_IENDIS_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IENDIS_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IENDIS_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_IENDIS_CH5_MASK) #define GTM_gtm_cls1_TIO1_IENDIS_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_IENDIS_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_IENDIS_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IENDIS_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IENDIS_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_IENDIS_CH6_MASK) #define GTM_gtm_cls1_TIO1_IENDIS_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_IENDIS_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_IENDIS_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IENDIS_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IENDIS_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_IENDIS_CH7_MASK) /*! @} */ /*! @name TIO1_IINVERT - TIO[i] toggle signal invert register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_IINVERT_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_IINVERT_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_IINVERT_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IINVERT_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IINVERT_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_IINVERT_CH0_MASK) #define GTM_gtm_cls1_TIO1_IINVERT_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_IINVERT_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_IINVERT_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IINVERT_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IINVERT_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_IINVERT_CH1_MASK) #define GTM_gtm_cls1_TIO1_IINVERT_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_IINVERT_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_IINVERT_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IINVERT_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IINVERT_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_IINVERT_CH2_MASK) #define GTM_gtm_cls1_TIO1_IINVERT_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_IINVERT_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_IINVERT_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IINVERT_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IINVERT_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_IINVERT_CH3_MASK) #define GTM_gtm_cls1_TIO1_IINVERT_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_IINVERT_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_IINVERT_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IINVERT_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IINVERT_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_IINVERT_CH4_MASK) #define GTM_gtm_cls1_TIO1_IINVERT_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_IINVERT_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_IINVERT_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IINVERT_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IINVERT_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_IINVERT_CH5_MASK) #define GTM_gtm_cls1_TIO1_IINVERT_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_IINVERT_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_IINVERT_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IINVERT_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IINVERT_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_IINVERT_CH6_MASK) #define GTM_gtm_cls1_TIO1_IINVERT_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_IINVERT_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_IINVERT_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IINVERT_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IINVERT_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_IINVERT_CH7_MASK) /*! @} */ /*! @name TIO1_IINPUT_MODE - TIO[i] enable input mode register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IINPUT_MODE_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_IINPUT_MODE_CH0_MASK) #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IINPUT_MODE_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_IINPUT_MODE_CH1_MASK) #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IINPUT_MODE_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_IINPUT_MODE_CH2_MASK) #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IINPUT_MODE_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_IINPUT_MODE_CH3_MASK) #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IINPUT_MODE_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_IINPUT_MODE_CH4_MASK) #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IINPUT_MODE_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_IINPUT_MODE_CH5_MASK) #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IINPUT_MODE_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_IINPUT_MODE_CH6_MASK) #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_IINPUT_MODE_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_IINPUT_MODE_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_IINPUT_MODE_CH7_MASK) /*! @} */ /*! @name TIO1_ICYCLIC_MODE - TIO[i] enable cyclic mode register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH0_MASK) #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH1_MASK) #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH2_MASK) #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH3_MASK) #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH4_MASK) #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH5_MASK) #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH6_MASK) #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_ICYCLIC_MODE_CH7_MASK) /*! @} */ /*! @name TIO1_FUPD - TIO[i] force update register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_FUPD_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_FUPD_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_FUPD_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_FUPD_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_FUPD_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_FUPD_CH0_MASK) #define GTM_gtm_cls1_TIO1_FUPD_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_FUPD_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_FUPD_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_FUPD_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_FUPD_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_FUPD_CH1_MASK) #define GTM_gtm_cls1_TIO1_FUPD_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_FUPD_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_FUPD_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_FUPD_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_FUPD_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_FUPD_CH2_MASK) #define GTM_gtm_cls1_TIO1_FUPD_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_FUPD_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_FUPD_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_FUPD_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_FUPD_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_FUPD_CH3_MASK) #define GTM_gtm_cls1_TIO1_FUPD_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_FUPD_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_FUPD_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_FUPD_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_FUPD_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_FUPD_CH4_MASK) #define GTM_gtm_cls1_TIO1_FUPD_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_FUPD_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_FUPD_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_FUPD_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_FUPD_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_FUPD_CH5_MASK) #define GTM_gtm_cls1_TIO1_FUPD_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_FUPD_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_FUPD_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_FUPD_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_FUPD_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_FUPD_CH6_MASK) #define GTM_gtm_cls1_TIO1_FUPD_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_FUPD_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_FUPD_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_FUPD_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_FUPD_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_FUPD_CH7_MASK) /*! @} */ /*! @name TIO1_HW_CONF - TIO[i] configuration register */ /*! @{ */ #define GTM_gtm_cls1_TIO1_HW_CONF_NTIO_CH8_MASK (0x3U) #define GTM_gtm_cls1_TIO1_HW_CONF_NTIO_CH8_SHIFT (0U) #define GTM_gtm_cls1_TIO1_HW_CONF_NTIO_CH8_WIDTH (2U) #define GTM_gtm_cls1_TIO1_HW_CONF_NTIO_CH8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_HW_CONF_NTIO_CH8_SHIFT)) & GTM_gtm_cls1_TIO1_HW_CONF_NTIO_CH8_MASK) #define GTM_gtm_cls1_TIO1_HW_CONF_TIO_PLUS_MASK (0x10U) #define GTM_gtm_cls1_TIO1_HW_CONF_TIO_PLUS_SHIFT (4U) #define GTM_gtm_cls1_TIO1_HW_CONF_TIO_PLUS_WIDTH (1U) #define GTM_gtm_cls1_TIO1_HW_CONF_TIO_PLUS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_HW_CONF_TIO_PLUS_SHIFT)) & GTM_gtm_cls1_TIO1_HW_CONF_TIO_PLUS_MASK) /*! @} */ /*! @name TIO1_RSEL_CTRL1 - TIO[i] resource selection control register 1 */ /*! @{ */ #define GTM_gtm_cls1_TIO1_RSEL_CTRL1_SEL_CLKEN6_0_MASK (0x1000000U) #define GTM_gtm_cls1_TIO1_RSEL_CTRL1_SEL_CLKEN6_0_SHIFT (24U) #define GTM_gtm_cls1_TIO1_RSEL_CTRL1_SEL_CLKEN6_0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_RSEL_CTRL1_SEL_CLKEN6_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_RSEL_CTRL1_SEL_CLKEN6_0_SHIFT)) & GTM_gtm_cls1_TIO1_RSEL_CTRL1_SEL_CLKEN6_0_MASK) #define GTM_gtm_cls1_TIO1_RSEL_CTRL1_SEL_CLKEN7_0_MASK (0x10000000U) #define GTM_gtm_cls1_TIO1_RSEL_CTRL1_SEL_CLKEN7_0_SHIFT (28U) #define GTM_gtm_cls1_TIO1_RSEL_CTRL1_SEL_CLKEN7_0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_RSEL_CTRL1_SEL_CLKEN7_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_RSEL_CTRL1_SEL_CLKEN7_0_SHIFT)) & GTM_gtm_cls1_TIO1_RSEL_CTRL1_SEL_CLKEN7_0_MASK) /*! @} */ /*! @name TIO1_RSEL_CTRL2 - TIO[i] resource selection control register 2 */ /*! @{ */ #define GTM_gtm_cls1_TIO1_RSEL_CTRL2_SEL_TB1_0_MASK (0x10U) #define GTM_gtm_cls1_TIO1_RSEL_CTRL2_SEL_TB1_0_SHIFT (4U) #define GTM_gtm_cls1_TIO1_RSEL_CTRL2_SEL_TB1_0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_RSEL_CTRL2_SEL_TB1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_RSEL_CTRL2_SEL_TB1_0_SHIFT)) & GTM_gtm_cls1_TIO1_RSEL_CTRL2_SEL_TB1_0_MASK) #define GTM_gtm_cls1_TIO1_RSEL_CTRL2_SEL_TB2_0_MASK (0x100U) #define GTM_gtm_cls1_TIO1_RSEL_CTRL2_SEL_TB2_0_SHIFT (8U) #define GTM_gtm_cls1_TIO1_RSEL_CTRL2_SEL_TB2_0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_RSEL_CTRL2_SEL_TB2_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_RSEL_CTRL2_SEL_TB2_0_SHIFT)) & GTM_gtm_cls1_TIO1_RSEL_CTRL2_SEL_TB2_0_MASK) /*! @} */ /*! @name TIO1_PL_SWRST - TIO[i] software reset for TIO Plus functionality */ /*! @{ */ #define GTM_gtm_cls1_TIO1_PL_SWRST_CH0_MASK (0x1U) #define GTM_gtm_cls1_TIO1_PL_SWRST_CH0_SHIFT (0U) #define GTM_gtm_cls1_TIO1_PL_SWRST_CH0_WIDTH (1U) #define GTM_gtm_cls1_TIO1_PL_SWRST_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_PL_SWRST_CH0_SHIFT)) & GTM_gtm_cls1_TIO1_PL_SWRST_CH0_MASK) #define GTM_gtm_cls1_TIO1_PL_SWRST_CH1_MASK (0x2U) #define GTM_gtm_cls1_TIO1_PL_SWRST_CH1_SHIFT (1U) #define GTM_gtm_cls1_TIO1_PL_SWRST_CH1_WIDTH (1U) #define GTM_gtm_cls1_TIO1_PL_SWRST_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_PL_SWRST_CH1_SHIFT)) & GTM_gtm_cls1_TIO1_PL_SWRST_CH1_MASK) #define GTM_gtm_cls1_TIO1_PL_SWRST_CH2_MASK (0x4U) #define GTM_gtm_cls1_TIO1_PL_SWRST_CH2_SHIFT (2U) #define GTM_gtm_cls1_TIO1_PL_SWRST_CH2_WIDTH (1U) #define GTM_gtm_cls1_TIO1_PL_SWRST_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_PL_SWRST_CH2_SHIFT)) & GTM_gtm_cls1_TIO1_PL_SWRST_CH2_MASK) #define GTM_gtm_cls1_TIO1_PL_SWRST_CH3_MASK (0x8U) #define GTM_gtm_cls1_TIO1_PL_SWRST_CH3_SHIFT (3U) #define GTM_gtm_cls1_TIO1_PL_SWRST_CH3_WIDTH (1U) #define GTM_gtm_cls1_TIO1_PL_SWRST_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_PL_SWRST_CH3_SHIFT)) & GTM_gtm_cls1_TIO1_PL_SWRST_CH3_MASK) #define GTM_gtm_cls1_TIO1_PL_SWRST_CH4_MASK (0x10U) #define GTM_gtm_cls1_TIO1_PL_SWRST_CH4_SHIFT (4U) #define GTM_gtm_cls1_TIO1_PL_SWRST_CH4_WIDTH (1U) #define GTM_gtm_cls1_TIO1_PL_SWRST_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_PL_SWRST_CH4_SHIFT)) & GTM_gtm_cls1_TIO1_PL_SWRST_CH4_MASK) #define GTM_gtm_cls1_TIO1_PL_SWRST_CH5_MASK (0x20U) #define GTM_gtm_cls1_TIO1_PL_SWRST_CH5_SHIFT (5U) #define GTM_gtm_cls1_TIO1_PL_SWRST_CH5_WIDTH (1U) #define GTM_gtm_cls1_TIO1_PL_SWRST_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_PL_SWRST_CH5_SHIFT)) & GTM_gtm_cls1_TIO1_PL_SWRST_CH5_MASK) #define GTM_gtm_cls1_TIO1_PL_SWRST_CH6_MASK (0x40U) #define GTM_gtm_cls1_TIO1_PL_SWRST_CH6_SHIFT (6U) #define GTM_gtm_cls1_TIO1_PL_SWRST_CH6_WIDTH (1U) #define GTM_gtm_cls1_TIO1_PL_SWRST_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_PL_SWRST_CH6_SHIFT)) & GTM_gtm_cls1_TIO1_PL_SWRST_CH6_MASK) #define GTM_gtm_cls1_TIO1_PL_SWRST_CH7_MASK (0x80U) #define GTM_gtm_cls1_TIO1_PL_SWRST_CH7_SHIFT (7U) #define GTM_gtm_cls1_TIO1_PL_SWRST_CH7_WIDTH (1U) #define GTM_gtm_cls1_TIO1_PL_SWRST_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_TIO1_PL_SWRST_CH7_SHIFT)) & GTM_gtm_cls1_TIO1_PL_SWRST_CH7_MASK) /*! @} */ /*! @name CCM1_ARP0_CTRL - CCM[i] Address Range Protector [a] Control Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_ARP0_CTRL_ADDR_MASK (0xFFFFU) #define GTM_gtm_cls1_CCM1_ARP0_CTRL_ADDR_SHIFT (0U) #define GTM_gtm_cls1_CCM1_ARP0_CTRL_ADDR_WIDTH (16U) #define GTM_gtm_cls1_CCM1_ARP0_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP0_CTRL_ADDR_SHIFT)) & GTM_gtm_cls1_CCM1_ARP0_CTRL_ADDR_MASK) #define GTM_gtm_cls1_CCM1_ARP0_CTRL_SIZE_MASK (0xF0000U) #define GTM_gtm_cls1_CCM1_ARP0_CTRL_SIZE_SHIFT (16U) #define GTM_gtm_cls1_CCM1_ARP0_CTRL_SIZE_WIDTH (4U) #define GTM_gtm_cls1_CCM1_ARP0_CTRL_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP0_CTRL_SIZE_SHIFT)) & GTM_gtm_cls1_CCM1_ARP0_CTRL_SIZE_MASK) #define GTM_gtm_cls1_CCM1_ARP0_CTRL_DIS_PROT_MASK (0x1000000U) #define GTM_gtm_cls1_CCM1_ARP0_CTRL_DIS_PROT_SHIFT (24U) #define GTM_gtm_cls1_CCM1_ARP0_CTRL_DIS_PROT_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP0_CTRL_DIS_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP0_CTRL_DIS_PROT_SHIFT)) & GTM_gtm_cls1_CCM1_ARP0_CTRL_DIS_PROT_MASK) #define GTM_gtm_cls1_CCM1_ARP0_CTRL_WPROT_AEI_MASK (0x80000000U) #define GTM_gtm_cls1_CCM1_ARP0_CTRL_WPROT_AEI_SHIFT (31U) #define GTM_gtm_cls1_CCM1_ARP0_CTRL_WPROT_AEI_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP0_CTRL_WPROT_AEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP0_CTRL_WPROT_AEI_SHIFT)) & GTM_gtm_cls1_CCM1_ARP0_CTRL_WPROT_AEI_MASK) /*! @} */ /*! @name CCM1_ARP0_PROT - CCM[i] Address Range Protector [a] Protection Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT0_MASK (0x1U) #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT0_SHIFT (0U) #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT0_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT0_SHIFT)) & GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT0_MASK) #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT1_MASK (0x2U) #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT1_SHIFT (1U) #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT1_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT1_SHIFT)) & GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT1_MASK) #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT2_MASK (0x4U) #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT2_SHIFT (2U) #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT2_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT2_SHIFT)) & GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT2_MASK) #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT3_MASK (0x8U) #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT3_SHIFT (3U) #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT3_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT3_SHIFT)) & GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT3_MASK) #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT4_MASK (0x10U) #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT4_SHIFT (4U) #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT4_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT4_SHIFT)) & GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT4_MASK) #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT5_MASK (0x20U) #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT5_SHIFT (5U) #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT5_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT5_SHIFT)) & GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT5_MASK) #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT6_MASK (0x40U) #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT6_SHIFT (6U) #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT6_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT6_SHIFT)) & GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT6_MASK) #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT7_MASK (0x80U) #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT7_SHIFT (7U) #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT7_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT7_SHIFT)) & GTM_gtm_cls1_CCM1_ARP0_PROT_WPROT7_MASK) /*! @} */ /*! @name CCM1_ARP1_CTRL - CCM[i] Address Range Protector [a] Control Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_ARP1_CTRL_ADDR_MASK (0xFFFFU) #define GTM_gtm_cls1_CCM1_ARP1_CTRL_ADDR_SHIFT (0U) #define GTM_gtm_cls1_CCM1_ARP1_CTRL_ADDR_WIDTH (16U) #define GTM_gtm_cls1_CCM1_ARP1_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP1_CTRL_ADDR_SHIFT)) & GTM_gtm_cls1_CCM1_ARP1_CTRL_ADDR_MASK) #define GTM_gtm_cls1_CCM1_ARP1_CTRL_SIZE_MASK (0xF0000U) #define GTM_gtm_cls1_CCM1_ARP1_CTRL_SIZE_SHIFT (16U) #define GTM_gtm_cls1_CCM1_ARP1_CTRL_SIZE_WIDTH (4U) #define GTM_gtm_cls1_CCM1_ARP1_CTRL_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP1_CTRL_SIZE_SHIFT)) & GTM_gtm_cls1_CCM1_ARP1_CTRL_SIZE_MASK) #define GTM_gtm_cls1_CCM1_ARP1_CTRL_DIS_PROT_MASK (0x1000000U) #define GTM_gtm_cls1_CCM1_ARP1_CTRL_DIS_PROT_SHIFT (24U) #define GTM_gtm_cls1_CCM1_ARP1_CTRL_DIS_PROT_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP1_CTRL_DIS_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP1_CTRL_DIS_PROT_SHIFT)) & GTM_gtm_cls1_CCM1_ARP1_CTRL_DIS_PROT_MASK) #define GTM_gtm_cls1_CCM1_ARP1_CTRL_WPROT_AEI_MASK (0x80000000U) #define GTM_gtm_cls1_CCM1_ARP1_CTRL_WPROT_AEI_SHIFT (31U) #define GTM_gtm_cls1_CCM1_ARP1_CTRL_WPROT_AEI_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP1_CTRL_WPROT_AEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP1_CTRL_WPROT_AEI_SHIFT)) & GTM_gtm_cls1_CCM1_ARP1_CTRL_WPROT_AEI_MASK) /*! @} */ /*! @name CCM1_ARP1_PROT - CCM[i] Address Range Protector [a] Protection Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT0_MASK (0x1U) #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT0_SHIFT (0U) #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT0_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT0_SHIFT)) & GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT0_MASK) #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT1_MASK (0x2U) #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT1_SHIFT (1U) #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT1_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT1_SHIFT)) & GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT1_MASK) #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT2_MASK (0x4U) #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT2_SHIFT (2U) #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT2_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT2_SHIFT)) & GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT2_MASK) #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT3_MASK (0x8U) #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT3_SHIFT (3U) #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT3_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT3_SHIFT)) & GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT3_MASK) #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT4_MASK (0x10U) #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT4_SHIFT (4U) #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT4_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT4_SHIFT)) & GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT4_MASK) #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT5_MASK (0x20U) #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT5_SHIFT (5U) #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT5_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT5_SHIFT)) & GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT5_MASK) #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT6_MASK (0x40U) #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT6_SHIFT (6U) #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT6_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT6_SHIFT)) & GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT6_MASK) #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT7_MASK (0x80U) #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT7_SHIFT (7U) #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT7_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT7_SHIFT)) & GTM_gtm_cls1_CCM1_ARP1_PROT_WPROT7_MASK) /*! @} */ /*! @name CCM1_ARP2_CTRL - CCM[i] Address Range Protector [a] Control Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_ARP2_CTRL_ADDR_MASK (0xFFFFU) #define GTM_gtm_cls1_CCM1_ARP2_CTRL_ADDR_SHIFT (0U) #define GTM_gtm_cls1_CCM1_ARP2_CTRL_ADDR_WIDTH (16U) #define GTM_gtm_cls1_CCM1_ARP2_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP2_CTRL_ADDR_SHIFT)) & GTM_gtm_cls1_CCM1_ARP2_CTRL_ADDR_MASK) #define GTM_gtm_cls1_CCM1_ARP2_CTRL_SIZE_MASK (0xF0000U) #define GTM_gtm_cls1_CCM1_ARP2_CTRL_SIZE_SHIFT (16U) #define GTM_gtm_cls1_CCM1_ARP2_CTRL_SIZE_WIDTH (4U) #define GTM_gtm_cls1_CCM1_ARP2_CTRL_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP2_CTRL_SIZE_SHIFT)) & GTM_gtm_cls1_CCM1_ARP2_CTRL_SIZE_MASK) #define GTM_gtm_cls1_CCM1_ARP2_CTRL_DIS_PROT_MASK (0x1000000U) #define GTM_gtm_cls1_CCM1_ARP2_CTRL_DIS_PROT_SHIFT (24U) #define GTM_gtm_cls1_CCM1_ARP2_CTRL_DIS_PROT_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP2_CTRL_DIS_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP2_CTRL_DIS_PROT_SHIFT)) & GTM_gtm_cls1_CCM1_ARP2_CTRL_DIS_PROT_MASK) #define GTM_gtm_cls1_CCM1_ARP2_CTRL_WPROT_AEI_MASK (0x80000000U) #define GTM_gtm_cls1_CCM1_ARP2_CTRL_WPROT_AEI_SHIFT (31U) #define GTM_gtm_cls1_CCM1_ARP2_CTRL_WPROT_AEI_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP2_CTRL_WPROT_AEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP2_CTRL_WPROT_AEI_SHIFT)) & GTM_gtm_cls1_CCM1_ARP2_CTRL_WPROT_AEI_MASK) /*! @} */ /*! @name CCM1_ARP2_PROT - CCM[i] Address Range Protector [a] Protection Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT0_MASK (0x1U) #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT0_SHIFT (0U) #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT0_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT0_SHIFT)) & GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT0_MASK) #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT1_MASK (0x2U) #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT1_SHIFT (1U) #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT1_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT1_SHIFT)) & GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT1_MASK) #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT2_MASK (0x4U) #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT2_SHIFT (2U) #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT2_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT2_SHIFT)) & GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT2_MASK) #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT3_MASK (0x8U) #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT3_SHIFT (3U) #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT3_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT3_SHIFT)) & GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT3_MASK) #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT4_MASK (0x10U) #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT4_SHIFT (4U) #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT4_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT4_SHIFT)) & GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT4_MASK) #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT5_MASK (0x20U) #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT5_SHIFT (5U) #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT5_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT5_SHIFT)) & GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT5_MASK) #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT6_MASK (0x40U) #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT6_SHIFT (6U) #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT6_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT6_SHIFT)) & GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT6_MASK) #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT7_MASK (0x80U) #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT7_SHIFT (7U) #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT7_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT7_SHIFT)) & GTM_gtm_cls1_CCM1_ARP2_PROT_WPROT7_MASK) /*! @} */ /*! @name CCM1_ARP3_CTRL - CCM[i] Address Range Protector [a] Control Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_ARP3_CTRL_ADDR_MASK (0xFFFFU) #define GTM_gtm_cls1_CCM1_ARP3_CTRL_ADDR_SHIFT (0U) #define GTM_gtm_cls1_CCM1_ARP3_CTRL_ADDR_WIDTH (16U) #define GTM_gtm_cls1_CCM1_ARP3_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP3_CTRL_ADDR_SHIFT)) & GTM_gtm_cls1_CCM1_ARP3_CTRL_ADDR_MASK) #define GTM_gtm_cls1_CCM1_ARP3_CTRL_SIZE_MASK (0xF0000U) #define GTM_gtm_cls1_CCM1_ARP3_CTRL_SIZE_SHIFT (16U) #define GTM_gtm_cls1_CCM1_ARP3_CTRL_SIZE_WIDTH (4U) #define GTM_gtm_cls1_CCM1_ARP3_CTRL_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP3_CTRL_SIZE_SHIFT)) & GTM_gtm_cls1_CCM1_ARP3_CTRL_SIZE_MASK) #define GTM_gtm_cls1_CCM1_ARP3_CTRL_DIS_PROT_MASK (0x1000000U) #define GTM_gtm_cls1_CCM1_ARP3_CTRL_DIS_PROT_SHIFT (24U) #define GTM_gtm_cls1_CCM1_ARP3_CTRL_DIS_PROT_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP3_CTRL_DIS_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP3_CTRL_DIS_PROT_SHIFT)) & GTM_gtm_cls1_CCM1_ARP3_CTRL_DIS_PROT_MASK) #define GTM_gtm_cls1_CCM1_ARP3_CTRL_WPROT_AEI_MASK (0x80000000U) #define GTM_gtm_cls1_CCM1_ARP3_CTRL_WPROT_AEI_SHIFT (31U) #define GTM_gtm_cls1_CCM1_ARP3_CTRL_WPROT_AEI_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP3_CTRL_WPROT_AEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP3_CTRL_WPROT_AEI_SHIFT)) & GTM_gtm_cls1_CCM1_ARP3_CTRL_WPROT_AEI_MASK) /*! @} */ /*! @name CCM1_ARP3_PROT - CCM[i] Address Range Protector [a] Protection Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT0_MASK (0x1U) #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT0_SHIFT (0U) #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT0_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT0_SHIFT)) & GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT0_MASK) #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT1_MASK (0x2U) #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT1_SHIFT (1U) #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT1_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT1_SHIFT)) & GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT1_MASK) #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT2_MASK (0x4U) #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT2_SHIFT (2U) #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT2_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT2_SHIFT)) & GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT2_MASK) #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT3_MASK (0x8U) #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT3_SHIFT (3U) #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT3_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT3_SHIFT)) & GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT3_MASK) #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT4_MASK (0x10U) #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT4_SHIFT (4U) #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT4_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT4_SHIFT)) & GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT4_MASK) #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT5_MASK (0x20U) #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT5_SHIFT (5U) #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT5_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT5_SHIFT)) & GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT5_MASK) #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT6_MASK (0x40U) #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT6_SHIFT (6U) #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT6_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT6_SHIFT)) & GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT6_MASK) #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT7_MASK (0x80U) #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT7_SHIFT (7U) #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT7_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT7_SHIFT)) & GTM_gtm_cls1_CCM1_ARP3_PROT_WPROT7_MASK) /*! @} */ /*! @name CCM1_ARP4_CTRL - CCM[i] Address Range Protector [a] Control Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_ARP4_CTRL_ADDR_MASK (0xFFFFU) #define GTM_gtm_cls1_CCM1_ARP4_CTRL_ADDR_SHIFT (0U) #define GTM_gtm_cls1_CCM1_ARP4_CTRL_ADDR_WIDTH (16U) #define GTM_gtm_cls1_CCM1_ARP4_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP4_CTRL_ADDR_SHIFT)) & GTM_gtm_cls1_CCM1_ARP4_CTRL_ADDR_MASK) #define GTM_gtm_cls1_CCM1_ARP4_CTRL_SIZE_MASK (0xF0000U) #define GTM_gtm_cls1_CCM1_ARP4_CTRL_SIZE_SHIFT (16U) #define GTM_gtm_cls1_CCM1_ARP4_CTRL_SIZE_WIDTH (4U) #define GTM_gtm_cls1_CCM1_ARP4_CTRL_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP4_CTRL_SIZE_SHIFT)) & GTM_gtm_cls1_CCM1_ARP4_CTRL_SIZE_MASK) #define GTM_gtm_cls1_CCM1_ARP4_CTRL_DIS_PROT_MASK (0x1000000U) #define GTM_gtm_cls1_CCM1_ARP4_CTRL_DIS_PROT_SHIFT (24U) #define GTM_gtm_cls1_CCM1_ARP4_CTRL_DIS_PROT_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP4_CTRL_DIS_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP4_CTRL_DIS_PROT_SHIFT)) & GTM_gtm_cls1_CCM1_ARP4_CTRL_DIS_PROT_MASK) #define GTM_gtm_cls1_CCM1_ARP4_CTRL_WPROT_AEI_MASK (0x80000000U) #define GTM_gtm_cls1_CCM1_ARP4_CTRL_WPROT_AEI_SHIFT (31U) #define GTM_gtm_cls1_CCM1_ARP4_CTRL_WPROT_AEI_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP4_CTRL_WPROT_AEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP4_CTRL_WPROT_AEI_SHIFT)) & GTM_gtm_cls1_CCM1_ARP4_CTRL_WPROT_AEI_MASK) /*! @} */ /*! @name CCM1_ARP4_PROT - CCM[i] Address Range Protector [a] Protection Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT0_MASK (0x1U) #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT0_SHIFT (0U) #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT0_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT0_SHIFT)) & GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT0_MASK) #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT1_MASK (0x2U) #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT1_SHIFT (1U) #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT1_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT1_SHIFT)) & GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT1_MASK) #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT2_MASK (0x4U) #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT2_SHIFT (2U) #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT2_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT2_SHIFT)) & GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT2_MASK) #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT3_MASK (0x8U) #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT3_SHIFT (3U) #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT3_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT3_SHIFT)) & GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT3_MASK) #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT4_MASK (0x10U) #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT4_SHIFT (4U) #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT4_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT4_SHIFT)) & GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT4_MASK) #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT5_MASK (0x20U) #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT5_SHIFT (5U) #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT5_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT5_SHIFT)) & GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT5_MASK) #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT6_MASK (0x40U) #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT6_SHIFT (6U) #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT6_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT6_SHIFT)) & GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT6_MASK) #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT7_MASK (0x80U) #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT7_SHIFT (7U) #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT7_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT7_SHIFT)) & GTM_gtm_cls1_CCM1_ARP4_PROT_WPROT7_MASK) /*! @} */ /*! @name CCM1_ARP5_CTRL - CCM[i] Address Range Protector [a] Control Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_ARP5_CTRL_ADDR_MASK (0xFFFFU) #define GTM_gtm_cls1_CCM1_ARP5_CTRL_ADDR_SHIFT (0U) #define GTM_gtm_cls1_CCM1_ARP5_CTRL_ADDR_WIDTH (16U) #define GTM_gtm_cls1_CCM1_ARP5_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP5_CTRL_ADDR_SHIFT)) & GTM_gtm_cls1_CCM1_ARP5_CTRL_ADDR_MASK) #define GTM_gtm_cls1_CCM1_ARP5_CTRL_SIZE_MASK (0xF0000U) #define GTM_gtm_cls1_CCM1_ARP5_CTRL_SIZE_SHIFT (16U) #define GTM_gtm_cls1_CCM1_ARP5_CTRL_SIZE_WIDTH (4U) #define GTM_gtm_cls1_CCM1_ARP5_CTRL_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP5_CTRL_SIZE_SHIFT)) & GTM_gtm_cls1_CCM1_ARP5_CTRL_SIZE_MASK) #define GTM_gtm_cls1_CCM1_ARP5_CTRL_DIS_PROT_MASK (0x1000000U) #define GTM_gtm_cls1_CCM1_ARP5_CTRL_DIS_PROT_SHIFT (24U) #define GTM_gtm_cls1_CCM1_ARP5_CTRL_DIS_PROT_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP5_CTRL_DIS_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP5_CTRL_DIS_PROT_SHIFT)) & GTM_gtm_cls1_CCM1_ARP5_CTRL_DIS_PROT_MASK) #define GTM_gtm_cls1_CCM1_ARP5_CTRL_WPROT_AEI_MASK (0x80000000U) #define GTM_gtm_cls1_CCM1_ARP5_CTRL_WPROT_AEI_SHIFT (31U) #define GTM_gtm_cls1_CCM1_ARP5_CTRL_WPROT_AEI_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP5_CTRL_WPROT_AEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP5_CTRL_WPROT_AEI_SHIFT)) & GTM_gtm_cls1_CCM1_ARP5_CTRL_WPROT_AEI_MASK) /*! @} */ /*! @name CCM1_ARP5_PROT - CCM[i] Address Range Protector [a] Protection Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT0_MASK (0x1U) #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT0_SHIFT (0U) #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT0_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT0_SHIFT)) & GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT0_MASK) #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT1_MASK (0x2U) #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT1_SHIFT (1U) #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT1_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT1_SHIFT)) & GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT1_MASK) #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT2_MASK (0x4U) #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT2_SHIFT (2U) #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT2_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT2_SHIFT)) & GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT2_MASK) #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT3_MASK (0x8U) #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT3_SHIFT (3U) #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT3_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT3_SHIFT)) & GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT3_MASK) #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT4_MASK (0x10U) #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT4_SHIFT (4U) #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT4_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT4_SHIFT)) & GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT4_MASK) #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT5_MASK (0x20U) #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT5_SHIFT (5U) #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT5_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT5_SHIFT)) & GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT5_MASK) #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT6_MASK (0x40U) #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT6_SHIFT (6U) #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT6_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT6_SHIFT)) & GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT6_MASK) #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT7_MASK (0x80U) #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT7_SHIFT (7U) #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT7_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT7_SHIFT)) & GTM_gtm_cls1_CCM1_ARP5_PROT_WPROT7_MASK) /*! @} */ /*! @name CCM1_ARP6_CTRL - CCM[i] Address Range Protector [a] Control Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_ARP6_CTRL_ADDR_MASK (0xFFFFU) #define GTM_gtm_cls1_CCM1_ARP6_CTRL_ADDR_SHIFT (0U) #define GTM_gtm_cls1_CCM1_ARP6_CTRL_ADDR_WIDTH (16U) #define GTM_gtm_cls1_CCM1_ARP6_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP6_CTRL_ADDR_SHIFT)) & GTM_gtm_cls1_CCM1_ARP6_CTRL_ADDR_MASK) #define GTM_gtm_cls1_CCM1_ARP6_CTRL_SIZE_MASK (0xF0000U) #define GTM_gtm_cls1_CCM1_ARP6_CTRL_SIZE_SHIFT (16U) #define GTM_gtm_cls1_CCM1_ARP6_CTRL_SIZE_WIDTH (4U) #define GTM_gtm_cls1_CCM1_ARP6_CTRL_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP6_CTRL_SIZE_SHIFT)) & GTM_gtm_cls1_CCM1_ARP6_CTRL_SIZE_MASK) #define GTM_gtm_cls1_CCM1_ARP6_CTRL_DIS_PROT_MASK (0x1000000U) #define GTM_gtm_cls1_CCM1_ARP6_CTRL_DIS_PROT_SHIFT (24U) #define GTM_gtm_cls1_CCM1_ARP6_CTRL_DIS_PROT_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP6_CTRL_DIS_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP6_CTRL_DIS_PROT_SHIFT)) & GTM_gtm_cls1_CCM1_ARP6_CTRL_DIS_PROT_MASK) #define GTM_gtm_cls1_CCM1_ARP6_CTRL_WPROT_AEI_MASK (0x80000000U) #define GTM_gtm_cls1_CCM1_ARP6_CTRL_WPROT_AEI_SHIFT (31U) #define GTM_gtm_cls1_CCM1_ARP6_CTRL_WPROT_AEI_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP6_CTRL_WPROT_AEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP6_CTRL_WPROT_AEI_SHIFT)) & GTM_gtm_cls1_CCM1_ARP6_CTRL_WPROT_AEI_MASK) /*! @} */ /*! @name CCM1_ARP6_PROT - CCM[i] Address Range Protector [a] Protection Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT0_MASK (0x1U) #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT0_SHIFT (0U) #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT0_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT0_SHIFT)) & GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT0_MASK) #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT1_MASK (0x2U) #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT1_SHIFT (1U) #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT1_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT1_SHIFT)) & GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT1_MASK) #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT2_MASK (0x4U) #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT2_SHIFT (2U) #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT2_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT2_SHIFT)) & GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT2_MASK) #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT3_MASK (0x8U) #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT3_SHIFT (3U) #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT3_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT3_SHIFT)) & GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT3_MASK) #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT4_MASK (0x10U) #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT4_SHIFT (4U) #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT4_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT4_SHIFT)) & GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT4_MASK) #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT5_MASK (0x20U) #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT5_SHIFT (5U) #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT5_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT5_SHIFT)) & GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT5_MASK) #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT6_MASK (0x40U) #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT6_SHIFT (6U) #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT6_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT6_SHIFT)) & GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT6_MASK) #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT7_MASK (0x80U) #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT7_SHIFT (7U) #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT7_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT7_SHIFT)) & GTM_gtm_cls1_CCM1_ARP6_PROT_WPROT7_MASK) /*! @} */ /*! @name CCM1_ARP7_CTRL - CCM[i] Address Range Protector [a] Control Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_ARP7_CTRL_ADDR_MASK (0xFFFFU) #define GTM_gtm_cls1_CCM1_ARP7_CTRL_ADDR_SHIFT (0U) #define GTM_gtm_cls1_CCM1_ARP7_CTRL_ADDR_WIDTH (16U) #define GTM_gtm_cls1_CCM1_ARP7_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP7_CTRL_ADDR_SHIFT)) & GTM_gtm_cls1_CCM1_ARP7_CTRL_ADDR_MASK) #define GTM_gtm_cls1_CCM1_ARP7_CTRL_SIZE_MASK (0xF0000U) #define GTM_gtm_cls1_CCM1_ARP7_CTRL_SIZE_SHIFT (16U) #define GTM_gtm_cls1_CCM1_ARP7_CTRL_SIZE_WIDTH (4U) #define GTM_gtm_cls1_CCM1_ARP7_CTRL_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP7_CTRL_SIZE_SHIFT)) & GTM_gtm_cls1_CCM1_ARP7_CTRL_SIZE_MASK) #define GTM_gtm_cls1_CCM1_ARP7_CTRL_DIS_PROT_MASK (0x1000000U) #define GTM_gtm_cls1_CCM1_ARP7_CTRL_DIS_PROT_SHIFT (24U) #define GTM_gtm_cls1_CCM1_ARP7_CTRL_DIS_PROT_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP7_CTRL_DIS_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP7_CTRL_DIS_PROT_SHIFT)) & GTM_gtm_cls1_CCM1_ARP7_CTRL_DIS_PROT_MASK) #define GTM_gtm_cls1_CCM1_ARP7_CTRL_WPROT_AEI_MASK (0x80000000U) #define GTM_gtm_cls1_CCM1_ARP7_CTRL_WPROT_AEI_SHIFT (31U) #define GTM_gtm_cls1_CCM1_ARP7_CTRL_WPROT_AEI_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP7_CTRL_WPROT_AEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP7_CTRL_WPROT_AEI_SHIFT)) & GTM_gtm_cls1_CCM1_ARP7_CTRL_WPROT_AEI_MASK) /*! @} */ /*! @name CCM1_ARP7_PROT - CCM[i] Address Range Protector [a] Protection Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT0_MASK (0x1U) #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT0_SHIFT (0U) #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT0_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT0_SHIFT)) & GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT0_MASK) #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT1_MASK (0x2U) #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT1_SHIFT (1U) #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT1_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT1_SHIFT)) & GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT1_MASK) #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT2_MASK (0x4U) #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT2_SHIFT (2U) #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT2_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT2_SHIFT)) & GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT2_MASK) #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT3_MASK (0x8U) #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT3_SHIFT (3U) #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT3_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT3_SHIFT)) & GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT3_MASK) #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT4_MASK (0x10U) #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT4_SHIFT (4U) #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT4_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT4_SHIFT)) & GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT4_MASK) #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT5_MASK (0x20U) #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT5_SHIFT (5U) #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT5_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT5_SHIFT)) & GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT5_MASK) #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT6_MASK (0x40U) #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT6_SHIFT (6U) #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT6_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT6_SHIFT)) & GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT6_MASK) #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT7_MASK (0x80U) #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT7_SHIFT (7U) #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT7_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT7_SHIFT)) & GTM_gtm_cls1_CCM1_ARP7_PROT_WPROT7_MASK) /*! @} */ /*! @name CCM1_ARP8_CTRL - CCM[i] Address Range Protector [a] Control Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_ARP8_CTRL_ADDR_MASK (0xFFFFU) #define GTM_gtm_cls1_CCM1_ARP8_CTRL_ADDR_SHIFT (0U) #define GTM_gtm_cls1_CCM1_ARP8_CTRL_ADDR_WIDTH (16U) #define GTM_gtm_cls1_CCM1_ARP8_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP8_CTRL_ADDR_SHIFT)) & GTM_gtm_cls1_CCM1_ARP8_CTRL_ADDR_MASK) #define GTM_gtm_cls1_CCM1_ARP8_CTRL_SIZE_MASK (0xF0000U) #define GTM_gtm_cls1_CCM1_ARP8_CTRL_SIZE_SHIFT (16U) #define GTM_gtm_cls1_CCM1_ARP8_CTRL_SIZE_WIDTH (4U) #define GTM_gtm_cls1_CCM1_ARP8_CTRL_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP8_CTRL_SIZE_SHIFT)) & GTM_gtm_cls1_CCM1_ARP8_CTRL_SIZE_MASK) #define GTM_gtm_cls1_CCM1_ARP8_CTRL_DIS_PROT_MASK (0x1000000U) #define GTM_gtm_cls1_CCM1_ARP8_CTRL_DIS_PROT_SHIFT (24U) #define GTM_gtm_cls1_CCM1_ARP8_CTRL_DIS_PROT_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP8_CTRL_DIS_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP8_CTRL_DIS_PROT_SHIFT)) & GTM_gtm_cls1_CCM1_ARP8_CTRL_DIS_PROT_MASK) #define GTM_gtm_cls1_CCM1_ARP8_CTRL_WPROT_AEI_MASK (0x80000000U) #define GTM_gtm_cls1_CCM1_ARP8_CTRL_WPROT_AEI_SHIFT (31U) #define GTM_gtm_cls1_CCM1_ARP8_CTRL_WPROT_AEI_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP8_CTRL_WPROT_AEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP8_CTRL_WPROT_AEI_SHIFT)) & GTM_gtm_cls1_CCM1_ARP8_CTRL_WPROT_AEI_MASK) /*! @} */ /*! @name CCM1_ARP8_PROT - CCM[i] Address Range Protector [a] Protection Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT0_MASK (0x1U) #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT0_SHIFT (0U) #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT0_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT0_SHIFT)) & GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT0_MASK) #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT1_MASK (0x2U) #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT1_SHIFT (1U) #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT1_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT1_SHIFT)) & GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT1_MASK) #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT2_MASK (0x4U) #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT2_SHIFT (2U) #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT2_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT2_SHIFT)) & GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT2_MASK) #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT3_MASK (0x8U) #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT3_SHIFT (3U) #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT3_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT3_SHIFT)) & GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT3_MASK) #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT4_MASK (0x10U) #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT4_SHIFT (4U) #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT4_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT4_SHIFT)) & GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT4_MASK) #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT5_MASK (0x20U) #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT5_SHIFT (5U) #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT5_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT5_SHIFT)) & GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT5_MASK) #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT6_MASK (0x40U) #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT6_SHIFT (6U) #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT6_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT6_SHIFT)) & GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT6_MASK) #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT7_MASK (0x80U) #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT7_SHIFT (7U) #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT7_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT7_SHIFT)) & GTM_gtm_cls1_CCM1_ARP8_PROT_WPROT7_MASK) /*! @} */ /*! @name CCM1_ARP9_CTRL - CCM[i] Address Range Protector [a] Control Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_ARP9_CTRL_ADDR_MASK (0xFFFFU) #define GTM_gtm_cls1_CCM1_ARP9_CTRL_ADDR_SHIFT (0U) #define GTM_gtm_cls1_CCM1_ARP9_CTRL_ADDR_WIDTH (16U) #define GTM_gtm_cls1_CCM1_ARP9_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP9_CTRL_ADDR_SHIFT)) & GTM_gtm_cls1_CCM1_ARP9_CTRL_ADDR_MASK) #define GTM_gtm_cls1_CCM1_ARP9_CTRL_SIZE_MASK (0xF0000U) #define GTM_gtm_cls1_CCM1_ARP9_CTRL_SIZE_SHIFT (16U) #define GTM_gtm_cls1_CCM1_ARP9_CTRL_SIZE_WIDTH (4U) #define GTM_gtm_cls1_CCM1_ARP9_CTRL_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP9_CTRL_SIZE_SHIFT)) & GTM_gtm_cls1_CCM1_ARP9_CTRL_SIZE_MASK) #define GTM_gtm_cls1_CCM1_ARP9_CTRL_DIS_PROT_MASK (0x1000000U) #define GTM_gtm_cls1_CCM1_ARP9_CTRL_DIS_PROT_SHIFT (24U) #define GTM_gtm_cls1_CCM1_ARP9_CTRL_DIS_PROT_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP9_CTRL_DIS_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP9_CTRL_DIS_PROT_SHIFT)) & GTM_gtm_cls1_CCM1_ARP9_CTRL_DIS_PROT_MASK) #define GTM_gtm_cls1_CCM1_ARP9_CTRL_WPROT_AEI_MASK (0x80000000U) #define GTM_gtm_cls1_CCM1_ARP9_CTRL_WPROT_AEI_SHIFT (31U) #define GTM_gtm_cls1_CCM1_ARP9_CTRL_WPROT_AEI_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP9_CTRL_WPROT_AEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP9_CTRL_WPROT_AEI_SHIFT)) & GTM_gtm_cls1_CCM1_ARP9_CTRL_WPROT_AEI_MASK) /*! @} */ /*! @name CCM1_ARP9_PROT - CCM[i] Address Range Protector [a] Protection Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT0_MASK (0x1U) #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT0_SHIFT (0U) #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT0_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT0_SHIFT)) & GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT0_MASK) #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT1_MASK (0x2U) #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT1_SHIFT (1U) #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT1_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT1_SHIFT)) & GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT1_MASK) #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT2_MASK (0x4U) #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT2_SHIFT (2U) #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT2_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT2_SHIFT)) & GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT2_MASK) #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT3_MASK (0x8U) #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT3_SHIFT (3U) #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT3_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT3_SHIFT)) & GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT3_MASK) #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT4_MASK (0x10U) #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT4_SHIFT (4U) #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT4_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT4_SHIFT)) & GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT4_MASK) #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT5_MASK (0x20U) #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT5_SHIFT (5U) #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT5_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT5_SHIFT)) & GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT5_MASK) #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT6_MASK (0x40U) #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT6_SHIFT (6U) #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT6_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT6_SHIFT)) & GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT6_MASK) #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT7_MASK (0x80U) #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT7_SHIFT (7U) #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT7_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT7_SHIFT)) & GTM_gtm_cls1_CCM1_ARP9_PROT_WPROT7_MASK) /*! @} */ /*! @name CCM1_TIO_G0_OUT - CCM[i] TIO Group 0,1 Output Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT0_MASK (0x1U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT0_SHIFT (0U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT0_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT0_SHIFT)) & GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT0_MASK) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT1_MASK (0x2U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT1_SHIFT (1U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT1_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT1_SHIFT)) & GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT1_MASK) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT2_MASK (0x4U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT2_SHIFT (2U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT2_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT2_SHIFT)) & GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT2_MASK) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT3_MASK (0x8U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT3_SHIFT (3U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT3_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT3_SHIFT)) & GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT3_MASK) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT4_MASK (0x10U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT4_SHIFT (4U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT4_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT4_SHIFT)) & GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT4_MASK) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT5_MASK (0x20U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT5_SHIFT (5U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT5_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT5_SHIFT)) & GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT5_MASK) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT6_MASK (0x40U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT6_SHIFT (6U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT6_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT6_SHIFT)) & GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT6_MASK) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT7_MASK (0x80U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT7_SHIFT (7U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT7_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT7_SHIFT)) & GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT7_MASK) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N0_MASK (0x10000U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N0_SHIFT (16U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N0_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N0_SHIFT)) & GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N0_MASK) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N1_MASK (0x20000U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N1_SHIFT (17U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N1_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N1_SHIFT)) & GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N1_MASK) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N2_MASK (0x40000U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N2_SHIFT (18U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N2_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N2_SHIFT)) & GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N2_MASK) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N3_MASK (0x80000U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N3_SHIFT (19U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N3_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N3_SHIFT)) & GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N3_MASK) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N4_MASK (0x100000U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N4_SHIFT (20U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N4_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N4_SHIFT)) & GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N4_MASK) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N5_MASK (0x200000U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N5_SHIFT (21U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N5_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N5_SHIFT)) & GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N5_MASK) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N6_MASK (0x400000U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N6_SHIFT (22U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N6_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N6_SHIFT)) & GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N6_MASK) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N7_MASK (0x800000U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N7_SHIFT (23U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N7_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N7_SHIFT)) & GTM_gtm_cls1_CCM1_TIO_G0_OUT_TIO_G0_OUT_N7_MASK) /*! @} */ /*! @name CCM1_HW_CONF2 - CCM[i] 2. Hardware Configuration Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_HW_CONF2_AXIM_ID_WIDTH_MASK (0x1FU) #define GTM_gtm_cls1_CCM1_HW_CONF2_AXIM_ID_WIDTH_SHIFT (0U) #define GTM_gtm_cls1_CCM1_HW_CONF2_AXIM_ID_WIDTH_WIDTH (5U) #define GTM_gtm_cls1_CCM1_HW_CONF2_AXIM_ID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_HW_CONF2_AXIM_ID_WIDTH_SHIFT)) & GTM_gtm_cls1_CCM1_HW_CONF2_AXIM_ID_WIDTH_MASK) #define GTM_gtm_cls1_CCM1_HW_CONF2_AXIM_PRIV_ACC_MASK (0x20U) #define GTM_gtm_cls1_CCM1_HW_CONF2_AXIM_PRIV_ACC_SHIFT (5U) #define GTM_gtm_cls1_CCM1_HW_CONF2_AXIM_PRIV_ACC_WIDTH (1U) #define GTM_gtm_cls1_CCM1_HW_CONF2_AXIM_PRIV_ACC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_HW_CONF2_AXIM_PRIV_ACC_SHIFT)) & GTM_gtm_cls1_CCM1_HW_CONF2_AXIM_PRIV_ACC_MASK) #define GTM_gtm_cls1_CCM1_HW_CONF2_AXIM_SEC_ACC_MASK (0x40U) #define GTM_gtm_cls1_CCM1_HW_CONF2_AXIM_SEC_ACC_SHIFT (6U) #define GTM_gtm_cls1_CCM1_HW_CONF2_AXIM_SEC_ACC_WIDTH (1U) #define GTM_gtm_cls1_CCM1_HW_CONF2_AXIM_SEC_ACC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_HW_CONF2_AXIM_SEC_ACC_SHIFT)) & GTM_gtm_cls1_CCM1_HW_CONF2_AXIM_SEC_ACC_MASK) #define GTM_gtm_cls1_CCM1_HW_CONF2_AXIM_POSTED_WRITE_MASK (0x80U) #define GTM_gtm_cls1_CCM1_HW_CONF2_AXIM_POSTED_WRITE_SHIFT (7U) #define GTM_gtm_cls1_CCM1_HW_CONF2_AXIM_POSTED_WRITE_WIDTH (1U) #define GTM_gtm_cls1_CCM1_HW_CONF2_AXIM_POSTED_WRITE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_HW_CONF2_AXIM_POSTED_WRITE_SHIFT)) & GTM_gtm_cls1_CCM1_HW_CONF2_AXIM_POSTED_WRITE_MASK) #define GTM_gtm_cls1_CCM1_HW_CONF2_TIO_OUT_RST_MASK (0x200U) #define GTM_gtm_cls1_CCM1_HW_CONF2_TIO_OUT_RST_SHIFT (9U) #define GTM_gtm_cls1_CCM1_HW_CONF2_TIO_OUT_RST_WIDTH (1U) #define GTM_gtm_cls1_CCM1_HW_CONF2_TIO_OUT_RST(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_HW_CONF2_TIO_OUT_RST_SHIFT)) & GTM_gtm_cls1_CCM1_HW_CONF2_TIO_OUT_RST_MASK) #define GTM_gtm_cls1_CCM1_HW_CONF2_AXIS_DATA_SIZE_MASK (0x10000U) #define GTM_gtm_cls1_CCM1_HW_CONF2_AXIS_DATA_SIZE_SHIFT (16U) #define GTM_gtm_cls1_CCM1_HW_CONF2_AXIS_DATA_SIZE_WIDTH (1U) #define GTM_gtm_cls1_CCM1_HW_CONF2_AXIS_DATA_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_HW_CONF2_AXIS_DATA_SIZE_SHIFT)) & GTM_gtm_cls1_CCM1_HW_CONF2_AXIS_DATA_SIZE_MASK) #define GTM_gtm_cls1_CCM1_HW_CONF2_AXIM_DATA_SIZE_MASK (0x40000U) #define GTM_gtm_cls1_CCM1_HW_CONF2_AXIM_DATA_SIZE_SHIFT (18U) #define GTM_gtm_cls1_CCM1_HW_CONF2_AXIM_DATA_SIZE_WIDTH (1U) #define GTM_gtm_cls1_CCM1_HW_CONF2_AXIM_DATA_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_HW_CONF2_AXIM_DATA_SIZE_SHIFT)) & GTM_gtm_cls1_CCM1_HW_CONF2_AXIM_DATA_SIZE_MASK) /*! @} */ /*! @name CCM1_AEIM_STA - CCM[i] MCS Bus Master Status Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_AEIM_STA_AEIM_XPT_ADDR_MASK (0xFFFFU) #define GTM_gtm_cls1_CCM1_AEIM_STA_AEIM_XPT_ADDR_SHIFT (0U) #define GTM_gtm_cls1_CCM1_AEIM_STA_AEIM_XPT_ADDR_WIDTH (16U) #define GTM_gtm_cls1_CCM1_AEIM_STA_AEIM_XPT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_AEIM_STA_AEIM_XPT_ADDR_SHIFT)) & GTM_gtm_cls1_CCM1_AEIM_STA_AEIM_XPT_ADDR_MASK) #define GTM_gtm_cls1_CCM1_AEIM_STA_AEIM_XPT_STA_MASK (0x3000000U) #define GTM_gtm_cls1_CCM1_AEIM_STA_AEIM_XPT_STA_SHIFT (24U) #define GTM_gtm_cls1_CCM1_AEIM_STA_AEIM_XPT_STA_WIDTH (2U) #define GTM_gtm_cls1_CCM1_AEIM_STA_AEIM_XPT_STA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_AEIM_STA_AEIM_XPT_STA_SHIFT)) & GTM_gtm_cls1_CCM1_AEIM_STA_AEIM_XPT_STA_MASK) /*! @} */ /*! @name CCM1_HW_CONF - CCM[i] Hardware Configuration Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_HW_CONF_GRSTEN_MASK (0x1U) #define GTM_gtm_cls1_CCM1_HW_CONF_GRSTEN_SHIFT (0U) #define GTM_gtm_cls1_CCM1_HW_CONF_GRSTEN_WIDTH (1U) #define GTM_gtm_cls1_CCM1_HW_CONF_GRSTEN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_HW_CONF_GRSTEN_SHIFT)) & GTM_gtm_cls1_CCM1_HW_CONF_GRSTEN_MASK) #define GTM_gtm_cls1_CCM1_HW_CONF_BRIDGE_MODE_RST_MASK (0x2U) #define GTM_gtm_cls1_CCM1_HW_CONF_BRIDGE_MODE_RST_SHIFT (1U) #define GTM_gtm_cls1_CCM1_HW_CONF_BRIDGE_MODE_RST_WIDTH (1U) #define GTM_gtm_cls1_CCM1_HW_CONF_BRIDGE_MODE_RST(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_HW_CONF_BRIDGE_MODE_RST_SHIFT)) & GTM_gtm_cls1_CCM1_HW_CONF_BRIDGE_MODE_RST_MASK) #define GTM_gtm_cls1_CCM1_HW_CONF_SYNC_INPUT_REG_MASK (0x4U) #define GTM_gtm_cls1_CCM1_HW_CONF_SYNC_INPUT_REG_SHIFT (2U) #define GTM_gtm_cls1_CCM1_HW_CONF_SYNC_INPUT_REG_WIDTH (1U) #define GTM_gtm_cls1_CCM1_HW_CONF_SYNC_INPUT_REG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_HW_CONF_SYNC_INPUT_REG_SHIFT)) & GTM_gtm_cls1_CCM1_HW_CONF_SYNC_INPUT_REG_MASK) #define GTM_gtm_cls1_CCM1_HW_CONF_CFG_CLOCK_RATE_MASK (0x8U) #define GTM_gtm_cls1_CCM1_HW_CONF_CFG_CLOCK_RATE_SHIFT (3U) #define GTM_gtm_cls1_CCM1_HW_CONF_CFG_CLOCK_RATE_WIDTH (1U) #define GTM_gtm_cls1_CCM1_HW_CONF_CFG_CLOCK_RATE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_HW_CONF_CFG_CLOCK_RATE_SHIFT)) & GTM_gtm_cls1_CCM1_HW_CONF_CFG_CLOCK_RATE_MASK) #define GTM_gtm_cls1_CCM1_HW_CONF_ATOM_OUT_RST_MASK (0x10U) #define GTM_gtm_cls1_CCM1_HW_CONF_ATOM_OUT_RST_SHIFT (4U) #define GTM_gtm_cls1_CCM1_HW_CONF_ATOM_OUT_RST_WIDTH (1U) #define GTM_gtm_cls1_CCM1_HW_CONF_ATOM_OUT_RST(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_HW_CONF_ATOM_OUT_RST_SHIFT)) & GTM_gtm_cls1_CCM1_HW_CONF_ATOM_OUT_RST_MASK) #define GTM_gtm_cls1_CCM1_HW_CONF_ATOM_TRIG_CHAIN_MASK (0xE0U) #define GTM_gtm_cls1_CCM1_HW_CONF_ATOM_TRIG_CHAIN_SHIFT (5U) #define GTM_gtm_cls1_CCM1_HW_CONF_ATOM_TRIG_CHAIN_WIDTH (3U) #define GTM_gtm_cls1_CCM1_HW_CONF_ATOM_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_HW_CONF_ATOM_TRIG_CHAIN_SHIFT)) & GTM_gtm_cls1_CCM1_HW_CONF_ATOM_TRIG_CHAIN_MASK) #define GTM_gtm_cls1_CCM1_HW_CONF_TOM_OUT_RST_MASK (0x100U) #define GTM_gtm_cls1_CCM1_HW_CONF_TOM_OUT_RST_SHIFT (8U) #define GTM_gtm_cls1_CCM1_HW_CONF_TOM_OUT_RST_WIDTH (1U) #define GTM_gtm_cls1_CCM1_HW_CONF_TOM_OUT_RST(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_HW_CONF_TOM_OUT_RST_SHIFT)) & GTM_gtm_cls1_CCM1_HW_CONF_TOM_OUT_RST_MASK) #define GTM_gtm_cls1_CCM1_HW_CONF_TOM_TRIG_CHAIN_MASK (0xE00U) #define GTM_gtm_cls1_CCM1_HW_CONF_TOM_TRIG_CHAIN_SHIFT (9U) #define GTM_gtm_cls1_CCM1_HW_CONF_TOM_TRIG_CHAIN_WIDTH (3U) #define GTM_gtm_cls1_CCM1_HW_CONF_TOM_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_HW_CONF_TOM_TRIG_CHAIN_SHIFT)) & GTM_gtm_cls1_CCM1_HW_CONF_TOM_TRIG_CHAIN_MASK) #define GTM_gtm_cls1_CCM1_HW_CONF_RAM_INIT_RST_MASK (0x1000U) #define GTM_gtm_cls1_CCM1_HW_CONF_RAM_INIT_RST_SHIFT (12U) #define GTM_gtm_cls1_CCM1_HW_CONF_RAM_INIT_RST_WIDTH (1U) #define GTM_gtm_cls1_CCM1_HW_CONF_RAM_INIT_RST(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_HW_CONF_RAM_INIT_RST_SHIFT)) & GTM_gtm_cls1_CCM1_HW_CONF_RAM_INIT_RST_MASK) #define GTM_gtm_cls1_CCM1_HW_CONF_ERM_MASK (0x2000U) #define GTM_gtm_cls1_CCM1_HW_CONF_ERM_SHIFT (13U) #define GTM_gtm_cls1_CCM1_HW_CONF_ERM_WIDTH (1U) #define GTM_gtm_cls1_CCM1_HW_CONF_ERM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_HW_CONF_ERM_SHIFT)) & GTM_gtm_cls1_CCM1_HW_CONF_ERM_MASK) #define GTM_gtm_cls1_CCM1_HW_CONF_RESET_ACTIVE_MASK (0x8000U) #define GTM_gtm_cls1_CCM1_HW_CONF_RESET_ACTIVE_SHIFT (15U) #define GTM_gtm_cls1_CCM1_HW_CONF_RESET_ACTIVE_WIDTH (1U) #define GTM_gtm_cls1_CCM1_HW_CONF_RESET_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_HW_CONF_RESET_ACTIVE_SHIFT)) & GTM_gtm_cls1_CCM1_HW_CONF_RESET_ACTIVE_MASK) #define GTM_gtm_cls1_CCM1_HW_CONF_IRQ_MODE_LEVEL_MASK (0x10000U) #define GTM_gtm_cls1_CCM1_HW_CONF_IRQ_MODE_LEVEL_SHIFT (16U) #define GTM_gtm_cls1_CCM1_HW_CONF_IRQ_MODE_LEVEL_WIDTH (1U) #define GTM_gtm_cls1_CCM1_HW_CONF_IRQ_MODE_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_HW_CONF_IRQ_MODE_LEVEL_SHIFT)) & GTM_gtm_cls1_CCM1_HW_CONF_IRQ_MODE_LEVEL_MASK) #define GTM_gtm_cls1_CCM1_HW_CONF_IRQ_MODE_PULSE_MASK (0x20000U) #define GTM_gtm_cls1_CCM1_HW_CONF_IRQ_MODE_PULSE_SHIFT (17U) #define GTM_gtm_cls1_CCM1_HW_CONF_IRQ_MODE_PULSE_WIDTH (1U) #define GTM_gtm_cls1_CCM1_HW_CONF_IRQ_MODE_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_HW_CONF_IRQ_MODE_PULSE_SHIFT)) & GTM_gtm_cls1_CCM1_HW_CONF_IRQ_MODE_PULSE_MASK) #define GTM_gtm_cls1_CCM1_HW_CONF_IRQ_MODE_PULSE_NOTIFY_MASK (0x40000U) #define GTM_gtm_cls1_CCM1_HW_CONF_IRQ_MODE_PULSE_NOTIFY_SHIFT (18U) #define GTM_gtm_cls1_CCM1_HW_CONF_IRQ_MODE_PULSE_NOTIFY_WIDTH (1U) #define GTM_gtm_cls1_CCM1_HW_CONF_IRQ_MODE_PULSE_NOTIFY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_HW_CONF_IRQ_MODE_PULSE_NOTIFY_SHIFT)) & GTM_gtm_cls1_CCM1_HW_CONF_IRQ_MODE_PULSE_NOTIFY_MASK) #define GTM_gtm_cls1_CCM1_HW_CONF_IRQ_MODE_SINGLE_PULSE_MASK (0x80000U) #define GTM_gtm_cls1_CCM1_HW_CONF_IRQ_MODE_SINGLE_PULSE_SHIFT (19U) #define GTM_gtm_cls1_CCM1_HW_CONF_IRQ_MODE_SINGLE_PULSE_WIDTH (1U) #define GTM_gtm_cls1_CCM1_HW_CONF_IRQ_MODE_SINGLE_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_HW_CONF_IRQ_MODE_SINGLE_PULSE_SHIFT)) & GTM_gtm_cls1_CCM1_HW_CONF_IRQ_MODE_SINGLE_PULSE_MASK) #define GTM_gtm_cls1_CCM1_HW_CONF_ATOM_TRIG_INTCHAIN_MASK (0xF00000U) #define GTM_gtm_cls1_CCM1_HW_CONF_ATOM_TRIG_INTCHAIN_SHIFT (20U) #define GTM_gtm_cls1_CCM1_HW_CONF_ATOM_TRIG_INTCHAIN_WIDTH (4U) #define GTM_gtm_cls1_CCM1_HW_CONF_ATOM_TRIG_INTCHAIN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_HW_CONF_ATOM_TRIG_INTCHAIN_SHIFT)) & GTM_gtm_cls1_CCM1_HW_CONF_ATOM_TRIG_INTCHAIN_MASK) #define GTM_gtm_cls1_CCM1_HW_CONF_TOM_TRIG_INTCHAIN_MASK (0x1F000000U) #define GTM_gtm_cls1_CCM1_HW_CONF_TOM_TRIG_INTCHAIN_SHIFT (24U) #define GTM_gtm_cls1_CCM1_HW_CONF_TOM_TRIG_INTCHAIN_WIDTH (5U) #define GTM_gtm_cls1_CCM1_HW_CONF_TOM_TRIG_INTCHAIN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_HW_CONF_TOM_TRIG_INTCHAIN_SHIFT)) & GTM_gtm_cls1_CCM1_HW_CONF_TOM_TRIG_INTCHAIN_MASK) #define GTM_gtm_cls1_CCM1_HW_CONF_INT_CLK_EN_GEN_MASK (0x20000000U) #define GTM_gtm_cls1_CCM1_HW_CONF_INT_CLK_EN_GEN_SHIFT (29U) #define GTM_gtm_cls1_CCM1_HW_CONF_INT_CLK_EN_GEN_WIDTH (1U) #define GTM_gtm_cls1_CCM1_HW_CONF_INT_CLK_EN_GEN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_HW_CONF_INT_CLK_EN_GEN_SHIFT)) & GTM_gtm_cls1_CCM1_HW_CONF_INT_CLK_EN_GEN_MASK) #define GTM_gtm_cls1_CCM1_HW_CONF_AEI_ADDR_PIPELINE_STAGE_MASK (0x40000000U) #define GTM_gtm_cls1_CCM1_HW_CONF_AEI_ADDR_PIPELINE_STAGE_SHIFT (30U) #define GTM_gtm_cls1_CCM1_HW_CONF_AEI_ADDR_PIPELINE_STAGE_WIDTH (1U) #define GTM_gtm_cls1_CCM1_HW_CONF_AEI_ADDR_PIPELINE_STAGE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_HW_CONF_AEI_ADDR_PIPELINE_STAGE_SHIFT)) & GTM_gtm_cls1_CCM1_HW_CONF_AEI_ADDR_PIPELINE_STAGE_MASK) #define GTM_gtm_cls1_CCM1_HW_CONF_AEI_RDATA_PIPELINE_STAGE_MASK (0x80000000U) #define GTM_gtm_cls1_CCM1_HW_CONF_AEI_RDATA_PIPELINE_STAGE_SHIFT (31U) #define GTM_gtm_cls1_CCM1_HW_CONF_AEI_RDATA_PIPELINE_STAGE_WIDTH (1U) #define GTM_gtm_cls1_CCM1_HW_CONF_AEI_RDATA_PIPELINE_STAGE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_HW_CONF_AEI_RDATA_PIPELINE_STAGE_SHIFT)) & GTM_gtm_cls1_CCM1_HW_CONF_AEI_RDATA_PIPELINE_STAGE_MASK) /*! @} */ /*! @name CCM1_TIM_AUX_IN_SRC - CCM[i] TIM AUX Input Source Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH0_MASK (0x1U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH0_SHIFT (0U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH0_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH0_SHIFT)) & GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH0_MASK) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH1_MASK (0x2U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH1_SHIFT (1U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH1_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH1_SHIFT)) & GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH1_MASK) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH2_MASK (0x4U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH2_SHIFT (2U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH2_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH2_SHIFT)) & GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH2_MASK) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH3_MASK (0x8U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH3_SHIFT (3U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH3_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH3_SHIFT)) & GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH3_MASK) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH4_MASK (0x10U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH4_SHIFT (4U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH4_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH4_SHIFT)) & GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH4_MASK) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH5_MASK (0x20U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH5_SHIFT (5U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH5_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH5_SHIFT)) & GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH5_MASK) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH6_MASK (0x40U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH6_SHIFT (6U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH6_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH6_SHIFT)) & GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH6_MASK) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH7_MASK (0x80U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH7_SHIFT (7U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH7_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH7_SHIFT)) & GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SRC_CH7_MASK) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH0_MASK (0x10000U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH0_SHIFT (16U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH0_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH0_SHIFT)) & GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH0_MASK) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH1_MASK (0x20000U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH1_SHIFT (17U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH1_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH1_SHIFT)) & GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH1_MASK) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH2_MASK (0x40000U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH2_SHIFT (18U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH2_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH2_SHIFT)) & GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH2_MASK) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH3_MASK (0x80000U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH3_SHIFT (19U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH3_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH3_SHIFT)) & GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH3_MASK) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH4_MASK (0x100000U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH4_SHIFT (20U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH4_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH4_SHIFT)) & GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH4_MASK) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH5_MASK (0x200000U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH5_SHIFT (21U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH5_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH5_SHIFT)) & GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH5_MASK) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH6_MASK (0x400000U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH6_SHIFT (22U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH6_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH6_SHIFT)) & GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH6_MASK) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH7_MASK (0x800000U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH7_SHIFT (23U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH7_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH7_SHIFT)) & GTM_gtm_cls1_CCM1_TIM_AUX_IN_SRC_SEL_OUT_N_CH7_MASK) /*! @} */ /*! @name CCM1_EXT_CAP_EN - CCM[i] External Capture Enable Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN0_MASK (0x1U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN0_SHIFT (0U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN0_WIDTH (1U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN0_SHIFT)) & GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN0_MASK) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN1_MASK (0x2U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN1_SHIFT (1U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN1_WIDTH (1U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN1_SHIFT)) & GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN1_MASK) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN2_MASK (0x4U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN2_SHIFT (2U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN2_WIDTH (1U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN2_SHIFT)) & GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN2_MASK) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN3_MASK (0x8U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN3_SHIFT (3U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN3_WIDTH (1U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN3_SHIFT)) & GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN3_MASK) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN4_MASK (0x10U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN4_SHIFT (4U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN4_WIDTH (1U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN4_SHIFT)) & GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN4_MASK) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN5_MASK (0x20U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN5_SHIFT (5U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN5_WIDTH (1U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN5_SHIFT)) & GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN5_MASK) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN6_MASK (0x40U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN6_SHIFT (6U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN6_WIDTH (1U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN6_SHIFT)) & GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN6_MASK) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN7_MASK (0x80U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN7_SHIFT (7U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN7_WIDTH (1U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN7_SHIFT)) & GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_I_EXT_CAP_EN7_MASK) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN0_MASK (0x100U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN0_SHIFT (8U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN0_WIDTH (1U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN0_SHIFT)) & GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN0_MASK) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN1_MASK (0x200U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN1_SHIFT (9U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN1_WIDTH (1U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN1_SHIFT)) & GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN1_MASK) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN2_MASK (0x400U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN2_SHIFT (10U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN2_WIDTH (1U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN2_SHIFT)) & GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN2_MASK) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN3_MASK (0x800U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN3_SHIFT (11U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN3_WIDTH (1U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN3_SHIFT)) & GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN3_MASK) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN4_MASK (0x1000U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN4_SHIFT (12U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN4_WIDTH (1U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN4_SHIFT)) & GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN4_MASK) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN5_MASK (0x2000U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN5_SHIFT (13U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN5_WIDTH (1U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN5_SHIFT)) & GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN5_MASK) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN6_MASK (0x4000U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN6_SHIFT (14U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN6_WIDTH (1U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN6_SHIFT)) & GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN6_MASK) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN7_MASK (0x8000U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN7_SHIFT (15U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN7_WIDTH (1U) #define GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN7_SHIFT)) & GTM_gtm_cls1_CCM1_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN7_MASK) /*! @} */ /*! @name CCM1_TOM_OUT - CCM[i] TOM Output Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT0_MASK (0x1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT0_SHIFT (0U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT0_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT0_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT0_MASK) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT1_MASK (0x2U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT1_SHIFT (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT1_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT1_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT1_MASK) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT2_MASK (0x4U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT2_SHIFT (2U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT2_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT2_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT2_MASK) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT3_MASK (0x8U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT3_SHIFT (3U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT3_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT3_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT3_MASK) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT4_MASK (0x10U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT4_SHIFT (4U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT4_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT4_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT4_MASK) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT5_MASK (0x20U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT5_SHIFT (5U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT5_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT5_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT5_MASK) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT6_MASK (0x40U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT6_SHIFT (6U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT6_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT6_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT6_MASK) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT7_MASK (0x80U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT7_SHIFT (7U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT7_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT7_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT7_MASK) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT8_MASK (0x100U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT8_SHIFT (8U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT8_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT8_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT8_MASK) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT9_MASK (0x200U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT9_SHIFT (9U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT9_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT9_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT9_MASK) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT10_MASK (0x400U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT10_SHIFT (10U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT10_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT10_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT10_MASK) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT11_MASK (0x800U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT11_SHIFT (11U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT11_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT11_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT11_MASK) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT12_MASK (0x1000U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT12_SHIFT (12U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT12_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT12(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT12_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT12_MASK) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT13_MASK (0x2000U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT13_SHIFT (13U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT13_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT13(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT13_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT13_MASK) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT14_MASK (0x4000U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT14_SHIFT (14U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT14_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT14(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT14_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT14_MASK) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT15_MASK (0x8000U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT15_SHIFT (15U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT15_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT15(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT15_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT15_MASK) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N0_MASK (0x10000U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N0_SHIFT (16U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N0_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N0_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N0_MASK) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N1_MASK (0x20000U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N1_SHIFT (17U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N1_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N1_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N1_MASK) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N2_MASK (0x40000U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N2_SHIFT (18U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N2_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N2_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N2_MASK) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N3_MASK (0x80000U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N3_SHIFT (19U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N3_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N3_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N3_MASK) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N4_MASK (0x100000U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N4_SHIFT (20U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N4_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N4_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N4_MASK) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N5_MASK (0x200000U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N5_SHIFT (21U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N5_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N5_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N5_MASK) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N6_MASK (0x400000U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N6_SHIFT (22U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N6_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N6_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N6_MASK) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N7_MASK (0x800000U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N7_SHIFT (23U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N7_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N7_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N7_MASK) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N8_MASK (0x1000000U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N8_SHIFT (24U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N8_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N8_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N8_MASK) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N9_MASK (0x2000000U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N9_SHIFT (25U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N9_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N9_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N9_MASK) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N10_MASK (0x4000000U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N10_SHIFT (26U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N10_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N10_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N10_MASK) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N11_MASK (0x8000000U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N11_SHIFT (27U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N11_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N11_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N11_MASK) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N12_MASK (0x10000000U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N12_SHIFT (28U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N12_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N12(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N12_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N12_MASK) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N13_MASK (0x20000000U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N13_SHIFT (29U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N13_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N13(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N13_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N13_MASK) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N14_MASK (0x40000000U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N14_SHIFT (30U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N14_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N14(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N14_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N14_MASK) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N15_MASK (0x80000000U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N15_SHIFT (31U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N15_WIDTH (1U) #define GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N15(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N15_SHIFT)) & GTM_gtm_cls1_CCM1_TOM_OUT_TOM_OUT_N15_MASK) /*! @} */ /*! @name CCM1_ATOM_OUT - CCM[i] ATOM Output Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT0_MASK (0x1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT0_SHIFT (0U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT0_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT0_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT0_MASK) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT1_MASK (0x2U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT1_SHIFT (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT1_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT1_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT1_MASK) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT2_MASK (0x4U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT2_SHIFT (2U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT2_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT2_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT2_MASK) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT3_MASK (0x8U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT3_SHIFT (3U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT3_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT3_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT3_MASK) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT4_MASK (0x10U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT4_SHIFT (4U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT4_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT4_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT4_MASK) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT5_MASK (0x20U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT5_SHIFT (5U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT5_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT5_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT5_MASK) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT6_MASK (0x40U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT6_SHIFT (6U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT6_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT6_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT6_MASK) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT7_MASK (0x80U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT7_SHIFT (7U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT7_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT7_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT7_MASK) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N0_MASK (0x100U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N0_SHIFT (8U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N0_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N0_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N0_MASK) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N1_MASK (0x200U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N1_SHIFT (9U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N1_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N1_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N1_MASK) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N2_MASK (0x400U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N2_SHIFT (10U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N2_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N2_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N2_MASK) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N3_MASK (0x800U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N3_SHIFT (11U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N3_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N3_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N3_MASK) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N4_MASK (0x1000U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N4_SHIFT (12U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N4_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N4_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N4_MASK) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N5_MASK (0x2000U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N5_SHIFT (13U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N5_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N5_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N5_MASK) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N6_MASK (0x4000U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N6_SHIFT (14U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N6_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N6_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N6_MASK) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N7_MASK (0x8000U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N7_SHIFT (15U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N7_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N7_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_I_OUT_N7_MASK) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT0_MASK (0x10000U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT0_SHIFT (16U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT0_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT0_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT0_MASK) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT1_MASK (0x20000U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT1_SHIFT (17U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT1_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT1_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT1_MASK) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT2_MASK (0x40000U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT2_SHIFT (18U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT2_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT2_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT2_MASK) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT3_MASK (0x80000U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT3_SHIFT (19U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT3_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT3_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT3_MASK) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT4_MASK (0x100000U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT4_SHIFT (20U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT4_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT4_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT4_MASK) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT5_MASK (0x200000U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT5_SHIFT (21U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT5_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT5_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT5_MASK) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT6_MASK (0x400000U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT6_SHIFT (22U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT6_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT6_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT6_MASK) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT7_MASK (0x800000U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT7_SHIFT (23U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT7_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT7_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT7_MASK) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N0_MASK (0x1000000U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N0_SHIFT (24U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N0_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N0_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N0_MASK) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N1_MASK (0x2000000U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N1_SHIFT (25U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N1_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N1_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N1_MASK) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N2_MASK (0x4000000U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N2_SHIFT (26U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N2_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N2_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N2_MASK) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N3_MASK (0x8000000U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N3_SHIFT (27U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N3_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N3_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N3_MASK) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N4_MASK (0x10000000U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N4_SHIFT (28U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N4_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N4_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N4_MASK) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N5_MASK (0x20000000U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N5_SHIFT (29U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N5_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N5_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N5_MASK) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N6_MASK (0x40000000U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N6_SHIFT (30U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N6_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N6_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N6_MASK) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N7_MASK (0x80000000U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N7_SHIFT (31U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N7_WIDTH (1U) #define GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N7_SHIFT)) & GTM_gtm_cls1_CCM1_ATOM_OUT_ATOM_IP1_OUT_N7_MASK) /*! @} */ /*! @name CCM1_CMU_CLK_CFG - CCM[i] CMU Clock Configuration Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK0_SRC_MASK (0x3U) #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK0_SRC_SHIFT (0U) #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK0_SRC_WIDTH (2U) #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK0_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK0_SRC_SHIFT)) & GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK0_SRC_MASK) #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK1_SRC_MASK (0x30U) #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK1_SRC_SHIFT (4U) #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK1_SRC_WIDTH (2U) #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK1_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK1_SRC_SHIFT)) & GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK1_SRC_MASK) #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK2_SRC_MASK (0x300U) #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK2_SRC_SHIFT (8U) #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK2_SRC_WIDTH (2U) #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK2_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK2_SRC_SHIFT)) & GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK2_SRC_MASK) #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK3_SRC_MASK (0x3000U) #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK3_SRC_SHIFT (12U) #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK3_SRC_WIDTH (2U) #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK3_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK3_SRC_SHIFT)) & GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK3_SRC_MASK) #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK4_SRC_MASK (0x30000U) #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK4_SRC_SHIFT (16U) #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK4_SRC_WIDTH (2U) #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK4_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK4_SRC_SHIFT)) & GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK4_SRC_MASK) #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK5_SRC_MASK (0x300000U) #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK5_SRC_SHIFT (20U) #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK5_SRC_WIDTH (2U) #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK5_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK5_SRC_SHIFT)) & GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK5_SRC_MASK) #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK6_SRC_MASK (0x3000000U) #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK6_SRC_SHIFT (24U) #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK6_SRC_WIDTH (2U) #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK6_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK6_SRC_SHIFT)) & GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK6_SRC_MASK) #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK7_SRC_MASK (0x30000000U) #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK7_SRC_SHIFT (28U) #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK7_SRC_WIDTH (2U) #define GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK7_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK7_SRC_SHIFT)) & GTM_gtm_cls1_CCM1_CMU_CLK_CFG_CLK7_SRC_MASK) /*! @} */ /*! @name CCM1_CMU_FXCLK_CFG - CCM[i] CMU Fixed Clock Configuration Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_CMU_FXCLK_CFG_FXCLK0_SRC_MASK (0xFU) #define GTM_gtm_cls1_CCM1_CMU_FXCLK_CFG_FXCLK0_SRC_SHIFT (0U) #define GTM_gtm_cls1_CCM1_CMU_FXCLK_CFG_FXCLK0_SRC_WIDTH (4U) #define GTM_gtm_cls1_CCM1_CMU_FXCLK_CFG_FXCLK0_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_CMU_FXCLK_CFG_FXCLK0_SRC_SHIFT)) & GTM_gtm_cls1_CCM1_CMU_FXCLK_CFG_FXCLK0_SRC_MASK) /*! @} */ /*! @name CCM1_CFG - CCM[i] Configuration Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_CFG_EN_TIM_MASK (0x1U) #define GTM_gtm_cls1_CCM1_CFG_EN_TIM_SHIFT (0U) #define GTM_gtm_cls1_CCM1_CFG_EN_TIM_WIDTH (1U) #define GTM_gtm_cls1_CCM1_CFG_EN_TIM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_CFG_EN_TIM_SHIFT)) & GTM_gtm_cls1_CCM1_CFG_EN_TIM_MASK) #define GTM_gtm_cls1_CCM1_CFG_EN_TOM_SPE_TDTM_MASK (0x2U) #define GTM_gtm_cls1_CCM1_CFG_EN_TOM_SPE_TDTM_SHIFT (1U) #define GTM_gtm_cls1_CCM1_CFG_EN_TOM_SPE_TDTM_WIDTH (1U) #define GTM_gtm_cls1_CCM1_CFG_EN_TOM_SPE_TDTM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_CFG_EN_TOM_SPE_TDTM_SHIFT)) & GTM_gtm_cls1_CCM1_CFG_EN_TOM_SPE_TDTM_MASK) #define GTM_gtm_cls1_CCM1_CFG_EN_ATOM_ADTM_MASK (0x4U) #define GTM_gtm_cls1_CCM1_CFG_EN_ATOM_ADTM_SHIFT (2U) #define GTM_gtm_cls1_CCM1_CFG_EN_ATOM_ADTM_WIDTH (1U) #define GTM_gtm_cls1_CCM1_CFG_EN_ATOM_ADTM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_CFG_EN_ATOM_ADTM_SHIFT)) & GTM_gtm_cls1_CCM1_CFG_EN_ATOM_ADTM_MASK) #define GTM_gtm_cls1_CCM1_CFG_EN_MCS_MASK (0x8U) #define GTM_gtm_cls1_CCM1_CFG_EN_MCS_SHIFT (3U) #define GTM_gtm_cls1_CCM1_CFG_EN_MCS_WIDTH (1U) #define GTM_gtm_cls1_CCM1_CFG_EN_MCS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_CFG_EN_MCS_SHIFT)) & GTM_gtm_cls1_CCM1_CFG_EN_MCS_MASK) #define GTM_gtm_cls1_CCM1_CFG_EN_CMP_MON_MASK (0x80U) #define GTM_gtm_cls1_CCM1_CFG_EN_CMP_MON_SHIFT (7U) #define GTM_gtm_cls1_CCM1_CFG_EN_CMP_MON_WIDTH (1U) #define GTM_gtm_cls1_CCM1_CFG_EN_CMP_MON(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_CFG_EN_CMP_MON_SHIFT)) & GTM_gtm_cls1_CCM1_CFG_EN_CMP_MON_MASK) #define GTM_gtm_cls1_CCM1_CFG_EN_TIO_DTM_MASK (0x100U) #define GTM_gtm_cls1_CCM1_CFG_EN_TIO_DTM_SHIFT (8U) #define GTM_gtm_cls1_CCM1_CFG_EN_TIO_DTM_WIDTH (1U) #define GTM_gtm_cls1_CCM1_CFG_EN_TIO_DTM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_CFG_EN_TIO_DTM_SHIFT)) & GTM_gtm_cls1_CCM1_CFG_EN_TIO_DTM_MASK) #define GTM_gtm_cls1_CCM1_CFG_CLS_CLK_DIV_MASK (0x30000U) #define GTM_gtm_cls1_CCM1_CFG_CLS_CLK_DIV_SHIFT (16U) #define GTM_gtm_cls1_CCM1_CFG_CLS_CLK_DIV_WIDTH (2U) #define GTM_gtm_cls1_CCM1_CFG_CLS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_CFG_CLS_CLK_DIV_SHIFT)) & GTM_gtm_cls1_CCM1_CFG_CLS_CLK_DIV_MASK) #define GTM_gtm_cls1_CCM1_CFG_TBU_DIR1_MASK (0x40000000U) #define GTM_gtm_cls1_CCM1_CFG_TBU_DIR1_SHIFT (30U) #define GTM_gtm_cls1_CCM1_CFG_TBU_DIR1_WIDTH (1U) #define GTM_gtm_cls1_CCM1_CFG_TBU_DIR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_CFG_TBU_DIR1_SHIFT)) & GTM_gtm_cls1_CCM1_CFG_TBU_DIR1_MASK) #define GTM_gtm_cls1_CCM1_CFG_TBU_DIR2_MASK (0x80000000U) #define GTM_gtm_cls1_CCM1_CFG_TBU_DIR2_SHIFT (31U) #define GTM_gtm_cls1_CCM1_CFG_TBU_DIR2_WIDTH (1U) #define GTM_gtm_cls1_CCM1_CFG_TBU_DIR2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_CFG_TBU_DIR2_SHIFT)) & GTM_gtm_cls1_CCM1_CFG_TBU_DIR2_MASK) /*! @} */ /*! @name CCM1_PROT - CCM[i] Protection Register */ /*! @{ */ #define GTM_gtm_cls1_CCM1_PROT_CLS_PROT_MASK (0x1U) #define GTM_gtm_cls1_CCM1_PROT_CLS_PROT_SHIFT (0U) #define GTM_gtm_cls1_CCM1_PROT_CLS_PROT_WIDTH (1U) #define GTM_gtm_cls1_CCM1_PROT_CLS_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CCM1_PROT_CLS_PROT_SHIFT)) & GTM_gtm_cls1_CCM1_PROT_CLS_PROT_MASK) /*! @} */ /*! @name CDTM1_DTM4_CTRL - CDTM[i]_DTM[d] global configuration and control register */ /*! @{ */ #define GTM_gtm_cls1_CDTM1_DTM4_CTRL_CLK_SEL_MASK (0x3U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL_CLK_SEL_SHIFT (0U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL_CLK_SEL_WIDTH (2U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CTRL_CLK_SEL_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CTRL_CLK_SEL_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL_DTM_SEL_MASK (0xCU) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL_DTM_SEL_SHIFT (2U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL_DTM_SEL_WIDTH (2U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL_DTM_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CTRL_DTM_SEL_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CTRL_DTM_SEL_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL_UPD_MODE_MASK (0x70U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL_UPD_MODE_SHIFT (4U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL_UPD_MODE_WIDTH (3U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL_UPD_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CTRL_UPD_MODE_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CTRL_UPD_MODE_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL_CH_SHUTOFF_EN_MASK (0x80U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL_CH_SHUTOFF_EN_SHIFT (7U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL_CH_SHUTOFF_EN_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL_CH_SHUTOFF_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CTRL_CH_SHUTOFF_EN_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CTRL_CH_SHUTOFF_EN_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL_SR_UPD_EN_MASK (0x100U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL_SR_UPD_EN_SHIFT (8U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL_SR_UPD_EN_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL_SR_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CTRL_SR_UPD_EN_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CTRL_SR_UPD_EN_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL_SHUT_OFF_RST_MASK (0x10000U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL_SHUT_OFF_RST_SHIFT (16U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL_SHUT_OFF_RST_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL_SHUT_OFF_RST(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CTRL_SHUT_OFF_RST_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CTRL_SHUT_OFF_RST_MASK) /*! @} */ /*! @name CDTM1_DTM4_CH_CTRL1 - CDTM[i]_DTM[d] channel control register 1 */ /*! @{ */ #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1SEL_0_MASK (0x1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1SEL_0_SHIFT (0U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1SEL_0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1SEL_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1SEL_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1SEL_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SWAP_0_MASK (0x8U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SWAP_0_SHIFT (3U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SWAP_0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SWAP_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SWAP_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SWAP_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1F_0_MASK (0x30U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1F_0_SHIFT (4U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1F_0_WIDTH (2U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1F_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1F_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1F_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_XDT_EN_0_1_MASK (0x40U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_XDT_EN_0_1_SHIFT (6U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_XDT_EN_0_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_XDT_EN_0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_XDT_EN_0_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_XDT_EN_0_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1SEL_1_MASK (0x100U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1SEL_1_SHIFT (8U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1SEL_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1SEL_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1SEL_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1SEL_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_I1SEL_1_MASK (0x200U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_I1SEL_1_SHIFT (9U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_I1SEL_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_I1SEL_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_I1SEL_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_I1SEL_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SH_EN_1_MASK (0x400U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SH_EN_1_SHIFT (10U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SH_EN_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SH_EN_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SH_EN_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SH_EN_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SWAP_1_MASK (0x800U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SWAP_1_SHIFT (11U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SWAP_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SWAP_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SWAP_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SWAP_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1F_1_MASK (0x3000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1F_1_SHIFT (12U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1F_1_WIDTH (2U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1F_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1F_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1F_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1SEL_2_MASK (0x10000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1SEL_2_SHIFT (16U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1SEL_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1SEL_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1SEL_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1SEL_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_I1SEL_2_MASK (0x20000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_I1SEL_2_SHIFT (17U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_I1SEL_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_I1SEL_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_I1SEL_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_I1SEL_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SH_EN_2_MASK (0x40000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SH_EN_2_SHIFT (18U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SH_EN_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SH_EN_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SH_EN_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SH_EN_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SWAP_2_MASK (0x80000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SWAP_2_SHIFT (19U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SWAP_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SWAP_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SWAP_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SWAP_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1F_2_MASK (0x300000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1F_2_SHIFT (20U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1F_2_WIDTH (2U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1F_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1F_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1F_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_XDT_EN_2_3_MASK (0x400000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_XDT_EN_2_3_SHIFT (22U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_XDT_EN_2_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_XDT_EN_2_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_XDT_EN_2_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_XDT_EN_2_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1SEL_3_MASK (0x1000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1SEL_3_SHIFT (24U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1SEL_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1SEL_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1SEL_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1SEL_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_I1SEL_3_MASK (0x2000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_I1SEL_3_SHIFT (25U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_I1SEL_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_I1SEL_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_I1SEL_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_I1SEL_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SH_EN_3_MASK (0x4000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SH_EN_3_SHIFT (26U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SH_EN_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SH_EN_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SH_EN_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SH_EN_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SWAP_3_MASK (0x8000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SWAP_3_SHIFT (27U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SWAP_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SWAP_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SWAP_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_SWAP_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1F_3_MASK (0x30000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1F_3_SHIFT (28U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1F_3_WIDTH (2U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1F_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1F_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL1_O1F_3_MASK) /*! @} */ /*! @name CDTM1_DTM4_CH_CTRL2 - CDTM[i]_DTM[d] channel control register 2 */ /*! @{ */ #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL0_0_MASK (0x1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL0_0_SHIFT (0U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL0_0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL0_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL0_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL0_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC0_0_MASK (0x2U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC0_0_SHIFT (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC0_0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC0_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC0_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC0_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL0_0_MASK (0x4U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL0_0_SHIFT (2U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL0_0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL0_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL0_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL0_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT0_0_MASK (0x8U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT0_0_SHIFT (3U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT0_0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT0_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT0_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT0_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL1_0_MASK (0x10U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL1_0_SHIFT (4U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL1_0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL1_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL1_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC1_0_MASK (0x20U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC1_0_SHIFT (5U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC1_0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC1_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC1_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL1_0_MASK (0x40U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL1_0_SHIFT (6U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL1_0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL1_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL1_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT1_0_MASK (0x80U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT1_0_SHIFT (7U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT1_0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT1_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT1_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL0_1_MASK (0x100U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL0_1_SHIFT (8U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL0_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL0_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL0_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC0_1_MASK (0x200U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC0_1_SHIFT (9U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC0_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC0_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC0_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL0_1_MASK (0x400U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL0_1_SHIFT (10U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL0_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL0_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL0_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT0_1_MASK (0x800U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT0_1_SHIFT (11U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT0_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT0_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT0_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL1_1_MASK (0x1000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL1_1_SHIFT (12U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL1_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL1_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL1_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL1_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC1_1_MASK (0x2000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC1_1_SHIFT (13U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC1_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC1_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC1_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC1_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL1_1_MASK (0x4000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL1_1_SHIFT (14U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL1_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL1_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL1_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL1_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT1_1_MASK (0x8000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT1_1_SHIFT (15U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT1_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT1_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT1_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT1_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL0_2_MASK (0x10000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL0_2_SHIFT (16U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL0_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL0_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL0_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL0_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC0_2_MASK (0x20000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC0_2_SHIFT (17U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC0_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC0_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC0_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC0_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL0_2_MASK (0x40000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL0_2_SHIFT (18U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL0_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL0_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL0_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL0_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT0_2_MASK (0x80000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT0_2_SHIFT (19U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT0_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT0_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT0_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT0_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL1_2_MASK (0x100000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL1_2_SHIFT (20U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL1_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL1_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL1_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL1_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC1_2_MASK (0x200000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC1_2_SHIFT (21U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC1_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC1_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC1_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC1_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL1_2_MASK (0x400000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL1_2_SHIFT (22U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL1_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL1_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL1_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL1_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT1_2_MASK (0x800000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT1_2_SHIFT (23U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT1_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT1_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT1_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT1_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL0_3_MASK (0x1000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL0_3_SHIFT (24U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL0_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL0_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL0_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL0_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC0_3_MASK (0x2000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC0_3_SHIFT (25U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC0_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC0_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC0_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC0_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL0_3_MASK (0x4000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL0_3_SHIFT (26U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL0_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL0_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL0_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL0_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT0_3_MASK (0x8000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT0_3_SHIFT (27U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT0_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT0_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT0_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT0_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL1_3_MASK (0x10000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL1_3_SHIFT (28U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL1_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL1_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL1_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_POL1_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC1_3_MASK (0x20000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC1_3_SHIFT (29U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC1_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC1_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC1_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_OC1_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL1_3_MASK (0x40000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL1_3_SHIFT (30U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL1_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL1_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL1_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SL1_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT1_3_MASK (0x80000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT1_3_SHIFT (31U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT1_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT1_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT1_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_DT1_3_MASK) /*! @} */ /*! @name CDTM1_DTM4_CH_CTRL2_SR - CDTM[i] DTM[j] channel control register 2 shadow */ /*! @{ */ #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL0_0_SR_MASK (0x1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL0_0_SR_SHIFT (0U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL0_0_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL0_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL0_0_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL0_0_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC0_0_SR_MASK (0x2U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC0_0_SR_SHIFT (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC0_0_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC0_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC0_0_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC0_0_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL0_0_SR_MASK (0x4U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL0_0_SR_SHIFT (2U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL0_0_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL0_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL0_0_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL0_0_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT0_0_SR_MASK (0x8U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT0_0_SR_SHIFT (3U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT0_0_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT0_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT0_0_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT0_0_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL1_0_SR_MASK (0x10U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL1_0_SR_SHIFT (4U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL1_0_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL1_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL1_0_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL1_0_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC1_0_SR_MASK (0x20U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC1_0_SR_SHIFT (5U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC1_0_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC1_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC1_0_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC1_0_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL1_0_SR_MASK (0x40U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL1_0_SR_SHIFT (6U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL1_0_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL1_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL1_0_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL1_0_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT1_0_SR_MASK (0x80U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT1_0_SR_SHIFT (7U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT1_0_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT1_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT1_0_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT1_0_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL0_1_SR_MASK (0x100U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL0_1_SR_SHIFT (8U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL0_1_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL0_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL0_1_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL0_1_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC0_1_SR_MASK (0x200U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC0_1_SR_SHIFT (9U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC0_1_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC0_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC0_1_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC0_1_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL0_1_SR_MASK (0x400U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL0_1_SR_SHIFT (10U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL0_1_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL0_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL0_1_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL0_1_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT0_1_SR_MASK (0x800U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT0_1_SR_SHIFT (11U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT0_1_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT0_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT0_1_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT0_1_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL1_1_SR_MASK (0x1000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL1_1_SR_SHIFT (12U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL1_1_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL1_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL1_1_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL1_1_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC1_1_SR_MASK (0x2000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC1_1_SR_SHIFT (13U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC1_1_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC1_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC1_1_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC1_1_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL1_1_SR_MASK (0x4000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL1_1_SR_SHIFT (14U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL1_1_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL1_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL1_1_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL1_1_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT1_1_SR_MASK (0x8000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT1_1_SR_SHIFT (15U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT1_1_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT1_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT1_1_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT1_1_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL0_2_SR_MASK (0x10000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL0_2_SR_SHIFT (16U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL0_2_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL0_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL0_2_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL0_2_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC0_2_SR_MASK (0x20000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC0_2_SR_SHIFT (17U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC0_2_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC0_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC0_2_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC0_2_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL0_2_SR_MASK (0x40000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL0_2_SR_SHIFT (18U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL0_2_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL0_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL0_2_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL0_2_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT0_2_SR_MASK (0x80000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT0_2_SR_SHIFT (19U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT0_2_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT0_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT0_2_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT0_2_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL1_2_SR_MASK (0x100000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL1_2_SR_SHIFT (20U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL1_2_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL1_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL1_2_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL1_2_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC1_2_SR_MASK (0x200000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC1_2_SR_SHIFT (21U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC1_2_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC1_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC1_2_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC1_2_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL1_2_SR_MASK (0x400000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL1_2_SR_SHIFT (22U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL1_2_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL1_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL1_2_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL1_2_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT1_2_SR_MASK (0x800000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT1_2_SR_SHIFT (23U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT1_2_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT1_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT1_2_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT1_2_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL0_3_SR_MASK (0x1000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL0_3_SR_SHIFT (24U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL0_3_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL0_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL0_3_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL0_3_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC0_3_SR_MASK (0x2000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC0_3_SR_SHIFT (25U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC0_3_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC0_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC0_3_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC0_3_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL0_3_SR_MASK (0x4000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL0_3_SR_SHIFT (26U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL0_3_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL0_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL0_3_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL0_3_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT0_3_SR_MASK (0x8000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT0_3_SR_SHIFT (27U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT0_3_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT0_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT0_3_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT0_3_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL1_3_SR_MASK (0x10000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL1_3_SR_SHIFT (28U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL1_3_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL1_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL1_3_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_POL1_3_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC1_3_SR_MASK (0x20000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC1_3_SR_SHIFT (29U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC1_3_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC1_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC1_3_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_OC1_3_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL1_3_SR_MASK (0x40000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL1_3_SR_SHIFT (30U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL1_3_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL1_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL1_3_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_SL1_3_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT1_3_SR_MASK (0x80000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT1_3_SR_SHIFT (31U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT1_3_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT1_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT1_3_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL2_SR_DT1_3_SR_MASK) /*! @} */ /*! @name CDTM1_DTM4_PS_CTRL - CDTM[i]_DTM[d] phase shift unit configuration and control register */ /*! @{ */ #define GTM_gtm_cls1_CDTM1_DTM4_PS_CTRL_RELBLK_MASK (0x3FFU) #define GTM_gtm_cls1_CDTM1_DTM4_PS_CTRL_RELBLK_SHIFT (0U) #define GTM_gtm_cls1_CDTM1_DTM4_PS_CTRL_RELBLK_WIDTH (10U) #define GTM_gtm_cls1_CDTM1_DTM4_PS_CTRL_RELBLK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_PS_CTRL_RELBLK_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_PS_CTRL_RELBLK_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_PS_CTRL_PSU_IN_SEL_MASK (0x10000U) #define GTM_gtm_cls1_CDTM1_DTM4_PS_CTRL_PSU_IN_SEL_SHIFT (16U) #define GTM_gtm_cls1_CDTM1_DTM4_PS_CTRL_PSU_IN_SEL_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_PS_CTRL_PSU_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_PS_CTRL_PSU_IN_SEL_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_PS_CTRL_PSU_IN_SEL_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_PS_CTRL_IN_POL_MASK (0x20000U) #define GTM_gtm_cls1_CDTM1_DTM4_PS_CTRL_IN_POL_SHIFT (17U) #define GTM_gtm_cls1_CDTM1_DTM4_PS_CTRL_IN_POL_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_PS_CTRL_IN_POL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_PS_CTRL_IN_POL_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_PS_CTRL_IN_POL_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_PS_CTRL_TIM_SEL_MASK (0x40000U) #define GTM_gtm_cls1_CDTM1_DTM4_PS_CTRL_TIM_SEL_SHIFT (18U) #define GTM_gtm_cls1_CDTM1_DTM4_PS_CTRL_TIM_SEL_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_PS_CTRL_TIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_PS_CTRL_TIM_SEL_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_PS_CTRL_TIM_SEL_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_PS_CTRL_SHIFT_SEL_MASK (0x300000U) #define GTM_gtm_cls1_CDTM1_DTM4_PS_CTRL_SHIFT_SEL_SHIFT (20U) #define GTM_gtm_cls1_CDTM1_DTM4_PS_CTRL_SHIFT_SEL_WIDTH (2U) #define GTM_gtm_cls1_CDTM1_DTM4_PS_CTRL_SHIFT_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_PS_CTRL_SHIFT_SEL_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_PS_CTRL_SHIFT_SEL_MASK) /*! @} */ /*! @name CDTM1_DTM4_CH_DTV - CDTM[i]_DTM[d] channel [x] dead time reload values */ /*! @{ */ #define GTM_gtm_cls1_CDTM1_DTM4_CH_DTV_RELRISE_MASK (0x1FFFU) #define GTM_gtm_cls1_CDTM1_DTM4_CH_DTV_RELRISE_SHIFT (0U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_DTV_RELRISE_WIDTH (13U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_DTV_RELRISE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_DTV_RELRISE_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_DTV_RELRISE_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_DTV_RELFALL_MASK (0x1FFF0000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_DTV_RELFALL_SHIFT (16U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_DTV_RELFALL_WIDTH (13U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_DTV_RELFALL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_DTV_RELFALL_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_DTV_RELFALL_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_DTV_HRES_MASK (0x80000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_DTV_HRES_SHIFT (31U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_DTV_HRES_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_DTV_HRES(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_DTV_HRES_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_DTV_HRES_MASK) /*! @} */ /*! @name CDTM1_DTM4_CH_SR - CDTM[i]_DTM[d] channel shadow register */ /*! @{ */ #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL0_0_SR_SR_MASK (0x1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL0_0_SR_SR_SHIFT (0U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL0_0_SR_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL0_0_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL0_0_SR_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL0_0_SR_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL1_0_SR_SR_MASK (0x2U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL1_0_SR_SR_SHIFT (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL1_0_SR_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL1_0_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL1_0_SR_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL1_0_SR_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL0_1_SR_SR_MASK (0x4U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL0_1_SR_SR_SHIFT (2U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL0_1_SR_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL0_1_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL0_1_SR_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL0_1_SR_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL1_1_SR_SR_MASK (0x8U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL1_1_SR_SR_SHIFT (3U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL1_1_SR_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL1_1_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL1_1_SR_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL1_1_SR_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL0_2_SR_SR_MASK (0x10U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL0_2_SR_SR_SHIFT (4U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL0_2_SR_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL0_2_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL0_2_SR_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL0_2_SR_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL1_2_SR_SR_MASK (0x20U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL1_2_SR_SR_SHIFT (5U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL1_2_SR_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL1_2_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL1_2_SR_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL1_2_SR_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL0_3_SR_SR_MASK (0x40U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL0_3_SR_SR_SHIFT (6U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL0_3_SR_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL0_3_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL0_3_SR_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL0_3_SR_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL1_3_SR_SR_MASK (0x80U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL1_3_SR_SR_SHIFT (7U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL1_3_SR_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL1_3_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL1_3_SR_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_SR_SL1_3_SR_SR_MASK) /*! @} */ /*! @name CDTM1_DTM4_CH_CTRL3 - CDTM[i]_DTM[d] channel control register 3 */ /*! @{ */ #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CII0_MASK (0x1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CII0_SHIFT (0U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CII0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CII0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CII0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CII0_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CIS0_MASK (0x2U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CIS0_SHIFT (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CIS0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CIS0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CIS0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CIS0_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL0_0_MASK (0x4U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL0_0_SHIFT (2U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL0_0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL0_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL0_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL0_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL1_0_MASK (0x8U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL1_0_SHIFT (3U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL1_0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL1_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL1_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CII1_MASK (0x100U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CII1_SHIFT (8U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CII1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CII1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CII1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CII1_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CIS1_MASK (0x200U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CIS1_SHIFT (9U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CIS1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CIS1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CIS1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CIS1_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL0_1_MASK (0x400U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL0_1_SHIFT (10U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL0_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL0_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL0_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL1_1_MASK (0x800U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL1_1_SHIFT (11U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL1_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL1_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL1_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL1_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CII2_MASK (0x10000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CII2_SHIFT (16U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CII2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CII2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CII2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CII2_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CIS2_MASK (0x20000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CIS2_SHIFT (17U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CIS2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CIS2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CIS2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CIS2_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL0_2_MASK (0x40000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL0_2_SHIFT (18U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL0_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL0_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL0_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL0_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL1_2_MASK (0x80000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL1_2_SHIFT (19U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL1_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL1_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL1_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL1_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CII3_MASK (0x1000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CII3_SHIFT (24U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CII3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CII3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CII3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CII3_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CIS3_MASK (0x2000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CIS3_SHIFT (25U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CIS3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CIS3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CIS3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_CIS3_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL0_3_MASK (0x4000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL0_3_SHIFT (26U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL0_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL0_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL0_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL0_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL1_3_MASK (0x8000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL1_3_SHIFT (27U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL1_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL1_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL1_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH_CTRL3_TSEL1_3_MASK) /*! @} */ /*! @name CDTM1_DTM4_CTRL2 - CDTM[i]_DTM[d] global configuration and control register 2 */ /*! @{ */ #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_SEL_0_MASK (0x7U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_SEL_0_SHIFT (0U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_SEL_0_WIDTH (3U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_SEL_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_SEL_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_SEL_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_POL_0_MASK (0x8U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_POL_0_SHIFT (3U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_POL_0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_POL_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_POL_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_POL_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_UPD_MODE_0_MASK (0x30U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_UPD_MODE_0_SHIFT (4U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_UPD_MODE_0_WIDTH (2U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_UPD_MODE_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CTRL2_UPD_MODE_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CTRL2_UPD_MODE_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUT_OFF_RST_0_MASK (0x40U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUT_OFF_RST_0_SHIFT (6U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUT_OFF_RST_0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUT_OFF_RST_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUT_OFF_RST_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUT_OFF_RST_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_WR_EN_0_MASK (0x80U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_WR_EN_0_SHIFT (7U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_WR_EN_0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_WR_EN_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CTRL2_WR_EN_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CTRL2_WR_EN_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_SEL_1_MASK (0x700U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_SEL_1_SHIFT (8U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_SEL_1_WIDTH (3U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_SEL_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_SEL_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_SEL_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_POL_1_MASK (0x800U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_POL_1_SHIFT (11U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_POL_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_POL_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_POL_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_POL_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_UPD_MODE_1_MASK (0x3000U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_UPD_MODE_1_SHIFT (12U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_UPD_MODE_1_WIDTH (2U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_UPD_MODE_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CTRL2_UPD_MODE_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CTRL2_UPD_MODE_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUT_OFF_RST_1_MASK (0x4000U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUT_OFF_RST_1_SHIFT (14U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUT_OFF_RST_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUT_OFF_RST_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUT_OFF_RST_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUT_OFF_RST_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_WR_EN_1_MASK (0x8000U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_WR_EN_1_SHIFT (15U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_WR_EN_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_WR_EN_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CTRL2_WR_EN_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CTRL2_WR_EN_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_SEL_2_MASK (0x70000U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_SEL_2_SHIFT (16U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_SEL_2_WIDTH (3U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_SEL_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_SEL_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_SEL_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_POL_2_MASK (0x80000U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_POL_2_SHIFT (19U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_POL_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_POL_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_POL_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_POL_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_UPD_MODE_2_MASK (0x300000U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_UPD_MODE_2_SHIFT (20U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_UPD_MODE_2_WIDTH (2U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_UPD_MODE_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CTRL2_UPD_MODE_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CTRL2_UPD_MODE_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUT_OFF_RST_2_MASK (0x400000U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUT_OFF_RST_2_SHIFT (22U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUT_OFF_RST_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUT_OFF_RST_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUT_OFF_RST_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUT_OFF_RST_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_WR_EN_2_MASK (0x800000U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_WR_EN_2_SHIFT (23U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_WR_EN_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_WR_EN_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CTRL2_WR_EN_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CTRL2_WR_EN_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_SEL_3_MASK (0x7000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_SEL_3_SHIFT (24U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_SEL_3_WIDTH (3U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_SEL_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_SEL_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_SEL_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_POL_3_MASK (0x8000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_POL_3_SHIFT (27U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_POL_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_POL_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_POL_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUTOFF_POL_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_UPD_MODE_3_MASK (0x30000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_UPD_MODE_3_SHIFT (28U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_UPD_MODE_3_WIDTH (2U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_UPD_MODE_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CTRL2_UPD_MODE_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CTRL2_UPD_MODE_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUT_OFF_RST_3_MASK (0x40000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUT_OFF_RST_3_SHIFT (30U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUT_OFF_RST_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUT_OFF_RST_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUT_OFF_RST_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CTRL2_SHUT_OFF_RST_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_WR_EN_3_MASK (0x80000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_WR_EN_3_SHIFT (31U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_WR_EN_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CTRL2_WR_EN_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CTRL2_WR_EN_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CTRL2_WR_EN_3_MASK) /*! @} */ /*! @name CDTM1_DTM4_CH0_DTV_SR - CDTM[i]_DTM[d] channel [x] dead time shadow values */ /*! @{ */ #define GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELRISE_SR_MASK (0x1FFFU) #define GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELRISE_SR_SHIFT (0U) #define GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELRISE_SR_WIDTH (13U) #define GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELRISE_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELRISE_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELRISE_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELRISE_UPD_FE0RE1_MASK (0x4000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT (14U) #define GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELRISE_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELRISE_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELRISE_UPD_FE0RE1_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELRISE_UPD_EN_MASK (0x8000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELRISE_UPD_EN_SHIFT (15U) #define GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELRISE_UPD_EN_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELRISE_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELRISE_UPD_EN_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELRISE_UPD_EN_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELFALL_SR_MASK (0x1FFF0000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELFALL_SR_SHIFT (16U) #define GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELFALL_SR_WIDTH (13U) #define GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELFALL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELFALL_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELFALL_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELFALL_UPD_FE0RE1_MASK (0x40000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT (30U) #define GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELFALL_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELFALL_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELFALL_UPD_FE0RE1_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELFALL_UPD_EN_MASK (0x80000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELFALL_UPD_EN_SHIFT (31U) #define GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELFALL_UPD_EN_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELFALL_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELFALL_UPD_EN_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH0_DTV_SR_RELFALL_UPD_EN_MASK) /*! @} */ /*! @name CDTM1_DTM4_CH1_DTV_SR - CDTM[i]_DTM[d] channel [x] dead time shadow values */ /*! @{ */ #define GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELRISE_SR_MASK (0x1FFFU) #define GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELRISE_SR_SHIFT (0U) #define GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELRISE_SR_WIDTH (13U) #define GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELRISE_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELRISE_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELRISE_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELRISE_UPD_FE0RE1_MASK (0x4000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT (14U) #define GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELRISE_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELRISE_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELRISE_UPD_FE0RE1_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELRISE_UPD_EN_MASK (0x8000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELRISE_UPD_EN_SHIFT (15U) #define GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELRISE_UPD_EN_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELRISE_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELRISE_UPD_EN_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELRISE_UPD_EN_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELFALL_SR_MASK (0x1FFF0000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELFALL_SR_SHIFT (16U) #define GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELFALL_SR_WIDTH (13U) #define GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELFALL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELFALL_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELFALL_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELFALL_UPD_FE0RE1_MASK (0x40000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT (30U) #define GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELFALL_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELFALL_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELFALL_UPD_FE0RE1_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELFALL_UPD_EN_MASK (0x80000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELFALL_UPD_EN_SHIFT (31U) #define GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELFALL_UPD_EN_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELFALL_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELFALL_UPD_EN_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH1_DTV_SR_RELFALL_UPD_EN_MASK) /*! @} */ /*! @name CDTM1_DTM4_CH2_DTV_SR - CDTM[i]_DTM[d] channel [x] dead time shadow values */ /*! @{ */ #define GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELRISE_SR_MASK (0x1FFFU) #define GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELRISE_SR_SHIFT (0U) #define GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELRISE_SR_WIDTH (13U) #define GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELRISE_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELRISE_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELRISE_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELRISE_UPD_FE0RE1_MASK (0x4000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT (14U) #define GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELRISE_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELRISE_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELRISE_UPD_FE0RE1_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELRISE_UPD_EN_MASK (0x8000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELRISE_UPD_EN_SHIFT (15U) #define GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELRISE_UPD_EN_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELRISE_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELRISE_UPD_EN_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELRISE_UPD_EN_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELFALL_SR_MASK (0x1FFF0000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELFALL_SR_SHIFT (16U) #define GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELFALL_SR_WIDTH (13U) #define GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELFALL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELFALL_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELFALL_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELFALL_UPD_FE0RE1_MASK (0x40000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT (30U) #define GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELFALL_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELFALL_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELFALL_UPD_FE0RE1_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELFALL_UPD_EN_MASK (0x80000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELFALL_UPD_EN_SHIFT (31U) #define GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELFALL_UPD_EN_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELFALL_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELFALL_UPD_EN_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH2_DTV_SR_RELFALL_UPD_EN_MASK) /*! @} */ /*! @name CDTM1_DTM4_CH3_DTV_SR - CDTM[i]_DTM[d] channel [x] dead time shadow values */ /*! @{ */ #define GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELRISE_SR_MASK (0x1FFFU) #define GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELRISE_SR_SHIFT (0U) #define GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELRISE_SR_WIDTH (13U) #define GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELRISE_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELRISE_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELRISE_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELRISE_UPD_FE0RE1_MASK (0x4000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT (14U) #define GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELRISE_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELRISE_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELRISE_UPD_FE0RE1_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELRISE_UPD_EN_MASK (0x8000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELRISE_UPD_EN_SHIFT (15U) #define GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELRISE_UPD_EN_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELRISE_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELRISE_UPD_EN_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELRISE_UPD_EN_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELFALL_SR_MASK (0x1FFF0000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELFALL_SR_SHIFT (16U) #define GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELFALL_SR_WIDTH (13U) #define GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELFALL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELFALL_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELFALL_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELFALL_UPD_FE0RE1_MASK (0x40000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT (30U) #define GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELFALL_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELFALL_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELFALL_UPD_FE0RE1_MASK) #define GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELFALL_UPD_EN_MASK (0x80000000U) #define GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELFALL_UPD_EN_SHIFT (31U) #define GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELFALL_UPD_EN_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELFALL_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELFALL_UPD_EN_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM4_CH3_DTV_SR_RELFALL_UPD_EN_MASK) /*! @} */ /*! @name CDTM1_DTM5_CTRL - CDTM[i]_DTM[d] global configuration and control register */ /*! @{ */ #define GTM_gtm_cls1_CDTM1_DTM5_CTRL_CLK_SEL_MASK (0x3U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL_CLK_SEL_SHIFT (0U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL_CLK_SEL_WIDTH (2U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CTRL_CLK_SEL_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CTRL_CLK_SEL_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL_DTM_SEL_MASK (0xCU) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL_DTM_SEL_SHIFT (2U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL_DTM_SEL_WIDTH (2U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL_DTM_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CTRL_DTM_SEL_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CTRL_DTM_SEL_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL_UPD_MODE_MASK (0x70U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL_UPD_MODE_SHIFT (4U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL_UPD_MODE_WIDTH (3U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL_UPD_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CTRL_UPD_MODE_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CTRL_UPD_MODE_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL_CH_SHUTOFF_EN_MASK (0x80U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL_CH_SHUTOFF_EN_SHIFT (7U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL_CH_SHUTOFF_EN_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL_CH_SHUTOFF_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CTRL_CH_SHUTOFF_EN_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CTRL_CH_SHUTOFF_EN_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL_SR_UPD_EN_MASK (0x100U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL_SR_UPD_EN_SHIFT (8U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL_SR_UPD_EN_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL_SR_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CTRL_SR_UPD_EN_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CTRL_SR_UPD_EN_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL_SHUT_OFF_RST_MASK (0x10000U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL_SHUT_OFF_RST_SHIFT (16U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL_SHUT_OFF_RST_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL_SHUT_OFF_RST(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CTRL_SHUT_OFF_RST_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CTRL_SHUT_OFF_RST_MASK) /*! @} */ /*! @name CDTM1_DTM5_CH_CTRL1 - CDTM[i]_DTM[d] channel control register 1 */ /*! @{ */ #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1SEL_0_MASK (0x1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1SEL_0_SHIFT (0U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1SEL_0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1SEL_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1SEL_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1SEL_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_I1SEL_0_MASK (0x2U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_I1SEL_0_SHIFT (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_I1SEL_0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_I1SEL_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_I1SEL_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_I1SEL_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SWAP_0_MASK (0x8U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SWAP_0_SHIFT (3U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SWAP_0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SWAP_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SWAP_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SWAP_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1F_0_MASK (0x30U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1F_0_SHIFT (4U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1F_0_WIDTH (2U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1F_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1F_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1F_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_XDT_EN_0_1_MASK (0x40U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_XDT_EN_0_1_SHIFT (6U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_XDT_EN_0_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_XDT_EN_0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_XDT_EN_0_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_XDT_EN_0_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1SEL_1_MASK (0x100U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1SEL_1_SHIFT (8U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1SEL_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1SEL_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1SEL_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1SEL_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_I1SEL_1_MASK (0x200U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_I1SEL_1_SHIFT (9U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_I1SEL_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_I1SEL_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_I1SEL_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_I1SEL_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SH_EN_1_MASK (0x400U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SH_EN_1_SHIFT (10U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SH_EN_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SH_EN_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SH_EN_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SH_EN_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SWAP_1_MASK (0x800U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SWAP_1_SHIFT (11U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SWAP_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SWAP_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SWAP_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SWAP_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1F_1_MASK (0x3000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1F_1_SHIFT (12U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1F_1_WIDTH (2U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1F_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1F_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1F_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1SEL_2_MASK (0x10000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1SEL_2_SHIFT (16U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1SEL_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1SEL_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1SEL_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1SEL_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_I1SEL_2_MASK (0x20000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_I1SEL_2_SHIFT (17U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_I1SEL_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_I1SEL_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_I1SEL_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_I1SEL_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SH_EN_2_MASK (0x40000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SH_EN_2_SHIFT (18U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SH_EN_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SH_EN_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SH_EN_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SH_EN_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SWAP_2_MASK (0x80000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SWAP_2_SHIFT (19U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SWAP_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SWAP_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SWAP_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SWAP_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1F_2_MASK (0x300000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1F_2_SHIFT (20U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1F_2_WIDTH (2U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1F_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1F_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1F_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_XDT_EN_2_3_MASK (0x400000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_XDT_EN_2_3_SHIFT (22U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_XDT_EN_2_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_XDT_EN_2_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_XDT_EN_2_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_XDT_EN_2_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1SEL_3_MASK (0x1000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1SEL_3_SHIFT (24U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1SEL_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1SEL_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1SEL_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1SEL_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_I1SEL_3_MASK (0x2000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_I1SEL_3_SHIFT (25U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_I1SEL_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_I1SEL_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_I1SEL_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_I1SEL_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SH_EN_3_MASK (0x4000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SH_EN_3_SHIFT (26U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SH_EN_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SH_EN_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SH_EN_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SH_EN_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SWAP_3_MASK (0x8000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SWAP_3_SHIFT (27U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SWAP_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SWAP_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SWAP_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_SWAP_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1F_3_MASK (0x30000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1F_3_SHIFT (28U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1F_3_WIDTH (2U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1F_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1F_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL1_O1F_3_MASK) /*! @} */ /*! @name CDTM1_DTM5_CH_CTRL2 - CDTM[i]_DTM[d] channel control register 2 */ /*! @{ */ #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL0_0_MASK (0x1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL0_0_SHIFT (0U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL0_0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL0_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL0_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL0_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC0_0_MASK (0x2U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC0_0_SHIFT (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC0_0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC0_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC0_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC0_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL0_0_MASK (0x4U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL0_0_SHIFT (2U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL0_0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL0_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL0_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL0_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT0_0_MASK (0x8U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT0_0_SHIFT (3U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT0_0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT0_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT0_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT0_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL1_0_MASK (0x10U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL1_0_SHIFT (4U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL1_0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL1_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL1_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC1_0_MASK (0x20U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC1_0_SHIFT (5U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC1_0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC1_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC1_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL1_0_MASK (0x40U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL1_0_SHIFT (6U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL1_0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL1_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL1_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT1_0_MASK (0x80U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT1_0_SHIFT (7U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT1_0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT1_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT1_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL0_1_MASK (0x100U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL0_1_SHIFT (8U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL0_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL0_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL0_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC0_1_MASK (0x200U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC0_1_SHIFT (9U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC0_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC0_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC0_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL0_1_MASK (0x400U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL0_1_SHIFT (10U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL0_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL0_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL0_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT0_1_MASK (0x800U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT0_1_SHIFT (11U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT0_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT0_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT0_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL1_1_MASK (0x1000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL1_1_SHIFT (12U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL1_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL1_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL1_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL1_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC1_1_MASK (0x2000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC1_1_SHIFT (13U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC1_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC1_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC1_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC1_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL1_1_MASK (0x4000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL1_1_SHIFT (14U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL1_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL1_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL1_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL1_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT1_1_MASK (0x8000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT1_1_SHIFT (15U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT1_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT1_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT1_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT1_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL0_2_MASK (0x10000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL0_2_SHIFT (16U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL0_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL0_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL0_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL0_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC0_2_MASK (0x20000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC0_2_SHIFT (17U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC0_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC0_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC0_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC0_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL0_2_MASK (0x40000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL0_2_SHIFT (18U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL0_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL0_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL0_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL0_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT0_2_MASK (0x80000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT0_2_SHIFT (19U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT0_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT0_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT0_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT0_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL1_2_MASK (0x100000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL1_2_SHIFT (20U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL1_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL1_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL1_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL1_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC1_2_MASK (0x200000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC1_2_SHIFT (21U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC1_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC1_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC1_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC1_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL1_2_MASK (0x400000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL1_2_SHIFT (22U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL1_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL1_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL1_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL1_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT1_2_MASK (0x800000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT1_2_SHIFT (23U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT1_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT1_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT1_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT1_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL0_3_MASK (0x1000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL0_3_SHIFT (24U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL0_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL0_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL0_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL0_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC0_3_MASK (0x2000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC0_3_SHIFT (25U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC0_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC0_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC0_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC0_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL0_3_MASK (0x4000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL0_3_SHIFT (26U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL0_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL0_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL0_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL0_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT0_3_MASK (0x8000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT0_3_SHIFT (27U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT0_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT0_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT0_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT0_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL1_3_MASK (0x10000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL1_3_SHIFT (28U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL1_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL1_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL1_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_POL1_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC1_3_MASK (0x20000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC1_3_SHIFT (29U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC1_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC1_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC1_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_OC1_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL1_3_MASK (0x40000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL1_3_SHIFT (30U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL1_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL1_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL1_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SL1_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT1_3_MASK (0x80000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT1_3_SHIFT (31U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT1_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT1_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT1_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_DT1_3_MASK) /*! @} */ /*! @name CDTM1_DTM5_CH_CTRL2_SR - CDTM[i] DTM[j] channel control register 2 shadow */ /*! @{ */ #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL0_0_SR_MASK (0x1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL0_0_SR_SHIFT (0U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL0_0_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL0_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL0_0_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL0_0_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC0_0_SR_MASK (0x2U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC0_0_SR_SHIFT (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC0_0_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC0_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC0_0_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC0_0_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL0_0_SR_MASK (0x4U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL0_0_SR_SHIFT (2U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL0_0_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL0_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL0_0_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL0_0_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT0_0_SR_MASK (0x8U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT0_0_SR_SHIFT (3U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT0_0_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT0_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT0_0_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT0_0_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL1_0_SR_MASK (0x10U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL1_0_SR_SHIFT (4U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL1_0_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL1_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL1_0_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL1_0_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC1_0_SR_MASK (0x20U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC1_0_SR_SHIFT (5U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC1_0_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC1_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC1_0_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC1_0_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL1_0_SR_MASK (0x40U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL1_0_SR_SHIFT (6U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL1_0_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL1_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL1_0_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL1_0_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT1_0_SR_MASK (0x80U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT1_0_SR_SHIFT (7U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT1_0_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT1_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT1_0_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT1_0_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL0_1_SR_MASK (0x100U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL0_1_SR_SHIFT (8U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL0_1_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL0_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL0_1_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL0_1_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC0_1_SR_MASK (0x200U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC0_1_SR_SHIFT (9U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC0_1_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC0_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC0_1_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC0_1_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL0_1_SR_MASK (0x400U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL0_1_SR_SHIFT (10U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL0_1_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL0_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL0_1_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL0_1_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT0_1_SR_MASK (0x800U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT0_1_SR_SHIFT (11U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT0_1_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT0_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT0_1_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT0_1_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL1_1_SR_MASK (0x1000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL1_1_SR_SHIFT (12U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL1_1_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL1_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL1_1_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL1_1_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC1_1_SR_MASK (0x2000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC1_1_SR_SHIFT (13U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC1_1_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC1_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC1_1_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC1_1_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL1_1_SR_MASK (0x4000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL1_1_SR_SHIFT (14U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL1_1_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL1_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL1_1_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL1_1_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT1_1_SR_MASK (0x8000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT1_1_SR_SHIFT (15U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT1_1_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT1_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT1_1_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT1_1_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL0_2_SR_MASK (0x10000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL0_2_SR_SHIFT (16U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL0_2_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL0_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL0_2_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL0_2_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC0_2_SR_MASK (0x20000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC0_2_SR_SHIFT (17U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC0_2_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC0_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC0_2_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC0_2_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL0_2_SR_MASK (0x40000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL0_2_SR_SHIFT (18U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL0_2_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL0_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL0_2_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL0_2_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT0_2_SR_MASK (0x80000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT0_2_SR_SHIFT (19U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT0_2_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT0_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT0_2_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT0_2_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL1_2_SR_MASK (0x100000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL1_2_SR_SHIFT (20U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL1_2_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL1_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL1_2_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL1_2_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC1_2_SR_MASK (0x200000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC1_2_SR_SHIFT (21U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC1_2_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC1_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC1_2_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC1_2_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL1_2_SR_MASK (0x400000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL1_2_SR_SHIFT (22U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL1_2_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL1_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL1_2_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL1_2_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT1_2_SR_MASK (0x800000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT1_2_SR_SHIFT (23U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT1_2_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT1_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT1_2_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT1_2_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL0_3_SR_MASK (0x1000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL0_3_SR_SHIFT (24U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL0_3_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL0_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL0_3_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL0_3_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC0_3_SR_MASK (0x2000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC0_3_SR_SHIFT (25U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC0_3_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC0_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC0_3_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC0_3_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL0_3_SR_MASK (0x4000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL0_3_SR_SHIFT (26U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL0_3_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL0_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL0_3_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL0_3_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT0_3_SR_MASK (0x8000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT0_3_SR_SHIFT (27U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT0_3_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT0_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT0_3_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT0_3_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL1_3_SR_MASK (0x10000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL1_3_SR_SHIFT (28U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL1_3_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL1_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL1_3_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_POL1_3_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC1_3_SR_MASK (0x20000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC1_3_SR_SHIFT (29U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC1_3_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC1_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC1_3_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_OC1_3_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL1_3_SR_MASK (0x40000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL1_3_SR_SHIFT (30U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL1_3_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL1_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL1_3_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_SL1_3_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT1_3_SR_MASK (0x80000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT1_3_SR_SHIFT (31U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT1_3_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT1_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT1_3_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL2_SR_DT1_3_SR_MASK) /*! @} */ /*! @name CDTM1_DTM5_PS_CTRL - CDTM[i]_DTM[d] phase shift unit configuration and control register */ /*! @{ */ #define GTM_gtm_cls1_CDTM1_DTM5_PS_CTRL_RELBLK_MASK (0x3FFU) #define GTM_gtm_cls1_CDTM1_DTM5_PS_CTRL_RELBLK_SHIFT (0U) #define GTM_gtm_cls1_CDTM1_DTM5_PS_CTRL_RELBLK_WIDTH (10U) #define GTM_gtm_cls1_CDTM1_DTM5_PS_CTRL_RELBLK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_PS_CTRL_RELBLK_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_PS_CTRL_RELBLK_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_PS_CTRL_PSU_IN_SEL_MASK (0x10000U) #define GTM_gtm_cls1_CDTM1_DTM5_PS_CTRL_PSU_IN_SEL_SHIFT (16U) #define GTM_gtm_cls1_CDTM1_DTM5_PS_CTRL_PSU_IN_SEL_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_PS_CTRL_PSU_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_PS_CTRL_PSU_IN_SEL_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_PS_CTRL_PSU_IN_SEL_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_PS_CTRL_IN_POL_MASK (0x20000U) #define GTM_gtm_cls1_CDTM1_DTM5_PS_CTRL_IN_POL_SHIFT (17U) #define GTM_gtm_cls1_CDTM1_DTM5_PS_CTRL_IN_POL_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_PS_CTRL_IN_POL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_PS_CTRL_IN_POL_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_PS_CTRL_IN_POL_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_PS_CTRL_TIM_SEL_MASK (0x40000U) #define GTM_gtm_cls1_CDTM1_DTM5_PS_CTRL_TIM_SEL_SHIFT (18U) #define GTM_gtm_cls1_CDTM1_DTM5_PS_CTRL_TIM_SEL_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_PS_CTRL_TIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_PS_CTRL_TIM_SEL_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_PS_CTRL_TIM_SEL_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_PS_CTRL_SHIFT_SEL_MASK (0x300000U) #define GTM_gtm_cls1_CDTM1_DTM5_PS_CTRL_SHIFT_SEL_SHIFT (20U) #define GTM_gtm_cls1_CDTM1_DTM5_PS_CTRL_SHIFT_SEL_WIDTH (2U) #define GTM_gtm_cls1_CDTM1_DTM5_PS_CTRL_SHIFT_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_PS_CTRL_SHIFT_SEL_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_PS_CTRL_SHIFT_SEL_MASK) /*! @} */ /*! @name CDTM1_DTM5_CH_DTV - CDTM[i]_DTM[d] channel [x] dead time reload values */ /*! @{ */ #define GTM_gtm_cls1_CDTM1_DTM5_CH_DTV_RELRISE_MASK (0x1FFFU) #define GTM_gtm_cls1_CDTM1_DTM5_CH_DTV_RELRISE_SHIFT (0U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_DTV_RELRISE_WIDTH (13U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_DTV_RELRISE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_DTV_RELRISE_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_DTV_RELRISE_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_DTV_RELFALL_MASK (0x1FFF0000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_DTV_RELFALL_SHIFT (16U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_DTV_RELFALL_WIDTH (13U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_DTV_RELFALL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_DTV_RELFALL_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_DTV_RELFALL_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_DTV_HRES_MASK (0x80000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_DTV_HRES_SHIFT (31U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_DTV_HRES_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_DTV_HRES(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_DTV_HRES_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_DTV_HRES_MASK) /*! @} */ /*! @name CDTM1_DTM5_CH_SR - CDTM[i]_DTM[d] channel shadow register */ /*! @{ */ #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL0_0_SR_SR_MASK (0x1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL0_0_SR_SR_SHIFT (0U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL0_0_SR_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL0_0_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL0_0_SR_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL0_0_SR_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL1_0_SR_SR_MASK (0x2U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL1_0_SR_SR_SHIFT (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL1_0_SR_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL1_0_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL1_0_SR_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL1_0_SR_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL0_1_SR_SR_MASK (0x4U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL0_1_SR_SR_SHIFT (2U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL0_1_SR_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL0_1_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL0_1_SR_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL0_1_SR_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL1_1_SR_SR_MASK (0x8U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL1_1_SR_SR_SHIFT (3U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL1_1_SR_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL1_1_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL1_1_SR_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL1_1_SR_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL0_2_SR_SR_MASK (0x10U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL0_2_SR_SR_SHIFT (4U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL0_2_SR_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL0_2_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL0_2_SR_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL0_2_SR_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL1_2_SR_SR_MASK (0x20U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL1_2_SR_SR_SHIFT (5U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL1_2_SR_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL1_2_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL1_2_SR_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL1_2_SR_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL0_3_SR_SR_MASK (0x40U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL0_3_SR_SR_SHIFT (6U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL0_3_SR_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL0_3_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL0_3_SR_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL0_3_SR_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL1_3_SR_SR_MASK (0x80U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL1_3_SR_SR_SHIFT (7U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL1_3_SR_SR_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL1_3_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL1_3_SR_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_SR_SL1_3_SR_SR_MASK) /*! @} */ /*! @name CDTM1_DTM5_CH_CTRL3 - CDTM[i]_DTM[d] channel control register 3 */ /*! @{ */ #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CII0_MASK (0x1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CII0_SHIFT (0U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CII0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CII0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CII0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CII0_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CIS0_MASK (0x2U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CIS0_SHIFT (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CIS0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CIS0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CIS0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CIS0_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL0_0_MASK (0x4U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL0_0_SHIFT (2U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL0_0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL0_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL0_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL0_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL1_0_MASK (0x8U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL1_0_SHIFT (3U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL1_0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL1_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL1_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CII1_MASK (0x100U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CII1_SHIFT (8U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CII1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CII1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CII1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CII1_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CIS1_MASK (0x200U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CIS1_SHIFT (9U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CIS1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CIS1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CIS1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CIS1_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL0_1_MASK (0x400U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL0_1_SHIFT (10U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL0_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL0_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL0_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL1_1_MASK (0x800U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL1_1_SHIFT (11U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL1_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL1_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL1_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL1_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CII2_MASK (0x10000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CII2_SHIFT (16U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CII2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CII2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CII2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CII2_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CIS2_MASK (0x20000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CIS2_SHIFT (17U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CIS2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CIS2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CIS2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CIS2_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL0_2_MASK (0x40000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL0_2_SHIFT (18U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL0_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL0_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL0_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL0_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL1_2_MASK (0x80000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL1_2_SHIFT (19U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL1_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL1_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL1_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL1_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CII3_MASK (0x1000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CII3_SHIFT (24U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CII3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CII3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CII3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CII3_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CIS3_MASK (0x2000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CIS3_SHIFT (25U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CIS3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CIS3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CIS3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_CIS3_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL0_3_MASK (0x4000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL0_3_SHIFT (26U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL0_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL0_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL0_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL0_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL1_3_MASK (0x8000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL1_3_SHIFT (27U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL1_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL1_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL1_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH_CTRL3_TSEL1_3_MASK) /*! @} */ /*! @name CDTM1_DTM5_CTRL2 - CDTM[i]_DTM[d] global configuration and control register 2 */ /*! @{ */ #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_SEL_0_MASK (0x7U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_SEL_0_SHIFT (0U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_SEL_0_WIDTH (3U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_SEL_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_SEL_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_SEL_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_POL_0_MASK (0x8U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_POL_0_SHIFT (3U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_POL_0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_POL_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_POL_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_POL_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_UPD_MODE_0_MASK (0x30U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_UPD_MODE_0_SHIFT (4U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_UPD_MODE_0_WIDTH (2U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_UPD_MODE_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CTRL2_UPD_MODE_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CTRL2_UPD_MODE_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUT_OFF_RST_0_MASK (0x40U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUT_OFF_RST_0_SHIFT (6U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUT_OFF_RST_0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUT_OFF_RST_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUT_OFF_RST_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUT_OFF_RST_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_WR_EN_0_MASK (0x80U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_WR_EN_0_SHIFT (7U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_WR_EN_0_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_WR_EN_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CTRL2_WR_EN_0_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CTRL2_WR_EN_0_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_SEL_1_MASK (0x700U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_SEL_1_SHIFT (8U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_SEL_1_WIDTH (3U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_SEL_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_SEL_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_SEL_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_POL_1_MASK (0x800U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_POL_1_SHIFT (11U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_POL_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_POL_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_POL_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_POL_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_UPD_MODE_1_MASK (0x3000U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_UPD_MODE_1_SHIFT (12U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_UPD_MODE_1_WIDTH (2U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_UPD_MODE_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CTRL2_UPD_MODE_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CTRL2_UPD_MODE_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUT_OFF_RST_1_MASK (0x4000U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUT_OFF_RST_1_SHIFT (14U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUT_OFF_RST_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUT_OFF_RST_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUT_OFF_RST_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUT_OFF_RST_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_WR_EN_1_MASK (0x8000U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_WR_EN_1_SHIFT (15U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_WR_EN_1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_WR_EN_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CTRL2_WR_EN_1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CTRL2_WR_EN_1_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_SEL_2_MASK (0x70000U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_SEL_2_SHIFT (16U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_SEL_2_WIDTH (3U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_SEL_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_SEL_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_SEL_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_POL_2_MASK (0x80000U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_POL_2_SHIFT (19U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_POL_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_POL_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_POL_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_POL_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_UPD_MODE_2_MASK (0x300000U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_UPD_MODE_2_SHIFT (20U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_UPD_MODE_2_WIDTH (2U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_UPD_MODE_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CTRL2_UPD_MODE_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CTRL2_UPD_MODE_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUT_OFF_RST_2_MASK (0x400000U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUT_OFF_RST_2_SHIFT (22U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUT_OFF_RST_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUT_OFF_RST_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUT_OFF_RST_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUT_OFF_RST_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_WR_EN_2_MASK (0x800000U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_WR_EN_2_SHIFT (23U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_WR_EN_2_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_WR_EN_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CTRL2_WR_EN_2_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CTRL2_WR_EN_2_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_SEL_3_MASK (0x7000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_SEL_3_SHIFT (24U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_SEL_3_WIDTH (3U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_SEL_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_SEL_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_SEL_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_POL_3_MASK (0x8000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_POL_3_SHIFT (27U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_POL_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_POL_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_POL_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUTOFF_POL_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_UPD_MODE_3_MASK (0x30000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_UPD_MODE_3_SHIFT (28U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_UPD_MODE_3_WIDTH (2U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_UPD_MODE_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CTRL2_UPD_MODE_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CTRL2_UPD_MODE_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUT_OFF_RST_3_MASK (0x40000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUT_OFF_RST_3_SHIFT (30U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUT_OFF_RST_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUT_OFF_RST_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUT_OFF_RST_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CTRL2_SHUT_OFF_RST_3_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_WR_EN_3_MASK (0x80000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_WR_EN_3_SHIFT (31U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_WR_EN_3_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CTRL2_WR_EN_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CTRL2_WR_EN_3_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CTRL2_WR_EN_3_MASK) /*! @} */ /*! @name CDTM1_DTM5_CH0_DTV_SR - CDTM[i]_DTM[d] channel [x] dead time shadow values */ /*! @{ */ #define GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELRISE_SR_MASK (0x1FFFU) #define GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELRISE_SR_SHIFT (0U) #define GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELRISE_SR_WIDTH (13U) #define GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELRISE_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELRISE_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELRISE_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELRISE_UPD_FE0RE1_MASK (0x4000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT (14U) #define GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELRISE_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELRISE_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELRISE_UPD_FE0RE1_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELRISE_UPD_EN_MASK (0x8000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELRISE_UPD_EN_SHIFT (15U) #define GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELRISE_UPD_EN_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELRISE_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELRISE_UPD_EN_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELRISE_UPD_EN_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELFALL_SR_MASK (0x1FFF0000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELFALL_SR_SHIFT (16U) #define GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELFALL_SR_WIDTH (13U) #define GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELFALL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELFALL_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELFALL_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELFALL_UPD_FE0RE1_MASK (0x40000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT (30U) #define GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELFALL_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELFALL_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELFALL_UPD_FE0RE1_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELFALL_UPD_EN_MASK (0x80000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELFALL_UPD_EN_SHIFT (31U) #define GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELFALL_UPD_EN_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELFALL_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELFALL_UPD_EN_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH0_DTV_SR_RELFALL_UPD_EN_MASK) /*! @} */ /*! @name CDTM1_DTM5_CH1_DTV_SR - CDTM[i]_DTM[d] channel [x] dead time shadow values */ /*! @{ */ #define GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELRISE_SR_MASK (0x1FFFU) #define GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELRISE_SR_SHIFT (0U) #define GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELRISE_SR_WIDTH (13U) #define GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELRISE_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELRISE_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELRISE_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELRISE_UPD_FE0RE1_MASK (0x4000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT (14U) #define GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELRISE_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELRISE_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELRISE_UPD_FE0RE1_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELRISE_UPD_EN_MASK (0x8000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELRISE_UPD_EN_SHIFT (15U) #define GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELRISE_UPD_EN_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELRISE_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELRISE_UPD_EN_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELRISE_UPD_EN_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELFALL_SR_MASK (0x1FFF0000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELFALL_SR_SHIFT (16U) #define GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELFALL_SR_WIDTH (13U) #define GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELFALL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELFALL_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELFALL_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELFALL_UPD_FE0RE1_MASK (0x40000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT (30U) #define GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELFALL_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELFALL_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELFALL_UPD_FE0RE1_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELFALL_UPD_EN_MASK (0x80000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELFALL_UPD_EN_SHIFT (31U) #define GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELFALL_UPD_EN_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELFALL_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELFALL_UPD_EN_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH1_DTV_SR_RELFALL_UPD_EN_MASK) /*! @} */ /*! @name CDTM1_DTM5_CH2_DTV_SR - CDTM[i]_DTM[d] channel [x] dead time shadow values */ /*! @{ */ #define GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELRISE_SR_MASK (0x1FFFU) #define GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELRISE_SR_SHIFT (0U) #define GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELRISE_SR_WIDTH (13U) #define GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELRISE_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELRISE_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELRISE_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELRISE_UPD_FE0RE1_MASK (0x4000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT (14U) #define GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELRISE_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELRISE_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELRISE_UPD_FE0RE1_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELRISE_UPD_EN_MASK (0x8000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELRISE_UPD_EN_SHIFT (15U) #define GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELRISE_UPD_EN_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELRISE_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELRISE_UPD_EN_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELRISE_UPD_EN_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELFALL_SR_MASK (0x1FFF0000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELFALL_SR_SHIFT (16U) #define GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELFALL_SR_WIDTH (13U) #define GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELFALL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELFALL_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELFALL_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELFALL_UPD_FE0RE1_MASK (0x40000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT (30U) #define GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELFALL_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELFALL_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELFALL_UPD_FE0RE1_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELFALL_UPD_EN_MASK (0x80000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELFALL_UPD_EN_SHIFT (31U) #define GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELFALL_UPD_EN_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELFALL_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELFALL_UPD_EN_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH2_DTV_SR_RELFALL_UPD_EN_MASK) /*! @} */ /*! @name CDTM1_DTM5_CH3_DTV_SR - CDTM[i]_DTM[d] channel [x] dead time shadow values */ /*! @{ */ #define GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELRISE_SR_MASK (0x1FFFU) #define GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELRISE_SR_SHIFT (0U) #define GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELRISE_SR_WIDTH (13U) #define GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELRISE_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELRISE_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELRISE_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELRISE_UPD_FE0RE1_MASK (0x4000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT (14U) #define GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELRISE_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELRISE_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELRISE_UPD_FE0RE1_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELRISE_UPD_EN_MASK (0x8000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELRISE_UPD_EN_SHIFT (15U) #define GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELRISE_UPD_EN_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELRISE_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELRISE_UPD_EN_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELRISE_UPD_EN_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELFALL_SR_MASK (0x1FFF0000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELFALL_SR_SHIFT (16U) #define GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELFALL_SR_WIDTH (13U) #define GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELFALL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELFALL_SR_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELFALL_SR_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELFALL_UPD_FE0RE1_MASK (0x40000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT (30U) #define GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELFALL_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELFALL_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELFALL_UPD_FE0RE1_MASK) #define GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELFALL_UPD_EN_MASK (0x80000000U) #define GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELFALL_UPD_EN_SHIFT (31U) #define GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELFALL_UPD_EN_WIDTH (1U) #define GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELFALL_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELFALL_UPD_EN_SHIFT)) & GTM_gtm_cls1_CDTM1_DTM5_CH3_DTV_SR_RELFALL_UPD_EN_MASK) /*! @} */ /*! @name SPE1_CTRL_STAT - SPE[i] Control Status Register */ /*! @{ */ #define GTM_gtm_cls1_SPE1_CTRL_STAT_EN_MASK (0x1U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_EN_SHIFT (0U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_EN_WIDTH (1U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_CTRL_STAT_EN_SHIFT)) & GTM_gtm_cls1_SPE1_CTRL_STAT_EN_MASK) #define GTM_gtm_cls1_SPE1_CTRL_STAT_SIE0_MASK (0x2U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_SIE0_SHIFT (1U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_SIE0_WIDTH (1U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_SIE0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_CTRL_STAT_SIE0_SHIFT)) & GTM_gtm_cls1_SPE1_CTRL_STAT_SIE0_MASK) #define GTM_gtm_cls1_SPE1_CTRL_STAT_SIE1_MASK (0x4U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_SIE1_SHIFT (2U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_SIE1_WIDTH (1U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_SIE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_CTRL_STAT_SIE1_SHIFT)) & GTM_gtm_cls1_SPE1_CTRL_STAT_SIE1_MASK) #define GTM_gtm_cls1_SPE1_CTRL_STAT_SIE2_MASK (0x8U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_SIE2_SHIFT (3U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_SIE2_WIDTH (1U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_SIE2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_CTRL_STAT_SIE2_SHIFT)) & GTM_gtm_cls1_SPE1_CTRL_STAT_SIE2_MASK) #define GTM_gtm_cls1_SPE1_CTRL_STAT_TRIG_SEL_MASK (0x30U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_TRIG_SEL_SHIFT (4U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_TRIG_SEL_WIDTH (2U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_TRIG_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_CTRL_STAT_TRIG_SEL_SHIFT)) & GTM_gtm_cls1_SPE1_CTRL_STAT_TRIG_SEL_MASK) #define GTM_gtm_cls1_SPE1_CTRL_STAT_TIM_SEL_MASK (0x40U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_TIM_SEL_SHIFT (6U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_TIM_SEL_WIDTH (1U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_TIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_CTRL_STAT_TIM_SEL_SHIFT)) & GTM_gtm_cls1_SPE1_CTRL_STAT_TIM_SEL_MASK) #define GTM_gtm_cls1_SPE1_CTRL_STAT_FSOM_MASK (0x80U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_FSOM_SHIFT (7U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_FSOM_WIDTH (1U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_FSOM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_CTRL_STAT_FSOM_SHIFT)) & GTM_gtm_cls1_SPE1_CTRL_STAT_FSOM_MASK) #define GTM_gtm_cls1_SPE1_CTRL_STAT_SPE_PAT_PTR_MASK (0x700U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_SPE_PAT_PTR_SHIFT (8U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_SPE_PAT_PTR_WIDTH (3U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_SPE_PAT_PTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_CTRL_STAT_SPE_PAT_PTR_SHIFT)) & GTM_gtm_cls1_SPE1_CTRL_STAT_SPE_PAT_PTR_MASK) #define GTM_gtm_cls1_SPE1_CTRL_STAT_AIP_MASK (0x7000U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_AIP_SHIFT (12U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_AIP_WIDTH (3U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_AIP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_CTRL_STAT_AIP_SHIFT)) & GTM_gtm_cls1_SPE1_CTRL_STAT_AIP_MASK) #define GTM_gtm_cls1_SPE1_CTRL_STAT_ADIR_MASK (0x8000U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_ADIR_SHIFT (15U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_ADIR_WIDTH (1U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_ADIR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_CTRL_STAT_ADIR_SHIFT)) & GTM_gtm_cls1_SPE1_CTRL_STAT_ADIR_MASK) #define GTM_gtm_cls1_SPE1_CTRL_STAT_PIP_MASK (0x70000U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_PIP_SHIFT (16U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_PIP_WIDTH (3U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_PIP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_CTRL_STAT_PIP_SHIFT)) & GTM_gtm_cls1_SPE1_CTRL_STAT_PIP_MASK) #define GTM_gtm_cls1_SPE1_CTRL_STAT_PDIR_MASK (0x80000U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_PDIR_SHIFT (19U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_PDIR_WIDTH (1U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_PDIR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_CTRL_STAT_PDIR_SHIFT)) & GTM_gtm_cls1_SPE1_CTRL_STAT_PDIR_MASK) #define GTM_gtm_cls1_SPE1_CTRL_STAT_NIP_MASK (0x700000U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_NIP_SHIFT (20U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_NIP_WIDTH (3U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_NIP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_CTRL_STAT_NIP_SHIFT)) & GTM_gtm_cls1_SPE1_CTRL_STAT_NIP_MASK) #define GTM_gtm_cls1_SPE1_CTRL_STAT_ETRIG_SEL_MASK (0x800000U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_ETRIG_SEL_SHIFT (23U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_ETRIG_SEL_WIDTH (1U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_ETRIG_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_CTRL_STAT_ETRIG_SEL_SHIFT)) & GTM_gtm_cls1_SPE1_CTRL_STAT_ETRIG_SEL_MASK) #define GTM_gtm_cls1_SPE1_CTRL_STAT_FSOL_MASK (0xFF000000U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_FSOL_SHIFT (24U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_FSOL_WIDTH (8U) #define GTM_gtm_cls1_SPE1_CTRL_STAT_FSOL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_CTRL_STAT_FSOL_SHIFT)) & GTM_gtm_cls1_SPE1_CTRL_STAT_FSOL_MASK) /*! @} */ /*! @name SPE1_PAT - SPE[i] Input Pattern Definition Register */ /*! @{ */ #define GTM_gtm_cls1_SPE1_PAT_IP0_VAL_MASK (0x1U) #define GTM_gtm_cls1_SPE1_PAT_IP0_VAL_SHIFT (0U) #define GTM_gtm_cls1_SPE1_PAT_IP0_VAL_WIDTH (1U) #define GTM_gtm_cls1_SPE1_PAT_IP0_VAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_PAT_IP0_VAL_SHIFT)) & GTM_gtm_cls1_SPE1_PAT_IP0_VAL_MASK) #define GTM_gtm_cls1_SPE1_PAT_IP0_PAT_MASK (0xEU) #define GTM_gtm_cls1_SPE1_PAT_IP0_PAT_SHIFT (1U) #define GTM_gtm_cls1_SPE1_PAT_IP0_PAT_WIDTH (3U) #define GTM_gtm_cls1_SPE1_PAT_IP0_PAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_PAT_IP0_PAT_SHIFT)) & GTM_gtm_cls1_SPE1_PAT_IP0_PAT_MASK) #define GTM_gtm_cls1_SPE1_PAT_IP1_VAL_MASK (0x10U) #define GTM_gtm_cls1_SPE1_PAT_IP1_VAL_SHIFT (4U) #define GTM_gtm_cls1_SPE1_PAT_IP1_VAL_WIDTH (1U) #define GTM_gtm_cls1_SPE1_PAT_IP1_VAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_PAT_IP1_VAL_SHIFT)) & GTM_gtm_cls1_SPE1_PAT_IP1_VAL_MASK) #define GTM_gtm_cls1_SPE1_PAT_IP1_PAT_MASK (0xE0U) #define GTM_gtm_cls1_SPE1_PAT_IP1_PAT_SHIFT (5U) #define GTM_gtm_cls1_SPE1_PAT_IP1_PAT_WIDTH (3U) #define GTM_gtm_cls1_SPE1_PAT_IP1_PAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_PAT_IP1_PAT_SHIFT)) & GTM_gtm_cls1_SPE1_PAT_IP1_PAT_MASK) #define GTM_gtm_cls1_SPE1_PAT_IP2_VAL_MASK (0x100U) #define GTM_gtm_cls1_SPE1_PAT_IP2_VAL_SHIFT (8U) #define GTM_gtm_cls1_SPE1_PAT_IP2_VAL_WIDTH (1U) #define GTM_gtm_cls1_SPE1_PAT_IP2_VAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_PAT_IP2_VAL_SHIFT)) & GTM_gtm_cls1_SPE1_PAT_IP2_VAL_MASK) #define GTM_gtm_cls1_SPE1_PAT_IP2_PAT_MASK (0xE00U) #define GTM_gtm_cls1_SPE1_PAT_IP2_PAT_SHIFT (9U) #define GTM_gtm_cls1_SPE1_PAT_IP2_PAT_WIDTH (3U) #define GTM_gtm_cls1_SPE1_PAT_IP2_PAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_PAT_IP2_PAT_SHIFT)) & GTM_gtm_cls1_SPE1_PAT_IP2_PAT_MASK) #define GTM_gtm_cls1_SPE1_PAT_IP3_VAL_MASK (0x1000U) #define GTM_gtm_cls1_SPE1_PAT_IP3_VAL_SHIFT (12U) #define GTM_gtm_cls1_SPE1_PAT_IP3_VAL_WIDTH (1U) #define GTM_gtm_cls1_SPE1_PAT_IP3_VAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_PAT_IP3_VAL_SHIFT)) & GTM_gtm_cls1_SPE1_PAT_IP3_VAL_MASK) #define GTM_gtm_cls1_SPE1_PAT_IP3_PAT_MASK (0xE000U) #define GTM_gtm_cls1_SPE1_PAT_IP3_PAT_SHIFT (13U) #define GTM_gtm_cls1_SPE1_PAT_IP3_PAT_WIDTH (3U) #define GTM_gtm_cls1_SPE1_PAT_IP3_PAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_PAT_IP3_PAT_SHIFT)) & GTM_gtm_cls1_SPE1_PAT_IP3_PAT_MASK) #define GTM_gtm_cls1_SPE1_PAT_IP4_VAL_MASK (0x10000U) #define GTM_gtm_cls1_SPE1_PAT_IP4_VAL_SHIFT (16U) #define GTM_gtm_cls1_SPE1_PAT_IP4_VAL_WIDTH (1U) #define GTM_gtm_cls1_SPE1_PAT_IP4_VAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_PAT_IP4_VAL_SHIFT)) & GTM_gtm_cls1_SPE1_PAT_IP4_VAL_MASK) #define GTM_gtm_cls1_SPE1_PAT_IP4_PAT_MASK (0xE0000U) #define GTM_gtm_cls1_SPE1_PAT_IP4_PAT_SHIFT (17U) #define GTM_gtm_cls1_SPE1_PAT_IP4_PAT_WIDTH (3U) #define GTM_gtm_cls1_SPE1_PAT_IP4_PAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_PAT_IP4_PAT_SHIFT)) & GTM_gtm_cls1_SPE1_PAT_IP4_PAT_MASK) #define GTM_gtm_cls1_SPE1_PAT_IP5_VAL_MASK (0x100000U) #define GTM_gtm_cls1_SPE1_PAT_IP5_VAL_SHIFT (20U) #define GTM_gtm_cls1_SPE1_PAT_IP5_VAL_WIDTH (1U) #define GTM_gtm_cls1_SPE1_PAT_IP5_VAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_PAT_IP5_VAL_SHIFT)) & GTM_gtm_cls1_SPE1_PAT_IP5_VAL_MASK) #define GTM_gtm_cls1_SPE1_PAT_IP5_PAT_MASK (0xE00000U) #define GTM_gtm_cls1_SPE1_PAT_IP5_PAT_SHIFT (21U) #define GTM_gtm_cls1_SPE1_PAT_IP5_PAT_WIDTH (3U) #define GTM_gtm_cls1_SPE1_PAT_IP5_PAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_PAT_IP5_PAT_SHIFT)) & GTM_gtm_cls1_SPE1_PAT_IP5_PAT_MASK) #define GTM_gtm_cls1_SPE1_PAT_IP6_VAL_MASK (0x1000000U) #define GTM_gtm_cls1_SPE1_PAT_IP6_VAL_SHIFT (24U) #define GTM_gtm_cls1_SPE1_PAT_IP6_VAL_WIDTH (1U) #define GTM_gtm_cls1_SPE1_PAT_IP6_VAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_PAT_IP6_VAL_SHIFT)) & GTM_gtm_cls1_SPE1_PAT_IP6_VAL_MASK) #define GTM_gtm_cls1_SPE1_PAT_IP6_PAT_MASK (0xE000000U) #define GTM_gtm_cls1_SPE1_PAT_IP6_PAT_SHIFT (25U) #define GTM_gtm_cls1_SPE1_PAT_IP6_PAT_WIDTH (3U) #define GTM_gtm_cls1_SPE1_PAT_IP6_PAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_PAT_IP6_PAT_SHIFT)) & GTM_gtm_cls1_SPE1_PAT_IP6_PAT_MASK) #define GTM_gtm_cls1_SPE1_PAT_IP7_VAL_MASK (0x10000000U) #define GTM_gtm_cls1_SPE1_PAT_IP7_VAL_SHIFT (28U) #define GTM_gtm_cls1_SPE1_PAT_IP7_VAL_WIDTH (1U) #define GTM_gtm_cls1_SPE1_PAT_IP7_VAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_PAT_IP7_VAL_SHIFT)) & GTM_gtm_cls1_SPE1_PAT_IP7_VAL_MASK) #define GTM_gtm_cls1_SPE1_PAT_IP7_PAT_MASK (0xE0000000U) #define GTM_gtm_cls1_SPE1_PAT_IP7_PAT_SHIFT (29U) #define GTM_gtm_cls1_SPE1_PAT_IP7_PAT_WIDTH (3U) #define GTM_gtm_cls1_SPE1_PAT_IP7_PAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_PAT_IP7_PAT_SHIFT)) & GTM_gtm_cls1_SPE1_PAT_IP7_PAT_MASK) /*! @} */ /*! @name SPE1_OUT_PAT0 - SPE[i] Output Definition Register */ /*! @{ */ #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT0_MASK (0x3U) #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT0_SHIFT (0U) #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT0_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT0_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT0_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT1_MASK (0xCU) #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT1_SHIFT (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT1_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT1_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT1_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT2_MASK (0x30U) #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT2_SHIFT (4U) #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT2_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT2_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT2_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT3_MASK (0xC0U) #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT3_SHIFT (6U) #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT3_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT3_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT3_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT4_MASK (0x300U) #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT4_SHIFT (8U) #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT4_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT4_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT4_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT5_MASK (0xC00U) #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT5_SHIFT (10U) #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT5_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT5_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT5_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT6_MASK (0x3000U) #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT6_SHIFT (12U) #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT6_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT6_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT6_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT7_MASK (0xC000U) #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT7_SHIFT (14U) #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT7_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT7_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT0_SPE_OUT_PAT7_MASK) /*! @} */ /*! @name SPE1_OUT_PAT1 - SPE[i] Output Definition Register */ /*! @{ */ #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT0_MASK (0x3U) #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT0_SHIFT (0U) #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT0_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT0_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT0_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT1_MASK (0xCU) #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT1_SHIFT (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT1_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT1_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT1_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT2_MASK (0x30U) #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT2_SHIFT (4U) #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT2_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT2_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT2_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT3_MASK (0xC0U) #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT3_SHIFT (6U) #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT3_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT3_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT3_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT4_MASK (0x300U) #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT4_SHIFT (8U) #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT4_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT4_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT4_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT5_MASK (0xC00U) #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT5_SHIFT (10U) #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT5_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT5_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT5_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT6_MASK (0x3000U) #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT6_SHIFT (12U) #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT6_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT6_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT6_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT7_MASK (0xC000U) #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT7_SHIFT (14U) #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT7_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT7_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT1_SPE_OUT_PAT7_MASK) /*! @} */ /*! @name SPE1_OUT_PAT2 - SPE[i] Output Definition Register */ /*! @{ */ #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT0_MASK (0x3U) #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT0_SHIFT (0U) #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT0_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT0_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT0_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT1_MASK (0xCU) #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT1_SHIFT (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT1_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT1_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT1_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT2_MASK (0x30U) #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT2_SHIFT (4U) #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT2_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT2_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT2_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT3_MASK (0xC0U) #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT3_SHIFT (6U) #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT3_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT3_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT3_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT4_MASK (0x300U) #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT4_SHIFT (8U) #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT4_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT4_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT4_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT5_MASK (0xC00U) #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT5_SHIFT (10U) #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT5_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT5_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT5_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT6_MASK (0x3000U) #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT6_SHIFT (12U) #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT6_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT6_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT6_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT7_MASK (0xC000U) #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT7_SHIFT (14U) #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT7_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT7_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT2_SPE_OUT_PAT7_MASK) /*! @} */ /*! @name SPE1_OUT_PAT3 - SPE[i] Output Definition Register */ /*! @{ */ #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT0_MASK (0x3U) #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT0_SHIFT (0U) #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT0_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT0_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT0_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT1_MASK (0xCU) #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT1_SHIFT (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT1_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT1_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT1_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT2_MASK (0x30U) #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT2_SHIFT (4U) #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT2_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT2_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT2_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT3_MASK (0xC0U) #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT3_SHIFT (6U) #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT3_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT3_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT3_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT4_MASK (0x300U) #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT4_SHIFT (8U) #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT4_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT4_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT4_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT5_MASK (0xC00U) #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT5_SHIFT (10U) #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT5_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT5_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT5_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT6_MASK (0x3000U) #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT6_SHIFT (12U) #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT6_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT6_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT6_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT7_MASK (0xC000U) #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT7_SHIFT (14U) #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT7_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT7_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT3_SPE_OUT_PAT7_MASK) /*! @} */ /*! @name SPE1_OUT_PAT4 - SPE[i] Output Definition Register */ /*! @{ */ #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT0_MASK (0x3U) #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT0_SHIFT (0U) #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT0_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT0_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT0_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT1_MASK (0xCU) #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT1_SHIFT (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT1_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT1_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT1_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT2_MASK (0x30U) #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT2_SHIFT (4U) #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT2_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT2_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT2_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT3_MASK (0xC0U) #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT3_SHIFT (6U) #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT3_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT3_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT3_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT4_MASK (0x300U) #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT4_SHIFT (8U) #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT4_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT4_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT4_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT5_MASK (0xC00U) #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT5_SHIFT (10U) #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT5_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT5_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT5_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT6_MASK (0x3000U) #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT6_SHIFT (12U) #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT6_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT6_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT6_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT7_MASK (0xC000U) #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT7_SHIFT (14U) #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT7_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT7_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT4_SPE_OUT_PAT7_MASK) /*! @} */ /*! @name SPE1_OUT_PAT5 - SPE[i] Output Definition Register */ /*! @{ */ #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT0_MASK (0x3U) #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT0_SHIFT (0U) #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT0_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT0_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT0_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT1_MASK (0xCU) #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT1_SHIFT (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT1_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT1_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT1_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT2_MASK (0x30U) #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT2_SHIFT (4U) #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT2_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT2_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT2_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT3_MASK (0xC0U) #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT3_SHIFT (6U) #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT3_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT3_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT3_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT4_MASK (0x300U) #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT4_SHIFT (8U) #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT4_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT4_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT4_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT5_MASK (0xC00U) #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT5_SHIFT (10U) #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT5_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT5_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT5_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT6_MASK (0x3000U) #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT6_SHIFT (12U) #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT6_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT6_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT6_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT7_MASK (0xC000U) #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT7_SHIFT (14U) #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT7_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT7_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT5_SPE_OUT_PAT7_MASK) /*! @} */ /*! @name SPE1_OUT_PAT6 - SPE[i] Output Definition Register */ /*! @{ */ #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT0_MASK (0x3U) #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT0_SHIFT (0U) #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT0_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT0_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT0_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT1_MASK (0xCU) #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT1_SHIFT (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT1_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT1_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT1_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT2_MASK (0x30U) #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT2_SHIFT (4U) #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT2_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT2_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT2_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT3_MASK (0xC0U) #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT3_SHIFT (6U) #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT3_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT3_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT3_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT4_MASK (0x300U) #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT4_SHIFT (8U) #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT4_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT4_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT4_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT5_MASK (0xC00U) #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT5_SHIFT (10U) #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT5_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT5_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT5_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT6_MASK (0x3000U) #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT6_SHIFT (12U) #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT6_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT6_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT6_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT7_MASK (0xC000U) #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT7_SHIFT (14U) #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT7_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT7_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT6_SPE_OUT_PAT7_MASK) /*! @} */ /*! @name SPE1_OUT_PAT7 - SPE[i] Output Definition Register */ /*! @{ */ #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT0_MASK (0x3U) #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT0_SHIFT (0U) #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT0_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT0_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT0_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT1_MASK (0xCU) #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT1_SHIFT (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT1_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT1_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT1_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT2_MASK (0x30U) #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT2_SHIFT (4U) #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT2_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT2_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT2_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT3_MASK (0xC0U) #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT3_SHIFT (6U) #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT3_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT3_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT3_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT4_MASK (0x300U) #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT4_SHIFT (8U) #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT4_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT4_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT4_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT5_MASK (0xC00U) #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT5_SHIFT (10U) #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT5_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT5_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT5_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT6_MASK (0x3000U) #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT6_SHIFT (12U) #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT6_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT6_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT6_MASK) #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT7_MASK (0xC000U) #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT7_SHIFT (14U) #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT7_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT7_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_PAT7_SPE_OUT_PAT7_MASK) /*! @} */ /*! @name SPE1_OUT_CTRL - SPE[i] Output Control Register */ /*! @{ */ #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL0_MASK (0x3U) #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL0_SHIFT (0U) #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL0_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL0_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL0_MASK) #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL1_MASK (0xCU) #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL1_SHIFT (2U) #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL1_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL1_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL1_MASK) #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL2_MASK (0x30U) #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL2_SHIFT (4U) #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL2_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL2_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL2_MASK) #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL3_MASK (0xC0U) #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL3_SHIFT (6U) #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL3_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL3_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL3_MASK) #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL4_MASK (0x300U) #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL4_SHIFT (8U) #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL4_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL4_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL4_MASK) #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL5_MASK (0xC00U) #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL5_SHIFT (10U) #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL5_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL5_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL5_MASK) #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL6_MASK (0x3000U) #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL6_SHIFT (12U) #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL6_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL6_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL6_MASK) #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL7_MASK (0xC000U) #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL7_SHIFT (14U) #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL7_WIDTH (2U) #define GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL7_SHIFT)) & GTM_gtm_cls1_SPE1_OUT_CTRL_SPE_OUT_CTRL7_MASK) /*! @} */ /*! @name SPE1_IRQ_NOTIFY - SPE[i] Interrupt Notification Register */ /*! @{ */ #define GTM_gtm_cls1_SPE1_IRQ_NOTIFY_SPE_NIPD_MASK (0x1U) #define GTM_gtm_cls1_SPE1_IRQ_NOTIFY_SPE_NIPD_SHIFT (0U) #define GTM_gtm_cls1_SPE1_IRQ_NOTIFY_SPE_NIPD_WIDTH (1U) #define GTM_gtm_cls1_SPE1_IRQ_NOTIFY_SPE_NIPD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_IRQ_NOTIFY_SPE_NIPD_SHIFT)) & GTM_gtm_cls1_SPE1_IRQ_NOTIFY_SPE_NIPD_MASK) #define GTM_gtm_cls1_SPE1_IRQ_NOTIFY_SPE_DCHG_MASK (0x2U) #define GTM_gtm_cls1_SPE1_IRQ_NOTIFY_SPE_DCHG_SHIFT (1U) #define GTM_gtm_cls1_SPE1_IRQ_NOTIFY_SPE_DCHG_WIDTH (1U) #define GTM_gtm_cls1_SPE1_IRQ_NOTIFY_SPE_DCHG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_IRQ_NOTIFY_SPE_DCHG_SHIFT)) & GTM_gtm_cls1_SPE1_IRQ_NOTIFY_SPE_DCHG_MASK) #define GTM_gtm_cls1_SPE1_IRQ_NOTIFY_SPE_PERR_MASK (0x4U) #define GTM_gtm_cls1_SPE1_IRQ_NOTIFY_SPE_PERR_SHIFT (2U) #define GTM_gtm_cls1_SPE1_IRQ_NOTIFY_SPE_PERR_WIDTH (1U) #define GTM_gtm_cls1_SPE1_IRQ_NOTIFY_SPE_PERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_IRQ_NOTIFY_SPE_PERR_SHIFT)) & GTM_gtm_cls1_SPE1_IRQ_NOTIFY_SPE_PERR_MASK) #define GTM_gtm_cls1_SPE1_IRQ_NOTIFY_SPE_BIS_MASK (0x8U) #define GTM_gtm_cls1_SPE1_IRQ_NOTIFY_SPE_BIS_SHIFT (3U) #define GTM_gtm_cls1_SPE1_IRQ_NOTIFY_SPE_BIS_WIDTH (1U) #define GTM_gtm_cls1_SPE1_IRQ_NOTIFY_SPE_BIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_IRQ_NOTIFY_SPE_BIS_SHIFT)) & GTM_gtm_cls1_SPE1_IRQ_NOTIFY_SPE_BIS_MASK) #define GTM_gtm_cls1_SPE1_IRQ_NOTIFY_SPE_RCMP_MASK (0x10U) #define GTM_gtm_cls1_SPE1_IRQ_NOTIFY_SPE_RCMP_SHIFT (4U) #define GTM_gtm_cls1_SPE1_IRQ_NOTIFY_SPE_RCMP_WIDTH (1U) #define GTM_gtm_cls1_SPE1_IRQ_NOTIFY_SPE_RCMP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_IRQ_NOTIFY_SPE_RCMP_SHIFT)) & GTM_gtm_cls1_SPE1_IRQ_NOTIFY_SPE_RCMP_MASK) /*! @} */ /*! @name SPE1_IRQ_EN - SPE[i] Interrupt Enable Register */ /*! @{ */ #define GTM_gtm_cls1_SPE1_IRQ_EN_SPE_NIPD_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_SPE1_IRQ_EN_SPE_NIPD_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_SPE1_IRQ_EN_SPE_NIPD_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_SPE1_IRQ_EN_SPE_NIPD_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_IRQ_EN_SPE_NIPD_IRQ_EN_SHIFT)) & GTM_gtm_cls1_SPE1_IRQ_EN_SPE_NIPD_IRQ_EN_MASK) #define GTM_gtm_cls1_SPE1_IRQ_EN_SPE_DCHG_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_SPE1_IRQ_EN_SPE_DCHG_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_SPE1_IRQ_EN_SPE_DCHG_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_SPE1_IRQ_EN_SPE_DCHG_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_IRQ_EN_SPE_DCHG_IRQ_EN_SHIFT)) & GTM_gtm_cls1_SPE1_IRQ_EN_SPE_DCHG_IRQ_EN_MASK) #define GTM_gtm_cls1_SPE1_IRQ_EN_SPE_PERR_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_SPE1_IRQ_EN_SPE_PERR_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_SPE1_IRQ_EN_SPE_PERR_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_SPE1_IRQ_EN_SPE_PERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_IRQ_EN_SPE_PERR_IRQ_EN_SHIFT)) & GTM_gtm_cls1_SPE1_IRQ_EN_SPE_PERR_IRQ_EN_MASK) #define GTM_gtm_cls1_SPE1_IRQ_EN_SPE_BIS_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls1_SPE1_IRQ_EN_SPE_BIS_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls1_SPE1_IRQ_EN_SPE_BIS_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_SPE1_IRQ_EN_SPE_BIS_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_IRQ_EN_SPE_BIS_IRQ_EN_SHIFT)) & GTM_gtm_cls1_SPE1_IRQ_EN_SPE_BIS_IRQ_EN_MASK) #define GTM_gtm_cls1_SPE1_IRQ_EN_SPE_RCMP_IRQ_EN_MASK (0x10U) #define GTM_gtm_cls1_SPE1_IRQ_EN_SPE_RCMP_IRQ_EN_SHIFT (4U) #define GTM_gtm_cls1_SPE1_IRQ_EN_SPE_RCMP_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_SPE1_IRQ_EN_SPE_RCMP_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_IRQ_EN_SPE_RCMP_IRQ_EN_SHIFT)) & GTM_gtm_cls1_SPE1_IRQ_EN_SPE_RCMP_IRQ_EN_MASK) /*! @} */ /*! @name SPE1_IRQ_FORCINT - SPE[i] Interrupt Generation By Software */ /*! @{ */ #define GTM_gtm_cls1_SPE1_IRQ_FORCINT_TRG_SPE_NIPD_MASK (0x1U) #define GTM_gtm_cls1_SPE1_IRQ_FORCINT_TRG_SPE_NIPD_SHIFT (0U) #define GTM_gtm_cls1_SPE1_IRQ_FORCINT_TRG_SPE_NIPD_WIDTH (1U) #define GTM_gtm_cls1_SPE1_IRQ_FORCINT_TRG_SPE_NIPD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_IRQ_FORCINT_TRG_SPE_NIPD_SHIFT)) & GTM_gtm_cls1_SPE1_IRQ_FORCINT_TRG_SPE_NIPD_MASK) #define GTM_gtm_cls1_SPE1_IRQ_FORCINT_TRG_SPE_DCHG_MASK (0x2U) #define GTM_gtm_cls1_SPE1_IRQ_FORCINT_TRG_SPE_DCHG_SHIFT (1U) #define GTM_gtm_cls1_SPE1_IRQ_FORCINT_TRG_SPE_DCHG_WIDTH (1U) #define GTM_gtm_cls1_SPE1_IRQ_FORCINT_TRG_SPE_DCHG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_IRQ_FORCINT_TRG_SPE_DCHG_SHIFT)) & GTM_gtm_cls1_SPE1_IRQ_FORCINT_TRG_SPE_DCHG_MASK) #define GTM_gtm_cls1_SPE1_IRQ_FORCINT_TRG_SPE_PERR_MASK (0x4U) #define GTM_gtm_cls1_SPE1_IRQ_FORCINT_TRG_SPE_PERR_SHIFT (2U) #define GTM_gtm_cls1_SPE1_IRQ_FORCINT_TRG_SPE_PERR_WIDTH (1U) #define GTM_gtm_cls1_SPE1_IRQ_FORCINT_TRG_SPE_PERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_IRQ_FORCINT_TRG_SPE_PERR_SHIFT)) & GTM_gtm_cls1_SPE1_IRQ_FORCINT_TRG_SPE_PERR_MASK) #define GTM_gtm_cls1_SPE1_IRQ_FORCINT_TRG_SPE_BIS_MASK (0x8U) #define GTM_gtm_cls1_SPE1_IRQ_FORCINT_TRG_SPE_BIS_SHIFT (3U) #define GTM_gtm_cls1_SPE1_IRQ_FORCINT_TRG_SPE_BIS_WIDTH (1U) #define GTM_gtm_cls1_SPE1_IRQ_FORCINT_TRG_SPE_BIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_IRQ_FORCINT_TRG_SPE_BIS_SHIFT)) & GTM_gtm_cls1_SPE1_IRQ_FORCINT_TRG_SPE_BIS_MASK) #define GTM_gtm_cls1_SPE1_IRQ_FORCINT_TRG_SPE_RCMP_MASK (0x10U) #define GTM_gtm_cls1_SPE1_IRQ_FORCINT_TRG_SPE_RCMP_SHIFT (4U) #define GTM_gtm_cls1_SPE1_IRQ_FORCINT_TRG_SPE_RCMP_WIDTH (1U) #define GTM_gtm_cls1_SPE1_IRQ_FORCINT_TRG_SPE_RCMP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_IRQ_FORCINT_TRG_SPE_RCMP_SHIFT)) & GTM_gtm_cls1_SPE1_IRQ_FORCINT_TRG_SPE_RCMP_MASK) /*! @} */ /*! @name SPE1_IRQ_MODE - SPE[i] Interrupt Mode Configuration Register */ /*! @{ */ #define GTM_gtm_cls1_SPE1_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls1_SPE1_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls1_SPE1_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls1_SPE1_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls1_SPE1_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name SPE1_EIRQ_EN - SPE[i] Error Interrupt Enable Register */ /*! @{ */ #define GTM_gtm_cls1_SPE1_EIRQ_EN_SPE_NIPD_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls1_SPE1_EIRQ_EN_SPE_NIPD_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls1_SPE1_EIRQ_EN_SPE_NIPD_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_SPE1_EIRQ_EN_SPE_NIPD_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_EIRQ_EN_SPE_NIPD_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_SPE1_EIRQ_EN_SPE_NIPD_EIRQ_EN_MASK) #define GTM_gtm_cls1_SPE1_EIRQ_EN_SPE_DCHG_EIRQ_EN_MASK (0x2U) #define GTM_gtm_cls1_SPE1_EIRQ_EN_SPE_DCHG_EIRQ_EN_SHIFT (1U) #define GTM_gtm_cls1_SPE1_EIRQ_EN_SPE_DCHG_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_SPE1_EIRQ_EN_SPE_DCHG_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_EIRQ_EN_SPE_DCHG_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_SPE1_EIRQ_EN_SPE_DCHG_EIRQ_EN_MASK) #define GTM_gtm_cls1_SPE1_EIRQ_EN_SPE_PERR_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls1_SPE1_EIRQ_EN_SPE_PERR_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls1_SPE1_EIRQ_EN_SPE_PERR_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_SPE1_EIRQ_EN_SPE_PERR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_EIRQ_EN_SPE_PERR_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_SPE1_EIRQ_EN_SPE_PERR_EIRQ_EN_MASK) #define GTM_gtm_cls1_SPE1_EIRQ_EN_SPE_BIS_EIRQ_EN_MASK (0x8U) #define GTM_gtm_cls1_SPE1_EIRQ_EN_SPE_BIS_EIRQ_EN_SHIFT (3U) #define GTM_gtm_cls1_SPE1_EIRQ_EN_SPE_BIS_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_SPE1_EIRQ_EN_SPE_BIS_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_EIRQ_EN_SPE_BIS_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_SPE1_EIRQ_EN_SPE_BIS_EIRQ_EN_MASK) #define GTM_gtm_cls1_SPE1_EIRQ_EN_SPE_RCMP_EIRQ_EN_MASK (0x10U) #define GTM_gtm_cls1_SPE1_EIRQ_EN_SPE_RCMP_EIRQ_EN_SHIFT (4U) #define GTM_gtm_cls1_SPE1_EIRQ_EN_SPE_RCMP_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls1_SPE1_EIRQ_EN_SPE_RCMP_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_EIRQ_EN_SPE_RCMP_EIRQ_EN_SHIFT)) & GTM_gtm_cls1_SPE1_EIRQ_EN_SPE_RCMP_EIRQ_EN_MASK) /*! @} */ /*! @name SPE1_REV_CNT - SPE[i] Input Revolution Counter */ /*! @{ */ #define GTM_gtm_cls1_SPE1_REV_CNT_REV_CNT_MASK (0xFFFFFFU) #define GTM_gtm_cls1_SPE1_REV_CNT_REV_CNT_SHIFT (0U) #define GTM_gtm_cls1_SPE1_REV_CNT_REV_CNT_WIDTH (24U) #define GTM_gtm_cls1_SPE1_REV_CNT_REV_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_REV_CNT_REV_CNT_SHIFT)) & GTM_gtm_cls1_SPE1_REV_CNT_REV_CNT_MASK) /*! @} */ /*! @name SPE1_REV_CMP - SPE[i] Revolution Counter Compare Value */ /*! @{ */ #define GTM_gtm_cls1_SPE1_REV_CMP_REV_CMP_MASK (0xFFFFFFU) #define GTM_gtm_cls1_SPE1_REV_CMP_REV_CMP_SHIFT (0U) #define GTM_gtm_cls1_SPE1_REV_CMP_REV_CMP_WIDTH (24U) #define GTM_gtm_cls1_SPE1_REV_CMP_REV_CMP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_REV_CMP_REV_CMP_SHIFT)) & GTM_gtm_cls1_SPE1_REV_CMP_REV_CMP_MASK) /*! @} */ /*! @name SPE1_CTRL_STAT2 - SPE[i] Control Status Register 2 */ /*! @{ */ #define GTM_gtm_cls1_SPE1_CTRL_STAT2_SPE_PAT_PTR_BWD_MASK (0x700U) #define GTM_gtm_cls1_SPE1_CTRL_STAT2_SPE_PAT_PTR_BWD_SHIFT (8U) #define GTM_gtm_cls1_SPE1_CTRL_STAT2_SPE_PAT_PTR_BWD_WIDTH (3U) #define GTM_gtm_cls1_SPE1_CTRL_STAT2_SPE_PAT_PTR_BWD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_CTRL_STAT2_SPE_PAT_PTR_BWD_SHIFT)) & GTM_gtm_cls1_SPE1_CTRL_STAT2_SPE_PAT_PTR_BWD_MASK) /*! @} */ /*! @name SPE1_CMD - SPE[i] Command Register */ /*! @{ */ #define GTM_gtm_cls1_SPE1_CMD_SPE_CTRL_CMD_MASK (0x3U) #define GTM_gtm_cls1_SPE1_CMD_SPE_CTRL_CMD_SHIFT (0U) #define GTM_gtm_cls1_SPE1_CMD_SPE_CTRL_CMD_WIDTH (2U) #define GTM_gtm_cls1_SPE1_CMD_SPE_CTRL_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_CMD_SPE_CTRL_CMD_SHIFT)) & GTM_gtm_cls1_SPE1_CMD_SPE_CTRL_CMD_MASK) #define GTM_gtm_cls1_SPE1_CMD_SPE_UPD_TRIG_MASK (0x10000U) #define GTM_gtm_cls1_SPE1_CMD_SPE_UPD_TRIG_SHIFT (16U) #define GTM_gtm_cls1_SPE1_CMD_SPE_UPD_TRIG_WIDTH (1U) #define GTM_gtm_cls1_SPE1_CMD_SPE_UPD_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_SPE1_CMD_SPE_UPD_TRIG_SHIFT)) & GTM_gtm_cls1_SPE1_CMD_SPE_UPD_TRIG_MASK) /*! @} */ /*! @name AXIM1_FREE - AXIM[i] slot allocation status. */ /*! @{ */ #define GTM_gtm_cls1_AXIM1_FREE_FREE0_MASK (0x1U) #define GTM_gtm_cls1_AXIM1_FREE_FREE0_SHIFT (0U) #define GTM_gtm_cls1_AXIM1_FREE_FREE0_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_FREE_FREE0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_FREE_FREE0_SHIFT)) & GTM_gtm_cls1_AXIM1_FREE_FREE0_MASK) #define GTM_gtm_cls1_AXIM1_FREE_FREE1_MASK (0x2U) #define GTM_gtm_cls1_AXIM1_FREE_FREE1_SHIFT (1U) #define GTM_gtm_cls1_AXIM1_FREE_FREE1_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_FREE_FREE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_FREE_FREE1_SHIFT)) & GTM_gtm_cls1_AXIM1_FREE_FREE1_MASK) #define GTM_gtm_cls1_AXIM1_FREE_FREE2_MASK (0x4U) #define GTM_gtm_cls1_AXIM1_FREE_FREE2_SHIFT (2U) #define GTM_gtm_cls1_AXIM1_FREE_FREE2_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_FREE_FREE2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_FREE_FREE2_SHIFT)) & GTM_gtm_cls1_AXIM1_FREE_FREE2_MASK) #define GTM_gtm_cls1_AXIM1_FREE_FREE3_MASK (0x8U) #define GTM_gtm_cls1_AXIM1_FREE_FREE3_SHIFT (3U) #define GTM_gtm_cls1_AXIM1_FREE_FREE3_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_FREE_FREE3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_FREE_FREE3_SHIFT)) & GTM_gtm_cls1_AXIM1_FREE_FREE3_MASK) /*! @} */ /*! @name AXIM1_REQUEST - AXIM[i] slot request (allocation). */ /*! @{ */ #define GTM_gtm_cls1_AXIM1_REQUEST_REQ1HOT0_MASK (0x1U) #define GTM_gtm_cls1_AXIM1_REQUEST_REQ1HOT0_SHIFT (0U) #define GTM_gtm_cls1_AXIM1_REQUEST_REQ1HOT0_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_REQUEST_REQ1HOT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_REQUEST_REQ1HOT0_SHIFT)) & GTM_gtm_cls1_AXIM1_REQUEST_REQ1HOT0_MASK) #define GTM_gtm_cls1_AXIM1_REQUEST_REQ1HOT1_MASK (0x2U) #define GTM_gtm_cls1_AXIM1_REQUEST_REQ1HOT1_SHIFT (1U) #define GTM_gtm_cls1_AXIM1_REQUEST_REQ1HOT1_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_REQUEST_REQ1HOT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_REQUEST_REQ1HOT1_SHIFT)) & GTM_gtm_cls1_AXIM1_REQUEST_REQ1HOT1_MASK) #define GTM_gtm_cls1_AXIM1_REQUEST_REQ1HOT2_MASK (0x4U) #define GTM_gtm_cls1_AXIM1_REQUEST_REQ1HOT2_SHIFT (2U) #define GTM_gtm_cls1_AXIM1_REQUEST_REQ1HOT2_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_REQUEST_REQ1HOT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_REQUEST_REQ1HOT2_SHIFT)) & GTM_gtm_cls1_AXIM1_REQUEST_REQ1HOT2_MASK) #define GTM_gtm_cls1_AXIM1_REQUEST_REQ1HOT3_MASK (0x8U) #define GTM_gtm_cls1_AXIM1_REQUEST_REQ1HOT3_SHIFT (3U) #define GTM_gtm_cls1_AXIM1_REQUEST_REQ1HOT3_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_REQUEST_REQ1HOT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_REQUEST_REQ1HOT3_SHIFT)) & GTM_gtm_cls1_AXIM1_REQUEST_REQ1HOT3_MASK) #define GTM_gtm_cls1_AXIM1_REQUEST_REQID_MASK (0xFF000000U) #define GTM_gtm_cls1_AXIM1_REQUEST_REQID_SHIFT (24U) #define GTM_gtm_cls1_AXIM1_REQUEST_REQID_WIDTH (8U) #define GTM_gtm_cls1_AXIM1_REQUEST_REQID(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_REQUEST_REQID_SHIFT)) & GTM_gtm_cls1_AXIM1_REQUEST_REQID_MASK) /*! @} */ /*! @name AXIM1_RELEASE - AXIM[i] slot release (de-allocation). */ /*! @{ */ #define GTM_gtm_cls1_AXIM1_RELEASE_RELREQ0_MASK (0x1U) #define GTM_gtm_cls1_AXIM1_RELEASE_RELREQ0_SHIFT (0U) #define GTM_gtm_cls1_AXIM1_RELEASE_RELREQ0_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_RELEASE_RELREQ0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_RELEASE_RELREQ0_SHIFT)) & GTM_gtm_cls1_AXIM1_RELEASE_RELREQ0_MASK) #define GTM_gtm_cls1_AXIM1_RELEASE_RELREQ1_MASK (0x2U) #define GTM_gtm_cls1_AXIM1_RELEASE_RELREQ1_SHIFT (1U) #define GTM_gtm_cls1_AXIM1_RELEASE_RELREQ1_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_RELEASE_RELREQ1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_RELEASE_RELREQ1_SHIFT)) & GTM_gtm_cls1_AXIM1_RELEASE_RELREQ1_MASK) #define GTM_gtm_cls1_AXIM1_RELEASE_RELREQ2_MASK (0x4U) #define GTM_gtm_cls1_AXIM1_RELEASE_RELREQ2_SHIFT (2U) #define GTM_gtm_cls1_AXIM1_RELEASE_RELREQ2_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_RELEASE_RELREQ2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_RELEASE_RELREQ2_SHIFT)) & GTM_gtm_cls1_AXIM1_RELEASE_RELREQ2_MASK) #define GTM_gtm_cls1_AXIM1_RELEASE_RELREQ3_MASK (0x8U) #define GTM_gtm_cls1_AXIM1_RELEASE_RELREQ3_SHIFT (3U) #define GTM_gtm_cls1_AXIM1_RELEASE_RELREQ3_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_RELEASE_RELREQ3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_RELEASE_RELREQ3_SHIFT)) & GTM_gtm_cls1_AXIM1_RELEASE_RELREQ3_MASK) /*! @} */ /*! @name AXIM1_SLOT0_ADDR_LOW - AXIM[i] slot[s] address bits 31:0 of AXI transaction. */ /*! @{ */ #define GTM_gtm_cls1_AXIM1_SLOT0_ADDR_LOW_AXI_ADDR_MASK (0xFFFFFFFFU) #define GTM_gtm_cls1_AXIM1_SLOT0_ADDR_LOW_AXI_ADDR_SHIFT (0U) #define GTM_gtm_cls1_AXIM1_SLOT0_ADDR_LOW_AXI_ADDR_WIDTH (32U) #define GTM_gtm_cls1_AXIM1_SLOT0_ADDR_LOW_AXI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT0_ADDR_LOW_AXI_ADDR_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT0_ADDR_LOW_AXI_ADDR_MASK) /*! @} */ /*! @name AXIM1_SLOT0_DATA_LOW - AXIM[i] slot[s] data bits 31:0 of AXI transaction. */ /*! @{ */ #define GTM_gtm_cls1_AXIM1_SLOT0_DATA_LOW_AXI_DATA_LOW_MASK (0xFFFFFFFFU) #define GTM_gtm_cls1_AXIM1_SLOT0_DATA_LOW_AXI_DATA_LOW_SHIFT (0U) #define GTM_gtm_cls1_AXIM1_SLOT0_DATA_LOW_AXI_DATA_LOW_WIDTH (32U) #define GTM_gtm_cls1_AXIM1_SLOT0_DATA_LOW_AXI_DATA_LOW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT0_DATA_LOW_AXI_DATA_LOW_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT0_DATA_LOW_AXI_DATA_LOW_MASK) /*! @} */ /*! @name AXIM1_SLOT0_CFG1 - AXIM[i] slot [s] configuration 1 */ /*! @{ */ #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_INCR_MASK (0xFU) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_INCR_SHIFT (0U) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_INCR_WIDTH (4U) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_INCR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT0_CFG1_INCR_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT0_CFG1_INCR_MASK) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AUTO_INCR_MASK (0x10U) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AUTO_INCR_SHIFT (4U) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AUTO_INCR_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AUTO_INCR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AUTO_INCR_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AUTO_INCR_MASK) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_PRIO_MASK (0x60U) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_PRIO_SHIFT (5U) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_PRIO_WIDTH (2U) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_PRIO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT0_CFG1_PRIO_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT0_CFG1_PRIO_MASK) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AXI_PROT_MASK (0x3800U) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AXI_PROT_SHIFT (11U) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AXI_PROT_WIDTH (3U) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AXI_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AXI_PROT_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AXI_PROT_MASK) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AXI_CACHE_MASK (0x3C000U) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AXI_CACHE_SHIFT (14U) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AXI_CACHE_WIDTH (4U) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AXI_CACHE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AXI_CACHE_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AXI_CACHE_MASK) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AXI_LOCK_MASK (0xC0000U) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AXI_LOCK_SHIFT (18U) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AXI_LOCK_WIDTH (2U) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AXI_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AXI_LOCK_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AXI_LOCK_MASK) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AXI_SIZE_MASK (0x1C00000U) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AXI_SIZE_SHIFT (22U) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AXI_SIZE_WIDTH (3U) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AXI_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AXI_SIZE_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AXI_SIZE_MASK) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AXI_RW_MASK (0x2000000U) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AXI_RW_SHIFT (25U) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AXI_RW_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AXI_RW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AXI_RW_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT0_CFG1_AXI_RW_MASK) /*! @} */ /*! @name AXIM1_SLOT0_CFG2 - AXIM[i] slot[s] configuration 2 */ /*! @{ */ #define GTM_gtm_cls1_AXIM1_SLOT0_CFG2_AXI_ID_MASK (0xFFFFU) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG2_AXI_ID_SHIFT (0U) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG2_AXI_ID_WIDTH (16U) #define GTM_gtm_cls1_AXIM1_SLOT0_CFG2_AXI_ID(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT0_CFG2_AXI_ID_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT0_CFG2_AXI_ID_MASK) /*! @} */ /*! @name AXIM1_SLOT0_STATUS - AXIM[i] slot[s] status */ /*! @{ */ #define GTM_gtm_cls1_AXIM1_SLOT0_STATUS_ALLOC_MASK (0x1U) #define GTM_gtm_cls1_AXIM1_SLOT0_STATUS_ALLOC_SHIFT (0U) #define GTM_gtm_cls1_AXIM1_SLOT0_STATUS_ALLOC_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_SLOT0_STATUS_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT0_STATUS_ALLOC_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT0_STATUS_ALLOC_MASK) #define GTM_gtm_cls1_AXIM1_SLOT0_STATUS_QUEUED_MASK (0x2U) #define GTM_gtm_cls1_AXIM1_SLOT0_STATUS_QUEUED_SHIFT (1U) #define GTM_gtm_cls1_AXIM1_SLOT0_STATUS_QUEUED_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_SLOT0_STATUS_QUEUED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT0_STATUS_QUEUED_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT0_STATUS_QUEUED_MASK) #define GTM_gtm_cls1_AXIM1_SLOT0_STATUS_STARTED_MASK (0x4U) #define GTM_gtm_cls1_AXIM1_SLOT0_STATUS_STARTED_SHIFT (2U) #define GTM_gtm_cls1_AXIM1_SLOT0_STATUS_STARTED_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_SLOT0_STATUS_STARTED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT0_STATUS_STARTED_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT0_STATUS_STARTED_MASK) #define GTM_gtm_cls1_AXIM1_SLOT0_STATUS_READY_MASK (0x8U) #define GTM_gtm_cls1_AXIM1_SLOT0_STATUS_READY_SHIFT (3U) #define GTM_gtm_cls1_AXIM1_SLOT0_STATUS_READY_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_SLOT0_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT0_STATUS_READY_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT0_STATUS_READY_MASK) #define GTM_gtm_cls1_AXIM1_SLOT0_STATUS_RESP_MASK (0x30U) #define GTM_gtm_cls1_AXIM1_SLOT0_STATUS_RESP_SHIFT (4U) #define GTM_gtm_cls1_AXIM1_SLOT0_STATUS_RESP_WIDTH (2U) #define GTM_gtm_cls1_AXIM1_SLOT0_STATUS_RESP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT0_STATUS_RESP_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT0_STATUS_RESP_MASK) /*! @} */ /*! @name AXIM1_SLOT1_ADDR_LOW - AXIM[i] slot[s] address bits 31:0 of AXI transaction. */ /*! @{ */ #define GTM_gtm_cls1_AXIM1_SLOT1_ADDR_LOW_AXI_ADDR_MASK (0xFFFFFFFFU) #define GTM_gtm_cls1_AXIM1_SLOT1_ADDR_LOW_AXI_ADDR_SHIFT (0U) #define GTM_gtm_cls1_AXIM1_SLOT1_ADDR_LOW_AXI_ADDR_WIDTH (32U) #define GTM_gtm_cls1_AXIM1_SLOT1_ADDR_LOW_AXI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT1_ADDR_LOW_AXI_ADDR_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT1_ADDR_LOW_AXI_ADDR_MASK) /*! @} */ /*! @name AXIM1_SLOT1_DATA_LOW - AXIM[i] slot[s] data bits 31:0 of AXI transaction. */ /*! @{ */ #define GTM_gtm_cls1_AXIM1_SLOT1_DATA_LOW_AXI_DATA_LOW_MASK (0xFFFFFFFFU) #define GTM_gtm_cls1_AXIM1_SLOT1_DATA_LOW_AXI_DATA_LOW_SHIFT (0U) #define GTM_gtm_cls1_AXIM1_SLOT1_DATA_LOW_AXI_DATA_LOW_WIDTH (32U) #define GTM_gtm_cls1_AXIM1_SLOT1_DATA_LOW_AXI_DATA_LOW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT1_DATA_LOW_AXI_DATA_LOW_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT1_DATA_LOW_AXI_DATA_LOW_MASK) /*! @} */ /*! @name AXIM1_SLOT1_CFG1 - AXIM[i] slot [s] configuration 1 */ /*! @{ */ #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_INCR_MASK (0xFU) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_INCR_SHIFT (0U) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_INCR_WIDTH (4U) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_INCR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT1_CFG1_INCR_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT1_CFG1_INCR_MASK) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AUTO_INCR_MASK (0x10U) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AUTO_INCR_SHIFT (4U) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AUTO_INCR_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AUTO_INCR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AUTO_INCR_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AUTO_INCR_MASK) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_PRIO_MASK (0x60U) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_PRIO_SHIFT (5U) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_PRIO_WIDTH (2U) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_PRIO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT1_CFG1_PRIO_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT1_CFG1_PRIO_MASK) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AXI_PROT_MASK (0x3800U) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AXI_PROT_SHIFT (11U) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AXI_PROT_WIDTH (3U) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AXI_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AXI_PROT_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AXI_PROT_MASK) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AXI_CACHE_MASK (0x3C000U) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AXI_CACHE_SHIFT (14U) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AXI_CACHE_WIDTH (4U) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AXI_CACHE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AXI_CACHE_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AXI_CACHE_MASK) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AXI_LOCK_MASK (0xC0000U) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AXI_LOCK_SHIFT (18U) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AXI_LOCK_WIDTH (2U) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AXI_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AXI_LOCK_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AXI_LOCK_MASK) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AXI_SIZE_MASK (0x1C00000U) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AXI_SIZE_SHIFT (22U) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AXI_SIZE_WIDTH (3U) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AXI_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AXI_SIZE_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AXI_SIZE_MASK) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AXI_RW_MASK (0x2000000U) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AXI_RW_SHIFT (25U) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AXI_RW_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AXI_RW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AXI_RW_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT1_CFG1_AXI_RW_MASK) /*! @} */ /*! @name AXIM1_SLOT1_CFG2 - AXIM[i] slot[s] configuration 2 */ /*! @{ */ #define GTM_gtm_cls1_AXIM1_SLOT1_CFG2_AXI_ID_MASK (0xFFFFU) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG2_AXI_ID_SHIFT (0U) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG2_AXI_ID_WIDTH (16U) #define GTM_gtm_cls1_AXIM1_SLOT1_CFG2_AXI_ID(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT1_CFG2_AXI_ID_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT1_CFG2_AXI_ID_MASK) /*! @} */ /*! @name AXIM1_SLOT1_STATUS - AXIM[i] slot[s] status */ /*! @{ */ #define GTM_gtm_cls1_AXIM1_SLOT1_STATUS_ALLOC_MASK (0x1U) #define GTM_gtm_cls1_AXIM1_SLOT1_STATUS_ALLOC_SHIFT (0U) #define GTM_gtm_cls1_AXIM1_SLOT1_STATUS_ALLOC_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_SLOT1_STATUS_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT1_STATUS_ALLOC_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT1_STATUS_ALLOC_MASK) #define GTM_gtm_cls1_AXIM1_SLOT1_STATUS_QUEUED_MASK (0x2U) #define GTM_gtm_cls1_AXIM1_SLOT1_STATUS_QUEUED_SHIFT (1U) #define GTM_gtm_cls1_AXIM1_SLOT1_STATUS_QUEUED_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_SLOT1_STATUS_QUEUED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT1_STATUS_QUEUED_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT1_STATUS_QUEUED_MASK) #define GTM_gtm_cls1_AXIM1_SLOT1_STATUS_STARTED_MASK (0x4U) #define GTM_gtm_cls1_AXIM1_SLOT1_STATUS_STARTED_SHIFT (2U) #define GTM_gtm_cls1_AXIM1_SLOT1_STATUS_STARTED_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_SLOT1_STATUS_STARTED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT1_STATUS_STARTED_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT1_STATUS_STARTED_MASK) #define GTM_gtm_cls1_AXIM1_SLOT1_STATUS_READY_MASK (0x8U) #define GTM_gtm_cls1_AXIM1_SLOT1_STATUS_READY_SHIFT (3U) #define GTM_gtm_cls1_AXIM1_SLOT1_STATUS_READY_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_SLOT1_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT1_STATUS_READY_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT1_STATUS_READY_MASK) #define GTM_gtm_cls1_AXIM1_SLOT1_STATUS_RESP_MASK (0x30U) #define GTM_gtm_cls1_AXIM1_SLOT1_STATUS_RESP_SHIFT (4U) #define GTM_gtm_cls1_AXIM1_SLOT1_STATUS_RESP_WIDTH (2U) #define GTM_gtm_cls1_AXIM1_SLOT1_STATUS_RESP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT1_STATUS_RESP_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT1_STATUS_RESP_MASK) /*! @} */ /*! @name AXIM1_SLOT2_ADDR_LOW - AXIM[i] slot[s] address bits 31:0 of AXI transaction. */ /*! @{ */ #define GTM_gtm_cls1_AXIM1_SLOT2_ADDR_LOW_AXI_ADDR_MASK (0xFFFFFFFFU) #define GTM_gtm_cls1_AXIM1_SLOT2_ADDR_LOW_AXI_ADDR_SHIFT (0U) #define GTM_gtm_cls1_AXIM1_SLOT2_ADDR_LOW_AXI_ADDR_WIDTH (32U) #define GTM_gtm_cls1_AXIM1_SLOT2_ADDR_LOW_AXI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT2_ADDR_LOW_AXI_ADDR_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT2_ADDR_LOW_AXI_ADDR_MASK) /*! @} */ /*! @name AXIM1_SLOT2_DATA_LOW - AXIM[i] slot[s] data bits 31:0 of AXI transaction. */ /*! @{ */ #define GTM_gtm_cls1_AXIM1_SLOT2_DATA_LOW_AXI_DATA_LOW_MASK (0xFFFFFFFFU) #define GTM_gtm_cls1_AXIM1_SLOT2_DATA_LOW_AXI_DATA_LOW_SHIFT (0U) #define GTM_gtm_cls1_AXIM1_SLOT2_DATA_LOW_AXI_DATA_LOW_WIDTH (32U) #define GTM_gtm_cls1_AXIM1_SLOT2_DATA_LOW_AXI_DATA_LOW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT2_DATA_LOW_AXI_DATA_LOW_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT2_DATA_LOW_AXI_DATA_LOW_MASK) /*! @} */ /*! @name AXIM1_SLOT2_CFG1 - AXIM[i] slot [s] configuration 1 */ /*! @{ */ #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_INCR_MASK (0xFU) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_INCR_SHIFT (0U) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_INCR_WIDTH (4U) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_INCR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT2_CFG1_INCR_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT2_CFG1_INCR_MASK) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AUTO_INCR_MASK (0x10U) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AUTO_INCR_SHIFT (4U) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AUTO_INCR_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AUTO_INCR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AUTO_INCR_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AUTO_INCR_MASK) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_PRIO_MASK (0x60U) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_PRIO_SHIFT (5U) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_PRIO_WIDTH (2U) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_PRIO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT2_CFG1_PRIO_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT2_CFG1_PRIO_MASK) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AXI_PROT_MASK (0x3800U) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AXI_PROT_SHIFT (11U) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AXI_PROT_WIDTH (3U) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AXI_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AXI_PROT_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AXI_PROT_MASK) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AXI_CACHE_MASK (0x3C000U) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AXI_CACHE_SHIFT (14U) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AXI_CACHE_WIDTH (4U) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AXI_CACHE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AXI_CACHE_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AXI_CACHE_MASK) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AXI_LOCK_MASK (0xC0000U) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AXI_LOCK_SHIFT (18U) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AXI_LOCK_WIDTH (2U) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AXI_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AXI_LOCK_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AXI_LOCK_MASK) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AXI_SIZE_MASK (0x1C00000U) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AXI_SIZE_SHIFT (22U) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AXI_SIZE_WIDTH (3U) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AXI_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AXI_SIZE_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AXI_SIZE_MASK) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AXI_RW_MASK (0x2000000U) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AXI_RW_SHIFT (25U) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AXI_RW_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AXI_RW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AXI_RW_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT2_CFG1_AXI_RW_MASK) /*! @} */ /*! @name AXIM1_SLOT2_CFG2 - AXIM[i] slot[s] configuration 2 */ /*! @{ */ #define GTM_gtm_cls1_AXIM1_SLOT2_CFG2_AXI_ID_MASK (0xFFFFU) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG2_AXI_ID_SHIFT (0U) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG2_AXI_ID_WIDTH (16U) #define GTM_gtm_cls1_AXIM1_SLOT2_CFG2_AXI_ID(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT2_CFG2_AXI_ID_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT2_CFG2_AXI_ID_MASK) /*! @} */ /*! @name AXIM1_SLOT2_STATUS - AXIM[i] slot[s] status */ /*! @{ */ #define GTM_gtm_cls1_AXIM1_SLOT2_STATUS_ALLOC_MASK (0x1U) #define GTM_gtm_cls1_AXIM1_SLOT2_STATUS_ALLOC_SHIFT (0U) #define GTM_gtm_cls1_AXIM1_SLOT2_STATUS_ALLOC_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_SLOT2_STATUS_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT2_STATUS_ALLOC_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT2_STATUS_ALLOC_MASK) #define GTM_gtm_cls1_AXIM1_SLOT2_STATUS_QUEUED_MASK (0x2U) #define GTM_gtm_cls1_AXIM1_SLOT2_STATUS_QUEUED_SHIFT (1U) #define GTM_gtm_cls1_AXIM1_SLOT2_STATUS_QUEUED_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_SLOT2_STATUS_QUEUED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT2_STATUS_QUEUED_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT2_STATUS_QUEUED_MASK) #define GTM_gtm_cls1_AXIM1_SLOT2_STATUS_STARTED_MASK (0x4U) #define GTM_gtm_cls1_AXIM1_SLOT2_STATUS_STARTED_SHIFT (2U) #define GTM_gtm_cls1_AXIM1_SLOT2_STATUS_STARTED_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_SLOT2_STATUS_STARTED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT2_STATUS_STARTED_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT2_STATUS_STARTED_MASK) #define GTM_gtm_cls1_AXIM1_SLOT2_STATUS_READY_MASK (0x8U) #define GTM_gtm_cls1_AXIM1_SLOT2_STATUS_READY_SHIFT (3U) #define GTM_gtm_cls1_AXIM1_SLOT2_STATUS_READY_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_SLOT2_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT2_STATUS_READY_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT2_STATUS_READY_MASK) #define GTM_gtm_cls1_AXIM1_SLOT2_STATUS_RESP_MASK (0x30U) #define GTM_gtm_cls1_AXIM1_SLOT2_STATUS_RESP_SHIFT (4U) #define GTM_gtm_cls1_AXIM1_SLOT2_STATUS_RESP_WIDTH (2U) #define GTM_gtm_cls1_AXIM1_SLOT2_STATUS_RESP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT2_STATUS_RESP_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT2_STATUS_RESP_MASK) /*! @} */ /*! @name AXIM1_SLOT3_ADDR_LOW - AXIM[i] slot[s] address bits 31:0 of AXI transaction. */ /*! @{ */ #define GTM_gtm_cls1_AXIM1_SLOT3_ADDR_LOW_AXI_ADDR_MASK (0xFFFFFFFFU) #define GTM_gtm_cls1_AXIM1_SLOT3_ADDR_LOW_AXI_ADDR_SHIFT (0U) #define GTM_gtm_cls1_AXIM1_SLOT3_ADDR_LOW_AXI_ADDR_WIDTH (32U) #define GTM_gtm_cls1_AXIM1_SLOT3_ADDR_LOW_AXI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT3_ADDR_LOW_AXI_ADDR_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT3_ADDR_LOW_AXI_ADDR_MASK) /*! @} */ /*! @name AXIM1_SLOT3_DATA_LOW - AXIM[i] slot[s] data bits 31:0 of AXI transaction. */ /*! @{ */ #define GTM_gtm_cls1_AXIM1_SLOT3_DATA_LOW_AXI_DATA_LOW_MASK (0xFFFFFFFFU) #define GTM_gtm_cls1_AXIM1_SLOT3_DATA_LOW_AXI_DATA_LOW_SHIFT (0U) #define GTM_gtm_cls1_AXIM1_SLOT3_DATA_LOW_AXI_DATA_LOW_WIDTH (32U) #define GTM_gtm_cls1_AXIM1_SLOT3_DATA_LOW_AXI_DATA_LOW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT3_DATA_LOW_AXI_DATA_LOW_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT3_DATA_LOW_AXI_DATA_LOW_MASK) /*! @} */ /*! @name AXIM1_SLOT3_CFG1 - AXIM[i] slot [s] configuration 1 */ /*! @{ */ #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_INCR_MASK (0xFU) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_INCR_SHIFT (0U) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_INCR_WIDTH (4U) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_INCR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT3_CFG1_INCR_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT3_CFG1_INCR_MASK) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AUTO_INCR_MASK (0x10U) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AUTO_INCR_SHIFT (4U) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AUTO_INCR_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AUTO_INCR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AUTO_INCR_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AUTO_INCR_MASK) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_PRIO_MASK (0x60U) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_PRIO_SHIFT (5U) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_PRIO_WIDTH (2U) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_PRIO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT3_CFG1_PRIO_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT3_CFG1_PRIO_MASK) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AXI_PROT_MASK (0x3800U) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AXI_PROT_SHIFT (11U) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AXI_PROT_WIDTH (3U) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AXI_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AXI_PROT_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AXI_PROT_MASK) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AXI_CACHE_MASK (0x3C000U) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AXI_CACHE_SHIFT (14U) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AXI_CACHE_WIDTH (4U) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AXI_CACHE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AXI_CACHE_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AXI_CACHE_MASK) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AXI_LOCK_MASK (0xC0000U) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AXI_LOCK_SHIFT (18U) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AXI_LOCK_WIDTH (2U) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AXI_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AXI_LOCK_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AXI_LOCK_MASK) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AXI_SIZE_MASK (0x1C00000U) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AXI_SIZE_SHIFT (22U) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AXI_SIZE_WIDTH (3U) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AXI_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AXI_SIZE_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AXI_SIZE_MASK) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AXI_RW_MASK (0x2000000U) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AXI_RW_SHIFT (25U) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AXI_RW_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AXI_RW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AXI_RW_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT3_CFG1_AXI_RW_MASK) /*! @} */ /*! @name AXIM1_SLOT3_CFG2 - AXIM[i] slot[s] configuration 2 */ /*! @{ */ #define GTM_gtm_cls1_AXIM1_SLOT3_CFG2_AXI_ID_MASK (0xFFFFU) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG2_AXI_ID_SHIFT (0U) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG2_AXI_ID_WIDTH (16U) #define GTM_gtm_cls1_AXIM1_SLOT3_CFG2_AXI_ID(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT3_CFG2_AXI_ID_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT3_CFG2_AXI_ID_MASK) /*! @} */ /*! @name AXIM1_SLOT3_STATUS - AXIM[i] slot[s] status */ /*! @{ */ #define GTM_gtm_cls1_AXIM1_SLOT3_STATUS_ALLOC_MASK (0x1U) #define GTM_gtm_cls1_AXIM1_SLOT3_STATUS_ALLOC_SHIFT (0U) #define GTM_gtm_cls1_AXIM1_SLOT3_STATUS_ALLOC_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_SLOT3_STATUS_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT3_STATUS_ALLOC_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT3_STATUS_ALLOC_MASK) #define GTM_gtm_cls1_AXIM1_SLOT3_STATUS_QUEUED_MASK (0x2U) #define GTM_gtm_cls1_AXIM1_SLOT3_STATUS_QUEUED_SHIFT (1U) #define GTM_gtm_cls1_AXIM1_SLOT3_STATUS_QUEUED_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_SLOT3_STATUS_QUEUED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT3_STATUS_QUEUED_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT3_STATUS_QUEUED_MASK) #define GTM_gtm_cls1_AXIM1_SLOT3_STATUS_STARTED_MASK (0x4U) #define GTM_gtm_cls1_AXIM1_SLOT3_STATUS_STARTED_SHIFT (2U) #define GTM_gtm_cls1_AXIM1_SLOT3_STATUS_STARTED_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_SLOT3_STATUS_STARTED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT3_STATUS_STARTED_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT3_STATUS_STARTED_MASK) #define GTM_gtm_cls1_AXIM1_SLOT3_STATUS_READY_MASK (0x8U) #define GTM_gtm_cls1_AXIM1_SLOT3_STATUS_READY_SHIFT (3U) #define GTM_gtm_cls1_AXIM1_SLOT3_STATUS_READY_WIDTH (1U) #define GTM_gtm_cls1_AXIM1_SLOT3_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT3_STATUS_READY_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT3_STATUS_READY_MASK) #define GTM_gtm_cls1_AXIM1_SLOT3_STATUS_RESP_MASK (0x30U) #define GTM_gtm_cls1_AXIM1_SLOT3_STATUS_RESP_SHIFT (4U) #define GTM_gtm_cls1_AXIM1_SLOT3_STATUS_RESP_WIDTH (2U) #define GTM_gtm_cls1_AXIM1_SLOT3_STATUS_RESP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_AXIM1_SLOT3_STATUS_RESP_SHIFT)) & GTM_gtm_cls1_AXIM1_SLOT3_STATUS_RESP_MASK) /*! @} */ /*! @name MCS1_MEM - MCS[i] memory region */ /*! @{ */ #define GTM_gtm_cls1_MCS1_MEM_DATA_MASK (0xFFFFFFFFU) #define GTM_gtm_cls1_MCS1_MEM_DATA_SHIFT (0U) #define GTM_gtm_cls1_MCS1_MEM_DATA_WIDTH (32U) #define GTM_gtm_cls1_MCS1_MEM_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls1_MCS1_MEM_DATA_SHIFT)) & GTM_gtm_cls1_MCS1_MEM_DATA_MASK) /*! @} */ /*! * @} */ /* end of group GTM_gtm_cls1_Register_Masks */ /*! * @} */ /* end of group GTM_gtm_cls1_Peripheral_Access_Layer */ #endif /* #if !defined(S32Z2_GTM_gtm_cls1_H_) */