/* * Copyright 1997-2016 Freescale Semiconductor, Inc. * Copyright 2016-2024 NXP * * SPDX-License-Identifier: BSD-3-Clause */ /*! * @file S32Z2_GTM_gtm_cls0.h * @version 2.3 * @date 2024-05-03 * @brief Peripheral Access Layer for S32Z2_GTM_gtm_cls0 * * This file contains register definitions and macros for easy access to their * bit fields. * * This file assumes LITTLE endian system. */ /** * @page misra_violations MISRA-C:2012 violations * * @section [global] * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced * The SoC header defines typedef for all modules. * * @section [global] * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced * The SoC header defines macros for all modules and registers. * * @section [global] * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro * These are generated macros used for accessing the bit-fields from registers. * * @section [global] * Violates MISRA 2012 Required Rule 5.1, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.2, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.4, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.5, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler * This type qualifier is needed to ensure correct I/O access and addressing. */ /* Prevention from multiple including the same memory map */ #if !defined(S32Z2_GTM_gtm_cls0_H_) /* Check if memory map has not been already included */ #define S32Z2_GTM_gtm_cls0_H_ #include "S32Z2_COMMON.h" /* ---------------------------------------------------------------------------- -- GTM_gtm_cls0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup GTM_gtm_cls0_Peripheral_Access_Layer GTM_gtm_cls0 Peripheral Access Layer * @{ */ /** GTM_gtm_cls0 - Size of Registers Arrays */ #define GTM_gtm_cls0_CDTM0_DTM4_CH4_DTV_COUNT 4u #define GTM_gtm_cls0_CDTM0_DTM5_CH4_DTV_COUNT 4u #define GTM_gtm_cls0_FIFO0_MEMORY_COUNT 1024u #define GTM_gtm_cls0_DPLL_RR2_COUNT 4096u #define GTM_gtm_cls0_MCS0_MEM_COUNT 6144u /** GTM_gtm_cls0 - Register Layout Typedef */ typedef struct { __I uint32_t GTM_REV; /**< GTM version control register, offset: 0x0 */ __IO uint32_t GTM_RST; /**< GTM global reset register, offset: 0x4 */ __IO uint32_t GTM_CTRL; /**< GTM global control register, offset: 0x8 */ __IO uint32_t GTM_CFG; /**< GTM configuration register, offset: 0xC */ __I uint32_t GTM_AEI_ADDR_XPT; /**< GTM AEI timeout exception address register, offset: 0x10 */ __I uint32_t GTM_AEI_STA_XPT; /**< GTM AEI non zero status register, offset: 0x14 */ __IO uint32_t GTM_IRQ_NOTIFY; /**< GTM Interrupt notification register, offset: 0x18 */ __IO uint32_t GTM_IRQ_EN; /**< GTM interrupt enable register, offset: 0x1C */ __IO uint32_t GTM_EIRQ_EN; /**< GTM error interrupt enable register, offset: 0x20 */ __IO uint32_t GTM_IRQ_FORCINT; /**< GTM Software interrupt generation register, offset: 0x24 */ __IO uint32_t GTM_IRQ_MODE; /**< GTM top level interrupts mode selection, offset: 0x28 */ __IO uint32_t GTM_CLS_CLK_CFG; /**< GTM Cluster Clock Configuration, offset: 0x2C */ __IO uint32_t GTM_ARU_COM_DIS; /**< GTM ARU communication disable, offset: 0x30 */ uint8_t RESERVED_0[12]; __IO uint32_t BRIDGE_MODE; /**< GTM AEI bridge mode register, offset: 0x40 */ __I uint32_t BRIDGE_PTR1; /**< GTM AEI bridge pointer 1 register, offset: 0x44 */ __I uint32_t BRIDGE_PTR2; /**< GTM AEI bridge pointer 2 register, offset: 0x48 */ __IO uint32_t MCS_AEM_DIS; /**< GTM MCS master port disable register, offset: 0x4C */ uint8_t RESERVED_1[48]; __IO uint32_t CMU_CLK_EN; /**< CMU clock enable, offset: 0x80 */ __IO uint32_t CMU_GCLK_NUM; /**< The numerator for CMU global clock resolution generator, offset: 0x84 */ __IO uint32_t CMU_GCLK_DEN; /**< The denominator for CMU global clock resolution generator, offset: 0x88 */ __IO uint32_t CMU_CLK_0_CTRL; /**< CMU control for clock resolution generator [x], offset: 0x8C */ __IO uint32_t CMU_CLK_1_CTRL; /**< CMU control for clock resolution generator [x], offset: 0x90 */ __IO uint32_t CMU_CLK_2_CTRL; /**< CMU control for clock resolution generator [x], offset: 0x94 */ __IO uint32_t CMU_CLK_3_CTRL; /**< CMU control for clock resolution generator [x], offset: 0x98 */ __IO uint32_t CMU_CLK_4_CTRL; /**< CMU control for clock resolution generator [x], offset: 0x9C */ __IO uint32_t CMU_CLK_5_CTRL; /**< CMU control for clock resolution generator [x], offset: 0xA0 */ __IO uint32_t CMU_CLK_6_CTRL; /**< CMU control for clock resolution generator 6, offset: 0xA4 */ __IO uint32_t CMU_CLK_7_CTRL; /**< CMU control for clock resolution generator 7, offset: 0xA8 */ __IO uint32_t CMU_ECLK_0_NUM; /**< The numerator for the external clock resolution generator [z], offset: 0xAC */ __IO uint32_t CMU_ECLK_0_DEN; /**< The denominator for the external clock resolution generator [z], offset: 0xB0 */ __IO uint32_t CMU_ECLK_1_NUM; /**< The numerator for the external clock resolution generator [z], offset: 0xB4 */ __IO uint32_t CMU_ECLK_1_DEN; /**< The denominator for the external clock resolution generator [z], offset: 0xB8 */ __IO uint32_t CMU_ECLK_2_NUM; /**< The numerator for the external clock resolution generator [z], offset: 0xBC */ __IO uint32_t CMU_ECLK_2_DEN; /**< The denominator for the external clock resolution generator [z], offset: 0xC0 */ __IO uint32_t CMU_FXCLK_CTRL; /**< CMU control for selection of FCR subblock input, offset: 0xC4 */ __IO uint32_t CMU_GLB_CTRL; /**< CMU synchronizing ARU and clock source, offset: 0xC8 */ __IO uint32_t CMU_CLK_CTRL; /**< CMU control for clock resolution generator, offset: 0xCC */ uint8_t RESERVED_2[48]; __IO uint32_t TBU_CHEN; /**< TBU global channel enable, offset: 0x100 */ __IO uint32_t TBU_CH0_CTRL; /**< TBU channel 0 control, offset: 0x104 */ __IO uint32_t TBU_CH0_BASE; /**< TBU channel 0 base, offset: 0x108 */ __IO uint32_t TBU_CH1_CTRL; /**< TBU channel 1 control, offset: 0x10C */ __IO uint32_t TBU_CH1_BASE; /**< TBU channel [x] base, offset: 0x110 */ __IO uint32_t TBU_CH2_CTRL; /**< TBU channel 2 control, offset: 0x114 */ __IO uint32_t TBU_CH2_BASE; /**< TBU channel [x] base, offset: 0x118 */ __IO uint32_t TBU_CH3_CTRL; /**< TBU channel 3 control, offset: 0x11C */ __IO uint32_t TBU_CH3_BASE; /**< TBU channel 3 base, offset: 0x120 */ __IO uint32_t TBU_CH3_BASE_MARK; /**< TBU channel 3 modulo value, offset: 0x124 */ __I uint32_t TBU_CH3_BASE_CAPTURE; /**< TBU channel 3 base captured, offset: 0x128 */ uint8_t RESERVED_3[84]; __IO uint32_t ARU_ACCESS; /**< ARU access register, offset: 0x180 */ __IO uint32_t ARU_DATA_H; /**< ARU access register upper data word, offset: 0x184 */ __IO uint32_t ARU_DATA_L; /**< ARU access register lower data word, offset: 0x188 */ __IO uint32_t ARU_DBG_ACCESS0; /**< ARU debug access channel 0, offset: 0x18C */ __I uint32_t ARU_DBG_DATA0_H; /**< ARU debug access 0 transfer register upper data word, offset: 0x190 */ __I uint32_t ARU_DBG_DATA0_L; /**< ARU debug access 0 transfer register lower data word, offset: 0x194 */ __IO uint32_t ARU_DBG_ACCESS1; /**< ARU debug access channel 0, offset: 0x198 */ __I uint32_t ARU_DBG_DATA1_H; /**< ARU debug access 1 transfer register upper data word, offset: 0x19C */ __I uint32_t ARU_DBG_DATA1_L; /**< ARU debug access 1 transfer register lower data word, offset: 0x1A0 */ __IO uint32_t ARU_IRQ_NOTIFY; /**< ARU interrupt notification register, offset: 0x1A4 */ __IO uint32_t ARU_IRQ_EN; /**< ARU interrupt enable register, offset: 0x1A8 */ __IO uint32_t ARU_IRQ_FORCINT; /**< ARU force interrupt register, offset: 0x1AC */ __IO uint32_t ARU_IRQ_MODE; /**< ARU interrupt mode register, offset: 0x1B0 */ __IO uint32_t ARU_CADDR_END; /**< ARU caddr counter end value, offset: 0x1B4 */ uint8_t RESERVED_4[4]; __IO uint32_t ARU_CTRL; /**< ARU enable dynamic routing, offset: 0x1BC */ __IO uint32_t ARU_0_DYN_CTRL; /**< ARU [g] dynamic routing control register, offset: 0x1C0 */ __IO uint32_t ARU_1_DYN_CTRL; /**< ARU [g] dynamic routing control register, offset: 0x1C4 */ __IO uint32_t ARU_0_DYN_ROUTE_LOW; /**< ARU [g] lower bits of DYN_ROUTE register, offset: 0x1C8 */ __IO uint32_t ARU_1_DYN_ROUTE_LOW; /**< ARU [g] lower bits of DYN_ROUTE register, offset: 0x1CC */ __IO uint32_t ARU_0_DYN_ROUTE_HIGH; /**< ARU [g] higher bits of DYN_ROUTE register, offset: 0x1D0 */ __IO uint32_t ARU_1_DYN_ROUTE_HIGH; /**< ARU [g] higher bits of DYN_ROUTE register, offset: 0x1D4 */ __IO uint32_t ARU_0_DYN_ROUTE_SR_LOW; /**< ARU [g] shadow register of DYN_ROUTE register lower bits, offset: 0x1D8 */ __IO uint32_t ARU_1_DYN_ROUTE_SR_LOW; /**< ARU [g] shadow register of DYN_ROUTE register lower bits, offset: 0x1DC */ __IO uint32_t ARU_0_DYN_ROUTE_SR_HIGH; /**< ARU [g] shadow register of DYN_ROUTE register higher bits, offset: 0x1E0 */ __IO uint32_t ARU_1_DYN_ROUTE_SR_HIGH; /**< ARU [g] shadow register of DYN_ROUTE register higher bits, offset: 0x1E4 */ __IO uint32_t ARU_0_DYN_RDADDR; /**< ARU [g] master ID for dynamic routing, offset: 0x1E8 */ __IO uint32_t ARU_1_DYN_RDADDR; /**< ARU [g] master ID for dynamic routing, offset: 0x1EC */ uint8_t RESERVED_5[12]; __I uint32_t ARU_CADDR; /**< ARU caddr counter value, offset: 0x1FC */ __IO uint32_t BRC_SRC_0_ADDR; /**< BRC read address for input channel [x], offset: 0x200 */ __IO uint32_t BRC_SRC_0_DEST; /**< BRC destination channels for input channel [x], offset: 0x204 */ __IO uint32_t BRC_SRC_1_ADDR; /**< BRC read address for input channel [x], offset: 0x208 */ __IO uint32_t BRC_SRC_1_DEST; /**< BRC destination channels for input channel [x], offset: 0x20C */ __IO uint32_t BRC_SRC_2_ADDR; /**< BRC read address for input channel [x], offset: 0x210 */ __IO uint32_t BRC_SRC_2_DEST; /**< BRC destination channels for input channel [x], offset: 0x214 */ __IO uint32_t BRC_SRC_3_ADDR; /**< BRC read address for input channel [x], offset: 0x218 */ __IO uint32_t BRC_SRC_3_DEST; /**< BRC destination channels for input channel [x], offset: 0x21C */ __IO uint32_t BRC_SRC_4_ADDR; /**< BRC read address for input channel [x], offset: 0x220 */ __IO uint32_t BRC_SRC_4_DEST; /**< BRC destination channels for input channel [x], offset: 0x224 */ __IO uint32_t BRC_SRC_5_ADDR; /**< BRC read address for input channel [x], offset: 0x228 */ __IO uint32_t BRC_SRC_5_DEST; /**< BRC destination channels for input channel [x], offset: 0x22C */ __IO uint32_t BRC_SRC_6_ADDR; /**< BRC read address for input channel [x], offset: 0x230 */ __IO uint32_t BRC_SRC_6_DEST; /**< BRC destination channels for input channel [x], offset: 0x234 */ __IO uint32_t BRC_SRC_7_ADDR; /**< BRC read address for input channel [x], offset: 0x238 */ __IO uint32_t BRC_SRC_7_DEST; /**< BRC destination channels for input channel [x], offset: 0x23C */ __IO uint32_t BRC_SRC_8_ADDR; /**< BRC read address for input channel [x], offset: 0x240 */ __IO uint32_t BRC_SRC_8_DEST; /**< BRC destination channels for input channel [x], offset: 0x244 */ __IO uint32_t BRC_SRC_9_ADDR; /**< BRC read address for input channel [x], offset: 0x248 */ __IO uint32_t BRC_SRC_9_DEST; /**< BRC destination channels for input channel [x], offset: 0x24C */ __IO uint32_t BRC_SRC_10_ADDR; /**< BRC read address for input channel [x], offset: 0x250 */ __IO uint32_t BRC_SRC_10_DEST; /**< BRC destination channels for input channel [x], offset: 0x254 */ __IO uint32_t BRC_SRC_11_ADDR; /**< BRC read address for input channel [x], offset: 0x258 */ __IO uint32_t BRC_SRC_11_DEST; /**< BRC destination channels for input channel [x], offset: 0x25C */ __IO uint32_t BRC_IRQ_NOTIFY; /**< BRC interrupt notification register, offset: 0x260 */ __IO uint32_t BRC_IRQ_EN; /**< BRC interrupt enable register, offset: 0x264 */ __IO uint32_t BRC_IRQ_FORCINT; /**< BRC force interrupt register, offset: 0x268 */ __IO uint32_t BRC_IRQ_MODE; /**< BRC interrupt mode configuration register, offset: 0x26C */ __IO uint32_t BRC_RST; /**< BRC software reset register, offset: 0x270 */ __IO uint32_t BRC_EIRQ_EN; /**< BRC error interrupt enable register, offset: 0x274 */ uint8_t RESERVED_6[392]; __I uint32_t ICM_IRQG_0; /**< ICM Interrupt group register covering infrastructural and safety components (ARU, BRC, AEI, PSM0, PSM1, MAP, CMP, SPE), offset: 0x400 */ __I uint32_t ICM_IRQG_1; /**< ICM Interrupt group register covering DPLL, offset: 0x404 */ __I uint32_t ICM_IRQG_2; /**< ICM Interrupt group register covering TIM0, TIM1, TIM2, TIM3, offset: 0x408 */ uint8_t RESERVED_7[4]; __I uint32_t ICM_IRQG_4; /**< ICM Interrupt group register covering MCS0 to MCS3 submodules, offset: 0x410 */ uint8_t RESERVED_8[28]; __I uint32_t ICM_IRQG_MEI; /**< ICM Interrupt group register for module error interrupt information, offset: 0x430 */ __I uint32_t ICM_IRQG_CEI0; /**< ICM Interrupt group register 0 for channel error interrupt information, offset: 0x434 */ __I uint32_t ICM_IRQG_CEI1; /**< ICM Interrupt group register 1 for channel error interrupt information, offset: 0x438 */ uint8_t RESERVED_9[4]; __I uint32_t ICM_IRQG_CEI3; /**< ICM Interrupt group register 3 for channel error interrupt information, offset: 0x440 */ uint8_t RESERVED_10[32]; __I uint32_t ICM_IRQG_MCS0_CEI; /**< ICM Interrupt group MCS[j] for Channel Error Interrupt information, offset: 0x464 */ __I uint32_t ICM_IRQG_MCS1_CEI; /**< ICM Interrupt group MCS[j] for Channel Error Interrupt information, offset: 0x468 */ __I uint32_t ICM_IRQG_MCS2_CEI; /**< ICM Interrupt group MCS[j] for Channel Error Interrupt information, offset: 0x46C */ __I uint32_t ICM_IRQG_MCS3_CEI; /**< ICM Interrupt group MCS[j] for Channel Error Interrupt information, offset: 0x470 */ uint8_t RESERVED_11[48]; __I uint32_t ICM_IRQG_PSM_0_CEI; /**< ICM Interrupt group PSM 0 for Channel Error Interrupt information of FIFO0, FIFO1, FIFO2, offset: 0x4A4 */ uint8_t RESERVED_12[12]; __I uint32_t ICM_IRQG_SPE_CEI; /**< ICM Interrupt group SPE for module Error Interrupt information, offset: 0x4B4 */ uint8_t RESERVED_13[88]; __I uint32_t ICM_IRQG_CLS_0_MEI; /**< ICM Interrupt group for module Error Interrupt information for each TIM[j], MCS[j], SPE[j], FIFO[j] (j=4*[g]+k, k∈{0, ... ,3}), offset: 0x510 */ uint8_t RESERVED_14[12]; __I uint32_t ICM_IRQG_MCS0_CI; /**< ICM Interrupt group MCS[j] for Channel Interrupt information, offset: 0x520 */ __I uint32_t ICM_IRQG_MCS1_CI; /**< ICM Interrupt group MCS[j] for Channel Interrupt information, offset: 0x524 */ __I uint32_t ICM_IRQG_MCS2_CI; /**< ICM Interrupt group MCS[j] for Channel Interrupt information, offset: 0x528 */ __I uint32_t ICM_IRQG_MCS3_CI; /**< ICM Interrupt group MCS[j] for Channel Interrupt information, offset: 0x52C */ uint8_t RESERVED_15[48]; __I uint32_t ICM_IRQG_PSM_0_CI; /**< ICM Interrupt group PSM 0 for Channel Interrupt information of FIFO0, FIFO1, FIFO2, offset: 0x560 */ uint8_t RESERVED_16[12]; __I uint32_t ICM_IRQG_SPE_CI; /**< ICM Interrupt group SPE for module Interrupt information, offset: 0x570 */ uint8_t RESERVED_17[28]; __I uint32_t ICM_IRQG_ATOM_0_CI; /**< ICM Interrupt group ATOM [g] for Channel Interrupt information of ATOM[j] (m=4*[g]+(0..3)), offset: 0x590 */ uint8_t RESERVED_18[12]; __I uint32_t ICM_IRQG_TOM_0_CI; /**< ICM Interrupt group TOM [g] for Channel Interrupt information of TOMm ([j]=2*[g]+(0..1)), offset: 0x5A0 */ uint8_t RESERVED_19[156]; __IO uint32_t MAP_CTRL; /**< MAP Control register, offset: 0x640 */ uint8_t RESERVED_20[444]; __IO uint32_t TIM0_CH0_GPR0; /**< TIM[i] channel [x] general purpose 0 register, offset: 0x800 */ __IO uint32_t TIM0_CH0_GPR1; /**< TIM[i] channel [x] general purpose 0 register, offset: 0x804 */ __I uint32_t TIM0_CH0_CNT; /**< TIM[i] channel [x] SMU counter register, offset: 0x808 */ __I uint32_t TIM0_CH0_ECNT; /**< TIM[i] channel [x] SMU edge counter register, offset: 0x80C */ __IO uint32_t TIM0_CH0_CNTS; /**< TIM[i] channel [x] SMU shadow counter register, offset: 0x810 */ __IO uint32_t TIM0_CH0_TDUC; /**< TIM[i] channel [x] TDU counter register, offset: 0x814 */ __IO uint32_t TIM0_CH0_TDUV; /**< TIM[i] channel [x] TDU control register, offset: 0x818 */ __IO uint32_t TIM0_CH0_FLT_RE; /**< TIM[i] channel [x] filter parameter 0 register, offset: 0x81C */ __IO uint32_t TIM0_CH0_FLT_FE; /**< TIM[i] channel [x] filter parameter 1 register, offset: 0x820 */ __IO uint32_t TIM0_CH0_CTRL; /**< TIM[i] channel [x] control register, offset: 0x824 */ __IO uint32_t TIM0_CH0_ECTRL; /**< TIM[i] channel [x] extended control register, offset: 0x828 */ __IO uint32_t TIM0_CH0_IRQ_NOTIFY; /**< TIM[i] channel [x] interrupt notification register, offset: 0x82C */ __IO uint32_t TIM0_CH0_IRQ_EN; /**< TIM[i] channel [x] interrupt enable register, offset: 0x830 */ __IO uint32_t TIM0_CH0_IRQ_FORCINT; /**< TIM[i] channel [x] force interrupt register, offset: 0x834 */ __IO uint32_t TIM0_CH0_IRQ_MODE; /**< TIM[i] channel [x] interrupt mode configuration register, offset: 0x838 */ __IO uint32_t TIM0_CH0_EIRQ_EN; /**< TIM[i] channel [x] error interrupt enable register, offset: 0x83C */ uint8_t RESERVED_21[64]; __IO uint32_t TIM0_CH1_GPR0; /**< TIM[i] channel [x] general purpose 0 register, offset: 0x880 */ __IO uint32_t TIM0_CH1_GPR1; /**< TIM[i] channel [x] general purpose 0 register, offset: 0x884 */ __I uint32_t TIM0_CH1_CNT; /**< TIM[i] channel [x] SMU counter register, offset: 0x888 */ __I uint32_t TIM0_CH1_ECNT; /**< TIM[i] channel [x] SMU edge counter register, offset: 0x88C */ __IO uint32_t TIM0_CH1_CNTS; /**< TIM[i] channel [x] SMU shadow counter register, offset: 0x890 */ __IO uint32_t TIM0_CH1_TDUC; /**< TIM[i] channel [x] TDU counter register, offset: 0x894 */ __IO uint32_t TIM0_CH1_TDUV; /**< TIM[i] channel [x] TDU control register, offset: 0x898 */ __IO uint32_t TIM0_CH1_FLT_RE; /**< TIM[i] channel [x] filter parameter 0 register, offset: 0x89C */ __IO uint32_t TIM0_CH1_FLT_FE; /**< TIM[i] channel [x] filter parameter 1 register, offset: 0x8A0 */ __IO uint32_t TIM0_CH1_CTRL; /**< TIM[i] channel [x] control register, offset: 0x8A4 */ __IO uint32_t TIM0_CH1_ECTRL; /**< TIM[i] channel [x] extended control register, offset: 0x8A8 */ __IO uint32_t TIM0_CH1_IRQ_NOTIFY; /**< TIM[i] channel [x] interrupt notification register, offset: 0x8AC */ __IO uint32_t TIM0_CH1_IRQ_EN; /**< TIM[i] channel [x] interrupt enable register, offset: 0x8B0 */ __IO uint32_t TIM0_CH1_IRQ_FORCINT; /**< TIM[i] channel [x] force interrupt register, offset: 0x8B4 */ __IO uint32_t TIM0_CH1_IRQ_MODE; /**< TIM[i] channel [x] interrupt mode configuration register, offset: 0x8B8 */ __IO uint32_t TIM0_CH1_EIRQ_EN; /**< TIM[i] channel [x] error interrupt enable register, offset: 0x8BC */ uint8_t RESERVED_22[64]; __IO uint32_t TIM0_CH2_GPR0; /**< TIM[i] channel [x] general purpose 0 register, offset: 0x900 */ __IO uint32_t TIM0_CH2_GPR1; /**< TIM[i] channel [x] general purpose 0 register, offset: 0x904 */ __I uint32_t TIM0_CH2_CNT; /**< TIM[i] channel [x] SMU counter register, offset: 0x908 */ __I uint32_t TIM0_CH2_ECNT; /**< TIM[i] channel [x] SMU edge counter register, offset: 0x90C */ __IO uint32_t TIM0_CH2_CNTS; /**< TIM[i] channel [x] SMU shadow counter register, offset: 0x910 */ __IO uint32_t TIM0_CH2_TDUC; /**< TIM[i] channel [x] TDU counter register, offset: 0x914 */ __IO uint32_t TIM0_CH2_TDUV; /**< TIM[i] channel [x] TDU control register, offset: 0x918 */ __IO uint32_t TIM0_CH2_FLT_RE; /**< TIM[i] channel [x] filter parameter 0 register, offset: 0x91C */ __IO uint32_t TIM0_CH2_FLT_FE; /**< TIM[i] channel [x] filter parameter 1 register, offset: 0x920 */ __IO uint32_t TIM0_CH2_CTRL; /**< TIM[i] channel [x] control register, offset: 0x924 */ __IO uint32_t TIM0_CH2_ECTRL; /**< TIM[i] channel [x] extended control register, offset: 0x928 */ __IO uint32_t TIM0_CH2_IRQ_NOTIFY; /**< TIM[i] channel [x] interrupt notification register, offset: 0x92C */ __IO uint32_t TIM0_CH2_IRQ_EN; /**< TIM[i] channel [x] interrupt enable register, offset: 0x930 */ __IO uint32_t TIM0_CH2_IRQ_FORCINT; /**< TIM[i] channel [x] force interrupt register, offset: 0x934 */ __IO uint32_t TIM0_CH2_IRQ_MODE; /**< TIM[i] channel [x] interrupt mode configuration register, offset: 0x938 */ __IO uint32_t TIM0_CH2_EIRQ_EN; /**< TIM[i] channel [x] error interrupt enable register, offset: 0x93C */ uint8_t RESERVED_23[64]; __IO uint32_t TIM0_CH3_GPR0; /**< TIM[i] channel [x] general purpose 0 register, offset: 0x980 */ __IO uint32_t TIM0_CH3_GPR1; /**< TIM[i] channel [x] general purpose 0 register, offset: 0x984 */ __I uint32_t TIM0_CH3_CNT; /**< TIM[i] channel [x] SMU counter register, offset: 0x988 */ __I uint32_t TIM0_CH3_ECNT; /**< TIM[i] channel [x] SMU edge counter register, offset: 0x98C */ __IO uint32_t TIM0_CH3_CNTS; /**< TIM[i] channel [x] SMU shadow counter register, offset: 0x990 */ __IO uint32_t TIM0_CH3_TDUC; /**< TIM[i] channel [x] TDU counter register, offset: 0x994 */ __IO uint32_t TIM0_CH3_TDUV; /**< TIM[i] channel [x] TDU control register, offset: 0x998 */ __IO uint32_t TIM0_CH3_FLT_RE; /**< TIM[i] channel [x] filter parameter 0 register, offset: 0x99C */ __IO uint32_t TIM0_CH3_FLT_FE; /**< TIM[i] channel [x] filter parameter 1 register, offset: 0x9A0 */ __IO uint32_t TIM0_CH3_CTRL; /**< TIM[i] channel [x] control register, offset: 0x9A4 */ __IO uint32_t TIM0_CH3_ECTRL; /**< TIM[i] channel [x] extended control register, offset: 0x9A8 */ __IO uint32_t TIM0_CH3_IRQ_NOTIFY; /**< TIM[i] channel [x] interrupt notification register, offset: 0x9AC */ __IO uint32_t TIM0_CH3_IRQ_EN; /**< TIM[i] channel [x] interrupt enable register, offset: 0x9B0 */ __IO uint32_t TIM0_CH3_IRQ_FORCINT; /**< TIM[i] channel [x] force interrupt register, offset: 0x9B4 */ __IO uint32_t TIM0_CH3_IRQ_MODE; /**< TIM[i] channel [x] interrupt mode configuration register, offset: 0x9B8 */ __IO uint32_t TIM0_CH3_EIRQ_EN; /**< TIM[i] channel [x] error interrupt enable register, offset: 0x9BC */ uint8_t RESERVED_24[64]; __IO uint32_t TIM0_CH4_GPR0; /**< TIM[i] channel [x] general purpose 0 register, offset: 0xA00 */ __IO uint32_t TIM0_CH4_GPR1; /**< TIM[i] channel [x] general purpose 0 register, offset: 0xA04 */ __I uint32_t TIM0_CH4_CNT; /**< TIM[i] channel [x] SMU counter register, offset: 0xA08 */ __I uint32_t TIM0_CH4_ECNT; /**< TIM[i] channel [x] SMU edge counter register, offset: 0xA0C */ __IO uint32_t TIM0_CH4_CNTS; /**< TIM[i] channel [x] SMU shadow counter register, offset: 0xA10 */ __IO uint32_t TIM0_CH4_TDUC; /**< TIM[i] channel [x] TDU counter register, offset: 0xA14 */ __IO uint32_t TIM0_CH4_TDUV; /**< TIM[i] channel [x] TDU control register, offset: 0xA18 */ __IO uint32_t TIM0_CH4_FLT_RE; /**< TIM[i] channel [x] filter parameter 0 register, offset: 0xA1C */ __IO uint32_t TIM0_CH4_FLT_FE; /**< TIM[i] channel [x] filter parameter 1 register, offset: 0xA20 */ __IO uint32_t TIM0_CH4_CTRL; /**< TIM[i] channel [x] control register, offset: 0xA24 */ __IO uint32_t TIM0_CH4_ECTRL; /**< TIM[i] channel [x] extended control register, offset: 0xA28 */ __IO uint32_t TIM0_CH4_IRQ_NOTIFY; /**< TIM[i] channel [x] interrupt notification register, offset: 0xA2C */ __IO uint32_t TIM0_CH4_IRQ_EN; /**< TIM[i] channel [x] interrupt enable register, offset: 0xA30 */ __IO uint32_t TIM0_CH4_IRQ_FORCINT; /**< TIM[i] channel [x] force interrupt register, offset: 0xA34 */ __IO uint32_t TIM0_CH4_IRQ_MODE; /**< TIM[i] channel [x] interrupt mode configuration register, offset: 0xA38 */ __IO uint32_t TIM0_CH4_EIRQ_EN; /**< TIM[i] channel [x] error interrupt enable register, offset: 0xA3C */ uint8_t RESERVED_25[64]; __IO uint32_t TIM0_CH5_GPR0; /**< TIM[i] channel [x] general purpose 0 register, offset: 0xA80 */ __IO uint32_t TIM0_CH5_GPR1; /**< TIM[i] channel [x] general purpose 0 register, offset: 0xA84 */ __I uint32_t TIM0_CH5_CNT; /**< TIM[i] channel [x] SMU counter register, offset: 0xA88 */ __I uint32_t TIM0_CH5_ECNT; /**< TIM[i] channel [x] SMU edge counter register, offset: 0xA8C */ __IO uint32_t TIM0_CH5_CNTS; /**< TIM[i] channel [x] SMU shadow counter register, offset: 0xA90 */ __IO uint32_t TIM0_CH5_TDUC; /**< TIM[i] channel [x] TDU counter register, offset: 0xA94 */ __IO uint32_t TIM0_CH5_TDUV; /**< TIM[i] channel [x] TDU control register, offset: 0xA98 */ __IO uint32_t TIM0_CH5_FLT_RE; /**< TIM[i] channel [x] filter parameter 0 register, offset: 0xA9C */ __IO uint32_t TIM0_CH5_FLT_FE; /**< TIM[i] channel [x] filter parameter 1 register, offset: 0xAA0 */ __IO uint32_t TIM0_CH5_CTRL; /**< TIM[i] channel [x] control register, offset: 0xAA4 */ __IO uint32_t TIM0_CH5_ECTRL; /**< TIM[i] channel [x] extended control register, offset: 0xAA8 */ __IO uint32_t TIM0_CH5_IRQ_NOTIFY; /**< TIM[i] channel [x] interrupt notification register, offset: 0xAAC */ __IO uint32_t TIM0_CH5_IRQ_EN; /**< TIM[i] channel [x] interrupt enable register, offset: 0xAB0 */ __IO uint32_t TIM0_CH5_IRQ_FORCINT; /**< TIM[i] channel [x] force interrupt register, offset: 0xAB4 */ __IO uint32_t TIM0_CH5_IRQ_MODE; /**< TIM[i] channel [x] interrupt mode configuration register, offset: 0xAB8 */ __IO uint32_t TIM0_CH5_EIRQ_EN; /**< TIM[i] channel [x] error interrupt enable register, offset: 0xABC */ uint8_t RESERVED_26[64]; __IO uint32_t TIM0_CH6_GPR0; /**< TIM[i] channel [x] general purpose 0 register, offset: 0xB00 */ __IO uint32_t TIM0_CH6_GPR1; /**< TIM[i] channel [x] general purpose 0 register, offset: 0xB04 */ __I uint32_t TIM0_CH6_CNT; /**< TIM[i] channel [x] SMU counter register, offset: 0xB08 */ __I uint32_t TIM0_CH6_ECNT; /**< TIM[i] channel [x] SMU edge counter register, offset: 0xB0C */ __IO uint32_t TIM0_CH6_CNTS; /**< TIM[i] channel [x] SMU shadow counter register, offset: 0xB10 */ __IO uint32_t TIM0_CH6_TDUC; /**< TIM[i] channel [x] TDU counter register, offset: 0xB14 */ __IO uint32_t TIM0_CH6_TDUV; /**< TIM[i] channel [x] TDU control register, offset: 0xB18 */ __IO uint32_t TIM0_CH6_FLT_RE; /**< TIM[i] channel [x] filter parameter 0 register, offset: 0xB1C */ __IO uint32_t TIM0_CH6_FLT_FE; /**< TIM[i] channel [x] filter parameter 1 register, offset: 0xB20 */ __IO uint32_t TIM0_CH6_CTRL; /**< TIM[i] channel [x] control register, offset: 0xB24 */ __IO uint32_t TIM0_CH6_ECTRL; /**< TIM[i] channel [x] extended control register, offset: 0xB28 */ __IO uint32_t TIM0_CH6_IRQ_NOTIFY; /**< TIM[i] channel [x] interrupt notification register, offset: 0xB2C */ __IO uint32_t TIM0_CH6_IRQ_EN; /**< TIM[i] channel [x] interrupt enable register, offset: 0xB30 */ __IO uint32_t TIM0_CH6_IRQ_FORCINT; /**< TIM[i] channel [x] force interrupt register, offset: 0xB34 */ __IO uint32_t TIM0_CH6_IRQ_MODE; /**< TIM[i] channel [x] interrupt mode configuration register, offset: 0xB38 */ __IO uint32_t TIM0_CH6_EIRQ_EN; /**< TIM[i] channel [x] error interrupt enable register, offset: 0xB3C */ uint8_t RESERVED_27[64]; __IO uint32_t TIM0_CH7_GPR0; /**< TIM[i] channel [x] general purpose 0 register, offset: 0xB80 */ __IO uint32_t TIM0_CH7_GPR1; /**< TIM[i] channel [x] general purpose 0 register, offset: 0xB84 */ __I uint32_t TIM0_CH7_CNT; /**< TIM[i] channel [x] SMU counter register, offset: 0xB88 */ __I uint32_t TIM0_CH7_ECNT; /**< TIM[i] channel [x] SMU edge counter register, offset: 0xB8C */ __IO uint32_t TIM0_CH7_CNTS; /**< TIM[i] channel [x] SMU shadow counter register, offset: 0xB90 */ __IO uint32_t TIM0_CH7_TDUC; /**< TIM[i] channel [x] TDU counter register, offset: 0xB94 */ __IO uint32_t TIM0_CH7_TDUV; /**< TIM[i] channel [x] TDU control register, offset: 0xB98 */ __IO uint32_t TIM0_CH7_FLT_RE; /**< TIM[i] channel [x] filter parameter 0 register, offset: 0xB9C */ __IO uint32_t TIM0_CH7_FLT_FE; /**< TIM[i] channel [x] filter parameter 1 register, offset: 0xBA0 */ __IO uint32_t TIM0_CH7_CTRL; /**< TIM[i] channel [x] control register, offset: 0xBA4 */ __IO uint32_t TIM0_CH7_ECTRL; /**< TIM[i] channel [x] extended control register, offset: 0xBA8 */ __IO uint32_t TIM0_CH7_IRQ_NOTIFY; /**< TIM[i] channel [x] interrupt notification register, offset: 0xBAC */ __IO uint32_t TIM0_CH7_IRQ_EN; /**< TIM[i] channel [x] interrupt enable register, offset: 0xBB0 */ __IO uint32_t TIM0_CH7_IRQ_FORCINT; /**< TIM[i] channel [x] force interrupt register, offset: 0xBB4 */ __IO uint32_t TIM0_CH7_IRQ_MODE; /**< TIM[i] channel [x] interrupt mode configuration register, offset: 0xBB8 */ __IO uint32_t TIM0_CH7_EIRQ_EN; /**< TIM[i] channel [x] error interrupt enable register, offset: 0xBBC */ uint8_t RESERVED_28[64]; __I uint32_t TIM0_INP_VAL; /**< TIM[i] input value observation register, offset: 0xC00 */ __IO uint32_t TIM0_IN_SRC; /**< TIM[i] AUX IN source selection register, offset: 0xC04 */ __IO uint32_t TIM0_RST; /**< TIM[i] global software reset register, offset: 0xC08 */ uint8_t RESERVED_29[1012]; __IO uint32_t TOM0_CH0_CTRL; /**< TOM[i] channel [x] control register, offset: 0x1000 */ __IO uint32_t TOM0_CH0_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x1004 */ __IO uint32_t TOM0_CH0_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x1008 */ __IO uint32_t TOM0_CH0_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x100C */ __IO uint32_t TOM0_CH0_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x1010 */ __IO uint32_t TOM0_CH0_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x1014 */ __IO uint32_t TOM0_CH0_STAT; /**< TOM[i] channel [x] status register, offset: 0x1018 */ __IO uint32_t TOM0_CH0_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x101C */ __IO uint32_t TOM0_CH0_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x1020 */ __IO uint32_t TOM0_CH0_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x1024 */ __IO uint32_t TOM0_CH0_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x1028 */ uint8_t RESERVED_30[4]; __IO uint32_t TOM0_CH0_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x1030 */ uint8_t RESERVED_31[12]; __IO uint32_t TOM0_CH1_CTRL; /**< TOM[i] channel [x] control register, offset: 0x1040 */ __IO uint32_t TOM0_CH1_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x1044 */ __IO uint32_t TOM0_CH1_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x1048 */ __IO uint32_t TOM0_CH1_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x104C */ __IO uint32_t TOM0_CH1_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x1050 */ __IO uint32_t TOM0_CH1_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x1054 */ __IO uint32_t TOM0_CH1_STAT; /**< TOM[i] channel [x] status register, offset: 0x1058 */ __IO uint32_t TOM0_CH1_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x105C */ __IO uint32_t TOM0_CH1_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x1060 */ __IO uint32_t TOM0_CH1_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x1064 */ __IO uint32_t TOM0_CH1_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x1068 */ uint8_t RESERVED_32[4]; __IO uint32_t TOM0_CH1_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x1070 */ uint8_t RESERVED_33[12]; __IO uint32_t TOM0_CH2_CTRL; /**< TOM[i] channel [x] control register, offset: 0x1080 */ __IO uint32_t TOM0_CH2_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x1084 */ __IO uint32_t TOM0_CH2_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x1088 */ __IO uint32_t TOM0_CH2_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x108C */ __IO uint32_t TOM0_CH2_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x1090 */ __IO uint32_t TOM0_CH2_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x1094 */ __IO uint32_t TOM0_CH2_STAT; /**< TOM[i] channel [x] status register, offset: 0x1098 */ __IO uint32_t TOM0_CH2_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x109C */ __IO uint32_t TOM0_CH2_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x10A0 */ __IO uint32_t TOM0_CH2_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x10A4 */ __IO uint32_t TOM0_CH2_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x10A8 */ uint8_t RESERVED_34[4]; __IO uint32_t TOM0_CH2_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x10B0 */ uint8_t RESERVED_35[12]; __IO uint32_t TOM0_CH3_CTRL; /**< TOM[i] channel [x] control register, offset: 0x10C0 */ __IO uint32_t TOM0_CH3_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x10C4 */ __IO uint32_t TOM0_CH3_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x10C8 */ __IO uint32_t TOM0_CH3_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x10CC */ __IO uint32_t TOM0_CH3_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x10D0 */ __IO uint32_t TOM0_CH3_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x10D4 */ __IO uint32_t TOM0_CH3_STAT; /**< TOM[i] channel [x] status register, offset: 0x10D8 */ __IO uint32_t TOM0_CH3_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x10DC */ __IO uint32_t TOM0_CH3_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x10E0 */ __IO uint32_t TOM0_CH3_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x10E4 */ __IO uint32_t TOM0_CH3_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x10E8 */ uint8_t RESERVED_36[4]; __IO uint32_t TOM0_CH3_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x10F0 */ uint8_t RESERVED_37[12]; __IO uint32_t TOM0_CH4_CTRL; /**< TOM[i] channel [x] control register, offset: 0x1100 */ __IO uint32_t TOM0_CH4_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x1104 */ __IO uint32_t TOM0_CH4_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x1108 */ __IO uint32_t TOM0_CH4_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x110C */ __IO uint32_t TOM0_CH4_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x1110 */ __IO uint32_t TOM0_CH4_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x1114 */ __IO uint32_t TOM0_CH4_STAT; /**< TOM[i] channel [x] status register, offset: 0x1118 */ __IO uint32_t TOM0_CH4_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x111C */ __IO uint32_t TOM0_CH4_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x1120 */ __IO uint32_t TOM0_CH4_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x1124 */ __IO uint32_t TOM0_CH4_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x1128 */ uint8_t RESERVED_38[4]; __IO uint32_t TOM0_CH4_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x1130 */ uint8_t RESERVED_39[12]; __IO uint32_t TOM0_CH5_CTRL; /**< TOM[i] channel [x] control register, offset: 0x1140 */ __IO uint32_t TOM0_CH5_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x1144 */ __IO uint32_t TOM0_CH5_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x1148 */ __IO uint32_t TOM0_CH5_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x114C */ __IO uint32_t TOM0_CH5_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x1150 */ __IO uint32_t TOM0_CH5_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x1154 */ __IO uint32_t TOM0_CH5_STAT; /**< TOM[i] channel [x] status register, offset: 0x1158 */ __IO uint32_t TOM0_CH5_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x115C */ __IO uint32_t TOM0_CH5_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x1160 */ __IO uint32_t TOM0_CH5_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x1164 */ __IO uint32_t TOM0_CH5_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x1168 */ uint8_t RESERVED_40[4]; __IO uint32_t TOM0_CH5_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x1170 */ uint8_t RESERVED_41[12]; __IO uint32_t TOM0_CH6_CTRL; /**< TOM[i] channel [x] control register, offset: 0x1180 */ __IO uint32_t TOM0_CH6_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x1184 */ __IO uint32_t TOM0_CH6_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x1188 */ __IO uint32_t TOM0_CH6_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x118C */ __IO uint32_t TOM0_CH6_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x1190 */ __IO uint32_t TOM0_CH6_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x1194 */ __IO uint32_t TOM0_CH6_STAT; /**< TOM[i] channel [x] status register, offset: 0x1198 */ __IO uint32_t TOM0_CH6_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x119C */ __IO uint32_t TOM0_CH6_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x11A0 */ __IO uint32_t TOM0_CH6_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x11A4 */ __IO uint32_t TOM0_CH6_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x11A8 */ uint8_t RESERVED_42[4]; __IO uint32_t TOM0_CH6_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x11B0 */ uint8_t RESERVED_43[12]; __IO uint32_t TOM0_CH7_CTRL; /**< TOM[i] channel [x] control register, offset: 0x11C0 */ __IO uint32_t TOM0_CH7_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x11C4 */ __IO uint32_t TOM0_CH7_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x11C8 */ __IO uint32_t TOM0_CH7_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x11CC */ __IO uint32_t TOM0_CH7_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x11D0 */ __IO uint32_t TOM0_CH7_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x11D4 */ __IO uint32_t TOM0_CH7_STAT; /**< TOM[i] channel [x] status register, offset: 0x11D8 */ __IO uint32_t TOM0_CH7_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x11DC */ __IO uint32_t TOM0_CH7_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x11E0 */ __IO uint32_t TOM0_CH7_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x11E4 */ __IO uint32_t TOM0_CH7_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x11E8 */ uint8_t RESERVED_44[4]; __IO uint32_t TOM0_CH7_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x11F0 */ uint8_t RESERVED_45[12]; __IO uint32_t TOM0_CH8_CTRL; /**< TOM[i] channel [x] control register, offset: 0x1200 */ __IO uint32_t TOM0_CH8_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x1204 */ __IO uint32_t TOM0_CH8_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x1208 */ __IO uint32_t TOM0_CH8_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x120C */ __IO uint32_t TOM0_CH8_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x1210 */ __IO uint32_t TOM0_CH8_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x1214 */ __IO uint32_t TOM0_CH8_STAT; /**< TOM[i] channel [x] status register, offset: 0x1218 */ __IO uint32_t TOM0_CH8_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x121C */ __IO uint32_t TOM0_CH8_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x1220 */ __IO uint32_t TOM0_CH8_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x1224 */ __IO uint32_t TOM0_CH8_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x1228 */ uint8_t RESERVED_46[4]; __IO uint32_t TOM0_CH8_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x1230 */ uint8_t RESERVED_47[12]; __IO uint32_t TOM0_CH9_CTRL; /**< TOM[i] channel [x] control register, offset: 0x1240 */ __IO uint32_t TOM0_CH9_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x1244 */ __IO uint32_t TOM0_CH9_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x1248 */ __IO uint32_t TOM0_CH9_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x124C */ __IO uint32_t TOM0_CH9_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x1250 */ __IO uint32_t TOM0_CH9_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x1254 */ __IO uint32_t TOM0_CH9_STAT; /**< TOM[i] channel [x] status register, offset: 0x1258 */ __IO uint32_t TOM0_CH9_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x125C */ __IO uint32_t TOM0_CH9_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x1260 */ __IO uint32_t TOM0_CH9_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x1264 */ __IO uint32_t TOM0_CH9_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x1268 */ uint8_t RESERVED_48[4]; __IO uint32_t TOM0_CH9_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x1270 */ uint8_t RESERVED_49[12]; __IO uint32_t TOM0_CH10_CTRL; /**< TOM[i] channel [x] control register, offset: 0x1280 */ __IO uint32_t TOM0_CH10_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x1284 */ __IO uint32_t TOM0_CH10_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x1288 */ __IO uint32_t TOM0_CH10_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x128C */ __IO uint32_t TOM0_CH10_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x1290 */ __IO uint32_t TOM0_CH10_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x1294 */ __IO uint32_t TOM0_CH10_STAT; /**< TOM[i] channel [x] status register, offset: 0x1298 */ __IO uint32_t TOM0_CH10_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x129C */ __IO uint32_t TOM0_CH10_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x12A0 */ __IO uint32_t TOM0_CH10_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x12A4 */ __IO uint32_t TOM0_CH10_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x12A8 */ uint8_t RESERVED_50[4]; __IO uint32_t TOM0_CH10_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x12B0 */ uint8_t RESERVED_51[12]; __IO uint32_t TOM0_CH11_CTRL; /**< TOM[i] channel [x] control register, offset: 0x12C0 */ __IO uint32_t TOM0_CH11_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x12C4 */ __IO uint32_t TOM0_CH11_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x12C8 */ __IO uint32_t TOM0_CH11_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x12CC */ __IO uint32_t TOM0_CH11_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x12D0 */ __IO uint32_t TOM0_CH11_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x12D4 */ __IO uint32_t TOM0_CH11_STAT; /**< TOM[i] channel [x] status register, offset: 0x12D8 */ __IO uint32_t TOM0_CH11_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x12DC */ __IO uint32_t TOM0_CH11_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x12E0 */ __IO uint32_t TOM0_CH11_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x12E4 */ __IO uint32_t TOM0_CH11_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x12E8 */ uint8_t RESERVED_52[4]; __IO uint32_t TOM0_CH11_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x12F0 */ uint8_t RESERVED_53[12]; __IO uint32_t TOM0_CH12_CTRL; /**< TOM[i] channel [x] control register, offset: 0x1300 */ __IO uint32_t TOM0_CH12_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x1304 */ __IO uint32_t TOM0_CH12_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x1308 */ __IO uint32_t TOM0_CH12_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x130C */ __IO uint32_t TOM0_CH12_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x1310 */ __IO uint32_t TOM0_CH12_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x1314 */ __IO uint32_t TOM0_CH12_STAT; /**< TOM[i] channel [x] status register, offset: 0x1318 */ __IO uint32_t TOM0_CH12_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x131C */ __IO uint32_t TOM0_CH12_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x1320 */ __IO uint32_t TOM0_CH12_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x1324 */ __IO uint32_t TOM0_CH12_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x1328 */ uint8_t RESERVED_54[4]; __IO uint32_t TOM0_CH12_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x1330 */ uint8_t RESERVED_55[12]; __IO uint32_t TOM0_CH13_CTRL; /**< TOM[i] channel [x] control register, offset: 0x1340 */ __IO uint32_t TOM0_CH13_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x1344 */ __IO uint32_t TOM0_CH13_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x1348 */ __IO uint32_t TOM0_CH13_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x134C */ __IO uint32_t TOM0_CH13_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x1350 */ __IO uint32_t TOM0_CH13_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x1354 */ __IO uint32_t TOM0_CH13_STAT; /**< TOM[i] channel [x] status register, offset: 0x1358 */ __IO uint32_t TOM0_CH13_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x135C */ __IO uint32_t TOM0_CH13_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x1360 */ __IO uint32_t TOM0_CH13_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x1364 */ __IO uint32_t TOM0_CH13_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x1368 */ uint8_t RESERVED_56[4]; __IO uint32_t TOM0_CH13_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x1370 */ uint8_t RESERVED_57[12]; __IO uint32_t TOM0_CH14_CTRL; /**< TOM[i] channel [x] control register, offset: 0x1380 */ __IO uint32_t TOM0_CH14_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x1384 */ __IO uint32_t TOM0_CH14_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x1388 */ __IO uint32_t TOM0_CH14_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x138C */ __IO uint32_t TOM0_CH14_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x1390 */ __IO uint32_t TOM0_CH14_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x1394 */ __IO uint32_t TOM0_CH14_STAT; /**< TOM[i] channel [x] status register, offset: 0x1398 */ __IO uint32_t TOM0_CH14_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x139C */ __IO uint32_t TOM0_CH14_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x13A0 */ __IO uint32_t TOM0_CH14_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x13A4 */ __IO uint32_t TOM0_CH14_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x13A8 */ uint8_t RESERVED_58[4]; __IO uint32_t TOM0_CH14_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x13B0 */ uint8_t RESERVED_59[12]; __IO uint32_t TOM0_CH15_CTRL; /**< TOM[i] channel [x] control register, offset: 0x13C0 */ __IO uint32_t TOM0_CH15_SR0; /**< TOM[i] channel [x] CCU0 compare shadow register, offset: 0x13C4 */ __IO uint32_t TOM0_CH15_SR1; /**< TOM[i] channel [x] CCU1 compare shadow register, offset: 0x13C8 */ __IO uint32_t TOM0_CH15_CM0; /**< TOM[i] channel [x] CCU0 compare register, offset: 0x13CC */ __IO uint32_t TOM0_CH15_CM1; /**< TOM[i] channel [x] CCU1 compare register, offset: 0x13D0 */ __IO uint32_t TOM0_CH15_CN0; /**< TOM[i] channel [x] CCU0 counter, offset: 0x13D4 */ __IO uint32_t TOM0_CH15_STAT; /**< TOM[i] channel [x] status register, offset: 0x13D8 */ __IO uint32_t TOM0_CH15_IRQ_NOTIFY; /**< TOM[i] channel [x] interrupt notification register, offset: 0x13DC */ __IO uint32_t TOM0_CH15_IRQ_EN; /**< TOM[i] channel [x] interrupt enable register, offset: 0x13E0 */ __IO uint32_t TOM0_CH15_IRQ_FORCINT; /**< TOM[i] channel [x] force interrupt register, offset: 0x13E4 */ __IO uint32_t TOM0_CH15_IRQ_MODE; /**< TOM[i] channel [x] interrupt mode register, offset: 0x13E8 */ uint8_t RESERVED_60[4]; __IO uint32_t TOM0_CH15_CTRL_SR; /**< TOM[i] channel [x] control shadow register, offset: 0x13F0 */ uint8_t RESERVED_61[60]; __IO uint32_t TOM0_TGC0_GLB_CTRL; /**< TOM[i] TGC [g] global control register, offset: 0x1430 */ __IO uint32_t TOM0_TGC0_ACT_TB; /**< TOM[i] TGC [g] action time base register, offset: 0x1434 */ __IO uint32_t TOM0_TGC0_FUPD_CTRL; /**< TOM[i] TGC [g] force update control register, offset: 0x1438 */ __IO uint32_t TOM0_TGC0_INT_TRIG; /**< TOM[i] TGC [g] internal trigger control register, offset: 0x143C */ uint8_t RESERVED_62[48]; __IO uint32_t TOM0_TGC0_ENDIS_CTRL; /**< TOM[i] TGC [g] enable/disable control register, offset: 0x1470 */ __IO uint32_t TOM0_TGC0_ENDIS_STAT; /**< TOM[i] TGC [g] enable/disable status register, offset: 0x1474 */ __IO uint32_t TOM0_TGC0_OUTEN_CTRL; /**< TOM[i] TGC [g] output enable control register, offset: 0x1478 */ __IO uint32_t TOM0_TGC0_OUTEN_STAT; /**< TOM[i] TGC [g] output enable status register, offset: 0x147C */ uint8_t RESERVED_63[48]; __IO uint32_t TOM0_TGC1_GLB_CTRL; /**< TOM[i] TGC [g] global control register, offset: 0x14B0 */ __IO uint32_t TOM0_TGC1_ACT_TB; /**< TOM[i] TGC [g] action time base register, offset: 0x14B4 */ __IO uint32_t TOM0_TGC1_FUPD_CTRL; /**< TOM[i] TGC [g] force update control register, offset: 0x14B8 */ __IO uint32_t TOM0_TGC1_INT_TRIG; /**< TOM[i] TGC [g] internal trigger control register, offset: 0x14BC */ uint8_t RESERVED_64[48]; __IO uint32_t TOM0_TGC1_ENDIS_CTRL; /**< TOM[i] TGC [g] enable/disable control register, offset: 0x14F0 */ __IO uint32_t TOM0_TGC1_ENDIS_STAT; /**< TOM[i] TGC [g] enable/disable status register, offset: 0x14F4 */ __IO uint32_t TOM0_TGC1_OUTEN_CTRL; /**< TOM[i] TGC [g] output enable control register, offset: 0x14F8 */ __IO uint32_t TOM0_TGC1_OUTEN_STAT; /**< TOM[i] TGC [g] output enable status register, offset: 0x14FC */ uint8_t RESERVED_65[768]; __IO uint32_t ATOM0_CH0_RDADDR; /**< ATOM[i] channel[x] ARU read address register, offset: 0x1800 */ __IO uint32_t ATOM0_CH0_CTRL; /**< ATOM[i] channel [x] control register, offset: 0x1804 */ __IO uint32_t ATOM0_CH0_SR0; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1808 */ __IO uint32_t ATOM0_CH0_SR1; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x180C */ __IO uint32_t ATOM0_CH0_CM0; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1810 */ __IO uint32_t ATOM0_CH0_CM1; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1814 */ __IO uint32_t ATOM0_CH0_CN0; /**< ATOM[i] channel [x] CCU0 counter register, offset: 0x1818 */ __IO uint32_t ATOM0_CH0_STAT; /**< ATOM[i] channel [x] status register, offset: 0x181C */ __IO uint32_t ATOM0_CH0_IRQ_NOTIFY; /**< ATOM[i] channel [x] interrupt notification register, offset: 0x1820 */ __IO uint32_t ATOM0_CH0_IRQ_EN; /**< ATOM[i] channel [x] interrupt enable register, offset: 0x1824 */ __IO uint32_t ATOM0_CH0_IRQ_FORCINT; /**< ATOM[i] channel [x] software interrupt generation, offset: 0x1828 */ __IO uint32_t ATOM0_CH0_IRQ_MODE; /**< ATOM[i] channel [x] interrupt mode configuration register, offset: 0x182C */ uint8_t RESERVED_66[4]; __IO uint32_t ATOM0_CH0_CTRL_SR; /**< ATOM[i] channel [x] control shadow register, offset: 0x1834 */ uint8_t RESERVED_67[72]; __IO uint32_t ATOM0_CH1_RDADDR; /**< ATOM[i] channel[x] ARU read address register, offset: 0x1880 */ __IO uint32_t ATOM0_CH1_CTRL; /**< ATOM[i] channel [x] control register, offset: 0x1884 */ __IO uint32_t ATOM0_CH1_SR0; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1888 */ __IO uint32_t ATOM0_CH1_SR1; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x188C */ __IO uint32_t ATOM0_CH1_CM0; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1890 */ __IO uint32_t ATOM0_CH1_CM1; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1894 */ __IO uint32_t ATOM0_CH1_CN0; /**< ATOM[i] channel [x] CCU0 counter register, offset: 0x1898 */ __IO uint32_t ATOM0_CH1_STAT; /**< ATOM[i] channel [x] status register, offset: 0x189C */ __IO uint32_t ATOM0_CH1_IRQ_NOTIFY; /**< ATOM[i] channel [x] interrupt notification register, offset: 0x18A0 */ __IO uint32_t ATOM0_CH1_IRQ_EN; /**< ATOM[i] channel [x] interrupt enable register, offset: 0x18A4 */ __IO uint32_t ATOM0_CH1_IRQ_FORCINT; /**< ATOM[i] channel [x] software interrupt generation, offset: 0x18A8 */ __IO uint32_t ATOM0_CH1_IRQ_MODE; /**< ATOM[i] channel [x] interrupt mode configuration register, offset: 0x18AC */ uint8_t RESERVED_68[4]; __IO uint32_t ATOM0_CH1_CTRL_SR; /**< ATOM[i] channel [x] control shadow register, offset: 0x18B4 */ uint8_t RESERVED_69[72]; __IO uint32_t ATOM0_CH2_RDADDR; /**< ATOM[i] channel[x] ARU read address register, offset: 0x1900 */ __IO uint32_t ATOM0_CH2_CTRL; /**< ATOM[i] channel [x] control register, offset: 0x1904 */ __IO uint32_t ATOM0_CH2_SR0; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1908 */ __IO uint32_t ATOM0_CH2_SR1; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x190C */ __IO uint32_t ATOM0_CH2_CM0; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1910 */ __IO uint32_t ATOM0_CH2_CM1; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1914 */ __IO uint32_t ATOM0_CH2_CN0; /**< ATOM[i] channel [x] CCU0 counter register, offset: 0x1918 */ __IO uint32_t ATOM0_CH2_STAT; /**< ATOM[i] channel [x] status register, offset: 0x191C */ __IO uint32_t ATOM0_CH2_IRQ_NOTIFY; /**< ATOM[i] channel [x] interrupt notification register, offset: 0x1920 */ __IO uint32_t ATOM0_CH2_IRQ_EN; /**< ATOM[i] channel [x] interrupt enable register, offset: 0x1924 */ __IO uint32_t ATOM0_CH2_IRQ_FORCINT; /**< ATOM[i] channel [x] software interrupt generation, offset: 0x1928 */ __IO uint32_t ATOM0_CH2_IRQ_MODE; /**< ATOM[i] channel [x] interrupt mode configuration register, offset: 0x192C */ uint8_t RESERVED_70[4]; __IO uint32_t ATOM0_CH2_CTRL_SR; /**< ATOM[i] channel [x] control shadow register, offset: 0x1934 */ uint8_t RESERVED_71[72]; __IO uint32_t ATOM0_CH3_RDADDR; /**< ATOM[i] channel[x] ARU read address register, offset: 0x1980 */ __IO uint32_t ATOM0_CH3_CTRL; /**< ATOM[i] channel [x] control register, offset: 0x1984 */ __IO uint32_t ATOM0_CH3_SR0; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1988 */ __IO uint32_t ATOM0_CH3_SR1; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x198C */ __IO uint32_t ATOM0_CH3_CM0; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1990 */ __IO uint32_t ATOM0_CH3_CM1; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1994 */ __IO uint32_t ATOM0_CH3_CN0; /**< ATOM[i] channel [x] CCU0 counter register, offset: 0x1998 */ __IO uint32_t ATOM0_CH3_STAT; /**< ATOM[i] channel [x] status register, offset: 0x199C */ __IO uint32_t ATOM0_CH3_IRQ_NOTIFY; /**< ATOM[i] channel [x] interrupt notification register, offset: 0x19A0 */ __IO uint32_t ATOM0_CH3_IRQ_EN; /**< ATOM[i] channel [x] interrupt enable register, offset: 0x19A4 */ __IO uint32_t ATOM0_CH3_IRQ_FORCINT; /**< ATOM[i] channel [x] software interrupt generation, offset: 0x19A8 */ __IO uint32_t ATOM0_CH3_IRQ_MODE; /**< ATOM[i] channel [x] interrupt mode configuration register, offset: 0x19AC */ uint8_t RESERVED_72[4]; __IO uint32_t ATOM0_CH3_CTRL_SR; /**< ATOM[i] channel [x] control shadow register, offset: 0x19B4 */ uint8_t RESERVED_73[72]; __IO uint32_t ATOM0_CH4_RDADDR; /**< ATOM[i] channel[x] ARU read address register, offset: 0x1A00 */ __IO uint32_t ATOM0_CH4_CTRL; /**< ATOM[i] channel [x] control register, offset: 0x1A04 */ __IO uint32_t ATOM0_CH4_SR0; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1A08 */ __IO uint32_t ATOM0_CH4_SR1; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1A0C */ __IO uint32_t ATOM0_CH4_CM0; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1A10 */ __IO uint32_t ATOM0_CH4_CM1; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1A14 */ __IO uint32_t ATOM0_CH4_CN0; /**< ATOM[i] channel [x] CCU0 counter register, offset: 0x1A18 */ __IO uint32_t ATOM0_CH4_STAT; /**< ATOM[i] channel [x] status register, offset: 0x1A1C */ __IO uint32_t ATOM0_CH4_IRQ_NOTIFY; /**< ATOM[i] channel [x] interrupt notification register, offset: 0x1A20 */ __IO uint32_t ATOM0_CH4_IRQ_EN; /**< ATOM[i] channel [x] interrupt enable register, offset: 0x1A24 */ __IO uint32_t ATOM0_CH4_IRQ_FORCINT; /**< ATOM[i] channel [x] software interrupt generation, offset: 0x1A28 */ __IO uint32_t ATOM0_CH4_IRQ_MODE; /**< ATOM[i] channel [x] interrupt mode configuration register, offset: 0x1A2C */ uint8_t RESERVED_74[4]; __IO uint32_t ATOM0_CH4_CTRL_SR; /**< ATOM[i] channel [x] control shadow register, offset: 0x1A34 */ uint8_t RESERVED_75[72]; __IO uint32_t ATOM0_CH5_RDADDR; /**< ATOM[i] channel[x] ARU read address register, offset: 0x1A80 */ __IO uint32_t ATOM0_CH5_CTRL; /**< ATOM[i] channel [x] control register, offset: 0x1A84 */ __IO uint32_t ATOM0_CH5_SR0; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1A88 */ __IO uint32_t ATOM0_CH5_SR1; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1A8C */ __IO uint32_t ATOM0_CH5_CM0; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1A90 */ __IO uint32_t ATOM0_CH5_CM1; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1A94 */ __IO uint32_t ATOM0_CH5_CN0; /**< ATOM[i] channel [x] CCU0 counter register, offset: 0x1A98 */ __IO uint32_t ATOM0_CH5_STAT; /**< ATOM[i] channel [x] status register, offset: 0x1A9C */ __IO uint32_t ATOM0_CH5_IRQ_NOTIFY; /**< ATOM[i] channel [x] interrupt notification register, offset: 0x1AA0 */ __IO uint32_t ATOM0_CH5_IRQ_EN; /**< ATOM[i] channel [x] interrupt enable register, offset: 0x1AA4 */ __IO uint32_t ATOM0_CH5_IRQ_FORCINT; /**< ATOM[i] channel [x] software interrupt generation, offset: 0x1AA8 */ __IO uint32_t ATOM0_CH5_IRQ_MODE; /**< ATOM[i] channel [x] interrupt mode configuration register, offset: 0x1AAC */ uint8_t RESERVED_76[4]; __IO uint32_t ATOM0_CH5_CTRL_SR; /**< ATOM[i] channel [x] control shadow register, offset: 0x1AB4 */ uint8_t RESERVED_77[72]; __IO uint32_t ATOM0_CH6_RDADDR; /**< ATOM[i] channel[x] ARU read address register, offset: 0x1B00 */ __IO uint32_t ATOM0_CH6_CTRL; /**< ATOM[i] channel [x] control register, offset: 0x1B04 */ __IO uint32_t ATOM0_CH6_SR0; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1B08 */ __IO uint32_t ATOM0_CH6_SR1; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1B0C */ __IO uint32_t ATOM0_CH6_CM0; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1B10 */ __IO uint32_t ATOM0_CH6_CM1; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1B14 */ __IO uint32_t ATOM0_CH6_CN0; /**< ATOM[i] channel [x] CCU0 counter register, offset: 0x1B18 */ __IO uint32_t ATOM0_CH6_STAT; /**< ATOM[i] channel [x] status register, offset: 0x1B1C */ __IO uint32_t ATOM0_CH6_IRQ_NOTIFY; /**< ATOM[i] channel [x] interrupt notification register, offset: 0x1B20 */ __IO uint32_t ATOM0_CH6_IRQ_EN; /**< ATOM[i] channel [x] interrupt enable register, offset: 0x1B24 */ __IO uint32_t ATOM0_CH6_IRQ_FORCINT; /**< ATOM[i] channel [x] software interrupt generation, offset: 0x1B28 */ __IO uint32_t ATOM0_CH6_IRQ_MODE; /**< ATOM[i] channel [x] interrupt mode configuration register, offset: 0x1B2C */ uint8_t RESERVED_78[4]; __IO uint32_t ATOM0_CH6_CTRL_SR; /**< ATOM[i] channel [x] control shadow register, offset: 0x1B34 */ uint8_t RESERVED_79[72]; __IO uint32_t ATOM0_CH7_RDADDR; /**< ATOM[i] channel[x] ARU read address register, offset: 0x1B80 */ __IO uint32_t ATOM0_CH7_CTRL; /**< ATOM[i] channel [x] control register, offset: 0x1B84 */ __IO uint32_t ATOM0_CH7_SR0; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1B88 */ __IO uint32_t ATOM0_CH7_SR1; /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1B8C */ __IO uint32_t ATOM0_CH7_CM0; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1B90 */ __IO uint32_t ATOM0_CH7_CM1; /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1B94 */ __IO uint32_t ATOM0_CH7_CN0; /**< ATOM[i] channel [x] CCU0 counter register, offset: 0x1B98 */ __IO uint32_t ATOM0_CH7_STAT; /**< ATOM[i] channel [x] status register, offset: 0x1B9C */ __IO uint32_t ATOM0_CH7_IRQ_NOTIFY; /**< ATOM[i] channel [x] interrupt notification register, offset: 0x1BA0 */ __IO uint32_t ATOM0_CH7_IRQ_EN; /**< ATOM[i] channel [x] interrupt enable register, offset: 0x1BA4 */ __IO uint32_t ATOM0_CH7_IRQ_FORCINT; /**< ATOM[i] channel [x] software interrupt generation, offset: 0x1BA8 */ __IO uint32_t ATOM0_CH7_IRQ_MODE; /**< ATOM[i] channel [x] interrupt mode configuration register, offset: 0x1BAC */ uint8_t RESERVED_80[4]; __IO uint32_t ATOM0_CH7_CTRL_SR; /**< ATOM[i] channel [x] control shadow register, offset: 0x1BB4 */ uint8_t RESERVED_81[136]; __IO uint32_t ATOM0_AGC_GLB_CTRL; /**< ATOM[i] AGC global control register, offset: 0x1C40 */ __IO uint32_t ATOM0_AGC_ENDIS_CTRL; /**< ATOM[i] AGC enable/disable control register, offset: 0x1C44 */ __IO uint32_t ATOM0_AGC_ENDIS_STAT; /**< ATOM[i] AGC enable/disable status register, offset: 0x1C48 */ __IO uint32_t ATOM0_AGC_ACT_TB; /**< ATOM[i] AGC action time base register, offset: 0x1C4C */ __IO uint32_t ATOM0_AGC_OUTEN_CTRL; /**< ATOM[i] AGC output enable control register, offset: 0x1C50 */ __IO uint32_t ATOM0_AGC_OUTEN_STAT; /**< ATOM[i] AGC output enable status register, offset: 0x1C54 */ __IO uint32_t ATOM0_AGC_FUPD_CTRL; /**< ATOM[i] AGC force update control register, offset: 0x1C58 */ __IO uint32_t ATOM0_AGC_INT_TRIG; /**< ATOM[i] AGC internal trigger control register, offset: 0x1C5C */ uint8_t RESERVED_82[928]; __IO uint32_t MCS0_CH0_R0; /**< MCS[i] channel x general purpose register [y], offset: 0x2000 */ __IO uint32_t MCS0_CH0_R1; /**< MCS[i] channel x general purpose register [y], offset: 0x2004 */ __IO uint32_t MCS0_CH0_R2; /**< MCS[i] channel x general purpose register [y], offset: 0x2008 */ __IO uint32_t MCS0_CH0_R3; /**< MCS[i] channel x general purpose register [y], offset: 0x200C */ __IO uint32_t MCS0_CH0_R4; /**< MCS[i] channel x general purpose register [y], offset: 0x2010 */ __IO uint32_t MCS0_CH0_R5; /**< MCS[i] channel x general purpose register [y], offset: 0x2014 */ __IO uint32_t MCS0_CH0_R6; /**< MCS[i] channel x general purpose register [y], offset: 0x2018 */ __IO uint32_t MCS0_CH0_R7; /**< MCS[i] channel x general purpose register [y], offset: 0x201C */ __IO uint32_t MCS0_CH0_CTRL; /**< MCS[i] channel x control register, offset: 0x2020 */ __I uint32_t MCS0_CH0_ACB; /**< MCS[i] channel x ARU control Bit register, offset: 0x2024 */ uint8_t RESERVED_83[20]; __I uint32_t MCS0_CH0_MHB; /**< MCS[i] channel x memory high byte register, offset: 0x203C */ uint8_t RESERVED_84[160]; __IO uint32_t MCS0_CH0_PC; /**< MCS[i] channel x program counter register, offset: 0x20E0 */ __IO uint32_t MCS0_CH0_IRQ_NOTIFY; /**< MCS[i] channel x interrupt notification register, offset: 0x20E4 */ __IO uint32_t MCS0_CH0_IRQ_EN; /**< MCS[i] channel x interrupt enable register, offset: 0x20E8 */ __IO uint32_t MCS0_CH0_IRQ_FORCINT; /**< MCS[i] channel x force interrupt register, offset: 0x20EC */ __IO uint32_t MCS0_CH0_IRQ_MODE; /**< MCS[i] channel x IRQ mode configuration register, offset: 0x20F0 */ __IO uint32_t MCS0_CH0_EIRQ_EN; /**< MCS[i] channel x error interrupt enable register, offset: 0x20F4 */ uint8_t RESERVED_85[8]; __IO uint32_t MCS0_CH1_R0; /**< MCS[i] channel x general purpose register [y], offset: 0x2100 */ __IO uint32_t MCS0_CH1_R1; /**< MCS[i] channel x general purpose register [y], offset: 0x2104 */ __IO uint32_t MCS0_CH1_R2; /**< MCS[i] channel x general purpose register [y], offset: 0x2108 */ __IO uint32_t MCS0_CH1_R3; /**< MCS[i] channel x general purpose register [y], offset: 0x210C */ __IO uint32_t MCS0_CH1_R4; /**< MCS[i] channel x general purpose register [y], offset: 0x2110 */ __IO uint32_t MCS0_CH1_R5; /**< MCS[i] channel x general purpose register [y], offset: 0x2114 */ __IO uint32_t MCS0_CH1_R6; /**< MCS[i] channel x general purpose register [y], offset: 0x2118 */ __IO uint32_t MCS0_CH1_R7; /**< MCS[i] channel x general purpose register [y], offset: 0x211C */ __IO uint32_t MCS0_CH1_CTRL; /**< MCS[i] channel x control register, offset: 0x2120 */ __I uint32_t MCS0_CH1_ACB; /**< MCS[i] channel x ARU control Bit register, offset: 0x2124 */ uint8_t RESERVED_86[20]; __I uint32_t MCS0_CH1_MHB; /**< MCS[i] channel x memory high byte register, offset: 0x213C */ uint8_t RESERVED_87[160]; __IO uint32_t MCS0_CH1_PC; /**< MCS[i] channel x program counter register, offset: 0x21E0 */ __IO uint32_t MCS0_CH1_IRQ_NOTIFY; /**< MCS[i] channel x interrupt notification register, offset: 0x21E4 */ __IO uint32_t MCS0_CH1_IRQ_EN; /**< MCS[i] channel x interrupt enable register, offset: 0x21E8 */ __IO uint32_t MCS0_CH1_IRQ_FORCINT; /**< MCS[i] channel x force interrupt register, offset: 0x21EC */ __IO uint32_t MCS0_CH1_IRQ_MODE; /**< MCS[i] channel x IRQ mode configuration register, offset: 0x21F0 */ __IO uint32_t MCS0_CH1_EIRQ_EN; /**< MCS[i] channel x error interrupt enable register, offset: 0x21F4 */ uint8_t RESERVED_88[8]; __IO uint32_t MCS0_CH2_R0; /**< MCS[i] channel x general purpose register [y], offset: 0x2200 */ __IO uint32_t MCS0_CH2_R1; /**< MCS[i] channel x general purpose register [y], offset: 0x2204 */ __IO uint32_t MCS0_CH2_R2; /**< MCS[i] channel x general purpose register [y], offset: 0x2208 */ __IO uint32_t MCS0_CH2_R3; /**< MCS[i] channel x general purpose register [y], offset: 0x220C */ __IO uint32_t MCS0_CH2_R4; /**< MCS[i] channel x general purpose register [y], offset: 0x2210 */ __IO uint32_t MCS0_CH2_R5; /**< MCS[i] channel x general purpose register [y], offset: 0x2214 */ __IO uint32_t MCS0_CH2_R6; /**< MCS[i] channel x general purpose register [y], offset: 0x2218 */ __IO uint32_t MCS0_CH2_R7; /**< MCS[i] channel x general purpose register [y], offset: 0x221C */ __IO uint32_t MCS0_CH2_CTRL; /**< MCS[i] channel x control register, offset: 0x2220 */ __I uint32_t MCS0_CH2_ACB; /**< MCS[i] channel x ARU control Bit register, offset: 0x2224 */ uint8_t RESERVED_89[20]; __I uint32_t MCS0_CH2_MHB; /**< MCS[i] channel x memory high byte register, offset: 0x223C */ uint8_t RESERVED_90[160]; __IO uint32_t MCS0_CH2_PC; /**< MCS[i] channel x program counter register, offset: 0x22E0 */ __IO uint32_t MCS0_CH2_IRQ_NOTIFY; /**< MCS[i] channel x interrupt notification register, offset: 0x22E4 */ __IO uint32_t MCS0_CH2_IRQ_EN; /**< MCS[i] channel x interrupt enable register, offset: 0x22E8 */ __IO uint32_t MCS0_CH2_IRQ_FORCINT; /**< MCS[i] channel x force interrupt register, offset: 0x22EC */ __IO uint32_t MCS0_CH2_IRQ_MODE; /**< MCS[i] channel x IRQ mode configuration register, offset: 0x22F0 */ __IO uint32_t MCS0_CH2_EIRQ_EN; /**< MCS[i] channel x error interrupt enable register, offset: 0x22F4 */ uint8_t RESERVED_91[8]; __IO uint32_t MCS0_CH3_R0; /**< MCS[i] channel x general purpose register [y], offset: 0x2300 */ __IO uint32_t MCS0_CH3_R1; /**< MCS[i] channel x general purpose register [y], offset: 0x2304 */ __IO uint32_t MCS0_CH3_R2; /**< MCS[i] channel x general purpose register [y], offset: 0x2308 */ __IO uint32_t MCS0_CH3_R3; /**< MCS[i] channel x general purpose register [y], offset: 0x230C */ __IO uint32_t MCS0_CH3_R4; /**< MCS[i] channel x general purpose register [y], offset: 0x2310 */ __IO uint32_t MCS0_CH3_R5; /**< MCS[i] channel x general purpose register [y], offset: 0x2314 */ __IO uint32_t MCS0_CH3_R6; /**< MCS[i] channel x general purpose register [y], offset: 0x2318 */ __IO uint32_t MCS0_CH3_R7; /**< MCS[i] channel x general purpose register [y], offset: 0x231C */ __IO uint32_t MCS0_CH3_CTRL; /**< MCS[i] channel x control register, offset: 0x2320 */ __I uint32_t MCS0_CH3_ACB; /**< MCS[i] channel x ARU control Bit register, offset: 0x2324 */ uint8_t RESERVED_92[20]; __I uint32_t MCS0_CH3_MHB; /**< MCS[i] channel x memory high byte register, offset: 0x233C */ uint8_t RESERVED_93[160]; __IO uint32_t MCS0_CH3_PC; /**< MCS[i] channel x program counter register, offset: 0x23E0 */ __IO uint32_t MCS0_CH3_IRQ_NOTIFY; /**< MCS[i] channel x interrupt notification register, offset: 0x23E4 */ __IO uint32_t MCS0_CH3_IRQ_EN; /**< MCS[i] channel x interrupt enable register, offset: 0x23E8 */ __IO uint32_t MCS0_CH3_IRQ_FORCINT; /**< MCS[i] channel x force interrupt register, offset: 0x23EC */ __IO uint32_t MCS0_CH3_IRQ_MODE; /**< MCS[i] channel x IRQ mode configuration register, offset: 0x23F0 */ __IO uint32_t MCS0_CH3_EIRQ_EN; /**< MCS[i] channel x error interrupt enable register, offset: 0x23F4 */ uint8_t RESERVED_94[8]; __IO uint32_t MCS0_CH4_R0; /**< MCS[i] channel x general purpose register [y], offset: 0x2400 */ __IO uint32_t MCS0_CH4_R1; /**< MCS[i] channel x general purpose register [y], offset: 0x2404 */ __IO uint32_t MCS0_CH4_R2; /**< MCS[i] channel x general purpose register [y], offset: 0x2408 */ __IO uint32_t MCS0_CH4_R3; /**< MCS[i] channel x general purpose register [y], offset: 0x240C */ __IO uint32_t MCS0_CH4_R4; /**< MCS[i] channel x general purpose register [y], offset: 0x2410 */ __IO uint32_t MCS0_CH4_R5; /**< MCS[i] channel x general purpose register [y], offset: 0x2414 */ __IO uint32_t MCS0_CH4_R6; /**< MCS[i] channel x general purpose register [y], offset: 0x2418 */ __IO uint32_t MCS0_CH4_R7; /**< MCS[i] channel x general purpose register [y], offset: 0x241C */ __IO uint32_t MCS0_CH4_CTRL; /**< MCS[i] channel x control register, offset: 0x2420 */ __I uint32_t MCS0_CH4_ACB; /**< MCS[i] channel x ARU control Bit register, offset: 0x2424 */ uint8_t RESERVED_95[20]; __I uint32_t MCS0_CH4_MHB; /**< MCS[i] channel x memory high byte register, offset: 0x243C */ uint8_t RESERVED_96[160]; __IO uint32_t MCS0_CH4_PC; /**< MCS[i] channel x program counter register, offset: 0x24E0 */ __IO uint32_t MCS0_CH4_IRQ_NOTIFY; /**< MCS[i] channel x interrupt notification register, offset: 0x24E4 */ __IO uint32_t MCS0_CH4_IRQ_EN; /**< MCS[i] channel x interrupt enable register, offset: 0x24E8 */ __IO uint32_t MCS0_CH4_IRQ_FORCINT; /**< MCS[i] channel x force interrupt register, offset: 0x24EC */ __IO uint32_t MCS0_CH4_IRQ_MODE; /**< MCS[i] channel x IRQ mode configuration register, offset: 0x24F0 */ __IO uint32_t MCS0_CH4_EIRQ_EN; /**< MCS[i] channel x error interrupt enable register, offset: 0x24F4 */ uint8_t RESERVED_97[8]; __IO uint32_t MCS0_CH5_R0; /**< MCS[i] channel x general purpose register [y], offset: 0x2500 */ __IO uint32_t MCS0_CH5_R1; /**< MCS[i] channel x general purpose register [y], offset: 0x2504 */ __IO uint32_t MCS0_CH5_R2; /**< MCS[i] channel x general purpose register [y], offset: 0x2508 */ __IO uint32_t MCS0_CH5_R3; /**< MCS[i] channel x general purpose register [y], offset: 0x250C */ __IO uint32_t MCS0_CH5_R4; /**< MCS[i] channel x general purpose register [y], offset: 0x2510 */ __IO uint32_t MCS0_CH5_R5; /**< MCS[i] channel x general purpose register [y], offset: 0x2514 */ __IO uint32_t MCS0_CH5_R6; /**< MCS[i] channel x general purpose register [y], offset: 0x2518 */ __IO uint32_t MCS0_CH5_R7; /**< MCS[i] channel x general purpose register [y], offset: 0x251C */ __IO uint32_t MCS0_CH5_CTRL; /**< MCS[i] channel x control register, offset: 0x2520 */ __I uint32_t MCS0_CH5_ACB; /**< MCS[i] channel x ARU control Bit register, offset: 0x2524 */ uint8_t RESERVED_98[20]; __I uint32_t MCS0_CH5_MHB; /**< MCS[i] channel x memory high byte register, offset: 0x253C */ uint8_t RESERVED_99[160]; __IO uint32_t MCS0_CH5_PC; /**< MCS[i] channel x program counter register, offset: 0x25E0 */ __IO uint32_t MCS0_CH5_IRQ_NOTIFY; /**< MCS[i] channel x interrupt notification register, offset: 0x25E4 */ __IO uint32_t MCS0_CH5_IRQ_EN; /**< MCS[i] channel x interrupt enable register, offset: 0x25E8 */ __IO uint32_t MCS0_CH5_IRQ_FORCINT; /**< MCS[i] channel x force interrupt register, offset: 0x25EC */ __IO uint32_t MCS0_CH5_IRQ_MODE; /**< MCS[i] channel x IRQ mode configuration register, offset: 0x25F0 */ __IO uint32_t MCS0_CH5_EIRQ_EN; /**< MCS[i] channel x error interrupt enable register, offset: 0x25F4 */ uint8_t RESERVED_100[8]; __IO uint32_t MCS0_CH6_R0; /**< MCS[i] channel x general purpose register [y], offset: 0x2600 */ __IO uint32_t MCS0_CH6_R1; /**< MCS[i] channel x general purpose register [y], offset: 0x2604 */ __IO uint32_t MCS0_CH6_R2; /**< MCS[i] channel x general purpose register [y], offset: 0x2608 */ __IO uint32_t MCS0_CH6_R3; /**< MCS[i] channel x general purpose register [y], offset: 0x260C */ __IO uint32_t MCS0_CH6_R4; /**< MCS[i] channel x general purpose register [y], offset: 0x2610 */ __IO uint32_t MCS0_CH6_R5; /**< MCS[i] channel x general purpose register [y], offset: 0x2614 */ __IO uint32_t MCS0_CH6_R6; /**< MCS[i] channel x general purpose register [y], offset: 0x2618 */ __IO uint32_t MCS0_CH6_R7; /**< MCS[i] channel x general purpose register [y], offset: 0x261C */ __IO uint32_t MCS0_CH6_CTRL; /**< MCS[i] channel x control register, offset: 0x2620 */ __I uint32_t MCS0_CH6_ACB; /**< MCS[i] channel x ARU control Bit register, offset: 0x2624 */ uint8_t RESERVED_101[20]; __I uint32_t MCS0_CH6_MHB; /**< MCS[i] channel x memory high byte register, offset: 0x263C */ uint8_t RESERVED_102[160]; __IO uint32_t MCS0_CH6_PC; /**< MCS[i] channel x program counter register, offset: 0x26E0 */ __IO uint32_t MCS0_CH6_IRQ_NOTIFY; /**< MCS[i] channel x interrupt notification register, offset: 0x26E4 */ __IO uint32_t MCS0_CH6_IRQ_EN; /**< MCS[i] channel x interrupt enable register, offset: 0x26E8 */ __IO uint32_t MCS0_CH6_IRQ_FORCINT; /**< MCS[i] channel x force interrupt register, offset: 0x26EC */ __IO uint32_t MCS0_CH6_IRQ_MODE; /**< MCS[i] channel x IRQ mode configuration register, offset: 0x26F0 */ __IO uint32_t MCS0_CH6_EIRQ_EN; /**< MCS[i] channel x error interrupt enable register, offset: 0x26F4 */ uint8_t RESERVED_103[8]; __IO uint32_t MCS0_CH7_R0; /**< MCS[i] channel x general purpose register [y], offset: 0x2700 */ __IO uint32_t MCS0_CH7_R1; /**< MCS[i] channel x general purpose register [y], offset: 0x2704 */ __IO uint32_t MCS0_CH7_R2; /**< MCS[i] channel x general purpose register [y], offset: 0x2708 */ __IO uint32_t MCS0_CH7_R3; /**< MCS[i] channel x general purpose register [y], offset: 0x270C */ __IO uint32_t MCS0_CH7_R4; /**< MCS[i] channel x general purpose register [y], offset: 0x2710 */ __IO uint32_t MCS0_CH7_R5; /**< MCS[i] channel x general purpose register [y], offset: 0x2714 */ __IO uint32_t MCS0_CH7_R6; /**< MCS[i] channel x general purpose register [y], offset: 0x2718 */ __IO uint32_t MCS0_CH7_R7; /**< MCS[i] channel x general purpose register [y], offset: 0x271C */ __IO uint32_t MCS0_CH7_CTRL; /**< MCS[i] channel x control register, offset: 0x2720 */ __I uint32_t MCS0_CH7_ACB; /**< MCS[i] channel x ARU control Bit register, offset: 0x2724 */ uint8_t RESERVED_104[20]; __I uint32_t MCS0_CH7_MHB; /**< MCS[i] channel x memory high byte register, offset: 0x273C */ uint8_t RESERVED_105[160]; __IO uint32_t MCS0_CH7_PC; /**< MCS[i] channel x program counter register, offset: 0x27E0 */ __IO uint32_t MCS0_CH7_IRQ_NOTIFY; /**< MCS[i] channel x interrupt notification register, offset: 0x27E4 */ __IO uint32_t MCS0_CH7_IRQ_EN; /**< MCS[i] channel x interrupt enable register, offset: 0x27E8 */ __IO uint32_t MCS0_CH7_IRQ_FORCINT; /**< MCS[i] channel x force interrupt register, offset: 0x27EC */ __IO uint32_t MCS0_CH7_IRQ_MODE; /**< MCS[i] channel x IRQ mode configuration register, offset: 0x27F0 */ __IO uint32_t MCS0_CH7_EIRQ_EN; /**< MCS[i] channel x error interrupt enable register, offset: 0x27F4 */ uint8_t RESERVED_106[1584]; __IO uint32_t MCS0_CTRG; /**< MCS[i] clear trigger control register, offset: 0x2E28 */ __IO uint32_t MCS0_STRG; /**< MCS[i] set trigger control register, offset: 0x2E2C */ uint8_t RESERVED_107[208]; __IO uint32_t MCS0_CTRL_STAT; /**< MCS[i] control and status register, offset: 0x2F00 */ __IO uint32_t MCS0_RESET; /**< MCS[i] reset register, offset: 0x2F04 */ __IO uint32_t MCS0_CAT; /**< MCS[i] cancel ARU transfer instruction, offset: 0x2F08 */ __IO uint32_t MCS0_CWT; /**< MCS[i] cancel waiting instruction, offset: 0x2F0C */ __IO uint32_t MCS0_ERR; /**< MCS[i] error register, offset: 0x2F10 */ uint8_t RESERVED_108[8]; __IO uint32_t MCS0_REG_PROT; /**< MCS[i] write protection register, offset: 0x2F1C */ __IO uint32_t MCS0_SINT_IRQ_NOTIFY; /**< MCS[i] shared interrupt notification register, offset: 0x2F20 */ __IO uint32_t MCS0_SINT_IRQ_EN; /**< MCS[i] shared interrupt enable register, offset: 0x2F24 */ __IO uint32_t MCS0_SINT_IRQ_FORCINT; /**< MCS[i] force shared interrupt register, offset: 0x2F28 */ __IO uint32_t MCS0_SINT_IRQ_MODE; /**< MCS[i] shared interrupt mode configuration register, offset: 0x2F2C */ uint8_t RESERVED_109[16]; __IO uint32_t MCS0_HBP0_CTRL; /**< MCS[i] hardware break point h control register, offset: 0x2F40 */ __IO uint32_t MCS0_HBP0_PATTERN; /**< MCS[i] hardware break point pattern register, offset: 0x2F44 */ __IO uint32_t MCS0_HBP0_STATUS; /**< MCS[i] hardware break point status register, offset: 0x2F48 */ __IO uint32_t MCS0_HBP0_IRQ_NOTIFY; /**< MCS[i] hardware break point interrupt notification register, offset: 0x2F4C */ __IO uint32_t MCS0_HBP0_IRQ_EN; /**< MCS[i] hardware break point interrupt enable register, offset: 0x2F50 */ __IO uint32_t MCS0_HBP0_IRQ_FORCINT; /**< MCS[i] force hardware break point interrupt register, offset: 0x2F54 */ __IO uint32_t MCS0_HBP0_IRQ_MODE; /**< MCS[i] break point h interrupt mode configuration register, offset: 0x2F58 */ uint8_t RESERVED_110[4]; __IO uint32_t MCS0_HBP1_CTRL; /**< MCS[i] hardware break point h control register, offset: 0x2F60 */ __IO uint32_t MCS0_HBP1_PATTERN; /**< MCS[i] hardware break point pattern register, offset: 0x2F64 */ __IO uint32_t MCS0_HBP1_STATUS; /**< MCS[i] hardware break point status register, offset: 0x2F68 */ __IO uint32_t MCS0_HBP1_IRQ_NOTIFY; /**< MCS[i] hardware break point interrupt notification register, offset: 0x2F6C */ __IO uint32_t MCS0_HBP1_IRQ_EN; /**< MCS[i] hardware break point interrupt enable register, offset: 0x2F70 */ __IO uint32_t MCS0_HBP1_IRQ_FORCINT; /**< MCS[i] force hardware break point interrupt register, offset: 0x2F74 */ __IO uint32_t MCS0_HBP1_IRQ_MODE; /**< MCS[i] break point h interrupt mode configuration register, offset: 0x2F78 */ uint8_t RESERVED_111[4228]; __IO uint32_t CCM0_ARP0_CTRL; /**< CCM[i] Address Range Protector [a] Control Register, offset: 0x4000 */ __IO uint32_t CCM0_ARP0_PROT; /**< CCM[i] Address Range Protector [a] Protection Register, offset: 0x4004 */ __IO uint32_t CCM0_ARP1_CTRL; /**< CCM[i] Address Range Protector [a] Control Register, offset: 0x4008 */ __IO uint32_t CCM0_ARP1_PROT; /**< CCM[i] Address Range Protector [a] Protection Register, offset: 0x400C */ __IO uint32_t CCM0_ARP2_CTRL; /**< CCM[i] Address Range Protector [a] Control Register, offset: 0x4010 */ __IO uint32_t CCM0_ARP2_PROT; /**< CCM[i] Address Range Protector [a] Protection Register, offset: 0x4014 */ __IO uint32_t CCM0_ARP3_CTRL; /**< CCM[i] Address Range Protector [a] Control Register, offset: 0x4018 */ __IO uint32_t CCM0_ARP3_PROT; /**< CCM[i] Address Range Protector [a] Protection Register, offset: 0x401C */ __IO uint32_t CCM0_ARP4_CTRL; /**< CCM[i] Address Range Protector [a] Control Register, offset: 0x4020 */ __IO uint32_t CCM0_ARP4_PROT; /**< CCM[i] Address Range Protector [a] Protection Register, offset: 0x4024 */ __IO uint32_t CCM0_ARP5_CTRL; /**< CCM[i] Address Range Protector [a] Control Register, offset: 0x4028 */ __IO uint32_t CCM0_ARP5_PROT; /**< CCM[i] Address Range Protector [a] Protection Register, offset: 0x402C */ __IO uint32_t CCM0_ARP6_CTRL; /**< CCM[i] Address Range Protector [a] Control Register, offset: 0x4030 */ __IO uint32_t CCM0_ARP6_PROT; /**< CCM[i] Address Range Protector [a] Protection Register, offset: 0x4034 */ __IO uint32_t CCM0_ARP7_CTRL; /**< CCM[i] Address Range Protector [a] Control Register, offset: 0x4038 */ __IO uint32_t CCM0_ARP7_PROT; /**< CCM[i] Address Range Protector [a] Protection Register, offset: 0x403C */ __IO uint32_t CCM0_ARP8_CTRL; /**< CCM[i] Address Range Protector [a] Control Register, offset: 0x4040 */ __IO uint32_t CCM0_ARP8_PROT; /**< CCM[i] Address Range Protector [a] Protection Register, offset: 0x4044 */ __IO uint32_t CCM0_ARP9_CTRL; /**< CCM[i] Address Range Protector [a] Control Register, offset: 0x4048 */ __IO uint32_t CCM0_ARP9_PROT; /**< CCM[i] Address Range Protector [a] Protection Register, offset: 0x404C */ uint8_t RESERVED_112[388]; __I uint32_t CCM0_HW_CONF2; /**< CCM[i] 2. Hardware Configuration Register, offset: 0x41D4 */ __IO uint32_t CCM0_AEIM_STA; /**< CCM[i] MCS Bus Master Status Register, offset: 0x41D8 */ __I uint32_t CCM0_HW_CONF; /**< CCM[i] Hardware Configuration Register, offset: 0x41DC */ __IO uint32_t CCM0_TIM_AUX_IN_SRC; /**< CCM[i] TIM AUX Input Source Register, offset: 0x41E0 */ __IO uint32_t CCM0_EXT_CAP_EN; /**< CCM[i] External Capture Enable Register, offset: 0x41E4 */ __I uint32_t CCM0_TOM_OUT; /**< CCM[i] TOM Output Register, offset: 0x41E8 */ __I uint32_t CCM0_ATOM_OUT; /**< CCM[i] ATOM Output Register, offset: 0x41EC */ __IO uint32_t CCM0_CMU_CLK_CFG; /**< CCM[i] CMU Clock Configuration Register, offset: 0x41F0 */ __IO uint32_t CCM0_CMU_FXCLK_CFG; /**< CCM[i] CMU Fixed Clock Configuration Register, offset: 0x41F4 */ __IO uint32_t CCM0_CFG; /**< CCM[i] Configuration Register, offset: 0x41F8 */ __IO uint32_t CCM0_PROT; /**< CCM[i] Protection Register, offset: 0x41FC */ uint8_t RESERVED_113[768]; __IO uint32_t CDTM0_DTM4_CTRL; /**< CDTM[i]_DTM[d] global configuration and control register, offset: 0x4500 */ __IO uint32_t CDTM0_DTM4_CH_CTRL1; /**< CDTM[i]_DTM[d] channel control register 1, offset: 0x4504 */ __IO uint32_t CDTM0_DTM4_CH_CTRL2; /**< CDTM[i]_DTM[d] channel control register 2, offset: 0x4508 */ __IO uint32_t CDTM0_DTM4_CH_CTRL2_SR; /**< CDTM[i] DTM[j] channel control register 2 shadow, offset: 0x450C */ __IO uint32_t CDTM0_DTM4_PS_CTRL; /**< CDTM[i]_DTM[d] phase shift unit configuration and control register, offset: 0x4510 */ __IO uint32_t CDTM0_DTM4_CH_DTV[GTM_gtm_cls0_CDTM0_DTM4_CH4_DTV_COUNT]; /**< CDTM[i]_DTM[d] channel [x] dead time reload values, array offset: 0x4514, array step: 0x4 */ __IO uint32_t CDTM0_DTM4_CH_SR; /**< CDTM[i]_DTM[d] channel shadow register, offset: 0x4524 */ __IO uint32_t CDTM0_DTM4_CH_CTRL3; /**< CDTM[i]_DTM[d] channel control register 3, offset: 0x4528 */ __IO uint32_t CDTM0_DTM4_CTRL2; /**< CDTM[i]_DTM[d] global configuration and control register 2, offset: 0x452C */ __IO uint32_t CDTM0_DTM4_CH0_DTV_SR; /**< CDTM[i]_DTM[d] channel [x] dead time shadow values, offset: 0x4530 */ __IO uint32_t CDTM0_DTM4_CH1_DTV_SR; /**< CDTM[i]_DTM[d] channel [x] dead time shadow values, offset: 0x4534 */ __IO uint32_t CDTM0_DTM4_CH2_DTV_SR; /**< CDTM[i]_DTM[d] channel [x] dead time shadow values, offset: 0x4538 */ __IO uint32_t CDTM0_DTM4_CH3_DTV_SR; /**< CDTM[i]_DTM[d] channel [x] dead time shadow values, offset: 0x453C */ __IO uint32_t CDTM0_DTM5_CTRL; /**< CDTM[i]_DTM[d] global configuration and control register, offset: 0x4540 */ __IO uint32_t CDTM0_DTM5_CH_CTRL1; /**< CDTM[i]_DTM[d] channel control register 1, offset: 0x4544 */ __IO uint32_t CDTM0_DTM5_CH_CTRL2; /**< CDTM[i]_DTM[d] channel control register 2, offset: 0x4548 */ __IO uint32_t CDTM0_DTM5_CH_CTRL2_SR; /**< CDTM[i] DTM[j] channel control register 2 shadow, offset: 0x454C */ __IO uint32_t CDTM0_DTM5_PS_CTRL; /**< CDTM[i]_DTM[d] phase shift unit configuration and control register, offset: 0x4550 */ __IO uint32_t CDTM0_DTM5_CH_DTV[GTM_gtm_cls0_CDTM0_DTM5_CH4_DTV_COUNT]; /**< CDTM[i]_DTM[d] channel [x] dead time reload values, array offset: 0x4554, array step: 0x4 */ __IO uint32_t CDTM0_DTM5_CH_SR; /**< CDTM[i]_DTM[d] channel shadow register, offset: 0x4564 */ __IO uint32_t CDTM0_DTM5_CH_CTRL3; /**< CDTM[i]_DTM[d] channel control register 3, offset: 0x4568 */ __IO uint32_t CDTM0_DTM5_CTRL2; /**< CDTM[i]_DTM[d] global configuration and control register 2, offset: 0x456C */ __IO uint32_t CDTM0_DTM5_CH0_DTV_SR; /**< CDTM[i]_DTM[d] channel [x] dead time shadow values, offset: 0x4570 */ __IO uint32_t CDTM0_DTM5_CH1_DTV_SR; /**< CDTM[i]_DTM[d] channel [x] dead time shadow values, offset: 0x4574 */ __IO uint32_t CDTM0_DTM5_CH2_DTV_SR; /**< CDTM[i]_DTM[d] channel [x] dead time shadow values, offset: 0x4578 */ __IO uint32_t CDTM0_DTM5_CH3_DTV_SR; /**< CDTM[i]_DTM[d] channel [x] dead time shadow values, offset: 0x457C */ uint8_t RESERVED_114[640]; __IO uint32_t F2A0_CH0_ARU_RD_FIFO; /**< F2A[i] stream [x] ARU read register, offset: 0x4800 */ __IO uint32_t F2A0_CH1_ARU_RD_FIFO; /**< F2A[i] stream [x] ARU read register, offset: 0x4804 */ __IO uint32_t F2A0_CH2_ARU_RD_FIFO; /**< F2A[i] stream [x] ARU read register, offset: 0x4808 */ __IO uint32_t F2A0_CH3_ARU_RD_FIFO; /**< F2A[i] stream [x] ARU read register, offset: 0x480C */ __IO uint32_t F2A0_CH4_ARU_RD_FIFO; /**< F2A[i] stream [x] ARU read register, offset: 0x4810 */ __IO uint32_t F2A0_CH5_ARU_RD_FIFO; /**< F2A[i] stream [x] ARU read register, offset: 0x4814 */ __IO uint32_t F2A0_CH6_ARU_RD_FIFO; /**< F2A[i] stream [x] ARU read register, offset: 0x4818 */ __IO uint32_t F2A0_CH7_ARU_RD_FIFO; /**< F2A[i] stream [x] ARU read register, offset: 0x481C */ __IO uint32_t F2A0_CH0_STR_CFG; /**< F2A[i] stream [x] configuration register, offset: 0x4820 */ __IO uint32_t F2A0_CH1_STR_CFG; /**< F2A[i] stream [x] configuration register, offset: 0x4824 */ __IO uint32_t F2A0_CH2_STR_CFG; /**< F2A[i] stream [x] configuration register, offset: 0x4828 */ __IO uint32_t F2A0_CH3_STR_CFG; /**< F2A[i] stream [x] configuration register, offset: 0x482C */ __IO uint32_t F2A0_CH4_STR_CFG; /**< F2A[i] stream [x] configuration register, offset: 0x4830 */ __IO uint32_t F2A0_CH5_STR_CFG; /**< F2A[i] stream [x] configuration register, offset: 0x4834 */ __IO uint32_t F2A0_CH6_STR_CFG; /**< F2A[i] stream [x] configuration register, offset: 0x4838 */ __IO uint32_t F2A0_CH7_STR_CFG; /**< F2A[i] stream [x] configuration register, offset: 0x483C */ __IO uint32_t F2A0_ENABLE; /**< F2A[i] stream activation register, offset: 0x4840 */ __IO uint32_t F2A0_CTRL; /**< F2A[i] stream control register, offset: 0x4844 */ uint8_t RESERVED_115[56]; __IO uint32_t AFD0_CH0_BUF_ACC; /**< AFD [i] FIFO [x] buffer access register, offset: 0x4880 */ uint8_t RESERVED_116[12]; __IO uint32_t AFD0_CH1_BUF_ACC; /**< AFD [i] FIFO [x] buffer access register, offset: 0x4890 */ uint8_t RESERVED_117[12]; __IO uint32_t AFD0_CH2_BUF_ACC; /**< AFD [i] FIFO [x] buffer access register, offset: 0x48A0 */ uint8_t RESERVED_118[12]; __IO uint32_t AFD0_CH3_BUF_ACC; /**< AFD [i] FIFO [x] buffer access register, offset: 0x48B0 */ uint8_t RESERVED_119[12]; __IO uint32_t AFD0_CH4_BUF_ACC; /**< AFD [i] FIFO [x] buffer access register, offset: 0x48C0 */ uint8_t RESERVED_120[12]; __IO uint32_t AFD0_CH5_BUF_ACC; /**< AFD [i] FIFO [x] buffer access register, offset: 0x48D0 */ uint8_t RESERVED_121[12]; __IO uint32_t AFD0_CH6_BUF_ACC; /**< AFD [i] FIFO [x] buffer access register, offset: 0x48E0 */ uint8_t RESERVED_122[12]; __IO uint32_t AFD0_CH7_BUF_ACC; /**< AFD [i] FIFO [x] buffer access register, offset: 0x48F0 */ uint8_t RESERVED_123[268]; __IO uint32_t FIFO0_CH0_CTRL; /**< FIFO[i] channel [x] control register, offset: 0x4A00 */ __IO uint32_t FIFO0_CH0_END_ADDR; /**< FIFO[i] channel [x] end address register, offset: 0x4A04 */ __IO uint32_t FIFO0_CH0_START_ADDR; /**< FIFO[i] channel [x] start address register, offset: 0x4A08 */ __IO uint32_t FIFO0_CH0_UPPER_WM; /**< FIFO[i] channel [x] upper watermark register, offset: 0x4A0C */ __IO uint32_t FIFO0_CH0_LOWER_WM; /**< FIFO[i] channel [x] lower watermark register, offset: 0x4A10 */ __I uint32_t FIFO0_CH0_STATUS; /**< FIFO[i] channel [x] status register, offset: 0x4A14 */ __I uint32_t FIFO0_CH0_FILL_LEVEL; /**< FIFO[i] channel [x] fill level register, offset: 0x4A18 */ __I uint32_t FIFO0_CH0_WR_PTR; /**< FIFO[i] channel [x] write pointer register, offset: 0x4A1C */ __I uint32_t FIFO0_CH0_RD_PTR; /**< FIFO[i] channel [x] read pointer register, offset: 0x4A20 */ __IO uint32_t FIFO0_CH0_IRQ_NOTIFY; /**< FIFO[i] channel [x] interrupt notification register, offset: 0x4A24 */ __IO uint32_t FIFO0_CH0_IRQ_EN; /**< FIFO[i] channel [x] interrupt enable register, offset: 0x4A28 */ __IO uint32_t FIFO0_CH0_IRQ_FORCINT; /**< FIFO[i] channel [x] force interrupt register, offset: 0x4A2C */ __IO uint32_t FIFO0_CH0_IRQ_MODE; /**< FIFO[i] channel [x] interrupt mode control register, offset: 0x4A30 */ __IO uint32_t FIFO0_CH0_EIRQ_EN; /**< FIFO[i] channel [x] error interrupt enable register, offset: 0x4A34 */ uint8_t RESERVED_124[8]; __IO uint32_t FIFO0_CH1_CTRL; /**< FIFO[i] channel [x] control register, offset: 0x4A40 */ __IO uint32_t FIFO0_CH1_END_ADDR; /**< FIFO[i] channel [x] end address register, offset: 0x4A44 */ __IO uint32_t FIFO0_CH1_START_ADDR; /**< FIFO[i] channel [x] start address register, offset: 0x4A48 */ __IO uint32_t FIFO0_CH1_UPPER_WM; /**< FIFO[i] channel [x] upper watermark register, offset: 0x4A4C */ __IO uint32_t FIFO0_CH1_LOWER_WM; /**< FIFO[i] channel [x] lower watermark register, offset: 0x4A50 */ __I uint32_t FIFO0_CH1_STATUS; /**< FIFO[i] channel [x] status register, offset: 0x4A54 */ __I uint32_t FIFO0_CH1_FILL_LEVEL; /**< FIFO[i] channel [x] fill level register, offset: 0x4A58 */ __I uint32_t FIFO0_CH1_WR_PTR; /**< FIFO[i] channel [x] write pointer register, offset: 0x4A5C */ __I uint32_t FIFO0_CH1_RD_PTR; /**< FIFO[i] channel [x] read pointer register, offset: 0x4A60 */ __IO uint32_t FIFO0_CH1_IRQ_NOTIFY; /**< FIFO[i] channel [x] interrupt notification register, offset: 0x4A64 */ __IO uint32_t FIFO0_CH1_IRQ_EN; /**< FIFO[i] channel [x] interrupt enable register, offset: 0x4A68 */ __IO uint32_t FIFO0_CH1_IRQ_FORCINT; /**< FIFO[i] channel [x] force interrupt register, offset: 0x4A6C */ __IO uint32_t FIFO0_CH1_IRQ_MODE; /**< FIFO[i] channel [x] interrupt mode control register, offset: 0x4A70 */ __IO uint32_t FIFO0_CH1_EIRQ_EN; /**< FIFO[i] channel [x] error interrupt enable register, offset: 0x4A74 */ uint8_t RESERVED_125[8]; __IO uint32_t FIFO0_CH2_CTRL; /**< FIFO[i] channel [x] control register, offset: 0x4A80 */ __IO uint32_t FIFO0_CH2_END_ADDR; /**< FIFO[i] channel [x] end address register, offset: 0x4A84 */ __IO uint32_t FIFO0_CH2_START_ADDR; /**< FIFO[i] channel [x] start address register, offset: 0x4A88 */ __IO uint32_t FIFO0_CH2_UPPER_WM; /**< FIFO[i] channel [x] upper watermark register, offset: 0x4A8C */ __IO uint32_t FIFO0_CH2_LOWER_WM; /**< FIFO[i] channel [x] lower watermark register, offset: 0x4A90 */ __I uint32_t FIFO0_CH2_STATUS; /**< FIFO[i] channel [x] status register, offset: 0x4A94 */ __I uint32_t FIFO0_CH2_FILL_LEVEL; /**< FIFO[i] channel [x] fill level register, offset: 0x4A98 */ __I uint32_t FIFO0_CH2_WR_PTR; /**< FIFO[i] channel [x] write pointer register, offset: 0x4A9C */ __I uint32_t FIFO0_CH2_RD_PTR; /**< FIFO[i] channel [x] read pointer register, offset: 0x4AA0 */ __IO uint32_t FIFO0_CH2_IRQ_NOTIFY; /**< FIFO[i] channel [x] interrupt notification register, offset: 0x4AA4 */ __IO uint32_t FIFO0_CH2_IRQ_EN; /**< FIFO[i] channel [x] interrupt enable register, offset: 0x4AA8 */ __IO uint32_t FIFO0_CH2_IRQ_FORCINT; /**< FIFO[i] channel [x] force interrupt register, offset: 0x4AAC */ __IO uint32_t FIFO0_CH2_IRQ_MODE; /**< FIFO[i] channel [x] interrupt mode control register, offset: 0x4AB0 */ __IO uint32_t FIFO0_CH2_EIRQ_EN; /**< FIFO[i] channel [x] error interrupt enable register, offset: 0x4AB4 */ uint8_t RESERVED_126[8]; __IO uint32_t FIFO0_CH3_CTRL; /**< FIFO[i] channel [x] control register, offset: 0x4AC0 */ __IO uint32_t FIFO0_CH3_END_ADDR; /**< FIFO[i] channel [x] end address register, offset: 0x4AC4 */ __IO uint32_t FIFO0_CH3_START_ADDR; /**< FIFO[i] channel [x] start address register, offset: 0x4AC8 */ __IO uint32_t FIFO0_CH3_UPPER_WM; /**< FIFO[i] channel [x] upper watermark register, offset: 0x4ACC */ __IO uint32_t FIFO0_CH3_LOWER_WM; /**< FIFO[i] channel [x] lower watermark register, offset: 0x4AD0 */ __I uint32_t FIFO0_CH3_STATUS; /**< FIFO[i] channel [x] status register, offset: 0x4AD4 */ __I uint32_t FIFO0_CH3_FILL_LEVEL; /**< FIFO[i] channel [x] fill level register, offset: 0x4AD8 */ __I uint32_t FIFO0_CH3_WR_PTR; /**< FIFO[i] channel [x] write pointer register, offset: 0x4ADC */ __I uint32_t FIFO0_CH3_RD_PTR; /**< FIFO[i] channel [x] read pointer register, offset: 0x4AE0 */ __IO uint32_t FIFO0_CH3_IRQ_NOTIFY; /**< FIFO[i] channel [x] interrupt notification register, offset: 0x4AE4 */ __IO uint32_t FIFO0_CH3_IRQ_EN; /**< FIFO[i] channel [x] interrupt enable register, offset: 0x4AE8 */ __IO uint32_t FIFO0_CH3_IRQ_FORCINT; /**< FIFO[i] channel [x] force interrupt register, offset: 0x4AEC */ __IO uint32_t FIFO0_CH3_IRQ_MODE; /**< FIFO[i] channel [x] interrupt mode control register, offset: 0x4AF0 */ __IO uint32_t FIFO0_CH3_EIRQ_EN; /**< FIFO[i] channel [x] error interrupt enable register, offset: 0x4AF4 */ uint8_t RESERVED_127[8]; __IO uint32_t FIFO0_CH4_CTRL; /**< FIFO[i] channel [x] control register, offset: 0x4B00 */ __IO uint32_t FIFO0_CH4_END_ADDR; /**< FIFO[i] channel [x] end address register, offset: 0x4B04 */ __IO uint32_t FIFO0_CH4_START_ADDR; /**< FIFO[i] channel [x] start address register, offset: 0x4B08 */ __IO uint32_t FIFO0_CH4_UPPER_WM; /**< FIFO[i] channel [x] upper watermark register, offset: 0x4B0C */ __IO uint32_t FIFO0_CH4_LOWER_WM; /**< FIFO[i] channel [x] lower watermark register, offset: 0x4B10 */ __I uint32_t FIFO0_CH4_STATUS; /**< FIFO[i] channel [x] status register, offset: 0x4B14 */ __I uint32_t FIFO0_CH4_FILL_LEVEL; /**< FIFO[i] channel [x] fill level register, offset: 0x4B18 */ __I uint32_t FIFO0_CH4_WR_PTR; /**< FIFO[i] channel [x] write pointer register, offset: 0x4B1C */ __I uint32_t FIFO0_CH4_RD_PTR; /**< FIFO[i] channel [x] read pointer register, offset: 0x4B20 */ __IO uint32_t FIFO0_CH4_IRQ_NOTIFY; /**< FIFO[i] channel [x] interrupt notification register, offset: 0x4B24 */ __IO uint32_t FIFO0_CH4_IRQ_EN; /**< FIFO[i] channel [x] interrupt enable register, offset: 0x4B28 */ __IO uint32_t FIFO0_CH4_IRQ_FORCINT; /**< FIFO[i] channel [x] force interrupt register, offset: 0x4B2C */ __IO uint32_t FIFO0_CH4_IRQ_MODE; /**< FIFO[i] channel [x] interrupt mode control register, offset: 0x4B30 */ __IO uint32_t FIFO0_CH4_EIRQ_EN; /**< FIFO[i] channel [x] error interrupt enable register, offset: 0x4B34 */ uint8_t RESERVED_128[8]; __IO uint32_t FIFO0_CH5_CTRL; /**< FIFO[i] channel [x] control register, offset: 0x4B40 */ __IO uint32_t FIFO0_CH5_END_ADDR; /**< FIFO[i] channel [x] end address register, offset: 0x4B44 */ __IO uint32_t FIFO0_CH5_START_ADDR; /**< FIFO[i] channel [x] start address register, offset: 0x4B48 */ __IO uint32_t FIFO0_CH5_UPPER_WM; /**< FIFO[i] channel [x] upper watermark register, offset: 0x4B4C */ __IO uint32_t FIFO0_CH5_LOWER_WM; /**< FIFO[i] channel [x] lower watermark register, offset: 0x4B50 */ __I uint32_t FIFO0_CH5_STATUS; /**< FIFO[i] channel [x] status register, offset: 0x4B54 */ __I uint32_t FIFO0_CH5_FILL_LEVEL; /**< FIFO[i] channel [x] fill level register, offset: 0x4B58 */ __I uint32_t FIFO0_CH5_WR_PTR; /**< FIFO[i] channel [x] write pointer register, offset: 0x4B5C */ __I uint32_t FIFO0_CH5_RD_PTR; /**< FIFO[i] channel [x] read pointer register, offset: 0x4B60 */ __IO uint32_t FIFO0_CH5_IRQ_NOTIFY; /**< FIFO[i] channel [x] interrupt notification register, offset: 0x4B64 */ __IO uint32_t FIFO0_CH5_IRQ_EN; /**< FIFO[i] channel [x] interrupt enable register, offset: 0x4B68 */ __IO uint32_t FIFO0_CH5_IRQ_FORCINT; /**< FIFO[i] channel [x] force interrupt register, offset: 0x4B6C */ __IO uint32_t FIFO0_CH5_IRQ_MODE; /**< FIFO[i] channel [x] interrupt mode control register, offset: 0x4B70 */ __IO uint32_t FIFO0_CH5_EIRQ_EN; /**< FIFO[i] channel [x] error interrupt enable register, offset: 0x4B74 */ uint8_t RESERVED_129[8]; __IO uint32_t FIFO0_CH6_CTRL; /**< FIFO[i] channel [x] control register, offset: 0x4B80 */ __IO uint32_t FIFO0_CH6_END_ADDR; /**< FIFO[i] channel [x] end address register, offset: 0x4B84 */ __IO uint32_t FIFO0_CH6_START_ADDR; /**< FIFO[i] channel [x] start address register, offset: 0x4B88 */ __IO uint32_t FIFO0_CH6_UPPER_WM; /**< FIFO[i] channel [x] upper watermark register, offset: 0x4B8C */ __IO uint32_t FIFO0_CH6_LOWER_WM; /**< FIFO[i] channel [x] lower watermark register, offset: 0x4B90 */ __I uint32_t FIFO0_CH6_STATUS; /**< FIFO[i] channel [x] status register, offset: 0x4B94 */ __I uint32_t FIFO0_CH6_FILL_LEVEL; /**< FIFO[i] channel [x] fill level register, offset: 0x4B98 */ __I uint32_t FIFO0_CH6_WR_PTR; /**< FIFO[i] channel [x] write pointer register, offset: 0x4B9C */ __I uint32_t FIFO0_CH6_RD_PTR; /**< FIFO[i] channel [x] read pointer register, offset: 0x4BA0 */ __IO uint32_t FIFO0_CH6_IRQ_NOTIFY; /**< FIFO[i] channel [x] interrupt notification register, offset: 0x4BA4 */ __IO uint32_t FIFO0_CH6_IRQ_EN; /**< FIFO[i] channel [x] interrupt enable register, offset: 0x4BA8 */ __IO uint32_t FIFO0_CH6_IRQ_FORCINT; /**< FIFO[i] channel [x] force interrupt register, offset: 0x4BAC */ __IO uint32_t FIFO0_CH6_IRQ_MODE; /**< FIFO[i] channel [x] interrupt mode control register, offset: 0x4BB0 */ __IO uint32_t FIFO0_CH6_EIRQ_EN; /**< FIFO[i] channel [x] error interrupt enable register, offset: 0x4BB4 */ uint8_t RESERVED_130[8]; __IO uint32_t FIFO0_CH7_CTRL; /**< FIFO[i] channel [x] control register, offset: 0x4BC0 */ __IO uint32_t FIFO0_CH7_END_ADDR; /**< FIFO[i] channel [x] end address register, offset: 0x4BC4 */ __IO uint32_t FIFO0_CH7_START_ADDR; /**< FIFO[i] channel [x] start address register, offset: 0x4BC8 */ __IO uint32_t FIFO0_CH7_UPPER_WM; /**< FIFO[i] channel [x] upper watermark register, offset: 0x4BCC */ __IO uint32_t FIFO0_CH7_LOWER_WM; /**< FIFO[i] channel [x] lower watermark register, offset: 0x4BD0 */ __I uint32_t FIFO0_CH7_STATUS; /**< FIFO[i] channel [x] status register, offset: 0x4BD4 */ __I uint32_t FIFO0_CH7_FILL_LEVEL; /**< FIFO[i] channel [x] fill level register, offset: 0x4BD8 */ __I uint32_t FIFO0_CH7_WR_PTR; /**< FIFO[i] channel [x] write pointer register, offset: 0x4BDC */ __I uint32_t FIFO0_CH7_RD_PTR; /**< FIFO[i] channel [x] read pointer register, offset: 0x4BE0 */ __IO uint32_t FIFO0_CH7_IRQ_NOTIFY; /**< FIFO[i] channel [x] interrupt notification register, offset: 0x4BE4 */ __IO uint32_t FIFO0_CH7_IRQ_EN; /**< FIFO[i] channel [x] interrupt enable register, offset: 0x4BE8 */ __IO uint32_t FIFO0_CH7_IRQ_FORCINT; /**< FIFO[i] channel [x] force interrupt register, offset: 0x4BEC */ __IO uint32_t FIFO0_CH7_IRQ_MODE; /**< FIFO[i] channel [x] interrupt mode control register, offset: 0x4BF0 */ __IO uint32_t FIFO0_CH7_EIRQ_EN; /**< FIFO[i] channel [x] error interrupt enable register, offset: 0x4BF4 */ uint8_t RESERVED_131[8]; __IO uint32_t SPE0_CTRL_STAT; /**< SPE[i] Control Status Register, offset: 0x4C00 */ __IO uint32_t SPE0_PAT; /**< SPE[i] Input Pattern Definition Register, offset: 0x4C04 */ __IO uint32_t SPE0_OUT_PAT0; /**< SPE[i] Output Definition Register, offset: 0x4C08 */ __IO uint32_t SPE0_OUT_PAT1; /**< SPE[i] Output Definition Register, offset: 0x4C0C */ __IO uint32_t SPE0_OUT_PAT2; /**< SPE[i] Output Definition Register, offset: 0x4C10 */ __IO uint32_t SPE0_OUT_PAT3; /**< SPE[i] Output Definition Register, offset: 0x4C14 */ __IO uint32_t SPE0_OUT_PAT4; /**< SPE[i] Output Definition Register, offset: 0x4C18 */ __IO uint32_t SPE0_OUT_PAT5; /**< SPE[i] Output Definition Register, offset: 0x4C1C */ __IO uint32_t SPE0_OUT_PAT6; /**< SPE[i] Output Definition Register, offset: 0x4C20 */ __IO uint32_t SPE0_OUT_PAT7; /**< SPE[i] Output Definition Register, offset: 0x4C24 */ __IO uint32_t SPE0_OUT_CTRL; /**< SPE[i] Output Control Register, offset: 0x4C28 */ __IO uint32_t SPE0_IRQ_NOTIFY; /**< SPE[i] Interrupt Notification Register, offset: 0x4C2C */ __IO uint32_t SPE0_IRQ_EN; /**< SPE[i] Interrupt Enable Register, offset: 0x4C30 */ __IO uint32_t SPE0_IRQ_FORCINT; /**< SPE[i] Interrupt Generation By Software, offset: 0x4C34 */ __IO uint32_t SPE0_IRQ_MODE; /**< SPE[i] Interrupt Mode Configuration Register, offset: 0x4C38 */ __IO uint32_t SPE0_EIRQ_EN; /**< SPE[i] Error Interrupt Enable Register, offset: 0x4C3C */ __IO uint32_t SPE0_REV_CNT; /**< SPE[i] Input Revolution Counter, offset: 0x4C40 */ __IO uint32_t SPE0_REV_CMP; /**< SPE[i] Revolution Counter Compare Value, offset: 0x4C44 */ __IO uint32_t SPE0_CTRL_STAT2; /**< SPE[i] Control Status Register 2, offset: 0x4C48 */ __IO uint32_t SPE0_CMD; /**< SPE[i] Command Register, offset: 0x4C4C */ uint8_t RESERVED_132[944]; __I uint32_t AXIM0_FREE; /**< AXIM[i] slot allocation status., offset: 0x5000 */ __I uint32_t AXIM0_REQUEST; /**< AXIM[i] slot request (allocation)., offset: 0x5004 */ __IO uint32_t AXIM0_RELEASE; /**< AXIM[i] slot release (de-allocation)., offset: 0x5008 */ uint8_t RESERVED_133[20]; __IO uint32_t AXIM0_SLOT0_ADDR_LOW; /**< AXIM[i] slot[s] address bits 31:0 of AXI transaction., offset: 0x5020 */ uint8_t RESERVED_134[4]; __IO uint32_t AXIM0_SLOT0_DATA_LOW; /**< AXIM[i] slot[s] data bits 31:0 of AXI transaction., offset: 0x5028 */ uint8_t RESERVED_135[4]; __IO uint32_t AXIM0_SLOT0_CFG1; /**< AXIM[i] slot [s] configuration 1, offset: 0x5030 */ __IO uint32_t AXIM0_SLOT0_CFG2; /**< AXIM[i] slot[s] configuration 2, offset: 0x5034 */ __I uint32_t AXIM0_SLOT0_STATUS; /**< AXIM[i] slot[s] status, offset: 0x5038 */ uint8_t RESERVED_136[4]; __IO uint32_t AXIM0_SLOT1_ADDR_LOW; /**< AXIM[i] slot[s] address bits 31:0 of AXI transaction., offset: 0x5040 */ uint8_t RESERVED_137[4]; __IO uint32_t AXIM0_SLOT1_DATA_LOW; /**< AXIM[i] slot[s] data bits 31:0 of AXI transaction., offset: 0x5048 */ uint8_t RESERVED_138[4]; __IO uint32_t AXIM0_SLOT1_CFG1; /**< AXIM[i] slot [s] configuration 1, offset: 0x5050 */ __IO uint32_t AXIM0_SLOT1_CFG2; /**< AXIM[i] slot[s] configuration 2, offset: 0x5054 */ __I uint32_t AXIM0_SLOT1_STATUS; /**< AXIM[i] slot[s] status, offset: 0x5058 */ uint8_t RESERVED_139[4]; __IO uint32_t AXIM0_SLOT2_ADDR_LOW; /**< AXIM[i] slot[s] address bits 31:0 of AXI transaction., offset: 0x5060 */ uint8_t RESERVED_140[4]; __IO uint32_t AXIM0_SLOT2_DATA_LOW; /**< AXIM[i] slot[s] data bits 31:0 of AXI transaction., offset: 0x5068 */ uint8_t RESERVED_141[4]; __IO uint32_t AXIM0_SLOT2_CFG1; /**< AXIM[i] slot [s] configuration 1, offset: 0x5070 */ __IO uint32_t AXIM0_SLOT2_CFG2; /**< AXIM[i] slot[s] configuration 2, offset: 0x5074 */ __I uint32_t AXIM0_SLOT2_STATUS; /**< AXIM[i] slot[s] status, offset: 0x5078 */ uint8_t RESERVED_142[4]; __IO uint32_t AXIM0_SLOT3_ADDR_LOW; /**< AXIM[i] slot[s] address bits 31:0 of AXI transaction., offset: 0x5080 */ uint8_t RESERVED_143[4]; __IO uint32_t AXIM0_SLOT3_DATA_LOW; /**< AXIM[i] slot[s] data bits 31:0 of AXI transaction., offset: 0x5088 */ uint8_t RESERVED_144[4]; __IO uint32_t AXIM0_SLOT3_CFG1; /**< AXIM[i] slot [s] configuration 1, offset: 0x5090 */ __IO uint32_t AXIM0_SLOT3_CFG2; /**< AXIM[i] slot[s] configuration 2, offset: 0x5094 */ __I uint32_t AXIM0_SLOT3_STATUS; /**< AXIM[i] slot[s] status, offset: 0x5098 */ uint8_t RESERVED_145[3940]; __IO uint32_t FIFO0_MEMORY[GTM_gtm_cls0_FIFO0_MEMORY_COUNT]; /**< FIFO data memory, array offset: 0x6000, array step: 0x4 */ uint8_t RESERVED_146[4096]; __IO uint32_t DPLL_CTRL_0; /**< Control Register 0, offset: 0x8000 */ __IO uint32_t DPLL_CTRL_1; /**< Control Register 1, offset: 0x8004 */ __IO uint32_t DPLL_CTRL_2; /**< Action Enable Register, offset: 0x8008 */ __IO uint32_t DPLL_CTRL_3; /**< Action Enable Register, offset: 0x800C */ __IO uint32_t DPLL_CTRL_4; /**< Action Enable Register, offset: 0x8010 */ __IO uint32_t DPLL_CTRL_5; /**< Action Enable Register, offset: 0x8014 */ __IO uint32_t DPLL_ACT_STA; /**< Action Status Register including Shadow Register, offset: 0x8018 */ __IO uint32_t DPLL_OSW; /**< Offset and Switch old/new Address Register, offset: 0x801C */ __I uint32_t DPLL_AOSV_2; /**< Address Offset Register of RAM 2 Regions, offset: 0x8020 */ __IO uint32_t DPLL_APT; /**< Actual RAM Pointer Address for TRIGGER, offset: 0x8024 */ __IO uint32_t DPLL_APS; /**< Actual RAM Pointer Address for STATE, offset: 0x8028 */ __IO uint32_t DPLL_APT_2C; /**< Actual RAM Pointer Address for Region 2c, offset: 0x802C */ __IO uint32_t DPLL_APS_1C3; /**< Actual RAM Pointer Address for RAM region 1c3, offset: 0x8030 */ __IO uint32_t DPLL_NUTC; /**< Number of Recent TRIGGER Events used for Calculations, offset: 0x8034 */ __IO uint32_t DPLL_NUSC; /**< Number of Recent STATE Events used for Calculations, offset: 0x8038 */ __IO uint32_t DPLL_NTI_CNT; /**< Number of Active TRIGGER Events to Interrupt, offset: 0x803C */ __IO uint32_t DPLL_IRQ_NOTIFY; /**< Interrupt Register, offset: 0x8040 */ __IO uint32_t DPLL_IRQ_EN; /**< Interrupt Enable Register, offset: 0x8044 */ __IO uint32_t DPLL_IRQ_FORCINT; /**< Force Interrupt Register, offset: 0x8048 */ __IO uint32_t DPLL_IRQ_MODE; /**< Interrupt Request Mode, offset: 0x804C */ __IO uint32_t DPLL_EIRQ_EN; /**< Error Interrupt Enable Register, offset: 0x8050 */ uint8_t RESERVED_147[92]; __IO uint32_t DPLL_INC_CNT1; /**< Counter Value of Sent SUB_INC1 Pulses, offset: 0x80B0 */ __IO uint32_t DPLL_INC_CNT2; /**< Counter Value of sent SUB_INC2 values (for DPLL_CTRL_1.SMC=1 and DPLL_CTRL_0.RMO=1), offset: 0x80B4 */ __IO uint32_t DPLL_APT_SYNC; /**< TRIGGER Time Stamp Field Offset at Synchronization Time, offset: 0x80B8 */ __IO uint32_t DPLL_APS_SYNC; /**< STATE Time Stamp Field Offset at Synchronization Time, offset: 0x80BC */ __IO uint32_t DPLL_TBU_TS0_T; /**< Time Stamp Value for the last active TRIGGER, offset: 0x80C0 */ __IO uint32_t DPLL_TBU_TS0_S; /**< Time Stamp Value for the last active STATE, offset: 0x80C4 */ __IO uint32_t DPLL_ADD_IN_LD1; /**< ADD_IN Value in Direct Load Mode for TRIGGER, offset: 0x80C8 */ __IO uint32_t DPLL_ADD_IN_LD2; /**< ADD_IN Value in Direct Load Mode for STATE, offset: 0x80CC */ uint8_t RESERVED_148[44]; __IO uint32_t DPLL_STATUS; /**< Status Register, offset: 0x80FC */ __IO uint32_t DPLL_ID_PMTR_0; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x8100 */ __IO uint32_t DPLL_ID_PMTR_1; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x8104 */ __IO uint32_t DPLL_ID_PMTR_2; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x8108 */ __IO uint32_t DPLL_ID_PMTR_3; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x810C */ __IO uint32_t DPLL_ID_PMTR_4; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x8110 */ __IO uint32_t DPLL_ID_PMTR_5; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x8114 */ __IO uint32_t DPLL_ID_PMTR_6; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x8118 */ __IO uint32_t DPLL_ID_PMTR_7; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x811C */ __IO uint32_t DPLL_ID_PMTR_8; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x8120 */ __IO uint32_t DPLL_ID_PMTR_9; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x8124 */ __IO uint32_t DPLL_ID_PMTR_10; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x8128 */ __IO uint32_t DPLL_ID_PMTR_11; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x812C */ __IO uint32_t DPLL_ID_PMTR_12; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x8130 */ __IO uint32_t DPLL_ID_PMTR_13; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x8134 */ __IO uint32_t DPLL_ID_PMTR_14; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x8138 */ __IO uint32_t DPLL_ID_PMTR_15; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x813C */ __IO uint32_t DPLL_ID_PMTR_16; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x8140 */ __IO uint32_t DPLL_ID_PMTR_17; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x8144 */ __IO uint32_t DPLL_ID_PMTR_18; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x8148 */ __IO uint32_t DPLL_ID_PMTR_19; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x814C */ __IO uint32_t DPLL_ID_PMTR_20; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x8150 */ __IO uint32_t DPLL_ID_PMTR_21; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x8154 */ __IO uint32_t DPLL_ID_PMTR_22; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x8158 */ __IO uint32_t DPLL_ID_PMTR_23; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x815C */ __IO uint32_t DPLL_ID_PMTR_24; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x8160 */ __IO uint32_t DPLL_ID_PMTR_25; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x8164 */ __IO uint32_t DPLL_ID_PMTR_26; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x8168 */ __IO uint32_t DPLL_ID_PMTR_27; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x816C */ __IO uint32_t DPLL_ID_PMTR_28; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x8170 */ __IO uint32_t DPLL_ID_PMTR_29; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x8174 */ __IO uint32_t DPLL_ID_PMTR_30; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x8178 */ __IO uint32_t DPLL_ID_PMTR_31; /**< ID Information for Input Signal PMTR[n] (Position minus Time Request), offset: 0x817C */ uint8_t RESERVED_149[96]; __I uint32_t DPLL_CTRL_0_SHADOW_TRIGGER; /**< Shadow Register of DPLL_CTRL_0 controlled by an active TRIGGER Slope, offset: 0x81E0 */ __I uint32_t DPLL_CTRL_0_SHADOW_STATE; /**< Shadow Register of DPLL_CTRL_0 controlled by an active STATE Slope, offset: 0x81E4 */ __I uint32_t DPLL_CTRL_1_SHADOW_TRIGGER; /**< Shadow Register of DPLL_CTRL_1 controlled by an active TRIGGER Slope, offset: 0x81E8 */ __I uint32_t DPLL_CTRL_1_SHADOW_STATE; /**< DPLL Shadow Register of DPLL_CTRL_1 controlled by an active STATE Slope, offset: 0x81EC */ uint8_t RESERVED_150[12]; __IO uint32_t DPLL_RAM_INI; /**< Register to control the RAM Initialization, offset: 0x81FC */ __IO uint32_t DPLL_PSA0; /**< Position Request for Action [n], offset: 0x8200 */ __IO uint32_t DPLL_PSA1; /**< Position Request for Action [n], offset: 0x8204 */ __IO uint32_t DPLL_PSA2; /**< Position Request for Action [n], offset: 0x8208 */ __IO uint32_t DPLL_PSA3; /**< Position Request for Action [n], offset: 0x820C */ __IO uint32_t DPLL_PSA4; /**< Position Request for Action [n], offset: 0x8210 */ __IO uint32_t DPLL_PSA5; /**< Position Request for Action [n], offset: 0x8214 */ __IO uint32_t DPLL_PSA6; /**< Position Request for Action [n], offset: 0x8218 */ __IO uint32_t DPLL_PSA7; /**< Position Request for Action [n], offset: 0x821C */ __IO uint32_t DPLL_PSA8; /**< Position Request for Action [n], offset: 0x8220 */ __IO uint32_t DPLL_PSA9; /**< Position Request for Action [n], offset: 0x8224 */ __IO uint32_t DPLL_PSA10; /**< Position Request for Action [n], offset: 0x8228 */ __IO uint32_t DPLL_PSA11; /**< Position Request for Action [n], offset: 0x822C */ __IO uint32_t DPLL_PSA12; /**< Position Request for Action [n], offset: 0x8230 */ __IO uint32_t DPLL_PSA13; /**< Position Request for Action [n], offset: 0x8234 */ __IO uint32_t DPLL_PSA14; /**< Position Request for Action [n], offset: 0x8238 */ __IO uint32_t DPLL_PSA15; /**< Position Request for Action [n], offset: 0x823C */ __IO uint32_t DPLL_PSA16; /**< Position Request for Action [n], offset: 0x8240 */ __IO uint32_t DPLL_PSA17; /**< Position Request for Action [n], offset: 0x8244 */ __IO uint32_t DPLL_PSA18; /**< Position Request for Action [n], offset: 0x8248 */ __IO uint32_t DPLL_PSA19; /**< Position Request for Action [n], offset: 0x824C */ __IO uint32_t DPLL_PSA20; /**< Position Request for Action [n], offset: 0x8250 */ __IO uint32_t DPLL_PSA21; /**< Position Request for Action [n], offset: 0x8254 */ __IO uint32_t DPLL_PSA22; /**< Position Request for Action [n], offset: 0x8258 */ __IO uint32_t DPLL_PSA23; /**< Position Request for Action [n], offset: 0x825C */ __IO uint32_t DPLL_PSA24; /**< Position Request for Action [n], offset: 0x8260 */ __IO uint32_t DPLL_PSA25; /**< Position Request for Action [n], offset: 0x8264 */ __IO uint32_t DPLL_PSA26; /**< Position Request for Action [n], offset: 0x8268 */ __IO uint32_t DPLL_PSA27; /**< Position Request for Action [n], offset: 0x826C */ __IO uint32_t DPLL_PSA28; /**< Position Request for Action [n], offset: 0x8270 */ __IO uint32_t DPLL_PSA29; /**< Position Request for Action [n], offset: 0x8274 */ __IO uint32_t DPLL_PSA30; /**< Position Request for Action [n], offset: 0x8278 */ __IO uint32_t DPLL_PSA31; /**< Position Request for Action [n], offset: 0x827C */ __IO uint32_t DPLL_DLA0; /**< Time to React for Action [n], offset: 0x8280 */ __IO uint32_t DPLL_DLA1; /**< Time to React for Action [n], offset: 0x8284 */ __IO uint32_t DPLL_DLA2; /**< Time to React for Action [n], offset: 0x8288 */ __IO uint32_t DPLL_DLA3; /**< Time to React for Action [n], offset: 0x828C */ __IO uint32_t DPLL_DLA4; /**< Time to React for Action [n], offset: 0x8290 */ __IO uint32_t DPLL_DLA5; /**< Time to React for Action [n], offset: 0x8294 */ __IO uint32_t DPLL_DLA6; /**< Time to React for Action [n], offset: 0x8298 */ __IO uint32_t DPLL_DLA7; /**< Time to React for Action [n], offset: 0x829C */ __IO uint32_t DPLL_DLA8; /**< Time to React for Action [n], offset: 0x82A0 */ __IO uint32_t DPLL_DLA9; /**< Time to React for Action [n], offset: 0x82A4 */ __IO uint32_t DPLL_DLA10; /**< Time to React for Action [n], offset: 0x82A8 */ __IO uint32_t DPLL_DLA11; /**< Time to React for Action [n], offset: 0x82AC */ __IO uint32_t DPLL_DLA12; /**< Time to React for Action [n], offset: 0x82B0 */ __IO uint32_t DPLL_DLA13; /**< Time to React for Action [n], offset: 0x82B4 */ __IO uint32_t DPLL_DLA14; /**< Time to React for Action [n], offset: 0x82B8 */ __IO uint32_t DPLL_DLA15; /**< Time to React for Action [n], offset: 0x82BC */ __IO uint32_t DPLL_DLA16; /**< Time to React for Action [n], offset: 0x82C0 */ __IO uint32_t DPLL_DLA17; /**< Time to React for Action [n], offset: 0x82C4 */ __IO uint32_t DPLL_DLA18; /**< Time to React for Action [n], offset: 0x82C8 */ __IO uint32_t DPLL_DLA19; /**< Time to React for Action [n], offset: 0x82CC */ __IO uint32_t DPLL_DLA20; /**< Time to React for Action [n], offset: 0x82D0 */ __IO uint32_t DPLL_DLA21; /**< Time to React for Action [n], offset: 0x82D4 */ __IO uint32_t DPLL_DLA22; /**< Time to React for Action [n], offset: 0x82D8 */ __IO uint32_t DPLL_DLA23; /**< Time to React for Action [n], offset: 0x82DC */ __IO uint32_t DPLL_DLA24; /**< Time to React for Action [n], offset: 0x82E0 */ __IO uint32_t DPLL_DLA25; /**< Time to React for Action [n], offset: 0x82E4 */ __IO uint32_t DPLL_DLA26; /**< Time to React for Action [n], offset: 0x82E8 */ __IO uint32_t DPLL_DLA27; /**< Time to React for Action [n], offset: 0x82EC */ __IO uint32_t DPLL_DLA28; /**< Time to React for Action [n], offset: 0x82F0 */ __IO uint32_t DPLL_DLA29; /**< Time to React for Action [n], offset: 0x82F4 */ __IO uint32_t DPLL_DLA30; /**< Time to React for Action [n], offset: 0x82F8 */ __IO uint32_t DPLL_DLA31; /**< Time to React for Action [n], offset: 0x82FC */ __IO uint32_t DPLL_NA0; /**< Calculated Relative Time to Action [n], offset: 0x8300 */ __IO uint32_t DPLL_NA1; /**< Calculated Relative Time to Action [n], offset: 0x8304 */ __IO uint32_t DPLL_NA2; /**< Calculated Relative Time to Action [n], offset: 0x8308 */ __IO uint32_t DPLL_NA3; /**< Calculated Relative Time to Action [n], offset: 0x830C */ __IO uint32_t DPLL_NA4; /**< Calculated Relative Time to Action [n], offset: 0x8310 */ __IO uint32_t DPLL_NA5; /**< Calculated Relative Time to Action [n], offset: 0x8314 */ __IO uint32_t DPLL_NA6; /**< Calculated Relative Time to Action [n], offset: 0x8318 */ __IO uint32_t DPLL_NA7; /**< Calculated Relative Time to Action [n], offset: 0x831C */ __IO uint32_t DPLL_NA8; /**< Calculated Relative Time to Action [n], offset: 0x8320 */ __IO uint32_t DPLL_NA9; /**< Calculated Relative Time to Action [n], offset: 0x8324 */ __IO uint32_t DPLL_NA10; /**< Calculated Relative Time to Action [n], offset: 0x8328 */ __IO uint32_t DPLL_NA11; /**< Calculated Relative Time to Action [n], offset: 0x832C */ __IO uint32_t DPLL_NA12; /**< Calculated Relative Time to Action [n], offset: 0x8330 */ __IO uint32_t DPLL_NA13; /**< Calculated Relative Time to Action [n], offset: 0x8334 */ __IO uint32_t DPLL_NA14; /**< Calculated Relative Time to Action [n], offset: 0x8338 */ __IO uint32_t DPLL_NA15; /**< Calculated Relative Time to Action [n], offset: 0x833C */ __IO uint32_t DPLL_NA16; /**< Calculated Relative Time to Action [n], offset: 0x8340 */ __IO uint32_t DPLL_NA17; /**< Calculated Relative Time to Action [n], offset: 0x8344 */ __IO uint32_t DPLL_NA18; /**< Calculated Relative Time to Action [n], offset: 0x8348 */ __IO uint32_t DPLL_NA19; /**< Calculated Relative Time to Action [n], offset: 0x834C */ __IO uint32_t DPLL_NA20; /**< Calculated Relative Time to Action [n], offset: 0x8350 */ __IO uint32_t DPLL_NA21; /**< Calculated Relative Time to Action [n], offset: 0x8354 */ __IO uint32_t DPLL_NA22; /**< Calculated Relative Time to Action [n], offset: 0x8358 */ __IO uint32_t DPLL_NA23; /**< Calculated Relative Time to Action [n], offset: 0x835C */ __IO uint32_t DPLL_NA24; /**< Calculated Relative Time to Action [n], offset: 0x8360 */ __IO uint32_t DPLL_NA25; /**< Calculated Relative Time to Action [n], offset: 0x8364 */ __IO uint32_t DPLL_NA26; /**< Calculated Relative Time to Action [n], offset: 0x8368 */ __IO uint32_t DPLL_NA27; /**< Calculated Relative Time to Action [n], offset: 0x836C */ __IO uint32_t DPLL_NA28; /**< Calculated Relative Time to Action [n], offset: 0x8370 */ __IO uint32_t DPLL_NA29; /**< Calculated Relative Time to Action [n], offset: 0x8374 */ __IO uint32_t DPLL_NA30; /**< Calculated Relative Time to Action [n], offset: 0x8378 */ __IO uint32_t DPLL_NA31; /**< Calculated Relative Time to Action [n], offset: 0x837C */ __IO uint32_t DPLL_DTA0; /**< Calculated Relative Time to Action [n], offset: 0x8380 */ __IO uint32_t DPLL_DTA1; /**< Calculated Relative Time to Action [n], offset: 0x8384 */ __IO uint32_t DPLL_DTA2; /**< Calculated Relative Time to Action [n], offset: 0x8388 */ __IO uint32_t DPLL_DTA3; /**< Calculated Relative Time to Action [n], offset: 0x838C */ __IO uint32_t DPLL_DTA4; /**< Calculated Relative Time to Action [n], offset: 0x8390 */ __IO uint32_t DPLL_DTA5; /**< Calculated Relative Time to Action [n], offset: 0x8394 */ __IO uint32_t DPLL_DTA6; /**< Calculated Relative Time to Action [n], offset: 0x8398 */ __IO uint32_t DPLL_DTA7; /**< Calculated Relative Time to Action [n], offset: 0x839C */ __IO uint32_t DPLL_DTA8; /**< Calculated Relative Time to Action [n], offset: 0x83A0 */ __IO uint32_t DPLL_DTA9; /**< Calculated Relative Time to Action [n], offset: 0x83A4 */ __IO uint32_t DPLL_DTA10; /**< Calculated Relative Time to Action [n], offset: 0x83A8 */ __IO uint32_t DPLL_DTA11; /**< Calculated Relative Time to Action [n], offset: 0x83AC */ __IO uint32_t DPLL_DTA12; /**< Calculated Relative Time to Action [n], offset: 0x83B0 */ __IO uint32_t DPLL_DTA13; /**< Calculated Relative Time to Action [n], offset: 0x83B4 */ __IO uint32_t DPLL_DTA14; /**< Calculated Relative Time to Action [n], offset: 0x83B8 */ __IO uint32_t DPLL_DTA15; /**< Calculated Relative Time to Action [n], offset: 0x83BC */ __IO uint32_t DPLL_DTA16; /**< Calculated Relative Time to Action [n], offset: 0x83C0 */ __IO uint32_t DPLL_DTA17; /**< Calculated Relative Time to Action [n], offset: 0x83C4 */ __IO uint32_t DPLL_DTA18; /**< Calculated Relative Time to Action [n], offset: 0x83C8 */ __IO uint32_t DPLL_DTA19; /**< Calculated Relative Time to Action [n], offset: 0x83CC */ __IO uint32_t DPLL_DTA20; /**< Calculated Relative Time to Action [n], offset: 0x83D0 */ __IO uint32_t DPLL_DTA21; /**< Calculated Relative Time to Action [n], offset: 0x83D4 */ __IO uint32_t DPLL_DTA22; /**< Calculated Relative Time to Action [n], offset: 0x83D8 */ __IO uint32_t DPLL_DTA23; /**< Calculated Relative Time to Action [n], offset: 0x83DC */ __IO uint32_t DPLL_DTA24; /**< Calculated Relative Time to Action [n], offset: 0x83E0 */ __IO uint32_t DPLL_DTA25; /**< Calculated Relative Time to Action [n], offset: 0x83E4 */ __IO uint32_t DPLL_DTA26; /**< Calculated Relative Time to Action [n], offset: 0x83E8 */ __IO uint32_t DPLL_DTA27; /**< Calculated Relative Time to Action [n], offset: 0x83EC */ __IO uint32_t DPLL_DTA28; /**< Calculated Relative Time to Action [n], offset: 0x83F0 */ __IO uint32_t DPLL_DTA29; /**< Calculated Relative Time to Action [n], offset: 0x83F4 */ __IO uint32_t DPLL_DTA30; /**< Calculated Relative Time to Action [n], offset: 0x83F8 */ __IO uint32_t DPLL_DTA31; /**< Calculated Relative Time to Action [n], offset: 0x83FC */ __IO uint32_t DPLL_TS_T; /**< Actual TRIGGER Time Stamp Value, offset: 0x8400 */ __IO uint32_t DPLL_TS_T_OLD; /**< Previous TRIGGER Time Stamp Value, offset: 0x8404 */ __IO uint32_t DPLL_FTV_T; /**< Actual TRIGGER Filter value, offset: 0x8408 */ __IO uint32_t DPLL_RAM1B_RSVD_0; /**< DPLL RAM1B reserved data, offset: 0x840C */ __IO uint32_t DPLL_TS_S; /**< Actual STATE Time Stamp Register, offset: 0x8410 */ __IO uint32_t DPLL_TS_S_OLD; /**< Previous STATE Time Stamp Register, offset: 0x8414 */ __IO uint32_t DPLL_FTV_S; /**< Actual STATE Filter Value, offset: 0x8418 */ __IO uint32_t DPLL_RAM1B_RSVD_1; /**< DPLL RAM1B reserved data, offset: 0x841C */ __IO uint32_t DPLL_THMI; /**< TRIGGER Hold Time Min. Value, offset: 0x8420 */ __IO uint32_t DPLL_THMA; /**< TRIGGER Hold Time Max. Value, offset: 0x8424 */ __IO uint32_t DPLL_THVAL; /**< Measured TRIGGER Hold Time Value, offset: 0x8428 */ __IO uint32_t DPLL_RAM1B_RSVD_2; /**< DPLL RAM1B reserved data, offset: 0x842C */ __IO uint32_t DPLL_TOV; /**< Time Out Value of Active TRIGGER Slope (for missing TRIGGER generation), offset: 0x8430 */ __IO uint32_t DPLL_TOV_S; /**< Time Out Value of active STATE Slope (for missing STATE generation), offset: 0x8434 */ __IO uint32_t DPLL_ADD_IN_CAL1; /**< Calculated ADD_IN Value for SUB_INC1 Generation, offset: 0x8438 */ __IO uint32_t DPLL_ADD_IN_CAL2; /**< Calculated ADD_IN Value for SUB_INC2 Generation, offset: 0x843C */ __IO uint32_t DPLL_MPVAL1; /**< Missing Pulses to be Added or Subtracted Directly, offset: 0x8440 */ __IO uint32_t DPLL_MPVAL2; /**< Missing Pulses to be Added or Subtracted Directly, offset: 0x8444 */ __IO uint32_t DPLL_NMB_T_TAR; /**< Target Number of Pulses to be sent in Normal Mode, offset: 0x8448 */ __IO uint32_t DPLL_NMB_T_TAR_OLD; /**< Last but one Target Number of Pulses to be sent in Normal Mode, offset: 0x844C */ __IO uint32_t DPLL_NMB_S_TAR; /**< Target Number of Pulses to be sent in Emergency Mode, offset: 0x8450 */ __IO uint32_t DPLL_NMB_S_TAR_OLD; /**< Last but one Target Number of Pulses to be sent in Emergency Mode, offset: 0x8454 */ __IO uint32_t DPLL_RAM1B_RSVD_3_0; /**< DPLL RAM1B reserved data [k], offset: 0x8458 */ __IO uint32_t DPLL_RAM1B_RSVD_3_1; /**< DPLL RAM1B reserved data [k], offset: 0x845C */ __IO uint32_t DPLL_RCDT_TX; /**< Reciprocal Value of the Expected Increment Duration of TRIGGER, offset: 0x8460 */ __IO uint32_t DPLL_RCDT_SX; /**< Reciprocal Value of the Expected Increment Duration of STATE, offset: 0x8464 */ __IO uint32_t DPLL_RCDT_TX_NOM; /**< Reciprocal Value of the Expected Nominal Increment Duration of TRIGGER, offset: 0x8468 */ __IO uint32_t DPLL_RCDT_SX_NOM; /**< Reciprocal Value of the Expected Nominal Increment Duration of STATE, offset: 0x846C */ __IO uint32_t DPLL_RDT_T_ACT; /**< Reciprocal Value of the Last Increment of TRIGGER, offset: 0x8470 */ __IO uint32_t DPLL_RDT_S_ACT; /**< Reciprocal Value of the Last Increment of STATE, offset: 0x8474 */ __IO uint32_t DPLL_DT_T_ACT; /**< Duration of the Last TRIGGER Increment, offset: 0x8478 */ __IO uint32_t DPLL_DT_S_ACT; /**< Duration of the Last STATE Increment, offset: 0x847C */ __IO uint32_t DPLL_EDT_T; /**< Difference of Prediction to Actual Value of the Last TRIGGER Increment, offset: 0x8480 */ __IO uint32_t DPLL_MEDT_T; /**< Weighted Difference of Prediction Errors of TRIGGER, offset: 0x8484 */ __IO uint32_t DPLL_EDT_S; /**< Difference of Prediction to Actual Value of the Last STATE Increment, offset: 0x8488 */ __IO uint32_t DPLL_MEDT_S; /**< Weighted Difference of Prediction Errors of STATE, offset: 0x848C */ __IO uint32_t DPLL_CDT_TX; /**< Prediction of the Actual TRIGGER Increment Duration, offset: 0x8490 */ __IO uint32_t DPLL_CDT_SX; /**< Prediction of the Actual STATE Increment Duration, offset: 0x8494 */ __IO uint32_t DPLL_CDT_TX_NOM; /**< Prediction of the Nominal TRIGGER Increment Duration, offset: 0x8498 */ __IO uint32_t DPLL_CDT_SX_NOM; /**< Prediction of the Nominal STATE Increment Duration, offset: 0x849C */ __IO uint32_t DPLL_TLR; /**< TRIGGER Locking Range, offset: 0x84A0 */ __IO uint32_t DPLL_SLR; /**< STATE Locking Range, offset: 0x84A4 */ __IO uint32_t DPLL_RAM1B_RSVD_4_0; /**< DPLL RAM1B reserved data [k], offset: 0x84A8 */ __IO uint32_t DPLL_RAM1B_RSVD_4_1; /**< DPLL RAM1B reserved data [k], offset: 0x84AC */ __IO uint32_t DPLL_RAM1B_RSVD_4_2; /**< DPLL RAM1B reserved data [k], offset: 0x84B0 */ __IO uint32_t DPLL_RAM1B_RSVD_4_3; /**< DPLL RAM1B reserved data [k], offset: 0x84B4 */ __IO uint32_t DPLL_RAM1B_RSVD_4_4; /**< DPLL RAM1B reserved data [k], offset: 0x84B8 */ __IO uint32_t DPLL_RAM1B_RSVD_4_5; /**< DPLL RAM1B reserved data [k], offset: 0x84BC */ __IO uint32_t DPLL_RAM1B_RSVD_4_6; /**< DPLL RAM1B reserved data [k], offset: 0x84C0 */ __IO uint32_t DPLL_RAM1B_RSVD_4_7; /**< DPLL RAM1B reserved data [k], offset: 0x84C4 */ __IO uint32_t DPLL_RAM1B_RSVD_4_8; /**< DPLL RAM1B reserved data [k], offset: 0x84C8 */ __IO uint32_t DPLL_RAM1B_RSVD_4_9; /**< DPLL RAM1B reserved data [k], offset: 0x84CC */ __IO uint32_t DPLL_RAM1B_RSVD_4_10; /**< DPLL RAM1B reserved data [k], offset: 0x84D0 */ __IO uint32_t DPLL_RAM1B_RSVD_4_11; /**< DPLL RAM1B reserved data [k], offset: 0x84D4 */ __IO uint32_t DPLL_RAM1B_RSVD_4_12; /**< DPLL RAM1B reserved data [k], offset: 0x84D8 */ __IO uint32_t DPLL_RAM1B_RSVD_4_13; /**< DPLL RAM1B reserved data [k], offset: 0x84DC */ __IO uint32_t DPLL_RAM1B_RSVD_4_14; /**< DPLL RAM1B reserved data [k], offset: 0x84E0 */ __IO uint32_t DPLL_RAM1B_RSVD_4_15; /**< DPLL RAM1B reserved data [k], offset: 0x84E4 */ __IO uint32_t DPLL_RAM1B_RSVD_4_16; /**< DPLL RAM1B reserved data [k], offset: 0x84E8 */ __IO uint32_t DPLL_RAM1B_RSVD_4_17; /**< DPLL RAM1B reserved data [k], offset: 0x84EC */ __IO uint32_t DPLL_RAM1B_RSVD_4_18; /**< DPLL RAM1B reserved data [k], offset: 0x84F0 */ __IO uint32_t DPLL_RAM1B_RSVD_4_19; /**< DPLL RAM1B reserved data [k], offset: 0x84F4 */ __IO uint32_t DPLL_RAM1B_RSVD_4_20; /**< DPLL RAM1B reserved data [k], offset: 0x84F8 */ __IO uint32_t DPLL_RAM1B_RSVD_4_21; /**< DPLL RAM1B reserved data [k], offset: 0x84FC */ __IO uint32_t DPLL_PDT_0; /**< Projected Increment Sum Relations for Action [n], offset: 0x8500 */ __IO uint32_t DPLL_PDT_1; /**< Projected Increment Sum Relations for Action [n], offset: 0x8504 */ __IO uint32_t DPLL_PDT_2; /**< Projected Increment Sum Relations for Action [n], offset: 0x8508 */ __IO uint32_t DPLL_PDT_3; /**< Projected Increment Sum Relations for Action [n], offset: 0x850C */ __IO uint32_t DPLL_PDT_4; /**< Projected Increment Sum Relations for Action [n], offset: 0x8510 */ __IO uint32_t DPLL_PDT_5; /**< Projected Increment Sum Relations for Action [n], offset: 0x8514 */ __IO uint32_t DPLL_PDT_6; /**< Projected Increment Sum Relations for Action [n], offset: 0x8518 */ __IO uint32_t DPLL_PDT_7; /**< Projected Increment Sum Relations for Action [n], offset: 0x851C */ __IO uint32_t DPLL_PDT_8; /**< Projected Increment Sum Relations for Action [n], offset: 0x8520 */ __IO uint32_t DPLL_PDT_9; /**< Projected Increment Sum Relations for Action [n], offset: 0x8524 */ __IO uint32_t DPLL_PDT_10; /**< Projected Increment Sum Relations for Action [n], offset: 0x8528 */ __IO uint32_t DPLL_PDT_11; /**< Projected Increment Sum Relations for Action [n], offset: 0x852C */ __IO uint32_t DPLL_PDT_12; /**< Projected Increment Sum Relations for Action [n], offset: 0x8530 */ __IO uint32_t DPLL_PDT_13; /**< Projected Increment Sum Relations for Action [n], offset: 0x8534 */ __IO uint32_t DPLL_PDT_14; /**< Projected Increment Sum Relations for Action [n], offset: 0x8538 */ __IO uint32_t DPLL_PDT_15; /**< Projected Increment Sum Relations for Action [n], offset: 0x853C */ __IO uint32_t DPLL_PDT_16; /**< Projected Increment Sum Relations for Action [n], offset: 0x8540 */ __IO uint32_t DPLL_PDT_17; /**< Projected Increment Sum Relations for Action [n], offset: 0x8544 */ __IO uint32_t DPLL_PDT_18; /**< Projected Increment Sum Relations for Action [n], offset: 0x8548 */ __IO uint32_t DPLL_PDT_19; /**< Projected Increment Sum Relations for Action [n], offset: 0x854C */ __IO uint32_t DPLL_PDT_20; /**< Projected Increment Sum Relations for Action [n], offset: 0x8550 */ __IO uint32_t DPLL_PDT_21; /**< Projected Increment Sum Relations for Action [n], offset: 0x8554 */ __IO uint32_t DPLL_PDT_22; /**< Projected Increment Sum Relations for Action [n], offset: 0x8558 */ __IO uint32_t DPLL_PDT_23; /**< Projected Increment Sum Relations for Action [n], offset: 0x855C */ __IO uint32_t DPLL_PDT_24; /**< Projected Increment Sum Relations for Action [n], offset: 0x8560 */ __IO uint32_t DPLL_PDT_25; /**< Projected Increment Sum Relations for Action [n], offset: 0x8564 */ __IO uint32_t DPLL_PDT_26; /**< Projected Increment Sum Relations for Action [n], offset: 0x8568 */ __IO uint32_t DPLL_PDT_27; /**< Projected Increment Sum Relations for Action [n], offset: 0x856C */ __IO uint32_t DPLL_PDT_28; /**< Projected Increment Sum Relations for Action [n], offset: 0x8570 */ __IO uint32_t DPLL_PDT_29; /**< Projected Increment Sum Relations for Action [n], offset: 0x8574 */ __IO uint32_t DPLL_PDT_30; /**< Projected Increment Sum Relations for Action [n], offset: 0x8578 */ __IO uint32_t DPLL_PDT_31; /**< Projected Increment Sum Relations for Action [n], offset: 0x857C */ __IO uint32_t DPLL_RAM1B_RSVD_5_0; /**< DPLL RAM1B reserved data [k], offset: 0x8580 */ __IO uint32_t DPLL_RAM1B_RSVD_5_1; /**< DPLL RAM1B reserved data [k], offset: 0x8584 */ __IO uint32_t DPLL_RAM1B_RSVD_5_2; /**< DPLL RAM1B reserved data [k], offset: 0x8588 */ __IO uint32_t DPLL_RAM1B_RSVD_5_3; /**< DPLL RAM1B reserved data [k], offset: 0x858C */ __IO uint32_t DPLL_RAM1B_RSVD_5_4; /**< DPLL RAM1B reserved data [k], offset: 0x8590 */ __IO uint32_t DPLL_RAM1B_RSVD_5_5; /**< DPLL RAM1B reserved data [k], offset: 0x8594 */ __IO uint32_t DPLL_RAM1B_RSVD_5_6; /**< DPLL RAM1B reserved data [k], offset: 0x8598 */ __IO uint32_t DPLL_RAM1B_RSVD_5_7; /**< DPLL RAM1B reserved data [k], offset: 0x859C */ __IO uint32_t DPLL_RAM1B_RSVD_5_8; /**< DPLL RAM1B reserved data [k], offset: 0x85A0 */ __IO uint32_t DPLL_RAM1B_RSVD_5_9; /**< DPLL RAM1B reserved data [k], offset: 0x85A4 */ __IO uint32_t DPLL_RAM1B_RSVD_5_10; /**< DPLL RAM1B reserved data [k], offset: 0x85A8 */ __IO uint32_t DPLL_RAM1B_RSVD_5_11; /**< DPLL RAM1B reserved data [k], offset: 0x85AC */ __IO uint32_t DPLL_RAM1B_RSVD_5_12; /**< DPLL RAM1B reserved data [k], offset: 0x85B0 */ __IO uint32_t DPLL_RAM1B_RSVD_5_13; /**< DPLL RAM1B reserved data [k], offset: 0x85B4 */ __IO uint32_t DPLL_RAM1B_RSVD_5_14; /**< DPLL RAM1B reserved data [k], offset: 0x85B8 */ __IO uint32_t DPLL_RAM1B_RSVD_5_15; /**< DPLL RAM1B reserved data [k], offset: 0x85BC */ __IO uint32_t DPLL_MLS1; /**< Calculated Number of Sub-Pulses between two nominal STATE Events for DPLL_CTRL_1.SMC = 0, offset: 0x85C0 */ __IO uint32_t DPLL_MLS2; /**< Calculated Number of Sub-Pulses between two nominal STATE Events for DPLL_CTRL_1.SMC=1 and RMO=1, offset: 0x85C4 */ __IO uint32_t DPLL_CNT_NUM_1; /**< Number of SUB_INC1 pulses in continuous mode, offset: 0x85C8 */ __IO uint32_t DPLL_CNT_NUM_2; /**< Number of SUB_INC2 pulses in continuous mode, offset: 0x85CC */ __IO uint32_t DPLL_PVT; /**< Plausibility Value of Next TRIGGER Slope, offset: 0x85D0 */ __IO uint32_t DPLL_RAM1B_RSVD_6_0; /**< DPLL RAM1B reserved data [k], offset: 0x85D4 */ __IO uint32_t DPLL_RAM1B_RSVD_6_1; /**< DPLL RAM1B reserved data [k], offset: 0x85D8 */ __IO uint32_t DPLL_RAM1B_RSVD_6_2; /**< DPLL RAM1B reserved data [k], offset: 0x85DC */ __IO uint32_t DPLL_PSTC; /**< Actual Calculated Position Stamp of TRIGGER, offset: 0x85E0 */ __IO uint32_t DPLL_PSSC; /**< Actual Calculated Position Stamp of STATE, offset: 0x85E4 */ __IO uint32_t DPLL_PSTM; /**< Measured Position Stamp at Last TRIGGER Input, offset: 0x85E8 */ __IO uint32_t DPLL_PSTM_OLD; /**< Measured Position Stamp at Last but one TRIGGER Input, offset: 0x85EC */ __IO uint32_t DPLL_PSSM; /**< Measured Position Stamp at Last STATE Input, offset: 0x85F0 */ __IO uint32_t DPLL_PSSM_OLD; /**< Measured Position Stamp at Last but one STATE Input, offset: 0x85F4 */ __IO uint32_t DPLL_NMB_T; /**< Number of Pulses to be sent in Normal Mode, offset: 0x85F8 */ __IO uint32_t DPLL_NMB_S; /**< Number of Pulses to be sent in Emergency Mode, offset: 0x85FC */ __IO uint32_t DPLL_RDT_S0; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8600 */ __IO uint32_t DPLL_RDT_S1; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8604 */ __IO uint32_t DPLL_RDT_S2; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8608 */ __IO uint32_t DPLL_RDT_S3; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x860C */ __IO uint32_t DPLL_RDT_S4; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8610 */ __IO uint32_t DPLL_RDT_S5; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8614 */ __IO uint32_t DPLL_RDT_S6; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8618 */ __IO uint32_t DPLL_RDT_S7; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x861C */ __IO uint32_t DPLL_RDT_S8; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8620 */ __IO uint32_t DPLL_RDT_S9; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8624 */ __IO uint32_t DPLL_RDT_S10; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8628 */ __IO uint32_t DPLL_RDT_S11; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x862C */ __IO uint32_t DPLL_RDT_S12; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8630 */ __IO uint32_t DPLL_RDT_S13; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8634 */ __IO uint32_t DPLL_RDT_S14; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8638 */ __IO uint32_t DPLL_RDT_S15; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x863C */ __IO uint32_t DPLL_RDT_S16; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8640 */ __IO uint32_t DPLL_RDT_S17; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8644 */ __IO uint32_t DPLL_RDT_S18; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8648 */ __IO uint32_t DPLL_RDT_S19; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x864C */ __IO uint32_t DPLL_RDT_S20; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8650 */ __IO uint32_t DPLL_RDT_S21; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8654 */ __IO uint32_t DPLL_RDT_S22; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8658 */ __IO uint32_t DPLL_RDT_S23; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x865C */ __IO uint32_t DPLL_RDT_S24; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8660 */ __IO uint32_t DPLL_RDT_S25; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8664 */ __IO uint32_t DPLL_RDT_S26; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8668 */ __IO uint32_t DPLL_RDT_S27; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x866C */ __IO uint32_t DPLL_RDT_S28; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8670 */ __IO uint32_t DPLL_RDT_S29; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8674 */ __IO uint32_t DPLL_RDT_S30; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8678 */ __IO uint32_t DPLL_RDT_S31; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x867C */ __IO uint32_t DPLL_RDT_S32; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8680 */ __IO uint32_t DPLL_RDT_S33; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8684 */ __IO uint32_t DPLL_RDT_S34; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8688 */ __IO uint32_t DPLL_RDT_S35; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x868C */ __IO uint32_t DPLL_RDT_S36; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8690 */ __IO uint32_t DPLL_RDT_S37; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8694 */ __IO uint32_t DPLL_RDT_S38; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8698 */ __IO uint32_t DPLL_RDT_S39; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x869C */ __IO uint32_t DPLL_RDT_S40; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x86A0 */ __IO uint32_t DPLL_RDT_S41; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x86A4 */ __IO uint32_t DPLL_RDT_S42; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x86A8 */ __IO uint32_t DPLL_RDT_S43; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x86AC */ __IO uint32_t DPLL_RDT_S44; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x86B0 */ __IO uint32_t DPLL_RDT_S45; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x86B4 */ __IO uint32_t DPLL_RDT_S46; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x86B8 */ __IO uint32_t DPLL_RDT_S47; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x86BC */ __IO uint32_t DPLL_RDT_S48; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x86C0 */ __IO uint32_t DPLL_RDT_S49; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x86C4 */ __IO uint32_t DPLL_RDT_S50; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x86C8 */ __IO uint32_t DPLL_RDT_S51; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x86CC */ __IO uint32_t DPLL_RDT_S52; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x86D0 */ __IO uint32_t DPLL_RDT_S53; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x86D4 */ __IO uint32_t DPLL_RDT_S54; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x86D8 */ __IO uint32_t DPLL_RDT_S55; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x86DC */ __IO uint32_t DPLL_RDT_S56; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x86E0 */ __IO uint32_t DPLL_RDT_S57; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x86E4 */ __IO uint32_t DPLL_RDT_S58; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x86E8 */ __IO uint32_t DPLL_RDT_S59; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x86EC */ __IO uint32_t DPLL_RDT_S60; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x86F0 */ __IO uint32_t DPLL_RDT_S61; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x86F4 */ __IO uint32_t DPLL_RDT_S62; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x86F8 */ __IO uint32_t DPLL_RDT_S63; /**< Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x86FC */ __IO uint32_t DPLL_TSF_S0; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8700 */ __IO uint32_t DPLL_TSF_S1; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8704 */ __IO uint32_t DPLL_TSF_S2; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8708 */ __IO uint32_t DPLL_TSF_S3; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x870C */ __IO uint32_t DPLL_TSF_S4; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8710 */ __IO uint32_t DPLL_TSF_S5; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8714 */ __IO uint32_t DPLL_TSF_S6; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8718 */ __IO uint32_t DPLL_TSF_S7; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x871C */ __IO uint32_t DPLL_TSF_S8; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8720 */ __IO uint32_t DPLL_TSF_S9; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8724 */ __IO uint32_t DPLL_TSF_S10; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8728 */ __IO uint32_t DPLL_TSF_S11; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x872C */ __IO uint32_t DPLL_TSF_S12; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8730 */ __IO uint32_t DPLL_TSF_S13; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8734 */ __IO uint32_t DPLL_TSF_S14; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8738 */ __IO uint32_t DPLL_TSF_S15; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x873C */ __IO uint32_t DPLL_TSF_S16; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8740 */ __IO uint32_t DPLL_TSF_S17; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8744 */ __IO uint32_t DPLL_TSF_S18; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8748 */ __IO uint32_t DPLL_TSF_S19; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x874C */ __IO uint32_t DPLL_TSF_S20; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8750 */ __IO uint32_t DPLL_TSF_S21; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8754 */ __IO uint32_t DPLL_TSF_S22; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8758 */ __IO uint32_t DPLL_TSF_S23; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x875C */ __IO uint32_t DPLL_TSF_S24; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8760 */ __IO uint32_t DPLL_TSF_S25; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8764 */ __IO uint32_t DPLL_TSF_S26; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8768 */ __IO uint32_t DPLL_TSF_S27; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x876C */ __IO uint32_t DPLL_TSF_S28; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8770 */ __IO uint32_t DPLL_TSF_S29; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8774 */ __IO uint32_t DPLL_TSF_S30; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8778 */ __IO uint32_t DPLL_TSF_S31; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x877C */ __IO uint32_t DPLL_TSF_S32; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8780 */ __IO uint32_t DPLL_TSF_S33; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8784 */ __IO uint32_t DPLL_TSF_S34; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8788 */ __IO uint32_t DPLL_TSF_S35; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x878C */ __IO uint32_t DPLL_TSF_S36; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8790 */ __IO uint32_t DPLL_TSF_S37; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8794 */ __IO uint32_t DPLL_TSF_S38; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8798 */ __IO uint32_t DPLL_TSF_S39; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x879C */ __IO uint32_t DPLL_TSF_S40; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x87A0 */ __IO uint32_t DPLL_TSF_S41; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x87A4 */ __IO uint32_t DPLL_TSF_S42; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x87A8 */ __IO uint32_t DPLL_TSF_S43; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x87AC */ __IO uint32_t DPLL_TSF_S44; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x87B0 */ __IO uint32_t DPLL_TSF_S45; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x87B4 */ __IO uint32_t DPLL_TSF_S46; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x87B8 */ __IO uint32_t DPLL_TSF_S47; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x87BC */ __IO uint32_t DPLL_TSF_S48; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x87C0 */ __IO uint32_t DPLL_TSF_S49; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x87C4 */ __IO uint32_t DPLL_TSF_S50; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x87C8 */ __IO uint32_t DPLL_TSF_S51; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x87CC */ __IO uint32_t DPLL_TSF_S52; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x87D0 */ __IO uint32_t DPLL_TSF_S53; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x87D4 */ __IO uint32_t DPLL_TSF_S54; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x87D8 */ __IO uint32_t DPLL_TSF_S55; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x87DC */ __IO uint32_t DPLL_TSF_S56; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x87E0 */ __IO uint32_t DPLL_TSF_S57; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x87E4 */ __IO uint32_t DPLL_TSF_S58; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x87E8 */ __IO uint32_t DPLL_TSF_S59; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x87EC */ __IO uint32_t DPLL_TSF_S60; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x87F0 */ __IO uint32_t DPLL_TSF_S61; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x87F4 */ __IO uint32_t DPLL_TSF_S62; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x87F8 */ __IO uint32_t DPLL_TSF_S63; /**< Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x87FC */ __IO uint32_t DPLL_ADT_S0; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x8800 */ __IO uint32_t DPLL_ADT_S1; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x8804 */ __IO uint32_t DPLL_ADT_S2; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x8808 */ __IO uint32_t DPLL_ADT_S3; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x880C */ __IO uint32_t DPLL_ADT_S4; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x8810 */ __IO uint32_t DPLL_ADT_S5; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x8814 */ __IO uint32_t DPLL_ADT_S6; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x8818 */ __IO uint32_t DPLL_ADT_S7; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x881C */ __IO uint32_t DPLL_ADT_S8; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x8820 */ __IO uint32_t DPLL_ADT_S9; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x8824 */ __IO uint32_t DPLL_ADT_S10; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x8828 */ __IO uint32_t DPLL_ADT_S11; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x882C */ __IO uint32_t DPLL_ADT_S12; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x8830 */ __IO uint32_t DPLL_ADT_S13; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x8834 */ __IO uint32_t DPLL_ADT_S14; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x8838 */ __IO uint32_t DPLL_ADT_S15; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x883C */ __IO uint32_t DPLL_ADT_S16; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x8840 */ __IO uint32_t DPLL_ADT_S17; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x8844 */ __IO uint32_t DPLL_ADT_S18; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x8848 */ __IO uint32_t DPLL_ADT_S19; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x884C */ __IO uint32_t DPLL_ADT_S20; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x8850 */ __IO uint32_t DPLL_ADT_S21; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x8854 */ __IO uint32_t DPLL_ADT_S22; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x8858 */ __IO uint32_t DPLL_ADT_S23; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x885C */ __IO uint32_t DPLL_ADT_S24; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x8860 */ __IO uint32_t DPLL_ADT_S25; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x8864 */ __IO uint32_t DPLL_ADT_S26; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x8868 */ __IO uint32_t DPLL_ADT_S27; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x886C */ __IO uint32_t DPLL_ADT_S28; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x8870 */ __IO uint32_t DPLL_ADT_S29; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x8874 */ __IO uint32_t DPLL_ADT_S30; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x8878 */ __IO uint32_t DPLL_ADT_S31; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x887C */ __IO uint32_t DPLL_ADT_S32; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x8880 */ __IO uint32_t DPLL_ADT_S33; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x8884 */ __IO uint32_t DPLL_ADT_S34; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x8888 */ __IO uint32_t DPLL_ADT_S35; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x888C */ __IO uint32_t DPLL_ADT_S36; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x8890 */ __IO uint32_t DPLL_ADT_S37; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x8894 */ __IO uint32_t DPLL_ADT_S38; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x8898 */ __IO uint32_t DPLL_ADT_S39; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x889C */ __IO uint32_t DPLL_ADT_S40; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x88A0 */ __IO uint32_t DPLL_ADT_S41; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x88A4 */ __IO uint32_t DPLL_ADT_S42; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x88A8 */ __IO uint32_t DPLL_ADT_S43; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x88AC */ __IO uint32_t DPLL_ADT_S44; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x88B0 */ __IO uint32_t DPLL_ADT_S45; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x88B4 */ __IO uint32_t DPLL_ADT_S46; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x88B8 */ __IO uint32_t DPLL_ADT_S47; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x88BC */ __IO uint32_t DPLL_ADT_S48; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x88C0 */ __IO uint32_t DPLL_ADT_S49; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x88C4 */ __IO uint32_t DPLL_ADT_S50; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x88C8 */ __IO uint32_t DPLL_ADT_S51; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x88CC */ __IO uint32_t DPLL_ADT_S52; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x88D0 */ __IO uint32_t DPLL_ADT_S53; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x88D4 */ __IO uint32_t DPLL_ADT_S54; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x88D8 */ __IO uint32_t DPLL_ADT_S55; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x88DC */ __IO uint32_t DPLL_ADT_S56; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x88E0 */ __IO uint32_t DPLL_ADT_S57; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x88E4 */ __IO uint32_t DPLL_ADT_S58; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x88E8 */ __IO uint32_t DPLL_ADT_S59; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x88EC */ __IO uint32_t DPLL_ADT_S60; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x88F0 */ __IO uint32_t DPLL_ADT_S61; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x88F4 */ __IO uint32_t DPLL_ADT_S62; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x88F8 */ __IO uint32_t DPLL_ADT_S63; /**< Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries, offset: 0x88FC */ __IO uint32_t DPLL_DT_S0; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8900 */ __IO uint32_t DPLL_DT_S1; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8904 */ __IO uint32_t DPLL_DT_S2; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8908 */ __IO uint32_t DPLL_DT_S3; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x890C */ __IO uint32_t DPLL_DT_S4; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8910 */ __IO uint32_t DPLL_DT_S5; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8914 */ __IO uint32_t DPLL_DT_S6; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8918 */ __IO uint32_t DPLL_DT_S7; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x891C */ __IO uint32_t DPLL_DT_S8; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8920 */ __IO uint32_t DPLL_DT_S9; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8924 */ __IO uint32_t DPLL_DT_S10; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8928 */ __IO uint32_t DPLL_DT_S11; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x892C */ __IO uint32_t DPLL_DT_S12; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8930 */ __IO uint32_t DPLL_DT_S13; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8934 */ __IO uint32_t DPLL_DT_S14; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8938 */ __IO uint32_t DPLL_DT_S15; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x893C */ __IO uint32_t DPLL_DT_S16; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8940 */ __IO uint32_t DPLL_DT_S17; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8944 */ __IO uint32_t DPLL_DT_S18; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8948 */ __IO uint32_t DPLL_DT_S19; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x894C */ __IO uint32_t DPLL_DT_S20; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8950 */ __IO uint32_t DPLL_DT_S21; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8954 */ __IO uint32_t DPLL_DT_S22; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8958 */ __IO uint32_t DPLL_DT_S23; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x895C */ __IO uint32_t DPLL_DT_S24; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8960 */ __IO uint32_t DPLL_DT_S25; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8964 */ __IO uint32_t DPLL_DT_S26; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8968 */ __IO uint32_t DPLL_DT_S27; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x896C */ __IO uint32_t DPLL_DT_S28; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8970 */ __IO uint32_t DPLL_DT_S29; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8974 */ __IO uint32_t DPLL_DT_S30; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8978 */ __IO uint32_t DPLL_DT_S31; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x897C */ __IO uint32_t DPLL_DT_S32; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8980 */ __IO uint32_t DPLL_DT_S33; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8984 */ __IO uint32_t DPLL_DT_S34; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8988 */ __IO uint32_t DPLL_DT_S35; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x898C */ __IO uint32_t DPLL_DT_S36; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8990 */ __IO uint32_t DPLL_DT_S37; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8994 */ __IO uint32_t DPLL_DT_S38; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x8998 */ __IO uint32_t DPLL_DT_S39; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x899C */ __IO uint32_t DPLL_DT_S40; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x89A0 */ __IO uint32_t DPLL_DT_S41; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x89A4 */ __IO uint32_t DPLL_DT_S42; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x89A8 */ __IO uint32_t DPLL_DT_S43; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x89AC */ __IO uint32_t DPLL_DT_S44; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x89B0 */ __IO uint32_t DPLL_DT_S45; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x89B4 */ __IO uint32_t DPLL_DT_S46; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x89B8 */ __IO uint32_t DPLL_DT_S47; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x89BC */ __IO uint32_t DPLL_DT_S48; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x89C0 */ __IO uint32_t DPLL_DT_S49; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x89C4 */ __IO uint32_t DPLL_DT_S50; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x89C8 */ __IO uint32_t DPLL_DT_S51; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x89CC */ __IO uint32_t DPLL_DT_S52; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x89D0 */ __IO uint32_t DPLL_DT_S53; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x89D4 */ __IO uint32_t DPLL_DT_S54; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x89D8 */ __IO uint32_t DPLL_DT_S55; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x89DC */ __IO uint32_t DPLL_DT_S56; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x89E0 */ __IO uint32_t DPLL_DT_S57; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x89E4 */ __IO uint32_t DPLL_DT_S58; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x89E8 */ __IO uint32_t DPLL_DT_S59; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x89EC */ __IO uint32_t DPLL_DT_S60; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x89F0 */ __IO uint32_t DPLL_DT_S61; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x89F4 */ __IO uint32_t DPLL_DT_S62; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x89F8 */ __IO uint32_t DPLL_DT_S63; /**< Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]), offset: 0x89FC */ uint8_t RESERVED_151[1024]; __IO uint32_t DPLL_TSAC0; /**< Calculated Time Value to start Action [n], offset: 0x8E00 */ __IO uint32_t DPLL_TSAC1; /**< Calculated Time Value to start Action [n], offset: 0x8E04 */ __IO uint32_t DPLL_TSAC2; /**< Calculated Time Value to start Action [n], offset: 0x8E08 */ __IO uint32_t DPLL_TSAC3; /**< Calculated Time Value to start Action [n], offset: 0x8E0C */ __IO uint32_t DPLL_TSAC4; /**< Calculated Time Value to start Action [n], offset: 0x8E10 */ __IO uint32_t DPLL_TSAC5; /**< Calculated Time Value to start Action [n], offset: 0x8E14 */ __IO uint32_t DPLL_TSAC6; /**< Calculated Time Value to start Action [n], offset: 0x8E18 */ __IO uint32_t DPLL_TSAC7; /**< Calculated Time Value to start Action [n], offset: 0x8E1C */ __IO uint32_t DPLL_TSAC8; /**< Calculated Time Value to start Action [n], offset: 0x8E20 */ __IO uint32_t DPLL_TSAC9; /**< Calculated Time Value to start Action [n], offset: 0x8E24 */ __IO uint32_t DPLL_TSAC10; /**< Calculated Time Value to start Action [n], offset: 0x8E28 */ __IO uint32_t DPLL_TSAC11; /**< Calculated Time Value to start Action [n], offset: 0x8E2C */ __IO uint32_t DPLL_TSAC12; /**< Calculated Time Value to start Action [n], offset: 0x8E30 */ __IO uint32_t DPLL_TSAC13; /**< Calculated Time Value to start Action [n], offset: 0x8E34 */ __IO uint32_t DPLL_TSAC14; /**< Calculated Time Value to start Action [n], offset: 0x8E38 */ __IO uint32_t DPLL_TSAC15; /**< Calculated Time Value to start Action [n], offset: 0x8E3C */ __IO uint32_t DPLL_TSAC16; /**< Calculated Time Value to start Action [n], offset: 0x8E40 */ __IO uint32_t DPLL_TSAC17; /**< Calculated Time Value to start Action [n], offset: 0x8E44 */ __IO uint32_t DPLL_TSAC18; /**< Calculated Time Value to start Action [n], offset: 0x8E48 */ __IO uint32_t DPLL_TSAC19; /**< Calculated Time Value to start Action [n], offset: 0x8E4C */ __IO uint32_t DPLL_TSAC20; /**< Calculated Time Value to start Action [n], offset: 0x8E50 */ __IO uint32_t DPLL_TSAC21; /**< Calculated Time Value to start Action [n], offset: 0x8E54 */ __IO uint32_t DPLL_TSAC22; /**< Calculated Time Value to start Action [n], offset: 0x8E58 */ __IO uint32_t DPLL_TSAC23; /**< Calculated Time Value to start Action [n], offset: 0x8E5C */ __IO uint32_t DPLL_TSAC24; /**< Calculated Time Value to start Action [n], offset: 0x8E60 */ __IO uint32_t DPLL_TSAC25; /**< Calculated Time Value to start Action [n], offset: 0x8E64 */ __IO uint32_t DPLL_TSAC26; /**< Calculated Time Value to start Action [n], offset: 0x8E68 */ __IO uint32_t DPLL_TSAC27; /**< Calculated Time Value to start Action [n], offset: 0x8E6C */ __IO uint32_t DPLL_TSAC28; /**< Calculated Time Value to start Action [n], offset: 0x8E70 */ __IO uint32_t DPLL_TSAC29; /**< Calculated Time Value to start Action [n], offset: 0x8E74 */ __IO uint32_t DPLL_TSAC30; /**< Calculated Time Value to start Action [n], offset: 0x8E78 */ __IO uint32_t DPLL_TSAC31; /**< Calculated Time Value to start Action [n], offset: 0x8E7C */ __IO uint32_t DPLL_PSAC0; /**< Calculated Position Value to start Action [n], offset: 0x8E80 */ __IO uint32_t DPLL_PSAC1; /**< Calculated Position Value to start Action [n], offset: 0x8E84 */ __IO uint32_t DPLL_PSAC2; /**< Calculated Position Value to start Action [n], offset: 0x8E88 */ __IO uint32_t DPLL_PSAC3; /**< Calculated Position Value to start Action [n], offset: 0x8E8C */ __IO uint32_t DPLL_PSAC4; /**< Calculated Position Value to start Action [n], offset: 0x8E90 */ __IO uint32_t DPLL_PSAC5; /**< Calculated Position Value to start Action [n], offset: 0x8E94 */ __IO uint32_t DPLL_PSAC6; /**< Calculated Position Value to start Action [n], offset: 0x8E98 */ __IO uint32_t DPLL_PSAC7; /**< Calculated Position Value to start Action [n], offset: 0x8E9C */ __IO uint32_t DPLL_PSAC8; /**< Calculated Position Value to start Action [n], offset: 0x8EA0 */ __IO uint32_t DPLL_PSAC9; /**< Calculated Position Value to start Action [n], offset: 0x8EA4 */ __IO uint32_t DPLL_PSAC10; /**< Calculated Position Value to start Action [n], offset: 0x8EA8 */ __IO uint32_t DPLL_PSAC11; /**< Calculated Position Value to start Action [n], offset: 0x8EAC */ __IO uint32_t DPLL_PSAC12; /**< Calculated Position Value to start Action [n], offset: 0x8EB0 */ __IO uint32_t DPLL_PSAC13; /**< Calculated Position Value to start Action [n], offset: 0x8EB4 */ __IO uint32_t DPLL_PSAC14; /**< Calculated Position Value to start Action [n], offset: 0x8EB8 */ __IO uint32_t DPLL_PSAC15; /**< Calculated Position Value to start Action [n], offset: 0x8EBC */ __IO uint32_t DPLL_PSAC16; /**< Calculated Position Value to start Action [n], offset: 0x8EC0 */ __IO uint32_t DPLL_PSAC17; /**< Calculated Position Value to start Action [n], offset: 0x8EC4 */ __IO uint32_t DPLL_PSAC18; /**< Calculated Position Value to start Action [n], offset: 0x8EC8 */ __IO uint32_t DPLL_PSAC19; /**< Calculated Position Value to start Action [n], offset: 0x8ECC */ __IO uint32_t DPLL_PSAC20; /**< Calculated Position Value to start Action [n], offset: 0x8ED0 */ __IO uint32_t DPLL_PSAC21; /**< Calculated Position Value to start Action [n], offset: 0x8ED4 */ __IO uint32_t DPLL_PSAC22; /**< Calculated Position Value to start Action [n], offset: 0x8ED8 */ __IO uint32_t DPLL_PSAC23; /**< Calculated Position Value to start Action [n], offset: 0x8EDC */ __IO uint32_t DPLL_PSAC24; /**< Calculated Position Value to start Action [n], offset: 0x8EE0 */ __IO uint32_t DPLL_PSAC25; /**< Calculated Position Value to start Action [n], offset: 0x8EE4 */ __IO uint32_t DPLL_PSAC26; /**< Calculated Position Value to start Action [n], offset: 0x8EE8 */ __IO uint32_t DPLL_PSAC27; /**< Calculated Position Value to start Action [n], offset: 0x8EEC */ __IO uint32_t DPLL_PSAC28; /**< Calculated Position Value to start Action [n], offset: 0x8EF0 */ __IO uint32_t DPLL_PSAC29; /**< Calculated Position Value to start Action [n], offset: 0x8EF4 */ __IO uint32_t DPLL_PSAC30; /**< Calculated Position Value to start Action [n], offset: 0x8EF8 */ __IO uint32_t DPLL_PSAC31; /**< Calculated Position Value to start Action [n], offset: 0x8EFC */ __IO uint32_t DPLL_ACB_0; /**< Control Bits for NOAC Actions, offset: 0x8F00 */ __IO uint32_t DPLL_ACB_1; /**< Control Bits for NOAC Actions, offset: 0x8F04 */ __IO uint32_t DPLL_ACB_2; /**< Control Bits for NOAC Actions, offset: 0x8F08 */ __IO uint32_t DPLL_ACB_3; /**< Control Bits for NOAC Actions, offset: 0x8F0C */ __IO uint32_t DPLL_ACB_4; /**< Control Bits for NOAC Actions, offset: 0x8F10 */ __IO uint32_t DPLL_ACB_5; /**< Control Bits for NOAC Actions, offset: 0x8F14 */ __IO uint32_t DPLL_ACB_6; /**< Control Bits for NOAC Actions, offset: 0x8F18 */ __IO uint32_t DPLL_ACB_7; /**< Control Bits for NOAC Actions, offset: 0x8F1C */ __IO uint32_t DPLL_CTRL_11; /**< Control Register 11, offset: 0x8F20 */ __I uint32_t DPLL_THVAL2; /**< Measured TRIGGER Hold Time Value 2, offset: 0x8F24 */ __IO uint32_t DPLL_TIDEL; /**< TRIGGER input delay, offset: 0x8F28 */ __IO uint32_t DPLL_SIDEL; /**< STATE input delay, offset: 0x8F2C */ __IO uint32_t DPLL_APS_SYNC_EXT; /**< STATE Time Stamp Field Offset at Synchronization Time, offset: 0x8F30 */ __IO uint32_t DPLL_CTRL_EXT; /**< STATE Time Stamp Field Offset at Synchronization Time, offset: 0x8F34 */ __IO uint32_t DPLL_APS_EXT; /**< Actual RAM Pointer Address for STATE, offset: 0x8F38 */ __IO uint32_t DPLL_APS_1C3_EXT; /**< Actual RAM Pointer Address for RAM region 1c3 (DPLL_CTRL_11.STATE_EXT=1), offset: 0x8F3C */ __I uint32_t DPLL_STA; /**< Status of the state machine states, offset: 0x8F40 */ __IO uint32_t DPLL_INCF1_OFFSET; /**< Start value of ADD_IN_ADDER1, offset: 0x8F44 */ __IO uint32_t DPLL_INCF2_OFFSET; /**< Start value of the ADD_IN_ADDER2, offset: 0x8F48 */ __IO uint32_t DPLL_DT_T_START; /**< Start value of DT_T_ACT, offset: 0x8F4C */ __IO uint32_t DPLL_DT_S_START; /**< Start value of DT_S_ACT, offset: 0x8F50 */ __IO uint32_t DPLL_STA_MASK; /**< Notify values for DPLL_STA, offset: 0x8F54 */ __IO uint32_t DPLL_STA_FLAG; /**< DPLL STA Flags, offset: 0x8F58 */ __IO uint32_t DPLL_INC_CNT1_MASK; /**< Notify value of DPLL_INC_CNT1, offset: 0x8F5C */ __IO uint32_t DPLL_INC_CNT2_MASK; /**< Notify value of DPLL_INC_CNT2, offset: 0x8F60 */ __IO uint32_t DPLL_NUSC_EXT1; /**< Number of Recent STATE Events used for Calculations, offset: 0x8F64 */ __IO uint32_t DPLL_NUSC_EXT2; /**< Number of Recent STATE Events used for Calculations, offset: 0x8F68 */ __IO uint32_t DPLL_CTN_MIN; /**< Minimum value of predicted nominal increment of TRIGGER, offset: 0x8F6C */ __IO uint32_t DPLL_CTN_MAX; /**< Maximum value of predicted nominal increment of TRIGGER, offset: 0x8F70 */ __IO uint32_t DPLL_CSN_MIN; /**< Minimum value of predicted nominal increment of STATE, offset: 0x8F74 */ __IO uint32_t DPLL_CSN_MAX; /**< Maximum value of predicted nominal increment of STATE, offset: 0x8F78 */ __IO uint32_t DPLL_SW_TRIG; /**< Software triggered input events, offset: 0x8F7C */ __I uint32_t DPLL_MP_T; /**< Missing pulses of TRIGGER, offset: 0x8F80 */ __I uint32_t DPLL_MP_S; /**< Missing pulses of STATE, offset: 0x8F84 */ __IO uint32_t DPLL_CTRL_12; /**< DPLL control register 12, offset: 0x8F88 */ uint8_t RESERVED_152[12404]; __IO uint32_t DPLL_RR2[GTM_gtm_cls0_DPLL_RR2_COUNT]; /**< DPLL memory RR2, array offset: 0xC000, array step: 0x4 */ __IO uint32_t MCS0_MEM[GTM_gtm_cls0_MCS0_MEM_COUNT]; /**< MCS[i] memory region, array offset: 0x10000, array step: 0x4 */ } GTM_gtm_cls0_Type, *GTM_gtm_cls0_MemMapPtr; /** Number of instances of the GTM_gtm_cls0 module. */ #define GTM_gtm_cls0_INSTANCE_COUNT (1u) /* GTM_gtm_cls0 - Peripheral instance base addresses */ /** Peripheral GTM_gtm_cls0 base address */ #define IP_GTM_gtm_cls0_BASE (0x73000000u) /** Peripheral GTM_gtm_cls0 base pointer */ #define IP_GTM_gtm_cls0 ((GTM_gtm_cls0_Type *)IP_GTM_gtm_cls0_BASE) /** Array initializer of GTM_gtm_cls0 peripheral base addresses */ #define IP_GTM_gtm_cls0_BASE_ADDRS { IP_GTM_gtm_cls0_BASE } /** Array initializer of GTM_gtm_cls0 peripheral base pointers */ #define IP_GTM_gtm_cls0_BASE_PTRS { IP_GTM_gtm_cls0 } /* ---------------------------------------------------------------------------- -- GTM_gtm_cls0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GTM_gtm_cls0_Register_Masks GTM_gtm_cls0 Register Masks * @{ */ /*! @name GTM_REV - GTM version control register */ /*! @{ */ #define GTM_gtm_cls0_GTM_REV_REL_ITER_MASK (0xFU) #define GTM_gtm_cls0_GTM_REV_REL_ITER_SHIFT (0U) #define GTM_gtm_cls0_GTM_REV_REL_ITER_WIDTH (4U) #define GTM_gtm_cls0_GTM_REV_REL_ITER(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_REV_REL_ITER_SHIFT)) & GTM_gtm_cls0_GTM_REV_REL_ITER_MASK) #define GTM_gtm_cls0_GTM_REV_REL_BASE_MASK (0xFF0U) #define GTM_gtm_cls0_GTM_REV_REL_BASE_SHIFT (4U) #define GTM_gtm_cls0_GTM_REV_REL_BASE_WIDTH (8U) #define GTM_gtm_cls0_GTM_REV_REL_BASE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_REV_REL_BASE_SHIFT)) & GTM_gtm_cls0_GTM_REV_REL_BASE_MASK) #define GTM_gtm_cls0_GTM_REV_VENDOR_CODE_MASK (0xF0000U) #define GTM_gtm_cls0_GTM_REV_VENDOR_CODE_SHIFT (16U) #define GTM_gtm_cls0_GTM_REV_VENDOR_CODE_WIDTH (4U) #define GTM_gtm_cls0_GTM_REV_VENDOR_CODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_REV_VENDOR_CODE_SHIFT)) & GTM_gtm_cls0_GTM_REV_VENDOR_CODE_MASK) #define GTM_gtm_cls0_GTM_REV_DEVICE_CODE_MASK (0xF00000U) #define GTM_gtm_cls0_GTM_REV_DEVICE_CODE_SHIFT (20U) #define GTM_gtm_cls0_GTM_REV_DEVICE_CODE_WIDTH (4U) #define GTM_gtm_cls0_GTM_REV_DEVICE_CODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_REV_DEVICE_CODE_SHIFT)) & GTM_gtm_cls0_GTM_REV_DEVICE_CODE_MASK) #define GTM_gtm_cls0_GTM_REV_VER_MINOR_MASK (0xF000000U) #define GTM_gtm_cls0_GTM_REV_VER_MINOR_SHIFT (24U) #define GTM_gtm_cls0_GTM_REV_VER_MINOR_WIDTH (4U) #define GTM_gtm_cls0_GTM_REV_VER_MINOR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_REV_VER_MINOR_SHIFT)) & GTM_gtm_cls0_GTM_REV_VER_MINOR_MASK) #define GTM_gtm_cls0_GTM_REV_VER_MAJOR_MASK (0xF0000000U) #define GTM_gtm_cls0_GTM_REV_VER_MAJOR_SHIFT (28U) #define GTM_gtm_cls0_GTM_REV_VER_MAJOR_WIDTH (4U) #define GTM_gtm_cls0_GTM_REV_VER_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_REV_VER_MAJOR_SHIFT)) & GTM_gtm_cls0_GTM_REV_VER_MAJOR_MASK) /*! @} */ /*! @name GTM_RST - GTM global reset register */ /*! @{ */ #define GTM_gtm_cls0_GTM_RST_RST_MASK (0x1U) #define GTM_gtm_cls0_GTM_RST_RST_SHIFT (0U) #define GTM_gtm_cls0_GTM_RST_RST_WIDTH (1U) #define GTM_gtm_cls0_GTM_RST_RST(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_RST_RST_SHIFT)) & GTM_gtm_cls0_GTM_RST_RST_MASK) #define GTM_gtm_cls0_GTM_RST_BRIDGE_MODE_WRDIS_MASK (0x8000000U) #define GTM_gtm_cls0_GTM_RST_BRIDGE_MODE_WRDIS_SHIFT (27U) #define GTM_gtm_cls0_GTM_RST_BRIDGE_MODE_WRDIS_WIDTH (1U) #define GTM_gtm_cls0_GTM_RST_BRIDGE_MODE_WRDIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_RST_BRIDGE_MODE_WRDIS_SHIFT)) & GTM_gtm_cls0_GTM_RST_BRIDGE_MODE_WRDIS_MASK) /*! @} */ /*! @name GTM_CTRL - GTM global control register */ /*! @{ */ #define GTM_gtm_cls0_GTM_CTRL_RF_PROT_MASK (0x1U) #define GTM_gtm_cls0_GTM_CTRL_RF_PROT_SHIFT (0U) #define GTM_gtm_cls0_GTM_CTRL_RF_PROT_WIDTH (1U) #define GTM_gtm_cls0_GTM_CTRL_RF_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_CTRL_RF_PROT_SHIFT)) & GTM_gtm_cls0_GTM_CTRL_RF_PROT_MASK) #define GTM_gtm_cls0_GTM_CTRL_TO_MODE_MASK (0x6U) #define GTM_gtm_cls0_GTM_CTRL_TO_MODE_SHIFT (1U) #define GTM_gtm_cls0_GTM_CTRL_TO_MODE_WIDTH (2U) #define GTM_gtm_cls0_GTM_CTRL_TO_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_CTRL_TO_MODE_SHIFT)) & GTM_gtm_cls0_GTM_CTRL_TO_MODE_MASK) #define GTM_gtm_cls0_GTM_CTRL_TO_VAL_MASK (0xFF0U) #define GTM_gtm_cls0_GTM_CTRL_TO_VAL_SHIFT (4U) #define GTM_gtm_cls0_GTM_CTRL_TO_VAL_WIDTH (8U) #define GTM_gtm_cls0_GTM_CTRL_TO_VAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_CTRL_TO_VAL_SHIFT)) & GTM_gtm_cls0_GTM_CTRL_TO_VAL_MASK) #define GTM_gtm_cls0_GTM_CTRL_AEIM_CLUSTER_MASK (0xF000U) #define GTM_gtm_cls0_GTM_CTRL_AEIM_CLUSTER_SHIFT (12U) #define GTM_gtm_cls0_GTM_CTRL_AEIM_CLUSTER_WIDTH (4U) #define GTM_gtm_cls0_GTM_CTRL_AEIM_CLUSTER(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_CTRL_AEIM_CLUSTER_SHIFT)) & GTM_gtm_cls0_GTM_CTRL_AEIM_CLUSTER_MASK) /*! @} */ /*! @name GTM_CFG - GTM configuration register */ /*! @{ */ #define GTM_gtm_cls0_GTM_CFG_SRC_IN_MUX_MASK (0x1U) #define GTM_gtm_cls0_GTM_CFG_SRC_IN_MUX_SHIFT (0U) #define GTM_gtm_cls0_GTM_CFG_SRC_IN_MUX_WIDTH (1U) #define GTM_gtm_cls0_GTM_CFG_SRC_IN_MUX(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_CFG_SRC_IN_MUX_SHIFT)) & GTM_gtm_cls0_GTM_CFG_SRC_IN_MUX_MASK) /*! @} */ /*! @name GTM_AEI_ADDR_XPT - GTM AEI timeout exception address register */ /*! @{ */ #define GTM_gtm_cls0_GTM_AEI_ADDR_XPT_TO_ADDR_MASK (0x1FFFFFU) #define GTM_gtm_cls0_GTM_AEI_ADDR_XPT_TO_ADDR_SHIFT (0U) #define GTM_gtm_cls0_GTM_AEI_ADDR_XPT_TO_ADDR_WIDTH (21U) #define GTM_gtm_cls0_GTM_AEI_ADDR_XPT_TO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_AEI_ADDR_XPT_TO_ADDR_SHIFT)) & GTM_gtm_cls0_GTM_AEI_ADDR_XPT_TO_ADDR_MASK) #define GTM_gtm_cls0_GTM_AEI_ADDR_XPT_TO_W1R0_MASK (0x1000000U) #define GTM_gtm_cls0_GTM_AEI_ADDR_XPT_TO_W1R0_SHIFT (24U) #define GTM_gtm_cls0_GTM_AEI_ADDR_XPT_TO_W1R0_WIDTH (1U) #define GTM_gtm_cls0_GTM_AEI_ADDR_XPT_TO_W1R0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_AEI_ADDR_XPT_TO_W1R0_SHIFT)) & GTM_gtm_cls0_GTM_AEI_ADDR_XPT_TO_W1R0_MASK) /*! @} */ /*! @name GTM_AEI_STA_XPT - GTM AEI non zero status register */ /*! @{ */ #define GTM_gtm_cls0_GTM_AEI_STA_XPT_ADDR_MASK (0x1FFFFFU) #define GTM_gtm_cls0_GTM_AEI_STA_XPT_ADDR_SHIFT (0U) #define GTM_gtm_cls0_GTM_AEI_STA_XPT_ADDR_WIDTH (21U) #define GTM_gtm_cls0_GTM_AEI_STA_XPT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_AEI_STA_XPT_ADDR_SHIFT)) & GTM_gtm_cls0_GTM_AEI_STA_XPT_ADDR_MASK) #define GTM_gtm_cls0_GTM_AEI_STA_XPT_W1R0_MASK (0x1000000U) #define GTM_gtm_cls0_GTM_AEI_STA_XPT_W1R0_SHIFT (24U) #define GTM_gtm_cls0_GTM_AEI_STA_XPT_W1R0_WIDTH (1U) #define GTM_gtm_cls0_GTM_AEI_STA_XPT_W1R0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_AEI_STA_XPT_W1R0_SHIFT)) & GTM_gtm_cls0_GTM_AEI_STA_XPT_W1R0_MASK) /*! @} */ /*! @name GTM_IRQ_NOTIFY - GTM Interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEI_TO_XPT_MASK (0x1U) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEI_TO_XPT_SHIFT (0U) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEI_TO_XPT_WIDTH (1U) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEI_TO_XPT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEI_TO_XPT_SHIFT)) & GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEI_TO_XPT_MASK) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEI_USP_ADDR_MASK (0x2U) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEI_USP_ADDR_SHIFT (1U) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEI_USP_ADDR_WIDTH (1U) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEI_USP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEI_USP_ADDR_SHIFT)) & GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEI_USP_ADDR_MASK) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEI_IM_ADDR_MASK (0x4U) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEI_IM_ADDR_SHIFT (2U) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEI_IM_ADDR_WIDTH (1U) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEI_IM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEI_IM_ADDR_SHIFT)) & GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEI_IM_ADDR_MASK) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEI_USP_BE_MASK (0x8U) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEI_USP_BE_SHIFT (3U) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEI_USP_BE_WIDTH (1U) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEI_USP_BE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEI_USP_BE_SHIFT)) & GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEI_USP_BE_MASK) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEIM_USP_ADDR_MASK (0x10U) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEIM_USP_ADDR_SHIFT (4U) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEIM_USP_ADDR_WIDTH (1U) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEIM_USP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEIM_USP_ADDR_SHIFT)) & GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEIM_USP_ADDR_MASK) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEIM_IM_ADDR_MASK (0x20U) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEIM_IM_ADDR_SHIFT (5U) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEIM_IM_ADDR_WIDTH (1U) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEIM_IM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEIM_IM_ADDR_SHIFT)) & GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEIM_IM_ADDR_MASK) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEIM_USP_BE_MASK (0x40U) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEIM_USP_BE_SHIFT (6U) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEIM_USP_BE_WIDTH (1U) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEIM_USP_BE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEIM_USP_BE_SHIFT)) & GTM_gtm_cls0_GTM_IRQ_NOTIFY_AEIM_USP_BE_MASK) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_CLK_EN_ERR_MASK (0x80U) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_CLK_EN_ERR_SHIFT (7U) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_CLK_EN_ERR_WIDTH (1U) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_CLK_EN_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_IRQ_NOTIFY_CLK_EN_ERR_SHIFT)) & GTM_gtm_cls0_GTM_IRQ_NOTIFY_CLK_EN_ERR_MASK) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_CLK_PER_ERR_MASK (0x100U) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_CLK_PER_ERR_SHIFT (8U) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_CLK_PER_ERR_WIDTH (1U) #define GTM_gtm_cls0_GTM_IRQ_NOTIFY_CLK_PER_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_IRQ_NOTIFY_CLK_PER_ERR_SHIFT)) & GTM_gtm_cls0_GTM_IRQ_NOTIFY_CLK_PER_ERR_MASK) /*! @} */ /*! @name GTM_IRQ_EN - GTM interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_GTM_IRQ_EN_AEI_TO_XPT_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_GTM_IRQ_EN_AEI_TO_XPT_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_GTM_IRQ_EN_AEI_TO_XPT_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_GTM_IRQ_EN_AEI_TO_XPT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_IRQ_EN_AEI_TO_XPT_IRQ_EN_SHIFT)) & GTM_gtm_cls0_GTM_IRQ_EN_AEI_TO_XPT_IRQ_EN_MASK) #define GTM_gtm_cls0_GTM_IRQ_EN_AEI_USP_ADDR_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_GTM_IRQ_EN_AEI_USP_ADDR_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_GTM_IRQ_EN_AEI_USP_ADDR_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_GTM_IRQ_EN_AEI_USP_ADDR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_IRQ_EN_AEI_USP_ADDR_IRQ_EN_SHIFT)) & GTM_gtm_cls0_GTM_IRQ_EN_AEI_USP_ADDR_IRQ_EN_MASK) #define GTM_gtm_cls0_GTM_IRQ_EN_AEI_IM_ADDR_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_GTM_IRQ_EN_AEI_IM_ADDR_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_GTM_IRQ_EN_AEI_IM_ADDR_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_GTM_IRQ_EN_AEI_IM_ADDR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_IRQ_EN_AEI_IM_ADDR_IRQ_EN_SHIFT)) & GTM_gtm_cls0_GTM_IRQ_EN_AEI_IM_ADDR_IRQ_EN_MASK) #define GTM_gtm_cls0_GTM_IRQ_EN_AEI_USP_BE_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_GTM_IRQ_EN_AEI_USP_BE_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_GTM_IRQ_EN_AEI_USP_BE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_GTM_IRQ_EN_AEI_USP_BE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_IRQ_EN_AEI_USP_BE_IRQ_EN_SHIFT)) & GTM_gtm_cls0_GTM_IRQ_EN_AEI_USP_BE_IRQ_EN_MASK) #define GTM_gtm_cls0_GTM_IRQ_EN_AEIM_USP_ADDR_IRQ_EN_MASK (0x10U) #define GTM_gtm_cls0_GTM_IRQ_EN_AEIM_USP_ADDR_IRQ_EN_SHIFT (4U) #define GTM_gtm_cls0_GTM_IRQ_EN_AEIM_USP_ADDR_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_GTM_IRQ_EN_AEIM_USP_ADDR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_IRQ_EN_AEIM_USP_ADDR_IRQ_EN_SHIFT)) & GTM_gtm_cls0_GTM_IRQ_EN_AEIM_USP_ADDR_IRQ_EN_MASK) #define GTM_gtm_cls0_GTM_IRQ_EN_AEIM_IM_ADDR_IRQ_EN_MASK (0x20U) #define GTM_gtm_cls0_GTM_IRQ_EN_AEIM_IM_ADDR_IRQ_EN_SHIFT (5U) #define GTM_gtm_cls0_GTM_IRQ_EN_AEIM_IM_ADDR_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_GTM_IRQ_EN_AEIM_IM_ADDR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_IRQ_EN_AEIM_IM_ADDR_IRQ_EN_SHIFT)) & GTM_gtm_cls0_GTM_IRQ_EN_AEIM_IM_ADDR_IRQ_EN_MASK) #define GTM_gtm_cls0_GTM_IRQ_EN_AEIM_USP_BE_IRQ_EN_MASK (0x40U) #define GTM_gtm_cls0_GTM_IRQ_EN_AEIM_USP_BE_IRQ_EN_SHIFT (6U) #define GTM_gtm_cls0_GTM_IRQ_EN_AEIM_USP_BE_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_GTM_IRQ_EN_AEIM_USP_BE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_IRQ_EN_AEIM_USP_BE_IRQ_EN_SHIFT)) & GTM_gtm_cls0_GTM_IRQ_EN_AEIM_USP_BE_IRQ_EN_MASK) #define GTM_gtm_cls0_GTM_IRQ_EN_CLK_EN_ERR_IRQ_EN_MASK (0x80U) #define GTM_gtm_cls0_GTM_IRQ_EN_CLK_EN_ERR_IRQ_EN_SHIFT (7U) #define GTM_gtm_cls0_GTM_IRQ_EN_CLK_EN_ERR_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_GTM_IRQ_EN_CLK_EN_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_IRQ_EN_CLK_EN_ERR_IRQ_EN_SHIFT)) & GTM_gtm_cls0_GTM_IRQ_EN_CLK_EN_ERR_IRQ_EN_MASK) #define GTM_gtm_cls0_GTM_IRQ_EN_CLK_PER_ERR_IRQ_EN_MASK (0x100U) #define GTM_gtm_cls0_GTM_IRQ_EN_CLK_PER_ERR_IRQ_EN_SHIFT (8U) #define GTM_gtm_cls0_GTM_IRQ_EN_CLK_PER_ERR_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_GTM_IRQ_EN_CLK_PER_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_IRQ_EN_CLK_PER_ERR_IRQ_EN_SHIFT)) & GTM_gtm_cls0_GTM_IRQ_EN_CLK_PER_ERR_IRQ_EN_MASK) /*! @} */ /*! @name GTM_EIRQ_EN - GTM error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_GTM_EIRQ_EN_AEI_TO_XPT_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_GTM_EIRQ_EN_AEI_TO_XPT_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_GTM_EIRQ_EN_AEI_TO_XPT_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_GTM_EIRQ_EN_AEI_TO_XPT_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_EIRQ_EN_AEI_TO_XPT_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_GTM_EIRQ_EN_AEI_TO_XPT_EIRQ_EN_MASK) #define GTM_gtm_cls0_GTM_EIRQ_EN_AEI_USP_ADDR_EIRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_GTM_EIRQ_EN_AEI_USP_ADDR_EIRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_GTM_EIRQ_EN_AEI_USP_ADDR_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_GTM_EIRQ_EN_AEI_USP_ADDR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_EIRQ_EN_AEI_USP_ADDR_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_GTM_EIRQ_EN_AEI_USP_ADDR_EIRQ_EN_MASK) #define GTM_gtm_cls0_GTM_EIRQ_EN_AEI_IM_ADDR_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_GTM_EIRQ_EN_AEI_IM_ADDR_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_GTM_EIRQ_EN_AEI_IM_ADDR_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_GTM_EIRQ_EN_AEI_IM_ADDR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_EIRQ_EN_AEI_IM_ADDR_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_GTM_EIRQ_EN_AEI_IM_ADDR_EIRQ_EN_MASK) #define GTM_gtm_cls0_GTM_EIRQ_EN_AEI_USP_BE_EIRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_GTM_EIRQ_EN_AEI_USP_BE_EIRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_GTM_EIRQ_EN_AEI_USP_BE_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_GTM_EIRQ_EN_AEI_USP_BE_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_EIRQ_EN_AEI_USP_BE_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_GTM_EIRQ_EN_AEI_USP_BE_EIRQ_EN_MASK) #define GTM_gtm_cls0_GTM_EIRQ_EN_AEIM_USP_ADDR_EIRQ_EN_MASK (0x10U) #define GTM_gtm_cls0_GTM_EIRQ_EN_AEIM_USP_ADDR_EIRQ_EN_SHIFT (4U) #define GTM_gtm_cls0_GTM_EIRQ_EN_AEIM_USP_ADDR_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_GTM_EIRQ_EN_AEIM_USP_ADDR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_EIRQ_EN_AEIM_USP_ADDR_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_GTM_EIRQ_EN_AEIM_USP_ADDR_EIRQ_EN_MASK) #define GTM_gtm_cls0_GTM_EIRQ_EN_AEIM_IM_ADDR_EIRQ_EN_MASK (0x20U) #define GTM_gtm_cls0_GTM_EIRQ_EN_AEIM_IM_ADDR_EIRQ_EN_SHIFT (5U) #define GTM_gtm_cls0_GTM_EIRQ_EN_AEIM_IM_ADDR_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_GTM_EIRQ_EN_AEIM_IM_ADDR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_EIRQ_EN_AEIM_IM_ADDR_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_GTM_EIRQ_EN_AEIM_IM_ADDR_EIRQ_EN_MASK) #define GTM_gtm_cls0_GTM_EIRQ_EN_AEIM_USP_BE_EIRQ_EN_MASK (0x40U) #define GTM_gtm_cls0_GTM_EIRQ_EN_AEIM_USP_BE_EIRQ_EN_SHIFT (6U) #define GTM_gtm_cls0_GTM_EIRQ_EN_AEIM_USP_BE_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_GTM_EIRQ_EN_AEIM_USP_BE_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_EIRQ_EN_AEIM_USP_BE_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_GTM_EIRQ_EN_AEIM_USP_BE_EIRQ_EN_MASK) #define GTM_gtm_cls0_GTM_EIRQ_EN_CLK_EN_ERR_EIRQ_EN_MASK (0x80U) #define GTM_gtm_cls0_GTM_EIRQ_EN_CLK_EN_ERR_EIRQ_EN_SHIFT (7U) #define GTM_gtm_cls0_GTM_EIRQ_EN_CLK_EN_ERR_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_GTM_EIRQ_EN_CLK_EN_ERR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_EIRQ_EN_CLK_EN_ERR_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_GTM_EIRQ_EN_CLK_EN_ERR_EIRQ_EN_MASK) #define GTM_gtm_cls0_GTM_EIRQ_EN_CLK_PER_ERR_EIRQ_EN_MASK (0x100U) #define GTM_gtm_cls0_GTM_EIRQ_EN_CLK_PER_ERR_EIRQ_EN_SHIFT (8U) #define GTM_gtm_cls0_GTM_EIRQ_EN_CLK_PER_ERR_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_GTM_EIRQ_EN_CLK_PER_ERR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_EIRQ_EN_CLK_PER_ERR_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_GTM_EIRQ_EN_CLK_PER_ERR_EIRQ_EN_MASK) /*! @} */ /*! @name GTM_IRQ_FORCINT - GTM Software interrupt generation register */ /*! @{ */ #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEI_TO_XPT_MASK (0x1U) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEI_TO_XPT_SHIFT (0U) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEI_TO_XPT_WIDTH (1U) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEI_TO_XPT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEI_TO_XPT_SHIFT)) & GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEI_TO_XPT_MASK) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEI_USP_ADDR_MASK (0x2U) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEI_USP_ADDR_SHIFT (1U) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEI_USP_ADDR_WIDTH (1U) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEI_USP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEI_USP_ADDR_SHIFT)) & GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEI_USP_ADDR_MASK) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEI_IM_ADDR_MASK (0x4U) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEI_IM_ADDR_SHIFT (2U) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEI_IM_ADDR_WIDTH (1U) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEI_IM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEI_IM_ADDR_SHIFT)) & GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEI_IM_ADDR_MASK) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEI_USP_BE_MASK (0x8U) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEI_USP_BE_SHIFT (3U) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEI_USP_BE_WIDTH (1U) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEI_USP_BE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEI_USP_BE_SHIFT)) & GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEI_USP_BE_MASK) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEIM_USP_ADDR_MASK (0x10U) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEIM_USP_ADDR_SHIFT (4U) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEIM_USP_ADDR_WIDTH (1U) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEIM_USP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEIM_USP_ADDR_SHIFT)) & GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEIM_USP_ADDR_MASK) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEIM_IM_ADDR_MASK (0x20U) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEIM_IM_ADDR_SHIFT (5U) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEIM_IM_ADDR_WIDTH (1U) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEIM_IM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEIM_IM_ADDR_SHIFT)) & GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEIM_IM_ADDR_MASK) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEIM_USP_BE_MASK (0x40U) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEIM_USP_BE_SHIFT (6U) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEIM_USP_BE_WIDTH (1U) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEIM_USP_BE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEIM_USP_BE_SHIFT)) & GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_AEIM_USP_BE_MASK) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_CLK_EN_ERR_MASK (0x80U) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_CLK_EN_ERR_SHIFT (7U) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_CLK_EN_ERR_WIDTH (1U) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_CLK_EN_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_CLK_EN_ERR_SHIFT)) & GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_CLK_EN_ERR_MASK) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_CLK_PER_ERR_MASK (0x100U) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_CLK_PER_ERR_SHIFT (8U) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_CLK_PER_ERR_WIDTH (1U) #define GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_CLK_PER_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_CLK_PER_ERR_SHIFT)) & GTM_gtm_cls0_GTM_IRQ_FORCINT_TRG_CLK_PER_ERR_MASK) /*! @} */ /*! @name GTM_IRQ_MODE - GTM top level interrupts mode selection */ /*! @{ */ #define GTM_gtm_cls0_GTM_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_GTM_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_GTM_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_GTM_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_GTM_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name GTM_CLS_CLK_CFG - GTM Cluster Clock Configuration */ /*! @{ */ #define GTM_gtm_cls0_GTM_CLS_CLK_CFG_CLS0_CLK_DIV_MASK (0x3U) #define GTM_gtm_cls0_GTM_CLS_CLK_CFG_CLS0_CLK_DIV_SHIFT (0U) #define GTM_gtm_cls0_GTM_CLS_CLK_CFG_CLS0_CLK_DIV_WIDTH (2U) #define GTM_gtm_cls0_GTM_CLS_CLK_CFG_CLS0_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_CLS_CLK_CFG_CLS0_CLK_DIV_SHIFT)) & GTM_gtm_cls0_GTM_CLS_CLK_CFG_CLS0_CLK_DIV_MASK) #define GTM_gtm_cls0_GTM_CLS_CLK_CFG_CLS1_CLK_DIV_MASK (0xCU) #define GTM_gtm_cls0_GTM_CLS_CLK_CFG_CLS1_CLK_DIV_SHIFT (2U) #define GTM_gtm_cls0_GTM_CLS_CLK_CFG_CLS1_CLK_DIV_WIDTH (2U) #define GTM_gtm_cls0_GTM_CLS_CLK_CFG_CLS1_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_CLS_CLK_CFG_CLS1_CLK_DIV_SHIFT)) & GTM_gtm_cls0_GTM_CLS_CLK_CFG_CLS1_CLK_DIV_MASK) #define GTM_gtm_cls0_GTM_CLS_CLK_CFG_CLS2_CLK_DIV_MASK (0x30U) #define GTM_gtm_cls0_GTM_CLS_CLK_CFG_CLS2_CLK_DIV_SHIFT (4U) #define GTM_gtm_cls0_GTM_CLS_CLK_CFG_CLS2_CLK_DIV_WIDTH (2U) #define GTM_gtm_cls0_GTM_CLS_CLK_CFG_CLS2_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_CLS_CLK_CFG_CLS2_CLK_DIV_SHIFT)) & GTM_gtm_cls0_GTM_CLS_CLK_CFG_CLS2_CLK_DIV_MASK) #define GTM_gtm_cls0_GTM_CLS_CLK_CFG_CLS3_CLK_DIV_MASK (0xC0U) #define GTM_gtm_cls0_GTM_CLS_CLK_CFG_CLS3_CLK_DIV_SHIFT (6U) #define GTM_gtm_cls0_GTM_CLS_CLK_CFG_CLS3_CLK_DIV_WIDTH (2U) #define GTM_gtm_cls0_GTM_CLS_CLK_CFG_CLS3_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_CLS_CLK_CFG_CLS3_CLK_DIV_SHIFT)) & GTM_gtm_cls0_GTM_CLS_CLK_CFG_CLS3_CLK_DIV_MASK) /*! @} */ /*! @name GTM_ARU_COM_DIS - GTM ARU communication disable */ /*! @{ */ #define GTM_gtm_cls0_GTM_ARU_COM_DIS_CLS0_DIS_MASK (0x1U) #define GTM_gtm_cls0_GTM_ARU_COM_DIS_CLS0_DIS_SHIFT (0U) #define GTM_gtm_cls0_GTM_ARU_COM_DIS_CLS0_DIS_WIDTH (1U) #define GTM_gtm_cls0_GTM_ARU_COM_DIS_CLS0_DIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_ARU_COM_DIS_CLS0_DIS_SHIFT)) & GTM_gtm_cls0_GTM_ARU_COM_DIS_CLS0_DIS_MASK) #define GTM_gtm_cls0_GTM_ARU_COM_DIS_CLS1_DIS_MASK (0x2U) #define GTM_gtm_cls0_GTM_ARU_COM_DIS_CLS1_DIS_SHIFT (1U) #define GTM_gtm_cls0_GTM_ARU_COM_DIS_CLS1_DIS_WIDTH (1U) #define GTM_gtm_cls0_GTM_ARU_COM_DIS_CLS1_DIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_ARU_COM_DIS_CLS1_DIS_SHIFT)) & GTM_gtm_cls0_GTM_ARU_COM_DIS_CLS1_DIS_MASK) #define GTM_gtm_cls0_GTM_ARU_COM_DIS_CLS2_DIS_MASK (0x4U) #define GTM_gtm_cls0_GTM_ARU_COM_DIS_CLS2_DIS_SHIFT (2U) #define GTM_gtm_cls0_GTM_ARU_COM_DIS_CLS2_DIS_WIDTH (1U) #define GTM_gtm_cls0_GTM_ARU_COM_DIS_CLS2_DIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_ARU_COM_DIS_CLS2_DIS_SHIFT)) & GTM_gtm_cls0_GTM_ARU_COM_DIS_CLS2_DIS_MASK) #define GTM_gtm_cls0_GTM_ARU_COM_DIS_CLS3_DIS_MASK (0x8U) #define GTM_gtm_cls0_GTM_ARU_COM_DIS_CLS3_DIS_SHIFT (3U) #define GTM_gtm_cls0_GTM_ARU_COM_DIS_CLS3_DIS_WIDTH (1U) #define GTM_gtm_cls0_GTM_ARU_COM_DIS_CLS3_DIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_GTM_ARU_COM_DIS_CLS3_DIS_SHIFT)) & GTM_gtm_cls0_GTM_ARU_COM_DIS_CLS3_DIS_MASK) /*! @} */ /*! @name BRIDGE_MODE - GTM AEI bridge mode register */ /*! @{ */ #define GTM_gtm_cls0_BRIDGE_MODE_BRG_MODE_MASK (0x1U) #define GTM_gtm_cls0_BRIDGE_MODE_BRG_MODE_SHIFT (0U) #define GTM_gtm_cls0_BRIDGE_MODE_BRG_MODE_WIDTH (1U) #define GTM_gtm_cls0_BRIDGE_MODE_BRG_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRIDGE_MODE_BRG_MODE_SHIFT)) & GTM_gtm_cls0_BRIDGE_MODE_BRG_MODE_MASK) #define GTM_gtm_cls0_BRIDGE_MODE_MSK_WR_RSP_MASK (0x2U) #define GTM_gtm_cls0_BRIDGE_MODE_MSK_WR_RSP_SHIFT (1U) #define GTM_gtm_cls0_BRIDGE_MODE_MSK_WR_RSP_WIDTH (1U) #define GTM_gtm_cls0_BRIDGE_MODE_MSK_WR_RSP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRIDGE_MODE_MSK_WR_RSP_SHIFT)) & GTM_gtm_cls0_BRIDGE_MODE_MSK_WR_RSP_MASK) #define GTM_gtm_cls0_BRIDGE_MODE_BYPASS_SYNC_MASK (0x4U) #define GTM_gtm_cls0_BRIDGE_MODE_BYPASS_SYNC_SHIFT (2U) #define GTM_gtm_cls0_BRIDGE_MODE_BYPASS_SYNC_WIDTH (1U) #define GTM_gtm_cls0_BRIDGE_MODE_BYPASS_SYNC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRIDGE_MODE_BYPASS_SYNC_SHIFT)) & GTM_gtm_cls0_BRIDGE_MODE_BYPASS_SYNC_MASK) #define GTM_gtm_cls0_BRIDGE_MODE_MODE_UP_PGR_MASK (0x100U) #define GTM_gtm_cls0_BRIDGE_MODE_MODE_UP_PGR_SHIFT (8U) #define GTM_gtm_cls0_BRIDGE_MODE_MODE_UP_PGR_WIDTH (1U) #define GTM_gtm_cls0_BRIDGE_MODE_MODE_UP_PGR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRIDGE_MODE_MODE_UP_PGR_SHIFT)) & GTM_gtm_cls0_BRIDGE_MODE_MODE_UP_PGR_MASK) #define GTM_gtm_cls0_BRIDGE_MODE_BUFF_OVL_MASK (0x200U) #define GTM_gtm_cls0_BRIDGE_MODE_BUFF_OVL_SHIFT (9U) #define GTM_gtm_cls0_BRIDGE_MODE_BUFF_OVL_WIDTH (1U) #define GTM_gtm_cls0_BRIDGE_MODE_BUFF_OVL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRIDGE_MODE_BUFF_OVL_SHIFT)) & GTM_gtm_cls0_BRIDGE_MODE_BUFF_OVL_MASK) #define GTM_gtm_cls0_BRIDGE_MODE_SYNC_INPUT_REG_MASK (0x1000U) #define GTM_gtm_cls0_BRIDGE_MODE_SYNC_INPUT_REG_SHIFT (12U) #define GTM_gtm_cls0_BRIDGE_MODE_SYNC_INPUT_REG_WIDTH (1U) #define GTM_gtm_cls0_BRIDGE_MODE_SYNC_INPUT_REG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRIDGE_MODE_SYNC_INPUT_REG_SHIFT)) & GTM_gtm_cls0_BRIDGE_MODE_SYNC_INPUT_REG_MASK) #define GTM_gtm_cls0_BRIDGE_MODE_BRG_RST_MASK (0x10000U) #define GTM_gtm_cls0_BRIDGE_MODE_BRG_RST_SHIFT (16U) #define GTM_gtm_cls0_BRIDGE_MODE_BRG_RST_WIDTH (1U) #define GTM_gtm_cls0_BRIDGE_MODE_BRG_RST(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRIDGE_MODE_BRG_RST_SHIFT)) & GTM_gtm_cls0_BRIDGE_MODE_BRG_RST_MASK) #define GTM_gtm_cls0_BRIDGE_MODE_BUFF_DPT_MASK (0xFF000000U) #define GTM_gtm_cls0_BRIDGE_MODE_BUFF_DPT_SHIFT (24U) #define GTM_gtm_cls0_BRIDGE_MODE_BUFF_DPT_WIDTH (8U) #define GTM_gtm_cls0_BRIDGE_MODE_BUFF_DPT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRIDGE_MODE_BUFF_DPT_SHIFT)) & GTM_gtm_cls0_BRIDGE_MODE_BUFF_DPT_MASK) /*! @} */ /*! @name BRIDGE_PTR1 - GTM AEI bridge pointer 1 register */ /*! @{ */ #define GTM_gtm_cls0_BRIDGE_PTR1_NEW_TRAN_PTR_MASK (0x1FU) #define GTM_gtm_cls0_BRIDGE_PTR1_NEW_TRAN_PTR_SHIFT (0U) #define GTM_gtm_cls0_BRIDGE_PTR1_NEW_TRAN_PTR_WIDTH (5U) #define GTM_gtm_cls0_BRIDGE_PTR1_NEW_TRAN_PTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRIDGE_PTR1_NEW_TRAN_PTR_SHIFT)) & GTM_gtm_cls0_BRIDGE_PTR1_NEW_TRAN_PTR_MASK) #define GTM_gtm_cls0_BRIDGE_PTR1_FIRST_RSP_PTR_MASK (0x3E0U) #define GTM_gtm_cls0_BRIDGE_PTR1_FIRST_RSP_PTR_SHIFT (5U) #define GTM_gtm_cls0_BRIDGE_PTR1_FIRST_RSP_PTR_WIDTH (5U) #define GTM_gtm_cls0_BRIDGE_PTR1_FIRST_RSP_PTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRIDGE_PTR1_FIRST_RSP_PTR_SHIFT)) & GTM_gtm_cls0_BRIDGE_PTR1_FIRST_RSP_PTR_MASK) #define GTM_gtm_cls0_BRIDGE_PTR1_TRAN_IN_PGR_MASK (0x7C00U) #define GTM_gtm_cls0_BRIDGE_PTR1_TRAN_IN_PGR_SHIFT (10U) #define GTM_gtm_cls0_BRIDGE_PTR1_TRAN_IN_PGR_WIDTH (5U) #define GTM_gtm_cls0_BRIDGE_PTR1_TRAN_IN_PGR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRIDGE_PTR1_TRAN_IN_PGR_SHIFT)) & GTM_gtm_cls0_BRIDGE_PTR1_TRAN_IN_PGR_MASK) #define GTM_gtm_cls0_BRIDGE_PTR1_ABT_TRAN_PGR_MASK (0xF8000U) #define GTM_gtm_cls0_BRIDGE_PTR1_ABT_TRAN_PGR_SHIFT (15U) #define GTM_gtm_cls0_BRIDGE_PTR1_ABT_TRAN_PGR_WIDTH (5U) #define GTM_gtm_cls0_BRIDGE_PTR1_ABT_TRAN_PGR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRIDGE_PTR1_ABT_TRAN_PGR_SHIFT)) & GTM_gtm_cls0_BRIDGE_PTR1_ABT_TRAN_PGR_MASK) #define GTM_gtm_cls0_BRIDGE_PTR1_FBC_MASK (0x3F00000U) #define GTM_gtm_cls0_BRIDGE_PTR1_FBC_SHIFT (20U) #define GTM_gtm_cls0_BRIDGE_PTR1_FBC_WIDTH (6U) #define GTM_gtm_cls0_BRIDGE_PTR1_FBC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRIDGE_PTR1_FBC_SHIFT)) & GTM_gtm_cls0_BRIDGE_PTR1_FBC_MASK) #define GTM_gtm_cls0_BRIDGE_PTR1_RSP_TRAN_RDY_MASK (0xFC000000U) #define GTM_gtm_cls0_BRIDGE_PTR1_RSP_TRAN_RDY_SHIFT (26U) #define GTM_gtm_cls0_BRIDGE_PTR1_RSP_TRAN_RDY_WIDTH (6U) #define GTM_gtm_cls0_BRIDGE_PTR1_RSP_TRAN_RDY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRIDGE_PTR1_RSP_TRAN_RDY_SHIFT)) & GTM_gtm_cls0_BRIDGE_PTR1_RSP_TRAN_RDY_MASK) /*! @} */ /*! @name BRIDGE_PTR2 - GTM AEI bridge pointer 2 register */ /*! @{ */ #define GTM_gtm_cls0_BRIDGE_PTR2_TRAN_IN_PGR2_MASK (0x1FU) #define GTM_gtm_cls0_BRIDGE_PTR2_TRAN_IN_PGR2_SHIFT (0U) #define GTM_gtm_cls0_BRIDGE_PTR2_TRAN_IN_PGR2_WIDTH (5U) #define GTM_gtm_cls0_BRIDGE_PTR2_TRAN_IN_PGR2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRIDGE_PTR2_TRAN_IN_PGR2_SHIFT)) & GTM_gtm_cls0_BRIDGE_PTR2_TRAN_IN_PGR2_MASK) /*! @} */ /*! @name MCS_AEM_DIS - GTM MCS master port disable register */ /*! @{ */ #define GTM_gtm_cls0_MCS_AEM_DIS_DIS_CLS0_MASK (0x3U) #define GTM_gtm_cls0_MCS_AEM_DIS_DIS_CLS0_SHIFT (0U) #define GTM_gtm_cls0_MCS_AEM_DIS_DIS_CLS0_WIDTH (2U) #define GTM_gtm_cls0_MCS_AEM_DIS_DIS_CLS0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS_AEM_DIS_DIS_CLS0_SHIFT)) & GTM_gtm_cls0_MCS_AEM_DIS_DIS_CLS0_MASK) #define GTM_gtm_cls0_MCS_AEM_DIS_DIS_CLS1_MASK (0xCU) #define GTM_gtm_cls0_MCS_AEM_DIS_DIS_CLS1_SHIFT (2U) #define GTM_gtm_cls0_MCS_AEM_DIS_DIS_CLS1_WIDTH (2U) #define GTM_gtm_cls0_MCS_AEM_DIS_DIS_CLS1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS_AEM_DIS_DIS_CLS1_SHIFT)) & GTM_gtm_cls0_MCS_AEM_DIS_DIS_CLS1_MASK) #define GTM_gtm_cls0_MCS_AEM_DIS_DIS_CLS2_MASK (0x30U) #define GTM_gtm_cls0_MCS_AEM_DIS_DIS_CLS2_SHIFT (4U) #define GTM_gtm_cls0_MCS_AEM_DIS_DIS_CLS2_WIDTH (2U) #define GTM_gtm_cls0_MCS_AEM_DIS_DIS_CLS2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS_AEM_DIS_DIS_CLS2_SHIFT)) & GTM_gtm_cls0_MCS_AEM_DIS_DIS_CLS2_MASK) #define GTM_gtm_cls0_MCS_AEM_DIS_DIS_CLS3_MASK (0xC0U) #define GTM_gtm_cls0_MCS_AEM_DIS_DIS_CLS3_SHIFT (6U) #define GTM_gtm_cls0_MCS_AEM_DIS_DIS_CLS3_WIDTH (2U) #define GTM_gtm_cls0_MCS_AEM_DIS_DIS_CLS3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS_AEM_DIS_DIS_CLS3_SHIFT)) & GTM_gtm_cls0_MCS_AEM_DIS_DIS_CLS3_MASK) /*! @} */ /*! @name CMU_CLK_EN - CMU clock enable */ /*! @{ */ #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK0_MASK (0x3U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK0_SHIFT (0U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK0_WIDTH (2U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_CLK_EN_EN_CLK0_SHIFT)) & GTM_gtm_cls0_CMU_CLK_EN_EN_CLK0_MASK) #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK1_MASK (0xCU) #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK1_SHIFT (2U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK1_WIDTH (2U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_CLK_EN_EN_CLK1_SHIFT)) & GTM_gtm_cls0_CMU_CLK_EN_EN_CLK1_MASK) #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK2_MASK (0x30U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK2_SHIFT (4U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK2_WIDTH (2U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_CLK_EN_EN_CLK2_SHIFT)) & GTM_gtm_cls0_CMU_CLK_EN_EN_CLK2_MASK) #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK3_MASK (0xC0U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK3_SHIFT (6U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK3_WIDTH (2U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_CLK_EN_EN_CLK3_SHIFT)) & GTM_gtm_cls0_CMU_CLK_EN_EN_CLK3_MASK) #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK4_MASK (0x300U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK4_SHIFT (8U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK4_WIDTH (2U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_CLK_EN_EN_CLK4_SHIFT)) & GTM_gtm_cls0_CMU_CLK_EN_EN_CLK4_MASK) #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK5_MASK (0xC00U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK5_SHIFT (10U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK5_WIDTH (2U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_CLK_EN_EN_CLK5_SHIFT)) & GTM_gtm_cls0_CMU_CLK_EN_EN_CLK5_MASK) #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK6_MASK (0x3000U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK6_SHIFT (12U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK6_WIDTH (2U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_CLK_EN_EN_CLK6_SHIFT)) & GTM_gtm_cls0_CMU_CLK_EN_EN_CLK6_MASK) #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK7_MASK (0xC000U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK7_SHIFT (14U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK7_WIDTH (2U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_CLK7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_CLK_EN_EN_CLK7_SHIFT)) & GTM_gtm_cls0_CMU_CLK_EN_EN_CLK7_MASK) #define GTM_gtm_cls0_CMU_CLK_EN_EN_ECLK0_MASK (0x30000U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_ECLK0_SHIFT (16U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_ECLK0_WIDTH (2U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_ECLK0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_CLK_EN_EN_ECLK0_SHIFT)) & GTM_gtm_cls0_CMU_CLK_EN_EN_ECLK0_MASK) #define GTM_gtm_cls0_CMU_CLK_EN_EN_ECLK1_MASK (0xC0000U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_ECLK1_SHIFT (18U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_ECLK1_WIDTH (2U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_ECLK1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_CLK_EN_EN_ECLK1_SHIFT)) & GTM_gtm_cls0_CMU_CLK_EN_EN_ECLK1_MASK) #define GTM_gtm_cls0_CMU_CLK_EN_EN_ECLK2_MASK (0x300000U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_ECLK2_SHIFT (20U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_ECLK2_WIDTH (2U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_ECLK2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_CLK_EN_EN_ECLK2_SHIFT)) & GTM_gtm_cls0_CMU_CLK_EN_EN_ECLK2_MASK) #define GTM_gtm_cls0_CMU_CLK_EN_EN_FXCLK_MASK (0xC00000U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_FXCLK_SHIFT (22U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_FXCLK_WIDTH (2U) #define GTM_gtm_cls0_CMU_CLK_EN_EN_FXCLK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_CLK_EN_EN_FXCLK_SHIFT)) & GTM_gtm_cls0_CMU_CLK_EN_EN_FXCLK_MASK) /*! @} */ /*! @name CMU_GCLK_NUM - The numerator for CMU global clock resolution generator */ /*! @{ */ #define GTM_gtm_cls0_CMU_GCLK_NUM_GCLK_NUM_MASK (0xFFFFFFU) #define GTM_gtm_cls0_CMU_GCLK_NUM_GCLK_NUM_SHIFT (0U) #define GTM_gtm_cls0_CMU_GCLK_NUM_GCLK_NUM_WIDTH (24U) #define GTM_gtm_cls0_CMU_GCLK_NUM_GCLK_NUM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_GCLK_NUM_GCLK_NUM_SHIFT)) & GTM_gtm_cls0_CMU_GCLK_NUM_GCLK_NUM_MASK) /*! @} */ /*! @name CMU_GCLK_DEN - The denominator for CMU global clock resolution generator */ /*! @{ */ #define GTM_gtm_cls0_CMU_GCLK_DEN_GCLK_DEN_MASK (0xFFFFFFU) #define GTM_gtm_cls0_CMU_GCLK_DEN_GCLK_DEN_SHIFT (0U) #define GTM_gtm_cls0_CMU_GCLK_DEN_GCLK_DEN_WIDTH (24U) #define GTM_gtm_cls0_CMU_GCLK_DEN_GCLK_DEN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_GCLK_DEN_GCLK_DEN_SHIFT)) & GTM_gtm_cls0_CMU_GCLK_DEN_GCLK_DEN_MASK) /*! @} */ /*! @name CMU_CLK_0_CTRL - CMU control for clock resolution generator [x] */ /*! @{ */ #define GTM_gtm_cls0_CMU_CLK_0_CTRL_CLK_CNT_MASK (0xFFFFFFU) #define GTM_gtm_cls0_CMU_CLK_0_CTRL_CLK_CNT_SHIFT (0U) #define GTM_gtm_cls0_CMU_CLK_0_CTRL_CLK_CNT_WIDTH (24U) #define GTM_gtm_cls0_CMU_CLK_0_CTRL_CLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_CLK_0_CTRL_CLK_CNT_SHIFT)) & GTM_gtm_cls0_CMU_CLK_0_CTRL_CLK_CNT_MASK) /*! @} */ /*! @name CMU_CLK_1_CTRL - CMU control for clock resolution generator [x] */ /*! @{ */ #define GTM_gtm_cls0_CMU_CLK_1_CTRL_CLK_CNT_MASK (0xFFFFFFU) #define GTM_gtm_cls0_CMU_CLK_1_CTRL_CLK_CNT_SHIFT (0U) #define GTM_gtm_cls0_CMU_CLK_1_CTRL_CLK_CNT_WIDTH (24U) #define GTM_gtm_cls0_CMU_CLK_1_CTRL_CLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_CLK_1_CTRL_CLK_CNT_SHIFT)) & GTM_gtm_cls0_CMU_CLK_1_CTRL_CLK_CNT_MASK) /*! @} */ /*! @name CMU_CLK_2_CTRL - CMU control for clock resolution generator [x] */ /*! @{ */ #define GTM_gtm_cls0_CMU_CLK_2_CTRL_CLK_CNT_MASK (0xFFFFFFU) #define GTM_gtm_cls0_CMU_CLK_2_CTRL_CLK_CNT_SHIFT (0U) #define GTM_gtm_cls0_CMU_CLK_2_CTRL_CLK_CNT_WIDTH (24U) #define GTM_gtm_cls0_CMU_CLK_2_CTRL_CLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_CLK_2_CTRL_CLK_CNT_SHIFT)) & GTM_gtm_cls0_CMU_CLK_2_CTRL_CLK_CNT_MASK) /*! @} */ /*! @name CMU_CLK_3_CTRL - CMU control for clock resolution generator [x] */ /*! @{ */ #define GTM_gtm_cls0_CMU_CLK_3_CTRL_CLK_CNT_MASK (0xFFFFFFU) #define GTM_gtm_cls0_CMU_CLK_3_CTRL_CLK_CNT_SHIFT (0U) #define GTM_gtm_cls0_CMU_CLK_3_CTRL_CLK_CNT_WIDTH (24U) #define GTM_gtm_cls0_CMU_CLK_3_CTRL_CLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_CLK_3_CTRL_CLK_CNT_SHIFT)) & GTM_gtm_cls0_CMU_CLK_3_CTRL_CLK_CNT_MASK) /*! @} */ /*! @name CMU_CLK_4_CTRL - CMU control for clock resolution generator [x] */ /*! @{ */ #define GTM_gtm_cls0_CMU_CLK_4_CTRL_CLK_CNT_MASK (0xFFFFFFU) #define GTM_gtm_cls0_CMU_CLK_4_CTRL_CLK_CNT_SHIFT (0U) #define GTM_gtm_cls0_CMU_CLK_4_CTRL_CLK_CNT_WIDTH (24U) #define GTM_gtm_cls0_CMU_CLK_4_CTRL_CLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_CLK_4_CTRL_CLK_CNT_SHIFT)) & GTM_gtm_cls0_CMU_CLK_4_CTRL_CLK_CNT_MASK) /*! @} */ /*! @name CMU_CLK_5_CTRL - CMU control for clock resolution generator [x] */ /*! @{ */ #define GTM_gtm_cls0_CMU_CLK_5_CTRL_CLK_CNT_MASK (0xFFFFFFU) #define GTM_gtm_cls0_CMU_CLK_5_CTRL_CLK_CNT_SHIFT (0U) #define GTM_gtm_cls0_CMU_CLK_5_CTRL_CLK_CNT_WIDTH (24U) #define GTM_gtm_cls0_CMU_CLK_5_CTRL_CLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_CLK_5_CTRL_CLK_CNT_SHIFT)) & GTM_gtm_cls0_CMU_CLK_5_CTRL_CLK_CNT_MASK) /*! @} */ /*! @name CMU_CLK_6_CTRL - CMU control for clock resolution generator 6 */ /*! @{ */ #define GTM_gtm_cls0_CMU_CLK_6_CTRL_CLK_CNT_MASK (0xFFFFFFU) #define GTM_gtm_cls0_CMU_CLK_6_CTRL_CLK_CNT_SHIFT (0U) #define GTM_gtm_cls0_CMU_CLK_6_CTRL_CLK_CNT_WIDTH (24U) #define GTM_gtm_cls0_CMU_CLK_6_CTRL_CLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_CLK_6_CTRL_CLK_CNT_SHIFT)) & GTM_gtm_cls0_CMU_CLK_6_CTRL_CLK_CNT_MASK) #define GTM_gtm_cls0_CMU_CLK_6_CTRL_CLK_SEL_MASK (0x3000000U) #define GTM_gtm_cls0_CMU_CLK_6_CTRL_CLK_SEL_SHIFT (24U) #define GTM_gtm_cls0_CMU_CLK_6_CTRL_CLK_SEL_WIDTH (2U) #define GTM_gtm_cls0_CMU_CLK_6_CTRL_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_CLK_6_CTRL_CLK_SEL_SHIFT)) & GTM_gtm_cls0_CMU_CLK_6_CTRL_CLK_SEL_MASK) /*! @} */ /*! @name CMU_CLK_7_CTRL - CMU control for clock resolution generator 7 */ /*! @{ */ #define GTM_gtm_cls0_CMU_CLK_7_CTRL_CLK_CNT_MASK (0xFFFFFFU) #define GTM_gtm_cls0_CMU_CLK_7_CTRL_CLK_CNT_SHIFT (0U) #define GTM_gtm_cls0_CMU_CLK_7_CTRL_CLK_CNT_WIDTH (24U) #define GTM_gtm_cls0_CMU_CLK_7_CTRL_CLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_CLK_7_CTRL_CLK_CNT_SHIFT)) & GTM_gtm_cls0_CMU_CLK_7_CTRL_CLK_CNT_MASK) #define GTM_gtm_cls0_CMU_CLK_7_CTRL_CLK_SEL_MASK (0x3000000U) #define GTM_gtm_cls0_CMU_CLK_7_CTRL_CLK_SEL_SHIFT (24U) #define GTM_gtm_cls0_CMU_CLK_7_CTRL_CLK_SEL_WIDTH (2U) #define GTM_gtm_cls0_CMU_CLK_7_CTRL_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_CLK_7_CTRL_CLK_SEL_SHIFT)) & GTM_gtm_cls0_CMU_CLK_7_CTRL_CLK_SEL_MASK) /*! @} */ /*! @name CMU_ECLK_0_NUM - The numerator for the external clock resolution generator [z] */ /*! @{ */ #define GTM_gtm_cls0_CMU_ECLK_0_NUM_ECLK_NUM_MASK (0xFFFFFFU) #define GTM_gtm_cls0_CMU_ECLK_0_NUM_ECLK_NUM_SHIFT (0U) #define GTM_gtm_cls0_CMU_ECLK_0_NUM_ECLK_NUM_WIDTH (24U) #define GTM_gtm_cls0_CMU_ECLK_0_NUM_ECLK_NUM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_ECLK_0_NUM_ECLK_NUM_SHIFT)) & GTM_gtm_cls0_CMU_ECLK_0_NUM_ECLK_NUM_MASK) /*! @} */ /*! @name CMU_ECLK_0_DEN - The denominator for the external clock resolution generator [z] */ /*! @{ */ #define GTM_gtm_cls0_CMU_ECLK_0_DEN_ECLK_DEN_MASK (0xFFFFFFU) #define GTM_gtm_cls0_CMU_ECLK_0_DEN_ECLK_DEN_SHIFT (0U) #define GTM_gtm_cls0_CMU_ECLK_0_DEN_ECLK_DEN_WIDTH (24U) #define GTM_gtm_cls0_CMU_ECLK_0_DEN_ECLK_DEN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_ECLK_0_DEN_ECLK_DEN_SHIFT)) & GTM_gtm_cls0_CMU_ECLK_0_DEN_ECLK_DEN_MASK) /*! @} */ /*! @name CMU_ECLK_1_NUM - The numerator for the external clock resolution generator [z] */ /*! @{ */ #define GTM_gtm_cls0_CMU_ECLK_1_NUM_ECLK_NUM_MASK (0xFFFFFFU) #define GTM_gtm_cls0_CMU_ECLK_1_NUM_ECLK_NUM_SHIFT (0U) #define GTM_gtm_cls0_CMU_ECLK_1_NUM_ECLK_NUM_WIDTH (24U) #define GTM_gtm_cls0_CMU_ECLK_1_NUM_ECLK_NUM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_ECLK_1_NUM_ECLK_NUM_SHIFT)) & GTM_gtm_cls0_CMU_ECLK_1_NUM_ECLK_NUM_MASK) /*! @} */ /*! @name CMU_ECLK_1_DEN - The denominator for the external clock resolution generator [z] */ /*! @{ */ #define GTM_gtm_cls0_CMU_ECLK_1_DEN_ECLK_DEN_MASK (0xFFFFFFU) #define GTM_gtm_cls0_CMU_ECLK_1_DEN_ECLK_DEN_SHIFT (0U) #define GTM_gtm_cls0_CMU_ECLK_1_DEN_ECLK_DEN_WIDTH (24U) #define GTM_gtm_cls0_CMU_ECLK_1_DEN_ECLK_DEN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_ECLK_1_DEN_ECLK_DEN_SHIFT)) & GTM_gtm_cls0_CMU_ECLK_1_DEN_ECLK_DEN_MASK) /*! @} */ /*! @name CMU_ECLK_2_NUM - The numerator for the external clock resolution generator [z] */ /*! @{ */ #define GTM_gtm_cls0_CMU_ECLK_2_NUM_ECLK_NUM_MASK (0xFFFFFFU) #define GTM_gtm_cls0_CMU_ECLK_2_NUM_ECLK_NUM_SHIFT (0U) #define GTM_gtm_cls0_CMU_ECLK_2_NUM_ECLK_NUM_WIDTH (24U) #define GTM_gtm_cls0_CMU_ECLK_2_NUM_ECLK_NUM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_ECLK_2_NUM_ECLK_NUM_SHIFT)) & GTM_gtm_cls0_CMU_ECLK_2_NUM_ECLK_NUM_MASK) /*! @} */ /*! @name CMU_ECLK_2_DEN - The denominator for the external clock resolution generator [z] */ /*! @{ */ #define GTM_gtm_cls0_CMU_ECLK_2_DEN_ECLK_DEN_MASK (0xFFFFFFU) #define GTM_gtm_cls0_CMU_ECLK_2_DEN_ECLK_DEN_SHIFT (0U) #define GTM_gtm_cls0_CMU_ECLK_2_DEN_ECLK_DEN_WIDTH (24U) #define GTM_gtm_cls0_CMU_ECLK_2_DEN_ECLK_DEN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_ECLK_2_DEN_ECLK_DEN_SHIFT)) & GTM_gtm_cls0_CMU_ECLK_2_DEN_ECLK_DEN_MASK) /*! @} */ /*! @name CMU_FXCLK_CTRL - CMU control for selection of FCR subblock input */ /*! @{ */ #define GTM_gtm_cls0_CMU_FXCLK_CTRL_FXCLK_SEL_MASK (0xFU) #define GTM_gtm_cls0_CMU_FXCLK_CTRL_FXCLK_SEL_SHIFT (0U) #define GTM_gtm_cls0_CMU_FXCLK_CTRL_FXCLK_SEL_WIDTH (4U) #define GTM_gtm_cls0_CMU_FXCLK_CTRL_FXCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_FXCLK_CTRL_FXCLK_SEL_SHIFT)) & GTM_gtm_cls0_CMU_FXCLK_CTRL_FXCLK_SEL_MASK) /*! @} */ /*! @name CMU_GLB_CTRL - CMU synchronizing ARU and clock source */ /*! @{ */ #define GTM_gtm_cls0_CMU_GLB_CTRL_ARU_ADDR_RSTGLB_MASK (0x1U) #define GTM_gtm_cls0_CMU_GLB_CTRL_ARU_ADDR_RSTGLB_SHIFT (0U) #define GTM_gtm_cls0_CMU_GLB_CTRL_ARU_ADDR_RSTGLB_WIDTH (1U) #define GTM_gtm_cls0_CMU_GLB_CTRL_ARU_ADDR_RSTGLB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_GLB_CTRL_ARU_ADDR_RSTGLB_SHIFT)) & GTM_gtm_cls0_CMU_GLB_CTRL_ARU_ADDR_RSTGLB_MASK) /*! @} */ /*! @name CMU_CLK_CTRL - CMU control for clock resolution generator */ /*! @{ */ #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK0_EXT_DIVIDER_MASK (0x1U) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK0_EXT_DIVIDER_SHIFT (0U) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK0_EXT_DIVIDER_WIDTH (1U) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK0_EXT_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_CLK_CTRL_CLK0_EXT_DIVIDER_SHIFT)) & GTM_gtm_cls0_CMU_CLK_CTRL_CLK0_EXT_DIVIDER_MASK) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK1_EXT_DIVIDER_MASK (0x2U) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK1_EXT_DIVIDER_SHIFT (1U) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK1_EXT_DIVIDER_WIDTH (1U) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK1_EXT_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_CLK_CTRL_CLK1_EXT_DIVIDER_SHIFT)) & GTM_gtm_cls0_CMU_CLK_CTRL_CLK1_EXT_DIVIDER_MASK) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK2_EXT_DIVIDER_MASK (0x4U) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK2_EXT_DIVIDER_SHIFT (2U) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK2_EXT_DIVIDER_WIDTH (1U) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK2_EXT_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_CLK_CTRL_CLK2_EXT_DIVIDER_SHIFT)) & GTM_gtm_cls0_CMU_CLK_CTRL_CLK2_EXT_DIVIDER_MASK) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK3_EXT_DIVIDER_MASK (0x8U) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK3_EXT_DIVIDER_SHIFT (3U) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK3_EXT_DIVIDER_WIDTH (1U) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK3_EXT_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_CLK_CTRL_CLK3_EXT_DIVIDER_SHIFT)) & GTM_gtm_cls0_CMU_CLK_CTRL_CLK3_EXT_DIVIDER_MASK) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK4_EXT_DIVIDER_MASK (0x10U) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK4_EXT_DIVIDER_SHIFT (4U) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK4_EXT_DIVIDER_WIDTH (1U) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK4_EXT_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_CLK_CTRL_CLK4_EXT_DIVIDER_SHIFT)) & GTM_gtm_cls0_CMU_CLK_CTRL_CLK4_EXT_DIVIDER_MASK) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK5_EXT_DIVIDER_MASK (0x20U) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK5_EXT_DIVIDER_SHIFT (5U) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK5_EXT_DIVIDER_WIDTH (1U) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK5_EXT_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_CLK_CTRL_CLK5_EXT_DIVIDER_SHIFT)) & GTM_gtm_cls0_CMU_CLK_CTRL_CLK5_EXT_DIVIDER_MASK) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK6_EXT_DIVIDER_MASK (0x40U) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK6_EXT_DIVIDER_SHIFT (6U) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK6_EXT_DIVIDER_WIDTH (1U) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK6_EXT_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_CLK_CTRL_CLK6_EXT_DIVIDER_SHIFT)) & GTM_gtm_cls0_CMU_CLK_CTRL_CLK6_EXT_DIVIDER_MASK) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK7_EXT_DIVIDER_MASK (0x80U) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK7_EXT_DIVIDER_SHIFT (7U) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK7_EXT_DIVIDER_WIDTH (1U) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK7_EXT_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_CLK_CTRL_CLK7_EXT_DIVIDER_SHIFT)) & GTM_gtm_cls0_CMU_CLK_CTRL_CLK7_EXT_DIVIDER_MASK) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK8_EXT_DIVIDER_MASK (0x100U) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK8_EXT_DIVIDER_SHIFT (8U) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK8_EXT_DIVIDER_WIDTH (1U) #define GTM_gtm_cls0_CMU_CLK_CTRL_CLK8_EXT_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CMU_CLK_CTRL_CLK8_EXT_DIVIDER_SHIFT)) & GTM_gtm_cls0_CMU_CLK_CTRL_CLK8_EXT_DIVIDER_MASK) /*! @} */ /*! @name TBU_CHEN - TBU global channel enable */ /*! @{ */ #define GTM_gtm_cls0_TBU_CHEN_ENDIS_CH0_MASK (0x3U) #define GTM_gtm_cls0_TBU_CHEN_ENDIS_CH0_SHIFT (0U) #define GTM_gtm_cls0_TBU_CHEN_ENDIS_CH0_WIDTH (2U) #define GTM_gtm_cls0_TBU_CHEN_ENDIS_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TBU_CHEN_ENDIS_CH0_SHIFT)) & GTM_gtm_cls0_TBU_CHEN_ENDIS_CH0_MASK) #define GTM_gtm_cls0_TBU_CHEN_ENDIS_CH1_MASK (0xCU) #define GTM_gtm_cls0_TBU_CHEN_ENDIS_CH1_SHIFT (2U) #define GTM_gtm_cls0_TBU_CHEN_ENDIS_CH1_WIDTH (2U) #define GTM_gtm_cls0_TBU_CHEN_ENDIS_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TBU_CHEN_ENDIS_CH1_SHIFT)) & GTM_gtm_cls0_TBU_CHEN_ENDIS_CH1_MASK) #define GTM_gtm_cls0_TBU_CHEN_ENDIS_CH2_MASK (0x30U) #define GTM_gtm_cls0_TBU_CHEN_ENDIS_CH2_SHIFT (4U) #define GTM_gtm_cls0_TBU_CHEN_ENDIS_CH2_WIDTH (2U) #define GTM_gtm_cls0_TBU_CHEN_ENDIS_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TBU_CHEN_ENDIS_CH2_SHIFT)) & GTM_gtm_cls0_TBU_CHEN_ENDIS_CH2_MASK) #define GTM_gtm_cls0_TBU_CHEN_ENDIS_CH3_MASK (0xC0U) #define GTM_gtm_cls0_TBU_CHEN_ENDIS_CH3_SHIFT (6U) #define GTM_gtm_cls0_TBU_CHEN_ENDIS_CH3_WIDTH (2U) #define GTM_gtm_cls0_TBU_CHEN_ENDIS_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TBU_CHEN_ENDIS_CH3_SHIFT)) & GTM_gtm_cls0_TBU_CHEN_ENDIS_CH3_MASK) /*! @} */ /*! @name TBU_CH0_CTRL - TBU channel 0 control */ /*! @{ */ #define GTM_gtm_cls0_TBU_CH0_CTRL_LOW_RES_MASK (0x1U) #define GTM_gtm_cls0_TBU_CH0_CTRL_LOW_RES_SHIFT (0U) #define GTM_gtm_cls0_TBU_CH0_CTRL_LOW_RES_WIDTH (1U) #define GTM_gtm_cls0_TBU_CH0_CTRL_LOW_RES(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TBU_CH0_CTRL_LOW_RES_SHIFT)) & GTM_gtm_cls0_TBU_CH0_CTRL_LOW_RES_MASK) #define GTM_gtm_cls0_TBU_CH0_CTRL_CH_CLK_SRC_MASK (0xEU) #define GTM_gtm_cls0_TBU_CH0_CTRL_CH_CLK_SRC_SHIFT (1U) #define GTM_gtm_cls0_TBU_CH0_CTRL_CH_CLK_SRC_WIDTH (3U) #define GTM_gtm_cls0_TBU_CH0_CTRL_CH_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TBU_CH0_CTRL_CH_CLK_SRC_SHIFT)) & GTM_gtm_cls0_TBU_CH0_CTRL_CH_CLK_SRC_MASK) /*! @} */ /*! @name TBU_CH0_BASE - TBU channel 0 base */ /*! @{ */ #define GTM_gtm_cls0_TBU_CH0_BASE_BASE_MASK (0x7FFFFFFU) #define GTM_gtm_cls0_TBU_CH0_BASE_BASE_SHIFT (0U) #define GTM_gtm_cls0_TBU_CH0_BASE_BASE_WIDTH (27U) #define GTM_gtm_cls0_TBU_CH0_BASE_BASE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TBU_CH0_BASE_BASE_SHIFT)) & GTM_gtm_cls0_TBU_CH0_BASE_BASE_MASK) /*! @} */ /*! @name TBU_CH1_CTRL - TBU channel 1 control */ /*! @{ */ #define GTM_gtm_cls0_TBU_CH1_CTRL_CH_MODE_MASK (0x1U) #define GTM_gtm_cls0_TBU_CH1_CTRL_CH_MODE_SHIFT (0U) #define GTM_gtm_cls0_TBU_CH1_CTRL_CH_MODE_WIDTH (1U) #define GTM_gtm_cls0_TBU_CH1_CTRL_CH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TBU_CH1_CTRL_CH_MODE_SHIFT)) & GTM_gtm_cls0_TBU_CH1_CTRL_CH_MODE_MASK) #define GTM_gtm_cls0_TBU_CH1_CTRL_CH_CLK_SRC_MASK (0xEU) #define GTM_gtm_cls0_TBU_CH1_CTRL_CH_CLK_SRC_SHIFT (1U) #define GTM_gtm_cls0_TBU_CH1_CTRL_CH_CLK_SRC_WIDTH (3U) #define GTM_gtm_cls0_TBU_CH1_CTRL_CH_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TBU_CH1_CTRL_CH_CLK_SRC_SHIFT)) & GTM_gtm_cls0_TBU_CH1_CTRL_CH_CLK_SRC_MASK) /*! @} */ /*! @name TBU_CH1_BASE - TBU channel [x] base */ /*! @{ */ #define GTM_gtm_cls0_TBU_CH1_BASE_BASE_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TBU_CH1_BASE_BASE_SHIFT (0U) #define GTM_gtm_cls0_TBU_CH1_BASE_BASE_WIDTH (24U) #define GTM_gtm_cls0_TBU_CH1_BASE_BASE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TBU_CH1_BASE_BASE_SHIFT)) & GTM_gtm_cls0_TBU_CH1_BASE_BASE_MASK) /*! @} */ /*! @name TBU_CH2_CTRL - TBU channel 2 control */ /*! @{ */ #define GTM_gtm_cls0_TBU_CH2_CTRL_CH_MODE_MASK (0x1U) #define GTM_gtm_cls0_TBU_CH2_CTRL_CH_MODE_SHIFT (0U) #define GTM_gtm_cls0_TBU_CH2_CTRL_CH_MODE_WIDTH (1U) #define GTM_gtm_cls0_TBU_CH2_CTRL_CH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TBU_CH2_CTRL_CH_MODE_SHIFT)) & GTM_gtm_cls0_TBU_CH2_CTRL_CH_MODE_MASK) #define GTM_gtm_cls0_TBU_CH2_CTRL_CH_CLK_SRC_MASK (0xEU) #define GTM_gtm_cls0_TBU_CH2_CTRL_CH_CLK_SRC_SHIFT (1U) #define GTM_gtm_cls0_TBU_CH2_CTRL_CH_CLK_SRC_WIDTH (3U) #define GTM_gtm_cls0_TBU_CH2_CTRL_CH_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TBU_CH2_CTRL_CH_CLK_SRC_SHIFT)) & GTM_gtm_cls0_TBU_CH2_CTRL_CH_CLK_SRC_MASK) /*! @} */ /*! @name TBU_CH2_BASE - TBU channel [x] base */ /*! @{ */ #define GTM_gtm_cls0_TBU_CH2_BASE_BASE_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TBU_CH2_BASE_BASE_SHIFT (0U) #define GTM_gtm_cls0_TBU_CH2_BASE_BASE_WIDTH (24U) #define GTM_gtm_cls0_TBU_CH2_BASE_BASE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TBU_CH2_BASE_BASE_SHIFT)) & GTM_gtm_cls0_TBU_CH2_BASE_BASE_MASK) /*! @} */ /*! @name TBU_CH3_CTRL - TBU channel 3 control */ /*! @{ */ #define GTM_gtm_cls0_TBU_CH3_CTRL_CH_MODE_MASK (0x1U) #define GTM_gtm_cls0_TBU_CH3_CTRL_CH_MODE_SHIFT (0U) #define GTM_gtm_cls0_TBU_CH3_CTRL_CH_MODE_WIDTH (1U) #define GTM_gtm_cls0_TBU_CH3_CTRL_CH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TBU_CH3_CTRL_CH_MODE_SHIFT)) & GTM_gtm_cls0_TBU_CH3_CTRL_CH_MODE_MASK) #define GTM_gtm_cls0_TBU_CH3_CTRL_USE_CH2_MASK (0x10U) #define GTM_gtm_cls0_TBU_CH3_CTRL_USE_CH2_SHIFT (4U) #define GTM_gtm_cls0_TBU_CH3_CTRL_USE_CH2_WIDTH (1U) #define GTM_gtm_cls0_TBU_CH3_CTRL_USE_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TBU_CH3_CTRL_USE_CH2_SHIFT)) & GTM_gtm_cls0_TBU_CH3_CTRL_USE_CH2_MASK) /*! @} */ /*! @name TBU_CH3_BASE - TBU channel 3 base */ /*! @{ */ #define GTM_gtm_cls0_TBU_CH3_BASE_BASE_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TBU_CH3_BASE_BASE_SHIFT (0U) #define GTM_gtm_cls0_TBU_CH3_BASE_BASE_WIDTH (24U) #define GTM_gtm_cls0_TBU_CH3_BASE_BASE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TBU_CH3_BASE_BASE_SHIFT)) & GTM_gtm_cls0_TBU_CH3_BASE_BASE_MASK) /*! @} */ /*! @name TBU_CH3_BASE_MARK - TBU channel 3 modulo value */ /*! @{ */ #define GTM_gtm_cls0_TBU_CH3_BASE_MARK_BASE_MARK_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TBU_CH3_BASE_MARK_BASE_MARK_SHIFT (0U) #define GTM_gtm_cls0_TBU_CH3_BASE_MARK_BASE_MARK_WIDTH (24U) #define GTM_gtm_cls0_TBU_CH3_BASE_MARK_BASE_MARK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TBU_CH3_BASE_MARK_BASE_MARK_SHIFT)) & GTM_gtm_cls0_TBU_CH3_BASE_MARK_BASE_MARK_MASK) /*! @} */ /*! @name TBU_CH3_BASE_CAPTURE - TBU channel 3 base captured */ /*! @{ */ #define GTM_gtm_cls0_TBU_CH3_BASE_CAPTURE_BASE_CAPTURE_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TBU_CH3_BASE_CAPTURE_BASE_CAPTURE_SHIFT (0U) #define GTM_gtm_cls0_TBU_CH3_BASE_CAPTURE_BASE_CAPTURE_WIDTH (24U) #define GTM_gtm_cls0_TBU_CH3_BASE_CAPTURE_BASE_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TBU_CH3_BASE_CAPTURE_BASE_CAPTURE_SHIFT)) & GTM_gtm_cls0_TBU_CH3_BASE_CAPTURE_BASE_CAPTURE_MASK) /*! @} */ /*! @name ARU_ACCESS - ARU access register */ /*! @{ */ #define GTM_gtm_cls0_ARU_ACCESS_ADDR_MASK (0x1FFU) #define GTM_gtm_cls0_ARU_ACCESS_ADDR_SHIFT (0U) #define GTM_gtm_cls0_ARU_ACCESS_ADDR_WIDTH (9U) #define GTM_gtm_cls0_ARU_ACCESS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_ACCESS_ADDR_SHIFT)) & GTM_gtm_cls0_ARU_ACCESS_ADDR_MASK) #define GTM_gtm_cls0_ARU_ACCESS_RREQ_MASK (0x1000U) #define GTM_gtm_cls0_ARU_ACCESS_RREQ_SHIFT (12U) #define GTM_gtm_cls0_ARU_ACCESS_RREQ_WIDTH (1U) #define GTM_gtm_cls0_ARU_ACCESS_RREQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_ACCESS_RREQ_SHIFT)) & GTM_gtm_cls0_ARU_ACCESS_RREQ_MASK) #define GTM_gtm_cls0_ARU_ACCESS_WREQ_MASK (0x2000U) #define GTM_gtm_cls0_ARU_ACCESS_WREQ_SHIFT (13U) #define GTM_gtm_cls0_ARU_ACCESS_WREQ_WIDTH (1U) #define GTM_gtm_cls0_ARU_ACCESS_WREQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_ACCESS_WREQ_SHIFT)) & GTM_gtm_cls0_ARU_ACCESS_WREQ_MASK) /*! @} */ /*! @name ARU_DATA_H - ARU access register upper data word */ /*! @{ */ #define GTM_gtm_cls0_ARU_DATA_H_DATA_MASK (0x1FFFFFFFU) #define GTM_gtm_cls0_ARU_DATA_H_DATA_SHIFT (0U) #define GTM_gtm_cls0_ARU_DATA_H_DATA_WIDTH (29U) #define GTM_gtm_cls0_ARU_DATA_H_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_DATA_H_DATA_SHIFT)) & GTM_gtm_cls0_ARU_DATA_H_DATA_MASK) /*! @} */ /*! @name ARU_DATA_L - ARU access register lower data word */ /*! @{ */ #define GTM_gtm_cls0_ARU_DATA_L_DATA_MASK (0x1FFFFFFFU) #define GTM_gtm_cls0_ARU_DATA_L_DATA_SHIFT (0U) #define GTM_gtm_cls0_ARU_DATA_L_DATA_WIDTH (29U) #define GTM_gtm_cls0_ARU_DATA_L_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_DATA_L_DATA_SHIFT)) & GTM_gtm_cls0_ARU_DATA_L_DATA_MASK) /*! @} */ /*! @name ARU_DBG_ACCESS0 - ARU debug access channel 0 */ /*! @{ */ #define GTM_gtm_cls0_ARU_DBG_ACCESS0_ADDR_MASK (0x1FFU) #define GTM_gtm_cls0_ARU_DBG_ACCESS0_ADDR_SHIFT (0U) #define GTM_gtm_cls0_ARU_DBG_ACCESS0_ADDR_WIDTH (9U) #define GTM_gtm_cls0_ARU_DBG_ACCESS0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_DBG_ACCESS0_ADDR_SHIFT)) & GTM_gtm_cls0_ARU_DBG_ACCESS0_ADDR_MASK) /*! @} */ /*! @name ARU_DBG_DATA0_H - ARU debug access 0 transfer register upper data word */ /*! @{ */ #define GTM_gtm_cls0_ARU_DBG_DATA0_H_DATA_MASK (0x1FFFFFFFU) #define GTM_gtm_cls0_ARU_DBG_DATA0_H_DATA_SHIFT (0U) #define GTM_gtm_cls0_ARU_DBG_DATA0_H_DATA_WIDTH (29U) #define GTM_gtm_cls0_ARU_DBG_DATA0_H_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_DBG_DATA0_H_DATA_SHIFT)) & GTM_gtm_cls0_ARU_DBG_DATA0_H_DATA_MASK) /*! @} */ /*! @name ARU_DBG_DATA0_L - ARU debug access 0 transfer register lower data word */ /*! @{ */ #define GTM_gtm_cls0_ARU_DBG_DATA0_L_DATA_MASK (0x1FFFFFFFU) #define GTM_gtm_cls0_ARU_DBG_DATA0_L_DATA_SHIFT (0U) #define GTM_gtm_cls0_ARU_DBG_DATA0_L_DATA_WIDTH (29U) #define GTM_gtm_cls0_ARU_DBG_DATA0_L_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_DBG_DATA0_L_DATA_SHIFT)) & GTM_gtm_cls0_ARU_DBG_DATA0_L_DATA_MASK) /*! @} */ /*! @name ARU_DBG_ACCESS1 - ARU debug access channel 0 */ /*! @{ */ #define GTM_gtm_cls0_ARU_DBG_ACCESS1_ADDR_MASK (0x1FFU) #define GTM_gtm_cls0_ARU_DBG_ACCESS1_ADDR_SHIFT (0U) #define GTM_gtm_cls0_ARU_DBG_ACCESS1_ADDR_WIDTH (9U) #define GTM_gtm_cls0_ARU_DBG_ACCESS1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_DBG_ACCESS1_ADDR_SHIFT)) & GTM_gtm_cls0_ARU_DBG_ACCESS1_ADDR_MASK) /*! @} */ /*! @name ARU_DBG_DATA1_H - ARU debug access 1 transfer register upper data word */ /*! @{ */ #define GTM_gtm_cls0_ARU_DBG_DATA1_H_DATA_MASK (0x1FFFFFFFU) #define GTM_gtm_cls0_ARU_DBG_DATA1_H_DATA_SHIFT (0U) #define GTM_gtm_cls0_ARU_DBG_DATA1_H_DATA_WIDTH (29U) #define GTM_gtm_cls0_ARU_DBG_DATA1_H_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_DBG_DATA1_H_DATA_SHIFT)) & GTM_gtm_cls0_ARU_DBG_DATA1_H_DATA_MASK) /*! @} */ /*! @name ARU_DBG_DATA1_L - ARU debug access 1 transfer register lower data word */ /*! @{ */ #define GTM_gtm_cls0_ARU_DBG_DATA1_L_DATA_MASK (0x1FFFFFFFU) #define GTM_gtm_cls0_ARU_DBG_DATA1_L_DATA_SHIFT (0U) #define GTM_gtm_cls0_ARU_DBG_DATA1_L_DATA_WIDTH (29U) #define GTM_gtm_cls0_ARU_DBG_DATA1_L_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_DBG_DATA1_L_DATA_SHIFT)) & GTM_gtm_cls0_ARU_DBG_DATA1_L_DATA_MASK) /*! @} */ /*! @name ARU_IRQ_NOTIFY - ARU interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_ARU_IRQ_NOTIFY_NEW_DATA0_MASK (0x1U) #define GTM_gtm_cls0_ARU_IRQ_NOTIFY_NEW_DATA0_SHIFT (0U) #define GTM_gtm_cls0_ARU_IRQ_NOTIFY_NEW_DATA0_WIDTH (1U) #define GTM_gtm_cls0_ARU_IRQ_NOTIFY_NEW_DATA0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_IRQ_NOTIFY_NEW_DATA0_SHIFT)) & GTM_gtm_cls0_ARU_IRQ_NOTIFY_NEW_DATA0_MASK) #define GTM_gtm_cls0_ARU_IRQ_NOTIFY_NEW_DATA1_MASK (0x2U) #define GTM_gtm_cls0_ARU_IRQ_NOTIFY_NEW_DATA1_SHIFT (1U) #define GTM_gtm_cls0_ARU_IRQ_NOTIFY_NEW_DATA1_WIDTH (1U) #define GTM_gtm_cls0_ARU_IRQ_NOTIFY_NEW_DATA1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_IRQ_NOTIFY_NEW_DATA1_SHIFT)) & GTM_gtm_cls0_ARU_IRQ_NOTIFY_NEW_DATA1_MASK) #define GTM_gtm_cls0_ARU_IRQ_NOTIFY_ACC_ACK_MASK (0x4U) #define GTM_gtm_cls0_ARU_IRQ_NOTIFY_ACC_ACK_SHIFT (2U) #define GTM_gtm_cls0_ARU_IRQ_NOTIFY_ACC_ACK_WIDTH (1U) #define GTM_gtm_cls0_ARU_IRQ_NOTIFY_ACC_ACK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_IRQ_NOTIFY_ACC_ACK_SHIFT)) & GTM_gtm_cls0_ARU_IRQ_NOTIFY_ACC_ACK_MASK) /*! @} */ /*! @name ARU_IRQ_EN - ARU interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_ARU_IRQ_EN_NEW_DATA0_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_ARU_IRQ_EN_NEW_DATA0_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_ARU_IRQ_EN_NEW_DATA0_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_ARU_IRQ_EN_NEW_DATA0_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_IRQ_EN_NEW_DATA0_IRQ_EN_SHIFT)) & GTM_gtm_cls0_ARU_IRQ_EN_NEW_DATA0_IRQ_EN_MASK) #define GTM_gtm_cls0_ARU_IRQ_EN_NEW_DATA1_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_ARU_IRQ_EN_NEW_DATA1_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_ARU_IRQ_EN_NEW_DATA1_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_ARU_IRQ_EN_NEW_DATA1_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_IRQ_EN_NEW_DATA1_IRQ_EN_SHIFT)) & GTM_gtm_cls0_ARU_IRQ_EN_NEW_DATA1_IRQ_EN_MASK) #define GTM_gtm_cls0_ARU_IRQ_EN_ACC_ACK_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_ARU_IRQ_EN_ACC_ACK_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_ARU_IRQ_EN_ACC_ACK_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_ARU_IRQ_EN_ACC_ACK_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_IRQ_EN_ACC_ACK_IRQ_EN_SHIFT)) & GTM_gtm_cls0_ARU_IRQ_EN_ACC_ACK_IRQ_EN_MASK) /*! @} */ /*! @name ARU_IRQ_FORCINT - ARU force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_ARU_IRQ_FORCINT_TRG_NEW_DATA0_MASK (0x1U) #define GTM_gtm_cls0_ARU_IRQ_FORCINT_TRG_NEW_DATA0_SHIFT (0U) #define GTM_gtm_cls0_ARU_IRQ_FORCINT_TRG_NEW_DATA0_WIDTH (1U) #define GTM_gtm_cls0_ARU_IRQ_FORCINT_TRG_NEW_DATA0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_IRQ_FORCINT_TRG_NEW_DATA0_SHIFT)) & GTM_gtm_cls0_ARU_IRQ_FORCINT_TRG_NEW_DATA0_MASK) #define GTM_gtm_cls0_ARU_IRQ_FORCINT_TRG_NEW_DATA1_MASK (0x2U) #define GTM_gtm_cls0_ARU_IRQ_FORCINT_TRG_NEW_DATA1_SHIFT (1U) #define GTM_gtm_cls0_ARU_IRQ_FORCINT_TRG_NEW_DATA1_WIDTH (1U) #define GTM_gtm_cls0_ARU_IRQ_FORCINT_TRG_NEW_DATA1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_IRQ_FORCINT_TRG_NEW_DATA1_SHIFT)) & GTM_gtm_cls0_ARU_IRQ_FORCINT_TRG_NEW_DATA1_MASK) #define GTM_gtm_cls0_ARU_IRQ_FORCINT_TRG_ACC_ACK_MASK (0x4U) #define GTM_gtm_cls0_ARU_IRQ_FORCINT_TRG_ACC_ACK_SHIFT (2U) #define GTM_gtm_cls0_ARU_IRQ_FORCINT_TRG_ACC_ACK_WIDTH (1U) #define GTM_gtm_cls0_ARU_IRQ_FORCINT_TRG_ACC_ACK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_IRQ_FORCINT_TRG_ACC_ACK_SHIFT)) & GTM_gtm_cls0_ARU_IRQ_FORCINT_TRG_ACC_ACK_MASK) /*! @} */ /*! @name ARU_IRQ_MODE - ARU interrupt mode register */ /*! @{ */ #define GTM_gtm_cls0_ARU_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_ARU_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_ARU_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_ARU_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_ARU_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name ARU_CADDR_END - ARU caddr counter end value */ /*! @{ */ #define GTM_gtm_cls0_ARU_CADDR_END_CADDR_END_MASK (0x7FU) #define GTM_gtm_cls0_ARU_CADDR_END_CADDR_END_SHIFT (0U) #define GTM_gtm_cls0_ARU_CADDR_END_CADDR_END_WIDTH (7U) #define GTM_gtm_cls0_ARU_CADDR_END_CADDR_END(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_CADDR_END_CADDR_END_SHIFT)) & GTM_gtm_cls0_ARU_CADDR_END_CADDR_END_MASK) /*! @} */ /*! @name ARU_CTRL - ARU enable dynamic routing */ /*! @{ */ #define GTM_gtm_cls0_ARU_CTRL_ARU_0_DYN_EN_MASK (0x3U) #define GTM_gtm_cls0_ARU_CTRL_ARU_0_DYN_EN_SHIFT (0U) #define GTM_gtm_cls0_ARU_CTRL_ARU_0_DYN_EN_WIDTH (2U) #define GTM_gtm_cls0_ARU_CTRL_ARU_0_DYN_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_CTRL_ARU_0_DYN_EN_SHIFT)) & GTM_gtm_cls0_ARU_CTRL_ARU_0_DYN_EN_MASK) #define GTM_gtm_cls0_ARU_CTRL_ARU_1_DYN_EN_MASK (0xCU) #define GTM_gtm_cls0_ARU_CTRL_ARU_1_DYN_EN_SHIFT (2U) #define GTM_gtm_cls0_ARU_CTRL_ARU_1_DYN_EN_WIDTH (2U) #define GTM_gtm_cls0_ARU_CTRL_ARU_1_DYN_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_CTRL_ARU_1_DYN_EN_SHIFT)) & GTM_gtm_cls0_ARU_CTRL_ARU_1_DYN_EN_MASK) #define GTM_gtm_cls0_ARU_CTRL_ARU_DYN_RING_MODE_MASK (0x10U) #define GTM_gtm_cls0_ARU_CTRL_ARU_DYN_RING_MODE_SHIFT (4U) #define GTM_gtm_cls0_ARU_CTRL_ARU_DYN_RING_MODE_WIDTH (1U) #define GTM_gtm_cls0_ARU_CTRL_ARU_DYN_RING_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_CTRL_ARU_DYN_RING_MODE_SHIFT)) & GTM_gtm_cls0_ARU_CTRL_ARU_DYN_RING_MODE_MASK) /*! @} */ /*! @name ARU_0_DYN_CTRL - ARU [g] dynamic routing control register */ /*! @{ */ #define GTM_gtm_cls0_ARU_0_DYN_CTRL_DYN_ARU_UPDATE_EN_MASK (0x1U) #define GTM_gtm_cls0_ARU_0_DYN_CTRL_DYN_ARU_UPDATE_EN_SHIFT (0U) #define GTM_gtm_cls0_ARU_0_DYN_CTRL_DYN_ARU_UPDATE_EN_WIDTH (1U) #define GTM_gtm_cls0_ARU_0_DYN_CTRL_DYN_ARU_UPDATE_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_0_DYN_CTRL_DYN_ARU_UPDATE_EN_SHIFT)) & GTM_gtm_cls0_ARU_0_DYN_CTRL_DYN_ARU_UPDATE_EN_MASK) #define GTM_gtm_cls0_ARU_0_DYN_CTRL_DYN_ROUTE_SWAP_MASK (0x2U) #define GTM_gtm_cls0_ARU_0_DYN_CTRL_DYN_ROUTE_SWAP_SHIFT (1U) #define GTM_gtm_cls0_ARU_0_DYN_CTRL_DYN_ROUTE_SWAP_WIDTH (1U) #define GTM_gtm_cls0_ARU_0_DYN_CTRL_DYN_ROUTE_SWAP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_0_DYN_CTRL_DYN_ROUTE_SWAP_SHIFT)) & GTM_gtm_cls0_ARU_0_DYN_CTRL_DYN_ROUTE_SWAP_MASK) /*! @} */ /*! @name ARU_1_DYN_CTRL - ARU [g] dynamic routing control register */ /*! @{ */ #define GTM_gtm_cls0_ARU_1_DYN_CTRL_DYN_ARU_UPDATE_EN_MASK (0x1U) #define GTM_gtm_cls0_ARU_1_DYN_CTRL_DYN_ARU_UPDATE_EN_SHIFT (0U) #define GTM_gtm_cls0_ARU_1_DYN_CTRL_DYN_ARU_UPDATE_EN_WIDTH (1U) #define GTM_gtm_cls0_ARU_1_DYN_CTRL_DYN_ARU_UPDATE_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_1_DYN_CTRL_DYN_ARU_UPDATE_EN_SHIFT)) & GTM_gtm_cls0_ARU_1_DYN_CTRL_DYN_ARU_UPDATE_EN_MASK) #define GTM_gtm_cls0_ARU_1_DYN_CTRL_DYN_ROUTE_SWAP_MASK (0x2U) #define GTM_gtm_cls0_ARU_1_DYN_CTRL_DYN_ROUTE_SWAP_SHIFT (1U) #define GTM_gtm_cls0_ARU_1_DYN_CTRL_DYN_ROUTE_SWAP_WIDTH (1U) #define GTM_gtm_cls0_ARU_1_DYN_CTRL_DYN_ROUTE_SWAP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_1_DYN_CTRL_DYN_ROUTE_SWAP_SHIFT)) & GTM_gtm_cls0_ARU_1_DYN_CTRL_DYN_ROUTE_SWAP_MASK) /*! @} */ /*! @name ARU_0_DYN_ROUTE_LOW - ARU [g] lower bits of DYN_ROUTE register */ /*! @{ */ #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_LOW_DYN_READ_ID0_MASK (0xFFU) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_LOW_DYN_READ_ID0_SHIFT (0U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_LOW_DYN_READ_ID0_WIDTH (8U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_LOW_DYN_READ_ID0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_0_DYN_ROUTE_LOW_DYN_READ_ID0_SHIFT)) & GTM_gtm_cls0_ARU_0_DYN_ROUTE_LOW_DYN_READ_ID0_MASK) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_LOW_DYN_READ_ID1_MASK (0xFF00U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_LOW_DYN_READ_ID1_SHIFT (8U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_LOW_DYN_READ_ID1_WIDTH (8U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_LOW_DYN_READ_ID1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_0_DYN_ROUTE_LOW_DYN_READ_ID1_SHIFT)) & GTM_gtm_cls0_ARU_0_DYN_ROUTE_LOW_DYN_READ_ID1_MASK) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_LOW_DYN_READ_ID2_MASK (0xFF0000U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_LOW_DYN_READ_ID2_SHIFT (16U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_LOW_DYN_READ_ID2_WIDTH (8U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_LOW_DYN_READ_ID2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_0_DYN_ROUTE_LOW_DYN_READ_ID2_SHIFT)) & GTM_gtm_cls0_ARU_0_DYN_ROUTE_LOW_DYN_READ_ID2_MASK) /*! @} */ /*! @name ARU_1_DYN_ROUTE_LOW - ARU [g] lower bits of DYN_ROUTE register */ /*! @{ */ #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_LOW_DYN_READ_ID0_MASK (0xFFU) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_LOW_DYN_READ_ID0_SHIFT (0U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_LOW_DYN_READ_ID0_WIDTH (8U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_LOW_DYN_READ_ID0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_1_DYN_ROUTE_LOW_DYN_READ_ID0_SHIFT)) & GTM_gtm_cls0_ARU_1_DYN_ROUTE_LOW_DYN_READ_ID0_MASK) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_LOW_DYN_READ_ID1_MASK (0xFF00U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_LOW_DYN_READ_ID1_SHIFT (8U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_LOW_DYN_READ_ID1_WIDTH (8U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_LOW_DYN_READ_ID1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_1_DYN_ROUTE_LOW_DYN_READ_ID1_SHIFT)) & GTM_gtm_cls0_ARU_1_DYN_ROUTE_LOW_DYN_READ_ID1_MASK) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_LOW_DYN_READ_ID2_MASK (0xFF0000U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_LOW_DYN_READ_ID2_SHIFT (16U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_LOW_DYN_READ_ID2_WIDTH (8U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_LOW_DYN_READ_ID2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_1_DYN_ROUTE_LOW_DYN_READ_ID2_SHIFT)) & GTM_gtm_cls0_ARU_1_DYN_ROUTE_LOW_DYN_READ_ID2_MASK) /*! @} */ /*! @name ARU_0_DYN_ROUTE_HIGH - ARU [g] higher bits of DYN_ROUTE register */ /*! @{ */ #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_HIGH_DYN_READ_ID3_MASK (0xFFU) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_HIGH_DYN_READ_ID3_SHIFT (0U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_HIGH_DYN_READ_ID3_WIDTH (8U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_HIGH_DYN_READ_ID3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_0_DYN_ROUTE_HIGH_DYN_READ_ID3_SHIFT)) & GTM_gtm_cls0_ARU_0_DYN_ROUTE_HIGH_DYN_READ_ID3_MASK) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_HIGH_DYN_READ_ID4_MASK (0xFF00U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_HIGH_DYN_READ_ID4_SHIFT (8U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_HIGH_DYN_READ_ID4_WIDTH (8U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_HIGH_DYN_READ_ID4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_0_DYN_ROUTE_HIGH_DYN_READ_ID4_SHIFT)) & GTM_gtm_cls0_ARU_0_DYN_ROUTE_HIGH_DYN_READ_ID4_MASK) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_HIGH_DYN_READ_ID5_MASK (0xFF0000U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_HIGH_DYN_READ_ID5_SHIFT (16U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_HIGH_DYN_READ_ID5_WIDTH (8U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_HIGH_DYN_READ_ID5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_0_DYN_ROUTE_HIGH_DYN_READ_ID5_SHIFT)) & GTM_gtm_cls0_ARU_0_DYN_ROUTE_HIGH_DYN_READ_ID5_MASK) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_HIGH_DYN_CLK_WAIT_MASK (0xF000000U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_HIGH_DYN_CLK_WAIT_SHIFT (24U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_HIGH_DYN_CLK_WAIT_WIDTH (4U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_HIGH_DYN_CLK_WAIT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_0_DYN_ROUTE_HIGH_DYN_CLK_WAIT_SHIFT)) & GTM_gtm_cls0_ARU_0_DYN_ROUTE_HIGH_DYN_CLK_WAIT_MASK) /*! @} */ /*! @name ARU_1_DYN_ROUTE_HIGH - ARU [g] higher bits of DYN_ROUTE register */ /*! @{ */ #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_HIGH_DYN_READ_ID3_MASK (0xFFU) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_HIGH_DYN_READ_ID3_SHIFT (0U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_HIGH_DYN_READ_ID3_WIDTH (8U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_HIGH_DYN_READ_ID3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_1_DYN_ROUTE_HIGH_DYN_READ_ID3_SHIFT)) & GTM_gtm_cls0_ARU_1_DYN_ROUTE_HIGH_DYN_READ_ID3_MASK) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_HIGH_DYN_READ_ID4_MASK (0xFF00U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_HIGH_DYN_READ_ID4_SHIFT (8U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_HIGH_DYN_READ_ID4_WIDTH (8U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_HIGH_DYN_READ_ID4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_1_DYN_ROUTE_HIGH_DYN_READ_ID4_SHIFT)) & GTM_gtm_cls0_ARU_1_DYN_ROUTE_HIGH_DYN_READ_ID4_MASK) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_HIGH_DYN_READ_ID5_MASK (0xFF0000U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_HIGH_DYN_READ_ID5_SHIFT (16U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_HIGH_DYN_READ_ID5_WIDTH (8U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_HIGH_DYN_READ_ID5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_1_DYN_ROUTE_HIGH_DYN_READ_ID5_SHIFT)) & GTM_gtm_cls0_ARU_1_DYN_ROUTE_HIGH_DYN_READ_ID5_MASK) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_HIGH_DYN_CLK_WAIT_MASK (0xF000000U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_HIGH_DYN_CLK_WAIT_SHIFT (24U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_HIGH_DYN_CLK_WAIT_WIDTH (4U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_HIGH_DYN_CLK_WAIT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_1_DYN_ROUTE_HIGH_DYN_CLK_WAIT_SHIFT)) & GTM_gtm_cls0_ARU_1_DYN_ROUTE_HIGH_DYN_CLK_WAIT_MASK) /*! @} */ /*! @name ARU_0_DYN_ROUTE_SR_LOW - ARU [g] shadow register of DYN_ROUTE register lower bits */ /*! @{ */ #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_LOW_DYN_READ_ID6_MASK (0xFFU) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_LOW_DYN_READ_ID6_SHIFT (0U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_LOW_DYN_READ_ID6_WIDTH (8U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_LOW_DYN_READ_ID6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_LOW_DYN_READ_ID6_SHIFT)) & GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_LOW_DYN_READ_ID6_MASK) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_LOW_DYN_READ_ID7_MASK (0xFF00U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_LOW_DYN_READ_ID7_SHIFT (8U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_LOW_DYN_READ_ID7_WIDTH (8U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_LOW_DYN_READ_ID7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_LOW_DYN_READ_ID7_SHIFT)) & GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_LOW_DYN_READ_ID7_MASK) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_LOW_DYN_READ_ID8_MASK (0xFF0000U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_LOW_DYN_READ_ID8_SHIFT (16U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_LOW_DYN_READ_ID8_WIDTH (8U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_LOW_DYN_READ_ID8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_LOW_DYN_READ_ID8_SHIFT)) & GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_LOW_DYN_READ_ID8_MASK) /*! @} */ /*! @name ARU_1_DYN_ROUTE_SR_LOW - ARU [g] shadow register of DYN_ROUTE register lower bits */ /*! @{ */ #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_LOW_DYN_READ_ID6_MASK (0xFFU) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_LOW_DYN_READ_ID6_SHIFT (0U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_LOW_DYN_READ_ID6_WIDTH (8U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_LOW_DYN_READ_ID6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_LOW_DYN_READ_ID6_SHIFT)) & GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_LOW_DYN_READ_ID6_MASK) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_LOW_DYN_READ_ID7_MASK (0xFF00U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_LOW_DYN_READ_ID7_SHIFT (8U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_LOW_DYN_READ_ID7_WIDTH (8U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_LOW_DYN_READ_ID7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_LOW_DYN_READ_ID7_SHIFT)) & GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_LOW_DYN_READ_ID7_MASK) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_LOW_DYN_READ_ID8_MASK (0xFF0000U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_LOW_DYN_READ_ID8_SHIFT (16U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_LOW_DYN_READ_ID8_WIDTH (8U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_LOW_DYN_READ_ID8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_LOW_DYN_READ_ID8_SHIFT)) & GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_LOW_DYN_READ_ID8_MASK) /*! @} */ /*! @name ARU_0_DYN_ROUTE_SR_HIGH - ARU [g] shadow register of DYN_ROUTE register higher bits */ /*! @{ */ #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_HIGH_DYN_READ_ID9_MASK (0xFFU) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_HIGH_DYN_READ_ID9_SHIFT (0U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_HIGH_DYN_READ_ID9_WIDTH (8U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_HIGH_DYN_READ_ID9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_HIGH_DYN_READ_ID9_SHIFT)) & GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_HIGH_DYN_READ_ID9_MASK) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_HIGH_DYN_READ_ID10_MASK (0xFF00U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_HIGH_DYN_READ_ID10_SHIFT (8U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_HIGH_DYN_READ_ID10_WIDTH (8U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_HIGH_DYN_READ_ID10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_HIGH_DYN_READ_ID10_SHIFT)) & GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_HIGH_DYN_READ_ID10_MASK) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_HIGH_DYN_READ_ID11_MASK (0xFF0000U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_HIGH_DYN_READ_ID11_SHIFT (16U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_HIGH_DYN_READ_ID11_WIDTH (8U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_HIGH_DYN_READ_ID11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_HIGH_DYN_READ_ID11_SHIFT)) & GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_HIGH_DYN_READ_ID11_MASK) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_HIGH_DYN_CLK_WAIT_MASK (0xF000000U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_HIGH_DYN_CLK_WAIT_SHIFT (24U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_HIGH_DYN_CLK_WAIT_WIDTH (4U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_HIGH_DYN_CLK_WAIT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_HIGH_DYN_CLK_WAIT_SHIFT)) & GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_HIGH_DYN_CLK_WAIT_MASK) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_HIGH_DYN_UPDATE_EN_MASK (0x10000000U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_HIGH_DYN_UPDATE_EN_SHIFT (28U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_HIGH_DYN_UPDATE_EN_WIDTH (1U) #define GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_HIGH_DYN_UPDATE_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_HIGH_DYN_UPDATE_EN_SHIFT)) & GTM_gtm_cls0_ARU_0_DYN_ROUTE_SR_HIGH_DYN_UPDATE_EN_MASK) /*! @} */ /*! @name ARU_1_DYN_ROUTE_SR_HIGH - ARU [g] shadow register of DYN_ROUTE register higher bits */ /*! @{ */ #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_HIGH_DYN_READ_ID9_MASK (0xFFU) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_HIGH_DYN_READ_ID9_SHIFT (0U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_HIGH_DYN_READ_ID9_WIDTH (8U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_HIGH_DYN_READ_ID9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_HIGH_DYN_READ_ID9_SHIFT)) & GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_HIGH_DYN_READ_ID9_MASK) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_HIGH_DYN_READ_ID10_MASK (0xFF00U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_HIGH_DYN_READ_ID10_SHIFT (8U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_HIGH_DYN_READ_ID10_WIDTH (8U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_HIGH_DYN_READ_ID10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_HIGH_DYN_READ_ID10_SHIFT)) & GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_HIGH_DYN_READ_ID10_MASK) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_HIGH_DYN_READ_ID11_MASK (0xFF0000U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_HIGH_DYN_READ_ID11_SHIFT (16U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_HIGH_DYN_READ_ID11_WIDTH (8U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_HIGH_DYN_READ_ID11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_HIGH_DYN_READ_ID11_SHIFT)) & GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_HIGH_DYN_READ_ID11_MASK) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_HIGH_DYN_CLK_WAIT_MASK (0xF000000U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_HIGH_DYN_CLK_WAIT_SHIFT (24U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_HIGH_DYN_CLK_WAIT_WIDTH (4U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_HIGH_DYN_CLK_WAIT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_HIGH_DYN_CLK_WAIT_SHIFT)) & GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_HIGH_DYN_CLK_WAIT_MASK) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_HIGH_DYN_UPDATE_EN_MASK (0x10000000U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_HIGH_DYN_UPDATE_EN_SHIFT (28U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_HIGH_DYN_UPDATE_EN_WIDTH (1U) #define GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_HIGH_DYN_UPDATE_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_HIGH_DYN_UPDATE_EN_SHIFT)) & GTM_gtm_cls0_ARU_1_DYN_ROUTE_SR_HIGH_DYN_UPDATE_EN_MASK) /*! @} */ /*! @name ARU_0_DYN_RDADDR - ARU [g] master ID for dynamic routing */ /*! @{ */ #define GTM_gtm_cls0_ARU_0_DYN_RDADDR_DYN_ARU_RDADDR_MASK (0x1FFU) #define GTM_gtm_cls0_ARU_0_DYN_RDADDR_DYN_ARU_RDADDR_SHIFT (0U) #define GTM_gtm_cls0_ARU_0_DYN_RDADDR_DYN_ARU_RDADDR_WIDTH (9U) #define GTM_gtm_cls0_ARU_0_DYN_RDADDR_DYN_ARU_RDADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_0_DYN_RDADDR_DYN_ARU_RDADDR_SHIFT)) & GTM_gtm_cls0_ARU_0_DYN_RDADDR_DYN_ARU_RDADDR_MASK) /*! @} */ /*! @name ARU_1_DYN_RDADDR - ARU [g] master ID for dynamic routing */ /*! @{ */ #define GTM_gtm_cls0_ARU_1_DYN_RDADDR_DYN_ARU_RDADDR_MASK (0x1FFU) #define GTM_gtm_cls0_ARU_1_DYN_RDADDR_DYN_ARU_RDADDR_SHIFT (0U) #define GTM_gtm_cls0_ARU_1_DYN_RDADDR_DYN_ARU_RDADDR_WIDTH (9U) #define GTM_gtm_cls0_ARU_1_DYN_RDADDR_DYN_ARU_RDADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_1_DYN_RDADDR_DYN_ARU_RDADDR_SHIFT)) & GTM_gtm_cls0_ARU_1_DYN_RDADDR_DYN_ARU_RDADDR_MASK) /*! @} */ /*! @name ARU_CADDR - ARU caddr counter value */ /*! @{ */ #define GTM_gtm_cls0_ARU_CADDR_CADDR_0_MASK (0x7FU) #define GTM_gtm_cls0_ARU_CADDR_CADDR_0_SHIFT (0U) #define GTM_gtm_cls0_ARU_CADDR_CADDR_0_WIDTH (7U) #define GTM_gtm_cls0_ARU_CADDR_CADDR_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_CADDR_CADDR_0_SHIFT)) & GTM_gtm_cls0_ARU_CADDR_CADDR_0_MASK) #define GTM_gtm_cls0_ARU_CADDR_CADDR_1_MASK (0x7F0000U) #define GTM_gtm_cls0_ARU_CADDR_CADDR_1_SHIFT (16U) #define GTM_gtm_cls0_ARU_CADDR_CADDR_1_WIDTH (7U) #define GTM_gtm_cls0_ARU_CADDR_CADDR_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ARU_CADDR_CADDR_1_SHIFT)) & GTM_gtm_cls0_ARU_CADDR_CADDR_1_MASK) /*! @} */ /*! @name BRC_SRC_0_ADDR - BRC read address for input channel [x] */ /*! @{ */ #define GTM_gtm_cls0_BRC_SRC_0_ADDR_ADDR_MASK (0x1FFU) #define GTM_gtm_cls0_BRC_SRC_0_ADDR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_BRC_SRC_0_ADDR_ADDR_WIDTH (9U) #define GTM_gtm_cls0_BRC_SRC_0_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_0_ADDR_ADDR_SHIFT)) & GTM_gtm_cls0_BRC_SRC_0_ADDR_ADDR_MASK) #define GTM_gtm_cls0_BRC_SRC_0_ADDR_BRC_MODE_MASK (0x1000U) #define GTM_gtm_cls0_BRC_SRC_0_ADDR_BRC_MODE_SHIFT (12U) #define GTM_gtm_cls0_BRC_SRC_0_ADDR_BRC_MODE_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_0_ADDR_BRC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_0_ADDR_BRC_MODE_SHIFT)) & GTM_gtm_cls0_BRC_SRC_0_ADDR_BRC_MODE_MASK) /*! @} */ /*! @name BRC_SRC_0_DEST - BRC destination channels for input channel [x] */ /*! @{ */ #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST0_MASK (0x1U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST0_SHIFT (0U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST0_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST0_SHIFT)) & GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST0_MASK) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST1_MASK (0x2U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST1_SHIFT (1U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST1_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST1_SHIFT)) & GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST1_MASK) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST2_MASK (0x4U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST2_SHIFT (2U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST2_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST2_SHIFT)) & GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST2_MASK) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST3_MASK (0x8U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST3_SHIFT (3U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST3_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST3_SHIFT)) & GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST3_MASK) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST4_MASK (0x10U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST4_SHIFT (4U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST4_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST4_SHIFT)) & GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST4_MASK) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST5_MASK (0x20U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST5_SHIFT (5U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST5_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST5_SHIFT)) & GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST5_MASK) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST6_MASK (0x40U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST6_SHIFT (6U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST6_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST6_SHIFT)) & GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST6_MASK) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST7_MASK (0x80U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST7_SHIFT (7U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST7_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST7_SHIFT)) & GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST7_MASK) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST8_MASK (0x100U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST8_SHIFT (8U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST8_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST8_SHIFT)) & GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST8_MASK) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST9_MASK (0x200U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST9_SHIFT (9U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST9_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST9_SHIFT)) & GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST9_MASK) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST10_MASK (0x400U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST10_SHIFT (10U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST10_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST10_SHIFT)) & GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST10_MASK) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST11_MASK (0x800U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST11_SHIFT (11U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST11_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST11_SHIFT)) & GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST11_MASK) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST12_MASK (0x1000U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST12_SHIFT (12U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST12_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST12(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST12_SHIFT)) & GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST12_MASK) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST13_MASK (0x2000U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST13_SHIFT (13U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST13_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST13(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST13_SHIFT)) & GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST13_MASK) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST14_MASK (0x4000U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST14_SHIFT (14U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST14_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST14(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST14_SHIFT)) & GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST14_MASK) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST15_MASK (0x8000U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST15_SHIFT (15U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST15_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST15(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST15_SHIFT)) & GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST15_MASK) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST16_MASK (0x10000U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST16_SHIFT (16U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST16_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST16(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST16_SHIFT)) & GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST16_MASK) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST17_MASK (0x20000U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST17_SHIFT (17U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST17_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST17(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST17_SHIFT)) & GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST17_MASK) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST18_MASK (0x40000U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST18_SHIFT (18U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST18_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST18(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST18_SHIFT)) & GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST18_MASK) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST19_MASK (0x80000U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST19_SHIFT (19U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST19_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST19(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST19_SHIFT)) & GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST19_MASK) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST20_MASK (0x100000U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST20_SHIFT (20U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST20_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST20(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST20_SHIFT)) & GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST20_MASK) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST21_MASK (0x200000U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST21_SHIFT (21U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST21_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST21(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST21_SHIFT)) & GTM_gtm_cls0_BRC_SRC_0_DEST_EN_DEST21_MASK) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_TRASHBIN_MASK (0x400000U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_TRASHBIN_SHIFT (22U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_TRASHBIN_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_0_DEST_EN_TRASHBIN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_0_DEST_EN_TRASHBIN_SHIFT)) & GTM_gtm_cls0_BRC_SRC_0_DEST_EN_TRASHBIN_MASK) /*! @} */ /*! @name BRC_SRC_1_ADDR - BRC read address for input channel [x] */ /*! @{ */ #define GTM_gtm_cls0_BRC_SRC_1_ADDR_ADDR_MASK (0x1FFU) #define GTM_gtm_cls0_BRC_SRC_1_ADDR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_BRC_SRC_1_ADDR_ADDR_WIDTH (9U) #define GTM_gtm_cls0_BRC_SRC_1_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_1_ADDR_ADDR_SHIFT)) & GTM_gtm_cls0_BRC_SRC_1_ADDR_ADDR_MASK) #define GTM_gtm_cls0_BRC_SRC_1_ADDR_BRC_MODE_MASK (0x1000U) #define GTM_gtm_cls0_BRC_SRC_1_ADDR_BRC_MODE_SHIFT (12U) #define GTM_gtm_cls0_BRC_SRC_1_ADDR_BRC_MODE_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_1_ADDR_BRC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_1_ADDR_BRC_MODE_SHIFT)) & GTM_gtm_cls0_BRC_SRC_1_ADDR_BRC_MODE_MASK) /*! @} */ /*! @name BRC_SRC_1_DEST - BRC destination channels for input channel [x] */ /*! @{ */ #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST0_MASK (0x1U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST0_SHIFT (0U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST0_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST0_SHIFT)) & GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST0_MASK) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST1_MASK (0x2U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST1_SHIFT (1U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST1_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST1_SHIFT)) & GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST1_MASK) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST2_MASK (0x4U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST2_SHIFT (2U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST2_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST2_SHIFT)) & GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST2_MASK) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST3_MASK (0x8U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST3_SHIFT (3U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST3_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST3_SHIFT)) & GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST3_MASK) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST4_MASK (0x10U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST4_SHIFT (4U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST4_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST4_SHIFT)) & GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST4_MASK) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST5_MASK (0x20U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST5_SHIFT (5U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST5_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST5_SHIFT)) & GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST5_MASK) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST6_MASK (0x40U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST6_SHIFT (6U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST6_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST6_SHIFT)) & GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST6_MASK) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST7_MASK (0x80U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST7_SHIFT (7U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST7_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST7_SHIFT)) & GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST7_MASK) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST8_MASK (0x100U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST8_SHIFT (8U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST8_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST8_SHIFT)) & GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST8_MASK) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST9_MASK (0x200U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST9_SHIFT (9U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST9_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST9_SHIFT)) & GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST9_MASK) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST10_MASK (0x400U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST10_SHIFT (10U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST10_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST10_SHIFT)) & GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST10_MASK) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST11_MASK (0x800U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST11_SHIFT (11U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST11_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST11_SHIFT)) & GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST11_MASK) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST12_MASK (0x1000U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST12_SHIFT (12U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST12_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST12(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST12_SHIFT)) & GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST12_MASK) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST13_MASK (0x2000U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST13_SHIFT (13U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST13_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST13(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST13_SHIFT)) & GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST13_MASK) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST14_MASK (0x4000U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST14_SHIFT (14U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST14_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST14(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST14_SHIFT)) & GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST14_MASK) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST15_MASK (0x8000U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST15_SHIFT (15U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST15_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST15(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST15_SHIFT)) & GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST15_MASK) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST16_MASK (0x10000U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST16_SHIFT (16U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST16_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST16(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST16_SHIFT)) & GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST16_MASK) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST17_MASK (0x20000U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST17_SHIFT (17U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST17_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST17(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST17_SHIFT)) & GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST17_MASK) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST18_MASK (0x40000U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST18_SHIFT (18U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST18_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST18(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST18_SHIFT)) & GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST18_MASK) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST19_MASK (0x80000U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST19_SHIFT (19U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST19_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST19(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST19_SHIFT)) & GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST19_MASK) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST20_MASK (0x100000U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST20_SHIFT (20U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST20_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST20(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST20_SHIFT)) & GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST20_MASK) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST21_MASK (0x200000U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST21_SHIFT (21U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST21_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST21(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST21_SHIFT)) & GTM_gtm_cls0_BRC_SRC_1_DEST_EN_DEST21_MASK) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_TRASHBIN_MASK (0x400000U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_TRASHBIN_SHIFT (22U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_TRASHBIN_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_1_DEST_EN_TRASHBIN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_1_DEST_EN_TRASHBIN_SHIFT)) & GTM_gtm_cls0_BRC_SRC_1_DEST_EN_TRASHBIN_MASK) /*! @} */ /*! @name BRC_SRC_2_ADDR - BRC read address for input channel [x] */ /*! @{ */ #define GTM_gtm_cls0_BRC_SRC_2_ADDR_ADDR_MASK (0x1FFU) #define GTM_gtm_cls0_BRC_SRC_2_ADDR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_BRC_SRC_2_ADDR_ADDR_WIDTH (9U) #define GTM_gtm_cls0_BRC_SRC_2_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_2_ADDR_ADDR_SHIFT)) & GTM_gtm_cls0_BRC_SRC_2_ADDR_ADDR_MASK) #define GTM_gtm_cls0_BRC_SRC_2_ADDR_BRC_MODE_MASK (0x1000U) #define GTM_gtm_cls0_BRC_SRC_2_ADDR_BRC_MODE_SHIFT (12U) #define GTM_gtm_cls0_BRC_SRC_2_ADDR_BRC_MODE_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_2_ADDR_BRC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_2_ADDR_BRC_MODE_SHIFT)) & GTM_gtm_cls0_BRC_SRC_2_ADDR_BRC_MODE_MASK) /*! @} */ /*! @name BRC_SRC_2_DEST - BRC destination channels for input channel [x] */ /*! @{ */ #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST0_MASK (0x1U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST0_SHIFT (0U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST0_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST0_SHIFT)) & GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST0_MASK) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST1_MASK (0x2U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST1_SHIFT (1U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST1_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST1_SHIFT)) & GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST1_MASK) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST2_MASK (0x4U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST2_SHIFT (2U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST2_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST2_SHIFT)) & GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST2_MASK) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST3_MASK (0x8U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST3_SHIFT (3U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST3_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST3_SHIFT)) & GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST3_MASK) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST4_MASK (0x10U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST4_SHIFT (4U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST4_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST4_SHIFT)) & GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST4_MASK) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST5_MASK (0x20U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST5_SHIFT (5U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST5_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST5_SHIFT)) & GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST5_MASK) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST6_MASK (0x40U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST6_SHIFT (6U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST6_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST6_SHIFT)) & GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST6_MASK) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST7_MASK (0x80U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST7_SHIFT (7U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST7_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST7_SHIFT)) & GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST7_MASK) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST8_MASK (0x100U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST8_SHIFT (8U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST8_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST8_SHIFT)) & GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST8_MASK) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST9_MASK (0x200U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST9_SHIFT (9U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST9_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST9_SHIFT)) & GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST9_MASK) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST10_MASK (0x400U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST10_SHIFT (10U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST10_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST10_SHIFT)) & GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST10_MASK) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST11_MASK (0x800U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST11_SHIFT (11U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST11_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST11_SHIFT)) & GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST11_MASK) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST12_MASK (0x1000U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST12_SHIFT (12U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST12_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST12(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST12_SHIFT)) & GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST12_MASK) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST13_MASK (0x2000U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST13_SHIFT (13U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST13_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST13(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST13_SHIFT)) & GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST13_MASK) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST14_MASK (0x4000U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST14_SHIFT (14U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST14_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST14(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST14_SHIFT)) & GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST14_MASK) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST15_MASK (0x8000U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST15_SHIFT (15U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST15_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST15(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST15_SHIFT)) & GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST15_MASK) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST16_MASK (0x10000U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST16_SHIFT (16U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST16_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST16(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST16_SHIFT)) & GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST16_MASK) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST17_MASK (0x20000U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST17_SHIFT (17U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST17_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST17(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST17_SHIFT)) & GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST17_MASK) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST18_MASK (0x40000U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST18_SHIFT (18U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST18_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST18(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST18_SHIFT)) & GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST18_MASK) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST19_MASK (0x80000U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST19_SHIFT (19U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST19_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST19(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST19_SHIFT)) & GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST19_MASK) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST20_MASK (0x100000U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST20_SHIFT (20U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST20_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST20(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST20_SHIFT)) & GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST20_MASK) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST21_MASK (0x200000U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST21_SHIFT (21U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST21_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST21(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST21_SHIFT)) & GTM_gtm_cls0_BRC_SRC_2_DEST_EN_DEST21_MASK) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_TRASHBIN_MASK (0x400000U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_TRASHBIN_SHIFT (22U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_TRASHBIN_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_2_DEST_EN_TRASHBIN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_2_DEST_EN_TRASHBIN_SHIFT)) & GTM_gtm_cls0_BRC_SRC_2_DEST_EN_TRASHBIN_MASK) /*! @} */ /*! @name BRC_SRC_3_ADDR - BRC read address for input channel [x] */ /*! @{ */ #define GTM_gtm_cls0_BRC_SRC_3_ADDR_ADDR_MASK (0x1FFU) #define GTM_gtm_cls0_BRC_SRC_3_ADDR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_BRC_SRC_3_ADDR_ADDR_WIDTH (9U) #define GTM_gtm_cls0_BRC_SRC_3_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_3_ADDR_ADDR_SHIFT)) & GTM_gtm_cls0_BRC_SRC_3_ADDR_ADDR_MASK) #define GTM_gtm_cls0_BRC_SRC_3_ADDR_BRC_MODE_MASK (0x1000U) #define GTM_gtm_cls0_BRC_SRC_3_ADDR_BRC_MODE_SHIFT (12U) #define GTM_gtm_cls0_BRC_SRC_3_ADDR_BRC_MODE_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_3_ADDR_BRC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_3_ADDR_BRC_MODE_SHIFT)) & GTM_gtm_cls0_BRC_SRC_3_ADDR_BRC_MODE_MASK) /*! @} */ /*! @name BRC_SRC_3_DEST - BRC destination channels for input channel [x] */ /*! @{ */ #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST0_MASK (0x1U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST0_SHIFT (0U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST0_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST0_SHIFT)) & GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST0_MASK) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST1_MASK (0x2U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST1_SHIFT (1U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST1_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST1_SHIFT)) & GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST1_MASK) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST2_MASK (0x4U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST2_SHIFT (2U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST2_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST2_SHIFT)) & GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST2_MASK) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST3_MASK (0x8U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST3_SHIFT (3U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST3_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST3_SHIFT)) & GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST3_MASK) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST4_MASK (0x10U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST4_SHIFT (4U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST4_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST4_SHIFT)) & GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST4_MASK) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST5_MASK (0x20U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST5_SHIFT (5U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST5_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST5_SHIFT)) & GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST5_MASK) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST6_MASK (0x40U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST6_SHIFT (6U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST6_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST6_SHIFT)) & GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST6_MASK) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST7_MASK (0x80U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST7_SHIFT (7U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST7_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST7_SHIFT)) & GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST7_MASK) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST8_MASK (0x100U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST8_SHIFT (8U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST8_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST8_SHIFT)) & GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST8_MASK) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST9_MASK (0x200U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST9_SHIFT (9U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST9_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST9_SHIFT)) & GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST9_MASK) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST10_MASK (0x400U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST10_SHIFT (10U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST10_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST10_SHIFT)) & GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST10_MASK) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST11_MASK (0x800U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST11_SHIFT (11U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST11_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST11_SHIFT)) & GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST11_MASK) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST12_MASK (0x1000U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST12_SHIFT (12U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST12_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST12(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST12_SHIFT)) & GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST12_MASK) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST13_MASK (0x2000U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST13_SHIFT (13U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST13_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST13(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST13_SHIFT)) & GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST13_MASK) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST14_MASK (0x4000U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST14_SHIFT (14U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST14_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST14(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST14_SHIFT)) & GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST14_MASK) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST15_MASK (0x8000U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST15_SHIFT (15U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST15_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST15(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST15_SHIFT)) & GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST15_MASK) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST16_MASK (0x10000U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST16_SHIFT (16U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST16_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST16(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST16_SHIFT)) & GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST16_MASK) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST17_MASK (0x20000U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST17_SHIFT (17U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST17_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST17(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST17_SHIFT)) & GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST17_MASK) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST18_MASK (0x40000U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST18_SHIFT (18U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST18_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST18(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST18_SHIFT)) & GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST18_MASK) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST19_MASK (0x80000U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST19_SHIFT (19U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST19_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST19(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST19_SHIFT)) & GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST19_MASK) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST20_MASK (0x100000U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST20_SHIFT (20U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST20_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST20(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST20_SHIFT)) & GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST20_MASK) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST21_MASK (0x200000U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST21_SHIFT (21U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST21_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST21(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST21_SHIFT)) & GTM_gtm_cls0_BRC_SRC_3_DEST_EN_DEST21_MASK) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_TRASHBIN_MASK (0x400000U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_TRASHBIN_SHIFT (22U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_TRASHBIN_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_3_DEST_EN_TRASHBIN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_3_DEST_EN_TRASHBIN_SHIFT)) & GTM_gtm_cls0_BRC_SRC_3_DEST_EN_TRASHBIN_MASK) /*! @} */ /*! @name BRC_SRC_4_ADDR - BRC read address for input channel [x] */ /*! @{ */ #define GTM_gtm_cls0_BRC_SRC_4_ADDR_ADDR_MASK (0x1FFU) #define GTM_gtm_cls0_BRC_SRC_4_ADDR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_BRC_SRC_4_ADDR_ADDR_WIDTH (9U) #define GTM_gtm_cls0_BRC_SRC_4_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_4_ADDR_ADDR_SHIFT)) & GTM_gtm_cls0_BRC_SRC_4_ADDR_ADDR_MASK) #define GTM_gtm_cls0_BRC_SRC_4_ADDR_BRC_MODE_MASK (0x1000U) #define GTM_gtm_cls0_BRC_SRC_4_ADDR_BRC_MODE_SHIFT (12U) #define GTM_gtm_cls0_BRC_SRC_4_ADDR_BRC_MODE_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_4_ADDR_BRC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_4_ADDR_BRC_MODE_SHIFT)) & GTM_gtm_cls0_BRC_SRC_4_ADDR_BRC_MODE_MASK) /*! @} */ /*! @name BRC_SRC_4_DEST - BRC destination channels for input channel [x] */ /*! @{ */ #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST0_MASK (0x1U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST0_SHIFT (0U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST0_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST0_SHIFT)) & GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST0_MASK) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST1_MASK (0x2U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST1_SHIFT (1U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST1_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST1_SHIFT)) & GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST1_MASK) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST2_MASK (0x4U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST2_SHIFT (2U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST2_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST2_SHIFT)) & GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST2_MASK) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST3_MASK (0x8U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST3_SHIFT (3U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST3_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST3_SHIFT)) & GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST3_MASK) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST4_MASK (0x10U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST4_SHIFT (4U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST4_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST4_SHIFT)) & GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST4_MASK) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST5_MASK (0x20U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST5_SHIFT (5U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST5_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST5_SHIFT)) & GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST5_MASK) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST6_MASK (0x40U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST6_SHIFT (6U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST6_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST6_SHIFT)) & GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST6_MASK) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST7_MASK (0x80U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST7_SHIFT (7U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST7_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST7_SHIFT)) & GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST7_MASK) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST8_MASK (0x100U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST8_SHIFT (8U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST8_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST8_SHIFT)) & GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST8_MASK) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST9_MASK (0x200U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST9_SHIFT (9U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST9_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST9_SHIFT)) & GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST9_MASK) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST10_MASK (0x400U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST10_SHIFT (10U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST10_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST10_SHIFT)) & GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST10_MASK) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST11_MASK (0x800U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST11_SHIFT (11U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST11_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST11_SHIFT)) & GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST11_MASK) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST12_MASK (0x1000U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST12_SHIFT (12U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST12_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST12(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST12_SHIFT)) & GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST12_MASK) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST13_MASK (0x2000U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST13_SHIFT (13U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST13_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST13(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST13_SHIFT)) & GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST13_MASK) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST14_MASK (0x4000U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST14_SHIFT (14U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST14_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST14(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST14_SHIFT)) & GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST14_MASK) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST15_MASK (0x8000U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST15_SHIFT (15U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST15_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST15(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST15_SHIFT)) & GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST15_MASK) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST16_MASK (0x10000U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST16_SHIFT (16U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST16_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST16(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST16_SHIFT)) & GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST16_MASK) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST17_MASK (0x20000U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST17_SHIFT (17U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST17_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST17(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST17_SHIFT)) & GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST17_MASK) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST18_MASK (0x40000U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST18_SHIFT (18U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST18_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST18(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST18_SHIFT)) & GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST18_MASK) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST19_MASK (0x80000U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST19_SHIFT (19U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST19_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST19(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST19_SHIFT)) & GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST19_MASK) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST20_MASK (0x100000U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST20_SHIFT (20U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST20_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST20(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST20_SHIFT)) & GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST20_MASK) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST21_MASK (0x200000U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST21_SHIFT (21U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST21_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST21(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST21_SHIFT)) & GTM_gtm_cls0_BRC_SRC_4_DEST_EN_DEST21_MASK) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_TRASHBIN_MASK (0x400000U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_TRASHBIN_SHIFT (22U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_TRASHBIN_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_4_DEST_EN_TRASHBIN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_4_DEST_EN_TRASHBIN_SHIFT)) & GTM_gtm_cls0_BRC_SRC_4_DEST_EN_TRASHBIN_MASK) /*! @} */ /*! @name BRC_SRC_5_ADDR - BRC read address for input channel [x] */ /*! @{ */ #define GTM_gtm_cls0_BRC_SRC_5_ADDR_ADDR_MASK (0x1FFU) #define GTM_gtm_cls0_BRC_SRC_5_ADDR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_BRC_SRC_5_ADDR_ADDR_WIDTH (9U) #define GTM_gtm_cls0_BRC_SRC_5_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_5_ADDR_ADDR_SHIFT)) & GTM_gtm_cls0_BRC_SRC_5_ADDR_ADDR_MASK) #define GTM_gtm_cls0_BRC_SRC_5_ADDR_BRC_MODE_MASK (0x1000U) #define GTM_gtm_cls0_BRC_SRC_5_ADDR_BRC_MODE_SHIFT (12U) #define GTM_gtm_cls0_BRC_SRC_5_ADDR_BRC_MODE_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_5_ADDR_BRC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_5_ADDR_BRC_MODE_SHIFT)) & GTM_gtm_cls0_BRC_SRC_5_ADDR_BRC_MODE_MASK) /*! @} */ /*! @name BRC_SRC_5_DEST - BRC destination channels for input channel [x] */ /*! @{ */ #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST0_MASK (0x1U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST0_SHIFT (0U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST0_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST0_SHIFT)) & GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST0_MASK) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST1_MASK (0x2U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST1_SHIFT (1U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST1_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST1_SHIFT)) & GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST1_MASK) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST2_MASK (0x4U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST2_SHIFT (2U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST2_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST2_SHIFT)) & GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST2_MASK) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST3_MASK (0x8U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST3_SHIFT (3U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST3_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST3_SHIFT)) & GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST3_MASK) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST4_MASK (0x10U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST4_SHIFT (4U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST4_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST4_SHIFT)) & GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST4_MASK) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST5_MASK (0x20U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST5_SHIFT (5U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST5_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST5_SHIFT)) & GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST5_MASK) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST6_MASK (0x40U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST6_SHIFT (6U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST6_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST6_SHIFT)) & GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST6_MASK) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST7_MASK (0x80U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST7_SHIFT (7U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST7_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST7_SHIFT)) & GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST7_MASK) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST8_MASK (0x100U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST8_SHIFT (8U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST8_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST8_SHIFT)) & GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST8_MASK) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST9_MASK (0x200U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST9_SHIFT (9U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST9_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST9_SHIFT)) & GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST9_MASK) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST10_MASK (0x400U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST10_SHIFT (10U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST10_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST10_SHIFT)) & GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST10_MASK) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST11_MASK (0x800U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST11_SHIFT (11U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST11_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST11_SHIFT)) & GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST11_MASK) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST12_MASK (0x1000U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST12_SHIFT (12U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST12_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST12(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST12_SHIFT)) & GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST12_MASK) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST13_MASK (0x2000U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST13_SHIFT (13U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST13_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST13(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST13_SHIFT)) & GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST13_MASK) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST14_MASK (0x4000U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST14_SHIFT (14U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST14_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST14(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST14_SHIFT)) & GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST14_MASK) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST15_MASK (0x8000U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST15_SHIFT (15U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST15_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST15(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST15_SHIFT)) & GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST15_MASK) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST16_MASK (0x10000U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST16_SHIFT (16U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST16_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST16(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST16_SHIFT)) & GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST16_MASK) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST17_MASK (0x20000U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST17_SHIFT (17U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST17_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST17(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST17_SHIFT)) & GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST17_MASK) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST18_MASK (0x40000U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST18_SHIFT (18U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST18_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST18(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST18_SHIFT)) & GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST18_MASK) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST19_MASK (0x80000U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST19_SHIFT (19U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST19_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST19(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST19_SHIFT)) & GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST19_MASK) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST20_MASK (0x100000U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST20_SHIFT (20U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST20_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST20(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST20_SHIFT)) & GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST20_MASK) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST21_MASK (0x200000U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST21_SHIFT (21U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST21_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST21(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST21_SHIFT)) & GTM_gtm_cls0_BRC_SRC_5_DEST_EN_DEST21_MASK) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_TRASHBIN_MASK (0x400000U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_TRASHBIN_SHIFT (22U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_TRASHBIN_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_5_DEST_EN_TRASHBIN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_5_DEST_EN_TRASHBIN_SHIFT)) & GTM_gtm_cls0_BRC_SRC_5_DEST_EN_TRASHBIN_MASK) /*! @} */ /*! @name BRC_SRC_6_ADDR - BRC read address for input channel [x] */ /*! @{ */ #define GTM_gtm_cls0_BRC_SRC_6_ADDR_ADDR_MASK (0x1FFU) #define GTM_gtm_cls0_BRC_SRC_6_ADDR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_BRC_SRC_6_ADDR_ADDR_WIDTH (9U) #define GTM_gtm_cls0_BRC_SRC_6_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_6_ADDR_ADDR_SHIFT)) & GTM_gtm_cls0_BRC_SRC_6_ADDR_ADDR_MASK) #define GTM_gtm_cls0_BRC_SRC_6_ADDR_BRC_MODE_MASK (0x1000U) #define GTM_gtm_cls0_BRC_SRC_6_ADDR_BRC_MODE_SHIFT (12U) #define GTM_gtm_cls0_BRC_SRC_6_ADDR_BRC_MODE_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_6_ADDR_BRC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_6_ADDR_BRC_MODE_SHIFT)) & GTM_gtm_cls0_BRC_SRC_6_ADDR_BRC_MODE_MASK) /*! @} */ /*! @name BRC_SRC_6_DEST - BRC destination channels for input channel [x] */ /*! @{ */ #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST0_MASK (0x1U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST0_SHIFT (0U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST0_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST0_SHIFT)) & GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST0_MASK) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST1_MASK (0x2U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST1_SHIFT (1U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST1_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST1_SHIFT)) & GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST1_MASK) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST2_MASK (0x4U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST2_SHIFT (2U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST2_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST2_SHIFT)) & GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST2_MASK) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST3_MASK (0x8U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST3_SHIFT (3U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST3_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST3_SHIFT)) & GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST3_MASK) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST4_MASK (0x10U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST4_SHIFT (4U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST4_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST4_SHIFT)) & GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST4_MASK) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST5_MASK (0x20U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST5_SHIFT (5U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST5_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST5_SHIFT)) & GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST5_MASK) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST6_MASK (0x40U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST6_SHIFT (6U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST6_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST6_SHIFT)) & GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST6_MASK) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST7_MASK (0x80U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST7_SHIFT (7U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST7_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST7_SHIFT)) & GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST7_MASK) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST8_MASK (0x100U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST8_SHIFT (8U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST8_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST8_SHIFT)) & GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST8_MASK) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST9_MASK (0x200U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST9_SHIFT (9U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST9_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST9_SHIFT)) & GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST9_MASK) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST10_MASK (0x400U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST10_SHIFT (10U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST10_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST10_SHIFT)) & GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST10_MASK) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST11_MASK (0x800U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST11_SHIFT (11U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST11_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST11_SHIFT)) & GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST11_MASK) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST12_MASK (0x1000U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST12_SHIFT (12U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST12_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST12(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST12_SHIFT)) & GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST12_MASK) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST13_MASK (0x2000U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST13_SHIFT (13U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST13_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST13(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST13_SHIFT)) & GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST13_MASK) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST14_MASK (0x4000U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST14_SHIFT (14U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST14_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST14(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST14_SHIFT)) & GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST14_MASK) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST15_MASK (0x8000U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST15_SHIFT (15U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST15_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST15(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST15_SHIFT)) & GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST15_MASK) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST16_MASK (0x10000U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST16_SHIFT (16U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST16_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST16(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST16_SHIFT)) & GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST16_MASK) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST17_MASK (0x20000U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST17_SHIFT (17U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST17_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST17(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST17_SHIFT)) & GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST17_MASK) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST18_MASK (0x40000U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST18_SHIFT (18U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST18_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST18(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST18_SHIFT)) & GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST18_MASK) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST19_MASK (0x80000U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST19_SHIFT (19U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST19_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST19(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST19_SHIFT)) & GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST19_MASK) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST20_MASK (0x100000U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST20_SHIFT (20U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST20_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST20(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST20_SHIFT)) & GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST20_MASK) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST21_MASK (0x200000U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST21_SHIFT (21U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST21_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST21(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST21_SHIFT)) & GTM_gtm_cls0_BRC_SRC_6_DEST_EN_DEST21_MASK) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_TRASHBIN_MASK (0x400000U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_TRASHBIN_SHIFT (22U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_TRASHBIN_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_6_DEST_EN_TRASHBIN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_6_DEST_EN_TRASHBIN_SHIFT)) & GTM_gtm_cls0_BRC_SRC_6_DEST_EN_TRASHBIN_MASK) /*! @} */ /*! @name BRC_SRC_7_ADDR - BRC read address for input channel [x] */ /*! @{ */ #define GTM_gtm_cls0_BRC_SRC_7_ADDR_ADDR_MASK (0x1FFU) #define GTM_gtm_cls0_BRC_SRC_7_ADDR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_BRC_SRC_7_ADDR_ADDR_WIDTH (9U) #define GTM_gtm_cls0_BRC_SRC_7_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_7_ADDR_ADDR_SHIFT)) & GTM_gtm_cls0_BRC_SRC_7_ADDR_ADDR_MASK) #define GTM_gtm_cls0_BRC_SRC_7_ADDR_BRC_MODE_MASK (0x1000U) #define GTM_gtm_cls0_BRC_SRC_7_ADDR_BRC_MODE_SHIFT (12U) #define GTM_gtm_cls0_BRC_SRC_7_ADDR_BRC_MODE_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_7_ADDR_BRC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_7_ADDR_BRC_MODE_SHIFT)) & GTM_gtm_cls0_BRC_SRC_7_ADDR_BRC_MODE_MASK) /*! @} */ /*! @name BRC_SRC_7_DEST - BRC destination channels for input channel [x] */ /*! @{ */ #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST0_MASK (0x1U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST0_SHIFT (0U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST0_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST0_SHIFT)) & GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST0_MASK) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST1_MASK (0x2U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST1_SHIFT (1U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST1_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST1_SHIFT)) & GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST1_MASK) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST2_MASK (0x4U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST2_SHIFT (2U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST2_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST2_SHIFT)) & GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST2_MASK) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST3_MASK (0x8U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST3_SHIFT (3U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST3_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST3_SHIFT)) & GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST3_MASK) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST4_MASK (0x10U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST4_SHIFT (4U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST4_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST4_SHIFT)) & GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST4_MASK) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST5_MASK (0x20U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST5_SHIFT (5U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST5_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST5_SHIFT)) & GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST5_MASK) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST6_MASK (0x40U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST6_SHIFT (6U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST6_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST6_SHIFT)) & GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST6_MASK) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST7_MASK (0x80U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST7_SHIFT (7U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST7_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST7_SHIFT)) & GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST7_MASK) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST8_MASK (0x100U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST8_SHIFT (8U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST8_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST8_SHIFT)) & GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST8_MASK) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST9_MASK (0x200U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST9_SHIFT (9U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST9_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST9_SHIFT)) & GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST9_MASK) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST10_MASK (0x400U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST10_SHIFT (10U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST10_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST10_SHIFT)) & GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST10_MASK) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST11_MASK (0x800U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST11_SHIFT (11U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST11_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST11_SHIFT)) & GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST11_MASK) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST12_MASK (0x1000U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST12_SHIFT (12U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST12_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST12(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST12_SHIFT)) & GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST12_MASK) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST13_MASK (0x2000U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST13_SHIFT (13U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST13_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST13(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST13_SHIFT)) & GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST13_MASK) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST14_MASK (0x4000U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST14_SHIFT (14U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST14_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST14(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST14_SHIFT)) & GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST14_MASK) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST15_MASK (0x8000U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST15_SHIFT (15U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST15_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST15(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST15_SHIFT)) & GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST15_MASK) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST16_MASK (0x10000U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST16_SHIFT (16U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST16_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST16(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST16_SHIFT)) & GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST16_MASK) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST17_MASK (0x20000U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST17_SHIFT (17U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST17_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST17(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST17_SHIFT)) & GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST17_MASK) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST18_MASK (0x40000U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST18_SHIFT (18U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST18_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST18(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST18_SHIFT)) & GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST18_MASK) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST19_MASK (0x80000U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST19_SHIFT (19U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST19_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST19(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST19_SHIFT)) & GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST19_MASK) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST20_MASK (0x100000U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST20_SHIFT (20U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST20_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST20(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST20_SHIFT)) & GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST20_MASK) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST21_MASK (0x200000U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST21_SHIFT (21U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST21_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST21(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST21_SHIFT)) & GTM_gtm_cls0_BRC_SRC_7_DEST_EN_DEST21_MASK) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_TRASHBIN_MASK (0x400000U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_TRASHBIN_SHIFT (22U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_TRASHBIN_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_7_DEST_EN_TRASHBIN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_7_DEST_EN_TRASHBIN_SHIFT)) & GTM_gtm_cls0_BRC_SRC_7_DEST_EN_TRASHBIN_MASK) /*! @} */ /*! @name BRC_SRC_8_ADDR - BRC read address for input channel [x] */ /*! @{ */ #define GTM_gtm_cls0_BRC_SRC_8_ADDR_ADDR_MASK (0x1FFU) #define GTM_gtm_cls0_BRC_SRC_8_ADDR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_BRC_SRC_8_ADDR_ADDR_WIDTH (9U) #define GTM_gtm_cls0_BRC_SRC_8_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_8_ADDR_ADDR_SHIFT)) & GTM_gtm_cls0_BRC_SRC_8_ADDR_ADDR_MASK) #define GTM_gtm_cls0_BRC_SRC_8_ADDR_BRC_MODE_MASK (0x1000U) #define GTM_gtm_cls0_BRC_SRC_8_ADDR_BRC_MODE_SHIFT (12U) #define GTM_gtm_cls0_BRC_SRC_8_ADDR_BRC_MODE_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_8_ADDR_BRC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_8_ADDR_BRC_MODE_SHIFT)) & GTM_gtm_cls0_BRC_SRC_8_ADDR_BRC_MODE_MASK) /*! @} */ /*! @name BRC_SRC_8_DEST - BRC destination channels for input channel [x] */ /*! @{ */ #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST0_MASK (0x1U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST0_SHIFT (0U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST0_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST0_SHIFT)) & GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST0_MASK) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST1_MASK (0x2U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST1_SHIFT (1U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST1_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST1_SHIFT)) & GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST1_MASK) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST2_MASK (0x4U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST2_SHIFT (2U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST2_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST2_SHIFT)) & GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST2_MASK) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST3_MASK (0x8U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST3_SHIFT (3U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST3_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST3_SHIFT)) & GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST3_MASK) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST4_MASK (0x10U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST4_SHIFT (4U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST4_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST4_SHIFT)) & GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST4_MASK) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST5_MASK (0x20U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST5_SHIFT (5U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST5_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST5_SHIFT)) & GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST5_MASK) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST6_MASK (0x40U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST6_SHIFT (6U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST6_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST6_SHIFT)) & GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST6_MASK) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST7_MASK (0x80U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST7_SHIFT (7U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST7_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST7_SHIFT)) & GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST7_MASK) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST8_MASK (0x100U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST8_SHIFT (8U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST8_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST8_SHIFT)) & GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST8_MASK) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST9_MASK (0x200U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST9_SHIFT (9U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST9_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST9_SHIFT)) & GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST9_MASK) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST10_MASK (0x400U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST10_SHIFT (10U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST10_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST10_SHIFT)) & GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST10_MASK) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST11_MASK (0x800U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST11_SHIFT (11U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST11_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST11_SHIFT)) & GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST11_MASK) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST12_MASK (0x1000U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST12_SHIFT (12U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST12_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST12(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST12_SHIFT)) & GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST12_MASK) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST13_MASK (0x2000U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST13_SHIFT (13U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST13_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST13(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST13_SHIFT)) & GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST13_MASK) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST14_MASK (0x4000U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST14_SHIFT (14U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST14_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST14(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST14_SHIFT)) & GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST14_MASK) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST15_MASK (0x8000U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST15_SHIFT (15U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST15_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST15(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST15_SHIFT)) & GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST15_MASK) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST16_MASK (0x10000U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST16_SHIFT (16U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST16_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST16(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST16_SHIFT)) & GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST16_MASK) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST17_MASK (0x20000U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST17_SHIFT (17U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST17_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST17(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST17_SHIFT)) & GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST17_MASK) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST18_MASK (0x40000U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST18_SHIFT (18U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST18_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST18(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST18_SHIFT)) & GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST18_MASK) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST19_MASK (0x80000U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST19_SHIFT (19U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST19_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST19(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST19_SHIFT)) & GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST19_MASK) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST20_MASK (0x100000U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST20_SHIFT (20U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST20_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST20(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST20_SHIFT)) & GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST20_MASK) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST21_MASK (0x200000U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST21_SHIFT (21U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST21_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST21(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST21_SHIFT)) & GTM_gtm_cls0_BRC_SRC_8_DEST_EN_DEST21_MASK) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_TRASHBIN_MASK (0x400000U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_TRASHBIN_SHIFT (22U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_TRASHBIN_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_8_DEST_EN_TRASHBIN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_8_DEST_EN_TRASHBIN_SHIFT)) & GTM_gtm_cls0_BRC_SRC_8_DEST_EN_TRASHBIN_MASK) /*! @} */ /*! @name BRC_SRC_9_ADDR - BRC read address for input channel [x] */ /*! @{ */ #define GTM_gtm_cls0_BRC_SRC_9_ADDR_ADDR_MASK (0x1FFU) #define GTM_gtm_cls0_BRC_SRC_9_ADDR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_BRC_SRC_9_ADDR_ADDR_WIDTH (9U) #define GTM_gtm_cls0_BRC_SRC_9_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_9_ADDR_ADDR_SHIFT)) & GTM_gtm_cls0_BRC_SRC_9_ADDR_ADDR_MASK) #define GTM_gtm_cls0_BRC_SRC_9_ADDR_BRC_MODE_MASK (0x1000U) #define GTM_gtm_cls0_BRC_SRC_9_ADDR_BRC_MODE_SHIFT (12U) #define GTM_gtm_cls0_BRC_SRC_9_ADDR_BRC_MODE_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_9_ADDR_BRC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_9_ADDR_BRC_MODE_SHIFT)) & GTM_gtm_cls0_BRC_SRC_9_ADDR_BRC_MODE_MASK) /*! @} */ /*! @name BRC_SRC_9_DEST - BRC destination channels for input channel [x] */ /*! @{ */ #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST0_MASK (0x1U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST0_SHIFT (0U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST0_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST0_SHIFT)) & GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST0_MASK) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST1_MASK (0x2U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST1_SHIFT (1U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST1_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST1_SHIFT)) & GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST1_MASK) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST2_MASK (0x4U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST2_SHIFT (2U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST2_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST2_SHIFT)) & GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST2_MASK) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST3_MASK (0x8U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST3_SHIFT (3U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST3_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST3_SHIFT)) & GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST3_MASK) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST4_MASK (0x10U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST4_SHIFT (4U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST4_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST4_SHIFT)) & GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST4_MASK) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST5_MASK (0x20U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST5_SHIFT (5U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST5_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST5_SHIFT)) & GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST5_MASK) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST6_MASK (0x40U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST6_SHIFT (6U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST6_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST6_SHIFT)) & GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST6_MASK) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST7_MASK (0x80U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST7_SHIFT (7U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST7_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST7_SHIFT)) & GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST7_MASK) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST8_MASK (0x100U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST8_SHIFT (8U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST8_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST8_SHIFT)) & GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST8_MASK) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST9_MASK (0x200U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST9_SHIFT (9U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST9_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST9_SHIFT)) & GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST9_MASK) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST10_MASK (0x400U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST10_SHIFT (10U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST10_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST10_SHIFT)) & GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST10_MASK) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST11_MASK (0x800U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST11_SHIFT (11U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST11_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST11_SHIFT)) & GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST11_MASK) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST12_MASK (0x1000U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST12_SHIFT (12U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST12_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST12(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST12_SHIFT)) & GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST12_MASK) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST13_MASK (0x2000U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST13_SHIFT (13U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST13_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST13(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST13_SHIFT)) & GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST13_MASK) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST14_MASK (0x4000U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST14_SHIFT (14U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST14_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST14(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST14_SHIFT)) & GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST14_MASK) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST15_MASK (0x8000U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST15_SHIFT (15U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST15_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST15(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST15_SHIFT)) & GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST15_MASK) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST16_MASK (0x10000U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST16_SHIFT (16U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST16_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST16(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST16_SHIFT)) & GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST16_MASK) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST17_MASK (0x20000U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST17_SHIFT (17U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST17_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST17(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST17_SHIFT)) & GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST17_MASK) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST18_MASK (0x40000U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST18_SHIFT (18U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST18_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST18(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST18_SHIFT)) & GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST18_MASK) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST19_MASK (0x80000U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST19_SHIFT (19U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST19_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST19(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST19_SHIFT)) & GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST19_MASK) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST20_MASK (0x100000U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST20_SHIFT (20U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST20_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST20(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST20_SHIFT)) & GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST20_MASK) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST21_MASK (0x200000U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST21_SHIFT (21U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST21_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST21(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST21_SHIFT)) & GTM_gtm_cls0_BRC_SRC_9_DEST_EN_DEST21_MASK) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_TRASHBIN_MASK (0x400000U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_TRASHBIN_SHIFT (22U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_TRASHBIN_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_9_DEST_EN_TRASHBIN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_9_DEST_EN_TRASHBIN_SHIFT)) & GTM_gtm_cls0_BRC_SRC_9_DEST_EN_TRASHBIN_MASK) /*! @} */ /*! @name BRC_SRC_10_ADDR - BRC read address for input channel [x] */ /*! @{ */ #define GTM_gtm_cls0_BRC_SRC_10_ADDR_ADDR_MASK (0x1FFU) #define GTM_gtm_cls0_BRC_SRC_10_ADDR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_BRC_SRC_10_ADDR_ADDR_WIDTH (9U) #define GTM_gtm_cls0_BRC_SRC_10_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_10_ADDR_ADDR_SHIFT)) & GTM_gtm_cls0_BRC_SRC_10_ADDR_ADDR_MASK) #define GTM_gtm_cls0_BRC_SRC_10_ADDR_BRC_MODE_MASK (0x1000U) #define GTM_gtm_cls0_BRC_SRC_10_ADDR_BRC_MODE_SHIFT (12U) #define GTM_gtm_cls0_BRC_SRC_10_ADDR_BRC_MODE_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_10_ADDR_BRC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_10_ADDR_BRC_MODE_SHIFT)) & GTM_gtm_cls0_BRC_SRC_10_ADDR_BRC_MODE_MASK) /*! @} */ /*! @name BRC_SRC_10_DEST - BRC destination channels for input channel [x] */ /*! @{ */ #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST0_MASK (0x1U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST0_SHIFT (0U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST0_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST0_SHIFT)) & GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST0_MASK) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST1_MASK (0x2U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST1_SHIFT (1U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST1_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST1_SHIFT)) & GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST1_MASK) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST2_MASK (0x4U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST2_SHIFT (2U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST2_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST2_SHIFT)) & GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST2_MASK) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST3_MASK (0x8U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST3_SHIFT (3U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST3_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST3_SHIFT)) & GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST3_MASK) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST4_MASK (0x10U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST4_SHIFT (4U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST4_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST4_SHIFT)) & GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST4_MASK) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST5_MASK (0x20U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST5_SHIFT (5U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST5_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST5_SHIFT)) & GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST5_MASK) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST6_MASK (0x40U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST6_SHIFT (6U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST6_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST6_SHIFT)) & GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST6_MASK) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST7_MASK (0x80U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST7_SHIFT (7U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST7_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST7_SHIFT)) & GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST7_MASK) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST8_MASK (0x100U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST8_SHIFT (8U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST8_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST8_SHIFT)) & GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST8_MASK) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST9_MASK (0x200U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST9_SHIFT (9U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST9_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST9_SHIFT)) & GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST9_MASK) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST10_MASK (0x400U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST10_SHIFT (10U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST10_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST10_SHIFT)) & GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST10_MASK) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST11_MASK (0x800U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST11_SHIFT (11U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST11_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST11_SHIFT)) & GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST11_MASK) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST12_MASK (0x1000U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST12_SHIFT (12U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST12_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST12(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST12_SHIFT)) & GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST12_MASK) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST13_MASK (0x2000U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST13_SHIFT (13U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST13_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST13(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST13_SHIFT)) & GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST13_MASK) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST14_MASK (0x4000U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST14_SHIFT (14U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST14_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST14(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST14_SHIFT)) & GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST14_MASK) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST15_MASK (0x8000U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST15_SHIFT (15U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST15_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST15(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST15_SHIFT)) & GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST15_MASK) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST16_MASK (0x10000U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST16_SHIFT (16U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST16_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST16(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST16_SHIFT)) & GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST16_MASK) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST17_MASK (0x20000U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST17_SHIFT (17U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST17_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST17(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST17_SHIFT)) & GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST17_MASK) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST18_MASK (0x40000U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST18_SHIFT (18U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST18_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST18(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST18_SHIFT)) & GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST18_MASK) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST19_MASK (0x80000U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST19_SHIFT (19U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST19_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST19(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST19_SHIFT)) & GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST19_MASK) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST20_MASK (0x100000U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST20_SHIFT (20U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST20_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST20(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST20_SHIFT)) & GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST20_MASK) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST21_MASK (0x200000U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST21_SHIFT (21U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST21_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST21(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST21_SHIFT)) & GTM_gtm_cls0_BRC_SRC_10_DEST_EN_DEST21_MASK) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_TRASHBIN_MASK (0x400000U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_TRASHBIN_SHIFT (22U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_TRASHBIN_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_10_DEST_EN_TRASHBIN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_10_DEST_EN_TRASHBIN_SHIFT)) & GTM_gtm_cls0_BRC_SRC_10_DEST_EN_TRASHBIN_MASK) /*! @} */ /*! @name BRC_SRC_11_ADDR - BRC read address for input channel [x] */ /*! @{ */ #define GTM_gtm_cls0_BRC_SRC_11_ADDR_ADDR_MASK (0x1FFU) #define GTM_gtm_cls0_BRC_SRC_11_ADDR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_BRC_SRC_11_ADDR_ADDR_WIDTH (9U) #define GTM_gtm_cls0_BRC_SRC_11_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_11_ADDR_ADDR_SHIFT)) & GTM_gtm_cls0_BRC_SRC_11_ADDR_ADDR_MASK) #define GTM_gtm_cls0_BRC_SRC_11_ADDR_BRC_MODE_MASK (0x1000U) #define GTM_gtm_cls0_BRC_SRC_11_ADDR_BRC_MODE_SHIFT (12U) #define GTM_gtm_cls0_BRC_SRC_11_ADDR_BRC_MODE_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_11_ADDR_BRC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_11_ADDR_BRC_MODE_SHIFT)) & GTM_gtm_cls0_BRC_SRC_11_ADDR_BRC_MODE_MASK) /*! @} */ /*! @name BRC_SRC_11_DEST - BRC destination channels for input channel [x] */ /*! @{ */ #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST0_MASK (0x1U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST0_SHIFT (0U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST0_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST0_SHIFT)) & GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST0_MASK) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST1_MASK (0x2U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST1_SHIFT (1U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST1_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST1_SHIFT)) & GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST1_MASK) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST2_MASK (0x4U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST2_SHIFT (2U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST2_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST2_SHIFT)) & GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST2_MASK) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST3_MASK (0x8U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST3_SHIFT (3U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST3_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST3_SHIFT)) & GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST3_MASK) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST4_MASK (0x10U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST4_SHIFT (4U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST4_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST4_SHIFT)) & GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST4_MASK) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST5_MASK (0x20U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST5_SHIFT (5U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST5_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST5_SHIFT)) & GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST5_MASK) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST6_MASK (0x40U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST6_SHIFT (6U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST6_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST6_SHIFT)) & GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST6_MASK) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST7_MASK (0x80U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST7_SHIFT (7U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST7_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST7_SHIFT)) & GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST7_MASK) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST8_MASK (0x100U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST8_SHIFT (8U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST8_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST8_SHIFT)) & GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST8_MASK) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST9_MASK (0x200U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST9_SHIFT (9U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST9_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST9_SHIFT)) & GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST9_MASK) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST10_MASK (0x400U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST10_SHIFT (10U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST10_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST10_SHIFT)) & GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST10_MASK) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST11_MASK (0x800U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST11_SHIFT (11U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST11_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST11_SHIFT)) & GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST11_MASK) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST12_MASK (0x1000U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST12_SHIFT (12U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST12_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST12(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST12_SHIFT)) & GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST12_MASK) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST13_MASK (0x2000U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST13_SHIFT (13U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST13_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST13(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST13_SHIFT)) & GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST13_MASK) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST14_MASK (0x4000U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST14_SHIFT (14U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST14_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST14(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST14_SHIFT)) & GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST14_MASK) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST15_MASK (0x8000U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST15_SHIFT (15U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST15_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST15(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST15_SHIFT)) & GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST15_MASK) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST16_MASK (0x10000U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST16_SHIFT (16U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST16_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST16(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST16_SHIFT)) & GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST16_MASK) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST17_MASK (0x20000U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST17_SHIFT (17U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST17_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST17(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST17_SHIFT)) & GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST17_MASK) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST18_MASK (0x40000U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST18_SHIFT (18U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST18_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST18(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST18_SHIFT)) & GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST18_MASK) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST19_MASK (0x80000U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST19_SHIFT (19U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST19_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST19(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST19_SHIFT)) & GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST19_MASK) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST20_MASK (0x100000U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST20_SHIFT (20U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST20_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST20(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST20_SHIFT)) & GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST20_MASK) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST21_MASK (0x200000U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST21_SHIFT (21U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST21_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST21(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST21_SHIFT)) & GTM_gtm_cls0_BRC_SRC_11_DEST_EN_DEST21_MASK) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_TRASHBIN_MASK (0x400000U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_TRASHBIN_SHIFT (22U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_TRASHBIN_WIDTH (1U) #define GTM_gtm_cls0_BRC_SRC_11_DEST_EN_TRASHBIN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_SRC_11_DEST_EN_TRASHBIN_SHIFT)) & GTM_gtm_cls0_BRC_SRC_11_DEST_EN_TRASHBIN_MASK) /*! @} */ /*! @name BRC_IRQ_NOTIFY - BRC interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DEST_ERR_MASK (0x1U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DEST_ERR_SHIFT (0U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DEST_ERR_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DEST_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_NOTIFY_DEST_ERR_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_NOTIFY_DEST_ERR_MASK) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID0_MASK (0x2U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID0_SHIFT (1U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID0_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID0_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID0_MASK) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID1_MASK (0x4U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID1_SHIFT (2U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID1_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID1_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID1_MASK) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID2_MASK (0x8U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID2_SHIFT (3U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID2_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID2_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID2_MASK) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID3_MASK (0x10U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID3_SHIFT (4U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID3_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID3_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID3_MASK) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID4_MASK (0x20U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID4_SHIFT (5U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID4_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID4_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID4_MASK) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID5_MASK (0x40U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID5_SHIFT (6U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID5_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID5_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID5_MASK) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID6_MASK (0x80U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID6_SHIFT (7U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID6_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID6_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID6_MASK) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID7_MASK (0x100U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID7_SHIFT (8U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID7_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID7_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID7_MASK) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID8_MASK (0x200U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID8_SHIFT (9U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID8_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID8_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID8_MASK) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID9_MASK (0x400U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID9_SHIFT (10U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID9_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID9_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID9_MASK) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID10_MASK (0x800U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID10_SHIFT (11U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID10_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID10_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID10_MASK) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID11_MASK (0x1000U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID11_SHIFT (12U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID11_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID11_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_NOTIFY_DID11_MASK) /*! @} */ /*! @name BRC_IRQ_EN - BRC interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_BRC_IRQ_EN_DEST_ERR_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_BRC_IRQ_EN_DEST_ERR_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_BRC_IRQ_EN_DEST_ERR_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_EN_DEST_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_EN_DEST_ERR_IRQ_EN_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_EN_DEST_ERR_IRQ_EN_MASK) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN0_MASK (0x2U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN0_SHIFT (1U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN0_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN0_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN0_MASK) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN1_MASK (0x4U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN1_SHIFT (2U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN1_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN1_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN1_MASK) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN2_MASK (0x8U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN2_SHIFT (3U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN2_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN2_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN2_MASK) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN3_MASK (0x10U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN3_SHIFT (4U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN3_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN3_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN3_MASK) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN4_MASK (0x20U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN4_SHIFT (5U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN4_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN4_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN4_MASK) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN5_MASK (0x40U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN5_SHIFT (6U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN5_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN5_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN5_MASK) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN6_MASK (0x80U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN6_SHIFT (7U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN6_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN6_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN6_MASK) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN7_MASK (0x100U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN7_SHIFT (8U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN7_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN7_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN7_MASK) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN8_MASK (0x200U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN8_SHIFT (9U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN8_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN8_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN8_MASK) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN9_MASK (0x400U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN9_SHIFT (10U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN9_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN9_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN9_MASK) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN10_MASK (0x800U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN10_SHIFT (11U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN10_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN10_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN10_MASK) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN11_MASK (0x1000U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN11_SHIFT (12U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN11_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN11_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_EN_DID_IRQ_EN11_MASK) /*! @} */ /*! @name BRC_IRQ_FORCINT - BRC force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DEST_ERR_MASK (0x1U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DEST_ERR_SHIFT (0U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DEST_ERR_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DEST_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DEST_ERR_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DEST_ERR_MASK) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID0_MASK (0x2U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID0_SHIFT (1U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID0_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID0_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID0_MASK) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID1_MASK (0x4U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID1_SHIFT (2U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID1_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID1_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID1_MASK) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID2_MASK (0x8U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID2_SHIFT (3U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID2_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID2_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID2_MASK) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID3_MASK (0x10U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID3_SHIFT (4U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID3_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID3_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID3_MASK) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID4_MASK (0x20U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID4_SHIFT (5U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID4_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID4_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID4_MASK) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID5_MASK (0x40U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID5_SHIFT (6U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID5_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID5_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID5_MASK) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID6_MASK (0x80U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID6_SHIFT (7U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID6_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID6_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID6_MASK) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID7_MASK (0x100U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID7_SHIFT (8U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID7_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID7_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID7_MASK) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID8_MASK (0x200U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID8_SHIFT (9U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID8_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID8_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID8_MASK) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID9_MASK (0x400U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID9_SHIFT (10U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID9_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID9_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID9_MASK) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID10_MASK (0x800U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID10_SHIFT (11U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID10_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID10_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID10_MASK) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID11_MASK (0x1000U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID11_SHIFT (12U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID11_WIDTH (1U) #define GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID11_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_FORCINT_TRG_DID11_MASK) /*! @} */ /*! @name BRC_IRQ_MODE - BRC interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls0_BRC_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_BRC_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_BRC_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_BRC_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_BRC_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name BRC_RST - BRC software reset register */ /*! @{ */ #define GTM_gtm_cls0_BRC_RST_RST_MASK (0x1U) #define GTM_gtm_cls0_BRC_RST_RST_SHIFT (0U) #define GTM_gtm_cls0_BRC_RST_RST_WIDTH (1U) #define GTM_gtm_cls0_BRC_RST_RST(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_RST_RST_SHIFT)) & GTM_gtm_cls0_BRC_RST_RST_MASK) /*! @} */ /*! @name BRC_EIRQ_EN - BRC error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_BRC_EIRQ_EN_DEST_ERR_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DEST_ERR_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DEST_ERR_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DEST_ERR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_EIRQ_EN_DEST_ERR_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_BRC_EIRQ_EN_DEST_ERR_EIRQ_EN_MASK) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN0_MASK (0x2U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN0_SHIFT (1U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN0_WIDTH (1U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN0_SHIFT)) & GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN0_MASK) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN1_MASK (0x4U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN1_SHIFT (2U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN1_WIDTH (1U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN1_SHIFT)) & GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN1_MASK) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN2_MASK (0x8U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN2_SHIFT (3U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN2_WIDTH (1U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN2_SHIFT)) & GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN2_MASK) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN3_MASK (0x10U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN3_SHIFT (4U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN3_WIDTH (1U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN3_SHIFT)) & GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN3_MASK) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN4_MASK (0x20U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN4_SHIFT (5U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN4_WIDTH (1U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN4_SHIFT)) & GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN4_MASK) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN5_MASK (0x40U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN5_SHIFT (6U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN5_WIDTH (1U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN5_SHIFT)) & GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN5_MASK) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN6_MASK (0x80U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN6_SHIFT (7U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN6_WIDTH (1U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN6_SHIFT)) & GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN6_MASK) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN7_MASK (0x100U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN7_SHIFT (8U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN7_WIDTH (1U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN7_SHIFT)) & GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN7_MASK) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN8_MASK (0x200U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN8_SHIFT (9U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN8_WIDTH (1U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN8_SHIFT)) & GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN8_MASK) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN9_MASK (0x400U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN9_SHIFT (10U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN9_WIDTH (1U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN9_SHIFT)) & GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN9_MASK) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN10_MASK (0x800U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN10_SHIFT (11U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN10_WIDTH (1U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN10_SHIFT)) & GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN10_MASK) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN11_MASK (0x1000U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN11_SHIFT (12U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN11_WIDTH (1U) #define GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN11_SHIFT)) & GTM_gtm_cls0_BRC_EIRQ_EN_DID_EIRQ_EN11_MASK) /*! @} */ /*! @name ICM_IRQG_0 - ICM Interrupt group register covering infrastructural and safety components (ARU, BRC, AEI, PSM0, PSM1, MAP, CMP, SPE) */ /*! @{ */ #define GTM_gtm_cls0_ICM_IRQG_0_ARU_NEW_DATA0_IRQ_MASK (0x1U) #define GTM_gtm_cls0_ICM_IRQG_0_ARU_NEW_DATA0_IRQ_SHIFT (0U) #define GTM_gtm_cls0_ICM_IRQG_0_ARU_NEW_DATA0_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_0_ARU_NEW_DATA0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_0_ARU_NEW_DATA0_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_0_ARU_NEW_DATA0_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_0_ARU_NEW_DATA1_IRQ_MASK (0x2U) #define GTM_gtm_cls0_ICM_IRQG_0_ARU_NEW_DATA1_IRQ_SHIFT (1U) #define GTM_gtm_cls0_ICM_IRQG_0_ARU_NEW_DATA1_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_0_ARU_NEW_DATA1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_0_ARU_NEW_DATA1_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_0_ARU_NEW_DATA1_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_0_ARU_ACC_ACK_IRQ_MASK (0x4U) #define GTM_gtm_cls0_ICM_IRQG_0_ARU_ACC_ACK_IRQ_SHIFT (2U) #define GTM_gtm_cls0_ICM_IRQG_0_ARU_ACC_ACK_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_0_ARU_ACC_ACK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_0_ARU_ACC_ACK_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_0_ARU_ACC_ACK_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_0_BRC_IRQ_MASK (0x8U) #define GTM_gtm_cls0_ICM_IRQG_0_BRC_IRQ_SHIFT (3U) #define GTM_gtm_cls0_ICM_IRQG_0_BRC_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_0_BRC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_0_BRC_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_0_BRC_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_0_AEI_IRQ_MASK (0x10U) #define GTM_gtm_cls0_ICM_IRQG_0_AEI_IRQ_SHIFT (4U) #define GTM_gtm_cls0_ICM_IRQG_0_AEI_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_0_AEI_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_0_AEI_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_0_AEI_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_0_CMP_IRQ_MASK (0x20U) #define GTM_gtm_cls0_ICM_IRQG_0_CMP_IRQ_SHIFT (5U) #define GTM_gtm_cls0_ICM_IRQG_0_CMP_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_0_CMP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_0_CMP_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_0_CMP_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_0_SPE0_IRQ_MASK (0x40U) #define GTM_gtm_cls0_ICM_IRQG_0_SPE0_IRQ_SHIFT (6U) #define GTM_gtm_cls0_ICM_IRQG_0_SPE0_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_0_SPE0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_0_SPE0_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_0_SPE0_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_0_SPE1_IRQ_MASK (0x80U) #define GTM_gtm_cls0_ICM_IRQG_0_SPE1_IRQ_SHIFT (7U) #define GTM_gtm_cls0_ICM_IRQG_0_SPE1_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_0_SPE1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_0_SPE1_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_0_SPE1_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH0_IRQ_MASK (0x10000U) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH0_IRQ_SHIFT (16U) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH0_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH0_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH0_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH1_IRQ_MASK (0x20000U) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH1_IRQ_SHIFT (17U) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH1_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH1_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH1_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH2_IRQ_MASK (0x40000U) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH2_IRQ_SHIFT (18U) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH2_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH2_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH2_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH3_IRQ_MASK (0x80000U) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH3_IRQ_SHIFT (19U) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH3_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH3_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH3_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH4_IRQ_MASK (0x100000U) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH4_IRQ_SHIFT (20U) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH4_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH4_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH4_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH5_IRQ_MASK (0x200000U) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH5_IRQ_SHIFT (21U) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH5_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH5_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH5_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH6_IRQ_MASK (0x400000U) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH6_IRQ_SHIFT (22U) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH6_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH6_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH6_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH7_IRQ_MASK (0x800000U) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH7_IRQ_SHIFT (23U) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH7_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH7_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_0_PSM0_CH7_IRQ_MASK) /*! @} */ /*! @name ICM_IRQG_1 - ICM Interrupt group register covering DPLL */ /*! @{ */ #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_DCGI_IRQ_MASK (0x1U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_DCGI_IRQ_SHIFT (0U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_DCGI_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_DCGI_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_1_DPLL_DCGI_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_1_DPLL_DCGI_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_EDI_IRQ_MASK (0x2U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_EDI_IRQ_SHIFT (1U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_EDI_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_EDI_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_1_DPLL_EDI_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_1_DPLL_EDI_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TINI_IRQ_MASK (0x4U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TINI_IRQ_SHIFT (2U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TINI_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TINI_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_1_DPLL_TINI_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_1_DPLL_TINI_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TAXI_IRQ_MASK (0x8U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TAXI_IRQ_SHIFT (3U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TAXI_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TAXI_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_1_DPLL_TAXI_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_1_DPLL_TAXI_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_SISI_IRQ_MASK (0x10U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_SISI_IRQ_SHIFT (4U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_SISI_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_SISI_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_1_DPLL_SISI_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_1_DPLL_SISI_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TISI_IRQ_MASK (0x20U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TISI_IRQ_SHIFT (5U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TISI_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TISI_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_1_DPLL_TISI_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_1_DPLL_TISI_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_MSI_IRQ_MASK (0x40U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_MSI_IRQ_SHIFT (6U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_MSI_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_MSI_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_1_DPLL_MSI_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_1_DPLL_MSI_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_MTI_IRQ_MASK (0x80U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_MTI_IRQ_SHIFT (7U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_MTI_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_MTI_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_1_DPLL_MTI_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_1_DPLL_MTI_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_SASI_IRQ_MASK (0x100U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_SASI_IRQ_SHIFT (8U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_SASI_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_SASI_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_1_DPLL_SASI_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_1_DPLL_SASI_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TASI_IRQ_MASK (0x200U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TASI_IRQ_SHIFT (9U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TASI_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TASI_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_1_DPLL_TASI_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_1_DPLL_TASI_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_PWI_IRQ_MASK (0x400U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_PWI_IRQ_SHIFT (10U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_PWI_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_PWI_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_1_DPLL_PWI_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_1_DPLL_PWI_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_W2I_IRQ_MASK (0x800U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_W2I_IRQ_SHIFT (11U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_W2I_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_W2I_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_1_DPLL_W2I_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_1_DPLL_W2I_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_W1I_IRQ_MASK (0x1000U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_W1I_IRQ_SHIFT (12U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_W1I_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_W1I_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_1_DPLL_W1I_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_1_DPLL_W1I_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_GL1I_IRQ_MASK (0x2000U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_GL1I_IRQ_SHIFT (13U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_GL1I_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_GL1I_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_1_DPLL_GL1I_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_1_DPLL_GL1I_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_LL1I_IRQ_MASK (0x4000U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_LL1I_IRQ_SHIFT (14U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_LL1I_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_LL1I_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_1_DPLL_LL1I_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_1_DPLL_LL1I_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_EI_IRQ_MASK (0x8000U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_EI_IRQ_SHIFT (15U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_EI_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_EI_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_1_DPLL_EI_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_1_DPLL_EI_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_GL2I_IRQ_MASK (0x10000U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_GL2I_IRQ_SHIFT (16U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_GL2I_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_GL2I_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_1_DPLL_GL2I_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_1_DPLL_GL2I_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_LL2I_IRQ_MASK (0x20000U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_LL2I_IRQ_SHIFT (17U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_LL2I_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_LL2I_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_1_DPLL_LL2I_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_1_DPLL_LL2I_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TE0I_IRQ_MASK (0x40000U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TE0I_IRQ_SHIFT (18U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TE0I_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TE0I_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_1_DPLL_TE0I_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_1_DPLL_TE0I_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TE1I_IRQ_MASK (0x80000U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TE1I_IRQ_SHIFT (19U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TE1I_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TE1I_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_1_DPLL_TE1I_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_1_DPLL_TE1I_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TE2I_IRQ_MASK (0x100000U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TE2I_IRQ_SHIFT (20U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TE2I_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TE2I_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_1_DPLL_TE2I_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_1_DPLL_TE2I_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TE3I_IRQ_MASK (0x200000U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TE3I_IRQ_SHIFT (21U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TE3I_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TE3I_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_1_DPLL_TE3I_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_1_DPLL_TE3I_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TE4I_IRQ_MASK (0x400000U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TE4I_IRQ_SHIFT (22U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TE4I_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TE4I_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_1_DPLL_TE4I_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_1_DPLL_TE4I_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_CDTI_IRQ_MASK (0x800000U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_CDTI_IRQ_SHIFT (23U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_CDTI_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_CDTI_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_1_DPLL_CDTI_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_1_DPLL_CDTI_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_CDSI_IRQ_MASK (0x1000000U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_CDSI_IRQ_SHIFT (24U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_CDSI_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_CDSI_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_1_DPLL_CDSI_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_1_DPLL_CDSI_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TORI_IRQ_MASK (0x2000000U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TORI_IRQ_SHIFT (25U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TORI_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_TORI_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_1_DPLL_TORI_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_1_DPLL_TORI_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_SORI_IRQ_MASK (0x4000000U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_SORI_IRQ_SHIFT (26U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_SORI_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_1_DPLL_SORI_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_1_DPLL_SORI_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_1_DPLL_SORI_IRQ_MASK) /*! @} */ /*! @name ICM_IRQG_2 - ICM Interrupt group register covering TIM0, TIM1, TIM2, TIM3 */ /*! @{ */ #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH0_IRQ_MASK (0x1U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH0_IRQ_SHIFT (0U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH0_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH0_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH0_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH1_IRQ_MASK (0x2U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH1_IRQ_SHIFT (1U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH1_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH1_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH1_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH2_IRQ_MASK (0x4U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH2_IRQ_SHIFT (2U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH2_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH2_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH2_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH3_IRQ_MASK (0x8U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH3_IRQ_SHIFT (3U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH3_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH3_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH3_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH4_IRQ_MASK (0x10U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH4_IRQ_SHIFT (4U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH4_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH4_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH4_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH5_IRQ_MASK (0x20U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH5_IRQ_SHIFT (5U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH5_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH5_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH5_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH6_IRQ_MASK (0x40U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH6_IRQ_SHIFT (6U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH6_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH6_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH6_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH7_IRQ_MASK (0x80U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH7_IRQ_SHIFT (7U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH7_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH7_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_2_TIM0_CH7_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH0_IRQ_MASK (0x100U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH0_IRQ_SHIFT (8U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH0_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH0_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH0_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH1_IRQ_MASK (0x200U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH1_IRQ_SHIFT (9U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH1_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH1_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH1_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH2_IRQ_MASK (0x400U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH2_IRQ_SHIFT (10U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH2_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH2_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH2_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH3_IRQ_MASK (0x800U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH3_IRQ_SHIFT (11U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH3_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH3_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH3_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH4_IRQ_MASK (0x1000U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH4_IRQ_SHIFT (12U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH4_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH4_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH4_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH5_IRQ_MASK (0x2000U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH5_IRQ_SHIFT (13U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH5_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH5_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH5_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH6_IRQ_MASK (0x4000U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH6_IRQ_SHIFT (14U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH6_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH6_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH6_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH7_IRQ_MASK (0x8000U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH7_IRQ_SHIFT (15U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH7_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH7_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_2_TIM1_CH7_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH0_IRQ_MASK (0x10000U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH0_IRQ_SHIFT (16U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH0_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH0_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH0_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH1_IRQ_MASK (0x20000U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH1_IRQ_SHIFT (17U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH1_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH1_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH1_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH2_IRQ_MASK (0x40000U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH2_IRQ_SHIFT (18U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH2_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH2_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH2_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH3_IRQ_MASK (0x80000U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH3_IRQ_SHIFT (19U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH3_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH3_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH3_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH4_IRQ_MASK (0x100000U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH4_IRQ_SHIFT (20U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH4_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH4_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH4_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH5_IRQ_MASK (0x200000U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH5_IRQ_SHIFT (21U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH5_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH5_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH5_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH6_IRQ_MASK (0x400000U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH6_IRQ_SHIFT (22U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH6_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH6_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH6_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH7_IRQ_MASK (0x800000U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH7_IRQ_SHIFT (23U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH7_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH7_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_2_TIM2_CH7_IRQ_MASK) /*! @} */ /*! @name ICM_IRQG_4 - ICM Interrupt group register covering MCS0 to MCS3 submodules */ /*! @{ */ #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH0_IRQ_MASK (0x1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH0_IRQ_SHIFT (0U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH0_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH0_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH0_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH1_IRQ_MASK (0x2U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH1_IRQ_SHIFT (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH1_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH1_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH1_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH2_IRQ_MASK (0x4U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH2_IRQ_SHIFT (2U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH2_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH2_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH2_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH3_IRQ_MASK (0x8U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH3_IRQ_SHIFT (3U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH3_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH3_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH3_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH4_IRQ_MASK (0x10U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH4_IRQ_SHIFT (4U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH4_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH4_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH4_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH5_IRQ_MASK (0x20U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH5_IRQ_SHIFT (5U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH5_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH5_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH5_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH6_IRQ_MASK (0x40U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH6_IRQ_SHIFT (6U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH6_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH6_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH6_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH7_IRQ_MASK (0x80U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH7_IRQ_SHIFT (7U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH7_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH7_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS0_CH7_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH0_IRQ_MASK (0x100U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH0_IRQ_SHIFT (8U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH0_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH0_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH0_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH1_IRQ_MASK (0x200U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH1_IRQ_SHIFT (9U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH1_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH1_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH1_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH2_IRQ_MASK (0x400U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH2_IRQ_SHIFT (10U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH2_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH2_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH2_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH3_IRQ_MASK (0x800U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH3_IRQ_SHIFT (11U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH3_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH3_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH3_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH4_IRQ_MASK (0x1000U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH4_IRQ_SHIFT (12U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH4_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH4_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH4_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH5_IRQ_MASK (0x2000U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH5_IRQ_SHIFT (13U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH5_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH5_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH5_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH6_IRQ_MASK (0x4000U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH6_IRQ_SHIFT (14U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH6_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH6_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH6_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH7_IRQ_MASK (0x8000U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH7_IRQ_SHIFT (15U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH7_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH7_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS1_CH7_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH0_IRQ_MASK (0x10000U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH0_IRQ_SHIFT (16U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH0_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH0_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH0_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH1_IRQ_MASK (0x20000U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH1_IRQ_SHIFT (17U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH1_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH1_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH1_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH2_IRQ_MASK (0x40000U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH2_IRQ_SHIFT (18U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH2_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH2_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH2_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH3_IRQ_MASK (0x80000U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH3_IRQ_SHIFT (19U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH3_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH3_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH3_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH4_IRQ_MASK (0x100000U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH4_IRQ_SHIFT (20U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH4_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH4_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH4_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH5_IRQ_MASK (0x200000U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH5_IRQ_SHIFT (21U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH5_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH5_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH5_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH6_IRQ_MASK (0x400000U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH6_IRQ_SHIFT (22U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH6_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH6_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH6_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH7_IRQ_MASK (0x800000U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH7_IRQ_SHIFT (23U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH7_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH7_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS2_CH7_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH0_IRQ_MASK (0x1000000U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH0_IRQ_SHIFT (24U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH0_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH0_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH0_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH1_IRQ_MASK (0x2000000U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH1_IRQ_SHIFT (25U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH1_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH1_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH1_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH2_IRQ_MASK (0x4000000U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH2_IRQ_SHIFT (26U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH2_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH2_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH2_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH3_IRQ_MASK (0x8000000U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH3_IRQ_SHIFT (27U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH3_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH3_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH3_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH4_IRQ_MASK (0x10000000U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH4_IRQ_SHIFT (28U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH4_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH4_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH4_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH5_IRQ_MASK (0x20000000U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH5_IRQ_SHIFT (29U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH5_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH5_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH5_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH6_IRQ_MASK (0x40000000U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH6_IRQ_SHIFT (30U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH6_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH6_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH6_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH7_IRQ_MASK (0x80000000U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH7_IRQ_SHIFT (31U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH7_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH7_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_4_MCS3_CH7_IRQ_MASK) /*! @} */ /*! @name ICM_IRQG_MEI - ICM Interrupt group register for module error interrupt information */ /*! @{ */ #define GTM_gtm_cls0_ICM_IRQG_MEI_GTM_EIRQ_MASK (0x1U) #define GTM_gtm_cls0_ICM_IRQG_MEI_GTM_EIRQ_SHIFT (0U) #define GTM_gtm_cls0_ICM_IRQG_MEI_GTM_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MEI_GTM_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MEI_GTM_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MEI_GTM_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MEI_BRC_EIRQ_MASK (0x2U) #define GTM_gtm_cls0_ICM_IRQG_MEI_BRC_EIRQ_SHIFT (1U) #define GTM_gtm_cls0_ICM_IRQG_MEI_BRC_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MEI_BRC_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MEI_BRC_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MEI_BRC_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MEI_FIFO0_EIRQ_MASK (0x4U) #define GTM_gtm_cls0_ICM_IRQG_MEI_FIFO0_EIRQ_SHIFT (2U) #define GTM_gtm_cls0_ICM_IRQG_MEI_FIFO0_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MEI_FIFO0_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MEI_FIFO0_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MEI_FIFO0_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MEI_TIM0_EIRQ_MASK (0x10U) #define GTM_gtm_cls0_ICM_IRQG_MEI_TIM0_EIRQ_SHIFT (4U) #define GTM_gtm_cls0_ICM_IRQG_MEI_TIM0_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MEI_TIM0_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MEI_TIM0_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MEI_TIM0_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MEI_TIM1_EIRQ_MASK (0x20U) #define GTM_gtm_cls0_ICM_IRQG_MEI_TIM1_EIRQ_SHIFT (5U) #define GTM_gtm_cls0_ICM_IRQG_MEI_TIM1_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MEI_TIM1_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MEI_TIM1_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MEI_TIM1_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MEI_TIM2_EIRQ_MASK (0x40U) #define GTM_gtm_cls0_ICM_IRQG_MEI_TIM2_EIRQ_SHIFT (6U) #define GTM_gtm_cls0_ICM_IRQG_MEI_TIM2_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MEI_TIM2_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MEI_TIM2_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MEI_TIM2_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MEI_MCS0_EIRQ_MASK (0x1000U) #define GTM_gtm_cls0_ICM_IRQG_MEI_MCS0_EIRQ_SHIFT (12U) #define GTM_gtm_cls0_ICM_IRQG_MEI_MCS0_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MEI_MCS0_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MEI_MCS0_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MEI_MCS0_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MEI_MCS1_EIRQ_MASK (0x2000U) #define GTM_gtm_cls0_ICM_IRQG_MEI_MCS1_EIRQ_SHIFT (13U) #define GTM_gtm_cls0_ICM_IRQG_MEI_MCS1_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MEI_MCS1_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MEI_MCS1_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MEI_MCS1_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MEI_MCS2_EIRQ_MASK (0x4000U) #define GTM_gtm_cls0_ICM_IRQG_MEI_MCS2_EIRQ_SHIFT (14U) #define GTM_gtm_cls0_ICM_IRQG_MEI_MCS2_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MEI_MCS2_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MEI_MCS2_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MEI_MCS2_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MEI_MCS3_EIRQ_MASK (0x8000U) #define GTM_gtm_cls0_ICM_IRQG_MEI_MCS3_EIRQ_SHIFT (15U) #define GTM_gtm_cls0_ICM_IRQG_MEI_MCS3_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MEI_MCS3_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MEI_MCS3_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MEI_MCS3_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MEI_SPE0_EIRQ_MASK (0x100000U) #define GTM_gtm_cls0_ICM_IRQG_MEI_SPE0_EIRQ_SHIFT (20U) #define GTM_gtm_cls0_ICM_IRQG_MEI_SPE0_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MEI_SPE0_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MEI_SPE0_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MEI_SPE0_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MEI_SPE1_EIRQ_MASK (0x200000U) #define GTM_gtm_cls0_ICM_IRQG_MEI_SPE1_EIRQ_SHIFT (21U) #define GTM_gtm_cls0_ICM_IRQG_MEI_SPE1_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MEI_SPE1_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MEI_SPE1_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MEI_SPE1_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MEI_CMP_EIRQ_MASK (0x1000000U) #define GTM_gtm_cls0_ICM_IRQG_MEI_CMP_EIRQ_SHIFT (24U) #define GTM_gtm_cls0_ICM_IRQG_MEI_CMP_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MEI_CMP_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MEI_CMP_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MEI_CMP_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MEI_DPLL_EIRQ_MASK (0x2000000U) #define GTM_gtm_cls0_ICM_IRQG_MEI_DPLL_EIRQ_SHIFT (25U) #define GTM_gtm_cls0_ICM_IRQG_MEI_DPLL_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MEI_DPLL_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MEI_DPLL_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MEI_DPLL_EIRQ_MASK) /*! @} */ /*! @name ICM_IRQG_CEI0 - ICM Interrupt group register 0 for channel error interrupt information */ /*! @{ */ #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH0_EIRQ_MASK (0x1U) #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH0_EIRQ_SHIFT (0U) #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH0_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH0_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH0_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH0_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH1_EIRQ_MASK (0x2U) #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH1_EIRQ_SHIFT (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH1_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH1_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH1_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH1_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH2_EIRQ_MASK (0x4U) #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH2_EIRQ_SHIFT (2U) #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH2_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH2_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH2_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH2_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH3_EIRQ_MASK (0x8U) #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH3_EIRQ_SHIFT (3U) #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH3_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH3_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH3_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH3_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH4_EIRQ_MASK (0x10U) #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH4_EIRQ_SHIFT (4U) #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH4_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH4_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH4_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH4_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH5_EIRQ_MASK (0x20U) #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH5_EIRQ_SHIFT (5U) #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH5_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH5_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH5_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH5_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH6_EIRQ_MASK (0x40U) #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH6_EIRQ_SHIFT (6U) #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH6_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH6_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH6_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH6_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH7_EIRQ_MASK (0x80U) #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH7_EIRQ_SHIFT (7U) #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH7_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH7_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH7_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI0_FIFO0_CH7_EIRQ_MASK) /*! @} */ /*! @name ICM_IRQG_CEI1 - ICM Interrupt group register 1 for channel error interrupt information */ /*! @{ */ #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH0_EIRQ_MASK (0x1U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH0_EIRQ_SHIFT (0U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH0_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH0_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH0_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH0_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH1_EIRQ_MASK (0x2U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH1_EIRQ_SHIFT (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH1_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH1_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH1_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH1_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH2_EIRQ_MASK (0x4U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH2_EIRQ_SHIFT (2U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH2_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH2_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH2_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH2_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH3_EIRQ_MASK (0x8U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH3_EIRQ_SHIFT (3U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH3_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH3_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH3_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH3_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH4_EIRQ_MASK (0x10U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH4_EIRQ_SHIFT (4U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH4_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH4_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH4_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH4_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH5_EIRQ_MASK (0x20U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH5_EIRQ_SHIFT (5U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH5_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH5_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH5_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH5_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH6_EIRQ_MASK (0x40U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH6_EIRQ_SHIFT (6U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH6_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH6_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH6_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH6_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH7_EIRQ_MASK (0x80U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH7_EIRQ_SHIFT (7U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH7_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH7_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH7_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI1_TIM0_CH7_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH0_EIRQ_MASK (0x100U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH0_EIRQ_SHIFT (8U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH0_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH0_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH0_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH0_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH1_EIRQ_MASK (0x200U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH1_EIRQ_SHIFT (9U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH1_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH1_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH1_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH1_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH2_EIRQ_MASK (0x400U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH2_EIRQ_SHIFT (10U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH2_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH2_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH2_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH2_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH3_EIRQ_MASK (0x800U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH3_EIRQ_SHIFT (11U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH3_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH3_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH3_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH3_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH4_EIRQ_MASK (0x1000U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH4_EIRQ_SHIFT (12U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH4_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH4_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH4_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH4_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH5_EIRQ_MASK (0x2000U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH5_EIRQ_SHIFT (13U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH5_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH5_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH5_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH5_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH6_EIRQ_MASK (0x4000U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH6_EIRQ_SHIFT (14U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH6_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH6_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH6_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH6_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH7_EIRQ_MASK (0x8000U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH7_EIRQ_SHIFT (15U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH7_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH7_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH7_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI1_TIM1_CH7_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH0_EIRQ_MASK (0x10000U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH0_EIRQ_SHIFT (16U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH0_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH0_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH0_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH0_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH1_EIRQ_MASK (0x20000U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH1_EIRQ_SHIFT (17U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH1_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH1_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH1_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH1_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH2_EIRQ_MASK (0x40000U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH2_EIRQ_SHIFT (18U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH2_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH2_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH2_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH2_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH3_EIRQ_MASK (0x80000U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH3_EIRQ_SHIFT (19U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH3_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH3_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH3_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH3_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH4_EIRQ_MASK (0x100000U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH4_EIRQ_SHIFT (20U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH4_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH4_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH4_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH4_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH5_EIRQ_MASK (0x200000U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH5_EIRQ_SHIFT (21U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH5_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH5_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH5_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH5_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH6_EIRQ_MASK (0x400000U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH6_EIRQ_SHIFT (22U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH6_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH6_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH6_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH6_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH7_EIRQ_MASK (0x800000U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH7_EIRQ_SHIFT (23U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH7_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH7_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH7_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI1_TIM2_CH7_EIRQ_MASK) /*! @} */ /*! @name ICM_IRQG_CEI3 - ICM Interrupt group register 3 for channel error interrupt information */ /*! @{ */ #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH0_EIRQ_MASK (0x1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH0_EIRQ_SHIFT (0U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH0_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH0_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH0_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH0_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH1_EIRQ_MASK (0x2U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH1_EIRQ_SHIFT (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH1_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH1_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH1_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH1_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH2_EIRQ_MASK (0x4U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH2_EIRQ_SHIFT (2U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH2_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH2_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH2_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH2_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH3_EIRQ_MASK (0x8U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH3_EIRQ_SHIFT (3U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH3_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH3_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH3_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH3_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH4_EIRQ_MASK (0x10U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH4_EIRQ_SHIFT (4U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH4_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH4_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH4_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH4_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH5_EIRQ_MASK (0x20U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH5_EIRQ_SHIFT (5U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH5_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH5_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH5_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH5_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH6_EIRQ_MASK (0x40U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH6_EIRQ_SHIFT (6U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH6_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH6_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH6_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH6_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH7_EIRQ_MASK (0x80U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH7_EIRQ_SHIFT (7U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH7_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH7_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH7_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS0_CH7_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH0_EIRQ_MASK (0x100U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH0_EIRQ_SHIFT (8U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH0_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH0_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH0_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH0_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH1_EIRQ_MASK (0x200U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH1_EIRQ_SHIFT (9U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH1_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH1_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH1_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH1_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH2_EIRQ_MASK (0x400U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH2_EIRQ_SHIFT (10U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH2_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH2_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH2_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH2_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH3_EIRQ_MASK (0x800U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH3_EIRQ_SHIFT (11U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH3_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH3_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH3_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH3_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH4_EIRQ_MASK (0x1000U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH4_EIRQ_SHIFT (12U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH4_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH4_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH4_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH4_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH5_EIRQ_MASK (0x2000U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH5_EIRQ_SHIFT (13U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH5_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH5_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH5_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH5_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH6_EIRQ_MASK (0x4000U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH6_EIRQ_SHIFT (14U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH6_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH6_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH6_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH6_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH7_EIRQ_MASK (0x8000U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH7_EIRQ_SHIFT (15U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH7_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH7_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH7_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS1_CH7_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH0_EIRQ_MASK (0x10000U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH0_EIRQ_SHIFT (16U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH0_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH0_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH0_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH0_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH1_EIRQ_MASK (0x20000U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH1_EIRQ_SHIFT (17U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH1_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH1_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH1_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH1_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH2_EIRQ_MASK (0x40000U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH2_EIRQ_SHIFT (18U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH2_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH2_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH2_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH2_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH3_EIRQ_MASK (0x80000U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH3_EIRQ_SHIFT (19U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH3_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH3_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH3_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH3_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH4_EIRQ_MASK (0x100000U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH4_EIRQ_SHIFT (20U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH4_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH4_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH4_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH4_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH5_EIRQ_MASK (0x200000U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH5_EIRQ_SHIFT (21U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH5_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH5_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH5_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH5_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH6_EIRQ_MASK (0x400000U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH6_EIRQ_SHIFT (22U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH6_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH6_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH6_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH6_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH7_EIRQ_MASK (0x800000U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH7_EIRQ_SHIFT (23U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH7_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH7_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH7_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS2_CH7_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH0_EIRQ_MASK (0x1000000U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH0_EIRQ_SHIFT (24U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH0_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH0_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH0_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH0_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH1_EIRQ_MASK (0x2000000U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH1_EIRQ_SHIFT (25U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH1_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH1_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH1_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH1_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH2_EIRQ_MASK (0x4000000U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH2_EIRQ_SHIFT (26U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH2_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH2_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH2_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH2_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH3_EIRQ_MASK (0x8000000U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH3_EIRQ_SHIFT (27U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH3_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH3_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH3_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH3_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH4_EIRQ_MASK (0x10000000U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH4_EIRQ_SHIFT (28U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH4_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH4_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH4_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH4_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH5_EIRQ_MASK (0x20000000U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH5_EIRQ_SHIFT (29U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH5_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH5_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH5_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH5_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH6_EIRQ_MASK (0x40000000U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH6_EIRQ_SHIFT (30U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH6_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH6_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH6_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH6_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH7_EIRQ_MASK (0x80000000U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH7_EIRQ_SHIFT (31U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH7_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH7_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH7_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CEI3_MCS3_CH7_EIRQ_MASK) /*! @} */ /*! @name ICM_IRQG_MCS0_CEI - ICM Interrupt group MCS[j] for Channel Error Interrupt information */ /*! @{ */ #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH0_EIRQ_MASK (0x1U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH0_EIRQ_SHIFT (0U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH0_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH0_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH0_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH0_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH1_EIRQ_MASK (0x2U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH1_EIRQ_SHIFT (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH1_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH1_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH1_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH1_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH2_EIRQ_MASK (0x4U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH2_EIRQ_SHIFT (2U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH2_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH2_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH2_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH2_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH3_EIRQ_MASK (0x8U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH3_EIRQ_SHIFT (3U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH3_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH3_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH3_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH3_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH4_EIRQ_MASK (0x10U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH4_EIRQ_SHIFT (4U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH4_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH4_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH4_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH4_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH5_EIRQ_MASK (0x20U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH5_EIRQ_SHIFT (5U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH5_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH5_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH5_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH5_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH6_EIRQ_MASK (0x40U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH6_EIRQ_SHIFT (6U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH6_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH6_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH6_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH6_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH7_EIRQ_MASK (0x80U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH7_EIRQ_SHIFT (7U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH7_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH7_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH7_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS0_CEI_MCS_CH7_EIRQ_MASK) /*! @} */ /*! @name ICM_IRQG_MCS1_CEI - ICM Interrupt group MCS[j] for Channel Error Interrupt information */ /*! @{ */ #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH0_EIRQ_MASK (0x1U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH0_EIRQ_SHIFT (0U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH0_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH0_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH0_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH0_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH1_EIRQ_MASK (0x2U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH1_EIRQ_SHIFT (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH1_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH1_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH1_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH1_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH2_EIRQ_MASK (0x4U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH2_EIRQ_SHIFT (2U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH2_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH2_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH2_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH2_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH3_EIRQ_MASK (0x8U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH3_EIRQ_SHIFT (3U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH3_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH3_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH3_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH3_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH4_EIRQ_MASK (0x10U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH4_EIRQ_SHIFT (4U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH4_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH4_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH4_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH4_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH5_EIRQ_MASK (0x20U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH5_EIRQ_SHIFT (5U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH5_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH5_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH5_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH5_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH6_EIRQ_MASK (0x40U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH6_EIRQ_SHIFT (6U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH6_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH6_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH6_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH6_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH7_EIRQ_MASK (0x80U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH7_EIRQ_SHIFT (7U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH7_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH7_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH7_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS1_CEI_MCS_CH7_EIRQ_MASK) /*! @} */ /*! @name ICM_IRQG_MCS2_CEI - ICM Interrupt group MCS[j] for Channel Error Interrupt information */ /*! @{ */ #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH0_EIRQ_MASK (0x1U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH0_EIRQ_SHIFT (0U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH0_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH0_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH0_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH0_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH1_EIRQ_MASK (0x2U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH1_EIRQ_SHIFT (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH1_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH1_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH1_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH1_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH2_EIRQ_MASK (0x4U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH2_EIRQ_SHIFT (2U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH2_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH2_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH2_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH2_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH3_EIRQ_MASK (0x8U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH3_EIRQ_SHIFT (3U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH3_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH3_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH3_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH3_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH4_EIRQ_MASK (0x10U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH4_EIRQ_SHIFT (4U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH4_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH4_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH4_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH4_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH5_EIRQ_MASK (0x20U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH5_EIRQ_SHIFT (5U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH5_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH5_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH5_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH5_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH6_EIRQ_MASK (0x40U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH6_EIRQ_SHIFT (6U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH6_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH6_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH6_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH6_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH7_EIRQ_MASK (0x80U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH7_EIRQ_SHIFT (7U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH7_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH7_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH7_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS2_CEI_MCS_CH7_EIRQ_MASK) /*! @} */ /*! @name ICM_IRQG_MCS3_CEI - ICM Interrupt group MCS[j] for Channel Error Interrupt information */ /*! @{ */ #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH0_EIRQ_MASK (0x1U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH0_EIRQ_SHIFT (0U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH0_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH0_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH0_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH0_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH1_EIRQ_MASK (0x2U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH1_EIRQ_SHIFT (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH1_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH1_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH1_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH1_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH2_EIRQ_MASK (0x4U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH2_EIRQ_SHIFT (2U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH2_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH2_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH2_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH2_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH3_EIRQ_MASK (0x8U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH3_EIRQ_SHIFT (3U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH3_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH3_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH3_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH3_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH4_EIRQ_MASK (0x10U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH4_EIRQ_SHIFT (4U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH4_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH4_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH4_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH4_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH5_EIRQ_MASK (0x20U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH5_EIRQ_SHIFT (5U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH5_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH5_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH5_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH5_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH6_EIRQ_MASK (0x40U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH6_EIRQ_SHIFT (6U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH6_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH6_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH6_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH6_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH7_EIRQ_MASK (0x80U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH7_EIRQ_SHIFT (7U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH7_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH7_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH7_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS3_CEI_MCS_CH7_EIRQ_MASK) /*! @} */ /*! @name ICM_IRQG_PSM_0_CEI - ICM Interrupt group PSM 0 for Channel Error Interrupt information of FIFO0, FIFO1, FIFO2 */ /*! @{ */ #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH0_EIRQ_MASK (0x1U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH0_EIRQ_SHIFT (0U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH0_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH0_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH0_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH0_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH1_EIRQ_MASK (0x2U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH1_EIRQ_SHIFT (1U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH1_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH1_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH1_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH1_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH2_EIRQ_MASK (0x4U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH2_EIRQ_SHIFT (2U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH2_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH2_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH2_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH2_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH3_EIRQ_MASK (0x8U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH3_EIRQ_SHIFT (3U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH3_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH3_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH3_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH3_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH4_EIRQ_MASK (0x10U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH4_EIRQ_SHIFT (4U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH4_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH4_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH4_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH4_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH5_EIRQ_MASK (0x20U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH5_EIRQ_SHIFT (5U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH5_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH5_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH5_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH5_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH6_EIRQ_MASK (0x40U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH6_EIRQ_SHIFT (6U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH6_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH6_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH6_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH6_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH7_EIRQ_MASK (0x80U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH7_EIRQ_SHIFT (7U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH7_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH7_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH7_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_PSM_0_CEI_PSM_M0_CH7_EIRQ_MASK) /*! @} */ /*! @name ICM_IRQG_SPE_CEI - ICM Interrupt group SPE for module Error Interrupt information */ /*! @{ */ #define GTM_gtm_cls0_ICM_IRQG_SPE_CEI_SPE0_EIRQ_MASK (0x1U) #define GTM_gtm_cls0_ICM_IRQG_SPE_CEI_SPE0_EIRQ_SHIFT (0U) #define GTM_gtm_cls0_ICM_IRQG_SPE_CEI_SPE0_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_SPE_CEI_SPE0_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_SPE_CEI_SPE0_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_SPE_CEI_SPE0_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_SPE_CEI_SPE1_EIRQ_MASK (0x2U) #define GTM_gtm_cls0_ICM_IRQG_SPE_CEI_SPE1_EIRQ_SHIFT (1U) #define GTM_gtm_cls0_ICM_IRQG_SPE_CEI_SPE1_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_SPE_CEI_SPE1_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_SPE_CEI_SPE1_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_SPE_CEI_SPE1_EIRQ_MASK) /*! @} */ /*! @name ICM_IRQG_CLS_0_MEI - ICM Interrupt group for module Error Interrupt information for each TIM[j], MCS[j], SPE[j], FIFO[j] (j=4*[g]+k, k∈{0, ... ,3}) */ /*! @{ */ #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_TIM_M0_EIRQ_MASK (0x1U) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_TIM_M0_EIRQ_SHIFT (0U) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_TIM_M0_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_TIM_M0_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_TIM_M0_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_TIM_M0_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_MCS_M0_EIRQ_MASK (0x2U) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_MCS_M0_EIRQ_SHIFT (1U) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_MCS_M0_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_MCS_M0_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_MCS_M0_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_MCS_M0_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_SPE_M0_EIRQ_MASK (0x4U) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_SPE_M0_EIRQ_SHIFT (2U) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_SPE_M0_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_SPE_M0_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_SPE_M0_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_SPE_M0_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_FIFO_M0_EIRQ_MASK (0x8U) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_FIFO_M0_EIRQ_SHIFT (3U) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_FIFO_M0_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_FIFO_M0_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_FIFO_M0_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_FIFO_M0_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_TIM_M1_EIRQ_MASK (0x100U) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_TIM_M1_EIRQ_SHIFT (8U) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_TIM_M1_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_TIM_M1_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_TIM_M1_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_TIM_M1_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_MCS_M1_EIRQ_MASK (0x200U) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_MCS_M1_EIRQ_SHIFT (9U) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_MCS_M1_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_MCS_M1_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_MCS_M1_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_MCS_M1_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_SPE_M1_EIRQ_MASK (0x400U) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_SPE_M1_EIRQ_SHIFT (10U) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_SPE_M1_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_SPE_M1_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_SPE_M1_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_SPE_M1_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_TIM_M2_EIRQ_MASK (0x10000U) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_TIM_M2_EIRQ_SHIFT (16U) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_TIM_M2_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_TIM_M2_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_TIM_M2_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_TIM_M2_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_MCS_M2_EIRQ_MASK (0x20000U) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_MCS_M2_EIRQ_SHIFT (17U) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_MCS_M2_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_MCS_M2_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_MCS_M2_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_MCS_M2_EIRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_MCS_M3_EIRQ_MASK (0x2000000U) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_MCS_M3_EIRQ_SHIFT (25U) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_MCS_M3_EIRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_MCS_M3_EIRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_MCS_M3_EIRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_CLS_0_MEI_MCS_M3_EIRQ_MASK) /*! @} */ /*! @name ICM_IRQG_MCS0_CI - ICM Interrupt group MCS[j] for Channel Interrupt information */ /*! @{ */ #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH0_IRQ_MASK (0x1U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH0_IRQ_SHIFT (0U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH0_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH0_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH0_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH1_IRQ_MASK (0x2U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH1_IRQ_SHIFT (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH1_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH1_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH1_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH2_IRQ_MASK (0x4U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH2_IRQ_SHIFT (2U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH2_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH2_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH2_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH3_IRQ_MASK (0x8U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH3_IRQ_SHIFT (3U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH3_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH3_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH3_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH4_IRQ_MASK (0x10U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH4_IRQ_SHIFT (4U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH4_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH4_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH4_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH5_IRQ_MASK (0x20U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH5_IRQ_SHIFT (5U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH5_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH5_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH5_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH6_IRQ_MASK (0x40U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH6_IRQ_SHIFT (6U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH6_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH6_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH6_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH7_IRQ_MASK (0x80U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH7_IRQ_SHIFT (7U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH7_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH7_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS0_CI_MCS_CH7_IRQ_MASK) /*! @} */ /*! @name ICM_IRQG_MCS1_CI - ICM Interrupt group MCS[j] for Channel Interrupt information */ /*! @{ */ #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH0_IRQ_MASK (0x1U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH0_IRQ_SHIFT (0U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH0_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH0_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH0_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH1_IRQ_MASK (0x2U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH1_IRQ_SHIFT (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH1_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH1_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH1_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH2_IRQ_MASK (0x4U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH2_IRQ_SHIFT (2U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH2_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH2_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH2_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH3_IRQ_MASK (0x8U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH3_IRQ_SHIFT (3U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH3_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH3_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH3_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH4_IRQ_MASK (0x10U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH4_IRQ_SHIFT (4U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH4_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH4_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH4_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH5_IRQ_MASK (0x20U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH5_IRQ_SHIFT (5U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH5_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH5_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH5_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH6_IRQ_MASK (0x40U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH6_IRQ_SHIFT (6U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH6_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH6_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH6_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH7_IRQ_MASK (0x80U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH7_IRQ_SHIFT (7U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH7_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH7_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS1_CI_MCS_CH7_IRQ_MASK) /*! @} */ /*! @name ICM_IRQG_MCS2_CI - ICM Interrupt group MCS[j] for Channel Interrupt information */ /*! @{ */ #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH0_IRQ_MASK (0x1U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH0_IRQ_SHIFT (0U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH0_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH0_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH0_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH1_IRQ_MASK (0x2U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH1_IRQ_SHIFT (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH1_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH1_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH1_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH2_IRQ_MASK (0x4U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH2_IRQ_SHIFT (2U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH2_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH2_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH2_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH3_IRQ_MASK (0x8U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH3_IRQ_SHIFT (3U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH3_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH3_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH3_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH4_IRQ_MASK (0x10U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH4_IRQ_SHIFT (4U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH4_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH4_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH4_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH5_IRQ_MASK (0x20U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH5_IRQ_SHIFT (5U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH5_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH5_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH5_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH6_IRQ_MASK (0x40U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH6_IRQ_SHIFT (6U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH6_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH6_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH6_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH7_IRQ_MASK (0x80U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH7_IRQ_SHIFT (7U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH7_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH7_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS2_CI_MCS_CH7_IRQ_MASK) /*! @} */ /*! @name ICM_IRQG_MCS3_CI - ICM Interrupt group MCS[j] for Channel Interrupt information */ /*! @{ */ #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH0_IRQ_MASK (0x1U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH0_IRQ_SHIFT (0U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH0_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH0_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH0_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH1_IRQ_MASK (0x2U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH1_IRQ_SHIFT (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH1_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH1_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH1_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH2_IRQ_MASK (0x4U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH2_IRQ_SHIFT (2U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH2_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH2_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH2_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH3_IRQ_MASK (0x8U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH3_IRQ_SHIFT (3U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH3_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH3_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH3_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH4_IRQ_MASK (0x10U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH4_IRQ_SHIFT (4U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH4_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH4_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH4_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH5_IRQ_MASK (0x20U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH5_IRQ_SHIFT (5U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH5_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH5_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH5_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH6_IRQ_MASK (0x40U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH6_IRQ_SHIFT (6U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH6_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH6_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH6_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH7_IRQ_MASK (0x80U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH7_IRQ_SHIFT (7U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH7_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH7_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_MCS3_CI_MCS_CH7_IRQ_MASK) /*! @} */ /*! @name ICM_IRQG_PSM_0_CI - ICM Interrupt group PSM 0 for Channel Interrupt information of FIFO0, FIFO1, FIFO2 */ /*! @{ */ #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH0_IRQ_MASK (0x1U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH0_IRQ_SHIFT (0U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH0_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH0_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH0_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH1_IRQ_MASK (0x2U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH1_IRQ_SHIFT (1U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH1_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH1_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH1_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH2_IRQ_MASK (0x4U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH2_IRQ_SHIFT (2U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH2_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH2_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH2_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH3_IRQ_MASK (0x8U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH3_IRQ_SHIFT (3U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH3_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH3_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH3_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH4_IRQ_MASK (0x10U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH4_IRQ_SHIFT (4U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH4_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH4_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH4_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH5_IRQ_MASK (0x20U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH5_IRQ_SHIFT (5U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH5_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH5_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH5_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH6_IRQ_MASK (0x40U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH6_IRQ_SHIFT (6U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH6_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH6_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH6_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH7_IRQ_MASK (0x80U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH7_IRQ_SHIFT (7U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH7_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH7_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_PSM_0_CI_PSM_M0_CH7_IRQ_MASK) /*! @} */ /*! @name ICM_IRQG_SPE_CI - ICM Interrupt group SPE for module Interrupt information */ /*! @{ */ #define GTM_gtm_cls0_ICM_IRQG_SPE_CI_SPE0_IRQ_MASK (0x1U) #define GTM_gtm_cls0_ICM_IRQG_SPE_CI_SPE0_IRQ_SHIFT (0U) #define GTM_gtm_cls0_ICM_IRQG_SPE_CI_SPE0_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_SPE_CI_SPE0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_SPE_CI_SPE0_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_SPE_CI_SPE0_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_SPE_CI_SPE1_IRQ_MASK (0x2U) #define GTM_gtm_cls0_ICM_IRQG_SPE_CI_SPE1_IRQ_SHIFT (1U) #define GTM_gtm_cls0_ICM_IRQG_SPE_CI_SPE1_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_SPE_CI_SPE1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_SPE_CI_SPE1_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_SPE_CI_SPE1_IRQ_MASK) /*! @} */ /*! @name ICM_IRQG_ATOM_0_CI - ICM Interrupt group ATOM [g] for Channel Interrupt information of ATOM[j] (m=4*[g]+(0..3)) */ /*! @{ */ #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH0_IRQ_MASK (0x1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH0_IRQ_SHIFT (0U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH0_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH0_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH0_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH1_IRQ_MASK (0x2U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH1_IRQ_SHIFT (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH1_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH1_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH1_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH2_IRQ_MASK (0x4U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH2_IRQ_SHIFT (2U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH2_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH2_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH2_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH3_IRQ_MASK (0x8U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH3_IRQ_SHIFT (3U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH3_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH3_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH3_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH4_IRQ_MASK (0x10U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH4_IRQ_SHIFT (4U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH4_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH4_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH4_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH5_IRQ_MASK (0x20U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH5_IRQ_SHIFT (5U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH5_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH5_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH5_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH6_IRQ_MASK (0x40U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH6_IRQ_SHIFT (6U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH6_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH6_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH6_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH7_IRQ_MASK (0x80U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH7_IRQ_SHIFT (7U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH7_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH7_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M0_CH7_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH0_IRQ_MASK (0x100U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH0_IRQ_SHIFT (8U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH0_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH0_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH0_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH1_IRQ_MASK (0x200U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH1_IRQ_SHIFT (9U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH1_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH1_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH1_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH2_IRQ_MASK (0x400U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH2_IRQ_SHIFT (10U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH2_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH2_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH2_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH3_IRQ_MASK (0x800U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH3_IRQ_SHIFT (11U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH3_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH3_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH3_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH4_IRQ_MASK (0x1000U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH4_IRQ_SHIFT (12U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH4_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH4_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH4_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH5_IRQ_MASK (0x2000U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH5_IRQ_SHIFT (13U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH5_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH5_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH5_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH6_IRQ_MASK (0x4000U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH6_IRQ_SHIFT (14U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH6_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH6_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH6_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH7_IRQ_MASK (0x8000U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH7_IRQ_SHIFT (15U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH7_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH7_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M1_CH7_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH0_IRQ_MASK (0x10000U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH0_IRQ_SHIFT (16U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH0_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH0_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH0_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH1_IRQ_MASK (0x20000U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH1_IRQ_SHIFT (17U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH1_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH1_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH1_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH2_IRQ_MASK (0x40000U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH2_IRQ_SHIFT (18U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH2_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH2_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH2_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH3_IRQ_MASK (0x80000U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH3_IRQ_SHIFT (19U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH3_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH3_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH3_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH4_IRQ_MASK (0x100000U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH4_IRQ_SHIFT (20U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH4_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH4_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH4_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH5_IRQ_MASK (0x200000U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH5_IRQ_SHIFT (21U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH5_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH5_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH5_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH6_IRQ_MASK (0x400000U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH6_IRQ_SHIFT (22U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH6_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH6_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH6_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH7_IRQ_MASK (0x800000U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH7_IRQ_SHIFT (23U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH7_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH7_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M2_CH7_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH0_IRQ_MASK (0x1000000U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH0_IRQ_SHIFT (24U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH0_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH0_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH0_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH1_IRQ_MASK (0x2000000U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH1_IRQ_SHIFT (25U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH1_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH1_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH1_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH2_IRQ_MASK (0x4000000U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH2_IRQ_SHIFT (26U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH2_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH2_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH2_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH3_IRQ_MASK (0x8000000U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH3_IRQ_SHIFT (27U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH3_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH3_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH3_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH4_IRQ_MASK (0x10000000U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH4_IRQ_SHIFT (28U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH4_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH4_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH4_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH5_IRQ_MASK (0x20000000U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH5_IRQ_SHIFT (29U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH5_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH5_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH5_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH6_IRQ_MASK (0x40000000U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH6_IRQ_SHIFT (30U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH6_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH6_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH6_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH7_IRQ_MASK (0x80000000U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH7_IRQ_SHIFT (31U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH7_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH7_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_ATOM_0_CI_ATOM_M3_CH7_IRQ_MASK) /*! @} */ /*! @name ICM_IRQG_TOM_0_CI - ICM Interrupt group TOM [g] for Channel Interrupt information of TOMm ([j]=2*[g]+(0..1)) */ /*! @{ */ #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH0_IRQ_MASK (0x1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH0_IRQ_SHIFT (0U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH0_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH0_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH0_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH1_IRQ_MASK (0x2U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH1_IRQ_SHIFT (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH1_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH1_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH1_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH2_IRQ_MASK (0x4U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH2_IRQ_SHIFT (2U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH2_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH2_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH2_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH3_IRQ_MASK (0x8U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH3_IRQ_SHIFT (3U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH3_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH3_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH3_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH4_IRQ_MASK (0x10U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH4_IRQ_SHIFT (4U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH4_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH4_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH4_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH5_IRQ_MASK (0x20U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH5_IRQ_SHIFT (5U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH5_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH5_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH5_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH6_IRQ_MASK (0x40U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH6_IRQ_SHIFT (6U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH6_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH6_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH6_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH7_IRQ_MASK (0x80U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH7_IRQ_SHIFT (7U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH7_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH7_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH7_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH8_IRQ_MASK (0x100U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH8_IRQ_SHIFT (8U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH8_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH8_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH8_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH8_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH9_IRQ_MASK (0x200U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH9_IRQ_SHIFT (9U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH9_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH9_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH9_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH9_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH10_IRQ_MASK (0x400U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH10_IRQ_SHIFT (10U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH10_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH10_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH10_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH10_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH11_IRQ_MASK (0x800U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH11_IRQ_SHIFT (11U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH11_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH11_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH11_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH11_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH12_IRQ_MASK (0x1000U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH12_IRQ_SHIFT (12U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH12_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH12_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH12_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH12_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH13_IRQ_MASK (0x2000U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH13_IRQ_SHIFT (13U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH13_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH13_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH13_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH13_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH14_IRQ_MASK (0x4000U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH14_IRQ_SHIFT (14U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH14_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH14_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH14_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH14_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH15_IRQ_MASK (0x8000U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH15_IRQ_SHIFT (15U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH15_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH15_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH15_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M0_CH15_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH0_IRQ_MASK (0x10000U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH0_IRQ_SHIFT (16U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH0_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH0_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH0_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH1_IRQ_MASK (0x20000U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH1_IRQ_SHIFT (17U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH1_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH1_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH1_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH2_IRQ_MASK (0x40000U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH2_IRQ_SHIFT (18U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH2_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH2_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH2_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH3_IRQ_MASK (0x80000U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH3_IRQ_SHIFT (19U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH3_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH3_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH3_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH4_IRQ_MASK (0x100000U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH4_IRQ_SHIFT (20U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH4_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH4_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH4_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH5_IRQ_MASK (0x200000U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH5_IRQ_SHIFT (21U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH5_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH5_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH5_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH6_IRQ_MASK (0x400000U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH6_IRQ_SHIFT (22U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH6_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH6_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH6_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH7_IRQ_MASK (0x800000U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH7_IRQ_SHIFT (23U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH7_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH7_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH7_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH8_IRQ_MASK (0x1000000U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH8_IRQ_SHIFT (24U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH8_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH8_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH8_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH8_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH9_IRQ_MASK (0x2000000U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH9_IRQ_SHIFT (25U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH9_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH9_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH9_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH9_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH10_IRQ_MASK (0x4000000U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH10_IRQ_SHIFT (26U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH10_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH10_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH10_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH10_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH11_IRQ_MASK (0x8000000U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH11_IRQ_SHIFT (27U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH11_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH11_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH11_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH11_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH12_IRQ_MASK (0x10000000U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH12_IRQ_SHIFT (28U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH12_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH12_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH12_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH12_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH13_IRQ_MASK (0x20000000U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH13_IRQ_SHIFT (29U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH13_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH13_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH13_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH13_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH14_IRQ_MASK (0x40000000U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH14_IRQ_SHIFT (30U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH14_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH14_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH14_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH14_IRQ_MASK) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH15_IRQ_MASK (0x80000000U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH15_IRQ_SHIFT (31U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH15_IRQ_WIDTH (1U) #define GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH15_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH15_IRQ_SHIFT)) & GTM_gtm_cls0_ICM_IRQG_TOM_0_CI_TOM_M1_CH15_IRQ_MASK) /*! @} */ /*! @name MAP_CTRL - MAP Control register */ /*! @{ */ #define GTM_gtm_cls0_MAP_CTRL_TSEL_MASK (0x1U) #define GTM_gtm_cls0_MAP_CTRL_TSEL_SHIFT (0U) #define GTM_gtm_cls0_MAP_CTRL_TSEL_WIDTH (1U) #define GTM_gtm_cls0_MAP_CTRL_TSEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MAP_CTRL_TSEL_SHIFT)) & GTM_gtm_cls0_MAP_CTRL_TSEL_MASK) #define GTM_gtm_cls0_MAP_CTRL_SSL_MASK (0xEU) #define GTM_gtm_cls0_MAP_CTRL_SSL_SHIFT (1U) #define GTM_gtm_cls0_MAP_CTRL_SSL_WIDTH (3U) #define GTM_gtm_cls0_MAP_CTRL_SSL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MAP_CTRL_SSL_SHIFT)) & GTM_gtm_cls0_MAP_CTRL_SSL_MASK) #define GTM_gtm_cls0_MAP_CTRL_LSEL_MASK (0x10U) #define GTM_gtm_cls0_MAP_CTRL_LSEL_SHIFT (4U) #define GTM_gtm_cls0_MAP_CTRL_LSEL_WIDTH (1U) #define GTM_gtm_cls0_MAP_CTRL_LSEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MAP_CTRL_LSEL_SHIFT)) & GTM_gtm_cls0_MAP_CTRL_LSEL_MASK) #define GTM_gtm_cls0_MAP_CTRL_TSPP0_EN_MASK (0x10000U) #define GTM_gtm_cls0_MAP_CTRL_TSPP0_EN_SHIFT (16U) #define GTM_gtm_cls0_MAP_CTRL_TSPP0_EN_WIDTH (1U) #define GTM_gtm_cls0_MAP_CTRL_TSPP0_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MAP_CTRL_TSPP0_EN_SHIFT)) & GTM_gtm_cls0_MAP_CTRL_TSPP0_EN_MASK) #define GTM_gtm_cls0_MAP_CTRL_TSPP0_DLD_MASK (0x20000U) #define GTM_gtm_cls0_MAP_CTRL_TSPP0_DLD_SHIFT (17U) #define GTM_gtm_cls0_MAP_CTRL_TSPP0_DLD_WIDTH (1U) #define GTM_gtm_cls0_MAP_CTRL_TSPP0_DLD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MAP_CTRL_TSPP0_DLD_SHIFT)) & GTM_gtm_cls0_MAP_CTRL_TSPP0_DLD_MASK) #define GTM_gtm_cls0_MAP_CTRL_TSPP0_I0V_MASK (0x100000U) #define GTM_gtm_cls0_MAP_CTRL_TSPP0_I0V_SHIFT (20U) #define GTM_gtm_cls0_MAP_CTRL_TSPP0_I0V_WIDTH (1U) #define GTM_gtm_cls0_MAP_CTRL_TSPP0_I0V(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MAP_CTRL_TSPP0_I0V_SHIFT)) & GTM_gtm_cls0_MAP_CTRL_TSPP0_I0V_MASK) #define GTM_gtm_cls0_MAP_CTRL_TSPP0_I1V_MASK (0x200000U) #define GTM_gtm_cls0_MAP_CTRL_TSPP0_I1V_SHIFT (21U) #define GTM_gtm_cls0_MAP_CTRL_TSPP0_I1V_WIDTH (1U) #define GTM_gtm_cls0_MAP_CTRL_TSPP0_I1V(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MAP_CTRL_TSPP0_I1V_SHIFT)) & GTM_gtm_cls0_MAP_CTRL_TSPP0_I1V_MASK) #define GTM_gtm_cls0_MAP_CTRL_TSPP0_I2V_MASK (0x400000U) #define GTM_gtm_cls0_MAP_CTRL_TSPP0_I2V_SHIFT (22U) #define GTM_gtm_cls0_MAP_CTRL_TSPP0_I2V_WIDTH (1U) #define GTM_gtm_cls0_MAP_CTRL_TSPP0_I2V(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MAP_CTRL_TSPP0_I2V_SHIFT)) & GTM_gtm_cls0_MAP_CTRL_TSPP0_I2V_MASK) #define GTM_gtm_cls0_MAP_CTRL_TSPP1_EN_MASK (0x1000000U) #define GTM_gtm_cls0_MAP_CTRL_TSPP1_EN_SHIFT (24U) #define GTM_gtm_cls0_MAP_CTRL_TSPP1_EN_WIDTH (1U) #define GTM_gtm_cls0_MAP_CTRL_TSPP1_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MAP_CTRL_TSPP1_EN_SHIFT)) & GTM_gtm_cls0_MAP_CTRL_TSPP1_EN_MASK) #define GTM_gtm_cls0_MAP_CTRL_TSPP1_DLD_MASK (0x2000000U) #define GTM_gtm_cls0_MAP_CTRL_TSPP1_DLD_SHIFT (25U) #define GTM_gtm_cls0_MAP_CTRL_TSPP1_DLD_WIDTH (1U) #define GTM_gtm_cls0_MAP_CTRL_TSPP1_DLD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MAP_CTRL_TSPP1_DLD_SHIFT)) & GTM_gtm_cls0_MAP_CTRL_TSPP1_DLD_MASK) #define GTM_gtm_cls0_MAP_CTRL_TSPP1_I0V_MASK (0x10000000U) #define GTM_gtm_cls0_MAP_CTRL_TSPP1_I0V_SHIFT (28U) #define GTM_gtm_cls0_MAP_CTRL_TSPP1_I0V_WIDTH (1U) #define GTM_gtm_cls0_MAP_CTRL_TSPP1_I0V(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MAP_CTRL_TSPP1_I0V_SHIFT)) & GTM_gtm_cls0_MAP_CTRL_TSPP1_I0V_MASK) #define GTM_gtm_cls0_MAP_CTRL_TSPP1_I1V_MASK (0x20000000U) #define GTM_gtm_cls0_MAP_CTRL_TSPP1_I1V_SHIFT (29U) #define GTM_gtm_cls0_MAP_CTRL_TSPP1_I1V_WIDTH (1U) #define GTM_gtm_cls0_MAP_CTRL_TSPP1_I1V(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MAP_CTRL_TSPP1_I1V_SHIFT)) & GTM_gtm_cls0_MAP_CTRL_TSPP1_I1V_MASK) #define GTM_gtm_cls0_MAP_CTRL_TSPP1_I2V_MASK (0x40000000U) #define GTM_gtm_cls0_MAP_CTRL_TSPP1_I2V_SHIFT (30U) #define GTM_gtm_cls0_MAP_CTRL_TSPP1_I2V_WIDTH (1U) #define GTM_gtm_cls0_MAP_CTRL_TSPP1_I2V(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MAP_CTRL_TSPP1_I2V_SHIFT)) & GTM_gtm_cls0_MAP_CTRL_TSPP1_I2V_MASK) /*! @} */ /*! @name TIM0_CH0_GPR0 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH0_GPR0_GPR0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH0_GPR0_GPR0_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH0_GPR0_GPR0_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH0_GPR0_GPR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_GPR0_GPR0_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_GPR0_GPR0_MASK) #define GTM_gtm_cls0_TIM0_CH0_GPR0_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls0_TIM0_CH0_GPR0_ECNT_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH0_GPR0_ECNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH0_GPR0_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_GPR0_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_GPR0_ECNT_MASK) /*! @} */ /*! @name TIM0_CH0_GPR1 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH0_GPR1_GPR1_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH0_GPR1_GPR1_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH0_GPR1_GPR1_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH0_GPR1_GPR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_GPR1_GPR1_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_GPR1_GPR1_MASK) #define GTM_gtm_cls0_TIM0_CH0_GPR1_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls0_TIM0_CH0_GPR1_ECNT_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH0_GPR1_ECNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH0_GPR1_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_GPR1_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_GPR1_ECNT_MASK) /*! @} */ /*! @name TIM0_CH0_CNT - TIM[i] channel [x] SMU counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH0_CNT_CNT_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH0_CNT_CNT_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH0_CNT_CNT_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH0_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_CNT_CNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_CNT_CNT_MASK) /*! @} */ /*! @name TIM0_CH0_ECNT - TIM[i] channel [x] SMU edge counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH0_ECNT_ECNT_MASK (0xFFFFU) #define GTM_gtm_cls0_TIM0_CH0_ECNT_ECNT_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH0_ECNT_ECNT_WIDTH (16U) #define GTM_gtm_cls0_TIM0_CH0_ECNT_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_ECNT_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_ECNT_ECNT_MASK) /*! @} */ /*! @name TIM0_CH0_CNTS - TIM[i] channel [x] SMU shadow counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH0_CNTS_CNTS_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH0_CNTS_CNTS_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH0_CNTS_CNTS_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH0_CNTS_CNTS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_CNTS_CNTS_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_CNTS_CNTS_MASK) #define GTM_gtm_cls0_TIM0_CH0_CNTS_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls0_TIM0_CH0_CNTS_ECNT_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH0_CNTS_ECNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH0_CNTS_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_CNTS_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_CNTS_ECNT_MASK) /*! @} */ /*! @name TIM0_CH0_TDUC - TIM[i] channel [x] TDU counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH0_TDUC_TO_CNT_MASK (0xFFU) #define GTM_gtm_cls0_TIM0_CH0_TDUC_TO_CNT_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH0_TDUC_TO_CNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH0_TDUC_TO_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_TDUC_TO_CNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_TDUC_TO_CNT_MASK) #define GTM_gtm_cls0_TIM0_CH0_TDUC_TO_CNT1_MASK (0xFF00U) #define GTM_gtm_cls0_TIM0_CH0_TDUC_TO_CNT1_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH0_TDUC_TO_CNT1_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH0_TDUC_TO_CNT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_TDUC_TO_CNT1_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_TDUC_TO_CNT1_MASK) #define GTM_gtm_cls0_TIM0_CH0_TDUC_TO_CNT2_MASK (0xFF0000U) #define GTM_gtm_cls0_TIM0_CH0_TDUC_TO_CNT2_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH0_TDUC_TO_CNT2_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH0_TDUC_TO_CNT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_TDUC_TO_CNT2_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_TDUC_TO_CNT2_MASK) /*! @} */ /*! @name TIM0_CH0_TDUV - TIM[i] channel [x] TDU control register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH0_TDUV_TOV_MASK (0xFFU) #define GTM_gtm_cls0_TIM0_CH0_TDUV_TOV_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH0_TDUV_TOV_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH0_TDUV_TOV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_TDUV_TOV_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_TDUV_TOV_MASK) #define GTM_gtm_cls0_TIM0_CH0_TDUV_TOV1_MASK (0xFF00U) #define GTM_gtm_cls0_TIM0_CH0_TDUV_TOV1_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH0_TDUV_TOV1_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH0_TDUV_TOV1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_TDUV_TOV1_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_TDUV_TOV1_MASK) #define GTM_gtm_cls0_TIM0_CH0_TDUV_TOV2_MASK (0xFF0000U) #define GTM_gtm_cls0_TIM0_CH0_TDUV_TOV2_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH0_TDUV_TOV2_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH0_TDUV_TOV2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_TDUV_TOV2_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_TDUV_TOV2_MASK) #define GTM_gtm_cls0_TIM0_CH0_TDUV_SLICING_MASK (0x3000000U) #define GTM_gtm_cls0_TIM0_CH0_TDUV_SLICING_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH0_TDUV_SLICING_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH0_TDUV_SLICING(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_TDUV_SLICING_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_TDUV_SLICING_MASK) #define GTM_gtm_cls0_TIM0_CH0_TDUV_TCS_USE_SAMPLE_EVT_MASK (0x4000000U) #define GTM_gtm_cls0_TIM0_CH0_TDUV_TCS_USE_SAMPLE_EVT_SHIFT (26U) #define GTM_gtm_cls0_TIM0_CH0_TDUV_TCS_USE_SAMPLE_EVT_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_TDUV_TCS_USE_SAMPLE_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_TDUV_TCS_USE_SAMPLE_EVT_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_TDUV_TCS_USE_SAMPLE_EVT_MASK) #define GTM_gtm_cls0_TIM0_CH0_TDUV_TDU_SAME_CNT_CLK_MASK (0x8000000U) #define GTM_gtm_cls0_TIM0_CH0_TDUV_TDU_SAME_CNT_CLK_SHIFT (27U) #define GTM_gtm_cls0_TIM0_CH0_TDUV_TDU_SAME_CNT_CLK_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_TDUV_TDU_SAME_CNT_CLK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_TDUV_TDU_SAME_CNT_CLK_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_TDUV_TDU_SAME_CNT_CLK_MASK) #define GTM_gtm_cls0_TIM0_CH0_TDUV_TCS_MASK (0x70000000U) #define GTM_gtm_cls0_TIM0_CH0_TDUV_TCS_SHIFT (28U) #define GTM_gtm_cls0_TIM0_CH0_TDUV_TCS_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH0_TDUV_TCS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_TDUV_TCS_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_TDUV_TCS_MASK) /*! @} */ /*! @name TIM0_CH0_FLT_RE - TIM[i] channel [x] filter parameter 0 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH0_FLT_RE_FLT_RE_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH0_FLT_RE_FLT_RE_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH0_FLT_RE_FLT_RE_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH0_FLT_RE_FLT_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_FLT_RE_FLT_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_FLT_RE_FLT_RE_MASK) /*! @} */ /*! @name TIM0_CH0_FLT_FE - TIM[i] channel [x] filter parameter 1 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH0_FLT_FE_FLT_FE_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH0_FLT_FE_FLT_FE_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH0_FLT_FE_FLT_FE_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH0_FLT_FE_FLT_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_FLT_FE_FLT_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_FLT_FE_FLT_FE_MASK) /*! @} */ /*! @name TIM0_CH0_CTRL - TIM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH0_CTRL_TIM_EN_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_TIM_EN_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_TIM_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_TIM_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_CTRL_TIM_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_CTRL_TIM_EN_MASK) #define GTM_gtm_cls0_TIM0_CH0_CTRL_TIM_MODE_MASK (0xEU) #define GTM_gtm_cls0_TIM0_CH0_CTRL_TIM_MODE_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_TIM_MODE_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_TIM_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_CTRL_TIM_MODE_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_CTRL_TIM_MODE_MASK) #define GTM_gtm_cls0_TIM0_CH0_CTRL_OSM_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_OSM_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_CTRL_OSM_MASK) #define GTM_gtm_cls0_TIM0_CH0_CTRL_ARU_EN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_ARU_EN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_CTRL_ARU_EN_MASK) #define GTM_gtm_cls0_TIM0_CH0_CTRL_CICTRL_MASK (0x40U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_CICTRL_SHIFT (6U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_CICTRL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_CICTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_CTRL_CICTRL_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_CTRL_CICTRL_MASK) #define GTM_gtm_cls0_TIM0_CH0_CTRL_TBU0_SEL_MASK (0x80U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_TBU0_SEL_SHIFT (7U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_TBU0_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_TBU0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_CTRL_TBU0_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_CTRL_TBU0_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH0_CTRL_GPR0_SEL_MASK (0x300U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_GPR0_SEL_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_GPR0_SEL_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_GPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_CTRL_GPR0_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_CTRL_GPR0_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH0_CTRL_GPR1_SEL_MASK (0xC00U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_GPR1_SEL_SHIFT (10U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_GPR1_SEL_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_GPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_CTRL_GPR1_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_CTRL_GPR1_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH0_CTRL_CNTS_SEL_MASK (0x1000U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_CNTS_SEL_SHIFT (12U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_CNTS_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_CNTS_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_CTRL_CNTS_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_CTRL_CNTS_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH0_CTRL_DSL_MASK (0x2000U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_DSL_SHIFT (13U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_DSL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_CTRL_DSL_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_CTRL_DSL_MASK) #define GTM_gtm_cls0_TIM0_CH0_CTRL_ISL_MASK (0x4000U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_ISL_SHIFT (14U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_ISL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_ISL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_CTRL_ISL_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_CTRL_ISL_MASK) #define GTM_gtm_cls0_TIM0_CH0_CTRL_ECNT_RESET_MASK (0x8000U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_ECNT_RESET_SHIFT (15U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_ECNT_RESET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_ECNT_RESET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_CTRL_ECNT_RESET_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_CTRL_ECNT_RESET_MASK) #define GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_EN_MASK (0x10000U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_EN_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_EN_MASK) #define GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_CNT_FRQ_MASK (0x60000U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_CNT_FRQ_SHIFT (17U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_CNT_FRQ_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_CNT_FRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_CNT_FRQ_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_CNT_FRQ_MASK) #define GTM_gtm_cls0_TIM0_CH0_CTRL_EXT_CAP_EN_MASK (0x80000U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_EXT_CAP_EN_SHIFT (19U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_EXT_CAP_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_EXT_CAP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_CTRL_EXT_CAP_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_CTRL_EXT_CAP_EN_MASK) #define GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_MODE_RE_MASK (0x100000U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_MODE_RE_SHIFT (20U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_MODE_RE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_MODE_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_MODE_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_MODE_RE_MASK) #define GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_CTR_RE_MASK (0x200000U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_CTR_RE_SHIFT (21U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_CTR_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_CTR_RE_MASK) #define GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_MODE_FE_MASK (0x400000U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_MODE_FE_SHIFT (22U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_MODE_FE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_MODE_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_MODE_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_MODE_FE_MASK) #define GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_CTR_FE_MASK (0x800000U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_CTR_FE_SHIFT (23U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_CTR_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_CTRL_FLT_CTR_FE_MASK) #define GTM_gtm_cls0_TIM0_CH0_CTRL_CLK_SEL_MASK (0x7000000U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_CLK_SEL_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_CLK_SEL_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_CTRL_CLK_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_CTRL_CLK_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH0_CTRL_FR_ECNT_OFL_MASK (0x8000000U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_FR_ECNT_OFL_SHIFT (27U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_FR_ECNT_OFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_FR_ECNT_OFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_CTRL_FR_ECNT_OFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_CTRL_FR_ECNT_OFL_MASK) #define GTM_gtm_cls0_TIM0_CH0_CTRL_EGPR0_SEL_MASK (0x10000000U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_EGPR0_SEL_SHIFT (28U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_EGPR0_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_EGPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_CTRL_EGPR0_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_CTRL_EGPR0_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH0_CTRL_EGPR1_SEL_MASK (0x20000000U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_EGPR1_SEL_SHIFT (29U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_EGPR1_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_EGPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_CTRL_EGPR1_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_CTRL_EGPR1_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH0_CTRL_TOCTRL_MASK (0xC0000000U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_TOCTRL_SHIFT (30U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_TOCTRL_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH0_CTRL_TOCTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_CTRL_TOCTRL_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_CTRL_TOCTRL_MASK) /*! @} */ /*! @name TIM0_CH0_ECTRL - TIM[i] channel [x] extended control register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH0_ECTRL_EXT_CAP_SRC_MASK (0xFU) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_EXT_CAP_SRC_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_EXT_CAP_SRC_WIDTH (4U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_EXT_CAP_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_ECTRL_EXT_CAP_SRC_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_ECTRL_EXT_CAP_SRC_MASK) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_USE_PREV_TDU_IN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_USE_PREV_TDU_IN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_USE_PREV_TDU_IN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_USE_PREV_TDU_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_ECTRL_USE_PREV_TDU_IN_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_ECTRL_USE_PREV_TDU_IN_MASK) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_TODET_IRQ_SRC_MASK (0xC0U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_TODET_IRQ_SRC_SHIFT (6U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_TODET_IRQ_SRC_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_TODET_IRQ_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_ECTRL_TODET_IRQ_SRC_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_ECTRL_TODET_IRQ_SRC_MASK) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_TDU_START_MASK (0x700U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_TDU_START_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_TDU_START_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_TDU_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_ECTRL_TDU_START_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_ECTRL_TDU_START_MASK) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_TDU_STOP_MASK (0x7000U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_TDU_STOP_SHIFT (12U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_TDU_STOP_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_TDU_STOP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_ECTRL_TDU_STOP_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_ECTRL_TDU_STOP_MASK) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_TDU_RESYNC_MASK (0xF0000U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_TDU_RESYNC_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_TDU_RESYNC_WIDTH (4U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_TDU_RESYNC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_ECTRL_TDU_RESYNC_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_ECTRL_TDU_RESYNC_MASK) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_USE_LUT_MASK (0xC00000U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_USE_LUT_SHIFT (22U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_USE_LUT_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_USE_LUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_ECTRL_USE_LUT_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_ECTRL_USE_LUT_MASK) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_EFLT_CTR_RE_MASK (0x1000000U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_EFLT_CTR_RE_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_EFLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_EFLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_ECTRL_EFLT_CTR_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_ECTRL_EFLT_CTR_RE_MASK) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_EFLT_CTR_FE_MASK (0x2000000U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_EFLT_CTR_FE_SHIFT (25U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_EFLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_EFLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_ECTRL_EFLT_CTR_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_ECTRL_EFLT_CTR_FE_MASK) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_SWAP_CAPTURE_MASK (0x10000000U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_SWAP_CAPTURE_SHIFT (28U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_SWAP_CAPTURE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_SWAP_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_ECTRL_SWAP_CAPTURE_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_ECTRL_SWAP_CAPTURE_MASK) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_IMM_START_MASK (0x20000000U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_IMM_START_SHIFT (29U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_IMM_START_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_IMM_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_ECTRL_IMM_START_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_ECTRL_IMM_START_MASK) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_ECLK_SEL_MASK (0x40000000U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_ECLK_SEL_SHIFT (30U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_ECLK_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_ECLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_ECTRL_ECLK_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_ECTRL_ECLK_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_USE_PREV_CH_IN_MASK (0x80000000U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_USE_PREV_CH_IN_SHIFT (31U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_USE_PREV_CH_IN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_ECTRL_USE_PREV_CH_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_ECTRL_USE_PREV_CH_IN_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_ECTRL_USE_PREV_CH_IN_MASK) /*! @} */ /*! @name TIM0_CH0_IRQ_NOTIFY - TIM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_NEWVAL_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_NEWVAL_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_NEWVAL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_NEWVAL_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_NEWVAL_MASK) #define GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_ECNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_ECNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_CNTOFL_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_CNTOFL_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_CNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_CNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_CNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_GPROFL_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_GPROFL_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_GPROFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_GPROFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_GPROFL_MASK) #define GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_TODET_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_TODET_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_TODET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_TODET_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_TODET_MASK) #define GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_GLITCHDET_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_IRQ_NOTIFY_GLITCHDET_MASK) /*! @} */ /*! @name TIM0_CH0_IRQ_EN - TIM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH0_IRQ_EN_NEWVAL_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_EN_NEWVAL_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_EN_NEWVAL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_EN_NEWVAL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_IRQ_EN_NEWVAL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_IRQ_EN_NEWVAL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH0_IRQ_EN_ECNTOFL_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_EN_ECNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_EN_ECNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_IRQ_EN_ECNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH0_IRQ_EN_CNTOFL_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_EN_CNTOFL_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_EN_CNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_EN_CNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_IRQ_EN_CNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_IRQ_EN_CNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH0_IRQ_EN_GPROFL_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_EN_GPROFL_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_EN_GPROFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_EN_GPROFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_IRQ_EN_GPROFL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_IRQ_EN_GPROFL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH0_IRQ_EN_TODET_IRQ_EN_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_EN_TODET_IRQ_EN_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_EN_TODET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_EN_TODET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_IRQ_EN_TODET_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_IRQ_EN_TODET_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH0_IRQ_EN_GLITCHDET_IRQ_EN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_EN_GLITCHDET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_EN_GLITCHDET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_IRQ_EN_GLITCHDET_IRQ_EN_MASK) /*! @} */ /*! @name TIM0_CH0_IRQ_FORCINT - TIM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_NEWVAL_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_NEWVAL_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_NEWVAL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_NEWVAL_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_NEWVAL_MASK) #define GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_ECNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_ECNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_CNTOFL_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_CNTOFL_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_CNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_CNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_CNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_GPROFL_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_GPROFL_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_GPROFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_GPROFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_GPROFL_MASK) #define GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_TODET_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_TODET_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_TODET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_TODET_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_TODET_MASK) #define GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_GLITCHDET_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_IRQ_FORCINT_TRG_GLITCHDET_MASK) /*! @} */ /*! @name TIM0_CH0_IRQ_MODE - TIM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH0_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH0_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TIM0_CH0_EIRQ_EN - TIM[i] channel [x] error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_NEWVAL_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_NEWVAL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_NEWVAL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_NEWVAL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_ECNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_ECNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_CNTOFL_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_CNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_CNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_CNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_GPROFL_EIRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_GPROFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_GPROFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_GPROFL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_TODET_EIRQ_EN_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_TODET_EIRQ_EN_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_TODET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_TODET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_TODET_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_TODET_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_GLITCHDET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_GLITCHDET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH0_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK) /*! @} */ /*! @name TIM0_CH1_GPR0 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH1_GPR0_GPR0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH1_GPR0_GPR0_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH1_GPR0_GPR0_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH1_GPR0_GPR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_GPR0_GPR0_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_GPR0_GPR0_MASK) #define GTM_gtm_cls0_TIM0_CH1_GPR0_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls0_TIM0_CH1_GPR0_ECNT_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH1_GPR0_ECNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH1_GPR0_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_GPR0_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_GPR0_ECNT_MASK) /*! @} */ /*! @name TIM0_CH1_GPR1 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH1_GPR1_GPR1_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH1_GPR1_GPR1_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH1_GPR1_GPR1_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH1_GPR1_GPR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_GPR1_GPR1_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_GPR1_GPR1_MASK) #define GTM_gtm_cls0_TIM0_CH1_GPR1_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls0_TIM0_CH1_GPR1_ECNT_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH1_GPR1_ECNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH1_GPR1_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_GPR1_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_GPR1_ECNT_MASK) /*! @} */ /*! @name TIM0_CH1_CNT - TIM[i] channel [x] SMU counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH1_CNT_CNT_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH1_CNT_CNT_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH1_CNT_CNT_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH1_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_CNT_CNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_CNT_CNT_MASK) /*! @} */ /*! @name TIM0_CH1_ECNT - TIM[i] channel [x] SMU edge counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH1_ECNT_ECNT_MASK (0xFFFFU) #define GTM_gtm_cls0_TIM0_CH1_ECNT_ECNT_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH1_ECNT_ECNT_WIDTH (16U) #define GTM_gtm_cls0_TIM0_CH1_ECNT_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_ECNT_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_ECNT_ECNT_MASK) /*! @} */ /*! @name TIM0_CH1_CNTS - TIM[i] channel [x] SMU shadow counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH1_CNTS_CNTS_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH1_CNTS_CNTS_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH1_CNTS_CNTS_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH1_CNTS_CNTS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_CNTS_CNTS_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_CNTS_CNTS_MASK) #define GTM_gtm_cls0_TIM0_CH1_CNTS_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls0_TIM0_CH1_CNTS_ECNT_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH1_CNTS_ECNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH1_CNTS_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_CNTS_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_CNTS_ECNT_MASK) /*! @} */ /*! @name TIM0_CH1_TDUC - TIM[i] channel [x] TDU counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH1_TDUC_TO_CNT_MASK (0xFFU) #define GTM_gtm_cls0_TIM0_CH1_TDUC_TO_CNT_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH1_TDUC_TO_CNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH1_TDUC_TO_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_TDUC_TO_CNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_TDUC_TO_CNT_MASK) #define GTM_gtm_cls0_TIM0_CH1_TDUC_TO_CNT1_MASK (0xFF00U) #define GTM_gtm_cls0_TIM0_CH1_TDUC_TO_CNT1_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH1_TDUC_TO_CNT1_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH1_TDUC_TO_CNT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_TDUC_TO_CNT1_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_TDUC_TO_CNT1_MASK) #define GTM_gtm_cls0_TIM0_CH1_TDUC_TO_CNT2_MASK (0xFF0000U) #define GTM_gtm_cls0_TIM0_CH1_TDUC_TO_CNT2_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH1_TDUC_TO_CNT2_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH1_TDUC_TO_CNT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_TDUC_TO_CNT2_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_TDUC_TO_CNT2_MASK) /*! @} */ /*! @name TIM0_CH1_TDUV - TIM[i] channel [x] TDU control register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH1_TDUV_TOV_MASK (0xFFU) #define GTM_gtm_cls0_TIM0_CH1_TDUV_TOV_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH1_TDUV_TOV_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH1_TDUV_TOV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_TDUV_TOV_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_TDUV_TOV_MASK) #define GTM_gtm_cls0_TIM0_CH1_TDUV_TOV1_MASK (0xFF00U) #define GTM_gtm_cls0_TIM0_CH1_TDUV_TOV1_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH1_TDUV_TOV1_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH1_TDUV_TOV1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_TDUV_TOV1_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_TDUV_TOV1_MASK) #define GTM_gtm_cls0_TIM0_CH1_TDUV_TOV2_MASK (0xFF0000U) #define GTM_gtm_cls0_TIM0_CH1_TDUV_TOV2_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH1_TDUV_TOV2_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH1_TDUV_TOV2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_TDUV_TOV2_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_TDUV_TOV2_MASK) #define GTM_gtm_cls0_TIM0_CH1_TDUV_SLICING_MASK (0x3000000U) #define GTM_gtm_cls0_TIM0_CH1_TDUV_SLICING_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH1_TDUV_SLICING_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH1_TDUV_SLICING(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_TDUV_SLICING_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_TDUV_SLICING_MASK) #define GTM_gtm_cls0_TIM0_CH1_TDUV_TCS_USE_SAMPLE_EVT_MASK (0x4000000U) #define GTM_gtm_cls0_TIM0_CH1_TDUV_TCS_USE_SAMPLE_EVT_SHIFT (26U) #define GTM_gtm_cls0_TIM0_CH1_TDUV_TCS_USE_SAMPLE_EVT_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_TDUV_TCS_USE_SAMPLE_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_TDUV_TCS_USE_SAMPLE_EVT_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_TDUV_TCS_USE_SAMPLE_EVT_MASK) #define GTM_gtm_cls0_TIM0_CH1_TDUV_TDU_SAME_CNT_CLK_MASK (0x8000000U) #define GTM_gtm_cls0_TIM0_CH1_TDUV_TDU_SAME_CNT_CLK_SHIFT (27U) #define GTM_gtm_cls0_TIM0_CH1_TDUV_TDU_SAME_CNT_CLK_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_TDUV_TDU_SAME_CNT_CLK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_TDUV_TDU_SAME_CNT_CLK_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_TDUV_TDU_SAME_CNT_CLK_MASK) #define GTM_gtm_cls0_TIM0_CH1_TDUV_TCS_MASK (0x70000000U) #define GTM_gtm_cls0_TIM0_CH1_TDUV_TCS_SHIFT (28U) #define GTM_gtm_cls0_TIM0_CH1_TDUV_TCS_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH1_TDUV_TCS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_TDUV_TCS_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_TDUV_TCS_MASK) /*! @} */ /*! @name TIM0_CH1_FLT_RE - TIM[i] channel [x] filter parameter 0 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH1_FLT_RE_FLT_RE_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH1_FLT_RE_FLT_RE_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH1_FLT_RE_FLT_RE_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH1_FLT_RE_FLT_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_FLT_RE_FLT_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_FLT_RE_FLT_RE_MASK) /*! @} */ /*! @name TIM0_CH1_FLT_FE - TIM[i] channel [x] filter parameter 1 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH1_FLT_FE_FLT_FE_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH1_FLT_FE_FLT_FE_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH1_FLT_FE_FLT_FE_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH1_FLT_FE_FLT_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_FLT_FE_FLT_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_FLT_FE_FLT_FE_MASK) /*! @} */ /*! @name TIM0_CH1_CTRL - TIM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH1_CTRL_TIM_EN_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_TIM_EN_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_TIM_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_TIM_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_CTRL_TIM_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_CTRL_TIM_EN_MASK) #define GTM_gtm_cls0_TIM0_CH1_CTRL_TIM_MODE_MASK (0xEU) #define GTM_gtm_cls0_TIM0_CH1_CTRL_TIM_MODE_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_TIM_MODE_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_TIM_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_CTRL_TIM_MODE_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_CTRL_TIM_MODE_MASK) #define GTM_gtm_cls0_TIM0_CH1_CTRL_OSM_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_OSM_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_CTRL_OSM_MASK) #define GTM_gtm_cls0_TIM0_CH1_CTRL_ARU_EN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_ARU_EN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_CTRL_ARU_EN_MASK) #define GTM_gtm_cls0_TIM0_CH1_CTRL_CICTRL_MASK (0x40U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_CICTRL_SHIFT (6U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_CICTRL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_CICTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_CTRL_CICTRL_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_CTRL_CICTRL_MASK) #define GTM_gtm_cls0_TIM0_CH1_CTRL_TBU0_SEL_MASK (0x80U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_TBU0_SEL_SHIFT (7U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_TBU0_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_TBU0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_CTRL_TBU0_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_CTRL_TBU0_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH1_CTRL_GPR0_SEL_MASK (0x300U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_GPR0_SEL_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_GPR0_SEL_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_GPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_CTRL_GPR0_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_CTRL_GPR0_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH1_CTRL_GPR1_SEL_MASK (0xC00U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_GPR1_SEL_SHIFT (10U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_GPR1_SEL_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_GPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_CTRL_GPR1_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_CTRL_GPR1_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH1_CTRL_CNTS_SEL_MASK (0x1000U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_CNTS_SEL_SHIFT (12U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_CNTS_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_CNTS_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_CTRL_CNTS_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_CTRL_CNTS_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH1_CTRL_DSL_MASK (0x2000U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_DSL_SHIFT (13U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_DSL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_CTRL_DSL_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_CTRL_DSL_MASK) #define GTM_gtm_cls0_TIM0_CH1_CTRL_ISL_MASK (0x4000U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_ISL_SHIFT (14U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_ISL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_ISL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_CTRL_ISL_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_CTRL_ISL_MASK) #define GTM_gtm_cls0_TIM0_CH1_CTRL_ECNT_RESET_MASK (0x8000U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_ECNT_RESET_SHIFT (15U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_ECNT_RESET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_ECNT_RESET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_CTRL_ECNT_RESET_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_CTRL_ECNT_RESET_MASK) #define GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_EN_MASK (0x10000U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_EN_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_EN_MASK) #define GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_CNT_FRQ_MASK (0x60000U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_CNT_FRQ_SHIFT (17U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_CNT_FRQ_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_CNT_FRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_CNT_FRQ_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_CNT_FRQ_MASK) #define GTM_gtm_cls0_TIM0_CH1_CTRL_EXT_CAP_EN_MASK (0x80000U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_EXT_CAP_EN_SHIFT (19U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_EXT_CAP_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_EXT_CAP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_CTRL_EXT_CAP_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_CTRL_EXT_CAP_EN_MASK) #define GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_MODE_RE_MASK (0x100000U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_MODE_RE_SHIFT (20U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_MODE_RE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_MODE_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_MODE_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_MODE_RE_MASK) #define GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_CTR_RE_MASK (0x200000U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_CTR_RE_SHIFT (21U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_CTR_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_CTR_RE_MASK) #define GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_MODE_FE_MASK (0x400000U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_MODE_FE_SHIFT (22U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_MODE_FE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_MODE_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_MODE_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_MODE_FE_MASK) #define GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_CTR_FE_MASK (0x800000U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_CTR_FE_SHIFT (23U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_CTR_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_CTRL_FLT_CTR_FE_MASK) #define GTM_gtm_cls0_TIM0_CH1_CTRL_CLK_SEL_MASK (0x7000000U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_CLK_SEL_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_CLK_SEL_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_CTRL_CLK_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_CTRL_CLK_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH1_CTRL_FR_ECNT_OFL_MASK (0x8000000U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_FR_ECNT_OFL_SHIFT (27U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_FR_ECNT_OFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_FR_ECNT_OFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_CTRL_FR_ECNT_OFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_CTRL_FR_ECNT_OFL_MASK) #define GTM_gtm_cls0_TIM0_CH1_CTRL_EGPR0_SEL_MASK (0x10000000U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_EGPR0_SEL_SHIFT (28U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_EGPR0_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_EGPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_CTRL_EGPR0_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_CTRL_EGPR0_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH1_CTRL_EGPR1_SEL_MASK (0x20000000U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_EGPR1_SEL_SHIFT (29U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_EGPR1_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_EGPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_CTRL_EGPR1_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_CTRL_EGPR1_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH1_CTRL_TOCTRL_MASK (0xC0000000U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_TOCTRL_SHIFT (30U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_TOCTRL_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH1_CTRL_TOCTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_CTRL_TOCTRL_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_CTRL_TOCTRL_MASK) /*! @} */ /*! @name TIM0_CH1_ECTRL - TIM[i] channel [x] extended control register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH1_ECTRL_EXT_CAP_SRC_MASK (0xFU) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_EXT_CAP_SRC_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_EXT_CAP_SRC_WIDTH (4U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_EXT_CAP_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_ECTRL_EXT_CAP_SRC_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_ECTRL_EXT_CAP_SRC_MASK) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_USE_PREV_TDU_IN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_USE_PREV_TDU_IN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_USE_PREV_TDU_IN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_USE_PREV_TDU_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_ECTRL_USE_PREV_TDU_IN_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_ECTRL_USE_PREV_TDU_IN_MASK) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_TODET_IRQ_SRC_MASK (0xC0U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_TODET_IRQ_SRC_SHIFT (6U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_TODET_IRQ_SRC_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_TODET_IRQ_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_ECTRL_TODET_IRQ_SRC_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_ECTRL_TODET_IRQ_SRC_MASK) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_TDU_START_MASK (0x700U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_TDU_START_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_TDU_START_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_TDU_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_ECTRL_TDU_START_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_ECTRL_TDU_START_MASK) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_TDU_STOP_MASK (0x7000U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_TDU_STOP_SHIFT (12U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_TDU_STOP_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_TDU_STOP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_ECTRL_TDU_STOP_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_ECTRL_TDU_STOP_MASK) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_TDU_RESYNC_MASK (0xF0000U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_TDU_RESYNC_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_TDU_RESYNC_WIDTH (4U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_TDU_RESYNC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_ECTRL_TDU_RESYNC_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_ECTRL_TDU_RESYNC_MASK) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_USE_LUT_MASK (0xC00000U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_USE_LUT_SHIFT (22U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_USE_LUT_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_USE_LUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_ECTRL_USE_LUT_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_ECTRL_USE_LUT_MASK) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_EFLT_CTR_RE_MASK (0x1000000U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_EFLT_CTR_RE_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_EFLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_EFLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_ECTRL_EFLT_CTR_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_ECTRL_EFLT_CTR_RE_MASK) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_EFLT_CTR_FE_MASK (0x2000000U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_EFLT_CTR_FE_SHIFT (25U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_EFLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_EFLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_ECTRL_EFLT_CTR_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_ECTRL_EFLT_CTR_FE_MASK) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_SWAP_CAPTURE_MASK (0x10000000U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_SWAP_CAPTURE_SHIFT (28U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_SWAP_CAPTURE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_SWAP_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_ECTRL_SWAP_CAPTURE_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_ECTRL_SWAP_CAPTURE_MASK) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_IMM_START_MASK (0x20000000U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_IMM_START_SHIFT (29U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_IMM_START_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_IMM_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_ECTRL_IMM_START_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_ECTRL_IMM_START_MASK) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_ECLK_SEL_MASK (0x40000000U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_ECLK_SEL_SHIFT (30U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_ECLK_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_ECLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_ECTRL_ECLK_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_ECTRL_ECLK_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_USE_PREV_CH_IN_MASK (0x80000000U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_USE_PREV_CH_IN_SHIFT (31U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_USE_PREV_CH_IN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_ECTRL_USE_PREV_CH_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_ECTRL_USE_PREV_CH_IN_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_ECTRL_USE_PREV_CH_IN_MASK) /*! @} */ /*! @name TIM0_CH1_IRQ_NOTIFY - TIM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_NEWVAL_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_NEWVAL_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_NEWVAL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_NEWVAL_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_NEWVAL_MASK) #define GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_ECNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_ECNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_CNTOFL_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_CNTOFL_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_CNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_CNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_CNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_GPROFL_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_GPROFL_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_GPROFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_GPROFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_GPROFL_MASK) #define GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_TODET_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_TODET_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_TODET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_TODET_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_TODET_MASK) #define GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_GLITCHDET_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_IRQ_NOTIFY_GLITCHDET_MASK) /*! @} */ /*! @name TIM0_CH1_IRQ_EN - TIM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH1_IRQ_EN_NEWVAL_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_EN_NEWVAL_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_EN_NEWVAL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_EN_NEWVAL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_IRQ_EN_NEWVAL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_IRQ_EN_NEWVAL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH1_IRQ_EN_ECNTOFL_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_EN_ECNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_EN_ECNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_IRQ_EN_ECNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH1_IRQ_EN_CNTOFL_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_EN_CNTOFL_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_EN_CNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_EN_CNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_IRQ_EN_CNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_IRQ_EN_CNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH1_IRQ_EN_GPROFL_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_EN_GPROFL_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_EN_GPROFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_EN_GPROFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_IRQ_EN_GPROFL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_IRQ_EN_GPROFL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH1_IRQ_EN_TODET_IRQ_EN_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_EN_TODET_IRQ_EN_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_EN_TODET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_EN_TODET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_IRQ_EN_TODET_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_IRQ_EN_TODET_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH1_IRQ_EN_GLITCHDET_IRQ_EN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_EN_GLITCHDET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_EN_GLITCHDET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_IRQ_EN_GLITCHDET_IRQ_EN_MASK) /*! @} */ /*! @name TIM0_CH1_IRQ_FORCINT - TIM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_NEWVAL_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_NEWVAL_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_NEWVAL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_NEWVAL_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_NEWVAL_MASK) #define GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_ECNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_ECNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_CNTOFL_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_CNTOFL_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_CNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_CNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_CNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_GPROFL_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_GPROFL_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_GPROFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_GPROFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_GPROFL_MASK) #define GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_TODET_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_TODET_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_TODET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_TODET_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_TODET_MASK) #define GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_GLITCHDET_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_IRQ_FORCINT_TRG_GLITCHDET_MASK) /*! @} */ /*! @name TIM0_CH1_IRQ_MODE - TIM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH1_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH1_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TIM0_CH1_EIRQ_EN - TIM[i] channel [x] error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_NEWVAL_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_NEWVAL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_NEWVAL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_NEWVAL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_ECNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_ECNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_CNTOFL_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_CNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_CNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_CNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_GPROFL_EIRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_GPROFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_GPROFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_GPROFL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_TODET_EIRQ_EN_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_TODET_EIRQ_EN_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_TODET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_TODET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_TODET_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_TODET_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_GLITCHDET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_GLITCHDET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH1_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK) /*! @} */ /*! @name TIM0_CH2_GPR0 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH2_GPR0_GPR0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH2_GPR0_GPR0_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH2_GPR0_GPR0_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH2_GPR0_GPR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_GPR0_GPR0_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_GPR0_GPR0_MASK) #define GTM_gtm_cls0_TIM0_CH2_GPR0_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls0_TIM0_CH2_GPR0_ECNT_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH2_GPR0_ECNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH2_GPR0_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_GPR0_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_GPR0_ECNT_MASK) /*! @} */ /*! @name TIM0_CH2_GPR1 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH2_GPR1_GPR1_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH2_GPR1_GPR1_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH2_GPR1_GPR1_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH2_GPR1_GPR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_GPR1_GPR1_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_GPR1_GPR1_MASK) #define GTM_gtm_cls0_TIM0_CH2_GPR1_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls0_TIM0_CH2_GPR1_ECNT_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH2_GPR1_ECNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH2_GPR1_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_GPR1_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_GPR1_ECNT_MASK) /*! @} */ /*! @name TIM0_CH2_CNT - TIM[i] channel [x] SMU counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH2_CNT_CNT_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH2_CNT_CNT_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH2_CNT_CNT_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH2_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_CNT_CNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_CNT_CNT_MASK) /*! @} */ /*! @name TIM0_CH2_ECNT - TIM[i] channel [x] SMU edge counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH2_ECNT_ECNT_MASK (0xFFFFU) #define GTM_gtm_cls0_TIM0_CH2_ECNT_ECNT_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH2_ECNT_ECNT_WIDTH (16U) #define GTM_gtm_cls0_TIM0_CH2_ECNT_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_ECNT_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_ECNT_ECNT_MASK) /*! @} */ /*! @name TIM0_CH2_CNTS - TIM[i] channel [x] SMU shadow counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH2_CNTS_CNTS_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH2_CNTS_CNTS_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH2_CNTS_CNTS_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH2_CNTS_CNTS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_CNTS_CNTS_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_CNTS_CNTS_MASK) #define GTM_gtm_cls0_TIM0_CH2_CNTS_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls0_TIM0_CH2_CNTS_ECNT_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH2_CNTS_ECNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH2_CNTS_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_CNTS_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_CNTS_ECNT_MASK) /*! @} */ /*! @name TIM0_CH2_TDUC - TIM[i] channel [x] TDU counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH2_TDUC_TO_CNT_MASK (0xFFU) #define GTM_gtm_cls0_TIM0_CH2_TDUC_TO_CNT_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH2_TDUC_TO_CNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH2_TDUC_TO_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_TDUC_TO_CNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_TDUC_TO_CNT_MASK) #define GTM_gtm_cls0_TIM0_CH2_TDUC_TO_CNT1_MASK (0xFF00U) #define GTM_gtm_cls0_TIM0_CH2_TDUC_TO_CNT1_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH2_TDUC_TO_CNT1_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH2_TDUC_TO_CNT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_TDUC_TO_CNT1_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_TDUC_TO_CNT1_MASK) #define GTM_gtm_cls0_TIM0_CH2_TDUC_TO_CNT2_MASK (0xFF0000U) #define GTM_gtm_cls0_TIM0_CH2_TDUC_TO_CNT2_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH2_TDUC_TO_CNT2_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH2_TDUC_TO_CNT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_TDUC_TO_CNT2_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_TDUC_TO_CNT2_MASK) /*! @} */ /*! @name TIM0_CH2_TDUV - TIM[i] channel [x] TDU control register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH2_TDUV_TOV_MASK (0xFFU) #define GTM_gtm_cls0_TIM0_CH2_TDUV_TOV_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH2_TDUV_TOV_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH2_TDUV_TOV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_TDUV_TOV_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_TDUV_TOV_MASK) #define GTM_gtm_cls0_TIM0_CH2_TDUV_TOV1_MASK (0xFF00U) #define GTM_gtm_cls0_TIM0_CH2_TDUV_TOV1_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH2_TDUV_TOV1_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH2_TDUV_TOV1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_TDUV_TOV1_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_TDUV_TOV1_MASK) #define GTM_gtm_cls0_TIM0_CH2_TDUV_TOV2_MASK (0xFF0000U) #define GTM_gtm_cls0_TIM0_CH2_TDUV_TOV2_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH2_TDUV_TOV2_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH2_TDUV_TOV2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_TDUV_TOV2_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_TDUV_TOV2_MASK) #define GTM_gtm_cls0_TIM0_CH2_TDUV_SLICING_MASK (0x3000000U) #define GTM_gtm_cls0_TIM0_CH2_TDUV_SLICING_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH2_TDUV_SLICING_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH2_TDUV_SLICING(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_TDUV_SLICING_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_TDUV_SLICING_MASK) #define GTM_gtm_cls0_TIM0_CH2_TDUV_TCS_USE_SAMPLE_EVT_MASK (0x4000000U) #define GTM_gtm_cls0_TIM0_CH2_TDUV_TCS_USE_SAMPLE_EVT_SHIFT (26U) #define GTM_gtm_cls0_TIM0_CH2_TDUV_TCS_USE_SAMPLE_EVT_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_TDUV_TCS_USE_SAMPLE_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_TDUV_TCS_USE_SAMPLE_EVT_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_TDUV_TCS_USE_SAMPLE_EVT_MASK) #define GTM_gtm_cls0_TIM0_CH2_TDUV_TDU_SAME_CNT_CLK_MASK (0x8000000U) #define GTM_gtm_cls0_TIM0_CH2_TDUV_TDU_SAME_CNT_CLK_SHIFT (27U) #define GTM_gtm_cls0_TIM0_CH2_TDUV_TDU_SAME_CNT_CLK_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_TDUV_TDU_SAME_CNT_CLK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_TDUV_TDU_SAME_CNT_CLK_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_TDUV_TDU_SAME_CNT_CLK_MASK) #define GTM_gtm_cls0_TIM0_CH2_TDUV_TCS_MASK (0x70000000U) #define GTM_gtm_cls0_TIM0_CH2_TDUV_TCS_SHIFT (28U) #define GTM_gtm_cls0_TIM0_CH2_TDUV_TCS_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH2_TDUV_TCS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_TDUV_TCS_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_TDUV_TCS_MASK) /*! @} */ /*! @name TIM0_CH2_FLT_RE - TIM[i] channel [x] filter parameter 0 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH2_FLT_RE_FLT_RE_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH2_FLT_RE_FLT_RE_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH2_FLT_RE_FLT_RE_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH2_FLT_RE_FLT_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_FLT_RE_FLT_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_FLT_RE_FLT_RE_MASK) /*! @} */ /*! @name TIM0_CH2_FLT_FE - TIM[i] channel [x] filter parameter 1 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH2_FLT_FE_FLT_FE_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH2_FLT_FE_FLT_FE_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH2_FLT_FE_FLT_FE_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH2_FLT_FE_FLT_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_FLT_FE_FLT_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_FLT_FE_FLT_FE_MASK) /*! @} */ /*! @name TIM0_CH2_CTRL - TIM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH2_CTRL_TIM_EN_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_TIM_EN_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_TIM_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_TIM_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_CTRL_TIM_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_CTRL_TIM_EN_MASK) #define GTM_gtm_cls0_TIM0_CH2_CTRL_TIM_MODE_MASK (0xEU) #define GTM_gtm_cls0_TIM0_CH2_CTRL_TIM_MODE_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_TIM_MODE_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_TIM_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_CTRL_TIM_MODE_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_CTRL_TIM_MODE_MASK) #define GTM_gtm_cls0_TIM0_CH2_CTRL_OSM_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_OSM_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_CTRL_OSM_MASK) #define GTM_gtm_cls0_TIM0_CH2_CTRL_ARU_EN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_ARU_EN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_CTRL_ARU_EN_MASK) #define GTM_gtm_cls0_TIM0_CH2_CTRL_CICTRL_MASK (0x40U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_CICTRL_SHIFT (6U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_CICTRL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_CICTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_CTRL_CICTRL_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_CTRL_CICTRL_MASK) #define GTM_gtm_cls0_TIM0_CH2_CTRL_TBU0_SEL_MASK (0x80U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_TBU0_SEL_SHIFT (7U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_TBU0_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_TBU0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_CTRL_TBU0_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_CTRL_TBU0_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH2_CTRL_GPR0_SEL_MASK (0x300U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_GPR0_SEL_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_GPR0_SEL_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_GPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_CTRL_GPR0_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_CTRL_GPR0_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH2_CTRL_GPR1_SEL_MASK (0xC00U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_GPR1_SEL_SHIFT (10U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_GPR1_SEL_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_GPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_CTRL_GPR1_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_CTRL_GPR1_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH2_CTRL_CNTS_SEL_MASK (0x1000U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_CNTS_SEL_SHIFT (12U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_CNTS_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_CNTS_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_CTRL_CNTS_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_CTRL_CNTS_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH2_CTRL_DSL_MASK (0x2000U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_DSL_SHIFT (13U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_DSL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_CTRL_DSL_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_CTRL_DSL_MASK) #define GTM_gtm_cls0_TIM0_CH2_CTRL_ISL_MASK (0x4000U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_ISL_SHIFT (14U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_ISL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_ISL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_CTRL_ISL_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_CTRL_ISL_MASK) #define GTM_gtm_cls0_TIM0_CH2_CTRL_ECNT_RESET_MASK (0x8000U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_ECNT_RESET_SHIFT (15U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_ECNT_RESET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_ECNT_RESET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_CTRL_ECNT_RESET_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_CTRL_ECNT_RESET_MASK) #define GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_EN_MASK (0x10000U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_EN_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_EN_MASK) #define GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_CNT_FRQ_MASK (0x60000U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_CNT_FRQ_SHIFT (17U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_CNT_FRQ_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_CNT_FRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_CNT_FRQ_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_CNT_FRQ_MASK) #define GTM_gtm_cls0_TIM0_CH2_CTRL_EXT_CAP_EN_MASK (0x80000U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_EXT_CAP_EN_SHIFT (19U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_EXT_CAP_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_EXT_CAP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_CTRL_EXT_CAP_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_CTRL_EXT_CAP_EN_MASK) #define GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_MODE_RE_MASK (0x100000U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_MODE_RE_SHIFT (20U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_MODE_RE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_MODE_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_MODE_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_MODE_RE_MASK) #define GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_CTR_RE_MASK (0x200000U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_CTR_RE_SHIFT (21U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_CTR_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_CTR_RE_MASK) #define GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_MODE_FE_MASK (0x400000U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_MODE_FE_SHIFT (22U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_MODE_FE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_MODE_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_MODE_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_MODE_FE_MASK) #define GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_CTR_FE_MASK (0x800000U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_CTR_FE_SHIFT (23U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_CTR_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_CTRL_FLT_CTR_FE_MASK) #define GTM_gtm_cls0_TIM0_CH2_CTRL_CLK_SEL_MASK (0x7000000U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_CLK_SEL_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_CLK_SEL_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_CTRL_CLK_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_CTRL_CLK_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH2_CTRL_FR_ECNT_OFL_MASK (0x8000000U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_FR_ECNT_OFL_SHIFT (27U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_FR_ECNT_OFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_FR_ECNT_OFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_CTRL_FR_ECNT_OFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_CTRL_FR_ECNT_OFL_MASK) #define GTM_gtm_cls0_TIM0_CH2_CTRL_EGPR0_SEL_MASK (0x10000000U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_EGPR0_SEL_SHIFT (28U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_EGPR0_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_EGPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_CTRL_EGPR0_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_CTRL_EGPR0_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH2_CTRL_EGPR1_SEL_MASK (0x20000000U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_EGPR1_SEL_SHIFT (29U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_EGPR1_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_EGPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_CTRL_EGPR1_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_CTRL_EGPR1_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH2_CTRL_TOCTRL_MASK (0xC0000000U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_TOCTRL_SHIFT (30U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_TOCTRL_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH2_CTRL_TOCTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_CTRL_TOCTRL_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_CTRL_TOCTRL_MASK) /*! @} */ /*! @name TIM0_CH2_ECTRL - TIM[i] channel [x] extended control register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH2_ECTRL_EXT_CAP_SRC_MASK (0xFU) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_EXT_CAP_SRC_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_EXT_CAP_SRC_WIDTH (4U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_EXT_CAP_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_ECTRL_EXT_CAP_SRC_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_ECTRL_EXT_CAP_SRC_MASK) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_USE_PREV_TDU_IN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_USE_PREV_TDU_IN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_USE_PREV_TDU_IN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_USE_PREV_TDU_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_ECTRL_USE_PREV_TDU_IN_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_ECTRL_USE_PREV_TDU_IN_MASK) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_TODET_IRQ_SRC_MASK (0xC0U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_TODET_IRQ_SRC_SHIFT (6U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_TODET_IRQ_SRC_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_TODET_IRQ_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_ECTRL_TODET_IRQ_SRC_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_ECTRL_TODET_IRQ_SRC_MASK) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_TDU_START_MASK (0x700U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_TDU_START_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_TDU_START_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_TDU_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_ECTRL_TDU_START_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_ECTRL_TDU_START_MASK) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_TDU_STOP_MASK (0x7000U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_TDU_STOP_SHIFT (12U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_TDU_STOP_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_TDU_STOP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_ECTRL_TDU_STOP_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_ECTRL_TDU_STOP_MASK) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_TDU_RESYNC_MASK (0xF0000U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_TDU_RESYNC_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_TDU_RESYNC_WIDTH (4U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_TDU_RESYNC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_ECTRL_TDU_RESYNC_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_ECTRL_TDU_RESYNC_MASK) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_USE_LUT_MASK (0xC00000U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_USE_LUT_SHIFT (22U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_USE_LUT_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_USE_LUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_ECTRL_USE_LUT_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_ECTRL_USE_LUT_MASK) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_EFLT_CTR_RE_MASK (0x1000000U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_EFLT_CTR_RE_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_EFLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_EFLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_ECTRL_EFLT_CTR_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_ECTRL_EFLT_CTR_RE_MASK) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_EFLT_CTR_FE_MASK (0x2000000U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_EFLT_CTR_FE_SHIFT (25U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_EFLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_EFLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_ECTRL_EFLT_CTR_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_ECTRL_EFLT_CTR_FE_MASK) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_SWAP_CAPTURE_MASK (0x10000000U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_SWAP_CAPTURE_SHIFT (28U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_SWAP_CAPTURE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_SWAP_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_ECTRL_SWAP_CAPTURE_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_ECTRL_SWAP_CAPTURE_MASK) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_IMM_START_MASK (0x20000000U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_IMM_START_SHIFT (29U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_IMM_START_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_IMM_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_ECTRL_IMM_START_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_ECTRL_IMM_START_MASK) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_ECLK_SEL_MASK (0x40000000U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_ECLK_SEL_SHIFT (30U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_ECLK_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_ECLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_ECTRL_ECLK_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_ECTRL_ECLK_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_USE_PREV_CH_IN_MASK (0x80000000U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_USE_PREV_CH_IN_SHIFT (31U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_USE_PREV_CH_IN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_ECTRL_USE_PREV_CH_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_ECTRL_USE_PREV_CH_IN_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_ECTRL_USE_PREV_CH_IN_MASK) /*! @} */ /*! @name TIM0_CH2_IRQ_NOTIFY - TIM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_NEWVAL_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_NEWVAL_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_NEWVAL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_NEWVAL_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_NEWVAL_MASK) #define GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_ECNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_ECNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_CNTOFL_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_CNTOFL_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_CNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_CNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_CNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_GPROFL_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_GPROFL_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_GPROFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_GPROFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_GPROFL_MASK) #define GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_TODET_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_TODET_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_TODET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_TODET_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_TODET_MASK) #define GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_GLITCHDET_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_IRQ_NOTIFY_GLITCHDET_MASK) /*! @} */ /*! @name TIM0_CH2_IRQ_EN - TIM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH2_IRQ_EN_NEWVAL_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_EN_NEWVAL_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_EN_NEWVAL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_EN_NEWVAL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_IRQ_EN_NEWVAL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_IRQ_EN_NEWVAL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH2_IRQ_EN_ECNTOFL_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_EN_ECNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_EN_ECNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_IRQ_EN_ECNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH2_IRQ_EN_CNTOFL_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_EN_CNTOFL_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_EN_CNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_EN_CNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_IRQ_EN_CNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_IRQ_EN_CNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH2_IRQ_EN_GPROFL_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_EN_GPROFL_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_EN_GPROFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_EN_GPROFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_IRQ_EN_GPROFL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_IRQ_EN_GPROFL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH2_IRQ_EN_TODET_IRQ_EN_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_EN_TODET_IRQ_EN_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_EN_TODET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_EN_TODET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_IRQ_EN_TODET_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_IRQ_EN_TODET_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH2_IRQ_EN_GLITCHDET_IRQ_EN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_EN_GLITCHDET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_EN_GLITCHDET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_IRQ_EN_GLITCHDET_IRQ_EN_MASK) /*! @} */ /*! @name TIM0_CH2_IRQ_FORCINT - TIM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_NEWVAL_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_NEWVAL_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_NEWVAL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_NEWVAL_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_NEWVAL_MASK) #define GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_ECNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_ECNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_CNTOFL_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_CNTOFL_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_CNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_CNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_CNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_GPROFL_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_GPROFL_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_GPROFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_GPROFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_GPROFL_MASK) #define GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_TODET_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_TODET_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_TODET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_TODET_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_TODET_MASK) #define GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_GLITCHDET_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_IRQ_FORCINT_TRG_GLITCHDET_MASK) /*! @} */ /*! @name TIM0_CH2_IRQ_MODE - TIM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH2_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH2_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TIM0_CH2_EIRQ_EN - TIM[i] channel [x] error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_NEWVAL_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_NEWVAL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_NEWVAL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_NEWVAL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_ECNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_ECNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_CNTOFL_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_CNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_CNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_CNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_GPROFL_EIRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_GPROFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_GPROFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_GPROFL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_TODET_EIRQ_EN_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_TODET_EIRQ_EN_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_TODET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_TODET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_TODET_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_TODET_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_GLITCHDET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_GLITCHDET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH2_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK) /*! @} */ /*! @name TIM0_CH3_GPR0 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH3_GPR0_GPR0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH3_GPR0_GPR0_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH3_GPR0_GPR0_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH3_GPR0_GPR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_GPR0_GPR0_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_GPR0_GPR0_MASK) #define GTM_gtm_cls0_TIM0_CH3_GPR0_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls0_TIM0_CH3_GPR0_ECNT_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH3_GPR0_ECNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH3_GPR0_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_GPR0_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_GPR0_ECNT_MASK) /*! @} */ /*! @name TIM0_CH3_GPR1 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH3_GPR1_GPR1_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH3_GPR1_GPR1_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH3_GPR1_GPR1_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH3_GPR1_GPR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_GPR1_GPR1_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_GPR1_GPR1_MASK) #define GTM_gtm_cls0_TIM0_CH3_GPR1_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls0_TIM0_CH3_GPR1_ECNT_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH3_GPR1_ECNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH3_GPR1_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_GPR1_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_GPR1_ECNT_MASK) /*! @} */ /*! @name TIM0_CH3_CNT - TIM[i] channel [x] SMU counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH3_CNT_CNT_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH3_CNT_CNT_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH3_CNT_CNT_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH3_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_CNT_CNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_CNT_CNT_MASK) /*! @} */ /*! @name TIM0_CH3_ECNT - TIM[i] channel [x] SMU edge counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH3_ECNT_ECNT_MASK (0xFFFFU) #define GTM_gtm_cls0_TIM0_CH3_ECNT_ECNT_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH3_ECNT_ECNT_WIDTH (16U) #define GTM_gtm_cls0_TIM0_CH3_ECNT_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_ECNT_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_ECNT_ECNT_MASK) /*! @} */ /*! @name TIM0_CH3_CNTS - TIM[i] channel [x] SMU shadow counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH3_CNTS_CNTS_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH3_CNTS_CNTS_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH3_CNTS_CNTS_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH3_CNTS_CNTS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_CNTS_CNTS_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_CNTS_CNTS_MASK) #define GTM_gtm_cls0_TIM0_CH3_CNTS_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls0_TIM0_CH3_CNTS_ECNT_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH3_CNTS_ECNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH3_CNTS_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_CNTS_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_CNTS_ECNT_MASK) /*! @} */ /*! @name TIM0_CH3_TDUC - TIM[i] channel [x] TDU counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH3_TDUC_TO_CNT_MASK (0xFFU) #define GTM_gtm_cls0_TIM0_CH3_TDUC_TO_CNT_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH3_TDUC_TO_CNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH3_TDUC_TO_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_TDUC_TO_CNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_TDUC_TO_CNT_MASK) #define GTM_gtm_cls0_TIM0_CH3_TDUC_TO_CNT1_MASK (0xFF00U) #define GTM_gtm_cls0_TIM0_CH3_TDUC_TO_CNT1_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH3_TDUC_TO_CNT1_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH3_TDUC_TO_CNT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_TDUC_TO_CNT1_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_TDUC_TO_CNT1_MASK) #define GTM_gtm_cls0_TIM0_CH3_TDUC_TO_CNT2_MASK (0xFF0000U) #define GTM_gtm_cls0_TIM0_CH3_TDUC_TO_CNT2_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH3_TDUC_TO_CNT2_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH3_TDUC_TO_CNT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_TDUC_TO_CNT2_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_TDUC_TO_CNT2_MASK) /*! @} */ /*! @name TIM0_CH3_TDUV - TIM[i] channel [x] TDU control register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH3_TDUV_TOV_MASK (0xFFU) #define GTM_gtm_cls0_TIM0_CH3_TDUV_TOV_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH3_TDUV_TOV_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH3_TDUV_TOV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_TDUV_TOV_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_TDUV_TOV_MASK) #define GTM_gtm_cls0_TIM0_CH3_TDUV_TOV1_MASK (0xFF00U) #define GTM_gtm_cls0_TIM0_CH3_TDUV_TOV1_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH3_TDUV_TOV1_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH3_TDUV_TOV1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_TDUV_TOV1_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_TDUV_TOV1_MASK) #define GTM_gtm_cls0_TIM0_CH3_TDUV_TOV2_MASK (0xFF0000U) #define GTM_gtm_cls0_TIM0_CH3_TDUV_TOV2_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH3_TDUV_TOV2_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH3_TDUV_TOV2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_TDUV_TOV2_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_TDUV_TOV2_MASK) #define GTM_gtm_cls0_TIM0_CH3_TDUV_SLICING_MASK (0x3000000U) #define GTM_gtm_cls0_TIM0_CH3_TDUV_SLICING_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH3_TDUV_SLICING_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH3_TDUV_SLICING(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_TDUV_SLICING_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_TDUV_SLICING_MASK) #define GTM_gtm_cls0_TIM0_CH3_TDUV_TCS_USE_SAMPLE_EVT_MASK (0x4000000U) #define GTM_gtm_cls0_TIM0_CH3_TDUV_TCS_USE_SAMPLE_EVT_SHIFT (26U) #define GTM_gtm_cls0_TIM0_CH3_TDUV_TCS_USE_SAMPLE_EVT_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_TDUV_TCS_USE_SAMPLE_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_TDUV_TCS_USE_SAMPLE_EVT_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_TDUV_TCS_USE_SAMPLE_EVT_MASK) #define GTM_gtm_cls0_TIM0_CH3_TDUV_TDU_SAME_CNT_CLK_MASK (0x8000000U) #define GTM_gtm_cls0_TIM0_CH3_TDUV_TDU_SAME_CNT_CLK_SHIFT (27U) #define GTM_gtm_cls0_TIM0_CH3_TDUV_TDU_SAME_CNT_CLK_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_TDUV_TDU_SAME_CNT_CLK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_TDUV_TDU_SAME_CNT_CLK_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_TDUV_TDU_SAME_CNT_CLK_MASK) #define GTM_gtm_cls0_TIM0_CH3_TDUV_TCS_MASK (0x70000000U) #define GTM_gtm_cls0_TIM0_CH3_TDUV_TCS_SHIFT (28U) #define GTM_gtm_cls0_TIM0_CH3_TDUV_TCS_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH3_TDUV_TCS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_TDUV_TCS_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_TDUV_TCS_MASK) /*! @} */ /*! @name TIM0_CH3_FLT_RE - TIM[i] channel [x] filter parameter 0 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH3_FLT_RE_FLT_RE_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH3_FLT_RE_FLT_RE_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH3_FLT_RE_FLT_RE_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH3_FLT_RE_FLT_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_FLT_RE_FLT_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_FLT_RE_FLT_RE_MASK) /*! @} */ /*! @name TIM0_CH3_FLT_FE - TIM[i] channel [x] filter parameter 1 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH3_FLT_FE_FLT_FE_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH3_FLT_FE_FLT_FE_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH3_FLT_FE_FLT_FE_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH3_FLT_FE_FLT_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_FLT_FE_FLT_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_FLT_FE_FLT_FE_MASK) /*! @} */ /*! @name TIM0_CH3_CTRL - TIM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH3_CTRL_TIM_EN_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_TIM_EN_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_TIM_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_TIM_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_CTRL_TIM_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_CTRL_TIM_EN_MASK) #define GTM_gtm_cls0_TIM0_CH3_CTRL_TIM_MODE_MASK (0xEU) #define GTM_gtm_cls0_TIM0_CH3_CTRL_TIM_MODE_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_TIM_MODE_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_TIM_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_CTRL_TIM_MODE_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_CTRL_TIM_MODE_MASK) #define GTM_gtm_cls0_TIM0_CH3_CTRL_OSM_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_OSM_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_CTRL_OSM_MASK) #define GTM_gtm_cls0_TIM0_CH3_CTRL_ARU_EN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_ARU_EN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_CTRL_ARU_EN_MASK) #define GTM_gtm_cls0_TIM0_CH3_CTRL_CICTRL_MASK (0x40U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_CICTRL_SHIFT (6U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_CICTRL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_CICTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_CTRL_CICTRL_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_CTRL_CICTRL_MASK) #define GTM_gtm_cls0_TIM0_CH3_CTRL_TBU0_SEL_MASK (0x80U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_TBU0_SEL_SHIFT (7U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_TBU0_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_TBU0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_CTRL_TBU0_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_CTRL_TBU0_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH3_CTRL_GPR0_SEL_MASK (0x300U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_GPR0_SEL_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_GPR0_SEL_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_GPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_CTRL_GPR0_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_CTRL_GPR0_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH3_CTRL_GPR1_SEL_MASK (0xC00U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_GPR1_SEL_SHIFT (10U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_GPR1_SEL_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_GPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_CTRL_GPR1_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_CTRL_GPR1_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH3_CTRL_CNTS_SEL_MASK (0x1000U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_CNTS_SEL_SHIFT (12U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_CNTS_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_CNTS_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_CTRL_CNTS_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_CTRL_CNTS_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH3_CTRL_DSL_MASK (0x2000U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_DSL_SHIFT (13U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_DSL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_CTRL_DSL_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_CTRL_DSL_MASK) #define GTM_gtm_cls0_TIM0_CH3_CTRL_ISL_MASK (0x4000U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_ISL_SHIFT (14U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_ISL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_ISL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_CTRL_ISL_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_CTRL_ISL_MASK) #define GTM_gtm_cls0_TIM0_CH3_CTRL_ECNT_RESET_MASK (0x8000U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_ECNT_RESET_SHIFT (15U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_ECNT_RESET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_ECNT_RESET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_CTRL_ECNT_RESET_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_CTRL_ECNT_RESET_MASK) #define GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_EN_MASK (0x10000U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_EN_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_EN_MASK) #define GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_CNT_FRQ_MASK (0x60000U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_CNT_FRQ_SHIFT (17U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_CNT_FRQ_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_CNT_FRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_CNT_FRQ_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_CNT_FRQ_MASK) #define GTM_gtm_cls0_TIM0_CH3_CTRL_EXT_CAP_EN_MASK (0x80000U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_EXT_CAP_EN_SHIFT (19U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_EXT_CAP_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_EXT_CAP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_CTRL_EXT_CAP_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_CTRL_EXT_CAP_EN_MASK) #define GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_MODE_RE_MASK (0x100000U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_MODE_RE_SHIFT (20U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_MODE_RE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_MODE_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_MODE_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_MODE_RE_MASK) #define GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_CTR_RE_MASK (0x200000U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_CTR_RE_SHIFT (21U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_CTR_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_CTR_RE_MASK) #define GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_MODE_FE_MASK (0x400000U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_MODE_FE_SHIFT (22U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_MODE_FE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_MODE_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_MODE_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_MODE_FE_MASK) #define GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_CTR_FE_MASK (0x800000U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_CTR_FE_SHIFT (23U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_CTR_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_CTRL_FLT_CTR_FE_MASK) #define GTM_gtm_cls0_TIM0_CH3_CTRL_CLK_SEL_MASK (0x7000000U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_CLK_SEL_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_CLK_SEL_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_CTRL_CLK_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_CTRL_CLK_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH3_CTRL_FR_ECNT_OFL_MASK (0x8000000U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_FR_ECNT_OFL_SHIFT (27U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_FR_ECNT_OFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_FR_ECNT_OFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_CTRL_FR_ECNT_OFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_CTRL_FR_ECNT_OFL_MASK) #define GTM_gtm_cls0_TIM0_CH3_CTRL_EGPR0_SEL_MASK (0x10000000U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_EGPR0_SEL_SHIFT (28U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_EGPR0_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_EGPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_CTRL_EGPR0_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_CTRL_EGPR0_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH3_CTRL_EGPR1_SEL_MASK (0x20000000U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_EGPR1_SEL_SHIFT (29U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_EGPR1_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_EGPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_CTRL_EGPR1_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_CTRL_EGPR1_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH3_CTRL_TOCTRL_MASK (0xC0000000U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_TOCTRL_SHIFT (30U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_TOCTRL_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH3_CTRL_TOCTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_CTRL_TOCTRL_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_CTRL_TOCTRL_MASK) /*! @} */ /*! @name TIM0_CH3_ECTRL - TIM[i] channel [x] extended control register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH3_ECTRL_EXT_CAP_SRC_MASK (0xFU) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_EXT_CAP_SRC_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_EXT_CAP_SRC_WIDTH (4U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_EXT_CAP_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_ECTRL_EXT_CAP_SRC_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_ECTRL_EXT_CAP_SRC_MASK) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_USE_PREV_TDU_IN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_USE_PREV_TDU_IN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_USE_PREV_TDU_IN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_USE_PREV_TDU_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_ECTRL_USE_PREV_TDU_IN_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_ECTRL_USE_PREV_TDU_IN_MASK) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_TODET_IRQ_SRC_MASK (0xC0U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_TODET_IRQ_SRC_SHIFT (6U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_TODET_IRQ_SRC_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_TODET_IRQ_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_ECTRL_TODET_IRQ_SRC_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_ECTRL_TODET_IRQ_SRC_MASK) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_TDU_START_MASK (0x700U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_TDU_START_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_TDU_START_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_TDU_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_ECTRL_TDU_START_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_ECTRL_TDU_START_MASK) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_TDU_STOP_MASK (0x7000U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_TDU_STOP_SHIFT (12U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_TDU_STOP_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_TDU_STOP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_ECTRL_TDU_STOP_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_ECTRL_TDU_STOP_MASK) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_TDU_RESYNC_MASK (0xF0000U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_TDU_RESYNC_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_TDU_RESYNC_WIDTH (4U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_TDU_RESYNC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_ECTRL_TDU_RESYNC_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_ECTRL_TDU_RESYNC_MASK) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_USE_LUT_MASK (0xC00000U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_USE_LUT_SHIFT (22U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_USE_LUT_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_USE_LUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_ECTRL_USE_LUT_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_ECTRL_USE_LUT_MASK) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_EFLT_CTR_RE_MASK (0x1000000U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_EFLT_CTR_RE_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_EFLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_EFLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_ECTRL_EFLT_CTR_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_ECTRL_EFLT_CTR_RE_MASK) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_EFLT_CTR_FE_MASK (0x2000000U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_EFLT_CTR_FE_SHIFT (25U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_EFLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_EFLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_ECTRL_EFLT_CTR_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_ECTRL_EFLT_CTR_FE_MASK) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_SWAP_CAPTURE_MASK (0x10000000U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_SWAP_CAPTURE_SHIFT (28U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_SWAP_CAPTURE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_SWAP_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_ECTRL_SWAP_CAPTURE_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_ECTRL_SWAP_CAPTURE_MASK) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_IMM_START_MASK (0x20000000U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_IMM_START_SHIFT (29U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_IMM_START_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_IMM_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_ECTRL_IMM_START_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_ECTRL_IMM_START_MASK) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_ECLK_SEL_MASK (0x40000000U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_ECLK_SEL_SHIFT (30U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_ECLK_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_ECLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_ECTRL_ECLK_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_ECTRL_ECLK_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_USE_PREV_CH_IN_MASK (0x80000000U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_USE_PREV_CH_IN_SHIFT (31U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_USE_PREV_CH_IN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_ECTRL_USE_PREV_CH_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_ECTRL_USE_PREV_CH_IN_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_ECTRL_USE_PREV_CH_IN_MASK) /*! @} */ /*! @name TIM0_CH3_IRQ_NOTIFY - TIM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_NEWVAL_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_NEWVAL_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_NEWVAL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_NEWVAL_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_NEWVAL_MASK) #define GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_ECNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_ECNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_CNTOFL_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_CNTOFL_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_CNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_CNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_CNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_GPROFL_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_GPROFL_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_GPROFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_GPROFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_GPROFL_MASK) #define GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_TODET_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_TODET_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_TODET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_TODET_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_TODET_MASK) #define GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_GLITCHDET_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_IRQ_NOTIFY_GLITCHDET_MASK) /*! @} */ /*! @name TIM0_CH3_IRQ_EN - TIM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH3_IRQ_EN_NEWVAL_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_EN_NEWVAL_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_EN_NEWVAL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_EN_NEWVAL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_IRQ_EN_NEWVAL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_IRQ_EN_NEWVAL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH3_IRQ_EN_ECNTOFL_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_EN_ECNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_EN_ECNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_IRQ_EN_ECNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH3_IRQ_EN_CNTOFL_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_EN_CNTOFL_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_EN_CNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_EN_CNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_IRQ_EN_CNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_IRQ_EN_CNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH3_IRQ_EN_GPROFL_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_EN_GPROFL_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_EN_GPROFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_EN_GPROFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_IRQ_EN_GPROFL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_IRQ_EN_GPROFL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH3_IRQ_EN_TODET_IRQ_EN_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_EN_TODET_IRQ_EN_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_EN_TODET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_EN_TODET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_IRQ_EN_TODET_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_IRQ_EN_TODET_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH3_IRQ_EN_GLITCHDET_IRQ_EN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_EN_GLITCHDET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_EN_GLITCHDET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_IRQ_EN_GLITCHDET_IRQ_EN_MASK) /*! @} */ /*! @name TIM0_CH3_IRQ_FORCINT - TIM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_NEWVAL_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_NEWVAL_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_NEWVAL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_NEWVAL_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_NEWVAL_MASK) #define GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_ECNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_ECNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_CNTOFL_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_CNTOFL_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_CNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_CNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_CNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_GPROFL_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_GPROFL_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_GPROFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_GPROFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_GPROFL_MASK) #define GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_TODET_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_TODET_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_TODET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_TODET_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_TODET_MASK) #define GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_GLITCHDET_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_IRQ_FORCINT_TRG_GLITCHDET_MASK) /*! @} */ /*! @name TIM0_CH3_IRQ_MODE - TIM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH3_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH3_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TIM0_CH3_EIRQ_EN - TIM[i] channel [x] error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_NEWVAL_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_NEWVAL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_NEWVAL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_NEWVAL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_ECNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_ECNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_CNTOFL_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_CNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_CNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_CNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_GPROFL_EIRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_GPROFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_GPROFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_GPROFL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_TODET_EIRQ_EN_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_TODET_EIRQ_EN_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_TODET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_TODET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_TODET_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_TODET_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_GLITCHDET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_GLITCHDET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH3_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK) /*! @} */ /*! @name TIM0_CH4_GPR0 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH4_GPR0_GPR0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH4_GPR0_GPR0_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH4_GPR0_GPR0_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH4_GPR0_GPR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_GPR0_GPR0_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_GPR0_GPR0_MASK) #define GTM_gtm_cls0_TIM0_CH4_GPR0_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls0_TIM0_CH4_GPR0_ECNT_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH4_GPR0_ECNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH4_GPR0_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_GPR0_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_GPR0_ECNT_MASK) /*! @} */ /*! @name TIM0_CH4_GPR1 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH4_GPR1_GPR1_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH4_GPR1_GPR1_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH4_GPR1_GPR1_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH4_GPR1_GPR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_GPR1_GPR1_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_GPR1_GPR1_MASK) #define GTM_gtm_cls0_TIM0_CH4_GPR1_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls0_TIM0_CH4_GPR1_ECNT_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH4_GPR1_ECNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH4_GPR1_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_GPR1_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_GPR1_ECNT_MASK) /*! @} */ /*! @name TIM0_CH4_CNT - TIM[i] channel [x] SMU counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH4_CNT_CNT_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH4_CNT_CNT_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH4_CNT_CNT_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH4_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_CNT_CNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_CNT_CNT_MASK) /*! @} */ /*! @name TIM0_CH4_ECNT - TIM[i] channel [x] SMU edge counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH4_ECNT_ECNT_MASK (0xFFFFU) #define GTM_gtm_cls0_TIM0_CH4_ECNT_ECNT_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH4_ECNT_ECNT_WIDTH (16U) #define GTM_gtm_cls0_TIM0_CH4_ECNT_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_ECNT_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_ECNT_ECNT_MASK) /*! @} */ /*! @name TIM0_CH4_CNTS - TIM[i] channel [x] SMU shadow counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH4_CNTS_CNTS_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH4_CNTS_CNTS_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH4_CNTS_CNTS_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH4_CNTS_CNTS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_CNTS_CNTS_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_CNTS_CNTS_MASK) #define GTM_gtm_cls0_TIM0_CH4_CNTS_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls0_TIM0_CH4_CNTS_ECNT_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH4_CNTS_ECNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH4_CNTS_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_CNTS_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_CNTS_ECNT_MASK) /*! @} */ /*! @name TIM0_CH4_TDUC - TIM[i] channel [x] TDU counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH4_TDUC_TO_CNT_MASK (0xFFU) #define GTM_gtm_cls0_TIM0_CH4_TDUC_TO_CNT_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH4_TDUC_TO_CNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH4_TDUC_TO_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_TDUC_TO_CNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_TDUC_TO_CNT_MASK) #define GTM_gtm_cls0_TIM0_CH4_TDUC_TO_CNT1_MASK (0xFF00U) #define GTM_gtm_cls0_TIM0_CH4_TDUC_TO_CNT1_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH4_TDUC_TO_CNT1_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH4_TDUC_TO_CNT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_TDUC_TO_CNT1_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_TDUC_TO_CNT1_MASK) #define GTM_gtm_cls0_TIM0_CH4_TDUC_TO_CNT2_MASK (0xFF0000U) #define GTM_gtm_cls0_TIM0_CH4_TDUC_TO_CNT2_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH4_TDUC_TO_CNT2_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH4_TDUC_TO_CNT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_TDUC_TO_CNT2_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_TDUC_TO_CNT2_MASK) /*! @} */ /*! @name TIM0_CH4_TDUV - TIM[i] channel [x] TDU control register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH4_TDUV_TOV_MASK (0xFFU) #define GTM_gtm_cls0_TIM0_CH4_TDUV_TOV_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH4_TDUV_TOV_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH4_TDUV_TOV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_TDUV_TOV_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_TDUV_TOV_MASK) #define GTM_gtm_cls0_TIM0_CH4_TDUV_TOV1_MASK (0xFF00U) #define GTM_gtm_cls0_TIM0_CH4_TDUV_TOV1_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH4_TDUV_TOV1_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH4_TDUV_TOV1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_TDUV_TOV1_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_TDUV_TOV1_MASK) #define GTM_gtm_cls0_TIM0_CH4_TDUV_TOV2_MASK (0xFF0000U) #define GTM_gtm_cls0_TIM0_CH4_TDUV_TOV2_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH4_TDUV_TOV2_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH4_TDUV_TOV2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_TDUV_TOV2_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_TDUV_TOV2_MASK) #define GTM_gtm_cls0_TIM0_CH4_TDUV_SLICING_MASK (0x3000000U) #define GTM_gtm_cls0_TIM0_CH4_TDUV_SLICING_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH4_TDUV_SLICING_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH4_TDUV_SLICING(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_TDUV_SLICING_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_TDUV_SLICING_MASK) #define GTM_gtm_cls0_TIM0_CH4_TDUV_TCS_USE_SAMPLE_EVT_MASK (0x4000000U) #define GTM_gtm_cls0_TIM0_CH4_TDUV_TCS_USE_SAMPLE_EVT_SHIFT (26U) #define GTM_gtm_cls0_TIM0_CH4_TDUV_TCS_USE_SAMPLE_EVT_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_TDUV_TCS_USE_SAMPLE_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_TDUV_TCS_USE_SAMPLE_EVT_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_TDUV_TCS_USE_SAMPLE_EVT_MASK) #define GTM_gtm_cls0_TIM0_CH4_TDUV_TDU_SAME_CNT_CLK_MASK (0x8000000U) #define GTM_gtm_cls0_TIM0_CH4_TDUV_TDU_SAME_CNT_CLK_SHIFT (27U) #define GTM_gtm_cls0_TIM0_CH4_TDUV_TDU_SAME_CNT_CLK_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_TDUV_TDU_SAME_CNT_CLK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_TDUV_TDU_SAME_CNT_CLK_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_TDUV_TDU_SAME_CNT_CLK_MASK) #define GTM_gtm_cls0_TIM0_CH4_TDUV_TCS_MASK (0x70000000U) #define GTM_gtm_cls0_TIM0_CH4_TDUV_TCS_SHIFT (28U) #define GTM_gtm_cls0_TIM0_CH4_TDUV_TCS_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH4_TDUV_TCS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_TDUV_TCS_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_TDUV_TCS_MASK) /*! @} */ /*! @name TIM0_CH4_FLT_RE - TIM[i] channel [x] filter parameter 0 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH4_FLT_RE_FLT_RE_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH4_FLT_RE_FLT_RE_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH4_FLT_RE_FLT_RE_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH4_FLT_RE_FLT_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_FLT_RE_FLT_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_FLT_RE_FLT_RE_MASK) /*! @} */ /*! @name TIM0_CH4_FLT_FE - TIM[i] channel [x] filter parameter 1 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH4_FLT_FE_FLT_FE_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH4_FLT_FE_FLT_FE_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH4_FLT_FE_FLT_FE_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH4_FLT_FE_FLT_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_FLT_FE_FLT_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_FLT_FE_FLT_FE_MASK) /*! @} */ /*! @name TIM0_CH4_CTRL - TIM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH4_CTRL_TIM_EN_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_TIM_EN_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_TIM_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_TIM_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_CTRL_TIM_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_CTRL_TIM_EN_MASK) #define GTM_gtm_cls0_TIM0_CH4_CTRL_TIM_MODE_MASK (0xEU) #define GTM_gtm_cls0_TIM0_CH4_CTRL_TIM_MODE_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_TIM_MODE_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_TIM_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_CTRL_TIM_MODE_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_CTRL_TIM_MODE_MASK) #define GTM_gtm_cls0_TIM0_CH4_CTRL_OSM_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_OSM_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_CTRL_OSM_MASK) #define GTM_gtm_cls0_TIM0_CH4_CTRL_ARU_EN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_ARU_EN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_CTRL_ARU_EN_MASK) #define GTM_gtm_cls0_TIM0_CH4_CTRL_CICTRL_MASK (0x40U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_CICTRL_SHIFT (6U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_CICTRL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_CICTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_CTRL_CICTRL_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_CTRL_CICTRL_MASK) #define GTM_gtm_cls0_TIM0_CH4_CTRL_TBU0_SEL_MASK (0x80U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_TBU0_SEL_SHIFT (7U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_TBU0_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_TBU0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_CTRL_TBU0_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_CTRL_TBU0_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH4_CTRL_GPR0_SEL_MASK (0x300U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_GPR0_SEL_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_GPR0_SEL_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_GPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_CTRL_GPR0_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_CTRL_GPR0_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH4_CTRL_GPR1_SEL_MASK (0xC00U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_GPR1_SEL_SHIFT (10U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_GPR1_SEL_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_GPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_CTRL_GPR1_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_CTRL_GPR1_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH4_CTRL_CNTS_SEL_MASK (0x1000U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_CNTS_SEL_SHIFT (12U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_CNTS_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_CNTS_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_CTRL_CNTS_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_CTRL_CNTS_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH4_CTRL_DSL_MASK (0x2000U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_DSL_SHIFT (13U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_DSL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_CTRL_DSL_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_CTRL_DSL_MASK) #define GTM_gtm_cls0_TIM0_CH4_CTRL_ISL_MASK (0x4000U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_ISL_SHIFT (14U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_ISL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_ISL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_CTRL_ISL_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_CTRL_ISL_MASK) #define GTM_gtm_cls0_TIM0_CH4_CTRL_ECNT_RESET_MASK (0x8000U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_ECNT_RESET_SHIFT (15U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_ECNT_RESET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_ECNT_RESET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_CTRL_ECNT_RESET_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_CTRL_ECNT_RESET_MASK) #define GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_EN_MASK (0x10000U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_EN_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_EN_MASK) #define GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_CNT_FRQ_MASK (0x60000U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_CNT_FRQ_SHIFT (17U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_CNT_FRQ_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_CNT_FRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_CNT_FRQ_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_CNT_FRQ_MASK) #define GTM_gtm_cls0_TIM0_CH4_CTRL_EXT_CAP_EN_MASK (0x80000U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_EXT_CAP_EN_SHIFT (19U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_EXT_CAP_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_EXT_CAP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_CTRL_EXT_CAP_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_CTRL_EXT_CAP_EN_MASK) #define GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_MODE_RE_MASK (0x100000U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_MODE_RE_SHIFT (20U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_MODE_RE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_MODE_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_MODE_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_MODE_RE_MASK) #define GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_CTR_RE_MASK (0x200000U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_CTR_RE_SHIFT (21U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_CTR_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_CTR_RE_MASK) #define GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_MODE_FE_MASK (0x400000U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_MODE_FE_SHIFT (22U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_MODE_FE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_MODE_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_MODE_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_MODE_FE_MASK) #define GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_CTR_FE_MASK (0x800000U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_CTR_FE_SHIFT (23U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_CTR_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_CTRL_FLT_CTR_FE_MASK) #define GTM_gtm_cls0_TIM0_CH4_CTRL_CLK_SEL_MASK (0x7000000U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_CLK_SEL_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_CLK_SEL_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_CTRL_CLK_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_CTRL_CLK_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH4_CTRL_FR_ECNT_OFL_MASK (0x8000000U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_FR_ECNT_OFL_SHIFT (27U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_FR_ECNT_OFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_FR_ECNT_OFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_CTRL_FR_ECNT_OFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_CTRL_FR_ECNT_OFL_MASK) #define GTM_gtm_cls0_TIM0_CH4_CTRL_EGPR0_SEL_MASK (0x10000000U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_EGPR0_SEL_SHIFT (28U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_EGPR0_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_EGPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_CTRL_EGPR0_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_CTRL_EGPR0_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH4_CTRL_EGPR1_SEL_MASK (0x20000000U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_EGPR1_SEL_SHIFT (29U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_EGPR1_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_EGPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_CTRL_EGPR1_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_CTRL_EGPR1_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH4_CTRL_TOCTRL_MASK (0xC0000000U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_TOCTRL_SHIFT (30U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_TOCTRL_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH4_CTRL_TOCTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_CTRL_TOCTRL_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_CTRL_TOCTRL_MASK) /*! @} */ /*! @name TIM0_CH4_ECTRL - TIM[i] channel [x] extended control register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH4_ECTRL_EXT_CAP_SRC_MASK (0xFU) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_EXT_CAP_SRC_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_EXT_CAP_SRC_WIDTH (4U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_EXT_CAP_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_ECTRL_EXT_CAP_SRC_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_ECTRL_EXT_CAP_SRC_MASK) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_USE_PREV_TDU_IN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_USE_PREV_TDU_IN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_USE_PREV_TDU_IN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_USE_PREV_TDU_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_ECTRL_USE_PREV_TDU_IN_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_ECTRL_USE_PREV_TDU_IN_MASK) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_TODET_IRQ_SRC_MASK (0xC0U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_TODET_IRQ_SRC_SHIFT (6U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_TODET_IRQ_SRC_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_TODET_IRQ_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_ECTRL_TODET_IRQ_SRC_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_ECTRL_TODET_IRQ_SRC_MASK) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_TDU_START_MASK (0x700U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_TDU_START_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_TDU_START_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_TDU_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_ECTRL_TDU_START_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_ECTRL_TDU_START_MASK) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_TDU_STOP_MASK (0x7000U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_TDU_STOP_SHIFT (12U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_TDU_STOP_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_TDU_STOP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_ECTRL_TDU_STOP_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_ECTRL_TDU_STOP_MASK) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_TDU_RESYNC_MASK (0xF0000U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_TDU_RESYNC_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_TDU_RESYNC_WIDTH (4U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_TDU_RESYNC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_ECTRL_TDU_RESYNC_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_ECTRL_TDU_RESYNC_MASK) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_USE_LUT_MASK (0xC00000U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_USE_LUT_SHIFT (22U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_USE_LUT_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_USE_LUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_ECTRL_USE_LUT_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_ECTRL_USE_LUT_MASK) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_EFLT_CTR_RE_MASK (0x1000000U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_EFLT_CTR_RE_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_EFLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_EFLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_ECTRL_EFLT_CTR_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_ECTRL_EFLT_CTR_RE_MASK) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_EFLT_CTR_FE_MASK (0x2000000U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_EFLT_CTR_FE_SHIFT (25U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_EFLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_EFLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_ECTRL_EFLT_CTR_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_ECTRL_EFLT_CTR_FE_MASK) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_SWAP_CAPTURE_MASK (0x10000000U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_SWAP_CAPTURE_SHIFT (28U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_SWAP_CAPTURE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_SWAP_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_ECTRL_SWAP_CAPTURE_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_ECTRL_SWAP_CAPTURE_MASK) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_IMM_START_MASK (0x20000000U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_IMM_START_SHIFT (29U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_IMM_START_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_IMM_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_ECTRL_IMM_START_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_ECTRL_IMM_START_MASK) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_ECLK_SEL_MASK (0x40000000U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_ECLK_SEL_SHIFT (30U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_ECLK_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_ECLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_ECTRL_ECLK_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_ECTRL_ECLK_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_USE_PREV_CH_IN_MASK (0x80000000U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_USE_PREV_CH_IN_SHIFT (31U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_USE_PREV_CH_IN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_ECTRL_USE_PREV_CH_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_ECTRL_USE_PREV_CH_IN_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_ECTRL_USE_PREV_CH_IN_MASK) /*! @} */ /*! @name TIM0_CH4_IRQ_NOTIFY - TIM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_NEWVAL_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_NEWVAL_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_NEWVAL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_NEWVAL_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_NEWVAL_MASK) #define GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_ECNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_ECNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_CNTOFL_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_CNTOFL_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_CNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_CNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_CNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_GPROFL_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_GPROFL_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_GPROFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_GPROFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_GPROFL_MASK) #define GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_TODET_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_TODET_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_TODET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_TODET_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_TODET_MASK) #define GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_GLITCHDET_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_IRQ_NOTIFY_GLITCHDET_MASK) /*! @} */ /*! @name TIM0_CH4_IRQ_EN - TIM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH4_IRQ_EN_NEWVAL_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_EN_NEWVAL_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_EN_NEWVAL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_EN_NEWVAL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_IRQ_EN_NEWVAL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_IRQ_EN_NEWVAL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH4_IRQ_EN_ECNTOFL_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_EN_ECNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_EN_ECNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_IRQ_EN_ECNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH4_IRQ_EN_CNTOFL_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_EN_CNTOFL_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_EN_CNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_EN_CNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_IRQ_EN_CNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_IRQ_EN_CNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH4_IRQ_EN_GPROFL_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_EN_GPROFL_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_EN_GPROFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_EN_GPROFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_IRQ_EN_GPROFL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_IRQ_EN_GPROFL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH4_IRQ_EN_TODET_IRQ_EN_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_EN_TODET_IRQ_EN_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_EN_TODET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_EN_TODET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_IRQ_EN_TODET_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_IRQ_EN_TODET_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH4_IRQ_EN_GLITCHDET_IRQ_EN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_EN_GLITCHDET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_EN_GLITCHDET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_IRQ_EN_GLITCHDET_IRQ_EN_MASK) /*! @} */ /*! @name TIM0_CH4_IRQ_FORCINT - TIM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_NEWVAL_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_NEWVAL_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_NEWVAL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_NEWVAL_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_NEWVAL_MASK) #define GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_ECNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_ECNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_CNTOFL_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_CNTOFL_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_CNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_CNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_CNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_GPROFL_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_GPROFL_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_GPROFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_GPROFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_GPROFL_MASK) #define GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_TODET_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_TODET_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_TODET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_TODET_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_TODET_MASK) #define GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_GLITCHDET_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_IRQ_FORCINT_TRG_GLITCHDET_MASK) /*! @} */ /*! @name TIM0_CH4_IRQ_MODE - TIM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH4_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH4_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TIM0_CH4_EIRQ_EN - TIM[i] channel [x] error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_NEWVAL_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_NEWVAL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_NEWVAL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_NEWVAL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_ECNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_ECNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_CNTOFL_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_CNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_CNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_CNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_GPROFL_EIRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_GPROFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_GPROFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_GPROFL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_TODET_EIRQ_EN_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_TODET_EIRQ_EN_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_TODET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_TODET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_TODET_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_TODET_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_GLITCHDET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_GLITCHDET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH4_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK) /*! @} */ /*! @name TIM0_CH5_GPR0 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH5_GPR0_GPR0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH5_GPR0_GPR0_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH5_GPR0_GPR0_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH5_GPR0_GPR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_GPR0_GPR0_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_GPR0_GPR0_MASK) #define GTM_gtm_cls0_TIM0_CH5_GPR0_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls0_TIM0_CH5_GPR0_ECNT_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH5_GPR0_ECNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH5_GPR0_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_GPR0_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_GPR0_ECNT_MASK) /*! @} */ /*! @name TIM0_CH5_GPR1 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH5_GPR1_GPR1_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH5_GPR1_GPR1_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH5_GPR1_GPR1_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH5_GPR1_GPR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_GPR1_GPR1_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_GPR1_GPR1_MASK) #define GTM_gtm_cls0_TIM0_CH5_GPR1_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls0_TIM0_CH5_GPR1_ECNT_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH5_GPR1_ECNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH5_GPR1_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_GPR1_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_GPR1_ECNT_MASK) /*! @} */ /*! @name TIM0_CH5_CNT - TIM[i] channel [x] SMU counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH5_CNT_CNT_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH5_CNT_CNT_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH5_CNT_CNT_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH5_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_CNT_CNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_CNT_CNT_MASK) /*! @} */ /*! @name TIM0_CH5_ECNT - TIM[i] channel [x] SMU edge counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH5_ECNT_ECNT_MASK (0xFFFFU) #define GTM_gtm_cls0_TIM0_CH5_ECNT_ECNT_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH5_ECNT_ECNT_WIDTH (16U) #define GTM_gtm_cls0_TIM0_CH5_ECNT_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_ECNT_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_ECNT_ECNT_MASK) /*! @} */ /*! @name TIM0_CH5_CNTS - TIM[i] channel [x] SMU shadow counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH5_CNTS_CNTS_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH5_CNTS_CNTS_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH5_CNTS_CNTS_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH5_CNTS_CNTS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_CNTS_CNTS_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_CNTS_CNTS_MASK) #define GTM_gtm_cls0_TIM0_CH5_CNTS_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls0_TIM0_CH5_CNTS_ECNT_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH5_CNTS_ECNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH5_CNTS_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_CNTS_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_CNTS_ECNT_MASK) /*! @} */ /*! @name TIM0_CH5_TDUC - TIM[i] channel [x] TDU counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH5_TDUC_TO_CNT_MASK (0xFFU) #define GTM_gtm_cls0_TIM0_CH5_TDUC_TO_CNT_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH5_TDUC_TO_CNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH5_TDUC_TO_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_TDUC_TO_CNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_TDUC_TO_CNT_MASK) #define GTM_gtm_cls0_TIM0_CH5_TDUC_TO_CNT1_MASK (0xFF00U) #define GTM_gtm_cls0_TIM0_CH5_TDUC_TO_CNT1_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH5_TDUC_TO_CNT1_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH5_TDUC_TO_CNT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_TDUC_TO_CNT1_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_TDUC_TO_CNT1_MASK) #define GTM_gtm_cls0_TIM0_CH5_TDUC_TO_CNT2_MASK (0xFF0000U) #define GTM_gtm_cls0_TIM0_CH5_TDUC_TO_CNT2_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH5_TDUC_TO_CNT2_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH5_TDUC_TO_CNT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_TDUC_TO_CNT2_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_TDUC_TO_CNT2_MASK) /*! @} */ /*! @name TIM0_CH5_TDUV - TIM[i] channel [x] TDU control register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH5_TDUV_TOV_MASK (0xFFU) #define GTM_gtm_cls0_TIM0_CH5_TDUV_TOV_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH5_TDUV_TOV_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH5_TDUV_TOV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_TDUV_TOV_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_TDUV_TOV_MASK) #define GTM_gtm_cls0_TIM0_CH5_TDUV_TOV1_MASK (0xFF00U) #define GTM_gtm_cls0_TIM0_CH5_TDUV_TOV1_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH5_TDUV_TOV1_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH5_TDUV_TOV1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_TDUV_TOV1_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_TDUV_TOV1_MASK) #define GTM_gtm_cls0_TIM0_CH5_TDUV_TOV2_MASK (0xFF0000U) #define GTM_gtm_cls0_TIM0_CH5_TDUV_TOV2_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH5_TDUV_TOV2_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH5_TDUV_TOV2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_TDUV_TOV2_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_TDUV_TOV2_MASK) #define GTM_gtm_cls0_TIM0_CH5_TDUV_SLICING_MASK (0x3000000U) #define GTM_gtm_cls0_TIM0_CH5_TDUV_SLICING_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH5_TDUV_SLICING_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH5_TDUV_SLICING(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_TDUV_SLICING_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_TDUV_SLICING_MASK) #define GTM_gtm_cls0_TIM0_CH5_TDUV_TCS_USE_SAMPLE_EVT_MASK (0x4000000U) #define GTM_gtm_cls0_TIM0_CH5_TDUV_TCS_USE_SAMPLE_EVT_SHIFT (26U) #define GTM_gtm_cls0_TIM0_CH5_TDUV_TCS_USE_SAMPLE_EVT_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_TDUV_TCS_USE_SAMPLE_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_TDUV_TCS_USE_SAMPLE_EVT_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_TDUV_TCS_USE_SAMPLE_EVT_MASK) #define GTM_gtm_cls0_TIM0_CH5_TDUV_TDU_SAME_CNT_CLK_MASK (0x8000000U) #define GTM_gtm_cls0_TIM0_CH5_TDUV_TDU_SAME_CNT_CLK_SHIFT (27U) #define GTM_gtm_cls0_TIM0_CH5_TDUV_TDU_SAME_CNT_CLK_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_TDUV_TDU_SAME_CNT_CLK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_TDUV_TDU_SAME_CNT_CLK_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_TDUV_TDU_SAME_CNT_CLK_MASK) #define GTM_gtm_cls0_TIM0_CH5_TDUV_TCS_MASK (0x70000000U) #define GTM_gtm_cls0_TIM0_CH5_TDUV_TCS_SHIFT (28U) #define GTM_gtm_cls0_TIM0_CH5_TDUV_TCS_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH5_TDUV_TCS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_TDUV_TCS_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_TDUV_TCS_MASK) /*! @} */ /*! @name TIM0_CH5_FLT_RE - TIM[i] channel [x] filter parameter 0 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH5_FLT_RE_FLT_RE_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH5_FLT_RE_FLT_RE_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH5_FLT_RE_FLT_RE_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH5_FLT_RE_FLT_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_FLT_RE_FLT_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_FLT_RE_FLT_RE_MASK) /*! @} */ /*! @name TIM0_CH5_FLT_FE - TIM[i] channel [x] filter parameter 1 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH5_FLT_FE_FLT_FE_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH5_FLT_FE_FLT_FE_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH5_FLT_FE_FLT_FE_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH5_FLT_FE_FLT_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_FLT_FE_FLT_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_FLT_FE_FLT_FE_MASK) /*! @} */ /*! @name TIM0_CH5_CTRL - TIM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH5_CTRL_TIM_EN_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_TIM_EN_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_TIM_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_TIM_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_CTRL_TIM_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_CTRL_TIM_EN_MASK) #define GTM_gtm_cls0_TIM0_CH5_CTRL_TIM_MODE_MASK (0xEU) #define GTM_gtm_cls0_TIM0_CH5_CTRL_TIM_MODE_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_TIM_MODE_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_TIM_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_CTRL_TIM_MODE_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_CTRL_TIM_MODE_MASK) #define GTM_gtm_cls0_TIM0_CH5_CTRL_OSM_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_OSM_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_CTRL_OSM_MASK) #define GTM_gtm_cls0_TIM0_CH5_CTRL_ARU_EN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_ARU_EN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_CTRL_ARU_EN_MASK) #define GTM_gtm_cls0_TIM0_CH5_CTRL_CICTRL_MASK (0x40U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_CICTRL_SHIFT (6U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_CICTRL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_CICTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_CTRL_CICTRL_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_CTRL_CICTRL_MASK) #define GTM_gtm_cls0_TIM0_CH5_CTRL_TBU0_SEL_MASK (0x80U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_TBU0_SEL_SHIFT (7U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_TBU0_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_TBU0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_CTRL_TBU0_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_CTRL_TBU0_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH5_CTRL_GPR0_SEL_MASK (0x300U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_GPR0_SEL_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_GPR0_SEL_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_GPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_CTRL_GPR0_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_CTRL_GPR0_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH5_CTRL_GPR1_SEL_MASK (0xC00U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_GPR1_SEL_SHIFT (10U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_GPR1_SEL_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_GPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_CTRL_GPR1_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_CTRL_GPR1_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH5_CTRL_CNTS_SEL_MASK (0x1000U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_CNTS_SEL_SHIFT (12U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_CNTS_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_CNTS_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_CTRL_CNTS_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_CTRL_CNTS_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH5_CTRL_DSL_MASK (0x2000U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_DSL_SHIFT (13U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_DSL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_CTRL_DSL_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_CTRL_DSL_MASK) #define GTM_gtm_cls0_TIM0_CH5_CTRL_ISL_MASK (0x4000U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_ISL_SHIFT (14U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_ISL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_ISL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_CTRL_ISL_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_CTRL_ISL_MASK) #define GTM_gtm_cls0_TIM0_CH5_CTRL_ECNT_RESET_MASK (0x8000U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_ECNT_RESET_SHIFT (15U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_ECNT_RESET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_ECNT_RESET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_CTRL_ECNT_RESET_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_CTRL_ECNT_RESET_MASK) #define GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_EN_MASK (0x10000U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_EN_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_EN_MASK) #define GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_CNT_FRQ_MASK (0x60000U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_CNT_FRQ_SHIFT (17U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_CNT_FRQ_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_CNT_FRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_CNT_FRQ_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_CNT_FRQ_MASK) #define GTM_gtm_cls0_TIM0_CH5_CTRL_EXT_CAP_EN_MASK (0x80000U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_EXT_CAP_EN_SHIFT (19U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_EXT_CAP_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_EXT_CAP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_CTRL_EXT_CAP_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_CTRL_EXT_CAP_EN_MASK) #define GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_MODE_RE_MASK (0x100000U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_MODE_RE_SHIFT (20U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_MODE_RE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_MODE_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_MODE_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_MODE_RE_MASK) #define GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_CTR_RE_MASK (0x200000U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_CTR_RE_SHIFT (21U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_CTR_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_CTR_RE_MASK) #define GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_MODE_FE_MASK (0x400000U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_MODE_FE_SHIFT (22U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_MODE_FE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_MODE_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_MODE_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_MODE_FE_MASK) #define GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_CTR_FE_MASK (0x800000U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_CTR_FE_SHIFT (23U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_CTR_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_CTRL_FLT_CTR_FE_MASK) #define GTM_gtm_cls0_TIM0_CH5_CTRL_CLK_SEL_MASK (0x7000000U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_CLK_SEL_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_CLK_SEL_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_CTRL_CLK_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_CTRL_CLK_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH5_CTRL_FR_ECNT_OFL_MASK (0x8000000U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_FR_ECNT_OFL_SHIFT (27U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_FR_ECNT_OFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_FR_ECNT_OFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_CTRL_FR_ECNT_OFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_CTRL_FR_ECNT_OFL_MASK) #define GTM_gtm_cls0_TIM0_CH5_CTRL_EGPR0_SEL_MASK (0x10000000U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_EGPR0_SEL_SHIFT (28U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_EGPR0_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_EGPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_CTRL_EGPR0_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_CTRL_EGPR0_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH5_CTRL_EGPR1_SEL_MASK (0x20000000U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_EGPR1_SEL_SHIFT (29U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_EGPR1_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_EGPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_CTRL_EGPR1_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_CTRL_EGPR1_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH5_CTRL_TOCTRL_MASK (0xC0000000U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_TOCTRL_SHIFT (30U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_TOCTRL_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH5_CTRL_TOCTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_CTRL_TOCTRL_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_CTRL_TOCTRL_MASK) /*! @} */ /*! @name TIM0_CH5_ECTRL - TIM[i] channel [x] extended control register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH5_ECTRL_EXT_CAP_SRC_MASK (0xFU) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_EXT_CAP_SRC_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_EXT_CAP_SRC_WIDTH (4U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_EXT_CAP_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_ECTRL_EXT_CAP_SRC_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_ECTRL_EXT_CAP_SRC_MASK) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_USE_PREV_TDU_IN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_USE_PREV_TDU_IN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_USE_PREV_TDU_IN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_USE_PREV_TDU_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_ECTRL_USE_PREV_TDU_IN_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_ECTRL_USE_PREV_TDU_IN_MASK) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_TODET_IRQ_SRC_MASK (0xC0U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_TODET_IRQ_SRC_SHIFT (6U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_TODET_IRQ_SRC_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_TODET_IRQ_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_ECTRL_TODET_IRQ_SRC_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_ECTRL_TODET_IRQ_SRC_MASK) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_TDU_START_MASK (0x700U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_TDU_START_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_TDU_START_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_TDU_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_ECTRL_TDU_START_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_ECTRL_TDU_START_MASK) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_TDU_STOP_MASK (0x7000U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_TDU_STOP_SHIFT (12U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_TDU_STOP_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_TDU_STOP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_ECTRL_TDU_STOP_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_ECTRL_TDU_STOP_MASK) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_TDU_RESYNC_MASK (0xF0000U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_TDU_RESYNC_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_TDU_RESYNC_WIDTH (4U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_TDU_RESYNC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_ECTRL_TDU_RESYNC_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_ECTRL_TDU_RESYNC_MASK) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_USE_LUT_MASK (0xC00000U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_USE_LUT_SHIFT (22U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_USE_LUT_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_USE_LUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_ECTRL_USE_LUT_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_ECTRL_USE_LUT_MASK) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_EFLT_CTR_RE_MASK (0x1000000U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_EFLT_CTR_RE_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_EFLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_EFLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_ECTRL_EFLT_CTR_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_ECTRL_EFLT_CTR_RE_MASK) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_EFLT_CTR_FE_MASK (0x2000000U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_EFLT_CTR_FE_SHIFT (25U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_EFLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_EFLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_ECTRL_EFLT_CTR_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_ECTRL_EFLT_CTR_FE_MASK) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_SWAP_CAPTURE_MASK (0x10000000U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_SWAP_CAPTURE_SHIFT (28U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_SWAP_CAPTURE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_SWAP_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_ECTRL_SWAP_CAPTURE_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_ECTRL_SWAP_CAPTURE_MASK) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_IMM_START_MASK (0x20000000U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_IMM_START_SHIFT (29U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_IMM_START_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_IMM_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_ECTRL_IMM_START_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_ECTRL_IMM_START_MASK) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_ECLK_SEL_MASK (0x40000000U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_ECLK_SEL_SHIFT (30U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_ECLK_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_ECLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_ECTRL_ECLK_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_ECTRL_ECLK_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_USE_PREV_CH_IN_MASK (0x80000000U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_USE_PREV_CH_IN_SHIFT (31U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_USE_PREV_CH_IN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_ECTRL_USE_PREV_CH_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_ECTRL_USE_PREV_CH_IN_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_ECTRL_USE_PREV_CH_IN_MASK) /*! @} */ /*! @name TIM0_CH5_IRQ_NOTIFY - TIM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_NEWVAL_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_NEWVAL_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_NEWVAL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_NEWVAL_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_NEWVAL_MASK) #define GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_ECNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_ECNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_CNTOFL_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_CNTOFL_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_CNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_CNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_CNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_GPROFL_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_GPROFL_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_GPROFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_GPROFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_GPROFL_MASK) #define GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_TODET_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_TODET_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_TODET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_TODET_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_TODET_MASK) #define GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_GLITCHDET_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_IRQ_NOTIFY_GLITCHDET_MASK) /*! @} */ /*! @name TIM0_CH5_IRQ_EN - TIM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH5_IRQ_EN_NEWVAL_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_EN_NEWVAL_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_EN_NEWVAL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_EN_NEWVAL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_IRQ_EN_NEWVAL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_IRQ_EN_NEWVAL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH5_IRQ_EN_ECNTOFL_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_EN_ECNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_EN_ECNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_IRQ_EN_ECNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH5_IRQ_EN_CNTOFL_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_EN_CNTOFL_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_EN_CNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_EN_CNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_IRQ_EN_CNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_IRQ_EN_CNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH5_IRQ_EN_GPROFL_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_EN_GPROFL_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_EN_GPROFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_EN_GPROFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_IRQ_EN_GPROFL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_IRQ_EN_GPROFL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH5_IRQ_EN_TODET_IRQ_EN_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_EN_TODET_IRQ_EN_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_EN_TODET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_EN_TODET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_IRQ_EN_TODET_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_IRQ_EN_TODET_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH5_IRQ_EN_GLITCHDET_IRQ_EN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_EN_GLITCHDET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_EN_GLITCHDET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_IRQ_EN_GLITCHDET_IRQ_EN_MASK) /*! @} */ /*! @name TIM0_CH5_IRQ_FORCINT - TIM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_NEWVAL_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_NEWVAL_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_NEWVAL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_NEWVAL_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_NEWVAL_MASK) #define GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_ECNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_ECNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_CNTOFL_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_CNTOFL_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_CNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_CNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_CNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_GPROFL_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_GPROFL_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_GPROFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_GPROFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_GPROFL_MASK) #define GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_TODET_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_TODET_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_TODET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_TODET_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_TODET_MASK) #define GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_GLITCHDET_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_IRQ_FORCINT_TRG_GLITCHDET_MASK) /*! @} */ /*! @name TIM0_CH5_IRQ_MODE - TIM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH5_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH5_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TIM0_CH5_EIRQ_EN - TIM[i] channel [x] error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_NEWVAL_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_NEWVAL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_NEWVAL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_NEWVAL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_ECNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_ECNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_CNTOFL_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_CNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_CNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_CNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_GPROFL_EIRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_GPROFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_GPROFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_GPROFL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_TODET_EIRQ_EN_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_TODET_EIRQ_EN_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_TODET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_TODET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_TODET_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_TODET_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_GLITCHDET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_GLITCHDET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH5_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK) /*! @} */ /*! @name TIM0_CH6_GPR0 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH6_GPR0_GPR0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH6_GPR0_GPR0_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH6_GPR0_GPR0_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH6_GPR0_GPR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_GPR0_GPR0_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_GPR0_GPR0_MASK) #define GTM_gtm_cls0_TIM0_CH6_GPR0_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls0_TIM0_CH6_GPR0_ECNT_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH6_GPR0_ECNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH6_GPR0_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_GPR0_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_GPR0_ECNT_MASK) /*! @} */ /*! @name TIM0_CH6_GPR1 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH6_GPR1_GPR1_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH6_GPR1_GPR1_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH6_GPR1_GPR1_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH6_GPR1_GPR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_GPR1_GPR1_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_GPR1_GPR1_MASK) #define GTM_gtm_cls0_TIM0_CH6_GPR1_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls0_TIM0_CH6_GPR1_ECNT_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH6_GPR1_ECNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH6_GPR1_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_GPR1_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_GPR1_ECNT_MASK) /*! @} */ /*! @name TIM0_CH6_CNT - TIM[i] channel [x] SMU counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH6_CNT_CNT_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH6_CNT_CNT_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH6_CNT_CNT_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH6_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_CNT_CNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_CNT_CNT_MASK) /*! @} */ /*! @name TIM0_CH6_ECNT - TIM[i] channel [x] SMU edge counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH6_ECNT_ECNT_MASK (0xFFFFU) #define GTM_gtm_cls0_TIM0_CH6_ECNT_ECNT_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH6_ECNT_ECNT_WIDTH (16U) #define GTM_gtm_cls0_TIM0_CH6_ECNT_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_ECNT_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_ECNT_ECNT_MASK) /*! @} */ /*! @name TIM0_CH6_CNTS - TIM[i] channel [x] SMU shadow counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH6_CNTS_CNTS_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH6_CNTS_CNTS_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH6_CNTS_CNTS_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH6_CNTS_CNTS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_CNTS_CNTS_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_CNTS_CNTS_MASK) #define GTM_gtm_cls0_TIM0_CH6_CNTS_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls0_TIM0_CH6_CNTS_ECNT_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH6_CNTS_ECNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH6_CNTS_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_CNTS_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_CNTS_ECNT_MASK) /*! @} */ /*! @name TIM0_CH6_TDUC - TIM[i] channel [x] TDU counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH6_TDUC_TO_CNT_MASK (0xFFU) #define GTM_gtm_cls0_TIM0_CH6_TDUC_TO_CNT_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH6_TDUC_TO_CNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH6_TDUC_TO_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_TDUC_TO_CNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_TDUC_TO_CNT_MASK) #define GTM_gtm_cls0_TIM0_CH6_TDUC_TO_CNT1_MASK (0xFF00U) #define GTM_gtm_cls0_TIM0_CH6_TDUC_TO_CNT1_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH6_TDUC_TO_CNT1_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH6_TDUC_TO_CNT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_TDUC_TO_CNT1_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_TDUC_TO_CNT1_MASK) #define GTM_gtm_cls0_TIM0_CH6_TDUC_TO_CNT2_MASK (0xFF0000U) #define GTM_gtm_cls0_TIM0_CH6_TDUC_TO_CNT2_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH6_TDUC_TO_CNT2_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH6_TDUC_TO_CNT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_TDUC_TO_CNT2_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_TDUC_TO_CNT2_MASK) /*! @} */ /*! @name TIM0_CH6_TDUV - TIM[i] channel [x] TDU control register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH6_TDUV_TOV_MASK (0xFFU) #define GTM_gtm_cls0_TIM0_CH6_TDUV_TOV_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH6_TDUV_TOV_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH6_TDUV_TOV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_TDUV_TOV_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_TDUV_TOV_MASK) #define GTM_gtm_cls0_TIM0_CH6_TDUV_TOV1_MASK (0xFF00U) #define GTM_gtm_cls0_TIM0_CH6_TDUV_TOV1_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH6_TDUV_TOV1_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH6_TDUV_TOV1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_TDUV_TOV1_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_TDUV_TOV1_MASK) #define GTM_gtm_cls0_TIM0_CH6_TDUV_TOV2_MASK (0xFF0000U) #define GTM_gtm_cls0_TIM0_CH6_TDUV_TOV2_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH6_TDUV_TOV2_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH6_TDUV_TOV2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_TDUV_TOV2_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_TDUV_TOV2_MASK) #define GTM_gtm_cls0_TIM0_CH6_TDUV_SLICING_MASK (0x3000000U) #define GTM_gtm_cls0_TIM0_CH6_TDUV_SLICING_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH6_TDUV_SLICING_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH6_TDUV_SLICING(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_TDUV_SLICING_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_TDUV_SLICING_MASK) #define GTM_gtm_cls0_TIM0_CH6_TDUV_TCS_USE_SAMPLE_EVT_MASK (0x4000000U) #define GTM_gtm_cls0_TIM0_CH6_TDUV_TCS_USE_SAMPLE_EVT_SHIFT (26U) #define GTM_gtm_cls0_TIM0_CH6_TDUV_TCS_USE_SAMPLE_EVT_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_TDUV_TCS_USE_SAMPLE_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_TDUV_TCS_USE_SAMPLE_EVT_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_TDUV_TCS_USE_SAMPLE_EVT_MASK) #define GTM_gtm_cls0_TIM0_CH6_TDUV_TDU_SAME_CNT_CLK_MASK (0x8000000U) #define GTM_gtm_cls0_TIM0_CH6_TDUV_TDU_SAME_CNT_CLK_SHIFT (27U) #define GTM_gtm_cls0_TIM0_CH6_TDUV_TDU_SAME_CNT_CLK_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_TDUV_TDU_SAME_CNT_CLK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_TDUV_TDU_SAME_CNT_CLK_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_TDUV_TDU_SAME_CNT_CLK_MASK) #define GTM_gtm_cls0_TIM0_CH6_TDUV_TCS_MASK (0x70000000U) #define GTM_gtm_cls0_TIM0_CH6_TDUV_TCS_SHIFT (28U) #define GTM_gtm_cls0_TIM0_CH6_TDUV_TCS_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH6_TDUV_TCS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_TDUV_TCS_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_TDUV_TCS_MASK) /*! @} */ /*! @name TIM0_CH6_FLT_RE - TIM[i] channel [x] filter parameter 0 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH6_FLT_RE_FLT_RE_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH6_FLT_RE_FLT_RE_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH6_FLT_RE_FLT_RE_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH6_FLT_RE_FLT_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_FLT_RE_FLT_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_FLT_RE_FLT_RE_MASK) /*! @} */ /*! @name TIM0_CH6_FLT_FE - TIM[i] channel [x] filter parameter 1 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH6_FLT_FE_FLT_FE_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH6_FLT_FE_FLT_FE_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH6_FLT_FE_FLT_FE_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH6_FLT_FE_FLT_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_FLT_FE_FLT_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_FLT_FE_FLT_FE_MASK) /*! @} */ /*! @name TIM0_CH6_CTRL - TIM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH6_CTRL_TIM_EN_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_TIM_EN_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_TIM_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_TIM_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_CTRL_TIM_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_CTRL_TIM_EN_MASK) #define GTM_gtm_cls0_TIM0_CH6_CTRL_TIM_MODE_MASK (0xEU) #define GTM_gtm_cls0_TIM0_CH6_CTRL_TIM_MODE_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_TIM_MODE_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_TIM_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_CTRL_TIM_MODE_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_CTRL_TIM_MODE_MASK) #define GTM_gtm_cls0_TIM0_CH6_CTRL_OSM_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_OSM_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_CTRL_OSM_MASK) #define GTM_gtm_cls0_TIM0_CH6_CTRL_ARU_EN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_ARU_EN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_CTRL_ARU_EN_MASK) #define GTM_gtm_cls0_TIM0_CH6_CTRL_CICTRL_MASK (0x40U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_CICTRL_SHIFT (6U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_CICTRL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_CICTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_CTRL_CICTRL_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_CTRL_CICTRL_MASK) #define GTM_gtm_cls0_TIM0_CH6_CTRL_TBU0_SEL_MASK (0x80U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_TBU0_SEL_SHIFT (7U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_TBU0_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_TBU0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_CTRL_TBU0_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_CTRL_TBU0_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH6_CTRL_GPR0_SEL_MASK (0x300U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_GPR0_SEL_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_GPR0_SEL_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_GPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_CTRL_GPR0_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_CTRL_GPR0_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH6_CTRL_GPR1_SEL_MASK (0xC00U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_GPR1_SEL_SHIFT (10U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_GPR1_SEL_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_GPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_CTRL_GPR1_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_CTRL_GPR1_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH6_CTRL_CNTS_SEL_MASK (0x1000U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_CNTS_SEL_SHIFT (12U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_CNTS_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_CNTS_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_CTRL_CNTS_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_CTRL_CNTS_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH6_CTRL_DSL_MASK (0x2000U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_DSL_SHIFT (13U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_DSL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_CTRL_DSL_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_CTRL_DSL_MASK) #define GTM_gtm_cls0_TIM0_CH6_CTRL_ISL_MASK (0x4000U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_ISL_SHIFT (14U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_ISL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_ISL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_CTRL_ISL_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_CTRL_ISL_MASK) #define GTM_gtm_cls0_TIM0_CH6_CTRL_ECNT_RESET_MASK (0x8000U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_ECNT_RESET_SHIFT (15U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_ECNT_RESET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_ECNT_RESET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_CTRL_ECNT_RESET_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_CTRL_ECNT_RESET_MASK) #define GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_EN_MASK (0x10000U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_EN_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_EN_MASK) #define GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_CNT_FRQ_MASK (0x60000U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_CNT_FRQ_SHIFT (17U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_CNT_FRQ_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_CNT_FRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_CNT_FRQ_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_CNT_FRQ_MASK) #define GTM_gtm_cls0_TIM0_CH6_CTRL_EXT_CAP_EN_MASK (0x80000U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_EXT_CAP_EN_SHIFT (19U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_EXT_CAP_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_EXT_CAP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_CTRL_EXT_CAP_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_CTRL_EXT_CAP_EN_MASK) #define GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_MODE_RE_MASK (0x100000U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_MODE_RE_SHIFT (20U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_MODE_RE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_MODE_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_MODE_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_MODE_RE_MASK) #define GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_CTR_RE_MASK (0x200000U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_CTR_RE_SHIFT (21U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_CTR_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_CTR_RE_MASK) #define GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_MODE_FE_MASK (0x400000U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_MODE_FE_SHIFT (22U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_MODE_FE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_MODE_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_MODE_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_MODE_FE_MASK) #define GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_CTR_FE_MASK (0x800000U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_CTR_FE_SHIFT (23U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_CTR_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_CTRL_FLT_CTR_FE_MASK) #define GTM_gtm_cls0_TIM0_CH6_CTRL_CLK_SEL_MASK (0x7000000U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_CLK_SEL_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_CLK_SEL_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_CTRL_CLK_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_CTRL_CLK_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH6_CTRL_FR_ECNT_OFL_MASK (0x8000000U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_FR_ECNT_OFL_SHIFT (27U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_FR_ECNT_OFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_FR_ECNT_OFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_CTRL_FR_ECNT_OFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_CTRL_FR_ECNT_OFL_MASK) #define GTM_gtm_cls0_TIM0_CH6_CTRL_EGPR0_SEL_MASK (0x10000000U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_EGPR0_SEL_SHIFT (28U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_EGPR0_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_EGPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_CTRL_EGPR0_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_CTRL_EGPR0_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH6_CTRL_EGPR1_SEL_MASK (0x20000000U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_EGPR1_SEL_SHIFT (29U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_EGPR1_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_EGPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_CTRL_EGPR1_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_CTRL_EGPR1_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH6_CTRL_TOCTRL_MASK (0xC0000000U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_TOCTRL_SHIFT (30U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_TOCTRL_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH6_CTRL_TOCTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_CTRL_TOCTRL_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_CTRL_TOCTRL_MASK) /*! @} */ /*! @name TIM0_CH6_ECTRL - TIM[i] channel [x] extended control register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH6_ECTRL_EXT_CAP_SRC_MASK (0xFU) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_EXT_CAP_SRC_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_EXT_CAP_SRC_WIDTH (4U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_EXT_CAP_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_ECTRL_EXT_CAP_SRC_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_ECTRL_EXT_CAP_SRC_MASK) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_USE_PREV_TDU_IN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_USE_PREV_TDU_IN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_USE_PREV_TDU_IN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_USE_PREV_TDU_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_ECTRL_USE_PREV_TDU_IN_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_ECTRL_USE_PREV_TDU_IN_MASK) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_TODET_IRQ_SRC_MASK (0xC0U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_TODET_IRQ_SRC_SHIFT (6U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_TODET_IRQ_SRC_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_TODET_IRQ_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_ECTRL_TODET_IRQ_SRC_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_ECTRL_TODET_IRQ_SRC_MASK) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_TDU_START_MASK (0x700U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_TDU_START_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_TDU_START_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_TDU_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_ECTRL_TDU_START_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_ECTRL_TDU_START_MASK) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_TDU_STOP_MASK (0x7000U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_TDU_STOP_SHIFT (12U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_TDU_STOP_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_TDU_STOP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_ECTRL_TDU_STOP_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_ECTRL_TDU_STOP_MASK) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_TDU_RESYNC_MASK (0xF0000U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_TDU_RESYNC_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_TDU_RESYNC_WIDTH (4U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_TDU_RESYNC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_ECTRL_TDU_RESYNC_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_ECTRL_TDU_RESYNC_MASK) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_USE_LUT_MASK (0xC00000U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_USE_LUT_SHIFT (22U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_USE_LUT_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_USE_LUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_ECTRL_USE_LUT_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_ECTRL_USE_LUT_MASK) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_EFLT_CTR_RE_MASK (0x1000000U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_EFLT_CTR_RE_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_EFLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_EFLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_ECTRL_EFLT_CTR_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_ECTRL_EFLT_CTR_RE_MASK) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_EFLT_CTR_FE_MASK (0x2000000U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_EFLT_CTR_FE_SHIFT (25U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_EFLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_EFLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_ECTRL_EFLT_CTR_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_ECTRL_EFLT_CTR_FE_MASK) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_SWAP_CAPTURE_MASK (0x10000000U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_SWAP_CAPTURE_SHIFT (28U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_SWAP_CAPTURE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_SWAP_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_ECTRL_SWAP_CAPTURE_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_ECTRL_SWAP_CAPTURE_MASK) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_IMM_START_MASK (0x20000000U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_IMM_START_SHIFT (29U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_IMM_START_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_IMM_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_ECTRL_IMM_START_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_ECTRL_IMM_START_MASK) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_ECLK_SEL_MASK (0x40000000U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_ECLK_SEL_SHIFT (30U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_ECLK_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_ECLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_ECTRL_ECLK_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_ECTRL_ECLK_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_USE_PREV_CH_IN_MASK (0x80000000U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_USE_PREV_CH_IN_SHIFT (31U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_USE_PREV_CH_IN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_ECTRL_USE_PREV_CH_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_ECTRL_USE_PREV_CH_IN_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_ECTRL_USE_PREV_CH_IN_MASK) /*! @} */ /*! @name TIM0_CH6_IRQ_NOTIFY - TIM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_NEWVAL_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_NEWVAL_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_NEWVAL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_NEWVAL_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_NEWVAL_MASK) #define GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_ECNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_ECNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_CNTOFL_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_CNTOFL_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_CNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_CNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_CNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_GPROFL_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_GPROFL_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_GPROFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_GPROFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_GPROFL_MASK) #define GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_TODET_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_TODET_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_TODET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_TODET_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_TODET_MASK) #define GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_GLITCHDET_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_IRQ_NOTIFY_GLITCHDET_MASK) /*! @} */ /*! @name TIM0_CH6_IRQ_EN - TIM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH6_IRQ_EN_NEWVAL_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_EN_NEWVAL_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_EN_NEWVAL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_EN_NEWVAL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_IRQ_EN_NEWVAL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_IRQ_EN_NEWVAL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH6_IRQ_EN_ECNTOFL_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_EN_ECNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_EN_ECNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_IRQ_EN_ECNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH6_IRQ_EN_CNTOFL_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_EN_CNTOFL_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_EN_CNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_EN_CNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_IRQ_EN_CNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_IRQ_EN_CNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH6_IRQ_EN_GPROFL_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_EN_GPROFL_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_EN_GPROFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_EN_GPROFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_IRQ_EN_GPROFL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_IRQ_EN_GPROFL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH6_IRQ_EN_TODET_IRQ_EN_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_EN_TODET_IRQ_EN_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_EN_TODET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_EN_TODET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_IRQ_EN_TODET_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_IRQ_EN_TODET_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH6_IRQ_EN_GLITCHDET_IRQ_EN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_EN_GLITCHDET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_EN_GLITCHDET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_IRQ_EN_GLITCHDET_IRQ_EN_MASK) /*! @} */ /*! @name TIM0_CH6_IRQ_FORCINT - TIM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_NEWVAL_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_NEWVAL_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_NEWVAL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_NEWVAL_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_NEWVAL_MASK) #define GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_ECNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_ECNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_CNTOFL_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_CNTOFL_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_CNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_CNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_CNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_GPROFL_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_GPROFL_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_GPROFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_GPROFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_GPROFL_MASK) #define GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_TODET_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_TODET_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_TODET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_TODET_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_TODET_MASK) #define GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_GLITCHDET_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_IRQ_FORCINT_TRG_GLITCHDET_MASK) /*! @} */ /*! @name TIM0_CH6_IRQ_MODE - TIM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH6_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH6_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TIM0_CH6_EIRQ_EN - TIM[i] channel [x] error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_NEWVAL_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_NEWVAL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_NEWVAL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_NEWVAL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_ECNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_ECNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_CNTOFL_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_CNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_CNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_CNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_GPROFL_EIRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_GPROFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_GPROFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_GPROFL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_TODET_EIRQ_EN_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_TODET_EIRQ_EN_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_TODET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_TODET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_TODET_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_TODET_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_GLITCHDET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_GLITCHDET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH6_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK) /*! @} */ /*! @name TIM0_CH7_GPR0 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH7_GPR0_GPR0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH7_GPR0_GPR0_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH7_GPR0_GPR0_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH7_GPR0_GPR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_GPR0_GPR0_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_GPR0_GPR0_MASK) #define GTM_gtm_cls0_TIM0_CH7_GPR0_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls0_TIM0_CH7_GPR0_ECNT_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH7_GPR0_ECNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH7_GPR0_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_GPR0_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_GPR0_ECNT_MASK) /*! @} */ /*! @name TIM0_CH7_GPR1 - TIM[i] channel [x] general purpose 0 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH7_GPR1_GPR1_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH7_GPR1_GPR1_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH7_GPR1_GPR1_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH7_GPR1_GPR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_GPR1_GPR1_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_GPR1_GPR1_MASK) #define GTM_gtm_cls0_TIM0_CH7_GPR1_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls0_TIM0_CH7_GPR1_ECNT_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH7_GPR1_ECNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH7_GPR1_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_GPR1_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_GPR1_ECNT_MASK) /*! @} */ /*! @name TIM0_CH7_CNT - TIM[i] channel [x] SMU counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH7_CNT_CNT_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH7_CNT_CNT_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH7_CNT_CNT_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH7_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_CNT_CNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_CNT_CNT_MASK) /*! @} */ /*! @name TIM0_CH7_ECNT - TIM[i] channel [x] SMU edge counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH7_ECNT_ECNT_MASK (0xFFFFU) #define GTM_gtm_cls0_TIM0_CH7_ECNT_ECNT_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH7_ECNT_ECNT_WIDTH (16U) #define GTM_gtm_cls0_TIM0_CH7_ECNT_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_ECNT_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_ECNT_ECNT_MASK) /*! @} */ /*! @name TIM0_CH7_CNTS - TIM[i] channel [x] SMU shadow counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH7_CNTS_CNTS_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH7_CNTS_CNTS_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH7_CNTS_CNTS_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH7_CNTS_CNTS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_CNTS_CNTS_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_CNTS_CNTS_MASK) #define GTM_gtm_cls0_TIM0_CH7_CNTS_ECNT_MASK (0xFF000000U) #define GTM_gtm_cls0_TIM0_CH7_CNTS_ECNT_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH7_CNTS_ECNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH7_CNTS_ECNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_CNTS_ECNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_CNTS_ECNT_MASK) /*! @} */ /*! @name TIM0_CH7_TDUC - TIM[i] channel [x] TDU counter register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH7_TDUC_TO_CNT_MASK (0xFFU) #define GTM_gtm_cls0_TIM0_CH7_TDUC_TO_CNT_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH7_TDUC_TO_CNT_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH7_TDUC_TO_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_TDUC_TO_CNT_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_TDUC_TO_CNT_MASK) #define GTM_gtm_cls0_TIM0_CH7_TDUC_TO_CNT1_MASK (0xFF00U) #define GTM_gtm_cls0_TIM0_CH7_TDUC_TO_CNT1_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH7_TDUC_TO_CNT1_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH7_TDUC_TO_CNT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_TDUC_TO_CNT1_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_TDUC_TO_CNT1_MASK) #define GTM_gtm_cls0_TIM0_CH7_TDUC_TO_CNT2_MASK (0xFF0000U) #define GTM_gtm_cls0_TIM0_CH7_TDUC_TO_CNT2_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH7_TDUC_TO_CNT2_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH7_TDUC_TO_CNT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_TDUC_TO_CNT2_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_TDUC_TO_CNT2_MASK) /*! @} */ /*! @name TIM0_CH7_TDUV - TIM[i] channel [x] TDU control register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH7_TDUV_TOV_MASK (0xFFU) #define GTM_gtm_cls0_TIM0_CH7_TDUV_TOV_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH7_TDUV_TOV_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH7_TDUV_TOV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_TDUV_TOV_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_TDUV_TOV_MASK) #define GTM_gtm_cls0_TIM0_CH7_TDUV_TOV1_MASK (0xFF00U) #define GTM_gtm_cls0_TIM0_CH7_TDUV_TOV1_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH7_TDUV_TOV1_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH7_TDUV_TOV1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_TDUV_TOV1_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_TDUV_TOV1_MASK) #define GTM_gtm_cls0_TIM0_CH7_TDUV_TOV2_MASK (0xFF0000U) #define GTM_gtm_cls0_TIM0_CH7_TDUV_TOV2_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH7_TDUV_TOV2_WIDTH (8U) #define GTM_gtm_cls0_TIM0_CH7_TDUV_TOV2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_TDUV_TOV2_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_TDUV_TOV2_MASK) #define GTM_gtm_cls0_TIM0_CH7_TDUV_SLICING_MASK (0x3000000U) #define GTM_gtm_cls0_TIM0_CH7_TDUV_SLICING_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH7_TDUV_SLICING_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH7_TDUV_SLICING(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_TDUV_SLICING_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_TDUV_SLICING_MASK) #define GTM_gtm_cls0_TIM0_CH7_TDUV_TCS_USE_SAMPLE_EVT_MASK (0x4000000U) #define GTM_gtm_cls0_TIM0_CH7_TDUV_TCS_USE_SAMPLE_EVT_SHIFT (26U) #define GTM_gtm_cls0_TIM0_CH7_TDUV_TCS_USE_SAMPLE_EVT_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_TDUV_TCS_USE_SAMPLE_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_TDUV_TCS_USE_SAMPLE_EVT_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_TDUV_TCS_USE_SAMPLE_EVT_MASK) #define GTM_gtm_cls0_TIM0_CH7_TDUV_TDU_SAME_CNT_CLK_MASK (0x8000000U) #define GTM_gtm_cls0_TIM0_CH7_TDUV_TDU_SAME_CNT_CLK_SHIFT (27U) #define GTM_gtm_cls0_TIM0_CH7_TDUV_TDU_SAME_CNT_CLK_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_TDUV_TDU_SAME_CNT_CLK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_TDUV_TDU_SAME_CNT_CLK_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_TDUV_TDU_SAME_CNT_CLK_MASK) #define GTM_gtm_cls0_TIM0_CH7_TDUV_TCS_MASK (0x70000000U) #define GTM_gtm_cls0_TIM0_CH7_TDUV_TCS_SHIFT (28U) #define GTM_gtm_cls0_TIM0_CH7_TDUV_TCS_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH7_TDUV_TCS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_TDUV_TCS_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_TDUV_TCS_MASK) /*! @} */ /*! @name TIM0_CH7_FLT_RE - TIM[i] channel [x] filter parameter 0 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH7_FLT_RE_FLT_RE_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH7_FLT_RE_FLT_RE_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH7_FLT_RE_FLT_RE_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH7_FLT_RE_FLT_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_FLT_RE_FLT_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_FLT_RE_FLT_RE_MASK) /*! @} */ /*! @name TIM0_CH7_FLT_FE - TIM[i] channel [x] filter parameter 1 register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH7_FLT_FE_FLT_FE_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TIM0_CH7_FLT_FE_FLT_FE_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH7_FLT_FE_FLT_FE_WIDTH (24U) #define GTM_gtm_cls0_TIM0_CH7_FLT_FE_FLT_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_FLT_FE_FLT_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_FLT_FE_FLT_FE_MASK) /*! @} */ /*! @name TIM0_CH7_CTRL - TIM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH7_CTRL_TIM_EN_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_TIM_EN_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_TIM_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_TIM_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_CTRL_TIM_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_CTRL_TIM_EN_MASK) #define GTM_gtm_cls0_TIM0_CH7_CTRL_TIM_MODE_MASK (0xEU) #define GTM_gtm_cls0_TIM0_CH7_CTRL_TIM_MODE_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_TIM_MODE_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_TIM_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_CTRL_TIM_MODE_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_CTRL_TIM_MODE_MASK) #define GTM_gtm_cls0_TIM0_CH7_CTRL_OSM_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_OSM_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_CTRL_OSM_MASK) #define GTM_gtm_cls0_TIM0_CH7_CTRL_ARU_EN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_ARU_EN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_CTRL_ARU_EN_MASK) #define GTM_gtm_cls0_TIM0_CH7_CTRL_CICTRL_MASK (0x40U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_CICTRL_SHIFT (6U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_CICTRL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_CICTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_CTRL_CICTRL_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_CTRL_CICTRL_MASK) #define GTM_gtm_cls0_TIM0_CH7_CTRL_TBU0_SEL_MASK (0x80U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_TBU0_SEL_SHIFT (7U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_TBU0_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_TBU0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_CTRL_TBU0_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_CTRL_TBU0_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH7_CTRL_GPR0_SEL_MASK (0x300U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_GPR0_SEL_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_GPR0_SEL_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_GPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_CTRL_GPR0_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_CTRL_GPR0_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH7_CTRL_GPR1_SEL_MASK (0xC00U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_GPR1_SEL_SHIFT (10U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_GPR1_SEL_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_GPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_CTRL_GPR1_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_CTRL_GPR1_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH7_CTRL_CNTS_SEL_MASK (0x1000U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_CNTS_SEL_SHIFT (12U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_CNTS_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_CNTS_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_CTRL_CNTS_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_CTRL_CNTS_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH7_CTRL_DSL_MASK (0x2000U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_DSL_SHIFT (13U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_DSL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_CTRL_DSL_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_CTRL_DSL_MASK) #define GTM_gtm_cls0_TIM0_CH7_CTRL_ISL_MASK (0x4000U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_ISL_SHIFT (14U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_ISL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_ISL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_CTRL_ISL_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_CTRL_ISL_MASK) #define GTM_gtm_cls0_TIM0_CH7_CTRL_ECNT_RESET_MASK (0x8000U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_ECNT_RESET_SHIFT (15U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_ECNT_RESET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_ECNT_RESET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_CTRL_ECNT_RESET_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_CTRL_ECNT_RESET_MASK) #define GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_EN_MASK (0x10000U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_EN_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_EN_MASK) #define GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_CNT_FRQ_MASK (0x60000U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_CNT_FRQ_SHIFT (17U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_CNT_FRQ_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_CNT_FRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_CNT_FRQ_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_CNT_FRQ_MASK) #define GTM_gtm_cls0_TIM0_CH7_CTRL_EXT_CAP_EN_MASK (0x80000U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_EXT_CAP_EN_SHIFT (19U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_EXT_CAP_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_EXT_CAP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_CTRL_EXT_CAP_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_CTRL_EXT_CAP_EN_MASK) #define GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_MODE_RE_MASK (0x100000U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_MODE_RE_SHIFT (20U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_MODE_RE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_MODE_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_MODE_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_MODE_RE_MASK) #define GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_CTR_RE_MASK (0x200000U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_CTR_RE_SHIFT (21U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_CTR_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_CTR_RE_MASK) #define GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_MODE_FE_MASK (0x400000U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_MODE_FE_SHIFT (22U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_MODE_FE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_MODE_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_MODE_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_MODE_FE_MASK) #define GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_CTR_FE_MASK (0x800000U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_CTR_FE_SHIFT (23U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_CTR_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_CTRL_FLT_CTR_FE_MASK) #define GTM_gtm_cls0_TIM0_CH7_CTRL_CLK_SEL_MASK (0x7000000U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_CLK_SEL_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_CLK_SEL_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_CTRL_CLK_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_CTRL_CLK_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH7_CTRL_FR_ECNT_OFL_MASK (0x8000000U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_FR_ECNT_OFL_SHIFT (27U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_FR_ECNT_OFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_FR_ECNT_OFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_CTRL_FR_ECNT_OFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_CTRL_FR_ECNT_OFL_MASK) #define GTM_gtm_cls0_TIM0_CH7_CTRL_EGPR0_SEL_MASK (0x10000000U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_EGPR0_SEL_SHIFT (28U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_EGPR0_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_EGPR0_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_CTRL_EGPR0_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_CTRL_EGPR0_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH7_CTRL_EGPR1_SEL_MASK (0x20000000U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_EGPR1_SEL_SHIFT (29U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_EGPR1_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_EGPR1_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_CTRL_EGPR1_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_CTRL_EGPR1_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH7_CTRL_TOCTRL_MASK (0xC0000000U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_TOCTRL_SHIFT (30U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_TOCTRL_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH7_CTRL_TOCTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_CTRL_TOCTRL_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_CTRL_TOCTRL_MASK) /*! @} */ /*! @name TIM0_CH7_ECTRL - TIM[i] channel [x] extended control register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH7_ECTRL_EXT_CAP_SRC_MASK (0xFU) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_EXT_CAP_SRC_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_EXT_CAP_SRC_WIDTH (4U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_EXT_CAP_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_ECTRL_EXT_CAP_SRC_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_ECTRL_EXT_CAP_SRC_MASK) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_USE_PREV_TDU_IN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_USE_PREV_TDU_IN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_USE_PREV_TDU_IN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_USE_PREV_TDU_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_ECTRL_USE_PREV_TDU_IN_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_ECTRL_USE_PREV_TDU_IN_MASK) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_TODET_IRQ_SRC_MASK (0xC0U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_TODET_IRQ_SRC_SHIFT (6U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_TODET_IRQ_SRC_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_TODET_IRQ_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_ECTRL_TODET_IRQ_SRC_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_ECTRL_TODET_IRQ_SRC_MASK) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_TDU_START_MASK (0x700U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_TDU_START_SHIFT (8U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_TDU_START_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_TDU_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_ECTRL_TDU_START_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_ECTRL_TDU_START_MASK) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_TDU_STOP_MASK (0x7000U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_TDU_STOP_SHIFT (12U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_TDU_STOP_WIDTH (3U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_TDU_STOP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_ECTRL_TDU_STOP_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_ECTRL_TDU_STOP_MASK) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_TDU_RESYNC_MASK (0xF0000U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_TDU_RESYNC_SHIFT (16U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_TDU_RESYNC_WIDTH (4U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_TDU_RESYNC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_ECTRL_TDU_RESYNC_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_ECTRL_TDU_RESYNC_MASK) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_USE_LUT_MASK (0xC00000U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_USE_LUT_SHIFT (22U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_USE_LUT_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_USE_LUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_ECTRL_USE_LUT_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_ECTRL_USE_LUT_MASK) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_EFLT_CTR_RE_MASK (0x1000000U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_EFLT_CTR_RE_SHIFT (24U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_EFLT_CTR_RE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_EFLT_CTR_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_ECTRL_EFLT_CTR_RE_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_ECTRL_EFLT_CTR_RE_MASK) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_EFLT_CTR_FE_MASK (0x2000000U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_EFLT_CTR_FE_SHIFT (25U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_EFLT_CTR_FE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_EFLT_CTR_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_ECTRL_EFLT_CTR_FE_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_ECTRL_EFLT_CTR_FE_MASK) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_SWAP_CAPTURE_MASK (0x10000000U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_SWAP_CAPTURE_SHIFT (28U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_SWAP_CAPTURE_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_SWAP_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_ECTRL_SWAP_CAPTURE_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_ECTRL_SWAP_CAPTURE_MASK) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_IMM_START_MASK (0x20000000U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_IMM_START_SHIFT (29U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_IMM_START_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_IMM_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_ECTRL_IMM_START_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_ECTRL_IMM_START_MASK) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_ECLK_SEL_MASK (0x40000000U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_ECLK_SEL_SHIFT (30U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_ECLK_SEL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_ECLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_ECTRL_ECLK_SEL_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_ECTRL_ECLK_SEL_MASK) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_USE_PREV_CH_IN_MASK (0x80000000U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_USE_PREV_CH_IN_SHIFT (31U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_USE_PREV_CH_IN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_ECTRL_USE_PREV_CH_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_ECTRL_USE_PREV_CH_IN_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_ECTRL_USE_PREV_CH_IN_MASK) /*! @} */ /*! @name TIM0_CH7_IRQ_NOTIFY - TIM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_NEWVAL_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_NEWVAL_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_NEWVAL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_NEWVAL_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_NEWVAL_MASK) #define GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_ECNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_ECNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_CNTOFL_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_CNTOFL_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_CNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_CNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_CNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_GPROFL_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_GPROFL_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_GPROFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_GPROFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_GPROFL_MASK) #define GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_TODET_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_TODET_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_TODET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_TODET_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_TODET_MASK) #define GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_GLITCHDET_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_IRQ_NOTIFY_GLITCHDET_MASK) /*! @} */ /*! @name TIM0_CH7_IRQ_EN - TIM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH7_IRQ_EN_NEWVAL_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_EN_NEWVAL_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_EN_NEWVAL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_EN_NEWVAL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_IRQ_EN_NEWVAL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_IRQ_EN_NEWVAL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH7_IRQ_EN_ECNTOFL_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_EN_ECNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_EN_ECNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_IRQ_EN_ECNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_IRQ_EN_ECNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH7_IRQ_EN_CNTOFL_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_EN_CNTOFL_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_EN_CNTOFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_EN_CNTOFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_IRQ_EN_CNTOFL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_IRQ_EN_CNTOFL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH7_IRQ_EN_GPROFL_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_EN_GPROFL_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_EN_GPROFL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_EN_GPROFL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_IRQ_EN_GPROFL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_IRQ_EN_GPROFL_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH7_IRQ_EN_TODET_IRQ_EN_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_EN_TODET_IRQ_EN_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_EN_TODET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_EN_TODET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_IRQ_EN_TODET_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_IRQ_EN_TODET_IRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH7_IRQ_EN_GLITCHDET_IRQ_EN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_EN_GLITCHDET_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_EN_GLITCHDET_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_IRQ_EN_GLITCHDET_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_IRQ_EN_GLITCHDET_IRQ_EN_MASK) /*! @} */ /*! @name TIM0_CH7_IRQ_FORCINT - TIM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_NEWVAL_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_NEWVAL_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_NEWVAL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_NEWVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_NEWVAL_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_NEWVAL_MASK) #define GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_ECNTOFL_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_ECNTOFL_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_ECNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_ECNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_ECNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_ECNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_CNTOFL_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_CNTOFL_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_CNTOFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_CNTOFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_CNTOFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_CNTOFL_MASK) #define GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_GPROFL_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_GPROFL_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_GPROFL_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_GPROFL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_GPROFL_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_GPROFL_MASK) #define GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_TODET_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_TODET_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_TODET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_TODET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_TODET_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_TODET_MASK) #define GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_GLITCHDET_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_GLITCHDET_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_GLITCHDET_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_GLITCHDET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_GLITCHDET_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_IRQ_FORCINT_TRG_GLITCHDET_MASK) /*! @} */ /*! @name TIM0_CH7_IRQ_MODE - TIM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH7_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_TIM0_CH7_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TIM0_CH7_EIRQ_EN - TIM[i] channel [x] error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_NEWVAL_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_NEWVAL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_NEWVAL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_NEWVAL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_NEWVAL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_ECNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_ECNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_ECNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_ECNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_CNTOFL_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_CNTOFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_CNTOFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_CNTOFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_CNTOFL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_GPROFL_EIRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_GPROFL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_GPROFL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_GPROFL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_GPROFL_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_TODET_EIRQ_EN_MASK (0x10U) #define GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_TODET_EIRQ_EN_SHIFT (4U) #define GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_TODET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_TODET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_TODET_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_TODET_EIRQ_EN_MASK) #define GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK (0x20U) #define GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT (5U) #define GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_GLITCHDET_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_GLITCHDET_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_GLITCHDET_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_TIM0_CH7_EIRQ_EN_GLITCHDET_EIRQ_EN_MASK) /*! @} */ /*! @name TIM0_INP_VAL - TIM[i] input value observation register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT0_MASK (0x1U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT0_SHIFT (0U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT0_WIDTH (1U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_INP_VAL_F_OUT0_SHIFT)) & GTM_gtm_cls0_TIM0_INP_VAL_F_OUT0_MASK) #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT1_MASK (0x2U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT1_SHIFT (1U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT1_WIDTH (1U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_INP_VAL_F_OUT1_SHIFT)) & GTM_gtm_cls0_TIM0_INP_VAL_F_OUT1_MASK) #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT2_MASK (0x4U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT2_SHIFT (2U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT2_WIDTH (1U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_INP_VAL_F_OUT2_SHIFT)) & GTM_gtm_cls0_TIM0_INP_VAL_F_OUT2_MASK) #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT3_MASK (0x8U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT3_SHIFT (3U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT3_WIDTH (1U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_INP_VAL_F_OUT3_SHIFT)) & GTM_gtm_cls0_TIM0_INP_VAL_F_OUT3_MASK) #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT4_MASK (0x10U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT4_SHIFT (4U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT4_WIDTH (1U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_INP_VAL_F_OUT4_SHIFT)) & GTM_gtm_cls0_TIM0_INP_VAL_F_OUT4_MASK) #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT5_MASK (0x20U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT5_SHIFT (5U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT5_WIDTH (1U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_INP_VAL_F_OUT5_SHIFT)) & GTM_gtm_cls0_TIM0_INP_VAL_F_OUT5_MASK) #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT6_MASK (0x40U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT6_SHIFT (6U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT6_WIDTH (1U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_INP_VAL_F_OUT6_SHIFT)) & GTM_gtm_cls0_TIM0_INP_VAL_F_OUT6_MASK) #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT7_MASK (0x80U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT7_SHIFT (7U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT7_WIDTH (1U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_OUT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_INP_VAL_F_OUT7_SHIFT)) & GTM_gtm_cls0_TIM0_INP_VAL_F_OUT7_MASK) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN0_MASK (0x100U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN0_SHIFT (8U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN0_WIDTH (1U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_INP_VAL_F_IN0_SHIFT)) & GTM_gtm_cls0_TIM0_INP_VAL_F_IN0_MASK) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN1_MASK (0x200U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN1_SHIFT (9U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN1_WIDTH (1U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_INP_VAL_F_IN1_SHIFT)) & GTM_gtm_cls0_TIM0_INP_VAL_F_IN1_MASK) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN2_MASK (0x400U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN2_SHIFT (10U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN2_WIDTH (1U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_INP_VAL_F_IN2_SHIFT)) & GTM_gtm_cls0_TIM0_INP_VAL_F_IN2_MASK) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN3_MASK (0x800U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN3_SHIFT (11U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN3_WIDTH (1U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_INP_VAL_F_IN3_SHIFT)) & GTM_gtm_cls0_TIM0_INP_VAL_F_IN3_MASK) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN4_MASK (0x1000U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN4_SHIFT (12U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN4_WIDTH (1U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_INP_VAL_F_IN4_SHIFT)) & GTM_gtm_cls0_TIM0_INP_VAL_F_IN4_MASK) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN5_MASK (0x2000U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN5_SHIFT (13U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN5_WIDTH (1U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_INP_VAL_F_IN5_SHIFT)) & GTM_gtm_cls0_TIM0_INP_VAL_F_IN5_MASK) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN6_MASK (0x4000U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN6_SHIFT (14U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN6_WIDTH (1U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_INP_VAL_F_IN6_SHIFT)) & GTM_gtm_cls0_TIM0_INP_VAL_F_IN6_MASK) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN7_MASK (0x8000U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN7_SHIFT (15U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN7_WIDTH (1U) #define GTM_gtm_cls0_TIM0_INP_VAL_F_IN7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_INP_VAL_F_IN7_SHIFT)) & GTM_gtm_cls0_TIM0_INP_VAL_F_IN7_MASK) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN0_MASK (0x10000U) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN0_SHIFT (16U) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN0_WIDTH (1U) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN0_SHIFT)) & GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN0_MASK) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN1_MASK (0x20000U) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN1_SHIFT (17U) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN1_WIDTH (1U) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN1_SHIFT)) & GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN1_MASK) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN2_MASK (0x40000U) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN2_SHIFT (18U) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN2_WIDTH (1U) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN2_SHIFT)) & GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN2_MASK) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN3_MASK (0x80000U) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN3_SHIFT (19U) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN3_WIDTH (1U) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN3_SHIFT)) & GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN3_MASK) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN4_MASK (0x100000U) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN4_SHIFT (20U) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN4_WIDTH (1U) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN4_SHIFT)) & GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN4_MASK) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN5_MASK (0x200000U) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN5_SHIFT (21U) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN5_WIDTH (1U) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN5_SHIFT)) & GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN5_MASK) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN6_MASK (0x400000U) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN6_SHIFT (22U) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN6_WIDTH (1U) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN6_SHIFT)) & GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN6_MASK) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN7_MASK (0x800000U) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN7_SHIFT (23U) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN7_WIDTH (1U) #define GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN7_SHIFT)) & GTM_gtm_cls0_TIM0_INP_VAL_TIM_IN7_MASK) /*! @} */ /*! @name TIM0_IN_SRC - TIM[i] AUX IN source selection register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_0_MASK (0x3U) #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_0_SHIFT (0U) #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_0_WIDTH (2U) #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_IN_SRC_VAL_0_SHIFT)) & GTM_gtm_cls0_TIM0_IN_SRC_VAL_0_MASK) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_0_MASK (0xCU) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_0_SHIFT (2U) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_0_WIDTH (2U) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_IN_SRC_MODE_0_SHIFT)) & GTM_gtm_cls0_TIM0_IN_SRC_MODE_0_MASK) #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_1_MASK (0x30U) #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_1_SHIFT (4U) #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_1_WIDTH (2U) #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_IN_SRC_VAL_1_SHIFT)) & GTM_gtm_cls0_TIM0_IN_SRC_VAL_1_MASK) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_1_MASK (0xC0U) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_1_SHIFT (6U) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_1_WIDTH (2U) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_IN_SRC_MODE_1_SHIFT)) & GTM_gtm_cls0_TIM0_IN_SRC_MODE_1_MASK) #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_2_MASK (0x300U) #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_2_SHIFT (8U) #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_2_WIDTH (2U) #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_IN_SRC_VAL_2_SHIFT)) & GTM_gtm_cls0_TIM0_IN_SRC_VAL_2_MASK) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_2_MASK (0xC00U) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_2_SHIFT (10U) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_2_WIDTH (2U) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_IN_SRC_MODE_2_SHIFT)) & GTM_gtm_cls0_TIM0_IN_SRC_MODE_2_MASK) #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_3_MASK (0x3000U) #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_3_SHIFT (12U) #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_3_WIDTH (2U) #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_IN_SRC_VAL_3_SHIFT)) & GTM_gtm_cls0_TIM0_IN_SRC_VAL_3_MASK) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_3_MASK (0xC000U) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_3_SHIFT (14U) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_3_WIDTH (2U) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_IN_SRC_MODE_3_SHIFT)) & GTM_gtm_cls0_TIM0_IN_SRC_MODE_3_MASK) #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_4_MASK (0x30000U) #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_4_SHIFT (16U) #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_4_WIDTH (2U) #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_IN_SRC_VAL_4_SHIFT)) & GTM_gtm_cls0_TIM0_IN_SRC_VAL_4_MASK) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_4_MASK (0xC0000U) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_4_SHIFT (18U) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_4_WIDTH (2U) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_IN_SRC_MODE_4_SHIFT)) & GTM_gtm_cls0_TIM0_IN_SRC_MODE_4_MASK) #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_5_MASK (0x300000U) #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_5_SHIFT (20U) #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_5_WIDTH (2U) #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_IN_SRC_VAL_5_SHIFT)) & GTM_gtm_cls0_TIM0_IN_SRC_VAL_5_MASK) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_5_MASK (0xC00000U) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_5_SHIFT (22U) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_5_WIDTH (2U) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_IN_SRC_MODE_5_SHIFT)) & GTM_gtm_cls0_TIM0_IN_SRC_MODE_5_MASK) #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_6_MASK (0x3000000U) #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_6_SHIFT (24U) #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_6_WIDTH (2U) #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_IN_SRC_VAL_6_SHIFT)) & GTM_gtm_cls0_TIM0_IN_SRC_VAL_6_MASK) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_6_MASK (0xC000000U) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_6_SHIFT (26U) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_6_WIDTH (2U) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_IN_SRC_MODE_6_SHIFT)) & GTM_gtm_cls0_TIM0_IN_SRC_MODE_6_MASK) #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_7_MASK (0x30000000U) #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_7_SHIFT (28U) #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_7_WIDTH (2U) #define GTM_gtm_cls0_TIM0_IN_SRC_VAL_7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_IN_SRC_VAL_7_SHIFT)) & GTM_gtm_cls0_TIM0_IN_SRC_VAL_7_MASK) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_7_MASK (0xC0000000U) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_7_SHIFT (30U) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_7_WIDTH (2U) #define GTM_gtm_cls0_TIM0_IN_SRC_MODE_7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_IN_SRC_MODE_7_SHIFT)) & GTM_gtm_cls0_TIM0_IN_SRC_MODE_7_MASK) /*! @} */ /*! @name TIM0_RST - TIM[i] global software reset register */ /*! @{ */ #define GTM_gtm_cls0_TIM0_RST_RST_CH0_MASK (0x1U) #define GTM_gtm_cls0_TIM0_RST_RST_CH0_SHIFT (0U) #define GTM_gtm_cls0_TIM0_RST_RST_CH0_WIDTH (1U) #define GTM_gtm_cls0_TIM0_RST_RST_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_RST_RST_CH0_SHIFT)) & GTM_gtm_cls0_TIM0_RST_RST_CH0_MASK) #define GTM_gtm_cls0_TIM0_RST_RST_CH1_MASK (0x2U) #define GTM_gtm_cls0_TIM0_RST_RST_CH1_SHIFT (1U) #define GTM_gtm_cls0_TIM0_RST_RST_CH1_WIDTH (1U) #define GTM_gtm_cls0_TIM0_RST_RST_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_RST_RST_CH1_SHIFT)) & GTM_gtm_cls0_TIM0_RST_RST_CH1_MASK) #define GTM_gtm_cls0_TIM0_RST_RST_CH2_MASK (0x4U) #define GTM_gtm_cls0_TIM0_RST_RST_CH2_SHIFT (2U) #define GTM_gtm_cls0_TIM0_RST_RST_CH2_WIDTH (1U) #define GTM_gtm_cls0_TIM0_RST_RST_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_RST_RST_CH2_SHIFT)) & GTM_gtm_cls0_TIM0_RST_RST_CH2_MASK) #define GTM_gtm_cls0_TIM0_RST_RST_CH3_MASK (0x8U) #define GTM_gtm_cls0_TIM0_RST_RST_CH3_SHIFT (3U) #define GTM_gtm_cls0_TIM0_RST_RST_CH3_WIDTH (1U) #define GTM_gtm_cls0_TIM0_RST_RST_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_RST_RST_CH3_SHIFT)) & GTM_gtm_cls0_TIM0_RST_RST_CH3_MASK) #define GTM_gtm_cls0_TIM0_RST_RST_CH4_MASK (0x10U) #define GTM_gtm_cls0_TIM0_RST_RST_CH4_SHIFT (4U) #define GTM_gtm_cls0_TIM0_RST_RST_CH4_WIDTH (1U) #define GTM_gtm_cls0_TIM0_RST_RST_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_RST_RST_CH4_SHIFT)) & GTM_gtm_cls0_TIM0_RST_RST_CH4_MASK) #define GTM_gtm_cls0_TIM0_RST_RST_CH5_MASK (0x20U) #define GTM_gtm_cls0_TIM0_RST_RST_CH5_SHIFT (5U) #define GTM_gtm_cls0_TIM0_RST_RST_CH5_WIDTH (1U) #define GTM_gtm_cls0_TIM0_RST_RST_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_RST_RST_CH5_SHIFT)) & GTM_gtm_cls0_TIM0_RST_RST_CH5_MASK) #define GTM_gtm_cls0_TIM0_RST_RST_CH6_MASK (0x40U) #define GTM_gtm_cls0_TIM0_RST_RST_CH6_SHIFT (6U) #define GTM_gtm_cls0_TIM0_RST_RST_CH6_WIDTH (1U) #define GTM_gtm_cls0_TIM0_RST_RST_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_RST_RST_CH6_SHIFT)) & GTM_gtm_cls0_TIM0_RST_RST_CH6_MASK) #define GTM_gtm_cls0_TIM0_RST_RST_CH7_MASK (0x80U) #define GTM_gtm_cls0_TIM0_RST_RST_CH7_SHIFT (7U) #define GTM_gtm_cls0_TIM0_RST_RST_CH7_WIDTH (1U) #define GTM_gtm_cls0_TIM0_RST_RST_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TIM0_RST_RST_CH7_SHIFT)) & GTM_gtm_cls0_TIM0_RST_RST_CH7_MASK) /*! @} */ /*! @name TOM0_CH0_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH0_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH0_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH0_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH0_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH0_CTRL_SL_SHIFT)) & GTM_gtm_cls0_TOM0_CH0_CTRL_SL_MASK) #define GTM_gtm_cls0_TOM0_CH0_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH0_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls0_TOM0_CH0_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls0_TOM0_CH0_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH0_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls0_TOM0_CH0_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls0_TOM0_CH0_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH0_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH0_CTRL_UDMODE_MASK) #define GTM_gtm_cls0_TOM0_CH0_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH0_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls0_TOM0_CH0_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls0_TOM0_CH0_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH0_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH0_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH0_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH0_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH0_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH0_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH0_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH0_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH0_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH0_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH0_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH0_CTRL_SPE_TRIG_MASK (0x2000000U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_SPE_TRIG_SHIFT (25U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_SPE_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_SPE_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH0_CTRL_SPE_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH0_CTRL_SPE_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH0_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH0_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_TOM0_CH0_CTRL_OSM_MASK) #define GTM_gtm_cls0_TOM0_CH0_CTRL_SPEM_MASK (0x10000000U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_SPEM_SHIFT (28U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_SPEM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_SPEM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH0_CTRL_SPEM_SHIFT)) & GTM_gtm_cls0_TOM0_CH0_CTRL_SPEM_MASK) #define GTM_gtm_cls0_TOM0_CH0_CTRL_GCM_MASK (0x20000000U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_GCM_SHIFT (29U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_GCM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_GCM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH0_CTRL_GCM_SHIFT)) & GTM_gtm_cls0_TOM0_CH0_CTRL_GCM_MASK) #define GTM_gtm_cls0_TOM0_CH0_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH0_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls0_TOM0_CH0_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM0_CH0_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH0_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH0_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH0_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH0_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH0_SR0_SR0_SHIFT)) & GTM_gtm_cls0_TOM0_CH0_SR0_SR0_MASK) /*! @} */ /*! @name TOM0_CH0_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH0_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH0_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH0_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH0_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH0_SR1_SR1_SHIFT)) & GTM_gtm_cls0_TOM0_CH0_SR1_SR1_MASK) /*! @} */ /*! @name TOM0_CH0_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH0_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH0_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH0_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH0_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH0_CM0_CM0_SHIFT)) & GTM_gtm_cls0_TOM0_CH0_CM0_CM0_MASK) /*! @} */ /*! @name TOM0_CH0_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH0_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH0_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH0_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH0_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH0_CM1_CM1_SHIFT)) & GTM_gtm_cls0_TOM0_CH0_CM1_CM1_MASK) /*! @} */ /*! @name TOM0_CH0_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH0_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH0_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH0_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH0_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH0_CN0_CN0_SHIFT)) & GTM_gtm_cls0_TOM0_CH0_CN0_CN0_MASK) /*! @} */ /*! @name TOM0_CH0_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH0_STAT_OL_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH0_STAT_OL_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH0_STAT_OL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH0_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH0_STAT_OL_SHIFT)) & GTM_gtm_cls0_TOM0_CH0_STAT_OL_MASK) #define GTM_gtm_cls0_TOM0_CH0_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls0_TOM0_CH0_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls0_TOM0_CH0_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH0_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH0_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls0_TOM0_CH0_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM0_CH0_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH0_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH0_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH0_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH0_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH0_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH0_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH0_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH0_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH0_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH0_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH0_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH0_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH0_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH0_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH0_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH0_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH0_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH0_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH0_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls0_TOM0_CH0_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH0_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH0_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH0_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH0_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH0_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM0_CH0_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH0_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH0_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH0_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH0_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH0_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH0_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH0_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH0_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH0_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH0_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH0_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH0_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH0_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH0_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_TOM0_CH0_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH0_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH0_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH0_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH0_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM0_CH0_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH0_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH0_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH0_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls0_TOM0_CH0_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH0_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH0_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH0_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM0_CH1_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH1_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH1_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH1_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH1_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH1_CTRL_SL_SHIFT)) & GTM_gtm_cls0_TOM0_CH1_CTRL_SL_MASK) #define GTM_gtm_cls0_TOM0_CH1_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH1_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls0_TOM0_CH1_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls0_TOM0_CH1_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH1_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls0_TOM0_CH1_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls0_TOM0_CH1_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH1_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH1_CTRL_UDMODE_MASK) #define GTM_gtm_cls0_TOM0_CH1_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH1_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls0_TOM0_CH1_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls0_TOM0_CH1_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH1_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH1_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH1_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH1_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH1_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH1_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH1_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH1_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH1_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH1_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH1_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH1_CTRL_SPE_TRIG_MASK (0x2000000U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_SPE_TRIG_SHIFT (25U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_SPE_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_SPE_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH1_CTRL_SPE_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH1_CTRL_SPE_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH1_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH1_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_TOM0_CH1_CTRL_OSM_MASK) #define GTM_gtm_cls0_TOM0_CH1_CTRL_SPEM_MASK (0x10000000U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_SPEM_SHIFT (28U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_SPEM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_SPEM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH1_CTRL_SPEM_SHIFT)) & GTM_gtm_cls0_TOM0_CH1_CTRL_SPEM_MASK) #define GTM_gtm_cls0_TOM0_CH1_CTRL_GCM_MASK (0x20000000U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_GCM_SHIFT (29U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_GCM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_GCM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH1_CTRL_GCM_SHIFT)) & GTM_gtm_cls0_TOM0_CH1_CTRL_GCM_MASK) #define GTM_gtm_cls0_TOM0_CH1_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH1_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls0_TOM0_CH1_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM0_CH1_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH1_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH1_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH1_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH1_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH1_SR0_SR0_SHIFT)) & GTM_gtm_cls0_TOM0_CH1_SR0_SR0_MASK) /*! @} */ /*! @name TOM0_CH1_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH1_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH1_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH1_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH1_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH1_SR1_SR1_SHIFT)) & GTM_gtm_cls0_TOM0_CH1_SR1_SR1_MASK) /*! @} */ /*! @name TOM0_CH1_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH1_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH1_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH1_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH1_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH1_CM0_CM0_SHIFT)) & GTM_gtm_cls0_TOM0_CH1_CM0_CM0_MASK) /*! @} */ /*! @name TOM0_CH1_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH1_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH1_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH1_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH1_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH1_CM1_CM1_SHIFT)) & GTM_gtm_cls0_TOM0_CH1_CM1_CM1_MASK) /*! @} */ /*! @name TOM0_CH1_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH1_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH1_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH1_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH1_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH1_CN0_CN0_SHIFT)) & GTM_gtm_cls0_TOM0_CH1_CN0_CN0_MASK) /*! @} */ /*! @name TOM0_CH1_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH1_STAT_OL_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH1_STAT_OL_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH1_STAT_OL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH1_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH1_STAT_OL_SHIFT)) & GTM_gtm_cls0_TOM0_CH1_STAT_OL_MASK) #define GTM_gtm_cls0_TOM0_CH1_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls0_TOM0_CH1_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls0_TOM0_CH1_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH1_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH1_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls0_TOM0_CH1_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM0_CH1_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH1_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH1_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH1_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH1_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH1_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH1_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH1_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH1_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH1_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH1_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH1_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH1_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH1_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH1_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH1_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH1_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH1_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH1_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH1_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls0_TOM0_CH1_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH1_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH1_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH1_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH1_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH1_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM0_CH1_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH1_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH1_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH1_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH1_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH1_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH1_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH1_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH1_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH1_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH1_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH1_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH1_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH1_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH1_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_TOM0_CH1_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH1_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH1_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH1_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH1_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM0_CH1_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH1_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH1_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH1_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls0_TOM0_CH1_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH1_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH1_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH1_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM0_CH2_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH2_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH2_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH2_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH2_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH2_CTRL_SL_SHIFT)) & GTM_gtm_cls0_TOM0_CH2_CTRL_SL_MASK) #define GTM_gtm_cls0_TOM0_CH2_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH2_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls0_TOM0_CH2_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls0_TOM0_CH2_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH2_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls0_TOM0_CH2_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls0_TOM0_CH2_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH2_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH2_CTRL_UDMODE_MASK) #define GTM_gtm_cls0_TOM0_CH2_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH2_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls0_TOM0_CH2_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls0_TOM0_CH2_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH2_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH2_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH2_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH2_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH2_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH2_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH2_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH2_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH2_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH2_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH2_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH2_CTRL_SPE_TRIG_MASK (0x2000000U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_SPE_TRIG_SHIFT (25U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_SPE_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_SPE_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH2_CTRL_SPE_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH2_CTRL_SPE_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH2_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH2_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_TOM0_CH2_CTRL_OSM_MASK) #define GTM_gtm_cls0_TOM0_CH2_CTRL_SPEM_MASK (0x10000000U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_SPEM_SHIFT (28U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_SPEM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_SPEM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH2_CTRL_SPEM_SHIFT)) & GTM_gtm_cls0_TOM0_CH2_CTRL_SPEM_MASK) #define GTM_gtm_cls0_TOM0_CH2_CTRL_GCM_MASK (0x20000000U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_GCM_SHIFT (29U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_GCM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_GCM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH2_CTRL_GCM_SHIFT)) & GTM_gtm_cls0_TOM0_CH2_CTRL_GCM_MASK) #define GTM_gtm_cls0_TOM0_CH2_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH2_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls0_TOM0_CH2_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM0_CH2_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH2_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH2_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH2_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH2_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH2_SR0_SR0_SHIFT)) & GTM_gtm_cls0_TOM0_CH2_SR0_SR0_MASK) /*! @} */ /*! @name TOM0_CH2_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH2_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH2_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH2_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH2_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH2_SR1_SR1_SHIFT)) & GTM_gtm_cls0_TOM0_CH2_SR1_SR1_MASK) /*! @} */ /*! @name TOM0_CH2_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH2_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH2_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH2_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH2_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH2_CM0_CM0_SHIFT)) & GTM_gtm_cls0_TOM0_CH2_CM0_CM0_MASK) /*! @} */ /*! @name TOM0_CH2_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH2_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH2_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH2_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH2_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH2_CM1_CM1_SHIFT)) & GTM_gtm_cls0_TOM0_CH2_CM1_CM1_MASK) /*! @} */ /*! @name TOM0_CH2_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH2_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH2_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH2_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH2_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH2_CN0_CN0_SHIFT)) & GTM_gtm_cls0_TOM0_CH2_CN0_CN0_MASK) /*! @} */ /*! @name TOM0_CH2_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH2_STAT_OL_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH2_STAT_OL_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH2_STAT_OL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH2_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH2_STAT_OL_SHIFT)) & GTM_gtm_cls0_TOM0_CH2_STAT_OL_MASK) #define GTM_gtm_cls0_TOM0_CH2_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls0_TOM0_CH2_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls0_TOM0_CH2_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH2_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH2_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls0_TOM0_CH2_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM0_CH2_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH2_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH2_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH2_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH2_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH2_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH2_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH2_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH2_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH2_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH2_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH2_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH2_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH2_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH2_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH2_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH2_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH2_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH2_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH2_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls0_TOM0_CH2_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH2_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH2_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH2_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH2_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH2_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM0_CH2_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH2_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH2_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH2_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH2_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH2_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH2_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH2_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH2_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH2_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH2_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH2_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH2_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH2_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH2_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_TOM0_CH2_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH2_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH2_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH2_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH2_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM0_CH2_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH2_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH2_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH2_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls0_TOM0_CH2_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH2_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH2_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH2_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM0_CH3_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH3_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH3_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH3_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH3_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH3_CTRL_SL_SHIFT)) & GTM_gtm_cls0_TOM0_CH3_CTRL_SL_MASK) #define GTM_gtm_cls0_TOM0_CH3_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH3_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls0_TOM0_CH3_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls0_TOM0_CH3_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH3_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls0_TOM0_CH3_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls0_TOM0_CH3_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH3_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH3_CTRL_UDMODE_MASK) #define GTM_gtm_cls0_TOM0_CH3_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH3_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls0_TOM0_CH3_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls0_TOM0_CH3_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH3_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH3_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH3_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH3_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH3_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH3_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH3_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH3_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH3_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH3_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH3_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH3_CTRL_SPE_TRIG_MASK (0x2000000U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_SPE_TRIG_SHIFT (25U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_SPE_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_SPE_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH3_CTRL_SPE_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH3_CTRL_SPE_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH3_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH3_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_TOM0_CH3_CTRL_OSM_MASK) #define GTM_gtm_cls0_TOM0_CH3_CTRL_SPEM_MASK (0x10000000U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_SPEM_SHIFT (28U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_SPEM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_SPEM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH3_CTRL_SPEM_SHIFT)) & GTM_gtm_cls0_TOM0_CH3_CTRL_SPEM_MASK) #define GTM_gtm_cls0_TOM0_CH3_CTRL_GCM_MASK (0x20000000U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_GCM_SHIFT (29U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_GCM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_GCM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH3_CTRL_GCM_SHIFT)) & GTM_gtm_cls0_TOM0_CH3_CTRL_GCM_MASK) #define GTM_gtm_cls0_TOM0_CH3_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH3_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls0_TOM0_CH3_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM0_CH3_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH3_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH3_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH3_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH3_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH3_SR0_SR0_SHIFT)) & GTM_gtm_cls0_TOM0_CH3_SR0_SR0_MASK) /*! @} */ /*! @name TOM0_CH3_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH3_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH3_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH3_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH3_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH3_SR1_SR1_SHIFT)) & GTM_gtm_cls0_TOM0_CH3_SR1_SR1_MASK) /*! @} */ /*! @name TOM0_CH3_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH3_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH3_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH3_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH3_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH3_CM0_CM0_SHIFT)) & GTM_gtm_cls0_TOM0_CH3_CM0_CM0_MASK) /*! @} */ /*! @name TOM0_CH3_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH3_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH3_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH3_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH3_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH3_CM1_CM1_SHIFT)) & GTM_gtm_cls0_TOM0_CH3_CM1_CM1_MASK) /*! @} */ /*! @name TOM0_CH3_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH3_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH3_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH3_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH3_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH3_CN0_CN0_SHIFT)) & GTM_gtm_cls0_TOM0_CH3_CN0_CN0_MASK) /*! @} */ /*! @name TOM0_CH3_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH3_STAT_OL_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH3_STAT_OL_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH3_STAT_OL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH3_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH3_STAT_OL_SHIFT)) & GTM_gtm_cls0_TOM0_CH3_STAT_OL_MASK) #define GTM_gtm_cls0_TOM0_CH3_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls0_TOM0_CH3_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls0_TOM0_CH3_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH3_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH3_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls0_TOM0_CH3_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM0_CH3_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH3_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH3_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH3_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH3_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH3_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH3_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH3_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH3_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH3_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH3_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH3_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH3_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH3_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH3_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH3_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH3_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH3_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH3_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH3_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls0_TOM0_CH3_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH3_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH3_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH3_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH3_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH3_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM0_CH3_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH3_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH3_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH3_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH3_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH3_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH3_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH3_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH3_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH3_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH3_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH3_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH3_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH3_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH3_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_TOM0_CH3_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH3_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH3_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH3_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH3_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM0_CH3_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH3_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH3_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH3_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls0_TOM0_CH3_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH3_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH3_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH3_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM0_CH4_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH4_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH4_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH4_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH4_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH4_CTRL_SL_SHIFT)) & GTM_gtm_cls0_TOM0_CH4_CTRL_SL_MASK) #define GTM_gtm_cls0_TOM0_CH4_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH4_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls0_TOM0_CH4_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls0_TOM0_CH4_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH4_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls0_TOM0_CH4_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls0_TOM0_CH4_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH4_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH4_CTRL_UDMODE_MASK) #define GTM_gtm_cls0_TOM0_CH4_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH4_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls0_TOM0_CH4_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls0_TOM0_CH4_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH4_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH4_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH4_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH4_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH4_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH4_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH4_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH4_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH4_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH4_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH4_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH4_CTRL_SPE_TRIG_MASK (0x2000000U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_SPE_TRIG_SHIFT (25U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_SPE_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_SPE_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH4_CTRL_SPE_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH4_CTRL_SPE_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH4_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH4_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_TOM0_CH4_CTRL_OSM_MASK) #define GTM_gtm_cls0_TOM0_CH4_CTRL_SPEM_MASK (0x10000000U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_SPEM_SHIFT (28U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_SPEM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_SPEM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH4_CTRL_SPEM_SHIFT)) & GTM_gtm_cls0_TOM0_CH4_CTRL_SPEM_MASK) #define GTM_gtm_cls0_TOM0_CH4_CTRL_GCM_MASK (0x20000000U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_GCM_SHIFT (29U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_GCM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_GCM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH4_CTRL_GCM_SHIFT)) & GTM_gtm_cls0_TOM0_CH4_CTRL_GCM_MASK) #define GTM_gtm_cls0_TOM0_CH4_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH4_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls0_TOM0_CH4_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM0_CH4_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH4_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH4_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH4_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH4_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH4_SR0_SR0_SHIFT)) & GTM_gtm_cls0_TOM0_CH4_SR0_SR0_MASK) /*! @} */ /*! @name TOM0_CH4_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH4_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH4_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH4_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH4_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH4_SR1_SR1_SHIFT)) & GTM_gtm_cls0_TOM0_CH4_SR1_SR1_MASK) /*! @} */ /*! @name TOM0_CH4_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH4_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH4_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH4_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH4_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH4_CM0_CM0_SHIFT)) & GTM_gtm_cls0_TOM0_CH4_CM0_CM0_MASK) /*! @} */ /*! @name TOM0_CH4_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH4_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH4_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH4_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH4_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH4_CM1_CM1_SHIFT)) & GTM_gtm_cls0_TOM0_CH4_CM1_CM1_MASK) /*! @} */ /*! @name TOM0_CH4_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH4_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH4_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH4_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH4_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH4_CN0_CN0_SHIFT)) & GTM_gtm_cls0_TOM0_CH4_CN0_CN0_MASK) /*! @} */ /*! @name TOM0_CH4_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH4_STAT_OL_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH4_STAT_OL_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH4_STAT_OL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH4_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH4_STAT_OL_SHIFT)) & GTM_gtm_cls0_TOM0_CH4_STAT_OL_MASK) #define GTM_gtm_cls0_TOM0_CH4_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls0_TOM0_CH4_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls0_TOM0_CH4_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH4_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH4_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls0_TOM0_CH4_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM0_CH4_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH4_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH4_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH4_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH4_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH4_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH4_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH4_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH4_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH4_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH4_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH4_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH4_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH4_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH4_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH4_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH4_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH4_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH4_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH4_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls0_TOM0_CH4_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH4_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH4_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH4_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH4_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH4_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM0_CH4_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH4_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH4_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH4_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH4_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH4_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH4_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH4_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH4_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH4_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH4_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH4_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH4_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH4_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH4_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_TOM0_CH4_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH4_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH4_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH4_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH4_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM0_CH4_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH4_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH4_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH4_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls0_TOM0_CH4_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH4_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH4_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH4_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM0_CH5_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH5_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH5_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH5_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH5_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH5_CTRL_SL_SHIFT)) & GTM_gtm_cls0_TOM0_CH5_CTRL_SL_MASK) #define GTM_gtm_cls0_TOM0_CH5_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH5_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls0_TOM0_CH5_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls0_TOM0_CH5_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH5_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls0_TOM0_CH5_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls0_TOM0_CH5_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH5_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH5_CTRL_UDMODE_MASK) #define GTM_gtm_cls0_TOM0_CH5_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH5_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls0_TOM0_CH5_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls0_TOM0_CH5_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH5_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH5_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH5_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH5_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH5_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH5_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH5_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH5_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH5_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH5_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH5_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH5_CTRL_SPE_TRIG_MASK (0x2000000U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_SPE_TRIG_SHIFT (25U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_SPE_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_SPE_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH5_CTRL_SPE_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH5_CTRL_SPE_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH5_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH5_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_TOM0_CH5_CTRL_OSM_MASK) #define GTM_gtm_cls0_TOM0_CH5_CTRL_SPEM_MASK (0x10000000U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_SPEM_SHIFT (28U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_SPEM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_SPEM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH5_CTRL_SPEM_SHIFT)) & GTM_gtm_cls0_TOM0_CH5_CTRL_SPEM_MASK) #define GTM_gtm_cls0_TOM0_CH5_CTRL_GCM_MASK (0x20000000U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_GCM_SHIFT (29U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_GCM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_GCM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH5_CTRL_GCM_SHIFT)) & GTM_gtm_cls0_TOM0_CH5_CTRL_GCM_MASK) #define GTM_gtm_cls0_TOM0_CH5_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH5_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls0_TOM0_CH5_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM0_CH5_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH5_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH5_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH5_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH5_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH5_SR0_SR0_SHIFT)) & GTM_gtm_cls0_TOM0_CH5_SR0_SR0_MASK) /*! @} */ /*! @name TOM0_CH5_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH5_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH5_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH5_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH5_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH5_SR1_SR1_SHIFT)) & GTM_gtm_cls0_TOM0_CH5_SR1_SR1_MASK) /*! @} */ /*! @name TOM0_CH5_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH5_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH5_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH5_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH5_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH5_CM0_CM0_SHIFT)) & GTM_gtm_cls0_TOM0_CH5_CM0_CM0_MASK) /*! @} */ /*! @name TOM0_CH5_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH5_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH5_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH5_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH5_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH5_CM1_CM1_SHIFT)) & GTM_gtm_cls0_TOM0_CH5_CM1_CM1_MASK) /*! @} */ /*! @name TOM0_CH5_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH5_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH5_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH5_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH5_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH5_CN0_CN0_SHIFT)) & GTM_gtm_cls0_TOM0_CH5_CN0_CN0_MASK) /*! @} */ /*! @name TOM0_CH5_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH5_STAT_OL_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH5_STAT_OL_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH5_STAT_OL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH5_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH5_STAT_OL_SHIFT)) & GTM_gtm_cls0_TOM0_CH5_STAT_OL_MASK) #define GTM_gtm_cls0_TOM0_CH5_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls0_TOM0_CH5_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls0_TOM0_CH5_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH5_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH5_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls0_TOM0_CH5_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM0_CH5_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH5_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH5_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH5_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH5_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH5_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH5_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH5_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH5_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH5_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH5_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH5_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH5_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH5_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH5_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH5_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH5_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH5_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH5_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH5_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls0_TOM0_CH5_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH5_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH5_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH5_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH5_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH5_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM0_CH5_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH5_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH5_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH5_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH5_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH5_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH5_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH5_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH5_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH5_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH5_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH5_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH5_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH5_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH5_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_TOM0_CH5_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH5_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH5_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH5_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH5_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM0_CH5_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH5_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH5_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH5_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls0_TOM0_CH5_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH5_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH5_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH5_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM0_CH6_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH6_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH6_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH6_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH6_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH6_CTRL_SL_SHIFT)) & GTM_gtm_cls0_TOM0_CH6_CTRL_SL_MASK) #define GTM_gtm_cls0_TOM0_CH6_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH6_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls0_TOM0_CH6_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls0_TOM0_CH6_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH6_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls0_TOM0_CH6_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls0_TOM0_CH6_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH6_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH6_CTRL_UDMODE_MASK) #define GTM_gtm_cls0_TOM0_CH6_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH6_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls0_TOM0_CH6_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls0_TOM0_CH6_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH6_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH6_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH6_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH6_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH6_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH6_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH6_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH6_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH6_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH6_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH6_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH6_CTRL_SPE_TRIG_MASK (0x2000000U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_SPE_TRIG_SHIFT (25U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_SPE_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_SPE_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH6_CTRL_SPE_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH6_CTRL_SPE_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH6_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH6_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_TOM0_CH6_CTRL_OSM_MASK) #define GTM_gtm_cls0_TOM0_CH6_CTRL_SPEM_MASK (0x10000000U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_SPEM_SHIFT (28U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_SPEM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_SPEM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH6_CTRL_SPEM_SHIFT)) & GTM_gtm_cls0_TOM0_CH6_CTRL_SPEM_MASK) #define GTM_gtm_cls0_TOM0_CH6_CTRL_GCM_MASK (0x20000000U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_GCM_SHIFT (29U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_GCM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_GCM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH6_CTRL_GCM_SHIFT)) & GTM_gtm_cls0_TOM0_CH6_CTRL_GCM_MASK) #define GTM_gtm_cls0_TOM0_CH6_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH6_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls0_TOM0_CH6_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM0_CH6_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH6_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH6_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH6_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH6_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH6_SR0_SR0_SHIFT)) & GTM_gtm_cls0_TOM0_CH6_SR0_SR0_MASK) /*! @} */ /*! @name TOM0_CH6_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH6_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH6_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH6_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH6_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH6_SR1_SR1_SHIFT)) & GTM_gtm_cls0_TOM0_CH6_SR1_SR1_MASK) /*! @} */ /*! @name TOM0_CH6_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH6_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH6_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH6_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH6_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH6_CM0_CM0_SHIFT)) & GTM_gtm_cls0_TOM0_CH6_CM0_CM0_MASK) /*! @} */ /*! @name TOM0_CH6_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH6_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH6_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH6_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH6_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH6_CM1_CM1_SHIFT)) & GTM_gtm_cls0_TOM0_CH6_CM1_CM1_MASK) /*! @} */ /*! @name TOM0_CH6_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH6_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH6_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH6_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH6_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH6_CN0_CN0_SHIFT)) & GTM_gtm_cls0_TOM0_CH6_CN0_CN0_MASK) /*! @} */ /*! @name TOM0_CH6_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH6_STAT_OL_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH6_STAT_OL_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH6_STAT_OL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH6_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH6_STAT_OL_SHIFT)) & GTM_gtm_cls0_TOM0_CH6_STAT_OL_MASK) #define GTM_gtm_cls0_TOM0_CH6_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls0_TOM0_CH6_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls0_TOM0_CH6_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH6_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH6_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls0_TOM0_CH6_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM0_CH6_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH6_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH6_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH6_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH6_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH6_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH6_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH6_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH6_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH6_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH6_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH6_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH6_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH6_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH6_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH6_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH6_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH6_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH6_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH6_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls0_TOM0_CH6_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH6_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH6_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH6_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH6_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH6_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM0_CH6_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH6_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH6_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH6_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH6_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH6_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH6_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH6_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH6_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH6_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH6_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH6_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH6_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH6_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH6_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_TOM0_CH6_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH6_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH6_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH6_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH6_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM0_CH6_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH6_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH6_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH6_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls0_TOM0_CH6_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH6_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH6_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH6_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM0_CH7_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH7_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH7_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH7_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH7_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH7_CTRL_SL_SHIFT)) & GTM_gtm_cls0_TOM0_CH7_CTRL_SL_MASK) #define GTM_gtm_cls0_TOM0_CH7_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH7_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls0_TOM0_CH7_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls0_TOM0_CH7_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH7_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls0_TOM0_CH7_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls0_TOM0_CH7_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH7_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH7_CTRL_UDMODE_MASK) #define GTM_gtm_cls0_TOM0_CH7_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH7_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls0_TOM0_CH7_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls0_TOM0_CH7_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH7_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH7_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH7_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH7_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH7_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH7_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH7_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH7_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH7_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH7_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH7_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH7_CTRL_SPE_TRIG_MASK (0x2000000U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_SPE_TRIG_SHIFT (25U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_SPE_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_SPE_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH7_CTRL_SPE_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH7_CTRL_SPE_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH7_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH7_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_TOM0_CH7_CTRL_OSM_MASK) #define GTM_gtm_cls0_TOM0_CH7_CTRL_SPEM_MASK (0x10000000U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_SPEM_SHIFT (28U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_SPEM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_SPEM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH7_CTRL_SPEM_SHIFT)) & GTM_gtm_cls0_TOM0_CH7_CTRL_SPEM_MASK) #define GTM_gtm_cls0_TOM0_CH7_CTRL_GCM_MASK (0x20000000U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_GCM_SHIFT (29U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_GCM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_GCM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH7_CTRL_GCM_SHIFT)) & GTM_gtm_cls0_TOM0_CH7_CTRL_GCM_MASK) #define GTM_gtm_cls0_TOM0_CH7_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH7_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls0_TOM0_CH7_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM0_CH7_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH7_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH7_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH7_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH7_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH7_SR0_SR0_SHIFT)) & GTM_gtm_cls0_TOM0_CH7_SR0_SR0_MASK) /*! @} */ /*! @name TOM0_CH7_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH7_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH7_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH7_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH7_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH7_SR1_SR1_SHIFT)) & GTM_gtm_cls0_TOM0_CH7_SR1_SR1_MASK) /*! @} */ /*! @name TOM0_CH7_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH7_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH7_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH7_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH7_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH7_CM0_CM0_SHIFT)) & GTM_gtm_cls0_TOM0_CH7_CM0_CM0_MASK) /*! @} */ /*! @name TOM0_CH7_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH7_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH7_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH7_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH7_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH7_CM1_CM1_SHIFT)) & GTM_gtm_cls0_TOM0_CH7_CM1_CM1_MASK) /*! @} */ /*! @name TOM0_CH7_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH7_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH7_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH7_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH7_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH7_CN0_CN0_SHIFT)) & GTM_gtm_cls0_TOM0_CH7_CN0_CN0_MASK) /*! @} */ /*! @name TOM0_CH7_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH7_STAT_OL_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH7_STAT_OL_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH7_STAT_OL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH7_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH7_STAT_OL_SHIFT)) & GTM_gtm_cls0_TOM0_CH7_STAT_OL_MASK) #define GTM_gtm_cls0_TOM0_CH7_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls0_TOM0_CH7_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls0_TOM0_CH7_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH7_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH7_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls0_TOM0_CH7_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM0_CH7_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH7_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH7_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH7_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH7_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH7_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH7_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH7_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH7_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH7_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH7_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH7_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH7_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH7_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH7_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH7_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH7_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH7_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH7_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH7_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls0_TOM0_CH7_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH7_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH7_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH7_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH7_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH7_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM0_CH7_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH7_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH7_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH7_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH7_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH7_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH7_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH7_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH7_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH7_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH7_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH7_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH7_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH7_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH7_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_TOM0_CH7_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH7_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH7_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH7_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH7_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM0_CH7_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH7_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH7_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH7_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls0_TOM0_CH7_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH7_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH7_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH7_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM0_CH8_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH8_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH8_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH8_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH8_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH8_CTRL_SL_SHIFT)) & GTM_gtm_cls0_TOM0_CH8_CTRL_SL_MASK) #define GTM_gtm_cls0_TOM0_CH8_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH8_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls0_TOM0_CH8_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls0_TOM0_CH8_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH8_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls0_TOM0_CH8_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls0_TOM0_CH8_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH8_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH8_CTRL_UDMODE_MASK) #define GTM_gtm_cls0_TOM0_CH8_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH8_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls0_TOM0_CH8_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls0_TOM0_CH8_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH8_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH8_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH8_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH8_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH8_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH8_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH8_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH8_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH8_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH8_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH8_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH8_CTRL_SPE_TRIG_MASK (0x2000000U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_SPE_TRIG_SHIFT (25U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_SPE_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_SPE_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH8_CTRL_SPE_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH8_CTRL_SPE_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH8_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH8_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_TOM0_CH8_CTRL_OSM_MASK) #define GTM_gtm_cls0_TOM0_CH8_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH8_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls0_TOM0_CH8_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM0_CH8_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH8_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH8_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH8_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH8_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH8_SR0_SR0_SHIFT)) & GTM_gtm_cls0_TOM0_CH8_SR0_SR0_MASK) /*! @} */ /*! @name TOM0_CH8_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH8_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH8_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH8_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH8_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH8_SR1_SR1_SHIFT)) & GTM_gtm_cls0_TOM0_CH8_SR1_SR1_MASK) /*! @} */ /*! @name TOM0_CH8_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH8_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH8_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH8_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH8_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH8_CM0_CM0_SHIFT)) & GTM_gtm_cls0_TOM0_CH8_CM0_CM0_MASK) /*! @} */ /*! @name TOM0_CH8_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH8_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH8_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH8_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH8_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH8_CM1_CM1_SHIFT)) & GTM_gtm_cls0_TOM0_CH8_CM1_CM1_MASK) /*! @} */ /*! @name TOM0_CH8_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH8_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH8_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH8_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH8_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH8_CN0_CN0_SHIFT)) & GTM_gtm_cls0_TOM0_CH8_CN0_CN0_MASK) /*! @} */ /*! @name TOM0_CH8_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH8_STAT_OL_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH8_STAT_OL_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH8_STAT_OL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH8_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH8_STAT_OL_SHIFT)) & GTM_gtm_cls0_TOM0_CH8_STAT_OL_MASK) #define GTM_gtm_cls0_TOM0_CH8_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls0_TOM0_CH8_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls0_TOM0_CH8_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH8_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH8_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls0_TOM0_CH8_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM0_CH8_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH8_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH8_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH8_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH8_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH8_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH8_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH8_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH8_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH8_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH8_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH8_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH8_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH8_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH8_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH8_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH8_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH8_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH8_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH8_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls0_TOM0_CH8_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH8_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH8_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH8_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH8_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH8_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM0_CH8_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH8_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH8_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH8_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH8_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH8_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH8_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH8_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH8_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH8_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH8_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH8_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH8_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH8_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH8_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_TOM0_CH8_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH8_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH8_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH8_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH8_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM0_CH8_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH8_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH8_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH8_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls0_TOM0_CH8_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH8_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH8_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH8_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM0_CH9_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH9_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH9_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH9_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH9_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH9_CTRL_SL_SHIFT)) & GTM_gtm_cls0_TOM0_CH9_CTRL_SL_MASK) #define GTM_gtm_cls0_TOM0_CH9_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH9_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls0_TOM0_CH9_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls0_TOM0_CH9_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH9_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls0_TOM0_CH9_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls0_TOM0_CH9_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH9_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH9_CTRL_UDMODE_MASK) #define GTM_gtm_cls0_TOM0_CH9_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH9_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls0_TOM0_CH9_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls0_TOM0_CH9_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH9_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH9_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH9_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH9_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH9_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH9_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH9_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH9_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH9_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH9_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH9_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH9_CTRL_SPE_TRIG_MASK (0x2000000U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_SPE_TRIG_SHIFT (25U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_SPE_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_SPE_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH9_CTRL_SPE_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH9_CTRL_SPE_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH9_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH9_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_TOM0_CH9_CTRL_OSM_MASK) #define GTM_gtm_cls0_TOM0_CH9_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH9_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls0_TOM0_CH9_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM0_CH9_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH9_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH9_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH9_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH9_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH9_SR0_SR0_SHIFT)) & GTM_gtm_cls0_TOM0_CH9_SR0_SR0_MASK) /*! @} */ /*! @name TOM0_CH9_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH9_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH9_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH9_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH9_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH9_SR1_SR1_SHIFT)) & GTM_gtm_cls0_TOM0_CH9_SR1_SR1_MASK) /*! @} */ /*! @name TOM0_CH9_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH9_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH9_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH9_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH9_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH9_CM0_CM0_SHIFT)) & GTM_gtm_cls0_TOM0_CH9_CM0_CM0_MASK) /*! @} */ /*! @name TOM0_CH9_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH9_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH9_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH9_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH9_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH9_CM1_CM1_SHIFT)) & GTM_gtm_cls0_TOM0_CH9_CM1_CM1_MASK) /*! @} */ /*! @name TOM0_CH9_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH9_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH9_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH9_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH9_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH9_CN0_CN0_SHIFT)) & GTM_gtm_cls0_TOM0_CH9_CN0_CN0_MASK) /*! @} */ /*! @name TOM0_CH9_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH9_STAT_OL_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH9_STAT_OL_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH9_STAT_OL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH9_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH9_STAT_OL_SHIFT)) & GTM_gtm_cls0_TOM0_CH9_STAT_OL_MASK) #define GTM_gtm_cls0_TOM0_CH9_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls0_TOM0_CH9_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls0_TOM0_CH9_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH9_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH9_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls0_TOM0_CH9_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM0_CH9_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH9_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH9_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH9_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH9_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH9_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH9_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH9_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH9_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH9_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH9_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH9_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH9_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH9_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH9_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH9_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH9_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH9_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH9_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH9_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls0_TOM0_CH9_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH9_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH9_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH9_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH9_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH9_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM0_CH9_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH9_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH9_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH9_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH9_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH9_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH9_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH9_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH9_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH9_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH9_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH9_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH9_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH9_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH9_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_TOM0_CH9_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH9_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH9_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH9_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH9_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM0_CH9_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH9_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH9_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH9_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls0_TOM0_CH9_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH9_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH9_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH9_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM0_CH10_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH10_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH10_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH10_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH10_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH10_CTRL_SL_SHIFT)) & GTM_gtm_cls0_TOM0_CH10_CTRL_SL_MASK) #define GTM_gtm_cls0_TOM0_CH10_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH10_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls0_TOM0_CH10_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls0_TOM0_CH10_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH10_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls0_TOM0_CH10_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls0_TOM0_CH10_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH10_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH10_CTRL_UDMODE_MASK) #define GTM_gtm_cls0_TOM0_CH10_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH10_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls0_TOM0_CH10_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls0_TOM0_CH10_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH10_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH10_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH10_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH10_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH10_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH10_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH10_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH10_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH10_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH10_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH10_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH10_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH10_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_TOM0_CH10_CTRL_OSM_MASK) #define GTM_gtm_cls0_TOM0_CH10_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH10_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls0_TOM0_CH10_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM0_CH10_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH10_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH10_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH10_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH10_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH10_SR0_SR0_SHIFT)) & GTM_gtm_cls0_TOM0_CH10_SR0_SR0_MASK) /*! @} */ /*! @name TOM0_CH10_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH10_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH10_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH10_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH10_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH10_SR1_SR1_SHIFT)) & GTM_gtm_cls0_TOM0_CH10_SR1_SR1_MASK) /*! @} */ /*! @name TOM0_CH10_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH10_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH10_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH10_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH10_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH10_CM0_CM0_SHIFT)) & GTM_gtm_cls0_TOM0_CH10_CM0_CM0_MASK) /*! @} */ /*! @name TOM0_CH10_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH10_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH10_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH10_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH10_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH10_CM1_CM1_SHIFT)) & GTM_gtm_cls0_TOM0_CH10_CM1_CM1_MASK) /*! @} */ /*! @name TOM0_CH10_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH10_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH10_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH10_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH10_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH10_CN0_CN0_SHIFT)) & GTM_gtm_cls0_TOM0_CH10_CN0_CN0_MASK) /*! @} */ /*! @name TOM0_CH10_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH10_STAT_OL_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH10_STAT_OL_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH10_STAT_OL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH10_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH10_STAT_OL_SHIFT)) & GTM_gtm_cls0_TOM0_CH10_STAT_OL_MASK) #define GTM_gtm_cls0_TOM0_CH10_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls0_TOM0_CH10_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls0_TOM0_CH10_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH10_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH10_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls0_TOM0_CH10_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM0_CH10_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH10_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH10_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH10_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH10_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH10_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH10_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH10_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH10_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH10_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH10_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH10_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH10_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH10_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH10_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH10_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH10_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH10_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH10_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH10_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls0_TOM0_CH10_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH10_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH10_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH10_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH10_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH10_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM0_CH10_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH10_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH10_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH10_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH10_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH10_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH10_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH10_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH10_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH10_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH10_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH10_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH10_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH10_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH10_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_TOM0_CH10_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH10_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH10_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH10_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH10_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM0_CH10_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH10_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH10_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH10_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls0_TOM0_CH10_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH10_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH10_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH10_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM0_CH11_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH11_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH11_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH11_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH11_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH11_CTRL_SL_SHIFT)) & GTM_gtm_cls0_TOM0_CH11_CTRL_SL_MASK) #define GTM_gtm_cls0_TOM0_CH11_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH11_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls0_TOM0_CH11_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls0_TOM0_CH11_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH11_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls0_TOM0_CH11_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls0_TOM0_CH11_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH11_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH11_CTRL_UDMODE_MASK) #define GTM_gtm_cls0_TOM0_CH11_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH11_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls0_TOM0_CH11_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls0_TOM0_CH11_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH11_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH11_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH11_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH11_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH11_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH11_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH11_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH11_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH11_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH11_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH11_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH11_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH11_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_TOM0_CH11_CTRL_OSM_MASK) #define GTM_gtm_cls0_TOM0_CH11_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH11_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls0_TOM0_CH11_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM0_CH11_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH11_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH11_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH11_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH11_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH11_SR0_SR0_SHIFT)) & GTM_gtm_cls0_TOM0_CH11_SR0_SR0_MASK) /*! @} */ /*! @name TOM0_CH11_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH11_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH11_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH11_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH11_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH11_SR1_SR1_SHIFT)) & GTM_gtm_cls0_TOM0_CH11_SR1_SR1_MASK) /*! @} */ /*! @name TOM0_CH11_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH11_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH11_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH11_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH11_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH11_CM0_CM0_SHIFT)) & GTM_gtm_cls0_TOM0_CH11_CM0_CM0_MASK) /*! @} */ /*! @name TOM0_CH11_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH11_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH11_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH11_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH11_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH11_CM1_CM1_SHIFT)) & GTM_gtm_cls0_TOM0_CH11_CM1_CM1_MASK) /*! @} */ /*! @name TOM0_CH11_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH11_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH11_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH11_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH11_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH11_CN0_CN0_SHIFT)) & GTM_gtm_cls0_TOM0_CH11_CN0_CN0_MASK) /*! @} */ /*! @name TOM0_CH11_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH11_STAT_OL_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH11_STAT_OL_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH11_STAT_OL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH11_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH11_STAT_OL_SHIFT)) & GTM_gtm_cls0_TOM0_CH11_STAT_OL_MASK) #define GTM_gtm_cls0_TOM0_CH11_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls0_TOM0_CH11_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls0_TOM0_CH11_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH11_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH11_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls0_TOM0_CH11_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM0_CH11_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH11_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH11_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH11_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH11_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH11_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH11_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH11_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH11_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH11_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH11_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH11_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH11_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH11_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH11_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH11_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH11_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH11_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH11_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH11_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls0_TOM0_CH11_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH11_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH11_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH11_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH11_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH11_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM0_CH11_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH11_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH11_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH11_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH11_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH11_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH11_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH11_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH11_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH11_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH11_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH11_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH11_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH11_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH11_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_TOM0_CH11_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH11_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH11_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH11_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH11_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM0_CH11_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH11_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH11_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH11_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls0_TOM0_CH11_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH11_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH11_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH11_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM0_CH12_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH12_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH12_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH12_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH12_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH12_CTRL_SL_SHIFT)) & GTM_gtm_cls0_TOM0_CH12_CTRL_SL_MASK) #define GTM_gtm_cls0_TOM0_CH12_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH12_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls0_TOM0_CH12_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls0_TOM0_CH12_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH12_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls0_TOM0_CH12_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls0_TOM0_CH12_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH12_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH12_CTRL_UDMODE_MASK) #define GTM_gtm_cls0_TOM0_CH12_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH12_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls0_TOM0_CH12_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls0_TOM0_CH12_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH12_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH12_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH12_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH12_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH12_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH12_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH12_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH12_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH12_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH12_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH12_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH12_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH12_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_TOM0_CH12_CTRL_OSM_MASK) #define GTM_gtm_cls0_TOM0_CH12_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH12_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls0_TOM0_CH12_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM0_CH12_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH12_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH12_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH12_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH12_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH12_SR0_SR0_SHIFT)) & GTM_gtm_cls0_TOM0_CH12_SR0_SR0_MASK) /*! @} */ /*! @name TOM0_CH12_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH12_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH12_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH12_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH12_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH12_SR1_SR1_SHIFT)) & GTM_gtm_cls0_TOM0_CH12_SR1_SR1_MASK) /*! @} */ /*! @name TOM0_CH12_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH12_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH12_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH12_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH12_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH12_CM0_CM0_SHIFT)) & GTM_gtm_cls0_TOM0_CH12_CM0_CM0_MASK) /*! @} */ /*! @name TOM0_CH12_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH12_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH12_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH12_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH12_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH12_CM1_CM1_SHIFT)) & GTM_gtm_cls0_TOM0_CH12_CM1_CM1_MASK) /*! @} */ /*! @name TOM0_CH12_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH12_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH12_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH12_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH12_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH12_CN0_CN0_SHIFT)) & GTM_gtm_cls0_TOM0_CH12_CN0_CN0_MASK) /*! @} */ /*! @name TOM0_CH12_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH12_STAT_OL_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH12_STAT_OL_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH12_STAT_OL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH12_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH12_STAT_OL_SHIFT)) & GTM_gtm_cls0_TOM0_CH12_STAT_OL_MASK) #define GTM_gtm_cls0_TOM0_CH12_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls0_TOM0_CH12_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls0_TOM0_CH12_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH12_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH12_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls0_TOM0_CH12_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM0_CH12_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH12_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH12_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH12_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH12_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH12_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH12_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH12_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH12_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH12_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH12_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH12_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH12_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH12_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH12_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH12_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH12_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH12_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH12_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH12_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls0_TOM0_CH12_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH12_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH12_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH12_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH12_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH12_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM0_CH12_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH12_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH12_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH12_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH12_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH12_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH12_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH12_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH12_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH12_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH12_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH12_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH12_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH12_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH12_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_TOM0_CH12_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH12_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH12_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH12_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH12_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM0_CH12_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH12_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH12_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH12_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls0_TOM0_CH12_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH12_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH12_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH12_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM0_CH13_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH13_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH13_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH13_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH13_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH13_CTRL_SL_SHIFT)) & GTM_gtm_cls0_TOM0_CH13_CTRL_SL_MASK) #define GTM_gtm_cls0_TOM0_CH13_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH13_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls0_TOM0_CH13_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls0_TOM0_CH13_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH13_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls0_TOM0_CH13_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls0_TOM0_CH13_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH13_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH13_CTRL_UDMODE_MASK) #define GTM_gtm_cls0_TOM0_CH13_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH13_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls0_TOM0_CH13_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls0_TOM0_CH13_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH13_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH13_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH13_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH13_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH13_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH13_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH13_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH13_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH13_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH13_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH13_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH13_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH13_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_TOM0_CH13_CTRL_OSM_MASK) #define GTM_gtm_cls0_TOM0_CH13_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH13_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls0_TOM0_CH13_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM0_CH13_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH13_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH13_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH13_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH13_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH13_SR0_SR0_SHIFT)) & GTM_gtm_cls0_TOM0_CH13_SR0_SR0_MASK) /*! @} */ /*! @name TOM0_CH13_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH13_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH13_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH13_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH13_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH13_SR1_SR1_SHIFT)) & GTM_gtm_cls0_TOM0_CH13_SR1_SR1_MASK) /*! @} */ /*! @name TOM0_CH13_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH13_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH13_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH13_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH13_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH13_CM0_CM0_SHIFT)) & GTM_gtm_cls0_TOM0_CH13_CM0_CM0_MASK) /*! @} */ /*! @name TOM0_CH13_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH13_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH13_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH13_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH13_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH13_CM1_CM1_SHIFT)) & GTM_gtm_cls0_TOM0_CH13_CM1_CM1_MASK) /*! @} */ /*! @name TOM0_CH13_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH13_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH13_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH13_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH13_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH13_CN0_CN0_SHIFT)) & GTM_gtm_cls0_TOM0_CH13_CN0_CN0_MASK) /*! @} */ /*! @name TOM0_CH13_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH13_STAT_OL_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH13_STAT_OL_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH13_STAT_OL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH13_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH13_STAT_OL_SHIFT)) & GTM_gtm_cls0_TOM0_CH13_STAT_OL_MASK) #define GTM_gtm_cls0_TOM0_CH13_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls0_TOM0_CH13_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls0_TOM0_CH13_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH13_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH13_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls0_TOM0_CH13_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM0_CH13_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH13_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH13_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH13_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH13_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH13_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH13_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH13_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH13_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH13_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH13_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH13_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH13_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH13_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH13_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH13_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH13_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH13_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH13_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH13_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls0_TOM0_CH13_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH13_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH13_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH13_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH13_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH13_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM0_CH13_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH13_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH13_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH13_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH13_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH13_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH13_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH13_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH13_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH13_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH13_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH13_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH13_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH13_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH13_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_TOM0_CH13_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH13_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH13_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH13_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH13_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM0_CH13_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH13_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH13_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH13_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls0_TOM0_CH13_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH13_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH13_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH13_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM0_CH14_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH14_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH14_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH14_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH14_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH14_CTRL_SL_SHIFT)) & GTM_gtm_cls0_TOM0_CH14_CTRL_SL_MASK) #define GTM_gtm_cls0_TOM0_CH14_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH14_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls0_TOM0_CH14_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls0_TOM0_CH14_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH14_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls0_TOM0_CH14_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls0_TOM0_CH14_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH14_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH14_CTRL_UDMODE_MASK) #define GTM_gtm_cls0_TOM0_CH14_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH14_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls0_TOM0_CH14_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls0_TOM0_CH14_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH14_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH14_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH14_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH14_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH14_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH14_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH14_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH14_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH14_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH14_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH14_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH14_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH14_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_TOM0_CH14_CTRL_OSM_MASK) #define GTM_gtm_cls0_TOM0_CH14_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH14_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls0_TOM0_CH14_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM0_CH14_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH14_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH14_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH14_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH14_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH14_SR0_SR0_SHIFT)) & GTM_gtm_cls0_TOM0_CH14_SR0_SR0_MASK) /*! @} */ /*! @name TOM0_CH14_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH14_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH14_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH14_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH14_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH14_SR1_SR1_SHIFT)) & GTM_gtm_cls0_TOM0_CH14_SR1_SR1_MASK) /*! @} */ /*! @name TOM0_CH14_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH14_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH14_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH14_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH14_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH14_CM0_CM0_SHIFT)) & GTM_gtm_cls0_TOM0_CH14_CM0_CM0_MASK) /*! @} */ /*! @name TOM0_CH14_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH14_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH14_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH14_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH14_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH14_CM1_CM1_SHIFT)) & GTM_gtm_cls0_TOM0_CH14_CM1_CM1_MASK) /*! @} */ /*! @name TOM0_CH14_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH14_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH14_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH14_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH14_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH14_CN0_CN0_SHIFT)) & GTM_gtm_cls0_TOM0_CH14_CN0_CN0_MASK) /*! @} */ /*! @name TOM0_CH14_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH14_STAT_OL_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH14_STAT_OL_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH14_STAT_OL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH14_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH14_STAT_OL_SHIFT)) & GTM_gtm_cls0_TOM0_CH14_STAT_OL_MASK) #define GTM_gtm_cls0_TOM0_CH14_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls0_TOM0_CH14_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls0_TOM0_CH14_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH14_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH14_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls0_TOM0_CH14_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM0_CH14_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH14_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH14_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH14_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH14_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH14_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH14_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH14_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH14_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH14_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH14_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH14_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH14_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH14_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH14_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH14_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH14_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH14_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH14_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH14_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls0_TOM0_CH14_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH14_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH14_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH14_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH14_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH14_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM0_CH14_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH14_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH14_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH14_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH14_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH14_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH14_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH14_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH14_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH14_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH14_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH14_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH14_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH14_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH14_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_TOM0_CH14_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH14_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH14_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH14_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH14_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM0_CH14_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH14_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH14_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH14_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls0_TOM0_CH14_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH14_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH14_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH14_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM0_CH15_CTRL - TOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH15_CTRL_SR0_TRIG_MASK (0x80U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_SR0_TRIG_SHIFT (7U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_SR0_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_SR0_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH15_CTRL_SR0_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH15_CTRL_SR0_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH15_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH15_CTRL_SL_SHIFT)) & GTM_gtm_cls0_TOM0_CH15_CTRL_SL_MASK) #define GTM_gtm_cls0_TOM0_CH15_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH15_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls0_TOM0_CH15_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls0_TOM0_CH15_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH15_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls0_TOM0_CH15_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls0_TOM0_CH15_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH15_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH15_CTRL_UDMODE_MASK) #define GTM_gtm_cls0_TOM0_CH15_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH15_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls0_TOM0_CH15_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls0_TOM0_CH15_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH15_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH15_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH15_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH15_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_CH15_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls0_TOM0_CH15_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH15_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH15_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH15_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH15_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls0_TOM0_CH15_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls0_TOM0_CH15_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH15_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_TOM0_CH15_CTRL_OSM_MASK) #define GTM_gtm_cls0_TOM0_CH15_CTRL_BITREV_MASK (0x8000000U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_BITREV_SHIFT (27U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_BITREV_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_BITREV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH15_CTRL_BITREV_SHIFT)) & GTM_gtm_cls0_TOM0_CH15_CTRL_BITREV_MASK) #define GTM_gtm_cls0_TOM0_CH15_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH15_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls0_TOM0_CH15_CTRL_FREEZE_MASK) /*! @} */ /*! @name TOM0_CH15_SR0 - TOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH15_SR0_SR0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH15_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH15_SR0_SR0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH15_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH15_SR0_SR0_SHIFT)) & GTM_gtm_cls0_TOM0_CH15_SR0_SR0_MASK) /*! @} */ /*! @name TOM0_CH15_SR1 - TOM[i] channel [x] CCU1 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH15_SR1_SR1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH15_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH15_SR1_SR1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH15_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH15_SR1_SR1_SHIFT)) & GTM_gtm_cls0_TOM0_CH15_SR1_SR1_MASK) /*! @} */ /*! @name TOM0_CH15_CM0 - TOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH15_CM0_CM0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH15_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH15_CM0_CM0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH15_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH15_CM0_CM0_SHIFT)) & GTM_gtm_cls0_TOM0_CH15_CM0_CM0_MASK) /*! @} */ /*! @name TOM0_CH15_CM1 - TOM[i] channel [x] CCU1 compare register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH15_CM1_CM1_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH15_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH15_CM1_CM1_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH15_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH15_CM1_CM1_SHIFT)) & GTM_gtm_cls0_TOM0_CH15_CM1_CM1_MASK) /*! @} */ /*! @name TOM0_CH15_CN0 - TOM[i] channel [x] CCU0 counter */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH15_CN0_CN0_MASK (0xFFFFU) #define GTM_gtm_cls0_TOM0_CH15_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH15_CN0_CN0_WIDTH (16U) #define GTM_gtm_cls0_TOM0_CH15_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH15_CN0_CN0_SHIFT)) & GTM_gtm_cls0_TOM0_CH15_CN0_CN0_MASK) /*! @} */ /*! @name TOM0_CH15_STAT - TOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH15_STAT_OL_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH15_STAT_OL_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH15_STAT_OL_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH15_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH15_STAT_OL_SHIFT)) & GTM_gtm_cls0_TOM0_CH15_STAT_OL_MASK) #define GTM_gtm_cls0_TOM0_CH15_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls0_TOM0_CH15_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls0_TOM0_CH15_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH15_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH15_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls0_TOM0_CH15_STAT_OSM_RTF_MASK) /*! @} */ /*! @name TOM0_CH15_IRQ_NOTIFY - TOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH15_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH15_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH15_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH15_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH15_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH15_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH15_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH15_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH15_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH15_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH15_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH15_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH15_IRQ_EN - TOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH15_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH15_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH15_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH15_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH15_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH15_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls0_TOM0_CH15_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH15_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH15_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH15_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH15_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_TOM0_CH15_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name TOM0_CH15_IRQ_FORCINT - TOM[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH15_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_TOM0_CH15_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH15_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH15_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH15_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH15_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls0_TOM0_CH15_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_TOM0_CH15_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_TOM0_CH15_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH15_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH15_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls0_TOM0_CH15_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name TOM0_CH15_IRQ_MODE - TOM[i] channel [x] interrupt mode register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH15_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_TOM0_CH15_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_TOM0_CH15_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_TOM0_CH15_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH15_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_TOM0_CH15_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name TOM0_CH15_CTRL_SR - TOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_CH15_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH15_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH15_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls0_TOM0_CH15_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls0_TOM0_CH15_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_CH15_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls0_TOM0_CH15_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name TOM0_TGC0_GLB_CTRL - TOM[i] TGC [g] global control register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_HOST_TRIG_MASK (0x1U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_HOST_TRIG_SHIFT (0U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_HOST_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_HOST_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_HOST_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_HOST_TRIG_MASK) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH0_MASK (0x100U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH0_SHIFT (8U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH0_WIDTH (1U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH0_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH0_MASK) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH1_MASK (0x200U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH1_SHIFT (9U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH1_WIDTH (1U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH1_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH1_MASK) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH2_MASK (0x400U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH2_SHIFT (10U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH2_WIDTH (1U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH2_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH2_MASK) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH3_MASK (0x800U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH3_SHIFT (11U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH3_WIDTH (1U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH3_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH3_MASK) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH4_MASK (0x1000U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH4_SHIFT (12U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH4_WIDTH (1U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH4_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH4_MASK) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH5_MASK (0x2000U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH5_SHIFT (13U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH5_WIDTH (1U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH5_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH5_MASK) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH6_MASK (0x4000U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH6_SHIFT (14U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH6_WIDTH (1U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH6_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH6_MASK) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH7_MASK (0x8000U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH7_SHIFT (15U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH7_WIDTH (1U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH7_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_RST_CH7_MASK) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL0_MASK (0x30000U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL0_SHIFT (16U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL0_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL0_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL0_MASK) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL1_MASK (0xC0000U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL1_SHIFT (18U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL1_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL1_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL1_MASK) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL2_MASK (0x300000U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL2_SHIFT (20U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL2_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL2_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL2_MASK) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL3_MASK (0xC00000U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL3_SHIFT (22U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL3_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL3_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL3_MASK) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL4_MASK (0x3000000U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL4_SHIFT (24U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL4_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL4_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL4_MASK) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL5_MASK (0xC000000U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL5_SHIFT (26U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL5_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL5_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL5_MASK) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL6_MASK (0x30000000U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL6_SHIFT (28U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL6_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL6_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL6_MASK) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL7_MASK (0xC0000000U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL7_SHIFT (30U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL7_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL7_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_GLB_CTRL_UPEN_CTRL7_MASK) /*! @} */ /*! @name TOM0_TGC0_ACT_TB - TOM[i] TGC [g] action time base register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_TGC0_ACT_TB_ACT_TB_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TOM0_TGC0_ACT_TB_ACT_TB_SHIFT (0U) #define GTM_gtm_cls0_TOM0_TGC0_ACT_TB_ACT_TB_WIDTH (24U) #define GTM_gtm_cls0_TOM0_TGC0_ACT_TB_ACT_TB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_ACT_TB_ACT_TB_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_ACT_TB_ACT_TB_MASK) #define GTM_gtm_cls0_TOM0_TGC0_ACT_TB_TB_TRIG_MASK (0x1000000U) #define GTM_gtm_cls0_TOM0_TGC0_ACT_TB_TB_TRIG_SHIFT (24U) #define GTM_gtm_cls0_TOM0_TGC0_ACT_TB_TB_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_TGC0_ACT_TB_TB_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_ACT_TB_TB_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_ACT_TB_TB_TRIG_MASK) #define GTM_gtm_cls0_TOM0_TGC0_ACT_TB_TBU_SEL_MASK (0x6000000U) #define GTM_gtm_cls0_TOM0_TGC0_ACT_TB_TBU_SEL_SHIFT (25U) #define GTM_gtm_cls0_TOM0_TGC0_ACT_TB_TBU_SEL_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_ACT_TB_TBU_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_ACT_TB_TBU_SEL_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_ACT_TB_TBU_SEL_MASK) /*! @} */ /*! @name TOM0_TGC0_FUPD_CTRL - TOM[i] TGC [g] force update control register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL0_MASK (0x3U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL0_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL0_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL0_MASK) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL1_MASK (0xCU) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL1_SHIFT (2U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL1_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL1_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL1_MASK) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL2_MASK (0x30U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL2_SHIFT (4U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL2_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL2_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL2_MASK) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL3_MASK (0xC0U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL3_SHIFT (6U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL3_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL3_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL3_MASK) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL4_MASK (0x300U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL4_SHIFT (8U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL4_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL4_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL4_MASK) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL5_MASK (0xC00U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL5_SHIFT (10U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL5_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL5_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL5_MASK) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL6_MASK (0x3000U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL6_SHIFT (12U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL6_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL6_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL6_MASK) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL7_MASK (0xC000U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL7_SHIFT (14U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL7_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL7_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_FUPD_CTRL7_MASK) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH0_MASK (0x30000U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH0_SHIFT (16U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH0_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH0_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH0_MASK) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH1_MASK (0xC0000U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH1_SHIFT (18U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH1_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH1_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH1_MASK) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH2_MASK (0x300000U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH2_SHIFT (20U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH2_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH2_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH2_MASK) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH3_MASK (0xC00000U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH3_SHIFT (22U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH3_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH3_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH3_MASK) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH4_MASK (0x3000000U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH4_SHIFT (24U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH4_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH4_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH4_MASK) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH5_MASK (0xC000000U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH5_SHIFT (26U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH5_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH5_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH5_MASK) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH6_MASK (0x30000000U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH6_SHIFT (28U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH6_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH6_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH6_MASK) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH7_MASK (0xC0000000U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH7_SHIFT (30U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH7_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH7_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_FUPD_CTRL_RSTCN0_CH7_MASK) /*! @} */ /*! @name TOM0_TGC0_INT_TRIG - TOM[i] TGC [g] internal trigger control register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG0_MASK (0x3U) #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG0_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG0_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG0_MASK) #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG1_MASK (0xCU) #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG1_SHIFT (2U) #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG1_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG1_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG1_MASK) #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG2_MASK (0x30U) #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG2_SHIFT (4U) #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG2_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG2_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG2_MASK) #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG3_MASK (0xC0U) #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG3_SHIFT (6U) #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG3_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG3_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG3_MASK) #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG4_MASK (0x300U) #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG4_SHIFT (8U) #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG4_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG4_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG4_MASK) #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG5_MASK (0xC00U) #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG5_SHIFT (10U) #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG5_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG5_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG5_MASK) #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG6_MASK (0x3000U) #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG6_SHIFT (12U) #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG6_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG6_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG6_MASK) #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG7_MASK (0xC000U) #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG7_SHIFT (14U) #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG7_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG7_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_INT_TRIG_INT_TRIG7_MASK) /*! @} */ /*! @name TOM0_TGC0_ENDIS_CTRL - TOM[i] TGC [g] enable/disable control register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL0_MASK (0x3U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL0_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL0_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL0_MASK) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL1_MASK (0xCU) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL1_SHIFT (2U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL1_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL1_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL1_MASK) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL2_MASK (0x30U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL2_SHIFT (4U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL2_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL2_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL2_MASK) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL3_MASK (0xC0U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL3_SHIFT (6U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL3_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL3_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL3_MASK) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL4_MASK (0x300U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL4_SHIFT (8U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL4_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL4_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL4_MASK) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL5_MASK (0xC00U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL5_SHIFT (10U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL5_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL5_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL5_MASK) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL6_MASK (0x3000U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL6_SHIFT (12U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL6_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL6_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL6_MASK) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL7_MASK (0xC000U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL7_SHIFT (14U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL7_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL7_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_ENDIS_CTRL_ENDIS_CTRL7_MASK) /*! @} */ /*! @name TOM0_TGC0_ENDIS_STAT - TOM[i] TGC [g] enable/disable status register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT0_MASK (0x3U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT0_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT0_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT0_MASK) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT1_MASK (0xCU) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT1_SHIFT (2U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT1_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT1_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT1_MASK) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT2_MASK (0x30U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT2_SHIFT (4U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT2_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT2_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT2_MASK) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT3_MASK (0xC0U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT3_SHIFT (6U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT3_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT3_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT3_MASK) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT4_MASK (0x300U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT4_SHIFT (8U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT4_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT4_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT4_MASK) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT5_MASK (0xC00U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT5_SHIFT (10U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT5_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT5_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT5_MASK) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT6_MASK (0x3000U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT6_SHIFT (12U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT6_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT6_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT6_MASK) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT7_MASK (0xC000U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT7_SHIFT (14U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT7_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT7_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_ENDIS_STAT_ENDIS_STAT7_MASK) /*! @} */ /*! @name TOM0_TGC0_OUTEN_CTRL - TOM[i] TGC [g] output enable control register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL0_MASK (0x3U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL0_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL0_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL0_MASK) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL1_MASK (0xCU) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL1_SHIFT (2U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL1_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL1_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL1_MASK) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL2_MASK (0x30U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL2_SHIFT (4U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL2_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL2_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL2_MASK) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL3_MASK (0xC0U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL3_SHIFT (6U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL3_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL3_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL3_MASK) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL4_MASK (0x300U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL4_SHIFT (8U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL4_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL4_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL4_MASK) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL5_MASK (0xC00U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL5_SHIFT (10U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL5_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL5_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL5_MASK) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL6_MASK (0x3000U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL6_SHIFT (12U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL6_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL6_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL6_MASK) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL7_MASK (0xC000U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL7_SHIFT (14U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL7_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL7_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_OUTEN_CTRL_OUTEN_CTRL7_MASK) /*! @} */ /*! @name TOM0_TGC0_OUTEN_STAT - TOM[i] TGC [g] output enable status register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT0_MASK (0x3U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT0_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT0_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT0_MASK) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT1_MASK (0xCU) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT1_SHIFT (2U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT1_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT1_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT1_MASK) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT2_MASK (0x30U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT2_SHIFT (4U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT2_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT2_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT2_MASK) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT3_MASK (0xC0U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT3_SHIFT (6U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT3_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT3_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT3_MASK) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT4_MASK (0x300U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT4_SHIFT (8U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT4_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT4_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT4_MASK) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT5_MASK (0xC00U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT5_SHIFT (10U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT5_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT5_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT5_MASK) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT6_MASK (0x3000U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT6_SHIFT (12U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT6_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT6_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT6_MASK) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT7_MASK (0xC000U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT7_SHIFT (14U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT7_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT7_SHIFT)) & GTM_gtm_cls0_TOM0_TGC0_OUTEN_STAT_OUTEN_STAT7_MASK) /*! @} */ /*! @name TOM0_TGC1_GLB_CTRL - TOM[i] TGC [g] global control register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_HOST_TRIG_MASK (0x1U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_HOST_TRIG_SHIFT (0U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_HOST_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_HOST_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_HOST_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_HOST_TRIG_MASK) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH0_MASK (0x100U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH0_SHIFT (8U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH0_WIDTH (1U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH0_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH0_MASK) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH1_MASK (0x200U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH1_SHIFT (9U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH1_WIDTH (1U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH1_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH1_MASK) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH2_MASK (0x400U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH2_SHIFT (10U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH2_WIDTH (1U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH2_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH2_MASK) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH3_MASK (0x800U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH3_SHIFT (11U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH3_WIDTH (1U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH3_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH3_MASK) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH4_MASK (0x1000U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH4_SHIFT (12U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH4_WIDTH (1U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH4_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH4_MASK) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH5_MASK (0x2000U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH5_SHIFT (13U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH5_WIDTH (1U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH5_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH5_MASK) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH6_MASK (0x4000U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH6_SHIFT (14U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH6_WIDTH (1U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH6_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH6_MASK) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH7_MASK (0x8000U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH7_SHIFT (15U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH7_WIDTH (1U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH7_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_RST_CH7_MASK) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL0_MASK (0x30000U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL0_SHIFT (16U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL0_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL0_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL0_MASK) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL1_MASK (0xC0000U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL1_SHIFT (18U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL1_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL1_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL1_MASK) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL2_MASK (0x300000U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL2_SHIFT (20U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL2_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL2_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL2_MASK) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL3_MASK (0xC00000U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL3_SHIFT (22U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL3_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL3_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL3_MASK) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL4_MASK (0x3000000U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL4_SHIFT (24U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL4_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL4_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL4_MASK) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL5_MASK (0xC000000U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL5_SHIFT (26U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL5_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL5_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL5_MASK) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL6_MASK (0x30000000U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL6_SHIFT (28U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL6_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL6_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL6_MASK) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL7_MASK (0xC0000000U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL7_SHIFT (30U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL7_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL7_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_GLB_CTRL_UPEN_CTRL7_MASK) /*! @} */ /*! @name TOM0_TGC1_ACT_TB - TOM[i] TGC [g] action time base register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_TGC1_ACT_TB_ACT_TB_MASK (0xFFFFFFU) #define GTM_gtm_cls0_TOM0_TGC1_ACT_TB_ACT_TB_SHIFT (0U) #define GTM_gtm_cls0_TOM0_TGC1_ACT_TB_ACT_TB_WIDTH (24U) #define GTM_gtm_cls0_TOM0_TGC1_ACT_TB_ACT_TB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_ACT_TB_ACT_TB_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_ACT_TB_ACT_TB_MASK) #define GTM_gtm_cls0_TOM0_TGC1_ACT_TB_TB_TRIG_MASK (0x1000000U) #define GTM_gtm_cls0_TOM0_TGC1_ACT_TB_TB_TRIG_SHIFT (24U) #define GTM_gtm_cls0_TOM0_TGC1_ACT_TB_TB_TRIG_WIDTH (1U) #define GTM_gtm_cls0_TOM0_TGC1_ACT_TB_TB_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_ACT_TB_TB_TRIG_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_ACT_TB_TB_TRIG_MASK) #define GTM_gtm_cls0_TOM0_TGC1_ACT_TB_TBU_SEL_MASK (0x6000000U) #define GTM_gtm_cls0_TOM0_TGC1_ACT_TB_TBU_SEL_SHIFT (25U) #define GTM_gtm_cls0_TOM0_TGC1_ACT_TB_TBU_SEL_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_ACT_TB_TBU_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_ACT_TB_TBU_SEL_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_ACT_TB_TBU_SEL_MASK) /*! @} */ /*! @name TOM0_TGC1_FUPD_CTRL - TOM[i] TGC [g] force update control register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL0_MASK (0x3U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL0_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL0_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL0_MASK) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL1_MASK (0xCU) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL1_SHIFT (2U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL1_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL1_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL1_MASK) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL2_MASK (0x30U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL2_SHIFT (4U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL2_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL2_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL2_MASK) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL3_MASK (0xC0U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL3_SHIFT (6U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL3_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL3_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL3_MASK) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL4_MASK (0x300U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL4_SHIFT (8U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL4_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL4_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL4_MASK) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL5_MASK (0xC00U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL5_SHIFT (10U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL5_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL5_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL5_MASK) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL6_MASK (0x3000U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL6_SHIFT (12U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL6_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL6_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL6_MASK) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL7_MASK (0xC000U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL7_SHIFT (14U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL7_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL7_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_FUPD_CTRL7_MASK) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH0_MASK (0x30000U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH0_SHIFT (16U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH0_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH0_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH0_MASK) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH1_MASK (0xC0000U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH1_SHIFT (18U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH1_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH1_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH1_MASK) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH2_MASK (0x300000U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH2_SHIFT (20U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH2_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH2_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH2_MASK) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH3_MASK (0xC00000U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH3_SHIFT (22U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH3_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH3_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH3_MASK) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH4_MASK (0x3000000U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH4_SHIFT (24U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH4_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH4_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH4_MASK) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH5_MASK (0xC000000U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH5_SHIFT (26U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH5_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH5_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH5_MASK) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH6_MASK (0x30000000U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH6_SHIFT (28U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH6_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH6_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH6_MASK) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH7_MASK (0xC0000000U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH7_SHIFT (30U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH7_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH7_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_FUPD_CTRL_RSTCN0_CH7_MASK) /*! @} */ /*! @name TOM0_TGC1_INT_TRIG - TOM[i] TGC [g] internal trigger control register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG0_MASK (0x3U) #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG0_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG0_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG0_MASK) #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG1_MASK (0xCU) #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG1_SHIFT (2U) #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG1_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG1_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG1_MASK) #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG2_MASK (0x30U) #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG2_SHIFT (4U) #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG2_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG2_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG2_MASK) #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG3_MASK (0xC0U) #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG3_SHIFT (6U) #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG3_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG3_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG3_MASK) #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG4_MASK (0x300U) #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG4_SHIFT (8U) #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG4_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG4_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG4_MASK) #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG5_MASK (0xC00U) #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG5_SHIFT (10U) #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG5_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG5_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG5_MASK) #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG6_MASK (0x3000U) #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG6_SHIFT (12U) #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG6_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG6_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG6_MASK) #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG7_MASK (0xC000U) #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG7_SHIFT (14U) #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG7_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG7_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_INT_TRIG_INT_TRIG7_MASK) /*! @} */ /*! @name TOM0_TGC1_ENDIS_CTRL - TOM[i] TGC [g] enable/disable control register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL0_MASK (0x3U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL0_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL0_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL0_MASK) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL1_MASK (0xCU) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL1_SHIFT (2U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL1_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL1_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL1_MASK) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL2_MASK (0x30U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL2_SHIFT (4U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL2_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL2_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL2_MASK) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL3_MASK (0xC0U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL3_SHIFT (6U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL3_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL3_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL3_MASK) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL4_MASK (0x300U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL4_SHIFT (8U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL4_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL4_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL4_MASK) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL5_MASK (0xC00U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL5_SHIFT (10U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL5_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL5_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL5_MASK) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL6_MASK (0x3000U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL6_SHIFT (12U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL6_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL6_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL6_MASK) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL7_MASK (0xC000U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL7_SHIFT (14U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL7_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL7_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_ENDIS_CTRL_ENDIS_CTRL7_MASK) /*! @} */ /*! @name TOM0_TGC1_ENDIS_STAT - TOM[i] TGC [g] enable/disable status register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT0_MASK (0x3U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT0_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT0_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT0_MASK) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT1_MASK (0xCU) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT1_SHIFT (2U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT1_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT1_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT1_MASK) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT2_MASK (0x30U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT2_SHIFT (4U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT2_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT2_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT2_MASK) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT3_MASK (0xC0U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT3_SHIFT (6U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT3_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT3_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT3_MASK) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT4_MASK (0x300U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT4_SHIFT (8U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT4_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT4_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT4_MASK) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT5_MASK (0xC00U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT5_SHIFT (10U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT5_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT5_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT5_MASK) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT6_MASK (0x3000U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT6_SHIFT (12U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT6_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT6_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT6_MASK) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT7_MASK (0xC000U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT7_SHIFT (14U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT7_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT7_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_ENDIS_STAT_ENDIS_STAT7_MASK) /*! @} */ /*! @name TOM0_TGC1_OUTEN_CTRL - TOM[i] TGC [g] output enable control register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL0_MASK (0x3U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL0_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL0_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL0_MASK) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL1_MASK (0xCU) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL1_SHIFT (2U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL1_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL1_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL1_MASK) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL2_MASK (0x30U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL2_SHIFT (4U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL2_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL2_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL2_MASK) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL3_MASK (0xC0U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL3_SHIFT (6U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL3_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL3_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL3_MASK) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL4_MASK (0x300U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL4_SHIFT (8U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL4_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL4_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL4_MASK) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL5_MASK (0xC00U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL5_SHIFT (10U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL5_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL5_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL5_MASK) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL6_MASK (0x3000U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL6_SHIFT (12U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL6_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL6_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL6_MASK) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL7_MASK (0xC000U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL7_SHIFT (14U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL7_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL7_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_OUTEN_CTRL_OUTEN_CTRL7_MASK) /*! @} */ /*! @name TOM0_TGC1_OUTEN_STAT - TOM[i] TGC [g] output enable status register */ /*! @{ */ #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT0_MASK (0x3U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT0_SHIFT (0U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT0_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT0_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT0_MASK) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT1_MASK (0xCU) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT1_SHIFT (2U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT1_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT1_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT1_MASK) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT2_MASK (0x30U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT2_SHIFT (4U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT2_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT2_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT2_MASK) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT3_MASK (0xC0U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT3_SHIFT (6U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT3_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT3_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT3_MASK) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT4_MASK (0x300U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT4_SHIFT (8U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT4_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT4_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT4_MASK) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT5_MASK (0xC00U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT5_SHIFT (10U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT5_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT5_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT5_MASK) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT6_MASK (0x3000U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT6_SHIFT (12U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT6_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT6_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT6_MASK) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT7_MASK (0xC000U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT7_SHIFT (14U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT7_WIDTH (2U) #define GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT7_SHIFT)) & GTM_gtm_cls0_TOM0_TGC1_OUTEN_STAT_OUTEN_STAT7_MASK) /*! @} */ /*! @name ATOM0_CH0_RDADDR - ATOM[i] channel[x] ARU read address register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH0_RDADDR_RDADDR0_MASK (0x1FFU) #define GTM_gtm_cls0_ATOM0_CH0_RDADDR_RDADDR0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH0_RDADDR_RDADDR0_WIDTH (9U) #define GTM_gtm_cls0_ATOM0_CH0_RDADDR_RDADDR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_RDADDR_RDADDR0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_RDADDR_RDADDR0_MASK) #define GTM_gtm_cls0_ATOM0_CH0_RDADDR_RDADDR1_MASK (0x1FF0000U) #define GTM_gtm_cls0_ATOM0_CH0_RDADDR_RDADDR1_SHIFT (16U) #define GTM_gtm_cls0_ATOM0_CH0_RDADDR_RDADDR1_WIDTH (9U) #define GTM_gtm_cls0_ATOM0_CH0_RDADDR_RDADDR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_RDADDR_RDADDR1_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_RDADDR_RDADDR1_MASK) /*! @} */ /*! @name ATOM0_CH0_CTRL - ATOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH0_CTRL_MODE_MASK (0x3U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_MODE_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_MODE_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_CTRL_MODE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_CTRL_MODE_MASK) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_TB12_SEL_MASK (0x4U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_TB12_SEL_SHIFT (2U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_TB12_SEL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_TB12_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_CTRL_TB12_SEL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_CTRL_TB12_SEL_MASK) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_ARU_EN_MASK (0x8U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_ARU_EN_SHIFT (3U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_CTRL_ARU_EN_MASK) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_ACB_MASK (0x1F0U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_ACB_SHIFT (4U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_ACB_WIDTH (5U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_ACB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_CTRL_ACB_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_CTRL_ACB_MASK) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_CMP_CTRL_MASK (0x200U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_CMP_CTRL_SHIFT (9U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_CMP_CTRL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_CMP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_CTRL_CMP_CTRL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_CTRL_CMP_CTRL_MASK) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_EUPM_MASK (0x400U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_EUPM_SHIFT (10U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_EUPM_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_EUPM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_CTRL_EUPM_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_CTRL_EUPM_MASK) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_CTRL_SL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_CTRL_SL_MASK) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_WR_REQ_MASK (0x10000U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_WR_REQ_SHIFT (16U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_WR_REQ_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_WR_REQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_CTRL_WR_REQ_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_CTRL_WR_REQ_MASK) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_CTRL_UDMODE_MASK) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_SLA_MASK (0x2000000U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_SLA_SHIFT (25U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_SLA_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_SLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_CTRL_SLA_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_CTRL_SLA_MASK) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_CTRL_OSM_MASK) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_ABM_MASK (0x8000000U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_ABM_SHIFT (27U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_ABM_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_ABM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_CTRL_ABM_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_CTRL_ABM_MASK) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_EXT_FUPD_MASK (0x20000000U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_EXT_FUPD_SHIFT (29U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_EXT_FUPD_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_EXT_FUPD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_CTRL_EXT_FUPD_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_CTRL_EXT_FUPD_MASK) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_SOMB_MASK (0x40000000U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_SOMB_SHIFT (30U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_SOMB_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_SOMB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_CTRL_SOMB_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_CTRL_SOMB_MASK) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_CTRL_FREEZE_MASK) /*! @} */ /*! @name ATOM0_CH0_SR0 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH0_SR0_SR0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH0_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH0_SR0_SR0_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH0_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_SR0_SR0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_SR0_SR0_MASK) /*! @} */ /*! @name ATOM0_CH0_SR1 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH0_SR1_SR1_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH0_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH0_SR1_SR1_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH0_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_SR1_SR1_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_SR1_SR1_MASK) /*! @} */ /*! @name ATOM0_CH0_CM0 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH0_CM0_CM0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH0_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH0_CM0_CM0_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH0_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_CM0_CM0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_CM0_CM0_MASK) /*! @} */ /*! @name ATOM0_CH0_CM1 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH0_CM1_CM1_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH0_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH0_CM1_CM1_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH0_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_CM1_CM1_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_CM1_CM1_MASK) /*! @} */ /*! @name ATOM0_CH0_CN0 - ATOM[i] channel [x] CCU0 counter register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH0_CN0_CN0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH0_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH0_CN0_CN0_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH0_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_CN0_CN0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_CN0_CN0_MASK) /*! @} */ /*! @name ATOM0_CH0_STAT - ATOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH0_STAT_OL_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH0_STAT_OL_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH0_STAT_OL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH0_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_STAT_OL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_STAT_OL_MASK) #define GTM_gtm_cls0_ATOM0_CH0_STAT_ACBI_MASK (0x1F0000U) #define GTM_gtm_cls0_ATOM0_CH0_STAT_ACBI_SHIFT (16U) #define GTM_gtm_cls0_ATOM0_CH0_STAT_ACBI_WIDTH (5U) #define GTM_gtm_cls0_ATOM0_CH0_STAT_ACBI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_STAT_ACBI_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_STAT_ACBI_MASK) #define GTM_gtm_cls0_ATOM0_CH0_STAT_DV_MASK (0x200000U) #define GTM_gtm_cls0_ATOM0_CH0_STAT_DV_SHIFT (21U) #define GTM_gtm_cls0_ATOM0_CH0_STAT_DV_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH0_STAT_DV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_STAT_DV_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_STAT_DV_MASK) #define GTM_gtm_cls0_ATOM0_CH0_STAT_WRF_MASK (0x400000U) #define GTM_gtm_cls0_ATOM0_CH0_STAT_WRF_SHIFT (22U) #define GTM_gtm_cls0_ATOM0_CH0_STAT_WRF_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH0_STAT_WRF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_STAT_WRF_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_STAT_WRF_MASK) #define GTM_gtm_cls0_ATOM0_CH0_STAT_DR_MASK (0x800000U) #define GTM_gtm_cls0_ATOM0_CH0_STAT_DR_SHIFT (23U) #define GTM_gtm_cls0_ATOM0_CH0_STAT_DR_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH0_STAT_DR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_STAT_DR_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_STAT_DR_MASK) #define GTM_gtm_cls0_ATOM0_CH0_STAT_ACBO_MASK (0x1F000000U) #define GTM_gtm_cls0_ATOM0_CH0_STAT_ACBO_SHIFT (24U) #define GTM_gtm_cls0_ATOM0_CH0_STAT_ACBO_WIDTH (5U) #define GTM_gtm_cls0_ATOM0_CH0_STAT_ACBO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_STAT_ACBO_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_STAT_ACBO_MASK) #define GTM_gtm_cls0_ATOM0_CH0_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls0_ATOM0_CH0_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls0_ATOM0_CH0_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH0_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_STAT_OSM_RTF_MASK) /*! @} */ /*! @name ATOM0_CH0_IRQ_NOTIFY - ATOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH0_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH0_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH0_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH0_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls0_ATOM0_CH0_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_ATOM0_CH0_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_ATOM0_CH0_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH0_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name ATOM0_CH0_IRQ_EN - ATOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH0_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH0_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH0_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH0_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls0_ATOM0_CH0_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_ATOM0_CH0_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_ATOM0_CH0_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH0_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name ATOM0_CH0_IRQ_FORCINT - ATOM[i] channel [x] software interrupt generation */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH0_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH0_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH0_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH0_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls0_ATOM0_CH0_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_ATOM0_CH0_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_ATOM0_CH0_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH0_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name ATOM0_CH0_IRQ_MODE - ATOM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH0_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_ATOM0_CH0_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH0_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_CH0_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name ATOM0_CH0_CTRL_SR - ATOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH0_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls0_ATOM0_CH0_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH0_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls0_ATOM0_CH0_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name ATOM0_CH1_RDADDR - ATOM[i] channel[x] ARU read address register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH1_RDADDR_RDADDR0_MASK (0x1FFU) #define GTM_gtm_cls0_ATOM0_CH1_RDADDR_RDADDR0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH1_RDADDR_RDADDR0_WIDTH (9U) #define GTM_gtm_cls0_ATOM0_CH1_RDADDR_RDADDR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_RDADDR_RDADDR0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_RDADDR_RDADDR0_MASK) #define GTM_gtm_cls0_ATOM0_CH1_RDADDR_RDADDR1_MASK (0x1FF0000U) #define GTM_gtm_cls0_ATOM0_CH1_RDADDR_RDADDR1_SHIFT (16U) #define GTM_gtm_cls0_ATOM0_CH1_RDADDR_RDADDR1_WIDTH (9U) #define GTM_gtm_cls0_ATOM0_CH1_RDADDR_RDADDR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_RDADDR_RDADDR1_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_RDADDR_RDADDR1_MASK) /*! @} */ /*! @name ATOM0_CH1_CTRL - ATOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH1_CTRL_MODE_MASK (0x3U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_MODE_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_MODE_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_CTRL_MODE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_CTRL_MODE_MASK) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_TB12_SEL_MASK (0x4U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_TB12_SEL_SHIFT (2U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_TB12_SEL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_TB12_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_CTRL_TB12_SEL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_CTRL_TB12_SEL_MASK) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_ARU_EN_MASK (0x8U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_ARU_EN_SHIFT (3U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_CTRL_ARU_EN_MASK) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_ACB_MASK (0x1F0U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_ACB_SHIFT (4U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_ACB_WIDTH (5U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_ACB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_CTRL_ACB_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_CTRL_ACB_MASK) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_CMP_CTRL_MASK (0x200U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_CMP_CTRL_SHIFT (9U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_CMP_CTRL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_CMP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_CTRL_CMP_CTRL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_CTRL_CMP_CTRL_MASK) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_EUPM_MASK (0x400U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_EUPM_SHIFT (10U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_EUPM_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_EUPM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_CTRL_EUPM_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_CTRL_EUPM_MASK) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_CTRL_SL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_CTRL_SL_MASK) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_WR_REQ_MASK (0x10000U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_WR_REQ_SHIFT (16U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_WR_REQ_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_WR_REQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_CTRL_WR_REQ_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_CTRL_WR_REQ_MASK) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_CTRL_UDMODE_MASK) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_SLA_MASK (0x2000000U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_SLA_SHIFT (25U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_SLA_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_SLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_CTRL_SLA_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_CTRL_SLA_MASK) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_CTRL_OSM_MASK) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_ABM_MASK (0x8000000U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_ABM_SHIFT (27U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_ABM_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_ABM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_CTRL_ABM_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_CTRL_ABM_MASK) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_EXT_FUPD_MASK (0x20000000U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_EXT_FUPD_SHIFT (29U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_EXT_FUPD_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_EXT_FUPD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_CTRL_EXT_FUPD_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_CTRL_EXT_FUPD_MASK) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_SOMB_MASK (0x40000000U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_SOMB_SHIFT (30U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_SOMB_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_SOMB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_CTRL_SOMB_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_CTRL_SOMB_MASK) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_CTRL_FREEZE_MASK) /*! @} */ /*! @name ATOM0_CH1_SR0 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH1_SR0_SR0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH1_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH1_SR0_SR0_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH1_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_SR0_SR0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_SR0_SR0_MASK) /*! @} */ /*! @name ATOM0_CH1_SR1 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH1_SR1_SR1_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH1_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH1_SR1_SR1_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH1_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_SR1_SR1_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_SR1_SR1_MASK) /*! @} */ /*! @name ATOM0_CH1_CM0 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH1_CM0_CM0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH1_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH1_CM0_CM0_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH1_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_CM0_CM0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_CM0_CM0_MASK) /*! @} */ /*! @name ATOM0_CH1_CM1 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH1_CM1_CM1_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH1_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH1_CM1_CM1_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH1_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_CM1_CM1_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_CM1_CM1_MASK) /*! @} */ /*! @name ATOM0_CH1_CN0 - ATOM[i] channel [x] CCU0 counter register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH1_CN0_CN0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH1_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH1_CN0_CN0_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH1_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_CN0_CN0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_CN0_CN0_MASK) /*! @} */ /*! @name ATOM0_CH1_STAT - ATOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH1_STAT_OL_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH1_STAT_OL_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH1_STAT_OL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH1_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_STAT_OL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_STAT_OL_MASK) #define GTM_gtm_cls0_ATOM0_CH1_STAT_ACBI_MASK (0x1F0000U) #define GTM_gtm_cls0_ATOM0_CH1_STAT_ACBI_SHIFT (16U) #define GTM_gtm_cls0_ATOM0_CH1_STAT_ACBI_WIDTH (5U) #define GTM_gtm_cls0_ATOM0_CH1_STAT_ACBI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_STAT_ACBI_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_STAT_ACBI_MASK) #define GTM_gtm_cls0_ATOM0_CH1_STAT_DV_MASK (0x200000U) #define GTM_gtm_cls0_ATOM0_CH1_STAT_DV_SHIFT (21U) #define GTM_gtm_cls0_ATOM0_CH1_STAT_DV_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH1_STAT_DV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_STAT_DV_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_STAT_DV_MASK) #define GTM_gtm_cls0_ATOM0_CH1_STAT_WRF_MASK (0x400000U) #define GTM_gtm_cls0_ATOM0_CH1_STAT_WRF_SHIFT (22U) #define GTM_gtm_cls0_ATOM0_CH1_STAT_WRF_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH1_STAT_WRF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_STAT_WRF_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_STAT_WRF_MASK) #define GTM_gtm_cls0_ATOM0_CH1_STAT_DR_MASK (0x800000U) #define GTM_gtm_cls0_ATOM0_CH1_STAT_DR_SHIFT (23U) #define GTM_gtm_cls0_ATOM0_CH1_STAT_DR_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH1_STAT_DR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_STAT_DR_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_STAT_DR_MASK) #define GTM_gtm_cls0_ATOM0_CH1_STAT_ACBO_MASK (0x1F000000U) #define GTM_gtm_cls0_ATOM0_CH1_STAT_ACBO_SHIFT (24U) #define GTM_gtm_cls0_ATOM0_CH1_STAT_ACBO_WIDTH (5U) #define GTM_gtm_cls0_ATOM0_CH1_STAT_ACBO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_STAT_ACBO_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_STAT_ACBO_MASK) #define GTM_gtm_cls0_ATOM0_CH1_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls0_ATOM0_CH1_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls0_ATOM0_CH1_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH1_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_STAT_OSM_RTF_MASK) /*! @} */ /*! @name ATOM0_CH1_IRQ_NOTIFY - ATOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH1_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH1_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH1_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH1_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls0_ATOM0_CH1_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_ATOM0_CH1_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_ATOM0_CH1_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH1_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name ATOM0_CH1_IRQ_EN - ATOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH1_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH1_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH1_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH1_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls0_ATOM0_CH1_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_ATOM0_CH1_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_ATOM0_CH1_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH1_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name ATOM0_CH1_IRQ_FORCINT - ATOM[i] channel [x] software interrupt generation */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH1_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH1_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH1_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH1_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls0_ATOM0_CH1_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_ATOM0_CH1_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_ATOM0_CH1_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH1_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name ATOM0_CH1_IRQ_MODE - ATOM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH1_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_ATOM0_CH1_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH1_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_CH1_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name ATOM0_CH1_CTRL_SR - ATOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH1_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls0_ATOM0_CH1_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH1_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls0_ATOM0_CH1_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name ATOM0_CH2_RDADDR - ATOM[i] channel[x] ARU read address register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH2_RDADDR_RDADDR0_MASK (0x1FFU) #define GTM_gtm_cls0_ATOM0_CH2_RDADDR_RDADDR0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH2_RDADDR_RDADDR0_WIDTH (9U) #define GTM_gtm_cls0_ATOM0_CH2_RDADDR_RDADDR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_RDADDR_RDADDR0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_RDADDR_RDADDR0_MASK) #define GTM_gtm_cls0_ATOM0_CH2_RDADDR_RDADDR1_MASK (0x1FF0000U) #define GTM_gtm_cls0_ATOM0_CH2_RDADDR_RDADDR1_SHIFT (16U) #define GTM_gtm_cls0_ATOM0_CH2_RDADDR_RDADDR1_WIDTH (9U) #define GTM_gtm_cls0_ATOM0_CH2_RDADDR_RDADDR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_RDADDR_RDADDR1_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_RDADDR_RDADDR1_MASK) /*! @} */ /*! @name ATOM0_CH2_CTRL - ATOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH2_CTRL_MODE_MASK (0x3U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_MODE_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_MODE_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_CTRL_MODE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_CTRL_MODE_MASK) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_TB12_SEL_MASK (0x4U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_TB12_SEL_SHIFT (2U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_TB12_SEL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_TB12_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_CTRL_TB12_SEL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_CTRL_TB12_SEL_MASK) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_ARU_EN_MASK (0x8U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_ARU_EN_SHIFT (3U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_CTRL_ARU_EN_MASK) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_ACB_MASK (0x1F0U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_ACB_SHIFT (4U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_ACB_WIDTH (5U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_ACB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_CTRL_ACB_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_CTRL_ACB_MASK) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_CMP_CTRL_MASK (0x200U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_CMP_CTRL_SHIFT (9U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_CMP_CTRL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_CMP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_CTRL_CMP_CTRL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_CTRL_CMP_CTRL_MASK) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_EUPM_MASK (0x400U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_EUPM_SHIFT (10U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_EUPM_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_EUPM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_CTRL_EUPM_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_CTRL_EUPM_MASK) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_CTRL_SL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_CTRL_SL_MASK) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_WR_REQ_MASK (0x10000U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_WR_REQ_SHIFT (16U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_WR_REQ_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_WR_REQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_CTRL_WR_REQ_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_CTRL_WR_REQ_MASK) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_CTRL_UDMODE_MASK) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_SLA_MASK (0x2000000U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_SLA_SHIFT (25U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_SLA_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_SLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_CTRL_SLA_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_CTRL_SLA_MASK) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_CTRL_OSM_MASK) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_ABM_MASK (0x8000000U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_ABM_SHIFT (27U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_ABM_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_ABM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_CTRL_ABM_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_CTRL_ABM_MASK) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_EXT_FUPD_MASK (0x20000000U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_EXT_FUPD_SHIFT (29U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_EXT_FUPD_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_EXT_FUPD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_CTRL_EXT_FUPD_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_CTRL_EXT_FUPD_MASK) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_SOMB_MASK (0x40000000U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_SOMB_SHIFT (30U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_SOMB_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_SOMB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_CTRL_SOMB_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_CTRL_SOMB_MASK) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_CTRL_FREEZE_MASK) /*! @} */ /*! @name ATOM0_CH2_SR0 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH2_SR0_SR0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH2_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH2_SR0_SR0_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH2_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_SR0_SR0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_SR0_SR0_MASK) /*! @} */ /*! @name ATOM0_CH2_SR1 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH2_SR1_SR1_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH2_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH2_SR1_SR1_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH2_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_SR1_SR1_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_SR1_SR1_MASK) /*! @} */ /*! @name ATOM0_CH2_CM0 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH2_CM0_CM0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH2_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH2_CM0_CM0_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH2_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_CM0_CM0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_CM0_CM0_MASK) /*! @} */ /*! @name ATOM0_CH2_CM1 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH2_CM1_CM1_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH2_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH2_CM1_CM1_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH2_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_CM1_CM1_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_CM1_CM1_MASK) /*! @} */ /*! @name ATOM0_CH2_CN0 - ATOM[i] channel [x] CCU0 counter register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH2_CN0_CN0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH2_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH2_CN0_CN0_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH2_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_CN0_CN0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_CN0_CN0_MASK) /*! @} */ /*! @name ATOM0_CH2_STAT - ATOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH2_STAT_OL_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH2_STAT_OL_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH2_STAT_OL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH2_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_STAT_OL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_STAT_OL_MASK) #define GTM_gtm_cls0_ATOM0_CH2_STAT_ACBI_MASK (0x1F0000U) #define GTM_gtm_cls0_ATOM0_CH2_STAT_ACBI_SHIFT (16U) #define GTM_gtm_cls0_ATOM0_CH2_STAT_ACBI_WIDTH (5U) #define GTM_gtm_cls0_ATOM0_CH2_STAT_ACBI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_STAT_ACBI_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_STAT_ACBI_MASK) #define GTM_gtm_cls0_ATOM0_CH2_STAT_DV_MASK (0x200000U) #define GTM_gtm_cls0_ATOM0_CH2_STAT_DV_SHIFT (21U) #define GTM_gtm_cls0_ATOM0_CH2_STAT_DV_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH2_STAT_DV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_STAT_DV_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_STAT_DV_MASK) #define GTM_gtm_cls0_ATOM0_CH2_STAT_WRF_MASK (0x400000U) #define GTM_gtm_cls0_ATOM0_CH2_STAT_WRF_SHIFT (22U) #define GTM_gtm_cls0_ATOM0_CH2_STAT_WRF_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH2_STAT_WRF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_STAT_WRF_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_STAT_WRF_MASK) #define GTM_gtm_cls0_ATOM0_CH2_STAT_DR_MASK (0x800000U) #define GTM_gtm_cls0_ATOM0_CH2_STAT_DR_SHIFT (23U) #define GTM_gtm_cls0_ATOM0_CH2_STAT_DR_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH2_STAT_DR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_STAT_DR_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_STAT_DR_MASK) #define GTM_gtm_cls0_ATOM0_CH2_STAT_ACBO_MASK (0x1F000000U) #define GTM_gtm_cls0_ATOM0_CH2_STAT_ACBO_SHIFT (24U) #define GTM_gtm_cls0_ATOM0_CH2_STAT_ACBO_WIDTH (5U) #define GTM_gtm_cls0_ATOM0_CH2_STAT_ACBO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_STAT_ACBO_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_STAT_ACBO_MASK) #define GTM_gtm_cls0_ATOM0_CH2_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls0_ATOM0_CH2_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls0_ATOM0_CH2_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH2_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_STAT_OSM_RTF_MASK) /*! @} */ /*! @name ATOM0_CH2_IRQ_NOTIFY - ATOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH2_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH2_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH2_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH2_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls0_ATOM0_CH2_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_ATOM0_CH2_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_ATOM0_CH2_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH2_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name ATOM0_CH2_IRQ_EN - ATOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH2_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH2_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH2_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH2_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls0_ATOM0_CH2_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_ATOM0_CH2_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_ATOM0_CH2_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH2_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name ATOM0_CH2_IRQ_FORCINT - ATOM[i] channel [x] software interrupt generation */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH2_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH2_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH2_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH2_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls0_ATOM0_CH2_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_ATOM0_CH2_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_ATOM0_CH2_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH2_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name ATOM0_CH2_IRQ_MODE - ATOM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH2_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_ATOM0_CH2_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH2_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_CH2_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name ATOM0_CH2_CTRL_SR - ATOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH2_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls0_ATOM0_CH2_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH2_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls0_ATOM0_CH2_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name ATOM0_CH3_RDADDR - ATOM[i] channel[x] ARU read address register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH3_RDADDR_RDADDR0_MASK (0x1FFU) #define GTM_gtm_cls0_ATOM0_CH3_RDADDR_RDADDR0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH3_RDADDR_RDADDR0_WIDTH (9U) #define GTM_gtm_cls0_ATOM0_CH3_RDADDR_RDADDR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_RDADDR_RDADDR0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_RDADDR_RDADDR0_MASK) #define GTM_gtm_cls0_ATOM0_CH3_RDADDR_RDADDR1_MASK (0x1FF0000U) #define GTM_gtm_cls0_ATOM0_CH3_RDADDR_RDADDR1_SHIFT (16U) #define GTM_gtm_cls0_ATOM0_CH3_RDADDR_RDADDR1_WIDTH (9U) #define GTM_gtm_cls0_ATOM0_CH3_RDADDR_RDADDR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_RDADDR_RDADDR1_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_RDADDR_RDADDR1_MASK) /*! @} */ /*! @name ATOM0_CH3_CTRL - ATOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH3_CTRL_MODE_MASK (0x3U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_MODE_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_MODE_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_CTRL_MODE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_CTRL_MODE_MASK) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_TB12_SEL_MASK (0x4U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_TB12_SEL_SHIFT (2U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_TB12_SEL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_TB12_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_CTRL_TB12_SEL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_CTRL_TB12_SEL_MASK) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_ARU_EN_MASK (0x8U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_ARU_EN_SHIFT (3U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_CTRL_ARU_EN_MASK) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_ACB_MASK (0x1F0U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_ACB_SHIFT (4U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_ACB_WIDTH (5U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_ACB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_CTRL_ACB_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_CTRL_ACB_MASK) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_CMP_CTRL_MASK (0x200U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_CMP_CTRL_SHIFT (9U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_CMP_CTRL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_CMP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_CTRL_CMP_CTRL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_CTRL_CMP_CTRL_MASK) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_EUPM_MASK (0x400U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_EUPM_SHIFT (10U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_EUPM_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_EUPM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_CTRL_EUPM_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_CTRL_EUPM_MASK) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_CTRL_SL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_CTRL_SL_MASK) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_WR_REQ_MASK (0x10000U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_WR_REQ_SHIFT (16U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_WR_REQ_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_WR_REQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_CTRL_WR_REQ_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_CTRL_WR_REQ_MASK) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_CTRL_UDMODE_MASK) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_SLA_MASK (0x2000000U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_SLA_SHIFT (25U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_SLA_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_SLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_CTRL_SLA_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_CTRL_SLA_MASK) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_CTRL_OSM_MASK) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_ABM_MASK (0x8000000U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_ABM_SHIFT (27U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_ABM_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_ABM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_CTRL_ABM_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_CTRL_ABM_MASK) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_EXT_FUPD_MASK (0x20000000U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_EXT_FUPD_SHIFT (29U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_EXT_FUPD_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_EXT_FUPD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_CTRL_EXT_FUPD_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_CTRL_EXT_FUPD_MASK) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_SOMB_MASK (0x40000000U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_SOMB_SHIFT (30U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_SOMB_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_SOMB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_CTRL_SOMB_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_CTRL_SOMB_MASK) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_CTRL_FREEZE_MASK) /*! @} */ /*! @name ATOM0_CH3_SR0 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH3_SR0_SR0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH3_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH3_SR0_SR0_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH3_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_SR0_SR0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_SR0_SR0_MASK) /*! @} */ /*! @name ATOM0_CH3_SR1 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH3_SR1_SR1_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH3_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH3_SR1_SR1_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH3_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_SR1_SR1_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_SR1_SR1_MASK) /*! @} */ /*! @name ATOM0_CH3_CM0 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH3_CM0_CM0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH3_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH3_CM0_CM0_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH3_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_CM0_CM0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_CM0_CM0_MASK) /*! @} */ /*! @name ATOM0_CH3_CM1 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH3_CM1_CM1_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH3_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH3_CM1_CM1_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH3_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_CM1_CM1_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_CM1_CM1_MASK) /*! @} */ /*! @name ATOM0_CH3_CN0 - ATOM[i] channel [x] CCU0 counter register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH3_CN0_CN0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH3_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH3_CN0_CN0_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH3_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_CN0_CN0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_CN0_CN0_MASK) /*! @} */ /*! @name ATOM0_CH3_STAT - ATOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH3_STAT_OL_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH3_STAT_OL_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH3_STAT_OL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH3_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_STAT_OL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_STAT_OL_MASK) #define GTM_gtm_cls0_ATOM0_CH3_STAT_ACBI_MASK (0x1F0000U) #define GTM_gtm_cls0_ATOM0_CH3_STAT_ACBI_SHIFT (16U) #define GTM_gtm_cls0_ATOM0_CH3_STAT_ACBI_WIDTH (5U) #define GTM_gtm_cls0_ATOM0_CH3_STAT_ACBI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_STAT_ACBI_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_STAT_ACBI_MASK) #define GTM_gtm_cls0_ATOM0_CH3_STAT_DV_MASK (0x200000U) #define GTM_gtm_cls0_ATOM0_CH3_STAT_DV_SHIFT (21U) #define GTM_gtm_cls0_ATOM0_CH3_STAT_DV_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH3_STAT_DV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_STAT_DV_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_STAT_DV_MASK) #define GTM_gtm_cls0_ATOM0_CH3_STAT_WRF_MASK (0x400000U) #define GTM_gtm_cls0_ATOM0_CH3_STAT_WRF_SHIFT (22U) #define GTM_gtm_cls0_ATOM0_CH3_STAT_WRF_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH3_STAT_WRF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_STAT_WRF_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_STAT_WRF_MASK) #define GTM_gtm_cls0_ATOM0_CH3_STAT_DR_MASK (0x800000U) #define GTM_gtm_cls0_ATOM0_CH3_STAT_DR_SHIFT (23U) #define GTM_gtm_cls0_ATOM0_CH3_STAT_DR_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH3_STAT_DR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_STAT_DR_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_STAT_DR_MASK) #define GTM_gtm_cls0_ATOM0_CH3_STAT_ACBO_MASK (0x1F000000U) #define GTM_gtm_cls0_ATOM0_CH3_STAT_ACBO_SHIFT (24U) #define GTM_gtm_cls0_ATOM0_CH3_STAT_ACBO_WIDTH (5U) #define GTM_gtm_cls0_ATOM0_CH3_STAT_ACBO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_STAT_ACBO_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_STAT_ACBO_MASK) #define GTM_gtm_cls0_ATOM0_CH3_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls0_ATOM0_CH3_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls0_ATOM0_CH3_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH3_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_STAT_OSM_RTF_MASK) /*! @} */ /*! @name ATOM0_CH3_IRQ_NOTIFY - ATOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH3_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH3_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH3_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH3_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls0_ATOM0_CH3_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_ATOM0_CH3_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_ATOM0_CH3_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH3_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name ATOM0_CH3_IRQ_EN - ATOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH3_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH3_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH3_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH3_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls0_ATOM0_CH3_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_ATOM0_CH3_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_ATOM0_CH3_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH3_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name ATOM0_CH3_IRQ_FORCINT - ATOM[i] channel [x] software interrupt generation */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH3_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH3_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH3_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH3_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls0_ATOM0_CH3_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_ATOM0_CH3_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_ATOM0_CH3_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH3_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name ATOM0_CH3_IRQ_MODE - ATOM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH3_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_ATOM0_CH3_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH3_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_CH3_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name ATOM0_CH3_CTRL_SR - ATOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH3_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls0_ATOM0_CH3_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH3_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls0_ATOM0_CH3_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name ATOM0_CH4_RDADDR - ATOM[i] channel[x] ARU read address register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH4_RDADDR_RDADDR0_MASK (0x1FFU) #define GTM_gtm_cls0_ATOM0_CH4_RDADDR_RDADDR0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH4_RDADDR_RDADDR0_WIDTH (9U) #define GTM_gtm_cls0_ATOM0_CH4_RDADDR_RDADDR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_RDADDR_RDADDR0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_RDADDR_RDADDR0_MASK) #define GTM_gtm_cls0_ATOM0_CH4_RDADDR_RDADDR1_MASK (0x1FF0000U) #define GTM_gtm_cls0_ATOM0_CH4_RDADDR_RDADDR1_SHIFT (16U) #define GTM_gtm_cls0_ATOM0_CH4_RDADDR_RDADDR1_WIDTH (9U) #define GTM_gtm_cls0_ATOM0_CH4_RDADDR_RDADDR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_RDADDR_RDADDR1_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_RDADDR_RDADDR1_MASK) /*! @} */ /*! @name ATOM0_CH4_CTRL - ATOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH4_CTRL_MODE_MASK (0x3U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_MODE_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_MODE_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_CTRL_MODE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_CTRL_MODE_MASK) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_TB12_SEL_MASK (0x4U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_TB12_SEL_SHIFT (2U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_TB12_SEL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_TB12_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_CTRL_TB12_SEL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_CTRL_TB12_SEL_MASK) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_ARU_EN_MASK (0x8U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_ARU_EN_SHIFT (3U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_CTRL_ARU_EN_MASK) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_ACB_MASK (0x1F0U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_ACB_SHIFT (4U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_ACB_WIDTH (5U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_ACB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_CTRL_ACB_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_CTRL_ACB_MASK) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_CMP_CTRL_MASK (0x200U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_CMP_CTRL_SHIFT (9U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_CMP_CTRL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_CMP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_CTRL_CMP_CTRL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_CTRL_CMP_CTRL_MASK) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_EUPM_MASK (0x400U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_EUPM_SHIFT (10U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_EUPM_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_EUPM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_CTRL_EUPM_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_CTRL_EUPM_MASK) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_CTRL_SL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_CTRL_SL_MASK) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_WR_REQ_MASK (0x10000U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_WR_REQ_SHIFT (16U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_WR_REQ_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_WR_REQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_CTRL_WR_REQ_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_CTRL_WR_REQ_MASK) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_CTRL_UDMODE_MASK) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_SLA_MASK (0x2000000U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_SLA_SHIFT (25U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_SLA_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_SLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_CTRL_SLA_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_CTRL_SLA_MASK) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_CTRL_OSM_MASK) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_ABM_MASK (0x8000000U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_ABM_SHIFT (27U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_ABM_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_ABM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_CTRL_ABM_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_CTRL_ABM_MASK) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_EXT_FUPD_MASK (0x20000000U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_EXT_FUPD_SHIFT (29U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_EXT_FUPD_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_EXT_FUPD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_CTRL_EXT_FUPD_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_CTRL_EXT_FUPD_MASK) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_SOMB_MASK (0x40000000U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_SOMB_SHIFT (30U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_SOMB_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_SOMB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_CTRL_SOMB_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_CTRL_SOMB_MASK) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_CTRL_FREEZE_MASK) /*! @} */ /*! @name ATOM0_CH4_SR0 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH4_SR0_SR0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH4_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH4_SR0_SR0_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH4_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_SR0_SR0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_SR0_SR0_MASK) /*! @} */ /*! @name ATOM0_CH4_SR1 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH4_SR1_SR1_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH4_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH4_SR1_SR1_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH4_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_SR1_SR1_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_SR1_SR1_MASK) /*! @} */ /*! @name ATOM0_CH4_CM0 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH4_CM0_CM0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH4_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH4_CM0_CM0_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH4_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_CM0_CM0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_CM0_CM0_MASK) /*! @} */ /*! @name ATOM0_CH4_CM1 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH4_CM1_CM1_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH4_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH4_CM1_CM1_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH4_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_CM1_CM1_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_CM1_CM1_MASK) /*! @} */ /*! @name ATOM0_CH4_CN0 - ATOM[i] channel [x] CCU0 counter register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH4_CN0_CN0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH4_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH4_CN0_CN0_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH4_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_CN0_CN0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_CN0_CN0_MASK) /*! @} */ /*! @name ATOM0_CH4_STAT - ATOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH4_STAT_OL_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH4_STAT_OL_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH4_STAT_OL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH4_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_STAT_OL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_STAT_OL_MASK) #define GTM_gtm_cls0_ATOM0_CH4_STAT_ACBI_MASK (0x1F0000U) #define GTM_gtm_cls0_ATOM0_CH4_STAT_ACBI_SHIFT (16U) #define GTM_gtm_cls0_ATOM0_CH4_STAT_ACBI_WIDTH (5U) #define GTM_gtm_cls0_ATOM0_CH4_STAT_ACBI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_STAT_ACBI_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_STAT_ACBI_MASK) #define GTM_gtm_cls0_ATOM0_CH4_STAT_DV_MASK (0x200000U) #define GTM_gtm_cls0_ATOM0_CH4_STAT_DV_SHIFT (21U) #define GTM_gtm_cls0_ATOM0_CH4_STAT_DV_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH4_STAT_DV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_STAT_DV_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_STAT_DV_MASK) #define GTM_gtm_cls0_ATOM0_CH4_STAT_WRF_MASK (0x400000U) #define GTM_gtm_cls0_ATOM0_CH4_STAT_WRF_SHIFT (22U) #define GTM_gtm_cls0_ATOM0_CH4_STAT_WRF_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH4_STAT_WRF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_STAT_WRF_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_STAT_WRF_MASK) #define GTM_gtm_cls0_ATOM0_CH4_STAT_DR_MASK (0x800000U) #define GTM_gtm_cls0_ATOM0_CH4_STAT_DR_SHIFT (23U) #define GTM_gtm_cls0_ATOM0_CH4_STAT_DR_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH4_STAT_DR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_STAT_DR_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_STAT_DR_MASK) #define GTM_gtm_cls0_ATOM0_CH4_STAT_ACBO_MASK (0x1F000000U) #define GTM_gtm_cls0_ATOM0_CH4_STAT_ACBO_SHIFT (24U) #define GTM_gtm_cls0_ATOM0_CH4_STAT_ACBO_WIDTH (5U) #define GTM_gtm_cls0_ATOM0_CH4_STAT_ACBO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_STAT_ACBO_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_STAT_ACBO_MASK) #define GTM_gtm_cls0_ATOM0_CH4_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls0_ATOM0_CH4_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls0_ATOM0_CH4_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH4_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_STAT_OSM_RTF_MASK) /*! @} */ /*! @name ATOM0_CH4_IRQ_NOTIFY - ATOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH4_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH4_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH4_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH4_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls0_ATOM0_CH4_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_ATOM0_CH4_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_ATOM0_CH4_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH4_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name ATOM0_CH4_IRQ_EN - ATOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH4_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH4_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH4_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH4_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls0_ATOM0_CH4_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_ATOM0_CH4_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_ATOM0_CH4_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH4_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name ATOM0_CH4_IRQ_FORCINT - ATOM[i] channel [x] software interrupt generation */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH4_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH4_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH4_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH4_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls0_ATOM0_CH4_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_ATOM0_CH4_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_ATOM0_CH4_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH4_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name ATOM0_CH4_IRQ_MODE - ATOM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH4_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_ATOM0_CH4_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH4_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_CH4_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name ATOM0_CH4_CTRL_SR - ATOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH4_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls0_ATOM0_CH4_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH4_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls0_ATOM0_CH4_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name ATOM0_CH5_RDADDR - ATOM[i] channel[x] ARU read address register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH5_RDADDR_RDADDR0_MASK (0x1FFU) #define GTM_gtm_cls0_ATOM0_CH5_RDADDR_RDADDR0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH5_RDADDR_RDADDR0_WIDTH (9U) #define GTM_gtm_cls0_ATOM0_CH5_RDADDR_RDADDR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_RDADDR_RDADDR0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_RDADDR_RDADDR0_MASK) #define GTM_gtm_cls0_ATOM0_CH5_RDADDR_RDADDR1_MASK (0x1FF0000U) #define GTM_gtm_cls0_ATOM0_CH5_RDADDR_RDADDR1_SHIFT (16U) #define GTM_gtm_cls0_ATOM0_CH5_RDADDR_RDADDR1_WIDTH (9U) #define GTM_gtm_cls0_ATOM0_CH5_RDADDR_RDADDR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_RDADDR_RDADDR1_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_RDADDR_RDADDR1_MASK) /*! @} */ /*! @name ATOM0_CH5_CTRL - ATOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH5_CTRL_MODE_MASK (0x3U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_MODE_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_MODE_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_CTRL_MODE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_CTRL_MODE_MASK) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_TB12_SEL_MASK (0x4U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_TB12_SEL_SHIFT (2U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_TB12_SEL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_TB12_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_CTRL_TB12_SEL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_CTRL_TB12_SEL_MASK) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_ARU_EN_MASK (0x8U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_ARU_EN_SHIFT (3U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_CTRL_ARU_EN_MASK) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_ACB_MASK (0x1F0U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_ACB_SHIFT (4U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_ACB_WIDTH (5U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_ACB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_CTRL_ACB_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_CTRL_ACB_MASK) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_CMP_CTRL_MASK (0x200U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_CMP_CTRL_SHIFT (9U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_CMP_CTRL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_CMP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_CTRL_CMP_CTRL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_CTRL_CMP_CTRL_MASK) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_EUPM_MASK (0x400U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_EUPM_SHIFT (10U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_EUPM_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_EUPM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_CTRL_EUPM_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_CTRL_EUPM_MASK) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_CTRL_SL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_CTRL_SL_MASK) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_WR_REQ_MASK (0x10000U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_WR_REQ_SHIFT (16U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_WR_REQ_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_WR_REQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_CTRL_WR_REQ_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_CTRL_WR_REQ_MASK) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_CTRL_UDMODE_MASK) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_SLA_MASK (0x2000000U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_SLA_SHIFT (25U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_SLA_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_SLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_CTRL_SLA_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_CTRL_SLA_MASK) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_CTRL_OSM_MASK) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_ABM_MASK (0x8000000U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_ABM_SHIFT (27U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_ABM_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_ABM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_CTRL_ABM_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_CTRL_ABM_MASK) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_EXT_FUPD_MASK (0x20000000U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_EXT_FUPD_SHIFT (29U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_EXT_FUPD_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_EXT_FUPD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_CTRL_EXT_FUPD_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_CTRL_EXT_FUPD_MASK) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_SOMB_MASK (0x40000000U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_SOMB_SHIFT (30U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_SOMB_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_SOMB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_CTRL_SOMB_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_CTRL_SOMB_MASK) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_CTRL_FREEZE_MASK) /*! @} */ /*! @name ATOM0_CH5_SR0 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH5_SR0_SR0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH5_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH5_SR0_SR0_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH5_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_SR0_SR0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_SR0_SR0_MASK) /*! @} */ /*! @name ATOM0_CH5_SR1 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH5_SR1_SR1_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH5_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH5_SR1_SR1_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH5_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_SR1_SR1_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_SR1_SR1_MASK) /*! @} */ /*! @name ATOM0_CH5_CM0 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH5_CM0_CM0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH5_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH5_CM0_CM0_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH5_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_CM0_CM0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_CM0_CM0_MASK) /*! @} */ /*! @name ATOM0_CH5_CM1 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH5_CM1_CM1_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH5_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH5_CM1_CM1_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH5_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_CM1_CM1_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_CM1_CM1_MASK) /*! @} */ /*! @name ATOM0_CH5_CN0 - ATOM[i] channel [x] CCU0 counter register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH5_CN0_CN0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH5_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH5_CN0_CN0_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH5_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_CN0_CN0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_CN0_CN0_MASK) /*! @} */ /*! @name ATOM0_CH5_STAT - ATOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH5_STAT_OL_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH5_STAT_OL_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH5_STAT_OL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH5_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_STAT_OL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_STAT_OL_MASK) #define GTM_gtm_cls0_ATOM0_CH5_STAT_ACBI_MASK (0x1F0000U) #define GTM_gtm_cls0_ATOM0_CH5_STAT_ACBI_SHIFT (16U) #define GTM_gtm_cls0_ATOM0_CH5_STAT_ACBI_WIDTH (5U) #define GTM_gtm_cls0_ATOM0_CH5_STAT_ACBI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_STAT_ACBI_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_STAT_ACBI_MASK) #define GTM_gtm_cls0_ATOM0_CH5_STAT_DV_MASK (0x200000U) #define GTM_gtm_cls0_ATOM0_CH5_STAT_DV_SHIFT (21U) #define GTM_gtm_cls0_ATOM0_CH5_STAT_DV_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH5_STAT_DV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_STAT_DV_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_STAT_DV_MASK) #define GTM_gtm_cls0_ATOM0_CH5_STAT_WRF_MASK (0x400000U) #define GTM_gtm_cls0_ATOM0_CH5_STAT_WRF_SHIFT (22U) #define GTM_gtm_cls0_ATOM0_CH5_STAT_WRF_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH5_STAT_WRF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_STAT_WRF_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_STAT_WRF_MASK) #define GTM_gtm_cls0_ATOM0_CH5_STAT_DR_MASK (0x800000U) #define GTM_gtm_cls0_ATOM0_CH5_STAT_DR_SHIFT (23U) #define GTM_gtm_cls0_ATOM0_CH5_STAT_DR_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH5_STAT_DR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_STAT_DR_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_STAT_DR_MASK) #define GTM_gtm_cls0_ATOM0_CH5_STAT_ACBO_MASK (0x1F000000U) #define GTM_gtm_cls0_ATOM0_CH5_STAT_ACBO_SHIFT (24U) #define GTM_gtm_cls0_ATOM0_CH5_STAT_ACBO_WIDTH (5U) #define GTM_gtm_cls0_ATOM0_CH5_STAT_ACBO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_STAT_ACBO_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_STAT_ACBO_MASK) #define GTM_gtm_cls0_ATOM0_CH5_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls0_ATOM0_CH5_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls0_ATOM0_CH5_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH5_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_STAT_OSM_RTF_MASK) /*! @} */ /*! @name ATOM0_CH5_IRQ_NOTIFY - ATOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH5_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH5_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH5_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH5_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls0_ATOM0_CH5_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_ATOM0_CH5_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_ATOM0_CH5_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH5_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name ATOM0_CH5_IRQ_EN - ATOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH5_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH5_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH5_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH5_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls0_ATOM0_CH5_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_ATOM0_CH5_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_ATOM0_CH5_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH5_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name ATOM0_CH5_IRQ_FORCINT - ATOM[i] channel [x] software interrupt generation */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH5_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH5_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH5_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH5_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls0_ATOM0_CH5_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_ATOM0_CH5_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_ATOM0_CH5_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH5_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name ATOM0_CH5_IRQ_MODE - ATOM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH5_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_ATOM0_CH5_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH5_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_CH5_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name ATOM0_CH5_CTRL_SR - ATOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH5_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls0_ATOM0_CH5_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH5_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls0_ATOM0_CH5_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name ATOM0_CH6_RDADDR - ATOM[i] channel[x] ARU read address register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH6_RDADDR_RDADDR0_MASK (0x1FFU) #define GTM_gtm_cls0_ATOM0_CH6_RDADDR_RDADDR0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH6_RDADDR_RDADDR0_WIDTH (9U) #define GTM_gtm_cls0_ATOM0_CH6_RDADDR_RDADDR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_RDADDR_RDADDR0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_RDADDR_RDADDR0_MASK) #define GTM_gtm_cls0_ATOM0_CH6_RDADDR_RDADDR1_MASK (0x1FF0000U) #define GTM_gtm_cls0_ATOM0_CH6_RDADDR_RDADDR1_SHIFT (16U) #define GTM_gtm_cls0_ATOM0_CH6_RDADDR_RDADDR1_WIDTH (9U) #define GTM_gtm_cls0_ATOM0_CH6_RDADDR_RDADDR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_RDADDR_RDADDR1_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_RDADDR_RDADDR1_MASK) /*! @} */ /*! @name ATOM0_CH6_CTRL - ATOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH6_CTRL_MODE_MASK (0x3U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_MODE_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_MODE_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_CTRL_MODE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_CTRL_MODE_MASK) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_TB12_SEL_MASK (0x4U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_TB12_SEL_SHIFT (2U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_TB12_SEL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_TB12_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_CTRL_TB12_SEL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_CTRL_TB12_SEL_MASK) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_ARU_EN_MASK (0x8U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_ARU_EN_SHIFT (3U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_CTRL_ARU_EN_MASK) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_ACB_MASK (0x1F0U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_ACB_SHIFT (4U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_ACB_WIDTH (5U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_ACB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_CTRL_ACB_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_CTRL_ACB_MASK) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_CMP_CTRL_MASK (0x200U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_CMP_CTRL_SHIFT (9U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_CMP_CTRL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_CMP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_CTRL_CMP_CTRL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_CTRL_CMP_CTRL_MASK) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_EUPM_MASK (0x400U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_EUPM_SHIFT (10U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_EUPM_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_EUPM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_CTRL_EUPM_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_CTRL_EUPM_MASK) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_CTRL_SL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_CTRL_SL_MASK) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_WR_REQ_MASK (0x10000U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_WR_REQ_SHIFT (16U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_WR_REQ_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_WR_REQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_CTRL_WR_REQ_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_CTRL_WR_REQ_MASK) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_CTRL_UDMODE_MASK) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_SLA_MASK (0x2000000U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_SLA_SHIFT (25U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_SLA_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_SLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_CTRL_SLA_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_CTRL_SLA_MASK) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_CTRL_OSM_MASK) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_ABM_MASK (0x8000000U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_ABM_SHIFT (27U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_ABM_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_ABM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_CTRL_ABM_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_CTRL_ABM_MASK) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_EXT_FUPD_MASK (0x20000000U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_EXT_FUPD_SHIFT (29U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_EXT_FUPD_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_EXT_FUPD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_CTRL_EXT_FUPD_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_CTRL_EXT_FUPD_MASK) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_SOMB_MASK (0x40000000U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_SOMB_SHIFT (30U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_SOMB_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_SOMB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_CTRL_SOMB_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_CTRL_SOMB_MASK) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_CTRL_FREEZE_MASK) /*! @} */ /*! @name ATOM0_CH6_SR0 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH6_SR0_SR0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH6_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH6_SR0_SR0_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH6_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_SR0_SR0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_SR0_SR0_MASK) /*! @} */ /*! @name ATOM0_CH6_SR1 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH6_SR1_SR1_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH6_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH6_SR1_SR1_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH6_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_SR1_SR1_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_SR1_SR1_MASK) /*! @} */ /*! @name ATOM0_CH6_CM0 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH6_CM0_CM0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH6_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH6_CM0_CM0_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH6_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_CM0_CM0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_CM0_CM0_MASK) /*! @} */ /*! @name ATOM0_CH6_CM1 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH6_CM1_CM1_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH6_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH6_CM1_CM1_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH6_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_CM1_CM1_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_CM1_CM1_MASK) /*! @} */ /*! @name ATOM0_CH6_CN0 - ATOM[i] channel [x] CCU0 counter register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH6_CN0_CN0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH6_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH6_CN0_CN0_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH6_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_CN0_CN0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_CN0_CN0_MASK) /*! @} */ /*! @name ATOM0_CH6_STAT - ATOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH6_STAT_OL_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH6_STAT_OL_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH6_STAT_OL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH6_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_STAT_OL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_STAT_OL_MASK) #define GTM_gtm_cls0_ATOM0_CH6_STAT_ACBI_MASK (0x1F0000U) #define GTM_gtm_cls0_ATOM0_CH6_STAT_ACBI_SHIFT (16U) #define GTM_gtm_cls0_ATOM0_CH6_STAT_ACBI_WIDTH (5U) #define GTM_gtm_cls0_ATOM0_CH6_STAT_ACBI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_STAT_ACBI_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_STAT_ACBI_MASK) #define GTM_gtm_cls0_ATOM0_CH6_STAT_DV_MASK (0x200000U) #define GTM_gtm_cls0_ATOM0_CH6_STAT_DV_SHIFT (21U) #define GTM_gtm_cls0_ATOM0_CH6_STAT_DV_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH6_STAT_DV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_STAT_DV_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_STAT_DV_MASK) #define GTM_gtm_cls0_ATOM0_CH6_STAT_WRF_MASK (0x400000U) #define GTM_gtm_cls0_ATOM0_CH6_STAT_WRF_SHIFT (22U) #define GTM_gtm_cls0_ATOM0_CH6_STAT_WRF_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH6_STAT_WRF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_STAT_WRF_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_STAT_WRF_MASK) #define GTM_gtm_cls0_ATOM0_CH6_STAT_DR_MASK (0x800000U) #define GTM_gtm_cls0_ATOM0_CH6_STAT_DR_SHIFT (23U) #define GTM_gtm_cls0_ATOM0_CH6_STAT_DR_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH6_STAT_DR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_STAT_DR_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_STAT_DR_MASK) #define GTM_gtm_cls0_ATOM0_CH6_STAT_ACBO_MASK (0x1F000000U) #define GTM_gtm_cls0_ATOM0_CH6_STAT_ACBO_SHIFT (24U) #define GTM_gtm_cls0_ATOM0_CH6_STAT_ACBO_WIDTH (5U) #define GTM_gtm_cls0_ATOM0_CH6_STAT_ACBO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_STAT_ACBO_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_STAT_ACBO_MASK) #define GTM_gtm_cls0_ATOM0_CH6_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls0_ATOM0_CH6_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls0_ATOM0_CH6_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH6_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_STAT_OSM_RTF_MASK) /*! @} */ /*! @name ATOM0_CH6_IRQ_NOTIFY - ATOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH6_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH6_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH6_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH6_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls0_ATOM0_CH6_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_ATOM0_CH6_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_ATOM0_CH6_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH6_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name ATOM0_CH6_IRQ_EN - ATOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH6_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH6_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH6_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH6_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls0_ATOM0_CH6_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_ATOM0_CH6_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_ATOM0_CH6_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH6_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name ATOM0_CH6_IRQ_FORCINT - ATOM[i] channel [x] software interrupt generation */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH6_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH6_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH6_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH6_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls0_ATOM0_CH6_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_ATOM0_CH6_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_ATOM0_CH6_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH6_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name ATOM0_CH6_IRQ_MODE - ATOM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH6_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_ATOM0_CH6_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH6_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_CH6_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name ATOM0_CH6_CTRL_SR - ATOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH6_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls0_ATOM0_CH6_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH6_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls0_ATOM0_CH6_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name ATOM0_CH7_RDADDR - ATOM[i] channel[x] ARU read address register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH7_RDADDR_RDADDR0_MASK (0x1FFU) #define GTM_gtm_cls0_ATOM0_CH7_RDADDR_RDADDR0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH7_RDADDR_RDADDR0_WIDTH (9U) #define GTM_gtm_cls0_ATOM0_CH7_RDADDR_RDADDR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_RDADDR_RDADDR0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_RDADDR_RDADDR0_MASK) #define GTM_gtm_cls0_ATOM0_CH7_RDADDR_RDADDR1_MASK (0x1FF0000U) #define GTM_gtm_cls0_ATOM0_CH7_RDADDR_RDADDR1_SHIFT (16U) #define GTM_gtm_cls0_ATOM0_CH7_RDADDR_RDADDR1_WIDTH (9U) #define GTM_gtm_cls0_ATOM0_CH7_RDADDR_RDADDR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_RDADDR_RDADDR1_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_RDADDR_RDADDR1_MASK) /*! @} */ /*! @name ATOM0_CH7_CTRL - ATOM[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH7_CTRL_MODE_MASK (0x3U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_MODE_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_MODE_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_CTRL_MODE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_CTRL_MODE_MASK) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_TB12_SEL_MASK (0x4U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_TB12_SEL_SHIFT (2U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_TB12_SEL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_TB12_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_CTRL_TB12_SEL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_CTRL_TB12_SEL_MASK) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_ARU_EN_MASK (0x8U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_ARU_EN_SHIFT (3U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_ARU_EN_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_ARU_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_CTRL_ARU_EN_MASK) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_ACB_MASK (0x1F0U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_ACB_SHIFT (4U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_ACB_WIDTH (5U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_ACB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_CTRL_ACB_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_CTRL_ACB_MASK) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_CMP_CTRL_MASK (0x200U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_CMP_CTRL_SHIFT (9U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_CMP_CTRL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_CMP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_CTRL_CMP_CTRL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_CTRL_CMP_CTRL_MASK) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_EUPM_MASK (0x400U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_EUPM_SHIFT (10U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_EUPM_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_EUPM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_CTRL_EUPM_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_CTRL_EUPM_MASK) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_SL_MASK (0x800U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_SL_SHIFT (11U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_SL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_CTRL_SL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_CTRL_SL_MASK) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_CLK_SRC_MASK (0xF000U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_CLK_SRC_SHIFT (12U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_CLK_SRC_WIDTH (4U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_CTRL_CLK_SRC_MASK) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_WR_REQ_MASK (0x10000U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_WR_REQ_SHIFT (16U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_WR_REQ_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_WR_REQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_CTRL_WR_REQ_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_CTRL_WR_REQ_MASK) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_TRIG_PULSE_MASK (0x20000U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_TRIG_PULSE_SHIFT (17U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_TRIG_PULSE_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_CTRL_TRIG_PULSE_MASK) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_UDMODE_MASK (0xC0000U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_UDMODE_SHIFT (18U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_UDMODE_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_UDMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_CTRL_UDMODE_MASK) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_RST_CCU0_MASK (0x100000U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_RST_CCU0_SHIFT (20U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_RST_CCU0_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_RST_CCU0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_CTRL_RST_CCU0_MASK) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_OSM_TRIG_MASK (0x200000U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_OSM_TRIG_SHIFT (21U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_OSM_TRIG_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_OSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_CTRL_OSM_TRIG_MASK) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_EXT_TRIG_MASK (0x400000U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_EXT_TRIG_SHIFT (22U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_EXT_TRIG_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_CTRL_EXT_TRIG_MASK) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_EXTTRIGOUT_MASK (0x800000U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_EXTTRIGOUT_SHIFT (23U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_EXTTRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_CTRL_EXTTRIGOUT_MASK) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_TRIGOUT_MASK (0x1000000U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_TRIGOUT_SHIFT (24U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_TRIGOUT_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_CTRL_TRIGOUT_MASK) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_SLA_MASK (0x2000000U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_SLA_SHIFT (25U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_SLA_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_SLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_CTRL_SLA_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_CTRL_SLA_MASK) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_OSM_MASK (0x4000000U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_OSM_SHIFT (26U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_OSM_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_OSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_CTRL_OSM_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_CTRL_OSM_MASK) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_ABM_MASK (0x8000000U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_ABM_SHIFT (27U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_ABM_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_ABM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_CTRL_ABM_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_CTRL_ABM_MASK) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_EXT_FUPD_MASK (0x20000000U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_EXT_FUPD_SHIFT (29U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_EXT_FUPD_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_EXT_FUPD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_CTRL_EXT_FUPD_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_CTRL_EXT_FUPD_MASK) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_SOMB_MASK (0x40000000U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_SOMB_SHIFT (30U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_SOMB_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_SOMB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_CTRL_SOMB_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_CTRL_SOMB_MASK) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_FREEZE_MASK (0x80000000U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_FREEZE_SHIFT (31U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_FREEZE_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_CTRL_FREEZE_MASK) /*! @} */ /*! @name ATOM0_CH7_SR0 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH7_SR0_SR0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH7_SR0_SR0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH7_SR0_SR0_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH7_SR0_SR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_SR0_SR0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_SR0_SR0_MASK) /*! @} */ /*! @name ATOM0_CH7_SR1 - ATOM[i] channel [x] CCU0 compare shadow register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH7_SR1_SR1_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH7_SR1_SR1_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH7_SR1_SR1_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH7_SR1_SR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_SR1_SR1_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_SR1_SR1_MASK) /*! @} */ /*! @name ATOM0_CH7_CM0 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH7_CM0_CM0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH7_CM0_CM0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH7_CM0_CM0_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH7_CM0_CM0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_CM0_CM0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_CM0_CM0_MASK) /*! @} */ /*! @name ATOM0_CH7_CM1 - ATOM[i] channel [x] CCU0 compare register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH7_CM1_CM1_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH7_CM1_CM1_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH7_CM1_CM1_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH7_CM1_CM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_CM1_CM1_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_CM1_CM1_MASK) /*! @} */ /*! @name ATOM0_CH7_CN0 - ATOM[i] channel [x] CCU0 counter register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH7_CN0_CN0_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_CH7_CN0_CN0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH7_CN0_CN0_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_CH7_CN0_CN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_CN0_CN0_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_CN0_CN0_MASK) /*! @} */ /*! @name ATOM0_CH7_STAT - ATOM[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH7_STAT_OL_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH7_STAT_OL_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH7_STAT_OL_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH7_STAT_OL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_STAT_OL_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_STAT_OL_MASK) #define GTM_gtm_cls0_ATOM0_CH7_STAT_ACBI_MASK (0x1F0000U) #define GTM_gtm_cls0_ATOM0_CH7_STAT_ACBI_SHIFT (16U) #define GTM_gtm_cls0_ATOM0_CH7_STAT_ACBI_WIDTH (5U) #define GTM_gtm_cls0_ATOM0_CH7_STAT_ACBI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_STAT_ACBI_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_STAT_ACBI_MASK) #define GTM_gtm_cls0_ATOM0_CH7_STAT_DV_MASK (0x200000U) #define GTM_gtm_cls0_ATOM0_CH7_STAT_DV_SHIFT (21U) #define GTM_gtm_cls0_ATOM0_CH7_STAT_DV_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH7_STAT_DV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_STAT_DV_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_STAT_DV_MASK) #define GTM_gtm_cls0_ATOM0_CH7_STAT_WRF_MASK (0x400000U) #define GTM_gtm_cls0_ATOM0_CH7_STAT_WRF_SHIFT (22U) #define GTM_gtm_cls0_ATOM0_CH7_STAT_WRF_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH7_STAT_WRF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_STAT_WRF_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_STAT_WRF_MASK) #define GTM_gtm_cls0_ATOM0_CH7_STAT_DR_MASK (0x800000U) #define GTM_gtm_cls0_ATOM0_CH7_STAT_DR_SHIFT (23U) #define GTM_gtm_cls0_ATOM0_CH7_STAT_DR_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH7_STAT_DR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_STAT_DR_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_STAT_DR_MASK) #define GTM_gtm_cls0_ATOM0_CH7_STAT_ACBO_MASK (0x1F000000U) #define GTM_gtm_cls0_ATOM0_CH7_STAT_ACBO_SHIFT (24U) #define GTM_gtm_cls0_ATOM0_CH7_STAT_ACBO_WIDTH (5U) #define GTM_gtm_cls0_ATOM0_CH7_STAT_ACBO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_STAT_ACBO_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_STAT_ACBO_MASK) #define GTM_gtm_cls0_ATOM0_CH7_STAT_OSM_RTF_MASK (0x20000000U) #define GTM_gtm_cls0_ATOM0_CH7_STAT_OSM_RTF_SHIFT (29U) #define GTM_gtm_cls0_ATOM0_CH7_STAT_OSM_RTF_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH7_STAT_OSM_RTF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_STAT_OSM_RTF_MASK) /*! @} */ /*! @name ATOM0_CH7_IRQ_NOTIFY - ATOM[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH7_IRQ_NOTIFY_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH7_IRQ_NOTIFY_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH7_IRQ_NOTIFY_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH7_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_IRQ_NOTIFY_CCU0TC_MASK) #define GTM_gtm_cls0_ATOM0_CH7_IRQ_NOTIFY_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_ATOM0_CH7_IRQ_NOTIFY_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_ATOM0_CH7_IRQ_NOTIFY_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH7_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_IRQ_NOTIFY_CCU1TC_MASK) /*! @} */ /*! @name ATOM0_CH7_IRQ_EN - ATOM[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH7_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH7_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH7_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH7_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_IRQ_EN_CCU0TC_IRQ_EN_MASK) #define GTM_gtm_cls0_ATOM0_CH7_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_ATOM0_CH7_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_ATOM0_CH7_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH7_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_IRQ_EN_CCU1TC_IRQ_EN_MASK) /*! @} */ /*! @name ATOM0_CH7_IRQ_FORCINT - ATOM[i] channel [x] software interrupt generation */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH7_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_CH7_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH7_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH7_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_IRQ_FORCINT_TRG_CCU0TC_MASK) #define GTM_gtm_cls0_ATOM0_CH7_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U) #define GTM_gtm_cls0_ATOM0_CH7_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U) #define GTM_gtm_cls0_ATOM0_CH7_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH7_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_IRQ_FORCINT_TRG_CCU1TC_MASK) /*! @} */ /*! @name ATOM0_CH7_IRQ_MODE - ATOM[i] channel [x] interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH7_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_ATOM0_CH7_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_CH7_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_CH7_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name ATOM0_CH7_CTRL_SR - ATOM[i] channel [x] control shadow register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_CH7_CTRL_SR_SL_SR_MASK (0x800U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_SR_SL_SR_SHIFT (11U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_SR_SL_SR_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_SR_SL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_CTRL_SR_SL_SR_MASK) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_SR_CLK_SRC_SR_MASK (0xF000U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_SR_CLK_SRC_SR_SHIFT (12U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_SR_CLK_SRC_SR_WIDTH (4U) #define GTM_gtm_cls0_ATOM0_CH7_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_CH7_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls0_ATOM0_CH7_CTRL_SR_CLK_SRC_SR_MASK) /*! @} */ /*! @name ATOM0_AGC_GLB_CTRL - ATOM[i] AGC global control register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_HOST_TRIG_MASK (0x1U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_HOST_TRIG_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_HOST_TRIG_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_HOST_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_HOST_TRIG_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_HOST_TRIG_MASK) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH0_MASK (0x100U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH0_SHIFT (8U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH0_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH0_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH0_MASK) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH1_MASK (0x200U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH1_SHIFT (9U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH1_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH1_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH1_MASK) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH2_MASK (0x400U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH2_SHIFT (10U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH2_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH2_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH2_MASK) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH3_MASK (0x800U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH3_SHIFT (11U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH3_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH3_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH3_MASK) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH4_MASK (0x1000U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH4_SHIFT (12U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH4_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH4_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH4_MASK) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH5_MASK (0x2000U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH5_SHIFT (13U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH5_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH5_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH5_MASK) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH6_MASK (0x4000U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH6_SHIFT (14U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH6_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH6_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH6_MASK) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH7_MASK (0x8000U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH7_SHIFT (15U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH7_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH7_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_RST_CH7_MASK) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL0_MASK (0x30000U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL0_SHIFT (16U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL0_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL0_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL0_MASK) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL1_MASK (0xC0000U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL1_SHIFT (18U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL1_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL1_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL1_MASK) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL2_MASK (0x300000U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL2_SHIFT (20U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL2_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL2_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL2_MASK) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL3_MASK (0xC00000U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL3_SHIFT (22U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL3_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL3_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL3_MASK) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL4_MASK (0x3000000U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL4_SHIFT (24U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL4_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL4_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL4_MASK) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL5_MASK (0xC000000U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL5_SHIFT (26U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL5_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL5_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL5_MASK) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL6_MASK (0x30000000U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL6_SHIFT (28U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL6_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL6_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL6_MASK) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL7_MASK (0xC0000000U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL7_SHIFT (30U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL7_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL7_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_GLB_CTRL_UPEN_CTRL7_MASK) /*! @} */ /*! @name ATOM0_AGC_ENDIS_CTRL - ATOM[i] AGC enable/disable control register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL0_MASK (0x3U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL0_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL0_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL0_MASK) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL1_MASK (0xCU) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL1_SHIFT (2U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL1_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL1_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL1_MASK) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL2_MASK (0x30U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL2_SHIFT (4U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL2_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL2_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL2_MASK) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL3_MASK (0xC0U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL3_SHIFT (6U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL3_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL3_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL3_MASK) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL4_MASK (0x300U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL4_SHIFT (8U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL4_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL4_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL4_MASK) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL5_MASK (0xC00U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL5_SHIFT (10U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL5_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL5_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL5_MASK) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL6_MASK (0x3000U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL6_SHIFT (12U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL6_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL6_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL6_MASK) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL7_MASK (0xC000U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL7_SHIFT (14U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL7_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL7_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_ENDIS_CTRL_ENDIS_CTRL7_MASK) /*! @} */ /*! @name ATOM0_AGC_ENDIS_STAT - ATOM[i] AGC enable/disable status register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT0_MASK (0x3U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT0_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT0_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT0_MASK) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT1_MASK (0xCU) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT1_SHIFT (2U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT1_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT1_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT1_MASK) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT2_MASK (0x30U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT2_SHIFT (4U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT2_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT2_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT2_MASK) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT3_MASK (0xC0U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT3_SHIFT (6U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT3_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT3_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT3_MASK) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT4_MASK (0x300U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT4_SHIFT (8U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT4_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT4_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT4_MASK) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT5_MASK (0xC00U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT5_SHIFT (10U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT5_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT5_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT5_MASK) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT6_MASK (0x3000U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT6_SHIFT (12U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT6_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT6_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT6_MASK) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT7_MASK (0xC000U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT7_SHIFT (14U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT7_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT7_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_ENDIS_STAT_ENDIS_STAT7_MASK) /*! @} */ /*! @name ATOM0_AGC_ACT_TB - ATOM[i] AGC action time base register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_AGC_ACT_TB_ACT_TB_MASK (0xFFFFFFU) #define GTM_gtm_cls0_ATOM0_AGC_ACT_TB_ACT_TB_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_AGC_ACT_TB_ACT_TB_WIDTH (24U) #define GTM_gtm_cls0_ATOM0_AGC_ACT_TB_ACT_TB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_ACT_TB_ACT_TB_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_ACT_TB_ACT_TB_MASK) #define GTM_gtm_cls0_ATOM0_AGC_ACT_TB_TB_TRIG_MASK (0x1000000U) #define GTM_gtm_cls0_ATOM0_AGC_ACT_TB_TB_TRIG_SHIFT (24U) #define GTM_gtm_cls0_ATOM0_AGC_ACT_TB_TB_TRIG_WIDTH (1U) #define GTM_gtm_cls0_ATOM0_AGC_ACT_TB_TB_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_ACT_TB_TB_TRIG_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_ACT_TB_TB_TRIG_MASK) #define GTM_gtm_cls0_ATOM0_AGC_ACT_TB_TBU_SEL_MASK (0x6000000U) #define GTM_gtm_cls0_ATOM0_AGC_ACT_TB_TBU_SEL_SHIFT (25U) #define GTM_gtm_cls0_ATOM0_AGC_ACT_TB_TBU_SEL_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_ACT_TB_TBU_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_ACT_TB_TBU_SEL_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_ACT_TB_TBU_SEL_MASK) /*! @} */ /*! @name ATOM0_AGC_OUTEN_CTRL - ATOM[i] AGC output enable control register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL0_MASK (0x3U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL0_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL0_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL0_MASK) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL1_MASK (0xCU) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL1_SHIFT (2U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL1_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL1_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL1_MASK) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL2_MASK (0x30U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL2_SHIFT (4U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL2_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL2_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL2_MASK) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL3_MASK (0xC0U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL3_SHIFT (6U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL3_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL3_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL3_MASK) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL4_MASK (0x300U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL4_SHIFT (8U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL4_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL4_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL4_MASK) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL5_MASK (0xC00U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL5_SHIFT (10U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL5_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL5_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL5_MASK) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL6_MASK (0x3000U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL6_SHIFT (12U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL6_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL6_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL6_MASK) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL7_MASK (0xC000U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL7_SHIFT (14U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL7_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL7_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_OUTEN_CTRL_OUTEN_CTRL7_MASK) /*! @} */ /*! @name ATOM0_AGC_OUTEN_STAT - ATOM[i] AGC output enable status register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT0_MASK (0x3U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT0_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT0_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT0_MASK) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT1_MASK (0xCU) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT1_SHIFT (2U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT1_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT1_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT1_MASK) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT2_MASK (0x30U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT2_SHIFT (4U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT2_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT2_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT2_MASK) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT3_MASK (0xC0U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT3_SHIFT (6U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT3_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT3_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT3_MASK) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT4_MASK (0x300U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT4_SHIFT (8U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT4_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT4_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT4_MASK) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT5_MASK (0xC00U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT5_SHIFT (10U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT5_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT5_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT5_MASK) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT6_MASK (0x3000U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT6_SHIFT (12U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT6_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT6_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT6_MASK) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT7_MASK (0xC000U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT7_SHIFT (14U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT7_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT7_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_OUTEN_STAT_OUTEN_STAT7_MASK) /*! @} */ /*! @name ATOM0_AGC_FUPD_CTRL - ATOM[i] AGC force update control register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL0_MASK (0x3U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL0_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL0_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL0_MASK) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL1_MASK (0xCU) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL1_SHIFT (2U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL1_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL1_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL1_MASK) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL2_MASK (0x30U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL2_SHIFT (4U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL2_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL2_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL2_MASK) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL3_MASK (0xC0U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL3_SHIFT (6U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL3_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL3_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL3_MASK) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL4_MASK (0x300U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL4_SHIFT (8U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL4_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL4_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL4_MASK) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL5_MASK (0xC00U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL5_SHIFT (10U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL5_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL5_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL5_MASK) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL6_MASK (0x3000U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL6_SHIFT (12U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL6_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL6_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL6_MASK) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL7_MASK (0xC000U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL7_SHIFT (14U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL7_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL7_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_FUPD_CTRL7_MASK) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH0_MASK (0x30000U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH0_SHIFT (16U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH0_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH0_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH0_MASK) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH1_MASK (0xC0000U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH1_SHIFT (18U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH1_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH1_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH1_MASK) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH2_MASK (0x300000U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH2_SHIFT (20U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH2_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH2_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH2_MASK) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH3_MASK (0xC00000U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH3_SHIFT (22U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH3_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH3_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH3_MASK) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH4_MASK (0x3000000U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH4_SHIFT (24U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH4_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH4_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH4_MASK) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH5_MASK (0xC000000U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH5_SHIFT (26U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH5_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH5_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH5_MASK) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH6_MASK (0x30000000U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH6_SHIFT (28U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH6_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH6_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH6_MASK) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH7_MASK (0xC0000000U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH7_SHIFT (30U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH7_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH7_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_FUPD_CTRL_RSTCN0_CH7_MASK) /*! @} */ /*! @name ATOM0_AGC_INT_TRIG - ATOM[i] AGC internal trigger control register */ /*! @{ */ #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG0_MASK (0x3U) #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG0_SHIFT (0U) #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG0_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG0_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG0_MASK) #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG1_MASK (0xCU) #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG1_SHIFT (2U) #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG1_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG1_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG1_MASK) #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG2_MASK (0x30U) #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG2_SHIFT (4U) #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG2_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG2_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG2_MASK) #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG3_MASK (0xC0U) #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG3_SHIFT (6U) #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG3_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG3_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG3_MASK) #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG4_MASK (0x300U) #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG4_SHIFT (8U) #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG4_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG4_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG4_MASK) #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG5_MASK (0xC00U) #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG5_SHIFT (10U) #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG5_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG5_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG5_MASK) #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG6_MASK (0x3000U) #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG6_SHIFT (12U) #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG6_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG6_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG6_MASK) #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG7_MASK (0xC000U) #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG7_SHIFT (14U) #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG7_WIDTH (2U) #define GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG7_SHIFT)) & GTM_gtm_cls0_ATOM0_AGC_INT_TRIG_INT_TRIG7_MASK) /*! @} */ /*! @name MCS0_CH0_R0 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH0_R0_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH0_R0_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH0_R0_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH0_R0_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_R0_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_R0_DATA_MASK) /*! @} */ /*! @name MCS0_CH0_R1 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH0_R1_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH0_R1_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH0_R1_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH0_R1_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_R1_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_R1_DATA_MASK) /*! @} */ /*! @name MCS0_CH0_R2 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH0_R2_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH0_R2_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH0_R2_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH0_R2_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_R2_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_R2_DATA_MASK) /*! @} */ /*! @name MCS0_CH0_R3 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH0_R3_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH0_R3_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH0_R3_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH0_R3_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_R3_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_R3_DATA_MASK) /*! @} */ /*! @name MCS0_CH0_R4 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH0_R4_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH0_R4_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH0_R4_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH0_R4_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_R4_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_R4_DATA_MASK) /*! @} */ /*! @name MCS0_CH0_R5 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH0_R5_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH0_R5_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH0_R5_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH0_R5_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_R5_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_R5_DATA_MASK) /*! @} */ /*! @name MCS0_CH0_R6 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH0_R6_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH0_R6_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH0_R6_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH0_R6_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_R6_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_R6_DATA_MASK) /*! @} */ /*! @name MCS0_CH0_R7 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH0_R7_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH0_R7_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH0_R7_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH0_R7_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_R7_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_R7_DATA_MASK) /*! @} */ /*! @name MCS0_CH0_CTRL - MCS[i] channel x control register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH0_CTRL_EN_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH0_CTRL_EN_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH0_CTRL_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH0_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_CTRL_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_CTRL_EN_MASK) #define GTM_gtm_cls0_MCS0_CH0_CTRL_IRQ_MASK (0x2U) #define GTM_gtm_cls0_MCS0_CH0_CTRL_IRQ_SHIFT (1U) #define GTM_gtm_cls0_MCS0_CH0_CTRL_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH0_CTRL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_CTRL_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_CTRL_IRQ_MASK) #define GTM_gtm_cls0_MCS0_CH0_CTRL_ERR_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH0_CTRL_ERR_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH0_CTRL_ERR_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH0_CTRL_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_CTRL_ERR_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_CTRL_ERR_MASK) #define GTM_gtm_cls0_MCS0_CH0_CTRL_CY_MASK (0x10U) #define GTM_gtm_cls0_MCS0_CH0_CTRL_CY_SHIFT (4U) #define GTM_gtm_cls0_MCS0_CH0_CTRL_CY_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH0_CTRL_CY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_CTRL_CY_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_CTRL_CY_MASK) #define GTM_gtm_cls0_MCS0_CH0_CTRL_Z_MASK (0x20U) #define GTM_gtm_cls0_MCS0_CH0_CTRL_Z_SHIFT (5U) #define GTM_gtm_cls0_MCS0_CH0_CTRL_Z_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH0_CTRL_Z(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_CTRL_Z_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_CTRL_Z_MASK) #define GTM_gtm_cls0_MCS0_CH0_CTRL_V_MASK (0x40U) #define GTM_gtm_cls0_MCS0_CH0_CTRL_V_SHIFT (6U) #define GTM_gtm_cls0_MCS0_CH0_CTRL_V_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH0_CTRL_V(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_CTRL_V_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_CTRL_V_MASK) #define GTM_gtm_cls0_MCS0_CH0_CTRL_N_MASK (0x80U) #define GTM_gtm_cls0_MCS0_CH0_CTRL_N_SHIFT (7U) #define GTM_gtm_cls0_MCS0_CH0_CTRL_N_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH0_CTRL_N(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_CTRL_N_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_CTRL_N_MASK) #define GTM_gtm_cls0_MCS0_CH0_CTRL_CAT_MASK (0x100U) #define GTM_gtm_cls0_MCS0_CH0_CTRL_CAT_SHIFT (8U) #define GTM_gtm_cls0_MCS0_CH0_CTRL_CAT_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH0_CTRL_CAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_CTRL_CAT_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_CTRL_CAT_MASK) #define GTM_gtm_cls0_MCS0_CH0_CTRL_CWT_MASK (0x200U) #define GTM_gtm_cls0_MCS0_CH0_CTRL_CWT_SHIFT (9U) #define GTM_gtm_cls0_MCS0_CH0_CTRL_CWT_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH0_CTRL_CWT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_CTRL_CWT_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_CTRL_CWT_MASK) #define GTM_gtm_cls0_MCS0_CH0_CTRL_SAT_MASK (0x400U) #define GTM_gtm_cls0_MCS0_CH0_CTRL_SAT_SHIFT (10U) #define GTM_gtm_cls0_MCS0_CH0_CTRL_SAT_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH0_CTRL_SAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_CTRL_SAT_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_CTRL_SAT_MASK) /*! @} */ /*! @name MCS0_CH0_ACB - MCS[i] channel x ARU control Bit register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH0_ACB_ACB0_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH0_ACB_ACB0_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH0_ACB_ACB0_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH0_ACB_ACB0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_ACB_ACB0_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_ACB_ACB0_MASK) #define GTM_gtm_cls0_MCS0_CH0_ACB_ACB1_MASK (0x2U) #define GTM_gtm_cls0_MCS0_CH0_ACB_ACB1_SHIFT (1U) #define GTM_gtm_cls0_MCS0_CH0_ACB_ACB1_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH0_ACB_ACB1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_ACB_ACB1_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_ACB_ACB1_MASK) #define GTM_gtm_cls0_MCS0_CH0_ACB_ACB2_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH0_ACB_ACB2_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH0_ACB_ACB2_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH0_ACB_ACB2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_ACB_ACB2_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_ACB_ACB2_MASK) #define GTM_gtm_cls0_MCS0_CH0_ACB_ACB3_MASK (0x8U) #define GTM_gtm_cls0_MCS0_CH0_ACB_ACB3_SHIFT (3U) #define GTM_gtm_cls0_MCS0_CH0_ACB_ACB3_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH0_ACB_ACB3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_ACB_ACB3_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_ACB_ACB3_MASK) #define GTM_gtm_cls0_MCS0_CH0_ACB_ACB4_MASK (0x10U) #define GTM_gtm_cls0_MCS0_CH0_ACB_ACB4_SHIFT (4U) #define GTM_gtm_cls0_MCS0_CH0_ACB_ACB4_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH0_ACB_ACB4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_ACB_ACB4_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_ACB_ACB4_MASK) /*! @} */ /*! @name MCS0_CH0_MHB - MCS[i] channel x memory high byte register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH0_MHB_DATA_MASK (0xFFU) #define GTM_gtm_cls0_MCS0_CH0_MHB_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH0_MHB_DATA_WIDTH (8U) #define GTM_gtm_cls0_MCS0_CH0_MHB_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_MHB_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_MHB_DATA_MASK) /*! @} */ /*! @name MCS0_CH0_PC - MCS[i] channel x program counter register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH0_PC_PC_MASK (0xFFFFU) #define GTM_gtm_cls0_MCS0_CH0_PC_PC_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH0_PC_PC_WIDTH (16U) #define GTM_gtm_cls0_MCS0_CH0_PC_PC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_PC_PC_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_PC_PC_MASK) /*! @} */ /*! @name MCS0_CH0_IRQ_NOTIFY - MCS[i] channel x interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH0_IRQ_NOTIFY_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH0_IRQ_NOTIFY_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH0_IRQ_NOTIFY_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH0_IRQ_NOTIFY_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_IRQ_NOTIFY_MCS_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_IRQ_NOTIFY_MCS_IRQ_MASK) #define GTM_gtm_cls0_MCS0_CH0_IRQ_NOTIFY_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH0_IRQ_NOTIFY_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH0_IRQ_NOTIFY_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH0_IRQ_NOTIFY_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_IRQ_NOTIFY_ERR_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_IRQ_NOTIFY_ERR_IRQ_MASK) /*! @} */ /*! @name MCS0_CH0_IRQ_EN - MCS[i] channel x interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH0_IRQ_EN_MCS_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH0_IRQ_EN_MCS_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH0_IRQ_EN_MCS_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH0_IRQ_EN_MCS_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_IRQ_EN_MCS_IRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_IRQ_EN_MCS_IRQ_EN_MASK) #define GTM_gtm_cls0_MCS0_CH0_IRQ_EN_ERR_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH0_IRQ_EN_ERR_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH0_IRQ_EN_ERR_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH0_IRQ_EN_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_IRQ_EN_ERR_IRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_IRQ_EN_ERR_IRQ_EN_MASK) /*! @} */ /*! @name MCS0_CH0_IRQ_FORCINT - MCS[i] channel x force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH0_IRQ_FORCINT_TRG_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH0_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH0_IRQ_FORCINT_TRG_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH0_IRQ_FORCINT_TRG_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_IRQ_FORCINT_TRG_MCS_IRQ_MASK) #define GTM_gtm_cls0_MCS0_CH0_IRQ_FORCINT_TRG_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH0_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH0_IRQ_FORCINT_TRG_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH0_IRQ_FORCINT_TRG_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_IRQ_FORCINT_TRG_ERR_IRQ_MASK) /*! @} */ /*! @name MCS0_CH0_IRQ_MODE - MCS[i] channel x IRQ mode configuration register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH0_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_MCS0_CH0_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH0_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_MCS0_CH0_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name MCS0_CH0_EIRQ_EN - MCS[i] channel x error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH0_EIRQ_EN_MCS_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH0_EIRQ_EN_MCS_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH0_EIRQ_EN_MCS_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH0_EIRQ_EN_MCS_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_EIRQ_EN_MCS_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_EIRQ_EN_MCS_EIRQ_EN_MASK) #define GTM_gtm_cls0_MCS0_CH0_EIRQ_EN_ERR_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH0_EIRQ_EN_ERR_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH0_EIRQ_EN_ERR_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH0_EIRQ_EN_ERR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH0_EIRQ_EN_ERR_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH0_EIRQ_EN_ERR_EIRQ_EN_MASK) /*! @} */ /*! @name MCS0_CH1_R0 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH1_R0_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH1_R0_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH1_R0_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH1_R0_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_R0_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_R0_DATA_MASK) /*! @} */ /*! @name MCS0_CH1_R1 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH1_R1_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH1_R1_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH1_R1_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH1_R1_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_R1_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_R1_DATA_MASK) /*! @} */ /*! @name MCS0_CH1_R2 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH1_R2_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH1_R2_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH1_R2_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH1_R2_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_R2_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_R2_DATA_MASK) /*! @} */ /*! @name MCS0_CH1_R3 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH1_R3_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH1_R3_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH1_R3_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH1_R3_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_R3_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_R3_DATA_MASK) /*! @} */ /*! @name MCS0_CH1_R4 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH1_R4_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH1_R4_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH1_R4_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH1_R4_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_R4_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_R4_DATA_MASK) /*! @} */ /*! @name MCS0_CH1_R5 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH1_R5_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH1_R5_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH1_R5_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH1_R5_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_R5_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_R5_DATA_MASK) /*! @} */ /*! @name MCS0_CH1_R6 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH1_R6_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH1_R6_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH1_R6_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH1_R6_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_R6_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_R6_DATA_MASK) /*! @} */ /*! @name MCS0_CH1_R7 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH1_R7_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH1_R7_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH1_R7_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH1_R7_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_R7_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_R7_DATA_MASK) /*! @} */ /*! @name MCS0_CH1_CTRL - MCS[i] channel x control register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH1_CTRL_EN_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH1_CTRL_EN_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH1_CTRL_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH1_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_CTRL_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_CTRL_EN_MASK) #define GTM_gtm_cls0_MCS0_CH1_CTRL_IRQ_MASK (0x2U) #define GTM_gtm_cls0_MCS0_CH1_CTRL_IRQ_SHIFT (1U) #define GTM_gtm_cls0_MCS0_CH1_CTRL_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH1_CTRL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_CTRL_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_CTRL_IRQ_MASK) #define GTM_gtm_cls0_MCS0_CH1_CTRL_ERR_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH1_CTRL_ERR_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH1_CTRL_ERR_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH1_CTRL_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_CTRL_ERR_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_CTRL_ERR_MASK) #define GTM_gtm_cls0_MCS0_CH1_CTRL_CY_MASK (0x10U) #define GTM_gtm_cls0_MCS0_CH1_CTRL_CY_SHIFT (4U) #define GTM_gtm_cls0_MCS0_CH1_CTRL_CY_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH1_CTRL_CY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_CTRL_CY_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_CTRL_CY_MASK) #define GTM_gtm_cls0_MCS0_CH1_CTRL_Z_MASK (0x20U) #define GTM_gtm_cls0_MCS0_CH1_CTRL_Z_SHIFT (5U) #define GTM_gtm_cls0_MCS0_CH1_CTRL_Z_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH1_CTRL_Z(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_CTRL_Z_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_CTRL_Z_MASK) #define GTM_gtm_cls0_MCS0_CH1_CTRL_V_MASK (0x40U) #define GTM_gtm_cls0_MCS0_CH1_CTRL_V_SHIFT (6U) #define GTM_gtm_cls0_MCS0_CH1_CTRL_V_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH1_CTRL_V(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_CTRL_V_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_CTRL_V_MASK) #define GTM_gtm_cls0_MCS0_CH1_CTRL_N_MASK (0x80U) #define GTM_gtm_cls0_MCS0_CH1_CTRL_N_SHIFT (7U) #define GTM_gtm_cls0_MCS0_CH1_CTRL_N_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH1_CTRL_N(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_CTRL_N_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_CTRL_N_MASK) #define GTM_gtm_cls0_MCS0_CH1_CTRL_CAT_MASK (0x100U) #define GTM_gtm_cls0_MCS0_CH1_CTRL_CAT_SHIFT (8U) #define GTM_gtm_cls0_MCS0_CH1_CTRL_CAT_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH1_CTRL_CAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_CTRL_CAT_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_CTRL_CAT_MASK) #define GTM_gtm_cls0_MCS0_CH1_CTRL_CWT_MASK (0x200U) #define GTM_gtm_cls0_MCS0_CH1_CTRL_CWT_SHIFT (9U) #define GTM_gtm_cls0_MCS0_CH1_CTRL_CWT_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH1_CTRL_CWT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_CTRL_CWT_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_CTRL_CWT_MASK) #define GTM_gtm_cls0_MCS0_CH1_CTRL_SAT_MASK (0x400U) #define GTM_gtm_cls0_MCS0_CH1_CTRL_SAT_SHIFT (10U) #define GTM_gtm_cls0_MCS0_CH1_CTRL_SAT_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH1_CTRL_SAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_CTRL_SAT_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_CTRL_SAT_MASK) /*! @} */ /*! @name MCS0_CH1_ACB - MCS[i] channel x ARU control Bit register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH1_ACB_ACB0_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH1_ACB_ACB0_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH1_ACB_ACB0_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH1_ACB_ACB0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_ACB_ACB0_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_ACB_ACB0_MASK) #define GTM_gtm_cls0_MCS0_CH1_ACB_ACB1_MASK (0x2U) #define GTM_gtm_cls0_MCS0_CH1_ACB_ACB1_SHIFT (1U) #define GTM_gtm_cls0_MCS0_CH1_ACB_ACB1_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH1_ACB_ACB1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_ACB_ACB1_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_ACB_ACB1_MASK) #define GTM_gtm_cls0_MCS0_CH1_ACB_ACB2_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH1_ACB_ACB2_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH1_ACB_ACB2_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH1_ACB_ACB2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_ACB_ACB2_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_ACB_ACB2_MASK) #define GTM_gtm_cls0_MCS0_CH1_ACB_ACB3_MASK (0x8U) #define GTM_gtm_cls0_MCS0_CH1_ACB_ACB3_SHIFT (3U) #define GTM_gtm_cls0_MCS0_CH1_ACB_ACB3_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH1_ACB_ACB3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_ACB_ACB3_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_ACB_ACB3_MASK) #define GTM_gtm_cls0_MCS0_CH1_ACB_ACB4_MASK (0x10U) #define GTM_gtm_cls0_MCS0_CH1_ACB_ACB4_SHIFT (4U) #define GTM_gtm_cls0_MCS0_CH1_ACB_ACB4_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH1_ACB_ACB4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_ACB_ACB4_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_ACB_ACB4_MASK) /*! @} */ /*! @name MCS0_CH1_MHB - MCS[i] channel x memory high byte register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH1_MHB_DATA_MASK (0xFFU) #define GTM_gtm_cls0_MCS0_CH1_MHB_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH1_MHB_DATA_WIDTH (8U) #define GTM_gtm_cls0_MCS0_CH1_MHB_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_MHB_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_MHB_DATA_MASK) /*! @} */ /*! @name MCS0_CH1_PC - MCS[i] channel x program counter register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH1_PC_PC_MASK (0xFFFFU) #define GTM_gtm_cls0_MCS0_CH1_PC_PC_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH1_PC_PC_WIDTH (16U) #define GTM_gtm_cls0_MCS0_CH1_PC_PC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_PC_PC_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_PC_PC_MASK) /*! @} */ /*! @name MCS0_CH1_IRQ_NOTIFY - MCS[i] channel x interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH1_IRQ_NOTIFY_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH1_IRQ_NOTIFY_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH1_IRQ_NOTIFY_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH1_IRQ_NOTIFY_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_IRQ_NOTIFY_MCS_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_IRQ_NOTIFY_MCS_IRQ_MASK) #define GTM_gtm_cls0_MCS0_CH1_IRQ_NOTIFY_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH1_IRQ_NOTIFY_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH1_IRQ_NOTIFY_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH1_IRQ_NOTIFY_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_IRQ_NOTIFY_ERR_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_IRQ_NOTIFY_ERR_IRQ_MASK) /*! @} */ /*! @name MCS0_CH1_IRQ_EN - MCS[i] channel x interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH1_IRQ_EN_MCS_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH1_IRQ_EN_MCS_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH1_IRQ_EN_MCS_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH1_IRQ_EN_MCS_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_IRQ_EN_MCS_IRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_IRQ_EN_MCS_IRQ_EN_MASK) #define GTM_gtm_cls0_MCS0_CH1_IRQ_EN_ERR_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH1_IRQ_EN_ERR_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH1_IRQ_EN_ERR_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH1_IRQ_EN_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_IRQ_EN_ERR_IRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_IRQ_EN_ERR_IRQ_EN_MASK) /*! @} */ /*! @name MCS0_CH1_IRQ_FORCINT - MCS[i] channel x force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH1_IRQ_FORCINT_TRG_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH1_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH1_IRQ_FORCINT_TRG_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH1_IRQ_FORCINT_TRG_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_IRQ_FORCINT_TRG_MCS_IRQ_MASK) #define GTM_gtm_cls0_MCS0_CH1_IRQ_FORCINT_TRG_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH1_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH1_IRQ_FORCINT_TRG_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH1_IRQ_FORCINT_TRG_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_IRQ_FORCINT_TRG_ERR_IRQ_MASK) /*! @} */ /*! @name MCS0_CH1_IRQ_MODE - MCS[i] channel x IRQ mode configuration register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH1_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_MCS0_CH1_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH1_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_MCS0_CH1_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name MCS0_CH1_EIRQ_EN - MCS[i] channel x error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH1_EIRQ_EN_MCS_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH1_EIRQ_EN_MCS_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH1_EIRQ_EN_MCS_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH1_EIRQ_EN_MCS_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_EIRQ_EN_MCS_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_EIRQ_EN_MCS_EIRQ_EN_MASK) #define GTM_gtm_cls0_MCS0_CH1_EIRQ_EN_ERR_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH1_EIRQ_EN_ERR_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH1_EIRQ_EN_ERR_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH1_EIRQ_EN_ERR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH1_EIRQ_EN_ERR_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH1_EIRQ_EN_ERR_EIRQ_EN_MASK) /*! @} */ /*! @name MCS0_CH2_R0 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH2_R0_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH2_R0_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH2_R0_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH2_R0_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_R0_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_R0_DATA_MASK) /*! @} */ /*! @name MCS0_CH2_R1 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH2_R1_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH2_R1_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH2_R1_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH2_R1_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_R1_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_R1_DATA_MASK) /*! @} */ /*! @name MCS0_CH2_R2 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH2_R2_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH2_R2_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH2_R2_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH2_R2_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_R2_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_R2_DATA_MASK) /*! @} */ /*! @name MCS0_CH2_R3 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH2_R3_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH2_R3_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH2_R3_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH2_R3_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_R3_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_R3_DATA_MASK) /*! @} */ /*! @name MCS0_CH2_R4 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH2_R4_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH2_R4_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH2_R4_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH2_R4_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_R4_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_R4_DATA_MASK) /*! @} */ /*! @name MCS0_CH2_R5 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH2_R5_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH2_R5_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH2_R5_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH2_R5_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_R5_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_R5_DATA_MASK) /*! @} */ /*! @name MCS0_CH2_R6 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH2_R6_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH2_R6_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH2_R6_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH2_R6_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_R6_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_R6_DATA_MASK) /*! @} */ /*! @name MCS0_CH2_R7 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH2_R7_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH2_R7_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH2_R7_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH2_R7_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_R7_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_R7_DATA_MASK) /*! @} */ /*! @name MCS0_CH2_CTRL - MCS[i] channel x control register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH2_CTRL_EN_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH2_CTRL_EN_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH2_CTRL_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH2_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_CTRL_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_CTRL_EN_MASK) #define GTM_gtm_cls0_MCS0_CH2_CTRL_IRQ_MASK (0x2U) #define GTM_gtm_cls0_MCS0_CH2_CTRL_IRQ_SHIFT (1U) #define GTM_gtm_cls0_MCS0_CH2_CTRL_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH2_CTRL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_CTRL_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_CTRL_IRQ_MASK) #define GTM_gtm_cls0_MCS0_CH2_CTRL_ERR_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH2_CTRL_ERR_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH2_CTRL_ERR_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH2_CTRL_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_CTRL_ERR_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_CTRL_ERR_MASK) #define GTM_gtm_cls0_MCS0_CH2_CTRL_CY_MASK (0x10U) #define GTM_gtm_cls0_MCS0_CH2_CTRL_CY_SHIFT (4U) #define GTM_gtm_cls0_MCS0_CH2_CTRL_CY_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH2_CTRL_CY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_CTRL_CY_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_CTRL_CY_MASK) #define GTM_gtm_cls0_MCS0_CH2_CTRL_Z_MASK (0x20U) #define GTM_gtm_cls0_MCS0_CH2_CTRL_Z_SHIFT (5U) #define GTM_gtm_cls0_MCS0_CH2_CTRL_Z_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH2_CTRL_Z(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_CTRL_Z_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_CTRL_Z_MASK) #define GTM_gtm_cls0_MCS0_CH2_CTRL_V_MASK (0x40U) #define GTM_gtm_cls0_MCS0_CH2_CTRL_V_SHIFT (6U) #define GTM_gtm_cls0_MCS0_CH2_CTRL_V_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH2_CTRL_V(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_CTRL_V_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_CTRL_V_MASK) #define GTM_gtm_cls0_MCS0_CH2_CTRL_N_MASK (0x80U) #define GTM_gtm_cls0_MCS0_CH2_CTRL_N_SHIFT (7U) #define GTM_gtm_cls0_MCS0_CH2_CTRL_N_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH2_CTRL_N(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_CTRL_N_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_CTRL_N_MASK) #define GTM_gtm_cls0_MCS0_CH2_CTRL_CAT_MASK (0x100U) #define GTM_gtm_cls0_MCS0_CH2_CTRL_CAT_SHIFT (8U) #define GTM_gtm_cls0_MCS0_CH2_CTRL_CAT_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH2_CTRL_CAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_CTRL_CAT_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_CTRL_CAT_MASK) #define GTM_gtm_cls0_MCS0_CH2_CTRL_CWT_MASK (0x200U) #define GTM_gtm_cls0_MCS0_CH2_CTRL_CWT_SHIFT (9U) #define GTM_gtm_cls0_MCS0_CH2_CTRL_CWT_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH2_CTRL_CWT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_CTRL_CWT_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_CTRL_CWT_MASK) #define GTM_gtm_cls0_MCS0_CH2_CTRL_SAT_MASK (0x400U) #define GTM_gtm_cls0_MCS0_CH2_CTRL_SAT_SHIFT (10U) #define GTM_gtm_cls0_MCS0_CH2_CTRL_SAT_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH2_CTRL_SAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_CTRL_SAT_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_CTRL_SAT_MASK) /*! @} */ /*! @name MCS0_CH2_ACB - MCS[i] channel x ARU control Bit register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH2_ACB_ACB0_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH2_ACB_ACB0_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH2_ACB_ACB0_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH2_ACB_ACB0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_ACB_ACB0_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_ACB_ACB0_MASK) #define GTM_gtm_cls0_MCS0_CH2_ACB_ACB1_MASK (0x2U) #define GTM_gtm_cls0_MCS0_CH2_ACB_ACB1_SHIFT (1U) #define GTM_gtm_cls0_MCS0_CH2_ACB_ACB1_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH2_ACB_ACB1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_ACB_ACB1_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_ACB_ACB1_MASK) #define GTM_gtm_cls0_MCS0_CH2_ACB_ACB2_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH2_ACB_ACB2_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH2_ACB_ACB2_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH2_ACB_ACB2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_ACB_ACB2_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_ACB_ACB2_MASK) #define GTM_gtm_cls0_MCS0_CH2_ACB_ACB3_MASK (0x8U) #define GTM_gtm_cls0_MCS0_CH2_ACB_ACB3_SHIFT (3U) #define GTM_gtm_cls0_MCS0_CH2_ACB_ACB3_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH2_ACB_ACB3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_ACB_ACB3_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_ACB_ACB3_MASK) #define GTM_gtm_cls0_MCS0_CH2_ACB_ACB4_MASK (0x10U) #define GTM_gtm_cls0_MCS0_CH2_ACB_ACB4_SHIFT (4U) #define GTM_gtm_cls0_MCS0_CH2_ACB_ACB4_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH2_ACB_ACB4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_ACB_ACB4_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_ACB_ACB4_MASK) /*! @} */ /*! @name MCS0_CH2_MHB - MCS[i] channel x memory high byte register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH2_MHB_DATA_MASK (0xFFU) #define GTM_gtm_cls0_MCS0_CH2_MHB_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH2_MHB_DATA_WIDTH (8U) #define GTM_gtm_cls0_MCS0_CH2_MHB_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_MHB_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_MHB_DATA_MASK) /*! @} */ /*! @name MCS0_CH2_PC - MCS[i] channel x program counter register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH2_PC_PC_MASK (0xFFFFU) #define GTM_gtm_cls0_MCS0_CH2_PC_PC_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH2_PC_PC_WIDTH (16U) #define GTM_gtm_cls0_MCS0_CH2_PC_PC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_PC_PC_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_PC_PC_MASK) /*! @} */ /*! @name MCS0_CH2_IRQ_NOTIFY - MCS[i] channel x interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH2_IRQ_NOTIFY_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH2_IRQ_NOTIFY_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH2_IRQ_NOTIFY_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH2_IRQ_NOTIFY_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_IRQ_NOTIFY_MCS_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_IRQ_NOTIFY_MCS_IRQ_MASK) #define GTM_gtm_cls0_MCS0_CH2_IRQ_NOTIFY_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH2_IRQ_NOTIFY_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH2_IRQ_NOTIFY_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH2_IRQ_NOTIFY_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_IRQ_NOTIFY_ERR_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_IRQ_NOTIFY_ERR_IRQ_MASK) /*! @} */ /*! @name MCS0_CH2_IRQ_EN - MCS[i] channel x interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH2_IRQ_EN_MCS_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH2_IRQ_EN_MCS_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH2_IRQ_EN_MCS_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH2_IRQ_EN_MCS_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_IRQ_EN_MCS_IRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_IRQ_EN_MCS_IRQ_EN_MASK) #define GTM_gtm_cls0_MCS0_CH2_IRQ_EN_ERR_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH2_IRQ_EN_ERR_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH2_IRQ_EN_ERR_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH2_IRQ_EN_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_IRQ_EN_ERR_IRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_IRQ_EN_ERR_IRQ_EN_MASK) /*! @} */ /*! @name MCS0_CH2_IRQ_FORCINT - MCS[i] channel x force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH2_IRQ_FORCINT_TRG_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH2_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH2_IRQ_FORCINT_TRG_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH2_IRQ_FORCINT_TRG_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_IRQ_FORCINT_TRG_MCS_IRQ_MASK) #define GTM_gtm_cls0_MCS0_CH2_IRQ_FORCINT_TRG_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH2_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH2_IRQ_FORCINT_TRG_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH2_IRQ_FORCINT_TRG_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_IRQ_FORCINT_TRG_ERR_IRQ_MASK) /*! @} */ /*! @name MCS0_CH2_IRQ_MODE - MCS[i] channel x IRQ mode configuration register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH2_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_MCS0_CH2_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH2_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_MCS0_CH2_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name MCS0_CH2_EIRQ_EN - MCS[i] channel x error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH2_EIRQ_EN_MCS_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH2_EIRQ_EN_MCS_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH2_EIRQ_EN_MCS_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH2_EIRQ_EN_MCS_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_EIRQ_EN_MCS_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_EIRQ_EN_MCS_EIRQ_EN_MASK) #define GTM_gtm_cls0_MCS0_CH2_EIRQ_EN_ERR_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH2_EIRQ_EN_ERR_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH2_EIRQ_EN_ERR_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH2_EIRQ_EN_ERR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH2_EIRQ_EN_ERR_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH2_EIRQ_EN_ERR_EIRQ_EN_MASK) /*! @} */ /*! @name MCS0_CH3_R0 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH3_R0_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH3_R0_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH3_R0_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH3_R0_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_R0_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_R0_DATA_MASK) /*! @} */ /*! @name MCS0_CH3_R1 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH3_R1_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH3_R1_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH3_R1_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH3_R1_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_R1_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_R1_DATA_MASK) /*! @} */ /*! @name MCS0_CH3_R2 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH3_R2_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH3_R2_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH3_R2_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH3_R2_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_R2_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_R2_DATA_MASK) /*! @} */ /*! @name MCS0_CH3_R3 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH3_R3_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH3_R3_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH3_R3_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH3_R3_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_R3_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_R3_DATA_MASK) /*! @} */ /*! @name MCS0_CH3_R4 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH3_R4_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH3_R4_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH3_R4_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH3_R4_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_R4_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_R4_DATA_MASK) /*! @} */ /*! @name MCS0_CH3_R5 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH3_R5_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH3_R5_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH3_R5_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH3_R5_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_R5_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_R5_DATA_MASK) /*! @} */ /*! @name MCS0_CH3_R6 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH3_R6_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH3_R6_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH3_R6_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH3_R6_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_R6_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_R6_DATA_MASK) /*! @} */ /*! @name MCS0_CH3_R7 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH3_R7_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH3_R7_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH3_R7_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH3_R7_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_R7_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_R7_DATA_MASK) /*! @} */ /*! @name MCS0_CH3_CTRL - MCS[i] channel x control register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH3_CTRL_EN_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH3_CTRL_EN_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH3_CTRL_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH3_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_CTRL_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_CTRL_EN_MASK) #define GTM_gtm_cls0_MCS0_CH3_CTRL_IRQ_MASK (0x2U) #define GTM_gtm_cls0_MCS0_CH3_CTRL_IRQ_SHIFT (1U) #define GTM_gtm_cls0_MCS0_CH3_CTRL_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH3_CTRL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_CTRL_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_CTRL_IRQ_MASK) #define GTM_gtm_cls0_MCS0_CH3_CTRL_ERR_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH3_CTRL_ERR_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH3_CTRL_ERR_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH3_CTRL_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_CTRL_ERR_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_CTRL_ERR_MASK) #define GTM_gtm_cls0_MCS0_CH3_CTRL_CY_MASK (0x10U) #define GTM_gtm_cls0_MCS0_CH3_CTRL_CY_SHIFT (4U) #define GTM_gtm_cls0_MCS0_CH3_CTRL_CY_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH3_CTRL_CY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_CTRL_CY_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_CTRL_CY_MASK) #define GTM_gtm_cls0_MCS0_CH3_CTRL_Z_MASK (0x20U) #define GTM_gtm_cls0_MCS0_CH3_CTRL_Z_SHIFT (5U) #define GTM_gtm_cls0_MCS0_CH3_CTRL_Z_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH3_CTRL_Z(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_CTRL_Z_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_CTRL_Z_MASK) #define GTM_gtm_cls0_MCS0_CH3_CTRL_V_MASK (0x40U) #define GTM_gtm_cls0_MCS0_CH3_CTRL_V_SHIFT (6U) #define GTM_gtm_cls0_MCS0_CH3_CTRL_V_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH3_CTRL_V(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_CTRL_V_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_CTRL_V_MASK) #define GTM_gtm_cls0_MCS0_CH3_CTRL_N_MASK (0x80U) #define GTM_gtm_cls0_MCS0_CH3_CTRL_N_SHIFT (7U) #define GTM_gtm_cls0_MCS0_CH3_CTRL_N_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH3_CTRL_N(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_CTRL_N_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_CTRL_N_MASK) #define GTM_gtm_cls0_MCS0_CH3_CTRL_CAT_MASK (0x100U) #define GTM_gtm_cls0_MCS0_CH3_CTRL_CAT_SHIFT (8U) #define GTM_gtm_cls0_MCS0_CH3_CTRL_CAT_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH3_CTRL_CAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_CTRL_CAT_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_CTRL_CAT_MASK) #define GTM_gtm_cls0_MCS0_CH3_CTRL_CWT_MASK (0x200U) #define GTM_gtm_cls0_MCS0_CH3_CTRL_CWT_SHIFT (9U) #define GTM_gtm_cls0_MCS0_CH3_CTRL_CWT_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH3_CTRL_CWT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_CTRL_CWT_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_CTRL_CWT_MASK) #define GTM_gtm_cls0_MCS0_CH3_CTRL_SAT_MASK (0x400U) #define GTM_gtm_cls0_MCS0_CH3_CTRL_SAT_SHIFT (10U) #define GTM_gtm_cls0_MCS0_CH3_CTRL_SAT_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH3_CTRL_SAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_CTRL_SAT_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_CTRL_SAT_MASK) /*! @} */ /*! @name MCS0_CH3_ACB - MCS[i] channel x ARU control Bit register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH3_ACB_ACB0_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH3_ACB_ACB0_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH3_ACB_ACB0_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH3_ACB_ACB0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_ACB_ACB0_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_ACB_ACB0_MASK) #define GTM_gtm_cls0_MCS0_CH3_ACB_ACB1_MASK (0x2U) #define GTM_gtm_cls0_MCS0_CH3_ACB_ACB1_SHIFT (1U) #define GTM_gtm_cls0_MCS0_CH3_ACB_ACB1_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH3_ACB_ACB1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_ACB_ACB1_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_ACB_ACB1_MASK) #define GTM_gtm_cls0_MCS0_CH3_ACB_ACB2_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH3_ACB_ACB2_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH3_ACB_ACB2_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH3_ACB_ACB2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_ACB_ACB2_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_ACB_ACB2_MASK) #define GTM_gtm_cls0_MCS0_CH3_ACB_ACB3_MASK (0x8U) #define GTM_gtm_cls0_MCS0_CH3_ACB_ACB3_SHIFT (3U) #define GTM_gtm_cls0_MCS0_CH3_ACB_ACB3_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH3_ACB_ACB3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_ACB_ACB3_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_ACB_ACB3_MASK) #define GTM_gtm_cls0_MCS0_CH3_ACB_ACB4_MASK (0x10U) #define GTM_gtm_cls0_MCS0_CH3_ACB_ACB4_SHIFT (4U) #define GTM_gtm_cls0_MCS0_CH3_ACB_ACB4_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH3_ACB_ACB4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_ACB_ACB4_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_ACB_ACB4_MASK) /*! @} */ /*! @name MCS0_CH3_MHB - MCS[i] channel x memory high byte register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH3_MHB_DATA_MASK (0xFFU) #define GTM_gtm_cls0_MCS0_CH3_MHB_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH3_MHB_DATA_WIDTH (8U) #define GTM_gtm_cls0_MCS0_CH3_MHB_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_MHB_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_MHB_DATA_MASK) /*! @} */ /*! @name MCS0_CH3_PC - MCS[i] channel x program counter register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH3_PC_PC_MASK (0xFFFFU) #define GTM_gtm_cls0_MCS0_CH3_PC_PC_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH3_PC_PC_WIDTH (16U) #define GTM_gtm_cls0_MCS0_CH3_PC_PC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_PC_PC_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_PC_PC_MASK) /*! @} */ /*! @name MCS0_CH3_IRQ_NOTIFY - MCS[i] channel x interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH3_IRQ_NOTIFY_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH3_IRQ_NOTIFY_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH3_IRQ_NOTIFY_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH3_IRQ_NOTIFY_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_IRQ_NOTIFY_MCS_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_IRQ_NOTIFY_MCS_IRQ_MASK) #define GTM_gtm_cls0_MCS0_CH3_IRQ_NOTIFY_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH3_IRQ_NOTIFY_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH3_IRQ_NOTIFY_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH3_IRQ_NOTIFY_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_IRQ_NOTIFY_ERR_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_IRQ_NOTIFY_ERR_IRQ_MASK) /*! @} */ /*! @name MCS0_CH3_IRQ_EN - MCS[i] channel x interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH3_IRQ_EN_MCS_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH3_IRQ_EN_MCS_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH3_IRQ_EN_MCS_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH3_IRQ_EN_MCS_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_IRQ_EN_MCS_IRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_IRQ_EN_MCS_IRQ_EN_MASK) #define GTM_gtm_cls0_MCS0_CH3_IRQ_EN_ERR_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH3_IRQ_EN_ERR_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH3_IRQ_EN_ERR_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH3_IRQ_EN_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_IRQ_EN_ERR_IRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_IRQ_EN_ERR_IRQ_EN_MASK) /*! @} */ /*! @name MCS0_CH3_IRQ_FORCINT - MCS[i] channel x force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH3_IRQ_FORCINT_TRG_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH3_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH3_IRQ_FORCINT_TRG_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH3_IRQ_FORCINT_TRG_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_IRQ_FORCINT_TRG_MCS_IRQ_MASK) #define GTM_gtm_cls0_MCS0_CH3_IRQ_FORCINT_TRG_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH3_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH3_IRQ_FORCINT_TRG_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH3_IRQ_FORCINT_TRG_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_IRQ_FORCINT_TRG_ERR_IRQ_MASK) /*! @} */ /*! @name MCS0_CH3_IRQ_MODE - MCS[i] channel x IRQ mode configuration register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH3_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_MCS0_CH3_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH3_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_MCS0_CH3_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name MCS0_CH3_EIRQ_EN - MCS[i] channel x error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH3_EIRQ_EN_MCS_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH3_EIRQ_EN_MCS_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH3_EIRQ_EN_MCS_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH3_EIRQ_EN_MCS_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_EIRQ_EN_MCS_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_EIRQ_EN_MCS_EIRQ_EN_MASK) #define GTM_gtm_cls0_MCS0_CH3_EIRQ_EN_ERR_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH3_EIRQ_EN_ERR_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH3_EIRQ_EN_ERR_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH3_EIRQ_EN_ERR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH3_EIRQ_EN_ERR_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH3_EIRQ_EN_ERR_EIRQ_EN_MASK) /*! @} */ /*! @name MCS0_CH4_R0 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH4_R0_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH4_R0_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH4_R0_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH4_R0_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_R0_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_R0_DATA_MASK) /*! @} */ /*! @name MCS0_CH4_R1 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH4_R1_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH4_R1_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH4_R1_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH4_R1_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_R1_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_R1_DATA_MASK) /*! @} */ /*! @name MCS0_CH4_R2 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH4_R2_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH4_R2_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH4_R2_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH4_R2_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_R2_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_R2_DATA_MASK) /*! @} */ /*! @name MCS0_CH4_R3 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH4_R3_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH4_R3_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH4_R3_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH4_R3_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_R3_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_R3_DATA_MASK) /*! @} */ /*! @name MCS0_CH4_R4 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH4_R4_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH4_R4_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH4_R4_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH4_R4_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_R4_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_R4_DATA_MASK) /*! @} */ /*! @name MCS0_CH4_R5 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH4_R5_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH4_R5_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH4_R5_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH4_R5_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_R5_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_R5_DATA_MASK) /*! @} */ /*! @name MCS0_CH4_R6 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH4_R6_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH4_R6_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH4_R6_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH4_R6_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_R6_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_R6_DATA_MASK) /*! @} */ /*! @name MCS0_CH4_R7 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH4_R7_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH4_R7_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH4_R7_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH4_R7_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_R7_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_R7_DATA_MASK) /*! @} */ /*! @name MCS0_CH4_CTRL - MCS[i] channel x control register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH4_CTRL_EN_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH4_CTRL_EN_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH4_CTRL_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH4_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_CTRL_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_CTRL_EN_MASK) #define GTM_gtm_cls0_MCS0_CH4_CTRL_IRQ_MASK (0x2U) #define GTM_gtm_cls0_MCS0_CH4_CTRL_IRQ_SHIFT (1U) #define GTM_gtm_cls0_MCS0_CH4_CTRL_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH4_CTRL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_CTRL_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_CTRL_IRQ_MASK) #define GTM_gtm_cls0_MCS0_CH4_CTRL_ERR_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH4_CTRL_ERR_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH4_CTRL_ERR_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH4_CTRL_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_CTRL_ERR_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_CTRL_ERR_MASK) #define GTM_gtm_cls0_MCS0_CH4_CTRL_CY_MASK (0x10U) #define GTM_gtm_cls0_MCS0_CH4_CTRL_CY_SHIFT (4U) #define GTM_gtm_cls0_MCS0_CH4_CTRL_CY_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH4_CTRL_CY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_CTRL_CY_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_CTRL_CY_MASK) #define GTM_gtm_cls0_MCS0_CH4_CTRL_Z_MASK (0x20U) #define GTM_gtm_cls0_MCS0_CH4_CTRL_Z_SHIFT (5U) #define GTM_gtm_cls0_MCS0_CH4_CTRL_Z_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH4_CTRL_Z(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_CTRL_Z_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_CTRL_Z_MASK) #define GTM_gtm_cls0_MCS0_CH4_CTRL_V_MASK (0x40U) #define GTM_gtm_cls0_MCS0_CH4_CTRL_V_SHIFT (6U) #define GTM_gtm_cls0_MCS0_CH4_CTRL_V_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH4_CTRL_V(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_CTRL_V_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_CTRL_V_MASK) #define GTM_gtm_cls0_MCS0_CH4_CTRL_N_MASK (0x80U) #define GTM_gtm_cls0_MCS0_CH4_CTRL_N_SHIFT (7U) #define GTM_gtm_cls0_MCS0_CH4_CTRL_N_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH4_CTRL_N(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_CTRL_N_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_CTRL_N_MASK) #define GTM_gtm_cls0_MCS0_CH4_CTRL_CAT_MASK (0x100U) #define GTM_gtm_cls0_MCS0_CH4_CTRL_CAT_SHIFT (8U) #define GTM_gtm_cls0_MCS0_CH4_CTRL_CAT_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH4_CTRL_CAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_CTRL_CAT_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_CTRL_CAT_MASK) #define GTM_gtm_cls0_MCS0_CH4_CTRL_CWT_MASK (0x200U) #define GTM_gtm_cls0_MCS0_CH4_CTRL_CWT_SHIFT (9U) #define GTM_gtm_cls0_MCS0_CH4_CTRL_CWT_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH4_CTRL_CWT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_CTRL_CWT_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_CTRL_CWT_MASK) #define GTM_gtm_cls0_MCS0_CH4_CTRL_SAT_MASK (0x400U) #define GTM_gtm_cls0_MCS0_CH4_CTRL_SAT_SHIFT (10U) #define GTM_gtm_cls0_MCS0_CH4_CTRL_SAT_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH4_CTRL_SAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_CTRL_SAT_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_CTRL_SAT_MASK) /*! @} */ /*! @name MCS0_CH4_ACB - MCS[i] channel x ARU control Bit register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH4_ACB_ACB0_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH4_ACB_ACB0_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH4_ACB_ACB0_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH4_ACB_ACB0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_ACB_ACB0_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_ACB_ACB0_MASK) #define GTM_gtm_cls0_MCS0_CH4_ACB_ACB1_MASK (0x2U) #define GTM_gtm_cls0_MCS0_CH4_ACB_ACB1_SHIFT (1U) #define GTM_gtm_cls0_MCS0_CH4_ACB_ACB1_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH4_ACB_ACB1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_ACB_ACB1_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_ACB_ACB1_MASK) #define GTM_gtm_cls0_MCS0_CH4_ACB_ACB2_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH4_ACB_ACB2_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH4_ACB_ACB2_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH4_ACB_ACB2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_ACB_ACB2_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_ACB_ACB2_MASK) #define GTM_gtm_cls0_MCS0_CH4_ACB_ACB3_MASK (0x8U) #define GTM_gtm_cls0_MCS0_CH4_ACB_ACB3_SHIFT (3U) #define GTM_gtm_cls0_MCS0_CH4_ACB_ACB3_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH4_ACB_ACB3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_ACB_ACB3_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_ACB_ACB3_MASK) #define GTM_gtm_cls0_MCS0_CH4_ACB_ACB4_MASK (0x10U) #define GTM_gtm_cls0_MCS0_CH4_ACB_ACB4_SHIFT (4U) #define GTM_gtm_cls0_MCS0_CH4_ACB_ACB4_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH4_ACB_ACB4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_ACB_ACB4_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_ACB_ACB4_MASK) /*! @} */ /*! @name MCS0_CH4_MHB - MCS[i] channel x memory high byte register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH4_MHB_DATA_MASK (0xFFU) #define GTM_gtm_cls0_MCS0_CH4_MHB_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH4_MHB_DATA_WIDTH (8U) #define GTM_gtm_cls0_MCS0_CH4_MHB_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_MHB_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_MHB_DATA_MASK) /*! @} */ /*! @name MCS0_CH4_PC - MCS[i] channel x program counter register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH4_PC_PC_MASK (0xFFFFU) #define GTM_gtm_cls0_MCS0_CH4_PC_PC_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH4_PC_PC_WIDTH (16U) #define GTM_gtm_cls0_MCS0_CH4_PC_PC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_PC_PC_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_PC_PC_MASK) /*! @} */ /*! @name MCS0_CH4_IRQ_NOTIFY - MCS[i] channel x interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH4_IRQ_NOTIFY_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH4_IRQ_NOTIFY_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH4_IRQ_NOTIFY_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH4_IRQ_NOTIFY_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_IRQ_NOTIFY_MCS_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_IRQ_NOTIFY_MCS_IRQ_MASK) #define GTM_gtm_cls0_MCS0_CH4_IRQ_NOTIFY_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH4_IRQ_NOTIFY_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH4_IRQ_NOTIFY_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH4_IRQ_NOTIFY_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_IRQ_NOTIFY_ERR_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_IRQ_NOTIFY_ERR_IRQ_MASK) /*! @} */ /*! @name MCS0_CH4_IRQ_EN - MCS[i] channel x interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH4_IRQ_EN_MCS_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH4_IRQ_EN_MCS_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH4_IRQ_EN_MCS_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH4_IRQ_EN_MCS_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_IRQ_EN_MCS_IRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_IRQ_EN_MCS_IRQ_EN_MASK) #define GTM_gtm_cls0_MCS0_CH4_IRQ_EN_ERR_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH4_IRQ_EN_ERR_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH4_IRQ_EN_ERR_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH4_IRQ_EN_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_IRQ_EN_ERR_IRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_IRQ_EN_ERR_IRQ_EN_MASK) /*! @} */ /*! @name MCS0_CH4_IRQ_FORCINT - MCS[i] channel x force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH4_IRQ_FORCINT_TRG_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH4_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH4_IRQ_FORCINT_TRG_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH4_IRQ_FORCINT_TRG_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_IRQ_FORCINT_TRG_MCS_IRQ_MASK) #define GTM_gtm_cls0_MCS0_CH4_IRQ_FORCINT_TRG_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH4_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH4_IRQ_FORCINT_TRG_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH4_IRQ_FORCINT_TRG_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_IRQ_FORCINT_TRG_ERR_IRQ_MASK) /*! @} */ /*! @name MCS0_CH4_IRQ_MODE - MCS[i] channel x IRQ mode configuration register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH4_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_MCS0_CH4_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH4_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_MCS0_CH4_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name MCS0_CH4_EIRQ_EN - MCS[i] channel x error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH4_EIRQ_EN_MCS_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH4_EIRQ_EN_MCS_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH4_EIRQ_EN_MCS_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH4_EIRQ_EN_MCS_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_EIRQ_EN_MCS_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_EIRQ_EN_MCS_EIRQ_EN_MASK) #define GTM_gtm_cls0_MCS0_CH4_EIRQ_EN_ERR_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH4_EIRQ_EN_ERR_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH4_EIRQ_EN_ERR_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH4_EIRQ_EN_ERR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH4_EIRQ_EN_ERR_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH4_EIRQ_EN_ERR_EIRQ_EN_MASK) /*! @} */ /*! @name MCS0_CH5_R0 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH5_R0_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH5_R0_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH5_R0_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH5_R0_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_R0_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_R0_DATA_MASK) /*! @} */ /*! @name MCS0_CH5_R1 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH5_R1_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH5_R1_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH5_R1_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH5_R1_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_R1_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_R1_DATA_MASK) /*! @} */ /*! @name MCS0_CH5_R2 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH5_R2_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH5_R2_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH5_R2_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH5_R2_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_R2_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_R2_DATA_MASK) /*! @} */ /*! @name MCS0_CH5_R3 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH5_R3_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH5_R3_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH5_R3_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH5_R3_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_R3_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_R3_DATA_MASK) /*! @} */ /*! @name MCS0_CH5_R4 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH5_R4_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH5_R4_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH5_R4_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH5_R4_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_R4_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_R4_DATA_MASK) /*! @} */ /*! @name MCS0_CH5_R5 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH5_R5_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH5_R5_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH5_R5_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH5_R5_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_R5_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_R5_DATA_MASK) /*! @} */ /*! @name MCS0_CH5_R6 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH5_R6_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH5_R6_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH5_R6_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH5_R6_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_R6_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_R6_DATA_MASK) /*! @} */ /*! @name MCS0_CH5_R7 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH5_R7_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH5_R7_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH5_R7_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH5_R7_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_R7_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_R7_DATA_MASK) /*! @} */ /*! @name MCS0_CH5_CTRL - MCS[i] channel x control register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH5_CTRL_EN_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH5_CTRL_EN_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH5_CTRL_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH5_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_CTRL_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_CTRL_EN_MASK) #define GTM_gtm_cls0_MCS0_CH5_CTRL_IRQ_MASK (0x2U) #define GTM_gtm_cls0_MCS0_CH5_CTRL_IRQ_SHIFT (1U) #define GTM_gtm_cls0_MCS0_CH5_CTRL_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH5_CTRL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_CTRL_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_CTRL_IRQ_MASK) #define GTM_gtm_cls0_MCS0_CH5_CTRL_ERR_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH5_CTRL_ERR_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH5_CTRL_ERR_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH5_CTRL_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_CTRL_ERR_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_CTRL_ERR_MASK) #define GTM_gtm_cls0_MCS0_CH5_CTRL_CY_MASK (0x10U) #define GTM_gtm_cls0_MCS0_CH5_CTRL_CY_SHIFT (4U) #define GTM_gtm_cls0_MCS0_CH5_CTRL_CY_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH5_CTRL_CY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_CTRL_CY_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_CTRL_CY_MASK) #define GTM_gtm_cls0_MCS0_CH5_CTRL_Z_MASK (0x20U) #define GTM_gtm_cls0_MCS0_CH5_CTRL_Z_SHIFT (5U) #define GTM_gtm_cls0_MCS0_CH5_CTRL_Z_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH5_CTRL_Z(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_CTRL_Z_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_CTRL_Z_MASK) #define GTM_gtm_cls0_MCS0_CH5_CTRL_V_MASK (0x40U) #define GTM_gtm_cls0_MCS0_CH5_CTRL_V_SHIFT (6U) #define GTM_gtm_cls0_MCS0_CH5_CTRL_V_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH5_CTRL_V(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_CTRL_V_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_CTRL_V_MASK) #define GTM_gtm_cls0_MCS0_CH5_CTRL_N_MASK (0x80U) #define GTM_gtm_cls0_MCS0_CH5_CTRL_N_SHIFT (7U) #define GTM_gtm_cls0_MCS0_CH5_CTRL_N_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH5_CTRL_N(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_CTRL_N_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_CTRL_N_MASK) #define GTM_gtm_cls0_MCS0_CH5_CTRL_CAT_MASK (0x100U) #define GTM_gtm_cls0_MCS0_CH5_CTRL_CAT_SHIFT (8U) #define GTM_gtm_cls0_MCS0_CH5_CTRL_CAT_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH5_CTRL_CAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_CTRL_CAT_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_CTRL_CAT_MASK) #define GTM_gtm_cls0_MCS0_CH5_CTRL_CWT_MASK (0x200U) #define GTM_gtm_cls0_MCS0_CH5_CTRL_CWT_SHIFT (9U) #define GTM_gtm_cls0_MCS0_CH5_CTRL_CWT_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH5_CTRL_CWT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_CTRL_CWT_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_CTRL_CWT_MASK) #define GTM_gtm_cls0_MCS0_CH5_CTRL_SAT_MASK (0x400U) #define GTM_gtm_cls0_MCS0_CH5_CTRL_SAT_SHIFT (10U) #define GTM_gtm_cls0_MCS0_CH5_CTRL_SAT_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH5_CTRL_SAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_CTRL_SAT_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_CTRL_SAT_MASK) /*! @} */ /*! @name MCS0_CH5_ACB - MCS[i] channel x ARU control Bit register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH5_ACB_ACB0_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH5_ACB_ACB0_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH5_ACB_ACB0_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH5_ACB_ACB0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_ACB_ACB0_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_ACB_ACB0_MASK) #define GTM_gtm_cls0_MCS0_CH5_ACB_ACB1_MASK (0x2U) #define GTM_gtm_cls0_MCS0_CH5_ACB_ACB1_SHIFT (1U) #define GTM_gtm_cls0_MCS0_CH5_ACB_ACB1_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH5_ACB_ACB1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_ACB_ACB1_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_ACB_ACB1_MASK) #define GTM_gtm_cls0_MCS0_CH5_ACB_ACB2_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH5_ACB_ACB2_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH5_ACB_ACB2_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH5_ACB_ACB2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_ACB_ACB2_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_ACB_ACB2_MASK) #define GTM_gtm_cls0_MCS0_CH5_ACB_ACB3_MASK (0x8U) #define GTM_gtm_cls0_MCS0_CH5_ACB_ACB3_SHIFT (3U) #define GTM_gtm_cls0_MCS0_CH5_ACB_ACB3_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH5_ACB_ACB3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_ACB_ACB3_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_ACB_ACB3_MASK) #define GTM_gtm_cls0_MCS0_CH5_ACB_ACB4_MASK (0x10U) #define GTM_gtm_cls0_MCS0_CH5_ACB_ACB4_SHIFT (4U) #define GTM_gtm_cls0_MCS0_CH5_ACB_ACB4_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH5_ACB_ACB4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_ACB_ACB4_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_ACB_ACB4_MASK) /*! @} */ /*! @name MCS0_CH5_MHB - MCS[i] channel x memory high byte register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH5_MHB_DATA_MASK (0xFFU) #define GTM_gtm_cls0_MCS0_CH5_MHB_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH5_MHB_DATA_WIDTH (8U) #define GTM_gtm_cls0_MCS0_CH5_MHB_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_MHB_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_MHB_DATA_MASK) /*! @} */ /*! @name MCS0_CH5_PC - MCS[i] channel x program counter register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH5_PC_PC_MASK (0xFFFFU) #define GTM_gtm_cls0_MCS0_CH5_PC_PC_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH5_PC_PC_WIDTH (16U) #define GTM_gtm_cls0_MCS0_CH5_PC_PC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_PC_PC_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_PC_PC_MASK) /*! @} */ /*! @name MCS0_CH5_IRQ_NOTIFY - MCS[i] channel x interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH5_IRQ_NOTIFY_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH5_IRQ_NOTIFY_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH5_IRQ_NOTIFY_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH5_IRQ_NOTIFY_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_IRQ_NOTIFY_MCS_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_IRQ_NOTIFY_MCS_IRQ_MASK) #define GTM_gtm_cls0_MCS0_CH5_IRQ_NOTIFY_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH5_IRQ_NOTIFY_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH5_IRQ_NOTIFY_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH5_IRQ_NOTIFY_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_IRQ_NOTIFY_ERR_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_IRQ_NOTIFY_ERR_IRQ_MASK) /*! @} */ /*! @name MCS0_CH5_IRQ_EN - MCS[i] channel x interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH5_IRQ_EN_MCS_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH5_IRQ_EN_MCS_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH5_IRQ_EN_MCS_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH5_IRQ_EN_MCS_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_IRQ_EN_MCS_IRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_IRQ_EN_MCS_IRQ_EN_MASK) #define GTM_gtm_cls0_MCS0_CH5_IRQ_EN_ERR_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH5_IRQ_EN_ERR_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH5_IRQ_EN_ERR_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH5_IRQ_EN_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_IRQ_EN_ERR_IRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_IRQ_EN_ERR_IRQ_EN_MASK) /*! @} */ /*! @name MCS0_CH5_IRQ_FORCINT - MCS[i] channel x force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH5_IRQ_FORCINT_TRG_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH5_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH5_IRQ_FORCINT_TRG_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH5_IRQ_FORCINT_TRG_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_IRQ_FORCINT_TRG_MCS_IRQ_MASK) #define GTM_gtm_cls0_MCS0_CH5_IRQ_FORCINT_TRG_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH5_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH5_IRQ_FORCINT_TRG_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH5_IRQ_FORCINT_TRG_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_IRQ_FORCINT_TRG_ERR_IRQ_MASK) /*! @} */ /*! @name MCS0_CH5_IRQ_MODE - MCS[i] channel x IRQ mode configuration register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH5_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_MCS0_CH5_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH5_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_MCS0_CH5_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name MCS0_CH5_EIRQ_EN - MCS[i] channel x error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH5_EIRQ_EN_MCS_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH5_EIRQ_EN_MCS_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH5_EIRQ_EN_MCS_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH5_EIRQ_EN_MCS_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_EIRQ_EN_MCS_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_EIRQ_EN_MCS_EIRQ_EN_MASK) #define GTM_gtm_cls0_MCS0_CH5_EIRQ_EN_ERR_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH5_EIRQ_EN_ERR_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH5_EIRQ_EN_ERR_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH5_EIRQ_EN_ERR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH5_EIRQ_EN_ERR_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH5_EIRQ_EN_ERR_EIRQ_EN_MASK) /*! @} */ /*! @name MCS0_CH6_R0 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH6_R0_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH6_R0_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH6_R0_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH6_R0_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_R0_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_R0_DATA_MASK) /*! @} */ /*! @name MCS0_CH6_R1 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH6_R1_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH6_R1_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH6_R1_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH6_R1_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_R1_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_R1_DATA_MASK) /*! @} */ /*! @name MCS0_CH6_R2 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH6_R2_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH6_R2_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH6_R2_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH6_R2_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_R2_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_R2_DATA_MASK) /*! @} */ /*! @name MCS0_CH6_R3 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH6_R3_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH6_R3_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH6_R3_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH6_R3_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_R3_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_R3_DATA_MASK) /*! @} */ /*! @name MCS0_CH6_R4 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH6_R4_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH6_R4_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH6_R4_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH6_R4_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_R4_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_R4_DATA_MASK) /*! @} */ /*! @name MCS0_CH6_R5 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH6_R5_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH6_R5_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH6_R5_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH6_R5_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_R5_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_R5_DATA_MASK) /*! @} */ /*! @name MCS0_CH6_R6 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH6_R6_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH6_R6_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH6_R6_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH6_R6_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_R6_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_R6_DATA_MASK) /*! @} */ /*! @name MCS0_CH6_R7 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH6_R7_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH6_R7_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH6_R7_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH6_R7_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_R7_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_R7_DATA_MASK) /*! @} */ /*! @name MCS0_CH6_CTRL - MCS[i] channel x control register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH6_CTRL_EN_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH6_CTRL_EN_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH6_CTRL_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH6_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_CTRL_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_CTRL_EN_MASK) #define GTM_gtm_cls0_MCS0_CH6_CTRL_IRQ_MASK (0x2U) #define GTM_gtm_cls0_MCS0_CH6_CTRL_IRQ_SHIFT (1U) #define GTM_gtm_cls0_MCS0_CH6_CTRL_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH6_CTRL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_CTRL_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_CTRL_IRQ_MASK) #define GTM_gtm_cls0_MCS0_CH6_CTRL_ERR_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH6_CTRL_ERR_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH6_CTRL_ERR_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH6_CTRL_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_CTRL_ERR_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_CTRL_ERR_MASK) #define GTM_gtm_cls0_MCS0_CH6_CTRL_CY_MASK (0x10U) #define GTM_gtm_cls0_MCS0_CH6_CTRL_CY_SHIFT (4U) #define GTM_gtm_cls0_MCS0_CH6_CTRL_CY_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH6_CTRL_CY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_CTRL_CY_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_CTRL_CY_MASK) #define GTM_gtm_cls0_MCS0_CH6_CTRL_Z_MASK (0x20U) #define GTM_gtm_cls0_MCS0_CH6_CTRL_Z_SHIFT (5U) #define GTM_gtm_cls0_MCS0_CH6_CTRL_Z_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH6_CTRL_Z(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_CTRL_Z_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_CTRL_Z_MASK) #define GTM_gtm_cls0_MCS0_CH6_CTRL_V_MASK (0x40U) #define GTM_gtm_cls0_MCS0_CH6_CTRL_V_SHIFT (6U) #define GTM_gtm_cls0_MCS0_CH6_CTRL_V_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH6_CTRL_V(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_CTRL_V_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_CTRL_V_MASK) #define GTM_gtm_cls0_MCS0_CH6_CTRL_N_MASK (0x80U) #define GTM_gtm_cls0_MCS0_CH6_CTRL_N_SHIFT (7U) #define GTM_gtm_cls0_MCS0_CH6_CTRL_N_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH6_CTRL_N(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_CTRL_N_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_CTRL_N_MASK) #define GTM_gtm_cls0_MCS0_CH6_CTRL_CAT_MASK (0x100U) #define GTM_gtm_cls0_MCS0_CH6_CTRL_CAT_SHIFT (8U) #define GTM_gtm_cls0_MCS0_CH6_CTRL_CAT_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH6_CTRL_CAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_CTRL_CAT_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_CTRL_CAT_MASK) #define GTM_gtm_cls0_MCS0_CH6_CTRL_CWT_MASK (0x200U) #define GTM_gtm_cls0_MCS0_CH6_CTRL_CWT_SHIFT (9U) #define GTM_gtm_cls0_MCS0_CH6_CTRL_CWT_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH6_CTRL_CWT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_CTRL_CWT_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_CTRL_CWT_MASK) #define GTM_gtm_cls0_MCS0_CH6_CTRL_SAT_MASK (0x400U) #define GTM_gtm_cls0_MCS0_CH6_CTRL_SAT_SHIFT (10U) #define GTM_gtm_cls0_MCS0_CH6_CTRL_SAT_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH6_CTRL_SAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_CTRL_SAT_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_CTRL_SAT_MASK) /*! @} */ /*! @name MCS0_CH6_ACB - MCS[i] channel x ARU control Bit register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH6_ACB_ACB0_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH6_ACB_ACB0_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH6_ACB_ACB0_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH6_ACB_ACB0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_ACB_ACB0_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_ACB_ACB0_MASK) #define GTM_gtm_cls0_MCS0_CH6_ACB_ACB1_MASK (0x2U) #define GTM_gtm_cls0_MCS0_CH6_ACB_ACB1_SHIFT (1U) #define GTM_gtm_cls0_MCS0_CH6_ACB_ACB1_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH6_ACB_ACB1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_ACB_ACB1_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_ACB_ACB1_MASK) #define GTM_gtm_cls0_MCS0_CH6_ACB_ACB2_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH6_ACB_ACB2_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH6_ACB_ACB2_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH6_ACB_ACB2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_ACB_ACB2_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_ACB_ACB2_MASK) #define GTM_gtm_cls0_MCS0_CH6_ACB_ACB3_MASK (0x8U) #define GTM_gtm_cls0_MCS0_CH6_ACB_ACB3_SHIFT (3U) #define GTM_gtm_cls0_MCS0_CH6_ACB_ACB3_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH6_ACB_ACB3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_ACB_ACB3_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_ACB_ACB3_MASK) #define GTM_gtm_cls0_MCS0_CH6_ACB_ACB4_MASK (0x10U) #define GTM_gtm_cls0_MCS0_CH6_ACB_ACB4_SHIFT (4U) #define GTM_gtm_cls0_MCS0_CH6_ACB_ACB4_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH6_ACB_ACB4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_ACB_ACB4_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_ACB_ACB4_MASK) /*! @} */ /*! @name MCS0_CH6_MHB - MCS[i] channel x memory high byte register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH6_MHB_DATA_MASK (0xFFU) #define GTM_gtm_cls0_MCS0_CH6_MHB_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH6_MHB_DATA_WIDTH (8U) #define GTM_gtm_cls0_MCS0_CH6_MHB_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_MHB_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_MHB_DATA_MASK) /*! @} */ /*! @name MCS0_CH6_PC - MCS[i] channel x program counter register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH6_PC_PC_MASK (0xFFFFU) #define GTM_gtm_cls0_MCS0_CH6_PC_PC_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH6_PC_PC_WIDTH (16U) #define GTM_gtm_cls0_MCS0_CH6_PC_PC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_PC_PC_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_PC_PC_MASK) /*! @} */ /*! @name MCS0_CH6_IRQ_NOTIFY - MCS[i] channel x interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH6_IRQ_NOTIFY_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH6_IRQ_NOTIFY_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH6_IRQ_NOTIFY_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH6_IRQ_NOTIFY_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_IRQ_NOTIFY_MCS_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_IRQ_NOTIFY_MCS_IRQ_MASK) #define GTM_gtm_cls0_MCS0_CH6_IRQ_NOTIFY_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH6_IRQ_NOTIFY_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH6_IRQ_NOTIFY_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH6_IRQ_NOTIFY_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_IRQ_NOTIFY_ERR_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_IRQ_NOTIFY_ERR_IRQ_MASK) /*! @} */ /*! @name MCS0_CH6_IRQ_EN - MCS[i] channel x interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH6_IRQ_EN_MCS_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH6_IRQ_EN_MCS_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH6_IRQ_EN_MCS_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH6_IRQ_EN_MCS_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_IRQ_EN_MCS_IRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_IRQ_EN_MCS_IRQ_EN_MASK) #define GTM_gtm_cls0_MCS0_CH6_IRQ_EN_ERR_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH6_IRQ_EN_ERR_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH6_IRQ_EN_ERR_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH6_IRQ_EN_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_IRQ_EN_ERR_IRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_IRQ_EN_ERR_IRQ_EN_MASK) /*! @} */ /*! @name MCS0_CH6_IRQ_FORCINT - MCS[i] channel x force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH6_IRQ_FORCINT_TRG_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH6_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH6_IRQ_FORCINT_TRG_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH6_IRQ_FORCINT_TRG_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_IRQ_FORCINT_TRG_MCS_IRQ_MASK) #define GTM_gtm_cls0_MCS0_CH6_IRQ_FORCINT_TRG_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH6_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH6_IRQ_FORCINT_TRG_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH6_IRQ_FORCINT_TRG_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_IRQ_FORCINT_TRG_ERR_IRQ_MASK) /*! @} */ /*! @name MCS0_CH6_IRQ_MODE - MCS[i] channel x IRQ mode configuration register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH6_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_MCS0_CH6_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH6_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_MCS0_CH6_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name MCS0_CH6_EIRQ_EN - MCS[i] channel x error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH6_EIRQ_EN_MCS_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH6_EIRQ_EN_MCS_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH6_EIRQ_EN_MCS_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH6_EIRQ_EN_MCS_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_EIRQ_EN_MCS_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_EIRQ_EN_MCS_EIRQ_EN_MASK) #define GTM_gtm_cls0_MCS0_CH6_EIRQ_EN_ERR_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH6_EIRQ_EN_ERR_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH6_EIRQ_EN_ERR_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH6_EIRQ_EN_ERR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH6_EIRQ_EN_ERR_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH6_EIRQ_EN_ERR_EIRQ_EN_MASK) /*! @} */ /*! @name MCS0_CH7_R0 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH7_R0_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH7_R0_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH7_R0_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH7_R0_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_R0_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_R0_DATA_MASK) /*! @} */ /*! @name MCS0_CH7_R1 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH7_R1_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH7_R1_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH7_R1_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH7_R1_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_R1_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_R1_DATA_MASK) /*! @} */ /*! @name MCS0_CH7_R2 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH7_R2_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH7_R2_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH7_R2_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH7_R2_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_R2_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_R2_DATA_MASK) /*! @} */ /*! @name MCS0_CH7_R3 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH7_R3_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH7_R3_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH7_R3_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH7_R3_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_R3_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_R3_DATA_MASK) /*! @} */ /*! @name MCS0_CH7_R4 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH7_R4_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH7_R4_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH7_R4_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH7_R4_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_R4_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_R4_DATA_MASK) /*! @} */ /*! @name MCS0_CH7_R5 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH7_R5_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH7_R5_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH7_R5_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH7_R5_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_R5_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_R5_DATA_MASK) /*! @} */ /*! @name MCS0_CH7_R6 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH7_R6_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH7_R6_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH7_R6_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH7_R6_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_R6_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_R6_DATA_MASK) /*! @} */ /*! @name MCS0_CH7_R7 - MCS[i] channel x general purpose register [y] */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH7_R7_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_MCS0_CH7_R7_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH7_R7_DATA_WIDTH (24U) #define GTM_gtm_cls0_MCS0_CH7_R7_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_R7_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_R7_DATA_MASK) /*! @} */ /*! @name MCS0_CH7_CTRL - MCS[i] channel x control register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH7_CTRL_EN_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH7_CTRL_EN_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH7_CTRL_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH7_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_CTRL_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_CTRL_EN_MASK) #define GTM_gtm_cls0_MCS0_CH7_CTRL_IRQ_MASK (0x2U) #define GTM_gtm_cls0_MCS0_CH7_CTRL_IRQ_SHIFT (1U) #define GTM_gtm_cls0_MCS0_CH7_CTRL_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH7_CTRL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_CTRL_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_CTRL_IRQ_MASK) #define GTM_gtm_cls0_MCS0_CH7_CTRL_ERR_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH7_CTRL_ERR_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH7_CTRL_ERR_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH7_CTRL_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_CTRL_ERR_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_CTRL_ERR_MASK) #define GTM_gtm_cls0_MCS0_CH7_CTRL_CY_MASK (0x10U) #define GTM_gtm_cls0_MCS0_CH7_CTRL_CY_SHIFT (4U) #define GTM_gtm_cls0_MCS0_CH7_CTRL_CY_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH7_CTRL_CY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_CTRL_CY_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_CTRL_CY_MASK) #define GTM_gtm_cls0_MCS0_CH7_CTRL_Z_MASK (0x20U) #define GTM_gtm_cls0_MCS0_CH7_CTRL_Z_SHIFT (5U) #define GTM_gtm_cls0_MCS0_CH7_CTRL_Z_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH7_CTRL_Z(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_CTRL_Z_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_CTRL_Z_MASK) #define GTM_gtm_cls0_MCS0_CH7_CTRL_V_MASK (0x40U) #define GTM_gtm_cls0_MCS0_CH7_CTRL_V_SHIFT (6U) #define GTM_gtm_cls0_MCS0_CH7_CTRL_V_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH7_CTRL_V(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_CTRL_V_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_CTRL_V_MASK) #define GTM_gtm_cls0_MCS0_CH7_CTRL_N_MASK (0x80U) #define GTM_gtm_cls0_MCS0_CH7_CTRL_N_SHIFT (7U) #define GTM_gtm_cls0_MCS0_CH7_CTRL_N_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH7_CTRL_N(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_CTRL_N_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_CTRL_N_MASK) #define GTM_gtm_cls0_MCS0_CH7_CTRL_CAT_MASK (0x100U) #define GTM_gtm_cls0_MCS0_CH7_CTRL_CAT_SHIFT (8U) #define GTM_gtm_cls0_MCS0_CH7_CTRL_CAT_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH7_CTRL_CAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_CTRL_CAT_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_CTRL_CAT_MASK) #define GTM_gtm_cls0_MCS0_CH7_CTRL_CWT_MASK (0x200U) #define GTM_gtm_cls0_MCS0_CH7_CTRL_CWT_SHIFT (9U) #define GTM_gtm_cls0_MCS0_CH7_CTRL_CWT_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH7_CTRL_CWT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_CTRL_CWT_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_CTRL_CWT_MASK) #define GTM_gtm_cls0_MCS0_CH7_CTRL_SAT_MASK (0x400U) #define GTM_gtm_cls0_MCS0_CH7_CTRL_SAT_SHIFT (10U) #define GTM_gtm_cls0_MCS0_CH7_CTRL_SAT_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH7_CTRL_SAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_CTRL_SAT_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_CTRL_SAT_MASK) /*! @} */ /*! @name MCS0_CH7_ACB - MCS[i] channel x ARU control Bit register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH7_ACB_ACB0_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH7_ACB_ACB0_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH7_ACB_ACB0_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH7_ACB_ACB0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_ACB_ACB0_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_ACB_ACB0_MASK) #define GTM_gtm_cls0_MCS0_CH7_ACB_ACB1_MASK (0x2U) #define GTM_gtm_cls0_MCS0_CH7_ACB_ACB1_SHIFT (1U) #define GTM_gtm_cls0_MCS0_CH7_ACB_ACB1_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH7_ACB_ACB1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_ACB_ACB1_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_ACB_ACB1_MASK) #define GTM_gtm_cls0_MCS0_CH7_ACB_ACB2_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH7_ACB_ACB2_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH7_ACB_ACB2_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH7_ACB_ACB2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_ACB_ACB2_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_ACB_ACB2_MASK) #define GTM_gtm_cls0_MCS0_CH7_ACB_ACB3_MASK (0x8U) #define GTM_gtm_cls0_MCS0_CH7_ACB_ACB3_SHIFT (3U) #define GTM_gtm_cls0_MCS0_CH7_ACB_ACB3_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH7_ACB_ACB3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_ACB_ACB3_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_ACB_ACB3_MASK) #define GTM_gtm_cls0_MCS0_CH7_ACB_ACB4_MASK (0x10U) #define GTM_gtm_cls0_MCS0_CH7_ACB_ACB4_SHIFT (4U) #define GTM_gtm_cls0_MCS0_CH7_ACB_ACB4_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH7_ACB_ACB4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_ACB_ACB4_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_ACB_ACB4_MASK) /*! @} */ /*! @name MCS0_CH7_MHB - MCS[i] channel x memory high byte register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH7_MHB_DATA_MASK (0xFFU) #define GTM_gtm_cls0_MCS0_CH7_MHB_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH7_MHB_DATA_WIDTH (8U) #define GTM_gtm_cls0_MCS0_CH7_MHB_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_MHB_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_MHB_DATA_MASK) /*! @} */ /*! @name MCS0_CH7_PC - MCS[i] channel x program counter register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH7_PC_PC_MASK (0xFFFFU) #define GTM_gtm_cls0_MCS0_CH7_PC_PC_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH7_PC_PC_WIDTH (16U) #define GTM_gtm_cls0_MCS0_CH7_PC_PC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_PC_PC_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_PC_PC_MASK) /*! @} */ /*! @name MCS0_CH7_IRQ_NOTIFY - MCS[i] channel x interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH7_IRQ_NOTIFY_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH7_IRQ_NOTIFY_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH7_IRQ_NOTIFY_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH7_IRQ_NOTIFY_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_IRQ_NOTIFY_MCS_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_IRQ_NOTIFY_MCS_IRQ_MASK) #define GTM_gtm_cls0_MCS0_CH7_IRQ_NOTIFY_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH7_IRQ_NOTIFY_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH7_IRQ_NOTIFY_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH7_IRQ_NOTIFY_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_IRQ_NOTIFY_ERR_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_IRQ_NOTIFY_ERR_IRQ_MASK) /*! @} */ /*! @name MCS0_CH7_IRQ_EN - MCS[i] channel x interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH7_IRQ_EN_MCS_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH7_IRQ_EN_MCS_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH7_IRQ_EN_MCS_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH7_IRQ_EN_MCS_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_IRQ_EN_MCS_IRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_IRQ_EN_MCS_IRQ_EN_MASK) #define GTM_gtm_cls0_MCS0_CH7_IRQ_EN_ERR_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH7_IRQ_EN_ERR_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH7_IRQ_EN_ERR_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH7_IRQ_EN_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_IRQ_EN_ERR_IRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_IRQ_EN_ERR_IRQ_EN_MASK) /*! @} */ /*! @name MCS0_CH7_IRQ_FORCINT - MCS[i] channel x force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH7_IRQ_FORCINT_TRG_MCS_IRQ_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH7_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH7_IRQ_FORCINT_TRG_MCS_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH7_IRQ_FORCINT_TRG_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_IRQ_FORCINT_TRG_MCS_IRQ_MASK) #define GTM_gtm_cls0_MCS0_CH7_IRQ_FORCINT_TRG_ERR_IRQ_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH7_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH7_IRQ_FORCINT_TRG_ERR_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH7_IRQ_FORCINT_TRG_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_IRQ_FORCINT_TRG_ERR_IRQ_MASK) /*! @} */ /*! @name MCS0_CH7_IRQ_MODE - MCS[i] channel x IRQ mode configuration register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH7_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_MCS0_CH7_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH7_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_MCS0_CH7_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name MCS0_CH7_EIRQ_EN - MCS[i] channel x error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CH7_EIRQ_EN_MCS_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CH7_EIRQ_EN_MCS_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CH7_EIRQ_EN_MCS_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH7_EIRQ_EN_MCS_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_EIRQ_EN_MCS_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_EIRQ_EN_MCS_EIRQ_EN_MASK) #define GTM_gtm_cls0_MCS0_CH7_EIRQ_EN_ERR_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CH7_EIRQ_EN_ERR_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CH7_EIRQ_EN_ERR_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CH7_EIRQ_EN_ERR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CH7_EIRQ_EN_ERR_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_CH7_EIRQ_EN_ERR_EIRQ_EN_MASK) /*! @} */ /*! @name MCS0_CTRG - MCS[i] clear trigger control register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CTRG_TRG0_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CTRG_TRG0_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CTRG_TRG0_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CTRG_TRG0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CTRG_TRG0_SHIFT)) & GTM_gtm_cls0_MCS0_CTRG_TRG0_MASK) #define GTM_gtm_cls0_MCS0_CTRG_TRG1_MASK (0x2U) #define GTM_gtm_cls0_MCS0_CTRG_TRG1_SHIFT (1U) #define GTM_gtm_cls0_MCS0_CTRG_TRG1_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CTRG_TRG1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CTRG_TRG1_SHIFT)) & GTM_gtm_cls0_MCS0_CTRG_TRG1_MASK) #define GTM_gtm_cls0_MCS0_CTRG_TRG2_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CTRG_TRG2_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CTRG_TRG2_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CTRG_TRG2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CTRG_TRG2_SHIFT)) & GTM_gtm_cls0_MCS0_CTRG_TRG2_MASK) #define GTM_gtm_cls0_MCS0_CTRG_TRG3_MASK (0x8U) #define GTM_gtm_cls0_MCS0_CTRG_TRG3_SHIFT (3U) #define GTM_gtm_cls0_MCS0_CTRG_TRG3_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CTRG_TRG3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CTRG_TRG3_SHIFT)) & GTM_gtm_cls0_MCS0_CTRG_TRG3_MASK) #define GTM_gtm_cls0_MCS0_CTRG_TRG4_MASK (0x10U) #define GTM_gtm_cls0_MCS0_CTRG_TRG4_SHIFT (4U) #define GTM_gtm_cls0_MCS0_CTRG_TRG4_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CTRG_TRG4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CTRG_TRG4_SHIFT)) & GTM_gtm_cls0_MCS0_CTRG_TRG4_MASK) #define GTM_gtm_cls0_MCS0_CTRG_TRG5_MASK (0x20U) #define GTM_gtm_cls0_MCS0_CTRG_TRG5_SHIFT (5U) #define GTM_gtm_cls0_MCS0_CTRG_TRG5_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CTRG_TRG5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CTRG_TRG5_SHIFT)) & GTM_gtm_cls0_MCS0_CTRG_TRG5_MASK) #define GTM_gtm_cls0_MCS0_CTRG_TRG6_MASK (0x40U) #define GTM_gtm_cls0_MCS0_CTRG_TRG6_SHIFT (6U) #define GTM_gtm_cls0_MCS0_CTRG_TRG6_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CTRG_TRG6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CTRG_TRG6_SHIFT)) & GTM_gtm_cls0_MCS0_CTRG_TRG6_MASK) #define GTM_gtm_cls0_MCS0_CTRG_TRG7_MASK (0x80U) #define GTM_gtm_cls0_MCS0_CTRG_TRG7_SHIFT (7U) #define GTM_gtm_cls0_MCS0_CTRG_TRG7_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CTRG_TRG7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CTRG_TRG7_SHIFT)) & GTM_gtm_cls0_MCS0_CTRG_TRG7_MASK) #define GTM_gtm_cls0_MCS0_CTRG_TRG8_MASK (0x100U) #define GTM_gtm_cls0_MCS0_CTRG_TRG8_SHIFT (8U) #define GTM_gtm_cls0_MCS0_CTRG_TRG8_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CTRG_TRG8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CTRG_TRG8_SHIFT)) & GTM_gtm_cls0_MCS0_CTRG_TRG8_MASK) #define GTM_gtm_cls0_MCS0_CTRG_TRG9_MASK (0x200U) #define GTM_gtm_cls0_MCS0_CTRG_TRG9_SHIFT (9U) #define GTM_gtm_cls0_MCS0_CTRG_TRG9_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CTRG_TRG9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CTRG_TRG9_SHIFT)) & GTM_gtm_cls0_MCS0_CTRG_TRG9_MASK) #define GTM_gtm_cls0_MCS0_CTRG_TRG10_MASK (0x400U) #define GTM_gtm_cls0_MCS0_CTRG_TRG10_SHIFT (10U) #define GTM_gtm_cls0_MCS0_CTRG_TRG10_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CTRG_TRG10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CTRG_TRG10_SHIFT)) & GTM_gtm_cls0_MCS0_CTRG_TRG10_MASK) #define GTM_gtm_cls0_MCS0_CTRG_TRG11_MASK (0x800U) #define GTM_gtm_cls0_MCS0_CTRG_TRG11_SHIFT (11U) #define GTM_gtm_cls0_MCS0_CTRG_TRG11_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CTRG_TRG11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CTRG_TRG11_SHIFT)) & GTM_gtm_cls0_MCS0_CTRG_TRG11_MASK) #define GTM_gtm_cls0_MCS0_CTRG_TRG12_MASK (0x1000U) #define GTM_gtm_cls0_MCS0_CTRG_TRG12_SHIFT (12U) #define GTM_gtm_cls0_MCS0_CTRG_TRG12_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CTRG_TRG12(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CTRG_TRG12_SHIFT)) & GTM_gtm_cls0_MCS0_CTRG_TRG12_MASK) #define GTM_gtm_cls0_MCS0_CTRG_TRG13_MASK (0x2000U) #define GTM_gtm_cls0_MCS0_CTRG_TRG13_SHIFT (13U) #define GTM_gtm_cls0_MCS0_CTRG_TRG13_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CTRG_TRG13(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CTRG_TRG13_SHIFT)) & GTM_gtm_cls0_MCS0_CTRG_TRG13_MASK) #define GTM_gtm_cls0_MCS0_CTRG_TRG14_MASK (0x4000U) #define GTM_gtm_cls0_MCS0_CTRG_TRG14_SHIFT (14U) #define GTM_gtm_cls0_MCS0_CTRG_TRG14_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CTRG_TRG14(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CTRG_TRG14_SHIFT)) & GTM_gtm_cls0_MCS0_CTRG_TRG14_MASK) #define GTM_gtm_cls0_MCS0_CTRG_TRG15_MASK (0x8000U) #define GTM_gtm_cls0_MCS0_CTRG_TRG15_SHIFT (15U) #define GTM_gtm_cls0_MCS0_CTRG_TRG15_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CTRG_TRG15(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CTRG_TRG15_SHIFT)) & GTM_gtm_cls0_MCS0_CTRG_TRG15_MASK) #define GTM_gtm_cls0_MCS0_CTRG_TRG16_MASK (0x10000U) #define GTM_gtm_cls0_MCS0_CTRG_TRG16_SHIFT (16U) #define GTM_gtm_cls0_MCS0_CTRG_TRG16_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CTRG_TRG16(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CTRG_TRG16_SHIFT)) & GTM_gtm_cls0_MCS0_CTRG_TRG16_MASK) #define GTM_gtm_cls0_MCS0_CTRG_TRG17_MASK (0x20000U) #define GTM_gtm_cls0_MCS0_CTRG_TRG17_SHIFT (17U) #define GTM_gtm_cls0_MCS0_CTRG_TRG17_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CTRG_TRG17(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CTRG_TRG17_SHIFT)) & GTM_gtm_cls0_MCS0_CTRG_TRG17_MASK) #define GTM_gtm_cls0_MCS0_CTRG_TRG18_MASK (0x40000U) #define GTM_gtm_cls0_MCS0_CTRG_TRG18_SHIFT (18U) #define GTM_gtm_cls0_MCS0_CTRG_TRG18_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CTRG_TRG18(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CTRG_TRG18_SHIFT)) & GTM_gtm_cls0_MCS0_CTRG_TRG18_MASK) #define GTM_gtm_cls0_MCS0_CTRG_TRG19_MASK (0x80000U) #define GTM_gtm_cls0_MCS0_CTRG_TRG19_SHIFT (19U) #define GTM_gtm_cls0_MCS0_CTRG_TRG19_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CTRG_TRG19(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CTRG_TRG19_SHIFT)) & GTM_gtm_cls0_MCS0_CTRG_TRG19_MASK) #define GTM_gtm_cls0_MCS0_CTRG_TRG20_MASK (0x100000U) #define GTM_gtm_cls0_MCS0_CTRG_TRG20_SHIFT (20U) #define GTM_gtm_cls0_MCS0_CTRG_TRG20_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CTRG_TRG20(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CTRG_TRG20_SHIFT)) & GTM_gtm_cls0_MCS0_CTRG_TRG20_MASK) #define GTM_gtm_cls0_MCS0_CTRG_TRG21_MASK (0x200000U) #define GTM_gtm_cls0_MCS0_CTRG_TRG21_SHIFT (21U) #define GTM_gtm_cls0_MCS0_CTRG_TRG21_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CTRG_TRG21(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CTRG_TRG21_SHIFT)) & GTM_gtm_cls0_MCS0_CTRG_TRG21_MASK) #define GTM_gtm_cls0_MCS0_CTRG_TRG22_MASK (0x400000U) #define GTM_gtm_cls0_MCS0_CTRG_TRG22_SHIFT (22U) #define GTM_gtm_cls0_MCS0_CTRG_TRG22_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CTRG_TRG22(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CTRG_TRG22_SHIFT)) & GTM_gtm_cls0_MCS0_CTRG_TRG22_MASK) #define GTM_gtm_cls0_MCS0_CTRG_TRG23_MASK (0x800000U) #define GTM_gtm_cls0_MCS0_CTRG_TRG23_SHIFT (23U) #define GTM_gtm_cls0_MCS0_CTRG_TRG23_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CTRG_TRG23(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CTRG_TRG23_SHIFT)) & GTM_gtm_cls0_MCS0_CTRG_TRG23_MASK) /*! @} */ /*! @name MCS0_STRG - MCS[i] set trigger control register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_STRG_TRG0_MASK (0x1U) #define GTM_gtm_cls0_MCS0_STRG_TRG0_SHIFT (0U) #define GTM_gtm_cls0_MCS0_STRG_TRG0_WIDTH (1U) #define GTM_gtm_cls0_MCS0_STRG_TRG0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_STRG_TRG0_SHIFT)) & GTM_gtm_cls0_MCS0_STRG_TRG0_MASK) #define GTM_gtm_cls0_MCS0_STRG_TRG1_MASK (0x2U) #define GTM_gtm_cls0_MCS0_STRG_TRG1_SHIFT (1U) #define GTM_gtm_cls0_MCS0_STRG_TRG1_WIDTH (1U) #define GTM_gtm_cls0_MCS0_STRG_TRG1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_STRG_TRG1_SHIFT)) & GTM_gtm_cls0_MCS0_STRG_TRG1_MASK) #define GTM_gtm_cls0_MCS0_STRG_TRG2_MASK (0x4U) #define GTM_gtm_cls0_MCS0_STRG_TRG2_SHIFT (2U) #define GTM_gtm_cls0_MCS0_STRG_TRG2_WIDTH (1U) #define GTM_gtm_cls0_MCS0_STRG_TRG2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_STRG_TRG2_SHIFT)) & GTM_gtm_cls0_MCS0_STRG_TRG2_MASK) #define GTM_gtm_cls0_MCS0_STRG_TRG3_MASK (0x8U) #define GTM_gtm_cls0_MCS0_STRG_TRG3_SHIFT (3U) #define GTM_gtm_cls0_MCS0_STRG_TRG3_WIDTH (1U) #define GTM_gtm_cls0_MCS0_STRG_TRG3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_STRG_TRG3_SHIFT)) & GTM_gtm_cls0_MCS0_STRG_TRG3_MASK) #define GTM_gtm_cls0_MCS0_STRG_TRG4_MASK (0x10U) #define GTM_gtm_cls0_MCS0_STRG_TRG4_SHIFT (4U) #define GTM_gtm_cls0_MCS0_STRG_TRG4_WIDTH (1U) #define GTM_gtm_cls0_MCS0_STRG_TRG4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_STRG_TRG4_SHIFT)) & GTM_gtm_cls0_MCS0_STRG_TRG4_MASK) #define GTM_gtm_cls0_MCS0_STRG_TRG5_MASK (0x20U) #define GTM_gtm_cls0_MCS0_STRG_TRG5_SHIFT (5U) #define GTM_gtm_cls0_MCS0_STRG_TRG5_WIDTH (1U) #define GTM_gtm_cls0_MCS0_STRG_TRG5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_STRG_TRG5_SHIFT)) & GTM_gtm_cls0_MCS0_STRG_TRG5_MASK) #define GTM_gtm_cls0_MCS0_STRG_TRG6_MASK (0x40U) #define GTM_gtm_cls0_MCS0_STRG_TRG6_SHIFT (6U) #define GTM_gtm_cls0_MCS0_STRG_TRG6_WIDTH (1U) #define GTM_gtm_cls0_MCS0_STRG_TRG6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_STRG_TRG6_SHIFT)) & GTM_gtm_cls0_MCS0_STRG_TRG6_MASK) #define GTM_gtm_cls0_MCS0_STRG_TRG7_MASK (0x80U) #define GTM_gtm_cls0_MCS0_STRG_TRG7_SHIFT (7U) #define GTM_gtm_cls0_MCS0_STRG_TRG7_WIDTH (1U) #define GTM_gtm_cls0_MCS0_STRG_TRG7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_STRG_TRG7_SHIFT)) & GTM_gtm_cls0_MCS0_STRG_TRG7_MASK) #define GTM_gtm_cls0_MCS0_STRG_TRG8_MASK (0x100U) #define GTM_gtm_cls0_MCS0_STRG_TRG8_SHIFT (8U) #define GTM_gtm_cls0_MCS0_STRG_TRG8_WIDTH (1U) #define GTM_gtm_cls0_MCS0_STRG_TRG8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_STRG_TRG8_SHIFT)) & GTM_gtm_cls0_MCS0_STRG_TRG8_MASK) #define GTM_gtm_cls0_MCS0_STRG_TRG9_MASK (0x200U) #define GTM_gtm_cls0_MCS0_STRG_TRG9_SHIFT (9U) #define GTM_gtm_cls0_MCS0_STRG_TRG9_WIDTH (1U) #define GTM_gtm_cls0_MCS0_STRG_TRG9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_STRG_TRG9_SHIFT)) & GTM_gtm_cls0_MCS0_STRG_TRG9_MASK) #define GTM_gtm_cls0_MCS0_STRG_TRG10_MASK (0x400U) #define GTM_gtm_cls0_MCS0_STRG_TRG10_SHIFT (10U) #define GTM_gtm_cls0_MCS0_STRG_TRG10_WIDTH (1U) #define GTM_gtm_cls0_MCS0_STRG_TRG10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_STRG_TRG10_SHIFT)) & GTM_gtm_cls0_MCS0_STRG_TRG10_MASK) #define GTM_gtm_cls0_MCS0_STRG_TRG11_MASK (0x800U) #define GTM_gtm_cls0_MCS0_STRG_TRG11_SHIFT (11U) #define GTM_gtm_cls0_MCS0_STRG_TRG11_WIDTH (1U) #define GTM_gtm_cls0_MCS0_STRG_TRG11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_STRG_TRG11_SHIFT)) & GTM_gtm_cls0_MCS0_STRG_TRG11_MASK) #define GTM_gtm_cls0_MCS0_STRG_TRG12_MASK (0x1000U) #define GTM_gtm_cls0_MCS0_STRG_TRG12_SHIFT (12U) #define GTM_gtm_cls0_MCS0_STRG_TRG12_WIDTH (1U) #define GTM_gtm_cls0_MCS0_STRG_TRG12(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_STRG_TRG12_SHIFT)) & GTM_gtm_cls0_MCS0_STRG_TRG12_MASK) #define GTM_gtm_cls0_MCS0_STRG_TRG13_MASK (0x2000U) #define GTM_gtm_cls0_MCS0_STRG_TRG13_SHIFT (13U) #define GTM_gtm_cls0_MCS0_STRG_TRG13_WIDTH (1U) #define GTM_gtm_cls0_MCS0_STRG_TRG13(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_STRG_TRG13_SHIFT)) & GTM_gtm_cls0_MCS0_STRG_TRG13_MASK) #define GTM_gtm_cls0_MCS0_STRG_TRG14_MASK (0x4000U) #define GTM_gtm_cls0_MCS0_STRG_TRG14_SHIFT (14U) #define GTM_gtm_cls0_MCS0_STRG_TRG14_WIDTH (1U) #define GTM_gtm_cls0_MCS0_STRG_TRG14(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_STRG_TRG14_SHIFT)) & GTM_gtm_cls0_MCS0_STRG_TRG14_MASK) #define GTM_gtm_cls0_MCS0_STRG_TRG15_MASK (0x8000U) #define GTM_gtm_cls0_MCS0_STRG_TRG15_SHIFT (15U) #define GTM_gtm_cls0_MCS0_STRG_TRG15_WIDTH (1U) #define GTM_gtm_cls0_MCS0_STRG_TRG15(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_STRG_TRG15_SHIFT)) & GTM_gtm_cls0_MCS0_STRG_TRG15_MASK) #define GTM_gtm_cls0_MCS0_STRG_TRG16_MASK (0x10000U) #define GTM_gtm_cls0_MCS0_STRG_TRG16_SHIFT (16U) #define GTM_gtm_cls0_MCS0_STRG_TRG16_WIDTH (1U) #define GTM_gtm_cls0_MCS0_STRG_TRG16(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_STRG_TRG16_SHIFT)) & GTM_gtm_cls0_MCS0_STRG_TRG16_MASK) #define GTM_gtm_cls0_MCS0_STRG_TRG17_MASK (0x20000U) #define GTM_gtm_cls0_MCS0_STRG_TRG17_SHIFT (17U) #define GTM_gtm_cls0_MCS0_STRG_TRG17_WIDTH (1U) #define GTM_gtm_cls0_MCS0_STRG_TRG17(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_STRG_TRG17_SHIFT)) & GTM_gtm_cls0_MCS0_STRG_TRG17_MASK) #define GTM_gtm_cls0_MCS0_STRG_TRG18_MASK (0x40000U) #define GTM_gtm_cls0_MCS0_STRG_TRG18_SHIFT (18U) #define GTM_gtm_cls0_MCS0_STRG_TRG18_WIDTH (1U) #define GTM_gtm_cls0_MCS0_STRG_TRG18(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_STRG_TRG18_SHIFT)) & GTM_gtm_cls0_MCS0_STRG_TRG18_MASK) #define GTM_gtm_cls0_MCS0_STRG_TRG19_MASK (0x80000U) #define GTM_gtm_cls0_MCS0_STRG_TRG19_SHIFT (19U) #define GTM_gtm_cls0_MCS0_STRG_TRG19_WIDTH (1U) #define GTM_gtm_cls0_MCS0_STRG_TRG19(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_STRG_TRG19_SHIFT)) & GTM_gtm_cls0_MCS0_STRG_TRG19_MASK) #define GTM_gtm_cls0_MCS0_STRG_TRG20_MASK (0x100000U) #define GTM_gtm_cls0_MCS0_STRG_TRG20_SHIFT (20U) #define GTM_gtm_cls0_MCS0_STRG_TRG20_WIDTH (1U) #define GTM_gtm_cls0_MCS0_STRG_TRG20(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_STRG_TRG20_SHIFT)) & GTM_gtm_cls0_MCS0_STRG_TRG20_MASK) #define GTM_gtm_cls0_MCS0_STRG_TRG21_MASK (0x200000U) #define GTM_gtm_cls0_MCS0_STRG_TRG21_SHIFT (21U) #define GTM_gtm_cls0_MCS0_STRG_TRG21_WIDTH (1U) #define GTM_gtm_cls0_MCS0_STRG_TRG21(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_STRG_TRG21_SHIFT)) & GTM_gtm_cls0_MCS0_STRG_TRG21_MASK) #define GTM_gtm_cls0_MCS0_STRG_TRG22_MASK (0x400000U) #define GTM_gtm_cls0_MCS0_STRG_TRG22_SHIFT (22U) #define GTM_gtm_cls0_MCS0_STRG_TRG22_WIDTH (1U) #define GTM_gtm_cls0_MCS0_STRG_TRG22(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_STRG_TRG22_SHIFT)) & GTM_gtm_cls0_MCS0_STRG_TRG22_MASK) #define GTM_gtm_cls0_MCS0_STRG_TRG23_MASK (0x800000U) #define GTM_gtm_cls0_MCS0_STRG_TRG23_SHIFT (23U) #define GTM_gtm_cls0_MCS0_STRG_TRG23_WIDTH (1U) #define GTM_gtm_cls0_MCS0_STRG_TRG23(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_STRG_TRG23_SHIFT)) & GTM_gtm_cls0_MCS0_STRG_TRG23_MASK) /*! @} */ /*! @name MCS0_CTRL_STAT - MCS[i] control and status register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CTRL_STAT_SCD_MODE_MASK (0x3U) #define GTM_gtm_cls0_MCS0_CTRL_STAT_SCD_MODE_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CTRL_STAT_SCD_MODE_WIDTH (2U) #define GTM_gtm_cls0_MCS0_CTRL_STAT_SCD_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CTRL_STAT_SCD_MODE_SHIFT)) & GTM_gtm_cls0_MCS0_CTRL_STAT_SCD_MODE_MASK) #define GTM_gtm_cls0_MCS0_CTRL_STAT_SCD_CH_MASK (0xF00U) #define GTM_gtm_cls0_MCS0_CTRL_STAT_SCD_CH_SHIFT (8U) #define GTM_gtm_cls0_MCS0_CTRL_STAT_SCD_CH_WIDTH (4U) #define GTM_gtm_cls0_MCS0_CTRL_STAT_SCD_CH(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CTRL_STAT_SCD_CH_SHIFT)) & GTM_gtm_cls0_MCS0_CTRL_STAT_SCD_CH_MASK) #define GTM_gtm_cls0_MCS0_CTRL_STAT_RAM_RST_MASK (0x10000U) #define GTM_gtm_cls0_MCS0_CTRL_STAT_RAM_RST_SHIFT (16U) #define GTM_gtm_cls0_MCS0_CTRL_STAT_RAM_RST_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CTRL_STAT_RAM_RST(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CTRL_STAT_RAM_RST_SHIFT)) & GTM_gtm_cls0_MCS0_CTRL_STAT_RAM_RST_MASK) #define GTM_gtm_cls0_MCS0_CTRL_STAT_ERR_SRC_ID_MASK (0x700000U) #define GTM_gtm_cls0_MCS0_CTRL_STAT_ERR_SRC_ID_SHIFT (20U) #define GTM_gtm_cls0_MCS0_CTRL_STAT_ERR_SRC_ID_WIDTH (3U) #define GTM_gtm_cls0_MCS0_CTRL_STAT_ERR_SRC_ID(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CTRL_STAT_ERR_SRC_ID_SHIFT)) & GTM_gtm_cls0_MCS0_CTRL_STAT_ERR_SRC_ID_MASK) #define GTM_gtm_cls0_MCS0_CTRL_STAT_EN_TIM_FOUT_MASK (0x1000000U) #define GTM_gtm_cls0_MCS0_CTRL_STAT_EN_TIM_FOUT_SHIFT (24U) #define GTM_gtm_cls0_MCS0_CTRL_STAT_EN_TIM_FOUT_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CTRL_STAT_EN_TIM_FOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CTRL_STAT_EN_TIM_FOUT_SHIFT)) & GTM_gtm_cls0_MCS0_CTRL_STAT_EN_TIM_FOUT_MASK) #define GTM_gtm_cls0_MCS0_CTRL_STAT_EN_HVD_MASK (0x2000000U) #define GTM_gtm_cls0_MCS0_CTRL_STAT_EN_HVD_SHIFT (25U) #define GTM_gtm_cls0_MCS0_CTRL_STAT_EN_HVD_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CTRL_STAT_EN_HVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CTRL_STAT_EN_HVD_SHIFT)) & GTM_gtm_cls0_MCS0_CTRL_STAT_EN_HVD_MASK) #define GTM_gtm_cls0_MCS0_CTRL_STAT_HLT_AEIM_ERR_MASK (0x4000000U) #define GTM_gtm_cls0_MCS0_CTRL_STAT_HLT_AEIM_ERR_SHIFT (26U) #define GTM_gtm_cls0_MCS0_CTRL_STAT_HLT_AEIM_ERR_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CTRL_STAT_HLT_AEIM_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CTRL_STAT_HLT_AEIM_ERR_SHIFT)) & GTM_gtm_cls0_MCS0_CTRL_STAT_HLT_AEIM_ERR_MASK) /*! @} */ /*! @name MCS0_RESET - MCS[i] reset register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_RESET_RST0_MASK (0x1U) #define GTM_gtm_cls0_MCS0_RESET_RST0_SHIFT (0U) #define GTM_gtm_cls0_MCS0_RESET_RST0_WIDTH (1U) #define GTM_gtm_cls0_MCS0_RESET_RST0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_RESET_RST0_SHIFT)) & GTM_gtm_cls0_MCS0_RESET_RST0_MASK) #define GTM_gtm_cls0_MCS0_RESET_RST1_MASK (0x2U) #define GTM_gtm_cls0_MCS0_RESET_RST1_SHIFT (1U) #define GTM_gtm_cls0_MCS0_RESET_RST1_WIDTH (1U) #define GTM_gtm_cls0_MCS0_RESET_RST1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_RESET_RST1_SHIFT)) & GTM_gtm_cls0_MCS0_RESET_RST1_MASK) #define GTM_gtm_cls0_MCS0_RESET_RST2_MASK (0x4U) #define GTM_gtm_cls0_MCS0_RESET_RST2_SHIFT (2U) #define GTM_gtm_cls0_MCS0_RESET_RST2_WIDTH (1U) #define GTM_gtm_cls0_MCS0_RESET_RST2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_RESET_RST2_SHIFT)) & GTM_gtm_cls0_MCS0_RESET_RST2_MASK) #define GTM_gtm_cls0_MCS0_RESET_RST3_MASK (0x8U) #define GTM_gtm_cls0_MCS0_RESET_RST3_SHIFT (3U) #define GTM_gtm_cls0_MCS0_RESET_RST3_WIDTH (1U) #define GTM_gtm_cls0_MCS0_RESET_RST3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_RESET_RST3_SHIFT)) & GTM_gtm_cls0_MCS0_RESET_RST3_MASK) #define GTM_gtm_cls0_MCS0_RESET_RST4_MASK (0x10U) #define GTM_gtm_cls0_MCS0_RESET_RST4_SHIFT (4U) #define GTM_gtm_cls0_MCS0_RESET_RST4_WIDTH (1U) #define GTM_gtm_cls0_MCS0_RESET_RST4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_RESET_RST4_SHIFT)) & GTM_gtm_cls0_MCS0_RESET_RST4_MASK) #define GTM_gtm_cls0_MCS0_RESET_RST5_MASK (0x20U) #define GTM_gtm_cls0_MCS0_RESET_RST5_SHIFT (5U) #define GTM_gtm_cls0_MCS0_RESET_RST5_WIDTH (1U) #define GTM_gtm_cls0_MCS0_RESET_RST5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_RESET_RST5_SHIFT)) & GTM_gtm_cls0_MCS0_RESET_RST5_MASK) #define GTM_gtm_cls0_MCS0_RESET_RST6_MASK (0x40U) #define GTM_gtm_cls0_MCS0_RESET_RST6_SHIFT (6U) #define GTM_gtm_cls0_MCS0_RESET_RST6_WIDTH (1U) #define GTM_gtm_cls0_MCS0_RESET_RST6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_RESET_RST6_SHIFT)) & GTM_gtm_cls0_MCS0_RESET_RST6_MASK) #define GTM_gtm_cls0_MCS0_RESET_RST7_MASK (0x80U) #define GTM_gtm_cls0_MCS0_RESET_RST7_SHIFT (7U) #define GTM_gtm_cls0_MCS0_RESET_RST7_WIDTH (1U) #define GTM_gtm_cls0_MCS0_RESET_RST7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_RESET_RST7_SHIFT)) & GTM_gtm_cls0_MCS0_RESET_RST7_MASK) /*! @} */ /*! @name MCS0_CAT - MCS[i] cancel ARU transfer instruction */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CAT_CAT0_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CAT_CAT0_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CAT_CAT0_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CAT_CAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CAT_CAT0_SHIFT)) & GTM_gtm_cls0_MCS0_CAT_CAT0_MASK) #define GTM_gtm_cls0_MCS0_CAT_CAT1_MASK (0x2U) #define GTM_gtm_cls0_MCS0_CAT_CAT1_SHIFT (1U) #define GTM_gtm_cls0_MCS0_CAT_CAT1_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CAT_CAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CAT_CAT1_SHIFT)) & GTM_gtm_cls0_MCS0_CAT_CAT1_MASK) #define GTM_gtm_cls0_MCS0_CAT_CAT2_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CAT_CAT2_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CAT_CAT2_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CAT_CAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CAT_CAT2_SHIFT)) & GTM_gtm_cls0_MCS0_CAT_CAT2_MASK) #define GTM_gtm_cls0_MCS0_CAT_CAT3_MASK (0x8U) #define GTM_gtm_cls0_MCS0_CAT_CAT3_SHIFT (3U) #define GTM_gtm_cls0_MCS0_CAT_CAT3_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CAT_CAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CAT_CAT3_SHIFT)) & GTM_gtm_cls0_MCS0_CAT_CAT3_MASK) #define GTM_gtm_cls0_MCS0_CAT_CAT4_MASK (0x10U) #define GTM_gtm_cls0_MCS0_CAT_CAT4_SHIFT (4U) #define GTM_gtm_cls0_MCS0_CAT_CAT4_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CAT_CAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CAT_CAT4_SHIFT)) & GTM_gtm_cls0_MCS0_CAT_CAT4_MASK) #define GTM_gtm_cls0_MCS0_CAT_CAT5_MASK (0x20U) #define GTM_gtm_cls0_MCS0_CAT_CAT5_SHIFT (5U) #define GTM_gtm_cls0_MCS0_CAT_CAT5_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CAT_CAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CAT_CAT5_SHIFT)) & GTM_gtm_cls0_MCS0_CAT_CAT5_MASK) #define GTM_gtm_cls0_MCS0_CAT_CAT6_MASK (0x40U) #define GTM_gtm_cls0_MCS0_CAT_CAT6_SHIFT (6U) #define GTM_gtm_cls0_MCS0_CAT_CAT6_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CAT_CAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CAT_CAT6_SHIFT)) & GTM_gtm_cls0_MCS0_CAT_CAT6_MASK) #define GTM_gtm_cls0_MCS0_CAT_CAT7_MASK (0x80U) #define GTM_gtm_cls0_MCS0_CAT_CAT7_SHIFT (7U) #define GTM_gtm_cls0_MCS0_CAT_CAT7_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CAT_CAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CAT_CAT7_SHIFT)) & GTM_gtm_cls0_MCS0_CAT_CAT7_MASK) /*! @} */ /*! @name MCS0_CWT - MCS[i] cancel waiting instruction */ /*! @{ */ #define GTM_gtm_cls0_MCS0_CWT_CWT0_MASK (0x1U) #define GTM_gtm_cls0_MCS0_CWT_CWT0_SHIFT (0U) #define GTM_gtm_cls0_MCS0_CWT_CWT0_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CWT_CWT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CWT_CWT0_SHIFT)) & GTM_gtm_cls0_MCS0_CWT_CWT0_MASK) #define GTM_gtm_cls0_MCS0_CWT_CWT1_MASK (0x2U) #define GTM_gtm_cls0_MCS0_CWT_CWT1_SHIFT (1U) #define GTM_gtm_cls0_MCS0_CWT_CWT1_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CWT_CWT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CWT_CWT1_SHIFT)) & GTM_gtm_cls0_MCS0_CWT_CWT1_MASK) #define GTM_gtm_cls0_MCS0_CWT_CWT2_MASK (0x4U) #define GTM_gtm_cls0_MCS0_CWT_CWT2_SHIFT (2U) #define GTM_gtm_cls0_MCS0_CWT_CWT2_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CWT_CWT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CWT_CWT2_SHIFT)) & GTM_gtm_cls0_MCS0_CWT_CWT2_MASK) #define GTM_gtm_cls0_MCS0_CWT_CWT3_MASK (0x8U) #define GTM_gtm_cls0_MCS0_CWT_CWT3_SHIFT (3U) #define GTM_gtm_cls0_MCS0_CWT_CWT3_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CWT_CWT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CWT_CWT3_SHIFT)) & GTM_gtm_cls0_MCS0_CWT_CWT3_MASK) #define GTM_gtm_cls0_MCS0_CWT_CWT4_MASK (0x10U) #define GTM_gtm_cls0_MCS0_CWT_CWT4_SHIFT (4U) #define GTM_gtm_cls0_MCS0_CWT_CWT4_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CWT_CWT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CWT_CWT4_SHIFT)) & GTM_gtm_cls0_MCS0_CWT_CWT4_MASK) #define GTM_gtm_cls0_MCS0_CWT_CWT5_MASK (0x20U) #define GTM_gtm_cls0_MCS0_CWT_CWT5_SHIFT (5U) #define GTM_gtm_cls0_MCS0_CWT_CWT5_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CWT_CWT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CWT_CWT5_SHIFT)) & GTM_gtm_cls0_MCS0_CWT_CWT5_MASK) #define GTM_gtm_cls0_MCS0_CWT_CWT6_MASK (0x40U) #define GTM_gtm_cls0_MCS0_CWT_CWT6_SHIFT (6U) #define GTM_gtm_cls0_MCS0_CWT_CWT6_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CWT_CWT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CWT_CWT6_SHIFT)) & GTM_gtm_cls0_MCS0_CWT_CWT6_MASK) #define GTM_gtm_cls0_MCS0_CWT_CWT7_MASK (0x80U) #define GTM_gtm_cls0_MCS0_CWT_CWT7_SHIFT (7U) #define GTM_gtm_cls0_MCS0_CWT_CWT7_WIDTH (1U) #define GTM_gtm_cls0_MCS0_CWT_CWT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_CWT_CWT7_SHIFT)) & GTM_gtm_cls0_MCS0_CWT_CWT7_MASK) /*! @} */ /*! @name MCS0_ERR - MCS[i] error register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_ERR_ERR0_MASK (0x1U) #define GTM_gtm_cls0_MCS0_ERR_ERR0_SHIFT (0U) #define GTM_gtm_cls0_MCS0_ERR_ERR0_WIDTH (1U) #define GTM_gtm_cls0_MCS0_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_ERR_ERR0_SHIFT)) & GTM_gtm_cls0_MCS0_ERR_ERR0_MASK) #define GTM_gtm_cls0_MCS0_ERR_ERR1_MASK (0x2U) #define GTM_gtm_cls0_MCS0_ERR_ERR1_SHIFT (1U) #define GTM_gtm_cls0_MCS0_ERR_ERR1_WIDTH (1U) #define GTM_gtm_cls0_MCS0_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_ERR_ERR1_SHIFT)) & GTM_gtm_cls0_MCS0_ERR_ERR1_MASK) #define GTM_gtm_cls0_MCS0_ERR_ERR2_MASK (0x4U) #define GTM_gtm_cls0_MCS0_ERR_ERR2_SHIFT (2U) #define GTM_gtm_cls0_MCS0_ERR_ERR2_WIDTH (1U) #define GTM_gtm_cls0_MCS0_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_ERR_ERR2_SHIFT)) & GTM_gtm_cls0_MCS0_ERR_ERR2_MASK) #define GTM_gtm_cls0_MCS0_ERR_ERR3_MASK (0x8U) #define GTM_gtm_cls0_MCS0_ERR_ERR3_SHIFT (3U) #define GTM_gtm_cls0_MCS0_ERR_ERR3_WIDTH (1U) #define GTM_gtm_cls0_MCS0_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_ERR_ERR3_SHIFT)) & GTM_gtm_cls0_MCS0_ERR_ERR3_MASK) #define GTM_gtm_cls0_MCS0_ERR_ERR4_MASK (0x10U) #define GTM_gtm_cls0_MCS0_ERR_ERR4_SHIFT (4U) #define GTM_gtm_cls0_MCS0_ERR_ERR4_WIDTH (1U) #define GTM_gtm_cls0_MCS0_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_ERR_ERR4_SHIFT)) & GTM_gtm_cls0_MCS0_ERR_ERR4_MASK) #define GTM_gtm_cls0_MCS0_ERR_ERR5_MASK (0x20U) #define GTM_gtm_cls0_MCS0_ERR_ERR5_SHIFT (5U) #define GTM_gtm_cls0_MCS0_ERR_ERR5_WIDTH (1U) #define GTM_gtm_cls0_MCS0_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_ERR_ERR5_SHIFT)) & GTM_gtm_cls0_MCS0_ERR_ERR5_MASK) #define GTM_gtm_cls0_MCS0_ERR_ERR6_MASK (0x40U) #define GTM_gtm_cls0_MCS0_ERR_ERR6_SHIFT (6U) #define GTM_gtm_cls0_MCS0_ERR_ERR6_WIDTH (1U) #define GTM_gtm_cls0_MCS0_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_ERR_ERR6_SHIFT)) & GTM_gtm_cls0_MCS0_ERR_ERR6_MASK) #define GTM_gtm_cls0_MCS0_ERR_ERR7_MASK (0x80U) #define GTM_gtm_cls0_MCS0_ERR_ERR7_SHIFT (7U) #define GTM_gtm_cls0_MCS0_ERR_ERR7_WIDTH (1U) #define GTM_gtm_cls0_MCS0_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_ERR_ERR7_SHIFT)) & GTM_gtm_cls0_MCS0_ERR_ERR7_MASK) /*! @} */ /*! @name MCS0_REG_PROT - MCS[i] write protection register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT0_MASK (0x3U) #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT0_SHIFT (0U) #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT0_WIDTH (2U) #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_REG_PROT_WPROT0_SHIFT)) & GTM_gtm_cls0_MCS0_REG_PROT_WPROT0_MASK) #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT1_MASK (0xCU) #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT1_SHIFT (2U) #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT1_WIDTH (2U) #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_REG_PROT_WPROT1_SHIFT)) & GTM_gtm_cls0_MCS0_REG_PROT_WPROT1_MASK) #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT2_MASK (0x30U) #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT2_SHIFT (4U) #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT2_WIDTH (2U) #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_REG_PROT_WPROT2_SHIFT)) & GTM_gtm_cls0_MCS0_REG_PROT_WPROT2_MASK) #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT3_MASK (0xC0U) #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT3_SHIFT (6U) #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT3_WIDTH (2U) #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_REG_PROT_WPROT3_SHIFT)) & GTM_gtm_cls0_MCS0_REG_PROT_WPROT3_MASK) #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT4_MASK (0x300U) #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT4_SHIFT (8U) #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT4_WIDTH (2U) #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_REG_PROT_WPROT4_SHIFT)) & GTM_gtm_cls0_MCS0_REG_PROT_WPROT4_MASK) #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT5_MASK (0xC00U) #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT5_SHIFT (10U) #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT5_WIDTH (2U) #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_REG_PROT_WPROT5_SHIFT)) & GTM_gtm_cls0_MCS0_REG_PROT_WPROT5_MASK) #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT6_MASK (0x3000U) #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT6_SHIFT (12U) #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT6_WIDTH (2U) #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_REG_PROT_WPROT6_SHIFT)) & GTM_gtm_cls0_MCS0_REG_PROT_WPROT6_MASK) #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT7_MASK (0xC000U) #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT7_SHIFT (14U) #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT7_WIDTH (2U) #define GTM_gtm_cls0_MCS0_REG_PROT_WPROT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_REG_PROT_WPROT7_SHIFT)) & GTM_gtm_cls0_MCS0_REG_PROT_WPROT7_MASK) /*! @} */ /*! @name MCS0_SINT_IRQ_NOTIFY - MCS[i] shared interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ0_MASK (0x1U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ0_SHIFT (0U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ0_WIDTH (1U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ0_SHIFT)) & GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ0_MASK) #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ1_MASK (0x2U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ1_SHIFT (1U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ1_WIDTH (1U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ1_SHIFT)) & GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ1_MASK) #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ2_MASK (0x4U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ2_SHIFT (2U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ2_WIDTH (1U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ2_SHIFT)) & GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ2_MASK) #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ3_MASK (0x8U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ3_SHIFT (3U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ3_WIDTH (1U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ3_SHIFT)) & GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ3_MASK) #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ4_MASK (0x10U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ4_SHIFT (4U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ4_WIDTH (1U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ4_SHIFT)) & GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ4_MASK) #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ5_MASK (0x20U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ5_SHIFT (5U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ5_WIDTH (1U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ5_SHIFT)) & GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ5_MASK) #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ6_MASK (0x40U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ6_SHIFT (6U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ6_WIDTH (1U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ6_SHIFT)) & GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ6_MASK) #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ7_MASK (0x80U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ7_SHIFT (7U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ7_WIDTH (1U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ7_SHIFT)) & GTM_gtm_cls0_MCS0_SINT_IRQ_NOTIFY_S_IRQ7_MASK) /*! @} */ /*! @name MCS0_SINT_IRQ_EN - MCS[i] shared interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ0_EN_MASK (0x1U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ0_EN_SHIFT (0U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ0_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ0_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ0_EN_SHIFT)) & GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ0_EN_MASK) #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ1_EN_MASK (0x2U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ1_EN_SHIFT (1U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ1_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ1_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ1_EN_SHIFT)) & GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ1_EN_MASK) #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ2_EN_MASK (0x4U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ2_EN_SHIFT (2U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ2_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ2_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ2_EN_SHIFT)) & GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ2_EN_MASK) #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ3_EN_MASK (0x8U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ3_EN_SHIFT (3U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ3_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ3_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ3_EN_SHIFT)) & GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ3_EN_MASK) #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ4_EN_MASK (0x10U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ4_EN_SHIFT (4U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ4_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ4_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ4_EN_SHIFT)) & GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ4_EN_MASK) #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ5_EN_MASK (0x20U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ5_EN_SHIFT (5U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ5_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ5_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ5_EN_SHIFT)) & GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ5_EN_MASK) #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ6_EN_MASK (0x40U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ6_EN_SHIFT (6U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ6_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ6_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ6_EN_SHIFT)) & GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ6_EN_MASK) #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ7_EN_MASK (0x80U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ7_EN_SHIFT (7U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ7_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ7_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ7_EN_SHIFT)) & GTM_gtm_cls0_MCS0_SINT_IRQ_EN_S_IRQ7_EN_MASK) /*! @} */ /*! @name MCS0_SINT_IRQ_FORCINT - MCS[i] force shared interrupt register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ0_MASK (0x1U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ0_SHIFT (0U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ0_WIDTH (1U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ0_SHIFT)) & GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ0_MASK) #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ1_MASK (0x2U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ1_SHIFT (1U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ1_WIDTH (1U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ1_SHIFT)) & GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ1_MASK) #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ2_MASK (0x4U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ2_SHIFT (2U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ2_WIDTH (1U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ2_SHIFT)) & GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ2_MASK) #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ3_MASK (0x8U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ3_SHIFT (3U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ3_WIDTH (1U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ3_SHIFT)) & GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ3_MASK) #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ4_MASK (0x10U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ4_SHIFT (4U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ4_WIDTH (1U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ4_SHIFT)) & GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ4_MASK) #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ5_MASK (0x20U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ5_SHIFT (5U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ5_WIDTH (1U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ5_SHIFT)) & GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ5_MASK) #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ6_MASK (0x40U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ6_SHIFT (6U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ6_WIDTH (1U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ6_SHIFT)) & GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ6_MASK) #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ7_MASK (0x80U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ7_SHIFT (7U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ7_WIDTH (1U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ7_SHIFT)) & GTM_gtm_cls0_MCS0_SINT_IRQ_FORCINT_TRG_S_IRQ7_MASK) /*! @} */ /*! @name MCS0_SINT_IRQ_MODE - MCS[i] shared interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_SINT_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_MCS0_SINT_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_SINT_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_MCS0_SINT_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name MCS0_HBP0_CTRL - MCS[i] hardware break point h control register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH0_MASK (0x1U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH0_SHIFT (0U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH0_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH0_SHIFT)) & GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH0_MASK) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH1_MASK (0x2U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH1_SHIFT (1U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH1_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH1_SHIFT)) & GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH1_MASK) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH2_MASK (0x4U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH2_SHIFT (2U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH2_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH2_SHIFT)) & GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH2_MASK) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH3_MASK (0x8U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH3_SHIFT (3U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH3_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH3_SHIFT)) & GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH3_MASK) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH4_MASK (0x10U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH4_SHIFT (4U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH4_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH4_SHIFT)) & GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH4_MASK) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH5_MASK (0x20U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH5_SHIFT (5U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH5_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH5_SHIFT)) & GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH5_MASK) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH6_MASK (0x40U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH6_SHIFT (6U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH6_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH6_SHIFT)) & GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH6_MASK) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH7_MASK (0x80U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH7_SHIFT (7U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH7_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH7_SHIFT)) & GTM_gtm_cls0_MCS0_HBP0_CTRL_EN_CH7_MASK) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_SCOPE_MASK (0x300U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_SCOPE_SHIFT (8U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_SCOPE_WIDTH (2U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_SCOPE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP0_CTRL_SCOPE_SHIFT)) & GTM_gtm_cls0_MCS0_HBP0_CTRL_SCOPE_MASK) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_TYPE_MASK (0x7000U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_TYPE_SHIFT (12U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_TYPE_WIDTH (3U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP0_CTRL_TYPE_SHIFT)) & GTM_gtm_cls0_MCS0_HBP0_CTRL_TYPE_MASK) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_AND_MASK (0x10000U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_AND_SHIFT (16U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_AND_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_AND(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP0_CTRL_AND_SHIFT)) & GTM_gtm_cls0_MCS0_HBP0_CTRL_AND_MASK) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_NOT_MASK (0x20000U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_NOT_SHIFT (17U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_NOT_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP0_CTRL_NOT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP0_CTRL_NOT_SHIFT)) & GTM_gtm_cls0_MCS0_HBP0_CTRL_NOT_MASK) /*! @} */ /*! @name MCS0_HBP0_PATTERN - MCS[i] hardware break point pattern register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_HBP0_PATTERN_DATA_MASK (0xFFFFFFFFU) #define GTM_gtm_cls0_MCS0_HBP0_PATTERN_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_HBP0_PATTERN_DATA_WIDTH (32U) #define GTM_gtm_cls0_MCS0_HBP0_PATTERN_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP0_PATTERN_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_HBP0_PATTERN_DATA_MASK) /*! @} */ /*! @name MCS0_HBP0_STATUS - MCS[i] hardware break point status register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH0_MASK (0x1U) #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH0_SHIFT (0U) #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH0_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH0_SHIFT)) & GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH0_MASK) #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH1_MASK (0x2U) #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH1_SHIFT (1U) #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH1_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH1_SHIFT)) & GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH1_MASK) #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH2_MASK (0x4U) #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH2_SHIFT (2U) #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH2_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH2_SHIFT)) & GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH2_MASK) #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH3_MASK (0x8U) #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH3_SHIFT (3U) #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH3_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH3_SHIFT)) & GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH3_MASK) #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH4_MASK (0x10U) #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH4_SHIFT (4U) #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH4_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH4_SHIFT)) & GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH4_MASK) #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH5_MASK (0x20U) #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH5_SHIFT (5U) #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH5_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH5_SHIFT)) & GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH5_MASK) #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH6_MASK (0x40U) #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH6_SHIFT (6U) #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH6_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH6_SHIFT)) & GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH6_MASK) #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH7_MASK (0x80U) #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH7_SHIFT (7U) #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH7_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH7_SHIFT)) & GTM_gtm_cls0_MCS0_HBP0_STATUS_HALT_CH7_MASK) /*! @} */ /*! @name MCS0_HBP0_IRQ_NOTIFY - MCS[i] hardware break point interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_HBP0_IRQ_NOTIFY_HBP_IRQ_MASK (0x1U) #define GTM_gtm_cls0_MCS0_HBP0_IRQ_NOTIFY_HBP_IRQ_SHIFT (0U) #define GTM_gtm_cls0_MCS0_HBP0_IRQ_NOTIFY_HBP_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP0_IRQ_NOTIFY_HBP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP0_IRQ_NOTIFY_HBP_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_HBP0_IRQ_NOTIFY_HBP_IRQ_MASK) /*! @} */ /*! @name MCS0_HBP0_IRQ_EN - MCS[i] hardware break point interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_HBP0_IRQ_EN_HBP_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_MCS0_HBP0_IRQ_EN_HBP_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_MCS0_HBP0_IRQ_EN_HBP_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP0_IRQ_EN_HBP_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP0_IRQ_EN_HBP_IRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_HBP0_IRQ_EN_HBP_IRQ_EN_MASK) /*! @} */ /*! @name MCS0_HBP0_IRQ_FORCINT - MCS[i] force hardware break point interrupt register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_HBP0_IRQ_FORCINT_TRG_HBP_IRQ_MASK (0x1U) #define GTM_gtm_cls0_MCS0_HBP0_IRQ_FORCINT_TRG_HBP_IRQ_SHIFT (0U) #define GTM_gtm_cls0_MCS0_HBP0_IRQ_FORCINT_TRG_HBP_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP0_IRQ_FORCINT_TRG_HBP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP0_IRQ_FORCINT_TRG_HBP_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_HBP0_IRQ_FORCINT_TRG_HBP_IRQ_MASK) /*! @} */ /*! @name MCS0_HBP0_IRQ_MODE - MCS[i] break point h interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_HBP0_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_MCS0_HBP0_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_MCS0_HBP0_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_MCS0_HBP0_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP0_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_MCS0_HBP0_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name MCS0_HBP1_CTRL - MCS[i] hardware break point h control register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH0_MASK (0x1U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH0_SHIFT (0U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH0_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH0_SHIFT)) & GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH0_MASK) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH1_MASK (0x2U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH1_SHIFT (1U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH1_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH1_SHIFT)) & GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH1_MASK) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH2_MASK (0x4U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH2_SHIFT (2U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH2_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH2_SHIFT)) & GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH2_MASK) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH3_MASK (0x8U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH3_SHIFT (3U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH3_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH3_SHIFT)) & GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH3_MASK) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH4_MASK (0x10U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH4_SHIFT (4U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH4_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH4_SHIFT)) & GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH4_MASK) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH5_MASK (0x20U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH5_SHIFT (5U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH5_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH5_SHIFT)) & GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH5_MASK) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH6_MASK (0x40U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH6_SHIFT (6U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH6_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH6_SHIFT)) & GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH6_MASK) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH7_MASK (0x80U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH7_SHIFT (7U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH7_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH7_SHIFT)) & GTM_gtm_cls0_MCS0_HBP1_CTRL_EN_CH7_MASK) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_SCOPE_MASK (0x300U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_SCOPE_SHIFT (8U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_SCOPE_WIDTH (2U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_SCOPE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP1_CTRL_SCOPE_SHIFT)) & GTM_gtm_cls0_MCS0_HBP1_CTRL_SCOPE_MASK) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_TYPE_MASK (0x7000U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_TYPE_SHIFT (12U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_TYPE_WIDTH (3U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP1_CTRL_TYPE_SHIFT)) & GTM_gtm_cls0_MCS0_HBP1_CTRL_TYPE_MASK) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_AND_MASK (0x10000U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_AND_SHIFT (16U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_AND_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_AND(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP1_CTRL_AND_SHIFT)) & GTM_gtm_cls0_MCS0_HBP1_CTRL_AND_MASK) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_NOT_MASK (0x20000U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_NOT_SHIFT (17U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_NOT_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP1_CTRL_NOT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP1_CTRL_NOT_SHIFT)) & GTM_gtm_cls0_MCS0_HBP1_CTRL_NOT_MASK) /*! @} */ /*! @name MCS0_HBP1_PATTERN - MCS[i] hardware break point pattern register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_HBP1_PATTERN_DATA_MASK (0xFFFFFFFFU) #define GTM_gtm_cls0_MCS0_HBP1_PATTERN_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_HBP1_PATTERN_DATA_WIDTH (32U) #define GTM_gtm_cls0_MCS0_HBP1_PATTERN_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP1_PATTERN_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_HBP1_PATTERN_DATA_MASK) /*! @} */ /*! @name MCS0_HBP1_STATUS - MCS[i] hardware break point status register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH0_MASK (0x1U) #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH0_SHIFT (0U) #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH0_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH0_SHIFT)) & GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH0_MASK) #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH1_MASK (0x2U) #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH1_SHIFT (1U) #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH1_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH1_SHIFT)) & GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH1_MASK) #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH2_MASK (0x4U) #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH2_SHIFT (2U) #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH2_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH2_SHIFT)) & GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH2_MASK) #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH3_MASK (0x8U) #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH3_SHIFT (3U) #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH3_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH3_SHIFT)) & GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH3_MASK) #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH4_MASK (0x10U) #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH4_SHIFT (4U) #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH4_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH4_SHIFT)) & GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH4_MASK) #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH5_MASK (0x20U) #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH5_SHIFT (5U) #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH5_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH5_SHIFT)) & GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH5_MASK) #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH6_MASK (0x40U) #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH6_SHIFT (6U) #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH6_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH6_SHIFT)) & GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH6_MASK) #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH7_MASK (0x80U) #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH7_SHIFT (7U) #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH7_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH7_SHIFT)) & GTM_gtm_cls0_MCS0_HBP1_STATUS_HALT_CH7_MASK) /*! @} */ /*! @name MCS0_HBP1_IRQ_NOTIFY - MCS[i] hardware break point interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_HBP1_IRQ_NOTIFY_HBP_IRQ_MASK (0x1U) #define GTM_gtm_cls0_MCS0_HBP1_IRQ_NOTIFY_HBP_IRQ_SHIFT (0U) #define GTM_gtm_cls0_MCS0_HBP1_IRQ_NOTIFY_HBP_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP1_IRQ_NOTIFY_HBP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP1_IRQ_NOTIFY_HBP_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_HBP1_IRQ_NOTIFY_HBP_IRQ_MASK) /*! @} */ /*! @name MCS0_HBP1_IRQ_EN - MCS[i] hardware break point interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_HBP1_IRQ_EN_HBP_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_MCS0_HBP1_IRQ_EN_HBP_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_MCS0_HBP1_IRQ_EN_HBP_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP1_IRQ_EN_HBP_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP1_IRQ_EN_HBP_IRQ_EN_SHIFT)) & GTM_gtm_cls0_MCS0_HBP1_IRQ_EN_HBP_IRQ_EN_MASK) /*! @} */ /*! @name MCS0_HBP1_IRQ_FORCINT - MCS[i] force hardware break point interrupt register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_HBP1_IRQ_FORCINT_TRG_HBP_IRQ_MASK (0x1U) #define GTM_gtm_cls0_MCS0_HBP1_IRQ_FORCINT_TRG_HBP_IRQ_SHIFT (0U) #define GTM_gtm_cls0_MCS0_HBP1_IRQ_FORCINT_TRG_HBP_IRQ_WIDTH (1U) #define GTM_gtm_cls0_MCS0_HBP1_IRQ_FORCINT_TRG_HBP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP1_IRQ_FORCINT_TRG_HBP_IRQ_SHIFT)) & GTM_gtm_cls0_MCS0_HBP1_IRQ_FORCINT_TRG_HBP_IRQ_MASK) /*! @} */ /*! @name MCS0_HBP1_IRQ_MODE - MCS[i] break point h interrupt mode configuration register */ /*! @{ */ #define GTM_gtm_cls0_MCS0_HBP1_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_MCS0_HBP1_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_MCS0_HBP1_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_MCS0_HBP1_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_HBP1_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_MCS0_HBP1_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name CCM0_ARP0_CTRL - CCM[i] Address Range Protector [a] Control Register */ /*! @{ */ #define GTM_gtm_cls0_CCM0_ARP0_CTRL_ADDR_MASK (0xFFFFU) #define GTM_gtm_cls0_CCM0_ARP0_CTRL_ADDR_SHIFT (0U) #define GTM_gtm_cls0_CCM0_ARP0_CTRL_ADDR_WIDTH (16U) #define GTM_gtm_cls0_CCM0_ARP0_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP0_CTRL_ADDR_SHIFT)) & GTM_gtm_cls0_CCM0_ARP0_CTRL_ADDR_MASK) #define GTM_gtm_cls0_CCM0_ARP0_CTRL_SIZE_MASK (0xF0000U) #define GTM_gtm_cls0_CCM0_ARP0_CTRL_SIZE_SHIFT (16U) #define GTM_gtm_cls0_CCM0_ARP0_CTRL_SIZE_WIDTH (4U) #define GTM_gtm_cls0_CCM0_ARP0_CTRL_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP0_CTRL_SIZE_SHIFT)) & GTM_gtm_cls0_CCM0_ARP0_CTRL_SIZE_MASK) #define GTM_gtm_cls0_CCM0_ARP0_CTRL_DIS_PROT_MASK (0x1000000U) #define GTM_gtm_cls0_CCM0_ARP0_CTRL_DIS_PROT_SHIFT (24U) #define GTM_gtm_cls0_CCM0_ARP0_CTRL_DIS_PROT_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP0_CTRL_DIS_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP0_CTRL_DIS_PROT_SHIFT)) & GTM_gtm_cls0_CCM0_ARP0_CTRL_DIS_PROT_MASK) #define GTM_gtm_cls0_CCM0_ARP0_CTRL_WPROT_AEI_MASK (0x80000000U) #define GTM_gtm_cls0_CCM0_ARP0_CTRL_WPROT_AEI_SHIFT (31U) #define GTM_gtm_cls0_CCM0_ARP0_CTRL_WPROT_AEI_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP0_CTRL_WPROT_AEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP0_CTRL_WPROT_AEI_SHIFT)) & GTM_gtm_cls0_CCM0_ARP0_CTRL_WPROT_AEI_MASK) /*! @} */ /*! @name CCM0_ARP0_PROT - CCM[i] Address Range Protector [a] Protection Register */ /*! @{ */ #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT0_MASK (0x1U) #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT0_SHIFT (0U) #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT0_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT0_SHIFT)) & GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT0_MASK) #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT1_MASK (0x2U) #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT1_SHIFT (1U) #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT1_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT1_SHIFT)) & GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT1_MASK) #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT2_MASK (0x4U) #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT2_SHIFT (2U) #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT2_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT2_SHIFT)) & GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT2_MASK) #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT3_MASK (0x8U) #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT3_SHIFT (3U) #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT3_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT3_SHIFT)) & GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT3_MASK) #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT4_MASK (0x10U) #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT4_SHIFT (4U) #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT4_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT4_SHIFT)) & GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT4_MASK) #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT5_MASK (0x20U) #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT5_SHIFT (5U) #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT5_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT5_SHIFT)) & GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT5_MASK) #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT6_MASK (0x40U) #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT6_SHIFT (6U) #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT6_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT6_SHIFT)) & GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT6_MASK) #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT7_MASK (0x80U) #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT7_SHIFT (7U) #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT7_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT7_SHIFT)) & GTM_gtm_cls0_CCM0_ARP0_PROT_WPROT7_MASK) /*! @} */ /*! @name CCM0_ARP1_CTRL - CCM[i] Address Range Protector [a] Control Register */ /*! @{ */ #define GTM_gtm_cls0_CCM0_ARP1_CTRL_ADDR_MASK (0xFFFFU) #define GTM_gtm_cls0_CCM0_ARP1_CTRL_ADDR_SHIFT (0U) #define GTM_gtm_cls0_CCM0_ARP1_CTRL_ADDR_WIDTH (16U) #define GTM_gtm_cls0_CCM0_ARP1_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP1_CTRL_ADDR_SHIFT)) & GTM_gtm_cls0_CCM0_ARP1_CTRL_ADDR_MASK) #define GTM_gtm_cls0_CCM0_ARP1_CTRL_SIZE_MASK (0xF0000U) #define GTM_gtm_cls0_CCM0_ARP1_CTRL_SIZE_SHIFT (16U) #define GTM_gtm_cls0_CCM0_ARP1_CTRL_SIZE_WIDTH (4U) #define GTM_gtm_cls0_CCM0_ARP1_CTRL_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP1_CTRL_SIZE_SHIFT)) & GTM_gtm_cls0_CCM0_ARP1_CTRL_SIZE_MASK) #define GTM_gtm_cls0_CCM0_ARP1_CTRL_DIS_PROT_MASK (0x1000000U) #define GTM_gtm_cls0_CCM0_ARP1_CTRL_DIS_PROT_SHIFT (24U) #define GTM_gtm_cls0_CCM0_ARP1_CTRL_DIS_PROT_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP1_CTRL_DIS_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP1_CTRL_DIS_PROT_SHIFT)) & GTM_gtm_cls0_CCM0_ARP1_CTRL_DIS_PROT_MASK) #define GTM_gtm_cls0_CCM0_ARP1_CTRL_WPROT_AEI_MASK (0x80000000U) #define GTM_gtm_cls0_CCM0_ARP1_CTRL_WPROT_AEI_SHIFT (31U) #define GTM_gtm_cls0_CCM0_ARP1_CTRL_WPROT_AEI_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP1_CTRL_WPROT_AEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP1_CTRL_WPROT_AEI_SHIFT)) & GTM_gtm_cls0_CCM0_ARP1_CTRL_WPROT_AEI_MASK) /*! @} */ /*! @name CCM0_ARP1_PROT - CCM[i] Address Range Protector [a] Protection Register */ /*! @{ */ #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT0_MASK (0x1U) #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT0_SHIFT (0U) #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT0_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT0_SHIFT)) & GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT0_MASK) #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT1_MASK (0x2U) #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT1_SHIFT (1U) #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT1_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT1_SHIFT)) & GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT1_MASK) #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT2_MASK (0x4U) #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT2_SHIFT (2U) #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT2_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT2_SHIFT)) & GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT2_MASK) #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT3_MASK (0x8U) #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT3_SHIFT (3U) #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT3_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT3_SHIFT)) & GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT3_MASK) #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT4_MASK (0x10U) #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT4_SHIFT (4U) #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT4_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT4_SHIFT)) & GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT4_MASK) #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT5_MASK (0x20U) #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT5_SHIFT (5U) #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT5_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT5_SHIFT)) & GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT5_MASK) #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT6_MASK (0x40U) #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT6_SHIFT (6U) #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT6_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT6_SHIFT)) & GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT6_MASK) #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT7_MASK (0x80U) #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT7_SHIFT (7U) #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT7_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT7_SHIFT)) & GTM_gtm_cls0_CCM0_ARP1_PROT_WPROT7_MASK) /*! @} */ /*! @name CCM0_ARP2_CTRL - CCM[i] Address Range Protector [a] Control Register */ /*! @{ */ #define GTM_gtm_cls0_CCM0_ARP2_CTRL_ADDR_MASK (0xFFFFU) #define GTM_gtm_cls0_CCM0_ARP2_CTRL_ADDR_SHIFT (0U) #define GTM_gtm_cls0_CCM0_ARP2_CTRL_ADDR_WIDTH (16U) #define GTM_gtm_cls0_CCM0_ARP2_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP2_CTRL_ADDR_SHIFT)) & GTM_gtm_cls0_CCM0_ARP2_CTRL_ADDR_MASK) #define GTM_gtm_cls0_CCM0_ARP2_CTRL_SIZE_MASK (0xF0000U) #define GTM_gtm_cls0_CCM0_ARP2_CTRL_SIZE_SHIFT (16U) #define GTM_gtm_cls0_CCM0_ARP2_CTRL_SIZE_WIDTH (4U) #define GTM_gtm_cls0_CCM0_ARP2_CTRL_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP2_CTRL_SIZE_SHIFT)) & GTM_gtm_cls0_CCM0_ARP2_CTRL_SIZE_MASK) #define GTM_gtm_cls0_CCM0_ARP2_CTRL_DIS_PROT_MASK (0x1000000U) #define GTM_gtm_cls0_CCM0_ARP2_CTRL_DIS_PROT_SHIFT (24U) #define GTM_gtm_cls0_CCM0_ARP2_CTRL_DIS_PROT_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP2_CTRL_DIS_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP2_CTRL_DIS_PROT_SHIFT)) & GTM_gtm_cls0_CCM0_ARP2_CTRL_DIS_PROT_MASK) #define GTM_gtm_cls0_CCM0_ARP2_CTRL_WPROT_AEI_MASK (0x80000000U) #define GTM_gtm_cls0_CCM0_ARP2_CTRL_WPROT_AEI_SHIFT (31U) #define GTM_gtm_cls0_CCM0_ARP2_CTRL_WPROT_AEI_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP2_CTRL_WPROT_AEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP2_CTRL_WPROT_AEI_SHIFT)) & GTM_gtm_cls0_CCM0_ARP2_CTRL_WPROT_AEI_MASK) /*! @} */ /*! @name CCM0_ARP2_PROT - CCM[i] Address Range Protector [a] Protection Register */ /*! @{ */ #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT0_MASK (0x1U) #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT0_SHIFT (0U) #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT0_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT0_SHIFT)) & GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT0_MASK) #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT1_MASK (0x2U) #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT1_SHIFT (1U) #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT1_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT1_SHIFT)) & GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT1_MASK) #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT2_MASK (0x4U) #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT2_SHIFT (2U) #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT2_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT2_SHIFT)) & GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT2_MASK) #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT3_MASK (0x8U) #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT3_SHIFT (3U) #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT3_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT3_SHIFT)) & GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT3_MASK) #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT4_MASK (0x10U) #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT4_SHIFT (4U) #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT4_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT4_SHIFT)) & GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT4_MASK) #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT5_MASK (0x20U) #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT5_SHIFT (5U) #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT5_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT5_SHIFT)) & GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT5_MASK) #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT6_MASK (0x40U) #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT6_SHIFT (6U) #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT6_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT6_SHIFT)) & GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT6_MASK) #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT7_MASK (0x80U) #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT7_SHIFT (7U) #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT7_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT7_SHIFT)) & GTM_gtm_cls0_CCM0_ARP2_PROT_WPROT7_MASK) /*! @} */ /*! @name CCM0_ARP3_CTRL - CCM[i] Address Range Protector [a] Control Register */ /*! @{ */ #define GTM_gtm_cls0_CCM0_ARP3_CTRL_ADDR_MASK (0xFFFFU) #define GTM_gtm_cls0_CCM0_ARP3_CTRL_ADDR_SHIFT (0U) #define GTM_gtm_cls0_CCM0_ARP3_CTRL_ADDR_WIDTH (16U) #define GTM_gtm_cls0_CCM0_ARP3_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP3_CTRL_ADDR_SHIFT)) & GTM_gtm_cls0_CCM0_ARP3_CTRL_ADDR_MASK) #define GTM_gtm_cls0_CCM0_ARP3_CTRL_SIZE_MASK (0xF0000U) #define GTM_gtm_cls0_CCM0_ARP3_CTRL_SIZE_SHIFT (16U) #define GTM_gtm_cls0_CCM0_ARP3_CTRL_SIZE_WIDTH (4U) #define GTM_gtm_cls0_CCM0_ARP3_CTRL_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP3_CTRL_SIZE_SHIFT)) & GTM_gtm_cls0_CCM0_ARP3_CTRL_SIZE_MASK) #define GTM_gtm_cls0_CCM0_ARP3_CTRL_DIS_PROT_MASK (0x1000000U) #define GTM_gtm_cls0_CCM0_ARP3_CTRL_DIS_PROT_SHIFT (24U) #define GTM_gtm_cls0_CCM0_ARP3_CTRL_DIS_PROT_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP3_CTRL_DIS_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP3_CTRL_DIS_PROT_SHIFT)) & GTM_gtm_cls0_CCM0_ARP3_CTRL_DIS_PROT_MASK) #define GTM_gtm_cls0_CCM0_ARP3_CTRL_WPROT_AEI_MASK (0x80000000U) #define GTM_gtm_cls0_CCM0_ARP3_CTRL_WPROT_AEI_SHIFT (31U) #define GTM_gtm_cls0_CCM0_ARP3_CTRL_WPROT_AEI_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP3_CTRL_WPROT_AEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP3_CTRL_WPROT_AEI_SHIFT)) & GTM_gtm_cls0_CCM0_ARP3_CTRL_WPROT_AEI_MASK) /*! @} */ /*! @name CCM0_ARP3_PROT - CCM[i] Address Range Protector [a] Protection Register */ /*! @{ */ #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT0_MASK (0x1U) #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT0_SHIFT (0U) #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT0_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT0_SHIFT)) & GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT0_MASK) #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT1_MASK (0x2U) #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT1_SHIFT (1U) #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT1_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT1_SHIFT)) & GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT1_MASK) #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT2_MASK (0x4U) #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT2_SHIFT (2U) #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT2_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT2_SHIFT)) & GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT2_MASK) #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT3_MASK (0x8U) #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT3_SHIFT (3U) #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT3_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT3_SHIFT)) & GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT3_MASK) #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT4_MASK (0x10U) #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT4_SHIFT (4U) #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT4_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT4_SHIFT)) & GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT4_MASK) #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT5_MASK (0x20U) #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT5_SHIFT (5U) #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT5_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT5_SHIFT)) & GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT5_MASK) #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT6_MASK (0x40U) #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT6_SHIFT (6U) #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT6_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT6_SHIFT)) & GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT6_MASK) #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT7_MASK (0x80U) #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT7_SHIFT (7U) #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT7_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT7_SHIFT)) & GTM_gtm_cls0_CCM0_ARP3_PROT_WPROT7_MASK) /*! @} */ /*! @name CCM0_ARP4_CTRL - CCM[i] Address Range Protector [a] Control Register */ /*! @{ */ #define GTM_gtm_cls0_CCM0_ARP4_CTRL_ADDR_MASK (0xFFFFU) #define GTM_gtm_cls0_CCM0_ARP4_CTRL_ADDR_SHIFT (0U) #define GTM_gtm_cls0_CCM0_ARP4_CTRL_ADDR_WIDTH (16U) #define GTM_gtm_cls0_CCM0_ARP4_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP4_CTRL_ADDR_SHIFT)) & GTM_gtm_cls0_CCM0_ARP4_CTRL_ADDR_MASK) #define GTM_gtm_cls0_CCM0_ARP4_CTRL_SIZE_MASK (0xF0000U) #define GTM_gtm_cls0_CCM0_ARP4_CTRL_SIZE_SHIFT (16U) #define GTM_gtm_cls0_CCM0_ARP4_CTRL_SIZE_WIDTH (4U) #define GTM_gtm_cls0_CCM0_ARP4_CTRL_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP4_CTRL_SIZE_SHIFT)) & GTM_gtm_cls0_CCM0_ARP4_CTRL_SIZE_MASK) #define GTM_gtm_cls0_CCM0_ARP4_CTRL_DIS_PROT_MASK (0x1000000U) #define GTM_gtm_cls0_CCM0_ARP4_CTRL_DIS_PROT_SHIFT (24U) #define GTM_gtm_cls0_CCM0_ARP4_CTRL_DIS_PROT_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP4_CTRL_DIS_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP4_CTRL_DIS_PROT_SHIFT)) & GTM_gtm_cls0_CCM0_ARP4_CTRL_DIS_PROT_MASK) #define GTM_gtm_cls0_CCM0_ARP4_CTRL_WPROT_AEI_MASK (0x80000000U) #define GTM_gtm_cls0_CCM0_ARP4_CTRL_WPROT_AEI_SHIFT (31U) #define GTM_gtm_cls0_CCM0_ARP4_CTRL_WPROT_AEI_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP4_CTRL_WPROT_AEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP4_CTRL_WPROT_AEI_SHIFT)) & GTM_gtm_cls0_CCM0_ARP4_CTRL_WPROT_AEI_MASK) /*! @} */ /*! @name CCM0_ARP4_PROT - CCM[i] Address Range Protector [a] Protection Register */ /*! @{ */ #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT0_MASK (0x1U) #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT0_SHIFT (0U) #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT0_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT0_SHIFT)) & GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT0_MASK) #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT1_MASK (0x2U) #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT1_SHIFT (1U) #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT1_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT1_SHIFT)) & GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT1_MASK) #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT2_MASK (0x4U) #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT2_SHIFT (2U) #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT2_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT2_SHIFT)) & GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT2_MASK) #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT3_MASK (0x8U) #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT3_SHIFT (3U) #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT3_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT3_SHIFT)) & GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT3_MASK) #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT4_MASK (0x10U) #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT4_SHIFT (4U) #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT4_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT4_SHIFT)) & GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT4_MASK) #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT5_MASK (0x20U) #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT5_SHIFT (5U) #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT5_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT5_SHIFT)) & GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT5_MASK) #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT6_MASK (0x40U) #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT6_SHIFT (6U) #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT6_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT6_SHIFT)) & GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT6_MASK) #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT7_MASK (0x80U) #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT7_SHIFT (7U) #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT7_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT7_SHIFT)) & GTM_gtm_cls0_CCM0_ARP4_PROT_WPROT7_MASK) /*! @} */ /*! @name CCM0_ARP5_CTRL - CCM[i] Address Range Protector [a] Control Register */ /*! @{ */ #define GTM_gtm_cls0_CCM0_ARP5_CTRL_ADDR_MASK (0xFFFFU) #define GTM_gtm_cls0_CCM0_ARP5_CTRL_ADDR_SHIFT (0U) #define GTM_gtm_cls0_CCM0_ARP5_CTRL_ADDR_WIDTH (16U) #define GTM_gtm_cls0_CCM0_ARP5_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP5_CTRL_ADDR_SHIFT)) & GTM_gtm_cls0_CCM0_ARP5_CTRL_ADDR_MASK) #define GTM_gtm_cls0_CCM0_ARP5_CTRL_SIZE_MASK (0xF0000U) #define GTM_gtm_cls0_CCM0_ARP5_CTRL_SIZE_SHIFT (16U) #define GTM_gtm_cls0_CCM0_ARP5_CTRL_SIZE_WIDTH (4U) #define GTM_gtm_cls0_CCM0_ARP5_CTRL_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP5_CTRL_SIZE_SHIFT)) & GTM_gtm_cls0_CCM0_ARP5_CTRL_SIZE_MASK) #define GTM_gtm_cls0_CCM0_ARP5_CTRL_DIS_PROT_MASK (0x1000000U) #define GTM_gtm_cls0_CCM0_ARP5_CTRL_DIS_PROT_SHIFT (24U) #define GTM_gtm_cls0_CCM0_ARP5_CTRL_DIS_PROT_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP5_CTRL_DIS_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP5_CTRL_DIS_PROT_SHIFT)) & GTM_gtm_cls0_CCM0_ARP5_CTRL_DIS_PROT_MASK) #define GTM_gtm_cls0_CCM0_ARP5_CTRL_WPROT_AEI_MASK (0x80000000U) #define GTM_gtm_cls0_CCM0_ARP5_CTRL_WPROT_AEI_SHIFT (31U) #define GTM_gtm_cls0_CCM0_ARP5_CTRL_WPROT_AEI_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP5_CTRL_WPROT_AEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP5_CTRL_WPROT_AEI_SHIFT)) & GTM_gtm_cls0_CCM0_ARP5_CTRL_WPROT_AEI_MASK) /*! @} */ /*! @name CCM0_ARP5_PROT - CCM[i] Address Range Protector [a] Protection Register */ /*! @{ */ #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT0_MASK (0x1U) #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT0_SHIFT (0U) #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT0_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT0_SHIFT)) & GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT0_MASK) #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT1_MASK (0x2U) #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT1_SHIFT (1U) #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT1_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT1_SHIFT)) & GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT1_MASK) #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT2_MASK (0x4U) #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT2_SHIFT (2U) #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT2_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT2_SHIFT)) & GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT2_MASK) #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT3_MASK (0x8U) #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT3_SHIFT (3U) #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT3_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT3_SHIFT)) & GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT3_MASK) #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT4_MASK (0x10U) #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT4_SHIFT (4U) #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT4_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT4_SHIFT)) & GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT4_MASK) #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT5_MASK (0x20U) #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT5_SHIFT (5U) #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT5_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT5_SHIFT)) & GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT5_MASK) #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT6_MASK (0x40U) #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT6_SHIFT (6U) #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT6_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT6_SHIFT)) & GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT6_MASK) #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT7_MASK (0x80U) #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT7_SHIFT (7U) #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT7_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT7_SHIFT)) & GTM_gtm_cls0_CCM0_ARP5_PROT_WPROT7_MASK) /*! @} */ /*! @name CCM0_ARP6_CTRL - CCM[i] Address Range Protector [a] Control Register */ /*! @{ */ #define GTM_gtm_cls0_CCM0_ARP6_CTRL_ADDR_MASK (0xFFFFU) #define GTM_gtm_cls0_CCM0_ARP6_CTRL_ADDR_SHIFT (0U) #define GTM_gtm_cls0_CCM0_ARP6_CTRL_ADDR_WIDTH (16U) #define GTM_gtm_cls0_CCM0_ARP6_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP6_CTRL_ADDR_SHIFT)) & GTM_gtm_cls0_CCM0_ARP6_CTRL_ADDR_MASK) #define GTM_gtm_cls0_CCM0_ARP6_CTRL_SIZE_MASK (0xF0000U) #define GTM_gtm_cls0_CCM0_ARP6_CTRL_SIZE_SHIFT (16U) #define GTM_gtm_cls0_CCM0_ARP6_CTRL_SIZE_WIDTH (4U) #define GTM_gtm_cls0_CCM0_ARP6_CTRL_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP6_CTRL_SIZE_SHIFT)) & GTM_gtm_cls0_CCM0_ARP6_CTRL_SIZE_MASK) #define GTM_gtm_cls0_CCM0_ARP6_CTRL_DIS_PROT_MASK (0x1000000U) #define GTM_gtm_cls0_CCM0_ARP6_CTRL_DIS_PROT_SHIFT (24U) #define GTM_gtm_cls0_CCM0_ARP6_CTRL_DIS_PROT_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP6_CTRL_DIS_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP6_CTRL_DIS_PROT_SHIFT)) & GTM_gtm_cls0_CCM0_ARP6_CTRL_DIS_PROT_MASK) #define GTM_gtm_cls0_CCM0_ARP6_CTRL_WPROT_AEI_MASK (0x80000000U) #define GTM_gtm_cls0_CCM0_ARP6_CTRL_WPROT_AEI_SHIFT (31U) #define GTM_gtm_cls0_CCM0_ARP6_CTRL_WPROT_AEI_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP6_CTRL_WPROT_AEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP6_CTRL_WPROT_AEI_SHIFT)) & GTM_gtm_cls0_CCM0_ARP6_CTRL_WPROT_AEI_MASK) /*! @} */ /*! @name CCM0_ARP6_PROT - CCM[i] Address Range Protector [a] Protection Register */ /*! @{ */ #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT0_MASK (0x1U) #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT0_SHIFT (0U) #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT0_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT0_SHIFT)) & GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT0_MASK) #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT1_MASK (0x2U) #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT1_SHIFT (1U) #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT1_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT1_SHIFT)) & GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT1_MASK) #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT2_MASK (0x4U) #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT2_SHIFT (2U) #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT2_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT2_SHIFT)) & GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT2_MASK) #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT3_MASK (0x8U) #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT3_SHIFT (3U) #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT3_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT3_SHIFT)) & GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT3_MASK) #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT4_MASK (0x10U) #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT4_SHIFT (4U) #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT4_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT4_SHIFT)) & GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT4_MASK) #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT5_MASK (0x20U) #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT5_SHIFT (5U) #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT5_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT5_SHIFT)) & GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT5_MASK) #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT6_MASK (0x40U) #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT6_SHIFT (6U) #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT6_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT6_SHIFT)) & GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT6_MASK) #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT7_MASK (0x80U) #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT7_SHIFT (7U) #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT7_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT7_SHIFT)) & GTM_gtm_cls0_CCM0_ARP6_PROT_WPROT7_MASK) /*! @} */ /*! @name CCM0_ARP7_CTRL - CCM[i] Address Range Protector [a] Control Register */ /*! @{ */ #define GTM_gtm_cls0_CCM0_ARP7_CTRL_ADDR_MASK (0xFFFFU) #define GTM_gtm_cls0_CCM0_ARP7_CTRL_ADDR_SHIFT (0U) #define GTM_gtm_cls0_CCM0_ARP7_CTRL_ADDR_WIDTH (16U) #define GTM_gtm_cls0_CCM0_ARP7_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP7_CTRL_ADDR_SHIFT)) & GTM_gtm_cls0_CCM0_ARP7_CTRL_ADDR_MASK) #define GTM_gtm_cls0_CCM0_ARP7_CTRL_SIZE_MASK (0xF0000U) #define GTM_gtm_cls0_CCM0_ARP7_CTRL_SIZE_SHIFT (16U) #define GTM_gtm_cls0_CCM0_ARP7_CTRL_SIZE_WIDTH (4U) #define GTM_gtm_cls0_CCM0_ARP7_CTRL_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP7_CTRL_SIZE_SHIFT)) & GTM_gtm_cls0_CCM0_ARP7_CTRL_SIZE_MASK) #define GTM_gtm_cls0_CCM0_ARP7_CTRL_DIS_PROT_MASK (0x1000000U) #define GTM_gtm_cls0_CCM0_ARP7_CTRL_DIS_PROT_SHIFT (24U) #define GTM_gtm_cls0_CCM0_ARP7_CTRL_DIS_PROT_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP7_CTRL_DIS_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP7_CTRL_DIS_PROT_SHIFT)) & GTM_gtm_cls0_CCM0_ARP7_CTRL_DIS_PROT_MASK) #define GTM_gtm_cls0_CCM0_ARP7_CTRL_WPROT_AEI_MASK (0x80000000U) #define GTM_gtm_cls0_CCM0_ARP7_CTRL_WPROT_AEI_SHIFT (31U) #define GTM_gtm_cls0_CCM0_ARP7_CTRL_WPROT_AEI_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP7_CTRL_WPROT_AEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP7_CTRL_WPROT_AEI_SHIFT)) & GTM_gtm_cls0_CCM0_ARP7_CTRL_WPROT_AEI_MASK) /*! @} */ /*! @name CCM0_ARP7_PROT - CCM[i] Address Range Protector [a] Protection Register */ /*! @{ */ #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT0_MASK (0x1U) #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT0_SHIFT (0U) #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT0_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT0_SHIFT)) & GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT0_MASK) #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT1_MASK (0x2U) #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT1_SHIFT (1U) #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT1_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT1_SHIFT)) & GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT1_MASK) #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT2_MASK (0x4U) #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT2_SHIFT (2U) #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT2_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT2_SHIFT)) & GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT2_MASK) #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT3_MASK (0x8U) #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT3_SHIFT (3U) #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT3_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT3_SHIFT)) & GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT3_MASK) #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT4_MASK (0x10U) #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT4_SHIFT (4U) #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT4_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT4_SHIFT)) & GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT4_MASK) #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT5_MASK (0x20U) #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT5_SHIFT (5U) #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT5_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT5_SHIFT)) & GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT5_MASK) #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT6_MASK (0x40U) #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT6_SHIFT (6U) #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT6_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT6_SHIFT)) & GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT6_MASK) #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT7_MASK (0x80U) #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT7_SHIFT (7U) #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT7_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT7_SHIFT)) & GTM_gtm_cls0_CCM0_ARP7_PROT_WPROT7_MASK) /*! @} */ /*! @name CCM0_ARP8_CTRL - CCM[i] Address Range Protector [a] Control Register */ /*! @{ */ #define GTM_gtm_cls0_CCM0_ARP8_CTRL_ADDR_MASK (0xFFFFU) #define GTM_gtm_cls0_CCM0_ARP8_CTRL_ADDR_SHIFT (0U) #define GTM_gtm_cls0_CCM0_ARP8_CTRL_ADDR_WIDTH (16U) #define GTM_gtm_cls0_CCM0_ARP8_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP8_CTRL_ADDR_SHIFT)) & GTM_gtm_cls0_CCM0_ARP8_CTRL_ADDR_MASK) #define GTM_gtm_cls0_CCM0_ARP8_CTRL_SIZE_MASK (0xF0000U) #define GTM_gtm_cls0_CCM0_ARP8_CTRL_SIZE_SHIFT (16U) #define GTM_gtm_cls0_CCM0_ARP8_CTRL_SIZE_WIDTH (4U) #define GTM_gtm_cls0_CCM0_ARP8_CTRL_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP8_CTRL_SIZE_SHIFT)) & GTM_gtm_cls0_CCM0_ARP8_CTRL_SIZE_MASK) #define GTM_gtm_cls0_CCM0_ARP8_CTRL_DIS_PROT_MASK (0x1000000U) #define GTM_gtm_cls0_CCM0_ARP8_CTRL_DIS_PROT_SHIFT (24U) #define GTM_gtm_cls0_CCM0_ARP8_CTRL_DIS_PROT_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP8_CTRL_DIS_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP8_CTRL_DIS_PROT_SHIFT)) & GTM_gtm_cls0_CCM0_ARP8_CTRL_DIS_PROT_MASK) #define GTM_gtm_cls0_CCM0_ARP8_CTRL_WPROT_AEI_MASK (0x80000000U) #define GTM_gtm_cls0_CCM0_ARP8_CTRL_WPROT_AEI_SHIFT (31U) #define GTM_gtm_cls0_CCM0_ARP8_CTRL_WPROT_AEI_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP8_CTRL_WPROT_AEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP8_CTRL_WPROT_AEI_SHIFT)) & GTM_gtm_cls0_CCM0_ARP8_CTRL_WPROT_AEI_MASK) /*! @} */ /*! @name CCM0_ARP8_PROT - CCM[i] Address Range Protector [a] Protection Register */ /*! @{ */ #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT0_MASK (0x1U) #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT0_SHIFT (0U) #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT0_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT0_SHIFT)) & GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT0_MASK) #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT1_MASK (0x2U) #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT1_SHIFT (1U) #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT1_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT1_SHIFT)) & GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT1_MASK) #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT2_MASK (0x4U) #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT2_SHIFT (2U) #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT2_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT2_SHIFT)) & GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT2_MASK) #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT3_MASK (0x8U) #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT3_SHIFT (3U) #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT3_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT3_SHIFT)) & GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT3_MASK) #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT4_MASK (0x10U) #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT4_SHIFT (4U) #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT4_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT4_SHIFT)) & GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT4_MASK) #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT5_MASK (0x20U) #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT5_SHIFT (5U) #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT5_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT5_SHIFT)) & GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT5_MASK) #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT6_MASK (0x40U) #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT6_SHIFT (6U) #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT6_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT6_SHIFT)) & GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT6_MASK) #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT7_MASK (0x80U) #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT7_SHIFT (7U) #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT7_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT7_SHIFT)) & GTM_gtm_cls0_CCM0_ARP8_PROT_WPROT7_MASK) /*! @} */ /*! @name CCM0_ARP9_CTRL - CCM[i] Address Range Protector [a] Control Register */ /*! @{ */ #define GTM_gtm_cls0_CCM0_ARP9_CTRL_ADDR_MASK (0xFFFFU) #define GTM_gtm_cls0_CCM0_ARP9_CTRL_ADDR_SHIFT (0U) #define GTM_gtm_cls0_CCM0_ARP9_CTRL_ADDR_WIDTH (16U) #define GTM_gtm_cls0_CCM0_ARP9_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP9_CTRL_ADDR_SHIFT)) & GTM_gtm_cls0_CCM0_ARP9_CTRL_ADDR_MASK) #define GTM_gtm_cls0_CCM0_ARP9_CTRL_SIZE_MASK (0xF0000U) #define GTM_gtm_cls0_CCM0_ARP9_CTRL_SIZE_SHIFT (16U) #define GTM_gtm_cls0_CCM0_ARP9_CTRL_SIZE_WIDTH (4U) #define GTM_gtm_cls0_CCM0_ARP9_CTRL_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP9_CTRL_SIZE_SHIFT)) & GTM_gtm_cls0_CCM0_ARP9_CTRL_SIZE_MASK) #define GTM_gtm_cls0_CCM0_ARP9_CTRL_DIS_PROT_MASK (0x1000000U) #define GTM_gtm_cls0_CCM0_ARP9_CTRL_DIS_PROT_SHIFT (24U) #define GTM_gtm_cls0_CCM0_ARP9_CTRL_DIS_PROT_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP9_CTRL_DIS_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP9_CTRL_DIS_PROT_SHIFT)) & GTM_gtm_cls0_CCM0_ARP9_CTRL_DIS_PROT_MASK) #define GTM_gtm_cls0_CCM0_ARP9_CTRL_WPROT_AEI_MASK (0x80000000U) #define GTM_gtm_cls0_CCM0_ARP9_CTRL_WPROT_AEI_SHIFT (31U) #define GTM_gtm_cls0_CCM0_ARP9_CTRL_WPROT_AEI_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP9_CTRL_WPROT_AEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP9_CTRL_WPROT_AEI_SHIFT)) & GTM_gtm_cls0_CCM0_ARP9_CTRL_WPROT_AEI_MASK) /*! @} */ /*! @name CCM0_ARP9_PROT - CCM[i] Address Range Protector [a] Protection Register */ /*! @{ */ #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT0_MASK (0x1U) #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT0_SHIFT (0U) #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT0_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT0_SHIFT)) & GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT0_MASK) #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT1_MASK (0x2U) #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT1_SHIFT (1U) #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT1_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT1_SHIFT)) & GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT1_MASK) #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT2_MASK (0x4U) #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT2_SHIFT (2U) #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT2_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT2_SHIFT)) & GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT2_MASK) #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT3_MASK (0x8U) #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT3_SHIFT (3U) #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT3_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT3_SHIFT)) & GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT3_MASK) #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT4_MASK (0x10U) #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT4_SHIFT (4U) #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT4_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT4_SHIFT)) & GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT4_MASK) #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT5_MASK (0x20U) #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT5_SHIFT (5U) #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT5_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT5_SHIFT)) & GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT5_MASK) #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT6_MASK (0x40U) #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT6_SHIFT (6U) #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT6_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT6_SHIFT)) & GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT6_MASK) #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT7_MASK (0x80U) #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT7_SHIFT (7U) #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT7_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT7_SHIFT)) & GTM_gtm_cls0_CCM0_ARP9_PROT_WPROT7_MASK) /*! @} */ /*! @name CCM0_HW_CONF2 - CCM[i] 2. Hardware Configuration Register */ /*! @{ */ #define GTM_gtm_cls0_CCM0_HW_CONF2_AXIM_ID_WIDTH_MASK (0x1FU) #define GTM_gtm_cls0_CCM0_HW_CONF2_AXIM_ID_WIDTH_SHIFT (0U) #define GTM_gtm_cls0_CCM0_HW_CONF2_AXIM_ID_WIDTH_WIDTH (5U) #define GTM_gtm_cls0_CCM0_HW_CONF2_AXIM_ID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_HW_CONF2_AXIM_ID_WIDTH_SHIFT)) & GTM_gtm_cls0_CCM0_HW_CONF2_AXIM_ID_WIDTH_MASK) #define GTM_gtm_cls0_CCM0_HW_CONF2_AXIM_PRIV_ACC_MASK (0x20U) #define GTM_gtm_cls0_CCM0_HW_CONF2_AXIM_PRIV_ACC_SHIFT (5U) #define GTM_gtm_cls0_CCM0_HW_CONF2_AXIM_PRIV_ACC_WIDTH (1U) #define GTM_gtm_cls0_CCM0_HW_CONF2_AXIM_PRIV_ACC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_HW_CONF2_AXIM_PRIV_ACC_SHIFT)) & GTM_gtm_cls0_CCM0_HW_CONF2_AXIM_PRIV_ACC_MASK) #define GTM_gtm_cls0_CCM0_HW_CONF2_AXIM_SEC_ACC_MASK (0x40U) #define GTM_gtm_cls0_CCM0_HW_CONF2_AXIM_SEC_ACC_SHIFT (6U) #define GTM_gtm_cls0_CCM0_HW_CONF2_AXIM_SEC_ACC_WIDTH (1U) #define GTM_gtm_cls0_CCM0_HW_CONF2_AXIM_SEC_ACC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_HW_CONF2_AXIM_SEC_ACC_SHIFT)) & GTM_gtm_cls0_CCM0_HW_CONF2_AXIM_SEC_ACC_MASK) #define GTM_gtm_cls0_CCM0_HW_CONF2_AXIM_POSTED_WRITE_MASK (0x80U) #define GTM_gtm_cls0_CCM0_HW_CONF2_AXIM_POSTED_WRITE_SHIFT (7U) #define GTM_gtm_cls0_CCM0_HW_CONF2_AXIM_POSTED_WRITE_WIDTH (1U) #define GTM_gtm_cls0_CCM0_HW_CONF2_AXIM_POSTED_WRITE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_HW_CONF2_AXIM_POSTED_WRITE_SHIFT)) & GTM_gtm_cls0_CCM0_HW_CONF2_AXIM_POSTED_WRITE_MASK) #define GTM_gtm_cls0_CCM0_HW_CONF2_TIO_OUT_RST_MASK (0x200U) #define GTM_gtm_cls0_CCM0_HW_CONF2_TIO_OUT_RST_SHIFT (9U) #define GTM_gtm_cls0_CCM0_HW_CONF2_TIO_OUT_RST_WIDTH (1U) #define GTM_gtm_cls0_CCM0_HW_CONF2_TIO_OUT_RST(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_HW_CONF2_TIO_OUT_RST_SHIFT)) & GTM_gtm_cls0_CCM0_HW_CONF2_TIO_OUT_RST_MASK) #define GTM_gtm_cls0_CCM0_HW_CONF2_AXIS_DATA_SIZE_MASK (0x10000U) #define GTM_gtm_cls0_CCM0_HW_CONF2_AXIS_DATA_SIZE_SHIFT (16U) #define GTM_gtm_cls0_CCM0_HW_CONF2_AXIS_DATA_SIZE_WIDTH (1U) #define GTM_gtm_cls0_CCM0_HW_CONF2_AXIS_DATA_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_HW_CONF2_AXIS_DATA_SIZE_SHIFT)) & GTM_gtm_cls0_CCM0_HW_CONF2_AXIS_DATA_SIZE_MASK) #define GTM_gtm_cls0_CCM0_HW_CONF2_AXIM_DATA_SIZE_MASK (0x40000U) #define GTM_gtm_cls0_CCM0_HW_CONF2_AXIM_DATA_SIZE_SHIFT (18U) #define GTM_gtm_cls0_CCM0_HW_CONF2_AXIM_DATA_SIZE_WIDTH (1U) #define GTM_gtm_cls0_CCM0_HW_CONF2_AXIM_DATA_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_HW_CONF2_AXIM_DATA_SIZE_SHIFT)) & GTM_gtm_cls0_CCM0_HW_CONF2_AXIM_DATA_SIZE_MASK) /*! @} */ /*! @name CCM0_AEIM_STA - CCM[i] MCS Bus Master Status Register */ /*! @{ */ #define GTM_gtm_cls0_CCM0_AEIM_STA_AEIM_XPT_ADDR_MASK (0xFFFFU) #define GTM_gtm_cls0_CCM0_AEIM_STA_AEIM_XPT_ADDR_SHIFT (0U) #define GTM_gtm_cls0_CCM0_AEIM_STA_AEIM_XPT_ADDR_WIDTH (16U) #define GTM_gtm_cls0_CCM0_AEIM_STA_AEIM_XPT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_AEIM_STA_AEIM_XPT_ADDR_SHIFT)) & GTM_gtm_cls0_CCM0_AEIM_STA_AEIM_XPT_ADDR_MASK) #define GTM_gtm_cls0_CCM0_AEIM_STA_AEIM_XPT_STA_MASK (0x3000000U) #define GTM_gtm_cls0_CCM0_AEIM_STA_AEIM_XPT_STA_SHIFT (24U) #define GTM_gtm_cls0_CCM0_AEIM_STA_AEIM_XPT_STA_WIDTH (2U) #define GTM_gtm_cls0_CCM0_AEIM_STA_AEIM_XPT_STA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_AEIM_STA_AEIM_XPT_STA_SHIFT)) & GTM_gtm_cls0_CCM0_AEIM_STA_AEIM_XPT_STA_MASK) /*! @} */ /*! @name CCM0_HW_CONF - CCM[i] Hardware Configuration Register */ /*! @{ */ #define GTM_gtm_cls0_CCM0_HW_CONF_GRSTEN_MASK (0x1U) #define GTM_gtm_cls0_CCM0_HW_CONF_GRSTEN_SHIFT (0U) #define GTM_gtm_cls0_CCM0_HW_CONF_GRSTEN_WIDTH (1U) #define GTM_gtm_cls0_CCM0_HW_CONF_GRSTEN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_HW_CONF_GRSTEN_SHIFT)) & GTM_gtm_cls0_CCM0_HW_CONF_GRSTEN_MASK) #define GTM_gtm_cls0_CCM0_HW_CONF_BRIDGE_MODE_RST_MASK (0x2U) #define GTM_gtm_cls0_CCM0_HW_CONF_BRIDGE_MODE_RST_SHIFT (1U) #define GTM_gtm_cls0_CCM0_HW_CONF_BRIDGE_MODE_RST_WIDTH (1U) #define GTM_gtm_cls0_CCM0_HW_CONF_BRIDGE_MODE_RST(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_HW_CONF_BRIDGE_MODE_RST_SHIFT)) & GTM_gtm_cls0_CCM0_HW_CONF_BRIDGE_MODE_RST_MASK) #define GTM_gtm_cls0_CCM0_HW_CONF_SYNC_INPUT_REG_MASK (0x4U) #define GTM_gtm_cls0_CCM0_HW_CONF_SYNC_INPUT_REG_SHIFT (2U) #define GTM_gtm_cls0_CCM0_HW_CONF_SYNC_INPUT_REG_WIDTH (1U) #define GTM_gtm_cls0_CCM0_HW_CONF_SYNC_INPUT_REG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_HW_CONF_SYNC_INPUT_REG_SHIFT)) & GTM_gtm_cls0_CCM0_HW_CONF_SYNC_INPUT_REG_MASK) #define GTM_gtm_cls0_CCM0_HW_CONF_CFG_CLOCK_RATE_MASK (0x8U) #define GTM_gtm_cls0_CCM0_HW_CONF_CFG_CLOCK_RATE_SHIFT (3U) #define GTM_gtm_cls0_CCM0_HW_CONF_CFG_CLOCK_RATE_WIDTH (1U) #define GTM_gtm_cls0_CCM0_HW_CONF_CFG_CLOCK_RATE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_HW_CONF_CFG_CLOCK_RATE_SHIFT)) & GTM_gtm_cls0_CCM0_HW_CONF_CFG_CLOCK_RATE_MASK) #define GTM_gtm_cls0_CCM0_HW_CONF_ATOM_OUT_RST_MASK (0x10U) #define GTM_gtm_cls0_CCM0_HW_CONF_ATOM_OUT_RST_SHIFT (4U) #define GTM_gtm_cls0_CCM0_HW_CONF_ATOM_OUT_RST_WIDTH (1U) #define GTM_gtm_cls0_CCM0_HW_CONF_ATOM_OUT_RST(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_HW_CONF_ATOM_OUT_RST_SHIFT)) & GTM_gtm_cls0_CCM0_HW_CONF_ATOM_OUT_RST_MASK) #define GTM_gtm_cls0_CCM0_HW_CONF_ATOM_TRIG_CHAIN_MASK (0xE0U) #define GTM_gtm_cls0_CCM0_HW_CONF_ATOM_TRIG_CHAIN_SHIFT (5U) #define GTM_gtm_cls0_CCM0_HW_CONF_ATOM_TRIG_CHAIN_WIDTH (3U) #define GTM_gtm_cls0_CCM0_HW_CONF_ATOM_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_HW_CONF_ATOM_TRIG_CHAIN_SHIFT)) & GTM_gtm_cls0_CCM0_HW_CONF_ATOM_TRIG_CHAIN_MASK) #define GTM_gtm_cls0_CCM0_HW_CONF_TOM_OUT_RST_MASK (0x100U) #define GTM_gtm_cls0_CCM0_HW_CONF_TOM_OUT_RST_SHIFT (8U) #define GTM_gtm_cls0_CCM0_HW_CONF_TOM_OUT_RST_WIDTH (1U) #define GTM_gtm_cls0_CCM0_HW_CONF_TOM_OUT_RST(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_HW_CONF_TOM_OUT_RST_SHIFT)) & GTM_gtm_cls0_CCM0_HW_CONF_TOM_OUT_RST_MASK) #define GTM_gtm_cls0_CCM0_HW_CONF_TOM_TRIG_CHAIN_MASK (0xE00U) #define GTM_gtm_cls0_CCM0_HW_CONF_TOM_TRIG_CHAIN_SHIFT (9U) #define GTM_gtm_cls0_CCM0_HW_CONF_TOM_TRIG_CHAIN_WIDTH (3U) #define GTM_gtm_cls0_CCM0_HW_CONF_TOM_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_HW_CONF_TOM_TRIG_CHAIN_SHIFT)) & GTM_gtm_cls0_CCM0_HW_CONF_TOM_TRIG_CHAIN_MASK) #define GTM_gtm_cls0_CCM0_HW_CONF_RAM_INIT_RST_MASK (0x1000U) #define GTM_gtm_cls0_CCM0_HW_CONF_RAM_INIT_RST_SHIFT (12U) #define GTM_gtm_cls0_CCM0_HW_CONF_RAM_INIT_RST_WIDTH (1U) #define GTM_gtm_cls0_CCM0_HW_CONF_RAM_INIT_RST(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_HW_CONF_RAM_INIT_RST_SHIFT)) & GTM_gtm_cls0_CCM0_HW_CONF_RAM_INIT_RST_MASK) #define GTM_gtm_cls0_CCM0_HW_CONF_ERM_MASK (0x2000U) #define GTM_gtm_cls0_CCM0_HW_CONF_ERM_SHIFT (13U) #define GTM_gtm_cls0_CCM0_HW_CONF_ERM_WIDTH (1U) #define GTM_gtm_cls0_CCM0_HW_CONF_ERM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_HW_CONF_ERM_SHIFT)) & GTM_gtm_cls0_CCM0_HW_CONF_ERM_MASK) #define GTM_gtm_cls0_CCM0_HW_CONF_RESET_ACTIVE_MASK (0x8000U) #define GTM_gtm_cls0_CCM0_HW_CONF_RESET_ACTIVE_SHIFT (15U) #define GTM_gtm_cls0_CCM0_HW_CONF_RESET_ACTIVE_WIDTH (1U) #define GTM_gtm_cls0_CCM0_HW_CONF_RESET_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_HW_CONF_RESET_ACTIVE_SHIFT)) & GTM_gtm_cls0_CCM0_HW_CONF_RESET_ACTIVE_MASK) #define GTM_gtm_cls0_CCM0_HW_CONF_IRQ_MODE_LEVEL_MASK (0x10000U) #define GTM_gtm_cls0_CCM0_HW_CONF_IRQ_MODE_LEVEL_SHIFT (16U) #define GTM_gtm_cls0_CCM0_HW_CONF_IRQ_MODE_LEVEL_WIDTH (1U) #define GTM_gtm_cls0_CCM0_HW_CONF_IRQ_MODE_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_HW_CONF_IRQ_MODE_LEVEL_SHIFT)) & GTM_gtm_cls0_CCM0_HW_CONF_IRQ_MODE_LEVEL_MASK) #define GTM_gtm_cls0_CCM0_HW_CONF_IRQ_MODE_PULSE_MASK (0x20000U) #define GTM_gtm_cls0_CCM0_HW_CONF_IRQ_MODE_PULSE_SHIFT (17U) #define GTM_gtm_cls0_CCM0_HW_CONF_IRQ_MODE_PULSE_WIDTH (1U) #define GTM_gtm_cls0_CCM0_HW_CONF_IRQ_MODE_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_HW_CONF_IRQ_MODE_PULSE_SHIFT)) & GTM_gtm_cls0_CCM0_HW_CONF_IRQ_MODE_PULSE_MASK) #define GTM_gtm_cls0_CCM0_HW_CONF_IRQ_MODE_PULSE_NOTIFY_MASK (0x40000U) #define GTM_gtm_cls0_CCM0_HW_CONF_IRQ_MODE_PULSE_NOTIFY_SHIFT (18U) #define GTM_gtm_cls0_CCM0_HW_CONF_IRQ_MODE_PULSE_NOTIFY_WIDTH (1U) #define GTM_gtm_cls0_CCM0_HW_CONF_IRQ_MODE_PULSE_NOTIFY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_HW_CONF_IRQ_MODE_PULSE_NOTIFY_SHIFT)) & GTM_gtm_cls0_CCM0_HW_CONF_IRQ_MODE_PULSE_NOTIFY_MASK) #define GTM_gtm_cls0_CCM0_HW_CONF_IRQ_MODE_SINGLE_PULSE_MASK (0x80000U) #define GTM_gtm_cls0_CCM0_HW_CONF_IRQ_MODE_SINGLE_PULSE_SHIFT (19U) #define GTM_gtm_cls0_CCM0_HW_CONF_IRQ_MODE_SINGLE_PULSE_WIDTH (1U) #define GTM_gtm_cls0_CCM0_HW_CONF_IRQ_MODE_SINGLE_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_HW_CONF_IRQ_MODE_SINGLE_PULSE_SHIFT)) & GTM_gtm_cls0_CCM0_HW_CONF_IRQ_MODE_SINGLE_PULSE_MASK) #define GTM_gtm_cls0_CCM0_HW_CONF_ATOM_TRIG_INTCHAIN_MASK (0xF00000U) #define GTM_gtm_cls0_CCM0_HW_CONF_ATOM_TRIG_INTCHAIN_SHIFT (20U) #define GTM_gtm_cls0_CCM0_HW_CONF_ATOM_TRIG_INTCHAIN_WIDTH (4U) #define GTM_gtm_cls0_CCM0_HW_CONF_ATOM_TRIG_INTCHAIN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_HW_CONF_ATOM_TRIG_INTCHAIN_SHIFT)) & GTM_gtm_cls0_CCM0_HW_CONF_ATOM_TRIG_INTCHAIN_MASK) #define GTM_gtm_cls0_CCM0_HW_CONF_TOM_TRIG_INTCHAIN_MASK (0x1F000000U) #define GTM_gtm_cls0_CCM0_HW_CONF_TOM_TRIG_INTCHAIN_SHIFT (24U) #define GTM_gtm_cls0_CCM0_HW_CONF_TOM_TRIG_INTCHAIN_WIDTH (5U) #define GTM_gtm_cls0_CCM0_HW_CONF_TOM_TRIG_INTCHAIN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_HW_CONF_TOM_TRIG_INTCHAIN_SHIFT)) & GTM_gtm_cls0_CCM0_HW_CONF_TOM_TRIG_INTCHAIN_MASK) #define GTM_gtm_cls0_CCM0_HW_CONF_INT_CLK_EN_GEN_MASK (0x20000000U) #define GTM_gtm_cls0_CCM0_HW_CONF_INT_CLK_EN_GEN_SHIFT (29U) #define GTM_gtm_cls0_CCM0_HW_CONF_INT_CLK_EN_GEN_WIDTH (1U) #define GTM_gtm_cls0_CCM0_HW_CONF_INT_CLK_EN_GEN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_HW_CONF_INT_CLK_EN_GEN_SHIFT)) & GTM_gtm_cls0_CCM0_HW_CONF_INT_CLK_EN_GEN_MASK) #define GTM_gtm_cls0_CCM0_HW_CONF_AEI_ADDR_PIPELINE_STAGE_MASK (0x40000000U) #define GTM_gtm_cls0_CCM0_HW_CONF_AEI_ADDR_PIPELINE_STAGE_SHIFT (30U) #define GTM_gtm_cls0_CCM0_HW_CONF_AEI_ADDR_PIPELINE_STAGE_WIDTH (1U) #define GTM_gtm_cls0_CCM0_HW_CONF_AEI_ADDR_PIPELINE_STAGE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_HW_CONF_AEI_ADDR_PIPELINE_STAGE_SHIFT)) & GTM_gtm_cls0_CCM0_HW_CONF_AEI_ADDR_PIPELINE_STAGE_MASK) #define GTM_gtm_cls0_CCM0_HW_CONF_AEI_RDATA_PIPELINE_STAGE_MASK (0x80000000U) #define GTM_gtm_cls0_CCM0_HW_CONF_AEI_RDATA_PIPELINE_STAGE_SHIFT (31U) #define GTM_gtm_cls0_CCM0_HW_CONF_AEI_RDATA_PIPELINE_STAGE_WIDTH (1U) #define GTM_gtm_cls0_CCM0_HW_CONF_AEI_RDATA_PIPELINE_STAGE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_HW_CONF_AEI_RDATA_PIPELINE_STAGE_SHIFT)) & GTM_gtm_cls0_CCM0_HW_CONF_AEI_RDATA_PIPELINE_STAGE_MASK) /*! @} */ /*! @name CCM0_TIM_AUX_IN_SRC - CCM[i] TIM AUX Input Source Register */ /*! @{ */ #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH0_MASK (0x1U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH0_SHIFT (0U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH0_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH0_SHIFT)) & GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH0_MASK) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH1_MASK (0x2U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH1_SHIFT (1U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH1_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH1_SHIFT)) & GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH1_MASK) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH2_MASK (0x4U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH2_SHIFT (2U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH2_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH2_SHIFT)) & GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH2_MASK) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH3_MASK (0x8U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH3_SHIFT (3U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH3_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH3_SHIFT)) & GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH3_MASK) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH4_MASK (0x10U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH4_SHIFT (4U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH4_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH4_SHIFT)) & GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH4_MASK) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH5_MASK (0x20U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH5_SHIFT (5U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH5_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH5_SHIFT)) & GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH5_MASK) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH6_MASK (0x40U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH6_SHIFT (6U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH6_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH6_SHIFT)) & GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH6_MASK) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH7_MASK (0x80U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH7_SHIFT (7U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH7_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH7_SHIFT)) & GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SRC_CH7_MASK) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH0_MASK (0x10000U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH0_SHIFT (16U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH0_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH0_SHIFT)) & GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH0_MASK) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH1_MASK (0x20000U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH1_SHIFT (17U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH1_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH1_SHIFT)) & GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH1_MASK) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH2_MASK (0x40000U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH2_SHIFT (18U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH2_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH2_SHIFT)) & GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH2_MASK) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH3_MASK (0x80000U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH3_SHIFT (19U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH3_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH3_SHIFT)) & GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH3_MASK) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH4_MASK (0x100000U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH4_SHIFT (20U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH4_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH4_SHIFT)) & GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH4_MASK) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH5_MASK (0x200000U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH5_SHIFT (21U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH5_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH5_SHIFT)) & GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH5_MASK) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH6_MASK (0x400000U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH6_SHIFT (22U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH6_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH6_SHIFT)) & GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH6_MASK) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH7_MASK (0x800000U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH7_SHIFT (23U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH7_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH7_SHIFT)) & GTM_gtm_cls0_CCM0_TIM_AUX_IN_SRC_SEL_OUT_N_CH7_MASK) /*! @} */ /*! @name CCM0_EXT_CAP_EN - CCM[i] External Capture Enable Register */ /*! @{ */ #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN0_MASK (0x1U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN0_SHIFT (0U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN0_WIDTH (1U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN0_SHIFT)) & GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN0_MASK) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN1_MASK (0x2U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN1_SHIFT (1U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN1_WIDTH (1U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN1_SHIFT)) & GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN1_MASK) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN2_MASK (0x4U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN2_SHIFT (2U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN2_WIDTH (1U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN2_SHIFT)) & GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN2_MASK) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN3_MASK (0x8U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN3_SHIFT (3U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN3_WIDTH (1U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN3_SHIFT)) & GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN3_MASK) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN4_MASK (0x10U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN4_SHIFT (4U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN4_WIDTH (1U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN4_SHIFT)) & GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN4_MASK) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN5_MASK (0x20U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN5_SHIFT (5U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN5_WIDTH (1U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN5_SHIFT)) & GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN5_MASK) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN6_MASK (0x40U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN6_SHIFT (6U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN6_WIDTH (1U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN6_SHIFT)) & GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN6_MASK) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN7_MASK (0x80U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN7_SHIFT (7U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN7_WIDTH (1U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN7_SHIFT)) & GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_I_EXT_CAP_EN7_MASK) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN0_MASK (0x100U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN0_SHIFT (8U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN0_WIDTH (1U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN0_SHIFT)) & GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN0_MASK) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN1_MASK (0x200U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN1_SHIFT (9U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN1_WIDTH (1U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN1_SHIFT)) & GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN1_MASK) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN2_MASK (0x400U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN2_SHIFT (10U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN2_WIDTH (1U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN2_SHIFT)) & GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN2_MASK) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN3_MASK (0x800U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN3_SHIFT (11U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN3_WIDTH (1U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN3_SHIFT)) & GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN3_MASK) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN4_MASK (0x1000U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN4_SHIFT (12U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN4_WIDTH (1U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN4_SHIFT)) & GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN4_MASK) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN5_MASK (0x2000U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN5_SHIFT (13U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN5_WIDTH (1U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN5_SHIFT)) & GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN5_MASK) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN6_MASK (0x4000U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN6_SHIFT (14U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN6_WIDTH (1U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN6_SHIFT)) & GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN6_MASK) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN7_MASK (0x8000U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN7_SHIFT (15U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN7_WIDTH (1U) #define GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN7_SHIFT)) & GTM_gtm_cls0_CCM0_EXT_CAP_EN_TIM_IP1_EXT_CAP_EN7_MASK) /*! @} */ /*! @name CCM0_TOM_OUT - CCM[i] TOM Output Register */ /*! @{ */ #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT0_MASK (0x1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT0_SHIFT (0U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT0_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT0_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT0_MASK) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT1_MASK (0x2U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT1_SHIFT (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT1_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT1_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT1_MASK) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT2_MASK (0x4U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT2_SHIFT (2U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT2_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT2_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT2_MASK) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT3_MASK (0x8U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT3_SHIFT (3U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT3_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT3_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT3_MASK) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT4_MASK (0x10U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT4_SHIFT (4U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT4_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT4_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT4_MASK) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT5_MASK (0x20U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT5_SHIFT (5U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT5_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT5_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT5_MASK) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT6_MASK (0x40U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT6_SHIFT (6U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT6_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT6_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT6_MASK) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT7_MASK (0x80U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT7_SHIFT (7U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT7_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT7_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT7_MASK) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT8_MASK (0x100U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT8_SHIFT (8U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT8_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT8_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT8_MASK) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT9_MASK (0x200U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT9_SHIFT (9U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT9_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT9_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT9_MASK) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT10_MASK (0x400U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT10_SHIFT (10U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT10_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT10_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT10_MASK) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT11_MASK (0x800U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT11_SHIFT (11U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT11_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT11_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT11_MASK) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT12_MASK (0x1000U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT12_SHIFT (12U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT12_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT12(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT12_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT12_MASK) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT13_MASK (0x2000U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT13_SHIFT (13U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT13_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT13(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT13_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT13_MASK) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT14_MASK (0x4000U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT14_SHIFT (14U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT14_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT14(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT14_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT14_MASK) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT15_MASK (0x8000U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT15_SHIFT (15U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT15_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT15(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT15_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT15_MASK) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N0_MASK (0x10000U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N0_SHIFT (16U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N0_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N0_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N0_MASK) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N1_MASK (0x20000U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N1_SHIFT (17U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N1_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N1_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N1_MASK) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N2_MASK (0x40000U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N2_SHIFT (18U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N2_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N2_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N2_MASK) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N3_MASK (0x80000U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N3_SHIFT (19U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N3_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N3_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N3_MASK) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N4_MASK (0x100000U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N4_SHIFT (20U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N4_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N4_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N4_MASK) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N5_MASK (0x200000U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N5_SHIFT (21U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N5_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N5_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N5_MASK) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N6_MASK (0x400000U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N6_SHIFT (22U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N6_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N6_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N6_MASK) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N7_MASK (0x800000U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N7_SHIFT (23U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N7_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N7_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N7_MASK) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N8_MASK (0x1000000U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N8_SHIFT (24U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N8_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N8_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N8_MASK) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N9_MASK (0x2000000U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N9_SHIFT (25U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N9_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N9_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N9_MASK) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N10_MASK (0x4000000U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N10_SHIFT (26U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N10_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N10_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N10_MASK) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N11_MASK (0x8000000U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N11_SHIFT (27U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N11_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N11_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N11_MASK) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N12_MASK (0x10000000U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N12_SHIFT (28U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N12_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N12(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N12_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N12_MASK) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N13_MASK (0x20000000U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N13_SHIFT (29U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N13_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N13(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N13_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N13_MASK) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N14_MASK (0x40000000U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N14_SHIFT (30U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N14_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N14(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N14_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N14_MASK) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N15_MASK (0x80000000U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N15_SHIFT (31U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N15_WIDTH (1U) #define GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N15(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N15_SHIFT)) & GTM_gtm_cls0_CCM0_TOM_OUT_TOM_OUT_N15_MASK) /*! @} */ /*! @name CCM0_ATOM_OUT - CCM[i] ATOM Output Register */ /*! @{ */ #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT0_MASK (0x1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT0_SHIFT (0U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT0_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT0_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT0_MASK) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT1_MASK (0x2U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT1_SHIFT (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT1_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT1_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT1_MASK) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT2_MASK (0x4U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT2_SHIFT (2U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT2_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT2_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT2_MASK) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT3_MASK (0x8U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT3_SHIFT (3U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT3_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT3_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT3_MASK) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT4_MASK (0x10U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT4_SHIFT (4U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT4_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT4_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT4_MASK) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT5_MASK (0x20U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT5_SHIFT (5U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT5_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT5_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT5_MASK) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT6_MASK (0x40U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT6_SHIFT (6U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT6_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT6_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT6_MASK) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT7_MASK (0x80U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT7_SHIFT (7U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT7_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT7_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT7_MASK) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N0_MASK (0x100U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N0_SHIFT (8U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N0_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N0_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N0_MASK) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N1_MASK (0x200U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N1_SHIFT (9U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N1_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N1_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N1_MASK) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N2_MASK (0x400U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N2_SHIFT (10U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N2_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N2_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N2_MASK) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N3_MASK (0x800U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N3_SHIFT (11U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N3_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N3_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N3_MASK) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N4_MASK (0x1000U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N4_SHIFT (12U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N4_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N4_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N4_MASK) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N5_MASK (0x2000U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N5_SHIFT (13U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N5_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N5_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N5_MASK) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N6_MASK (0x4000U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N6_SHIFT (14U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N6_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N6_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N6_MASK) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N7_MASK (0x8000U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N7_SHIFT (15U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N7_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N7_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_I_OUT_N7_MASK) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT0_MASK (0x10000U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT0_SHIFT (16U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT0_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT0_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT0_MASK) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT1_MASK (0x20000U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT1_SHIFT (17U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT1_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT1_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT1_MASK) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT2_MASK (0x40000U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT2_SHIFT (18U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT2_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT2_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT2_MASK) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT3_MASK (0x80000U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT3_SHIFT (19U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT3_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT3_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT3_MASK) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT4_MASK (0x100000U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT4_SHIFT (20U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT4_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT4_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT4_MASK) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT5_MASK (0x200000U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT5_SHIFT (21U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT5_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT5_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT5_MASK) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT6_MASK (0x400000U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT6_SHIFT (22U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT6_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT6_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT6_MASK) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT7_MASK (0x800000U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT7_SHIFT (23U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT7_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT7_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT7_MASK) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N0_MASK (0x1000000U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N0_SHIFT (24U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N0_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N0_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N0_MASK) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N1_MASK (0x2000000U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N1_SHIFT (25U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N1_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N1_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N1_MASK) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N2_MASK (0x4000000U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N2_SHIFT (26U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N2_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N2_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N2_MASK) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N3_MASK (0x8000000U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N3_SHIFT (27U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N3_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N3_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N3_MASK) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N4_MASK (0x10000000U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N4_SHIFT (28U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N4_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N4_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N4_MASK) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N5_MASK (0x20000000U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N5_SHIFT (29U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N5_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N5_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N5_MASK) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N6_MASK (0x40000000U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N6_SHIFT (30U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N6_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N6_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N6_MASK) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N7_MASK (0x80000000U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N7_SHIFT (31U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N7_WIDTH (1U) #define GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N7_SHIFT)) & GTM_gtm_cls0_CCM0_ATOM_OUT_ATOM_IP1_OUT_N7_MASK) /*! @} */ /*! @name CCM0_CMU_CLK_CFG - CCM[i] CMU Clock Configuration Register */ /*! @{ */ #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK0_SRC_MASK (0x3U) #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK0_SRC_SHIFT (0U) #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK0_SRC_WIDTH (2U) #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK0_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK0_SRC_SHIFT)) & GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK0_SRC_MASK) #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK1_SRC_MASK (0x30U) #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK1_SRC_SHIFT (4U) #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK1_SRC_WIDTH (2U) #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK1_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK1_SRC_SHIFT)) & GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK1_SRC_MASK) #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK2_SRC_MASK (0x300U) #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK2_SRC_SHIFT (8U) #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK2_SRC_WIDTH (2U) #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK2_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK2_SRC_SHIFT)) & GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK2_SRC_MASK) #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK3_SRC_MASK (0x3000U) #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK3_SRC_SHIFT (12U) #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK3_SRC_WIDTH (2U) #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK3_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK3_SRC_SHIFT)) & GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK3_SRC_MASK) #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK4_SRC_MASK (0x30000U) #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK4_SRC_SHIFT (16U) #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK4_SRC_WIDTH (2U) #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK4_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK4_SRC_SHIFT)) & GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK4_SRC_MASK) #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK5_SRC_MASK (0x300000U) #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK5_SRC_SHIFT (20U) #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK5_SRC_WIDTH (2U) #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK5_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK5_SRC_SHIFT)) & GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK5_SRC_MASK) #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK6_SRC_MASK (0x3000000U) #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK6_SRC_SHIFT (24U) #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK6_SRC_WIDTH (2U) #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK6_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK6_SRC_SHIFT)) & GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK6_SRC_MASK) #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK7_SRC_MASK (0x30000000U) #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK7_SRC_SHIFT (28U) #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK7_SRC_WIDTH (2U) #define GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK7_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK7_SRC_SHIFT)) & GTM_gtm_cls0_CCM0_CMU_CLK_CFG_CLK7_SRC_MASK) /*! @} */ /*! @name CCM0_CMU_FXCLK_CFG - CCM[i] CMU Fixed Clock Configuration Register */ /*! @{ */ #define GTM_gtm_cls0_CCM0_CMU_FXCLK_CFG_FXCLK0_SRC_MASK (0xFU) #define GTM_gtm_cls0_CCM0_CMU_FXCLK_CFG_FXCLK0_SRC_SHIFT (0U) #define GTM_gtm_cls0_CCM0_CMU_FXCLK_CFG_FXCLK0_SRC_WIDTH (4U) #define GTM_gtm_cls0_CCM0_CMU_FXCLK_CFG_FXCLK0_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_CMU_FXCLK_CFG_FXCLK0_SRC_SHIFT)) & GTM_gtm_cls0_CCM0_CMU_FXCLK_CFG_FXCLK0_SRC_MASK) /*! @} */ /*! @name CCM0_CFG - CCM[i] Configuration Register */ /*! @{ */ #define GTM_gtm_cls0_CCM0_CFG_EN_TIM_MASK (0x1U) #define GTM_gtm_cls0_CCM0_CFG_EN_TIM_SHIFT (0U) #define GTM_gtm_cls0_CCM0_CFG_EN_TIM_WIDTH (1U) #define GTM_gtm_cls0_CCM0_CFG_EN_TIM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_CFG_EN_TIM_SHIFT)) & GTM_gtm_cls0_CCM0_CFG_EN_TIM_MASK) #define GTM_gtm_cls0_CCM0_CFG_EN_TOM_SPE_TDTM_MASK (0x2U) #define GTM_gtm_cls0_CCM0_CFG_EN_TOM_SPE_TDTM_SHIFT (1U) #define GTM_gtm_cls0_CCM0_CFG_EN_TOM_SPE_TDTM_WIDTH (1U) #define GTM_gtm_cls0_CCM0_CFG_EN_TOM_SPE_TDTM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_CFG_EN_TOM_SPE_TDTM_SHIFT)) & GTM_gtm_cls0_CCM0_CFG_EN_TOM_SPE_TDTM_MASK) #define GTM_gtm_cls0_CCM0_CFG_EN_ATOM_ADTM_MASK (0x4U) #define GTM_gtm_cls0_CCM0_CFG_EN_ATOM_ADTM_SHIFT (2U) #define GTM_gtm_cls0_CCM0_CFG_EN_ATOM_ADTM_WIDTH (1U) #define GTM_gtm_cls0_CCM0_CFG_EN_ATOM_ADTM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_CFG_EN_ATOM_ADTM_SHIFT)) & GTM_gtm_cls0_CCM0_CFG_EN_ATOM_ADTM_MASK) #define GTM_gtm_cls0_CCM0_CFG_EN_MCS_MASK (0x8U) #define GTM_gtm_cls0_CCM0_CFG_EN_MCS_SHIFT (3U) #define GTM_gtm_cls0_CCM0_CFG_EN_MCS_WIDTH (1U) #define GTM_gtm_cls0_CCM0_CFG_EN_MCS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_CFG_EN_MCS_SHIFT)) & GTM_gtm_cls0_CCM0_CFG_EN_MCS_MASK) #define GTM_gtm_cls0_CCM0_CFG_EN_DPLL_MAP_MASK (0x10U) #define GTM_gtm_cls0_CCM0_CFG_EN_DPLL_MAP_SHIFT (4U) #define GTM_gtm_cls0_CCM0_CFG_EN_DPLL_MAP_WIDTH (1U) #define GTM_gtm_cls0_CCM0_CFG_EN_DPLL_MAP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_CFG_EN_DPLL_MAP_SHIFT)) & GTM_gtm_cls0_CCM0_CFG_EN_DPLL_MAP_MASK) #define GTM_gtm_cls0_CCM0_CFG_EN_BRC_MASK (0x20U) #define GTM_gtm_cls0_CCM0_CFG_EN_BRC_SHIFT (5U) #define GTM_gtm_cls0_CCM0_CFG_EN_BRC_WIDTH (1U) #define GTM_gtm_cls0_CCM0_CFG_EN_BRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_CFG_EN_BRC_SHIFT)) & GTM_gtm_cls0_CCM0_CFG_EN_BRC_MASK) #define GTM_gtm_cls0_CCM0_CFG_EN_PSM_MASK (0x40U) #define GTM_gtm_cls0_CCM0_CFG_EN_PSM_SHIFT (6U) #define GTM_gtm_cls0_CCM0_CFG_EN_PSM_WIDTH (1U) #define GTM_gtm_cls0_CCM0_CFG_EN_PSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_CFG_EN_PSM_SHIFT)) & GTM_gtm_cls0_CCM0_CFG_EN_PSM_MASK) #define GTM_gtm_cls0_CCM0_CFG_CLS_CLK_DIV_MASK (0x30000U) #define GTM_gtm_cls0_CCM0_CFG_CLS_CLK_DIV_SHIFT (16U) #define GTM_gtm_cls0_CCM0_CFG_CLS_CLK_DIV_WIDTH (2U) #define GTM_gtm_cls0_CCM0_CFG_CLS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_CFG_CLS_CLK_DIV_SHIFT)) & GTM_gtm_cls0_CCM0_CFG_CLS_CLK_DIV_MASK) #define GTM_gtm_cls0_CCM0_CFG_TBU_DIR1_MASK (0x40000000U) #define GTM_gtm_cls0_CCM0_CFG_TBU_DIR1_SHIFT (30U) #define GTM_gtm_cls0_CCM0_CFG_TBU_DIR1_WIDTH (1U) #define GTM_gtm_cls0_CCM0_CFG_TBU_DIR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_CFG_TBU_DIR1_SHIFT)) & GTM_gtm_cls0_CCM0_CFG_TBU_DIR1_MASK) #define GTM_gtm_cls0_CCM0_CFG_TBU_DIR2_MASK (0x80000000U) #define GTM_gtm_cls0_CCM0_CFG_TBU_DIR2_SHIFT (31U) #define GTM_gtm_cls0_CCM0_CFG_TBU_DIR2_WIDTH (1U) #define GTM_gtm_cls0_CCM0_CFG_TBU_DIR2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_CFG_TBU_DIR2_SHIFT)) & GTM_gtm_cls0_CCM0_CFG_TBU_DIR2_MASK) /*! @} */ /*! @name CCM0_PROT - CCM[i] Protection Register */ /*! @{ */ #define GTM_gtm_cls0_CCM0_PROT_CLS_PROT_MASK (0x1U) #define GTM_gtm_cls0_CCM0_PROT_CLS_PROT_SHIFT (0U) #define GTM_gtm_cls0_CCM0_PROT_CLS_PROT_WIDTH (1U) #define GTM_gtm_cls0_CCM0_PROT_CLS_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CCM0_PROT_CLS_PROT_SHIFT)) & GTM_gtm_cls0_CCM0_PROT_CLS_PROT_MASK) /*! @} */ /*! @name CDTM0_DTM4_CTRL - CDTM[i]_DTM[d] global configuration and control register */ /*! @{ */ #define GTM_gtm_cls0_CDTM0_DTM4_CTRL_CLK_SEL_MASK (0x3U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL_CLK_SEL_SHIFT (0U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL_CLK_SEL_WIDTH (2U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CTRL_CLK_SEL_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CTRL_CLK_SEL_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL_DTM_SEL_MASK (0xCU) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL_DTM_SEL_SHIFT (2U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL_DTM_SEL_WIDTH (2U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL_DTM_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CTRL_DTM_SEL_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CTRL_DTM_SEL_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL_UPD_MODE_MASK (0x70U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL_UPD_MODE_SHIFT (4U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL_UPD_MODE_WIDTH (3U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL_UPD_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CTRL_UPD_MODE_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CTRL_UPD_MODE_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL_CH_SHUTOFF_EN_MASK (0x80U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL_CH_SHUTOFF_EN_SHIFT (7U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL_CH_SHUTOFF_EN_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL_CH_SHUTOFF_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CTRL_CH_SHUTOFF_EN_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CTRL_CH_SHUTOFF_EN_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL_SR_UPD_EN_MASK (0x100U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL_SR_UPD_EN_SHIFT (8U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL_SR_UPD_EN_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL_SR_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CTRL_SR_UPD_EN_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CTRL_SR_UPD_EN_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL_SHUT_OFF_RST_MASK (0x10000U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL_SHUT_OFF_RST_SHIFT (16U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL_SHUT_OFF_RST_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL_SHUT_OFF_RST(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CTRL_SHUT_OFF_RST_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CTRL_SHUT_OFF_RST_MASK) /*! @} */ /*! @name CDTM0_DTM4_CH_CTRL1 - CDTM[i]_DTM[d] channel control register 1 */ /*! @{ */ #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1SEL_0_MASK (0x1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1SEL_0_SHIFT (0U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1SEL_0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1SEL_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1SEL_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1SEL_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SWAP_0_MASK (0x8U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SWAP_0_SHIFT (3U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SWAP_0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SWAP_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SWAP_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SWAP_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1F_0_MASK (0x30U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1F_0_SHIFT (4U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1F_0_WIDTH (2U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1F_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1F_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1F_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_XDT_EN_0_1_MASK (0x40U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_XDT_EN_0_1_SHIFT (6U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_XDT_EN_0_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_XDT_EN_0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_XDT_EN_0_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_XDT_EN_0_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1SEL_1_MASK (0x100U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1SEL_1_SHIFT (8U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1SEL_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1SEL_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1SEL_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1SEL_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_I1SEL_1_MASK (0x200U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_I1SEL_1_SHIFT (9U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_I1SEL_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_I1SEL_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_I1SEL_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_I1SEL_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SH_EN_1_MASK (0x400U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SH_EN_1_SHIFT (10U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SH_EN_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SH_EN_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SH_EN_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SH_EN_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SWAP_1_MASK (0x800U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SWAP_1_SHIFT (11U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SWAP_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SWAP_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SWAP_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SWAP_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1F_1_MASK (0x3000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1F_1_SHIFT (12U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1F_1_WIDTH (2U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1F_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1F_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1F_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1SEL_2_MASK (0x10000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1SEL_2_SHIFT (16U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1SEL_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1SEL_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1SEL_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1SEL_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_I1SEL_2_MASK (0x20000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_I1SEL_2_SHIFT (17U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_I1SEL_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_I1SEL_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_I1SEL_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_I1SEL_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SH_EN_2_MASK (0x40000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SH_EN_2_SHIFT (18U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SH_EN_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SH_EN_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SH_EN_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SH_EN_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SWAP_2_MASK (0x80000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SWAP_2_SHIFT (19U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SWAP_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SWAP_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SWAP_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SWAP_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1F_2_MASK (0x300000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1F_2_SHIFT (20U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1F_2_WIDTH (2U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1F_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1F_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1F_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_XDT_EN_2_3_MASK (0x400000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_XDT_EN_2_3_SHIFT (22U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_XDT_EN_2_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_XDT_EN_2_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_XDT_EN_2_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_XDT_EN_2_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1SEL_3_MASK (0x1000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1SEL_3_SHIFT (24U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1SEL_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1SEL_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1SEL_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1SEL_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_I1SEL_3_MASK (0x2000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_I1SEL_3_SHIFT (25U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_I1SEL_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_I1SEL_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_I1SEL_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_I1SEL_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SH_EN_3_MASK (0x4000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SH_EN_3_SHIFT (26U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SH_EN_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SH_EN_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SH_EN_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SH_EN_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SWAP_3_MASK (0x8000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SWAP_3_SHIFT (27U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SWAP_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SWAP_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SWAP_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_SWAP_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1F_3_MASK (0x30000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1F_3_SHIFT (28U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1F_3_WIDTH (2U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1F_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1F_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL1_O1F_3_MASK) /*! @} */ /*! @name CDTM0_DTM4_CH_CTRL2 - CDTM[i]_DTM[d] channel control register 2 */ /*! @{ */ #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL0_0_MASK (0x1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL0_0_SHIFT (0U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL0_0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL0_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL0_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL0_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC0_0_MASK (0x2U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC0_0_SHIFT (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC0_0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC0_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC0_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC0_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL0_0_MASK (0x4U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL0_0_SHIFT (2U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL0_0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL0_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL0_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL0_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT0_0_MASK (0x8U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT0_0_SHIFT (3U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT0_0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT0_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT0_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT0_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL1_0_MASK (0x10U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL1_0_SHIFT (4U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL1_0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL1_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL1_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC1_0_MASK (0x20U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC1_0_SHIFT (5U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC1_0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC1_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC1_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL1_0_MASK (0x40U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL1_0_SHIFT (6U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL1_0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL1_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL1_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT1_0_MASK (0x80U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT1_0_SHIFT (7U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT1_0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT1_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT1_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL0_1_MASK (0x100U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL0_1_SHIFT (8U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL0_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL0_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL0_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC0_1_MASK (0x200U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC0_1_SHIFT (9U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC0_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC0_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC0_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL0_1_MASK (0x400U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL0_1_SHIFT (10U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL0_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL0_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL0_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT0_1_MASK (0x800U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT0_1_SHIFT (11U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT0_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT0_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT0_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL1_1_MASK (0x1000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL1_1_SHIFT (12U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL1_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL1_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL1_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL1_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC1_1_MASK (0x2000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC1_1_SHIFT (13U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC1_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC1_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC1_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC1_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL1_1_MASK (0x4000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL1_1_SHIFT (14U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL1_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL1_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL1_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL1_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT1_1_MASK (0x8000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT1_1_SHIFT (15U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT1_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT1_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT1_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT1_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL0_2_MASK (0x10000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL0_2_SHIFT (16U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL0_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL0_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL0_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL0_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC0_2_MASK (0x20000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC0_2_SHIFT (17U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC0_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC0_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC0_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC0_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL0_2_MASK (0x40000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL0_2_SHIFT (18U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL0_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL0_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL0_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL0_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT0_2_MASK (0x80000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT0_2_SHIFT (19U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT0_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT0_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT0_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT0_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL1_2_MASK (0x100000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL1_2_SHIFT (20U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL1_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL1_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL1_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL1_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC1_2_MASK (0x200000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC1_2_SHIFT (21U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC1_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC1_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC1_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC1_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL1_2_MASK (0x400000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL1_2_SHIFT (22U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL1_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL1_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL1_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL1_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT1_2_MASK (0x800000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT1_2_SHIFT (23U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT1_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT1_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT1_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT1_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL0_3_MASK (0x1000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL0_3_SHIFT (24U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL0_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL0_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL0_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL0_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC0_3_MASK (0x2000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC0_3_SHIFT (25U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC0_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC0_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC0_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC0_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL0_3_MASK (0x4000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL0_3_SHIFT (26U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL0_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL0_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL0_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL0_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT0_3_MASK (0x8000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT0_3_SHIFT (27U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT0_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT0_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT0_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT0_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL1_3_MASK (0x10000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL1_3_SHIFT (28U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL1_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL1_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL1_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_POL1_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC1_3_MASK (0x20000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC1_3_SHIFT (29U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC1_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC1_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC1_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_OC1_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL1_3_MASK (0x40000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL1_3_SHIFT (30U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL1_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL1_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL1_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SL1_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT1_3_MASK (0x80000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT1_3_SHIFT (31U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT1_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT1_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT1_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_DT1_3_MASK) /*! @} */ /*! @name CDTM0_DTM4_CH_CTRL2_SR - CDTM[i] DTM[j] channel control register 2 shadow */ /*! @{ */ #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL0_0_SR_MASK (0x1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL0_0_SR_SHIFT (0U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL0_0_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL0_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL0_0_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL0_0_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC0_0_SR_MASK (0x2U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC0_0_SR_SHIFT (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC0_0_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC0_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC0_0_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC0_0_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL0_0_SR_MASK (0x4U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL0_0_SR_SHIFT (2U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL0_0_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL0_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL0_0_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL0_0_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT0_0_SR_MASK (0x8U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT0_0_SR_SHIFT (3U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT0_0_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT0_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT0_0_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT0_0_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL1_0_SR_MASK (0x10U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL1_0_SR_SHIFT (4U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL1_0_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL1_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL1_0_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL1_0_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC1_0_SR_MASK (0x20U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC1_0_SR_SHIFT (5U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC1_0_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC1_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC1_0_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC1_0_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL1_0_SR_MASK (0x40U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL1_0_SR_SHIFT (6U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL1_0_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL1_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL1_0_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL1_0_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT1_0_SR_MASK (0x80U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT1_0_SR_SHIFT (7U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT1_0_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT1_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT1_0_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT1_0_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL0_1_SR_MASK (0x100U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL0_1_SR_SHIFT (8U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL0_1_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL0_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL0_1_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL0_1_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC0_1_SR_MASK (0x200U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC0_1_SR_SHIFT (9U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC0_1_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC0_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC0_1_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC0_1_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL0_1_SR_MASK (0x400U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL0_1_SR_SHIFT (10U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL0_1_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL0_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL0_1_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL0_1_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT0_1_SR_MASK (0x800U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT0_1_SR_SHIFT (11U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT0_1_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT0_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT0_1_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT0_1_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL1_1_SR_MASK (0x1000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL1_1_SR_SHIFT (12U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL1_1_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL1_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL1_1_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL1_1_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC1_1_SR_MASK (0x2000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC1_1_SR_SHIFT (13U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC1_1_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC1_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC1_1_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC1_1_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL1_1_SR_MASK (0x4000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL1_1_SR_SHIFT (14U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL1_1_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL1_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL1_1_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL1_1_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT1_1_SR_MASK (0x8000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT1_1_SR_SHIFT (15U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT1_1_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT1_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT1_1_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT1_1_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL0_2_SR_MASK (0x10000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL0_2_SR_SHIFT (16U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL0_2_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL0_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL0_2_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL0_2_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC0_2_SR_MASK (0x20000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC0_2_SR_SHIFT (17U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC0_2_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC0_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC0_2_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC0_2_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL0_2_SR_MASK (0x40000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL0_2_SR_SHIFT (18U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL0_2_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL0_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL0_2_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL0_2_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT0_2_SR_MASK (0x80000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT0_2_SR_SHIFT (19U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT0_2_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT0_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT0_2_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT0_2_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL1_2_SR_MASK (0x100000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL1_2_SR_SHIFT (20U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL1_2_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL1_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL1_2_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL1_2_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC1_2_SR_MASK (0x200000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC1_2_SR_SHIFT (21U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC1_2_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC1_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC1_2_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC1_2_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL1_2_SR_MASK (0x400000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL1_2_SR_SHIFT (22U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL1_2_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL1_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL1_2_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL1_2_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT1_2_SR_MASK (0x800000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT1_2_SR_SHIFT (23U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT1_2_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT1_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT1_2_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT1_2_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL0_3_SR_MASK (0x1000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL0_3_SR_SHIFT (24U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL0_3_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL0_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL0_3_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL0_3_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC0_3_SR_MASK (0x2000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC0_3_SR_SHIFT (25U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC0_3_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC0_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC0_3_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC0_3_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL0_3_SR_MASK (0x4000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL0_3_SR_SHIFT (26U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL0_3_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL0_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL0_3_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL0_3_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT0_3_SR_MASK (0x8000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT0_3_SR_SHIFT (27U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT0_3_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT0_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT0_3_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT0_3_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL1_3_SR_MASK (0x10000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL1_3_SR_SHIFT (28U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL1_3_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL1_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL1_3_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_POL1_3_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC1_3_SR_MASK (0x20000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC1_3_SR_SHIFT (29U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC1_3_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC1_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC1_3_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_OC1_3_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL1_3_SR_MASK (0x40000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL1_3_SR_SHIFT (30U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL1_3_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL1_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL1_3_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_SL1_3_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT1_3_SR_MASK (0x80000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT1_3_SR_SHIFT (31U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT1_3_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT1_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT1_3_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL2_SR_DT1_3_SR_MASK) /*! @} */ /*! @name CDTM0_DTM4_PS_CTRL - CDTM[i]_DTM[d] phase shift unit configuration and control register */ /*! @{ */ #define GTM_gtm_cls0_CDTM0_DTM4_PS_CTRL_RELBLK_MASK (0x3FFU) #define GTM_gtm_cls0_CDTM0_DTM4_PS_CTRL_RELBLK_SHIFT (0U) #define GTM_gtm_cls0_CDTM0_DTM4_PS_CTRL_RELBLK_WIDTH (10U) #define GTM_gtm_cls0_CDTM0_DTM4_PS_CTRL_RELBLK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_PS_CTRL_RELBLK_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_PS_CTRL_RELBLK_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_PS_CTRL_PSU_IN_SEL_MASK (0x10000U) #define GTM_gtm_cls0_CDTM0_DTM4_PS_CTRL_PSU_IN_SEL_SHIFT (16U) #define GTM_gtm_cls0_CDTM0_DTM4_PS_CTRL_PSU_IN_SEL_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_PS_CTRL_PSU_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_PS_CTRL_PSU_IN_SEL_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_PS_CTRL_PSU_IN_SEL_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_PS_CTRL_IN_POL_MASK (0x20000U) #define GTM_gtm_cls0_CDTM0_DTM4_PS_CTRL_IN_POL_SHIFT (17U) #define GTM_gtm_cls0_CDTM0_DTM4_PS_CTRL_IN_POL_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_PS_CTRL_IN_POL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_PS_CTRL_IN_POL_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_PS_CTRL_IN_POL_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_PS_CTRL_TIM_SEL_MASK (0x40000U) #define GTM_gtm_cls0_CDTM0_DTM4_PS_CTRL_TIM_SEL_SHIFT (18U) #define GTM_gtm_cls0_CDTM0_DTM4_PS_CTRL_TIM_SEL_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_PS_CTRL_TIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_PS_CTRL_TIM_SEL_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_PS_CTRL_TIM_SEL_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_PS_CTRL_SHIFT_SEL_MASK (0x300000U) #define GTM_gtm_cls0_CDTM0_DTM4_PS_CTRL_SHIFT_SEL_SHIFT (20U) #define GTM_gtm_cls0_CDTM0_DTM4_PS_CTRL_SHIFT_SEL_WIDTH (2U) #define GTM_gtm_cls0_CDTM0_DTM4_PS_CTRL_SHIFT_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_PS_CTRL_SHIFT_SEL_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_PS_CTRL_SHIFT_SEL_MASK) /*! @} */ /*! @name CDTM0_DTM4_CH_DTV - CDTM[i]_DTM[d] channel [x] dead time reload values */ /*! @{ */ #define GTM_gtm_cls0_CDTM0_DTM4_CH_DTV_RELRISE_MASK (0x1FFFU) #define GTM_gtm_cls0_CDTM0_DTM4_CH_DTV_RELRISE_SHIFT (0U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_DTV_RELRISE_WIDTH (13U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_DTV_RELRISE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_DTV_RELRISE_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_DTV_RELRISE_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_DTV_RELFALL_MASK (0x1FFF0000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_DTV_RELFALL_SHIFT (16U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_DTV_RELFALL_WIDTH (13U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_DTV_RELFALL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_DTV_RELFALL_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_DTV_RELFALL_MASK) /*! @} */ /*! @name CDTM0_DTM4_CH_SR - CDTM[i]_DTM[d] channel shadow register */ /*! @{ */ #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL0_0_SR_SR_MASK (0x1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL0_0_SR_SR_SHIFT (0U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL0_0_SR_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL0_0_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL0_0_SR_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL0_0_SR_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL1_0_SR_SR_MASK (0x2U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL1_0_SR_SR_SHIFT (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL1_0_SR_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL1_0_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL1_0_SR_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL1_0_SR_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL0_1_SR_SR_MASK (0x4U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL0_1_SR_SR_SHIFT (2U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL0_1_SR_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL0_1_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL0_1_SR_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL0_1_SR_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL1_1_SR_SR_MASK (0x8U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL1_1_SR_SR_SHIFT (3U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL1_1_SR_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL1_1_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL1_1_SR_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL1_1_SR_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL0_2_SR_SR_MASK (0x10U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL0_2_SR_SR_SHIFT (4U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL0_2_SR_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL0_2_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL0_2_SR_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL0_2_SR_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL1_2_SR_SR_MASK (0x20U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL1_2_SR_SR_SHIFT (5U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL1_2_SR_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL1_2_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL1_2_SR_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL1_2_SR_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL0_3_SR_SR_MASK (0x40U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL0_3_SR_SR_SHIFT (6U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL0_3_SR_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL0_3_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL0_3_SR_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL0_3_SR_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL1_3_SR_SR_MASK (0x80U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL1_3_SR_SR_SHIFT (7U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL1_3_SR_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL1_3_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL1_3_SR_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_SR_SL1_3_SR_SR_MASK) /*! @} */ /*! @name CDTM0_DTM4_CH_CTRL3 - CDTM[i]_DTM[d] channel control register 3 */ /*! @{ */ #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CII0_MASK (0x1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CII0_SHIFT (0U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CII0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CII0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CII0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CII0_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CIS0_MASK (0x2U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CIS0_SHIFT (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CIS0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CIS0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CIS0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CIS0_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL0_0_MASK (0x4U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL0_0_SHIFT (2U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL0_0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL0_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL0_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL0_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL1_0_MASK (0x8U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL1_0_SHIFT (3U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL1_0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL1_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL1_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CII1_MASK (0x100U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CII1_SHIFT (8U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CII1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CII1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CII1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CII1_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CIS1_MASK (0x200U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CIS1_SHIFT (9U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CIS1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CIS1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CIS1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CIS1_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL0_1_MASK (0x400U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL0_1_SHIFT (10U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL0_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL0_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL0_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL1_1_MASK (0x800U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL1_1_SHIFT (11U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL1_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL1_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL1_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL1_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CII2_MASK (0x10000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CII2_SHIFT (16U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CII2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CII2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CII2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CII2_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CIS2_MASK (0x20000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CIS2_SHIFT (17U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CIS2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CIS2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CIS2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CIS2_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL0_2_MASK (0x40000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL0_2_SHIFT (18U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL0_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL0_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL0_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL0_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL1_2_MASK (0x80000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL1_2_SHIFT (19U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL1_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL1_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL1_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL1_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CII3_MASK (0x1000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CII3_SHIFT (24U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CII3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CII3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CII3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CII3_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CIS3_MASK (0x2000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CIS3_SHIFT (25U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CIS3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CIS3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CIS3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_CIS3_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL0_3_MASK (0x4000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL0_3_SHIFT (26U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL0_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL0_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL0_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL0_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL1_3_MASK (0x8000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL1_3_SHIFT (27U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL1_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL1_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL1_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH_CTRL3_TSEL1_3_MASK) /*! @} */ /*! @name CDTM0_DTM4_CTRL2 - CDTM[i]_DTM[d] global configuration and control register 2 */ /*! @{ */ #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_SEL_0_MASK (0x7U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_SEL_0_SHIFT (0U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_SEL_0_WIDTH (3U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_SEL_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_SEL_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_SEL_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_POL_0_MASK (0x8U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_POL_0_SHIFT (3U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_POL_0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_POL_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_POL_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_POL_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_UPD_MODE_0_MASK (0x30U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_UPD_MODE_0_SHIFT (4U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_UPD_MODE_0_WIDTH (2U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_UPD_MODE_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CTRL2_UPD_MODE_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CTRL2_UPD_MODE_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUT_OFF_RST_0_MASK (0x40U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUT_OFF_RST_0_SHIFT (6U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUT_OFF_RST_0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUT_OFF_RST_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUT_OFF_RST_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUT_OFF_RST_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_WR_EN_0_MASK (0x80U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_WR_EN_0_SHIFT (7U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_WR_EN_0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_WR_EN_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CTRL2_WR_EN_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CTRL2_WR_EN_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_SEL_1_MASK (0x700U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_SEL_1_SHIFT (8U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_SEL_1_WIDTH (3U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_SEL_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_SEL_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_SEL_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_POL_1_MASK (0x800U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_POL_1_SHIFT (11U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_POL_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_POL_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_POL_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_POL_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_UPD_MODE_1_MASK (0x3000U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_UPD_MODE_1_SHIFT (12U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_UPD_MODE_1_WIDTH (2U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_UPD_MODE_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CTRL2_UPD_MODE_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CTRL2_UPD_MODE_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUT_OFF_RST_1_MASK (0x4000U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUT_OFF_RST_1_SHIFT (14U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUT_OFF_RST_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUT_OFF_RST_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUT_OFF_RST_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUT_OFF_RST_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_WR_EN_1_MASK (0x8000U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_WR_EN_1_SHIFT (15U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_WR_EN_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_WR_EN_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CTRL2_WR_EN_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CTRL2_WR_EN_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_SEL_2_MASK (0x70000U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_SEL_2_SHIFT (16U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_SEL_2_WIDTH (3U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_SEL_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_SEL_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_SEL_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_POL_2_MASK (0x80000U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_POL_2_SHIFT (19U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_POL_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_POL_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_POL_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_POL_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_UPD_MODE_2_MASK (0x300000U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_UPD_MODE_2_SHIFT (20U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_UPD_MODE_2_WIDTH (2U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_UPD_MODE_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CTRL2_UPD_MODE_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CTRL2_UPD_MODE_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUT_OFF_RST_2_MASK (0x400000U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUT_OFF_RST_2_SHIFT (22U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUT_OFF_RST_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUT_OFF_RST_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUT_OFF_RST_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUT_OFF_RST_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_WR_EN_2_MASK (0x800000U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_WR_EN_2_SHIFT (23U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_WR_EN_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_WR_EN_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CTRL2_WR_EN_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CTRL2_WR_EN_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_SEL_3_MASK (0x7000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_SEL_3_SHIFT (24U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_SEL_3_WIDTH (3U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_SEL_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_SEL_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_SEL_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_POL_3_MASK (0x8000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_POL_3_SHIFT (27U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_POL_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_POL_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_POL_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUTOFF_POL_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_UPD_MODE_3_MASK (0x30000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_UPD_MODE_3_SHIFT (28U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_UPD_MODE_3_WIDTH (2U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_UPD_MODE_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CTRL2_UPD_MODE_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CTRL2_UPD_MODE_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUT_OFF_RST_3_MASK (0x40000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUT_OFF_RST_3_SHIFT (30U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUT_OFF_RST_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUT_OFF_RST_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUT_OFF_RST_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CTRL2_SHUT_OFF_RST_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_WR_EN_3_MASK (0x80000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_WR_EN_3_SHIFT (31U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_WR_EN_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CTRL2_WR_EN_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CTRL2_WR_EN_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CTRL2_WR_EN_3_MASK) /*! @} */ /*! @name CDTM0_DTM4_CH0_DTV_SR - CDTM[i]_DTM[d] channel [x] dead time shadow values */ /*! @{ */ #define GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELRISE_SR_MASK (0x1FFFU) #define GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELRISE_SR_SHIFT (0U) #define GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELRISE_SR_WIDTH (13U) #define GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELRISE_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELRISE_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELRISE_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELRISE_UPD_FE0RE1_MASK (0x4000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT (14U) #define GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELRISE_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELRISE_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELRISE_UPD_FE0RE1_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELRISE_UPD_EN_MASK (0x8000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELRISE_UPD_EN_SHIFT (15U) #define GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELRISE_UPD_EN_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELRISE_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELRISE_UPD_EN_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELRISE_UPD_EN_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELFALL_SR_MASK (0x1FFF0000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELFALL_SR_SHIFT (16U) #define GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELFALL_SR_WIDTH (13U) #define GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELFALL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELFALL_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELFALL_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELFALL_UPD_FE0RE1_MASK (0x40000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT (30U) #define GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELFALL_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELFALL_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELFALL_UPD_FE0RE1_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELFALL_UPD_EN_MASK (0x80000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELFALL_UPD_EN_SHIFT (31U) #define GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELFALL_UPD_EN_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELFALL_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELFALL_UPD_EN_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH0_DTV_SR_RELFALL_UPD_EN_MASK) /*! @} */ /*! @name CDTM0_DTM4_CH1_DTV_SR - CDTM[i]_DTM[d] channel [x] dead time shadow values */ /*! @{ */ #define GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELRISE_SR_MASK (0x1FFFU) #define GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELRISE_SR_SHIFT (0U) #define GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELRISE_SR_WIDTH (13U) #define GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELRISE_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELRISE_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELRISE_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELRISE_UPD_FE0RE1_MASK (0x4000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT (14U) #define GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELRISE_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELRISE_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELRISE_UPD_FE0RE1_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELRISE_UPD_EN_MASK (0x8000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELRISE_UPD_EN_SHIFT (15U) #define GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELRISE_UPD_EN_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELRISE_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELRISE_UPD_EN_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELRISE_UPD_EN_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELFALL_SR_MASK (0x1FFF0000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELFALL_SR_SHIFT (16U) #define GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELFALL_SR_WIDTH (13U) #define GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELFALL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELFALL_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELFALL_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELFALL_UPD_FE0RE1_MASK (0x40000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT (30U) #define GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELFALL_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELFALL_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELFALL_UPD_FE0RE1_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELFALL_UPD_EN_MASK (0x80000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELFALL_UPD_EN_SHIFT (31U) #define GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELFALL_UPD_EN_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELFALL_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELFALL_UPD_EN_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH1_DTV_SR_RELFALL_UPD_EN_MASK) /*! @} */ /*! @name CDTM0_DTM4_CH2_DTV_SR - CDTM[i]_DTM[d] channel [x] dead time shadow values */ /*! @{ */ #define GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELRISE_SR_MASK (0x1FFFU) #define GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELRISE_SR_SHIFT (0U) #define GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELRISE_SR_WIDTH (13U) #define GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELRISE_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELRISE_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELRISE_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELRISE_UPD_FE0RE1_MASK (0x4000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT (14U) #define GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELRISE_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELRISE_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELRISE_UPD_FE0RE1_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELRISE_UPD_EN_MASK (0x8000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELRISE_UPD_EN_SHIFT (15U) #define GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELRISE_UPD_EN_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELRISE_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELRISE_UPD_EN_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELRISE_UPD_EN_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELFALL_SR_MASK (0x1FFF0000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELFALL_SR_SHIFT (16U) #define GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELFALL_SR_WIDTH (13U) #define GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELFALL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELFALL_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELFALL_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELFALL_UPD_FE0RE1_MASK (0x40000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT (30U) #define GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELFALL_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELFALL_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELFALL_UPD_FE0RE1_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELFALL_UPD_EN_MASK (0x80000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELFALL_UPD_EN_SHIFT (31U) #define GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELFALL_UPD_EN_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELFALL_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELFALL_UPD_EN_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH2_DTV_SR_RELFALL_UPD_EN_MASK) /*! @} */ /*! @name CDTM0_DTM4_CH3_DTV_SR - CDTM[i]_DTM[d] channel [x] dead time shadow values */ /*! @{ */ #define GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELRISE_SR_MASK (0x1FFFU) #define GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELRISE_SR_SHIFT (0U) #define GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELRISE_SR_WIDTH (13U) #define GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELRISE_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELRISE_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELRISE_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELRISE_UPD_FE0RE1_MASK (0x4000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT (14U) #define GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELRISE_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELRISE_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELRISE_UPD_FE0RE1_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELRISE_UPD_EN_MASK (0x8000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELRISE_UPD_EN_SHIFT (15U) #define GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELRISE_UPD_EN_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELRISE_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELRISE_UPD_EN_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELRISE_UPD_EN_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELFALL_SR_MASK (0x1FFF0000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELFALL_SR_SHIFT (16U) #define GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELFALL_SR_WIDTH (13U) #define GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELFALL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELFALL_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELFALL_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELFALL_UPD_FE0RE1_MASK (0x40000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT (30U) #define GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELFALL_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELFALL_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELFALL_UPD_FE0RE1_MASK) #define GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELFALL_UPD_EN_MASK (0x80000000U) #define GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELFALL_UPD_EN_SHIFT (31U) #define GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELFALL_UPD_EN_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELFALL_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELFALL_UPD_EN_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM4_CH3_DTV_SR_RELFALL_UPD_EN_MASK) /*! @} */ /*! @name CDTM0_DTM5_CTRL - CDTM[i]_DTM[d] global configuration and control register */ /*! @{ */ #define GTM_gtm_cls0_CDTM0_DTM5_CTRL_CLK_SEL_MASK (0x3U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL_CLK_SEL_SHIFT (0U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL_CLK_SEL_WIDTH (2U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CTRL_CLK_SEL_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CTRL_CLK_SEL_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL_DTM_SEL_MASK (0xCU) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL_DTM_SEL_SHIFT (2U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL_DTM_SEL_WIDTH (2U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL_DTM_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CTRL_DTM_SEL_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CTRL_DTM_SEL_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL_UPD_MODE_MASK (0x70U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL_UPD_MODE_SHIFT (4U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL_UPD_MODE_WIDTH (3U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL_UPD_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CTRL_UPD_MODE_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CTRL_UPD_MODE_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL_CH_SHUTOFF_EN_MASK (0x80U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL_CH_SHUTOFF_EN_SHIFT (7U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL_CH_SHUTOFF_EN_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL_CH_SHUTOFF_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CTRL_CH_SHUTOFF_EN_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CTRL_CH_SHUTOFF_EN_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL_SR_UPD_EN_MASK (0x100U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL_SR_UPD_EN_SHIFT (8U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL_SR_UPD_EN_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL_SR_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CTRL_SR_UPD_EN_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CTRL_SR_UPD_EN_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL_SHUT_OFF_RST_MASK (0x10000U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL_SHUT_OFF_RST_SHIFT (16U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL_SHUT_OFF_RST_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL_SHUT_OFF_RST(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CTRL_SHUT_OFF_RST_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CTRL_SHUT_OFF_RST_MASK) /*! @} */ /*! @name CDTM0_DTM5_CH_CTRL1 - CDTM[i]_DTM[d] channel control register 1 */ /*! @{ */ #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1SEL_0_MASK (0x1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1SEL_0_SHIFT (0U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1SEL_0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1SEL_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1SEL_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1SEL_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_I1SEL_0_MASK (0x2U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_I1SEL_0_SHIFT (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_I1SEL_0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_I1SEL_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_I1SEL_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_I1SEL_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SWAP_0_MASK (0x8U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SWAP_0_SHIFT (3U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SWAP_0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SWAP_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SWAP_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SWAP_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1F_0_MASK (0x30U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1F_0_SHIFT (4U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1F_0_WIDTH (2U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1F_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1F_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1F_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_XDT_EN_0_1_MASK (0x40U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_XDT_EN_0_1_SHIFT (6U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_XDT_EN_0_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_XDT_EN_0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_XDT_EN_0_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_XDT_EN_0_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1SEL_1_MASK (0x100U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1SEL_1_SHIFT (8U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1SEL_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1SEL_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1SEL_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1SEL_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_I1SEL_1_MASK (0x200U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_I1SEL_1_SHIFT (9U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_I1SEL_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_I1SEL_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_I1SEL_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_I1SEL_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SH_EN_1_MASK (0x400U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SH_EN_1_SHIFT (10U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SH_EN_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SH_EN_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SH_EN_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SH_EN_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SWAP_1_MASK (0x800U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SWAP_1_SHIFT (11U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SWAP_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SWAP_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SWAP_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SWAP_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1F_1_MASK (0x3000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1F_1_SHIFT (12U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1F_1_WIDTH (2U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1F_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1F_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1F_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1SEL_2_MASK (0x10000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1SEL_2_SHIFT (16U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1SEL_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1SEL_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1SEL_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1SEL_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_I1SEL_2_MASK (0x20000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_I1SEL_2_SHIFT (17U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_I1SEL_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_I1SEL_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_I1SEL_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_I1SEL_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SH_EN_2_MASK (0x40000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SH_EN_2_SHIFT (18U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SH_EN_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SH_EN_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SH_EN_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SH_EN_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SWAP_2_MASK (0x80000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SWAP_2_SHIFT (19U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SWAP_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SWAP_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SWAP_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SWAP_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1F_2_MASK (0x300000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1F_2_SHIFT (20U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1F_2_WIDTH (2U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1F_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1F_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1F_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_XDT_EN_2_3_MASK (0x400000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_XDT_EN_2_3_SHIFT (22U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_XDT_EN_2_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_XDT_EN_2_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_XDT_EN_2_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_XDT_EN_2_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1SEL_3_MASK (0x1000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1SEL_3_SHIFT (24U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1SEL_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1SEL_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1SEL_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1SEL_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_I1SEL_3_MASK (0x2000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_I1SEL_3_SHIFT (25U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_I1SEL_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_I1SEL_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_I1SEL_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_I1SEL_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SH_EN_3_MASK (0x4000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SH_EN_3_SHIFT (26U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SH_EN_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SH_EN_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SH_EN_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SH_EN_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SWAP_3_MASK (0x8000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SWAP_3_SHIFT (27U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SWAP_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SWAP_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SWAP_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_SWAP_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1F_3_MASK (0x30000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1F_3_SHIFT (28U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1F_3_WIDTH (2U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1F_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1F_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL1_O1F_3_MASK) /*! @} */ /*! @name CDTM0_DTM5_CH_CTRL2 - CDTM[i]_DTM[d] channel control register 2 */ /*! @{ */ #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL0_0_MASK (0x1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL0_0_SHIFT (0U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL0_0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL0_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL0_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL0_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC0_0_MASK (0x2U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC0_0_SHIFT (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC0_0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC0_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC0_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC0_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL0_0_MASK (0x4U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL0_0_SHIFT (2U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL0_0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL0_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL0_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL0_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT0_0_MASK (0x8U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT0_0_SHIFT (3U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT0_0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT0_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT0_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT0_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL1_0_MASK (0x10U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL1_0_SHIFT (4U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL1_0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL1_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL1_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC1_0_MASK (0x20U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC1_0_SHIFT (5U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC1_0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC1_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC1_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL1_0_MASK (0x40U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL1_0_SHIFT (6U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL1_0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL1_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL1_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT1_0_MASK (0x80U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT1_0_SHIFT (7U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT1_0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT1_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT1_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL0_1_MASK (0x100U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL0_1_SHIFT (8U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL0_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL0_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL0_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC0_1_MASK (0x200U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC0_1_SHIFT (9U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC0_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC0_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC0_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL0_1_MASK (0x400U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL0_1_SHIFT (10U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL0_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL0_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL0_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT0_1_MASK (0x800U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT0_1_SHIFT (11U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT0_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT0_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT0_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL1_1_MASK (0x1000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL1_1_SHIFT (12U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL1_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL1_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL1_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL1_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC1_1_MASK (0x2000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC1_1_SHIFT (13U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC1_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC1_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC1_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC1_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL1_1_MASK (0x4000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL1_1_SHIFT (14U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL1_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL1_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL1_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL1_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT1_1_MASK (0x8000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT1_1_SHIFT (15U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT1_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT1_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT1_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT1_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL0_2_MASK (0x10000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL0_2_SHIFT (16U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL0_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL0_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL0_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL0_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC0_2_MASK (0x20000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC0_2_SHIFT (17U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC0_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC0_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC0_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC0_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL0_2_MASK (0x40000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL0_2_SHIFT (18U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL0_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL0_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL0_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL0_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT0_2_MASK (0x80000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT0_2_SHIFT (19U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT0_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT0_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT0_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT0_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL1_2_MASK (0x100000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL1_2_SHIFT (20U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL1_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL1_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL1_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL1_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC1_2_MASK (0x200000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC1_2_SHIFT (21U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC1_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC1_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC1_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC1_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL1_2_MASK (0x400000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL1_2_SHIFT (22U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL1_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL1_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL1_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL1_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT1_2_MASK (0x800000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT1_2_SHIFT (23U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT1_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT1_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT1_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT1_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL0_3_MASK (0x1000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL0_3_SHIFT (24U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL0_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL0_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL0_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL0_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC0_3_MASK (0x2000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC0_3_SHIFT (25U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC0_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC0_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC0_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC0_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL0_3_MASK (0x4000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL0_3_SHIFT (26U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL0_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL0_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL0_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL0_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT0_3_MASK (0x8000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT0_3_SHIFT (27U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT0_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT0_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT0_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT0_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL1_3_MASK (0x10000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL1_3_SHIFT (28U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL1_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL1_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL1_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_POL1_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC1_3_MASK (0x20000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC1_3_SHIFT (29U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC1_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC1_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC1_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_OC1_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL1_3_MASK (0x40000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL1_3_SHIFT (30U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL1_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL1_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL1_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SL1_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT1_3_MASK (0x80000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT1_3_SHIFT (31U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT1_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT1_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT1_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_DT1_3_MASK) /*! @} */ /*! @name CDTM0_DTM5_CH_CTRL2_SR - CDTM[i] DTM[j] channel control register 2 shadow */ /*! @{ */ #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL0_0_SR_MASK (0x1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL0_0_SR_SHIFT (0U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL0_0_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL0_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL0_0_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL0_0_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC0_0_SR_MASK (0x2U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC0_0_SR_SHIFT (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC0_0_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC0_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC0_0_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC0_0_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL0_0_SR_MASK (0x4U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL0_0_SR_SHIFT (2U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL0_0_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL0_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL0_0_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL0_0_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT0_0_SR_MASK (0x8U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT0_0_SR_SHIFT (3U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT0_0_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT0_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT0_0_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT0_0_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL1_0_SR_MASK (0x10U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL1_0_SR_SHIFT (4U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL1_0_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL1_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL1_0_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL1_0_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC1_0_SR_MASK (0x20U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC1_0_SR_SHIFT (5U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC1_0_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC1_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC1_0_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC1_0_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL1_0_SR_MASK (0x40U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL1_0_SR_SHIFT (6U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL1_0_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL1_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL1_0_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL1_0_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT1_0_SR_MASK (0x80U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT1_0_SR_SHIFT (7U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT1_0_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT1_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT1_0_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT1_0_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL0_1_SR_MASK (0x100U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL0_1_SR_SHIFT (8U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL0_1_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL0_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL0_1_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL0_1_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC0_1_SR_MASK (0x200U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC0_1_SR_SHIFT (9U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC0_1_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC0_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC0_1_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC0_1_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL0_1_SR_MASK (0x400U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL0_1_SR_SHIFT (10U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL0_1_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL0_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL0_1_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL0_1_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT0_1_SR_MASK (0x800U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT0_1_SR_SHIFT (11U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT0_1_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT0_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT0_1_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT0_1_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL1_1_SR_MASK (0x1000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL1_1_SR_SHIFT (12U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL1_1_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL1_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL1_1_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL1_1_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC1_1_SR_MASK (0x2000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC1_1_SR_SHIFT (13U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC1_1_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC1_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC1_1_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC1_1_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL1_1_SR_MASK (0x4000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL1_1_SR_SHIFT (14U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL1_1_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL1_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL1_1_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL1_1_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT1_1_SR_MASK (0x8000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT1_1_SR_SHIFT (15U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT1_1_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT1_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT1_1_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT1_1_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL0_2_SR_MASK (0x10000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL0_2_SR_SHIFT (16U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL0_2_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL0_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL0_2_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL0_2_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC0_2_SR_MASK (0x20000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC0_2_SR_SHIFT (17U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC0_2_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC0_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC0_2_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC0_2_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL0_2_SR_MASK (0x40000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL0_2_SR_SHIFT (18U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL0_2_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL0_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL0_2_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL0_2_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT0_2_SR_MASK (0x80000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT0_2_SR_SHIFT (19U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT0_2_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT0_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT0_2_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT0_2_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL1_2_SR_MASK (0x100000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL1_2_SR_SHIFT (20U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL1_2_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL1_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL1_2_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL1_2_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC1_2_SR_MASK (0x200000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC1_2_SR_SHIFT (21U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC1_2_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC1_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC1_2_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC1_2_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL1_2_SR_MASK (0x400000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL1_2_SR_SHIFT (22U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL1_2_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL1_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL1_2_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL1_2_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT1_2_SR_MASK (0x800000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT1_2_SR_SHIFT (23U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT1_2_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT1_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT1_2_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT1_2_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL0_3_SR_MASK (0x1000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL0_3_SR_SHIFT (24U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL0_3_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL0_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL0_3_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL0_3_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC0_3_SR_MASK (0x2000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC0_3_SR_SHIFT (25U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC0_3_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC0_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC0_3_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC0_3_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL0_3_SR_MASK (0x4000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL0_3_SR_SHIFT (26U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL0_3_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL0_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL0_3_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL0_3_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT0_3_SR_MASK (0x8000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT0_3_SR_SHIFT (27U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT0_3_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT0_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT0_3_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT0_3_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL1_3_SR_MASK (0x10000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL1_3_SR_SHIFT (28U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL1_3_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL1_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL1_3_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_POL1_3_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC1_3_SR_MASK (0x20000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC1_3_SR_SHIFT (29U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC1_3_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC1_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC1_3_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_OC1_3_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL1_3_SR_MASK (0x40000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL1_3_SR_SHIFT (30U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL1_3_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL1_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL1_3_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_SL1_3_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT1_3_SR_MASK (0x80000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT1_3_SR_SHIFT (31U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT1_3_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT1_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT1_3_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL2_SR_DT1_3_SR_MASK) /*! @} */ /*! @name CDTM0_DTM5_PS_CTRL - CDTM[i]_DTM[d] phase shift unit configuration and control register */ /*! @{ */ #define GTM_gtm_cls0_CDTM0_DTM5_PS_CTRL_RELBLK_MASK (0x3FFU) #define GTM_gtm_cls0_CDTM0_DTM5_PS_CTRL_RELBLK_SHIFT (0U) #define GTM_gtm_cls0_CDTM0_DTM5_PS_CTRL_RELBLK_WIDTH (10U) #define GTM_gtm_cls0_CDTM0_DTM5_PS_CTRL_RELBLK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_PS_CTRL_RELBLK_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_PS_CTRL_RELBLK_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_PS_CTRL_PSU_IN_SEL_MASK (0x10000U) #define GTM_gtm_cls0_CDTM0_DTM5_PS_CTRL_PSU_IN_SEL_SHIFT (16U) #define GTM_gtm_cls0_CDTM0_DTM5_PS_CTRL_PSU_IN_SEL_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_PS_CTRL_PSU_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_PS_CTRL_PSU_IN_SEL_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_PS_CTRL_PSU_IN_SEL_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_PS_CTRL_IN_POL_MASK (0x20000U) #define GTM_gtm_cls0_CDTM0_DTM5_PS_CTRL_IN_POL_SHIFT (17U) #define GTM_gtm_cls0_CDTM0_DTM5_PS_CTRL_IN_POL_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_PS_CTRL_IN_POL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_PS_CTRL_IN_POL_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_PS_CTRL_IN_POL_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_PS_CTRL_TIM_SEL_MASK (0x40000U) #define GTM_gtm_cls0_CDTM0_DTM5_PS_CTRL_TIM_SEL_SHIFT (18U) #define GTM_gtm_cls0_CDTM0_DTM5_PS_CTRL_TIM_SEL_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_PS_CTRL_TIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_PS_CTRL_TIM_SEL_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_PS_CTRL_TIM_SEL_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_PS_CTRL_SHIFT_SEL_MASK (0x300000U) #define GTM_gtm_cls0_CDTM0_DTM5_PS_CTRL_SHIFT_SEL_SHIFT (20U) #define GTM_gtm_cls0_CDTM0_DTM5_PS_CTRL_SHIFT_SEL_WIDTH (2U) #define GTM_gtm_cls0_CDTM0_DTM5_PS_CTRL_SHIFT_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_PS_CTRL_SHIFT_SEL_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_PS_CTRL_SHIFT_SEL_MASK) /*! @} */ /*! @name CDTM0_DTM5_CH_DTV - CDTM[i]_DTM[d] channel [x] dead time reload values */ /*! @{ */ #define GTM_gtm_cls0_CDTM0_DTM5_CH_DTV_RELRISE_MASK (0x1FFFU) #define GTM_gtm_cls0_CDTM0_DTM5_CH_DTV_RELRISE_SHIFT (0U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_DTV_RELRISE_WIDTH (13U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_DTV_RELRISE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_DTV_RELRISE_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_DTV_RELRISE_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_DTV_RELFALL_MASK (0x1FFF0000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_DTV_RELFALL_SHIFT (16U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_DTV_RELFALL_WIDTH (13U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_DTV_RELFALL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_DTV_RELFALL_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_DTV_RELFALL_MASK) /*! @} */ /*! @name CDTM0_DTM5_CH_SR - CDTM[i]_DTM[d] channel shadow register */ /*! @{ */ #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL0_0_SR_SR_MASK (0x1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL0_0_SR_SR_SHIFT (0U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL0_0_SR_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL0_0_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL0_0_SR_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL0_0_SR_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL1_0_SR_SR_MASK (0x2U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL1_0_SR_SR_SHIFT (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL1_0_SR_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL1_0_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL1_0_SR_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL1_0_SR_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL0_1_SR_SR_MASK (0x4U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL0_1_SR_SR_SHIFT (2U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL0_1_SR_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL0_1_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL0_1_SR_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL0_1_SR_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL1_1_SR_SR_MASK (0x8U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL1_1_SR_SR_SHIFT (3U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL1_1_SR_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL1_1_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL1_1_SR_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL1_1_SR_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL0_2_SR_SR_MASK (0x10U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL0_2_SR_SR_SHIFT (4U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL0_2_SR_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL0_2_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL0_2_SR_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL0_2_SR_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL1_2_SR_SR_MASK (0x20U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL1_2_SR_SR_SHIFT (5U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL1_2_SR_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL1_2_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL1_2_SR_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL1_2_SR_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL0_3_SR_SR_MASK (0x40U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL0_3_SR_SR_SHIFT (6U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL0_3_SR_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL0_3_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL0_3_SR_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL0_3_SR_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL1_3_SR_SR_MASK (0x80U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL1_3_SR_SR_SHIFT (7U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL1_3_SR_SR_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL1_3_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL1_3_SR_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_SR_SL1_3_SR_SR_MASK) /*! @} */ /*! @name CDTM0_DTM5_CH_CTRL3 - CDTM[i]_DTM[d] channel control register 3 */ /*! @{ */ #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CII0_MASK (0x1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CII0_SHIFT (0U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CII0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CII0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CII0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CII0_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CIS0_MASK (0x2U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CIS0_SHIFT (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CIS0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CIS0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CIS0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CIS0_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL0_0_MASK (0x4U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL0_0_SHIFT (2U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL0_0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL0_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL0_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL0_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL1_0_MASK (0x8U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL1_0_SHIFT (3U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL1_0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL1_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL1_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CII1_MASK (0x100U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CII1_SHIFT (8U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CII1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CII1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CII1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CII1_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CIS1_MASK (0x200U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CIS1_SHIFT (9U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CIS1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CIS1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CIS1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CIS1_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL0_1_MASK (0x400U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL0_1_SHIFT (10U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL0_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL0_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL0_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL1_1_MASK (0x800U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL1_1_SHIFT (11U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL1_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL1_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL1_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL1_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CII2_MASK (0x10000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CII2_SHIFT (16U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CII2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CII2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CII2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CII2_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CIS2_MASK (0x20000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CIS2_SHIFT (17U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CIS2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CIS2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CIS2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CIS2_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL0_2_MASK (0x40000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL0_2_SHIFT (18U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL0_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL0_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL0_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL0_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL1_2_MASK (0x80000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL1_2_SHIFT (19U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL1_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL1_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL1_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL1_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CII3_MASK (0x1000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CII3_SHIFT (24U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CII3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CII3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CII3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CII3_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CIS3_MASK (0x2000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CIS3_SHIFT (25U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CIS3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CIS3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CIS3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_CIS3_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL0_3_MASK (0x4000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL0_3_SHIFT (26U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL0_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL0_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL0_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL0_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL1_3_MASK (0x8000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL1_3_SHIFT (27U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL1_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL1_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL1_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH_CTRL3_TSEL1_3_MASK) /*! @} */ /*! @name CDTM0_DTM5_CTRL2 - CDTM[i]_DTM[d] global configuration and control register 2 */ /*! @{ */ #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_SEL_0_MASK (0x7U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_SEL_0_SHIFT (0U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_SEL_0_WIDTH (3U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_SEL_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_SEL_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_SEL_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_POL_0_MASK (0x8U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_POL_0_SHIFT (3U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_POL_0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_POL_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_POL_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_POL_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_UPD_MODE_0_MASK (0x30U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_UPD_MODE_0_SHIFT (4U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_UPD_MODE_0_WIDTH (2U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_UPD_MODE_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CTRL2_UPD_MODE_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CTRL2_UPD_MODE_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUT_OFF_RST_0_MASK (0x40U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUT_OFF_RST_0_SHIFT (6U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUT_OFF_RST_0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUT_OFF_RST_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUT_OFF_RST_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUT_OFF_RST_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_WR_EN_0_MASK (0x80U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_WR_EN_0_SHIFT (7U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_WR_EN_0_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_WR_EN_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CTRL2_WR_EN_0_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CTRL2_WR_EN_0_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_SEL_1_MASK (0x700U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_SEL_1_SHIFT (8U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_SEL_1_WIDTH (3U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_SEL_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_SEL_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_SEL_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_POL_1_MASK (0x800U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_POL_1_SHIFT (11U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_POL_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_POL_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_POL_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_POL_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_UPD_MODE_1_MASK (0x3000U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_UPD_MODE_1_SHIFT (12U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_UPD_MODE_1_WIDTH (2U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_UPD_MODE_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CTRL2_UPD_MODE_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CTRL2_UPD_MODE_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUT_OFF_RST_1_MASK (0x4000U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUT_OFF_RST_1_SHIFT (14U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUT_OFF_RST_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUT_OFF_RST_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUT_OFF_RST_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUT_OFF_RST_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_WR_EN_1_MASK (0x8000U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_WR_EN_1_SHIFT (15U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_WR_EN_1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_WR_EN_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CTRL2_WR_EN_1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CTRL2_WR_EN_1_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_SEL_2_MASK (0x70000U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_SEL_2_SHIFT (16U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_SEL_2_WIDTH (3U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_SEL_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_SEL_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_SEL_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_POL_2_MASK (0x80000U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_POL_2_SHIFT (19U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_POL_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_POL_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_POL_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_POL_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_UPD_MODE_2_MASK (0x300000U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_UPD_MODE_2_SHIFT (20U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_UPD_MODE_2_WIDTH (2U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_UPD_MODE_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CTRL2_UPD_MODE_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CTRL2_UPD_MODE_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUT_OFF_RST_2_MASK (0x400000U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUT_OFF_RST_2_SHIFT (22U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUT_OFF_RST_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUT_OFF_RST_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUT_OFF_RST_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUT_OFF_RST_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_WR_EN_2_MASK (0x800000U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_WR_EN_2_SHIFT (23U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_WR_EN_2_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_WR_EN_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CTRL2_WR_EN_2_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CTRL2_WR_EN_2_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_SEL_3_MASK (0x7000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_SEL_3_SHIFT (24U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_SEL_3_WIDTH (3U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_SEL_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_SEL_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_SEL_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_POL_3_MASK (0x8000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_POL_3_SHIFT (27U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_POL_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_POL_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_POL_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUTOFF_POL_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_UPD_MODE_3_MASK (0x30000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_UPD_MODE_3_SHIFT (28U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_UPD_MODE_3_WIDTH (2U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_UPD_MODE_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CTRL2_UPD_MODE_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CTRL2_UPD_MODE_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUT_OFF_RST_3_MASK (0x40000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUT_OFF_RST_3_SHIFT (30U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUT_OFF_RST_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUT_OFF_RST_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUT_OFF_RST_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CTRL2_SHUT_OFF_RST_3_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_WR_EN_3_MASK (0x80000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_WR_EN_3_SHIFT (31U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_WR_EN_3_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CTRL2_WR_EN_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CTRL2_WR_EN_3_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CTRL2_WR_EN_3_MASK) /*! @} */ /*! @name CDTM0_DTM5_CH0_DTV_SR - CDTM[i]_DTM[d] channel [x] dead time shadow values */ /*! @{ */ #define GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELRISE_SR_MASK (0x1FFFU) #define GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELRISE_SR_SHIFT (0U) #define GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELRISE_SR_WIDTH (13U) #define GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELRISE_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELRISE_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELRISE_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELRISE_UPD_FE0RE1_MASK (0x4000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT (14U) #define GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELRISE_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELRISE_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELRISE_UPD_FE0RE1_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELRISE_UPD_EN_MASK (0x8000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELRISE_UPD_EN_SHIFT (15U) #define GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELRISE_UPD_EN_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELRISE_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELRISE_UPD_EN_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELRISE_UPD_EN_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELFALL_SR_MASK (0x1FFF0000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELFALL_SR_SHIFT (16U) #define GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELFALL_SR_WIDTH (13U) #define GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELFALL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELFALL_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELFALL_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELFALL_UPD_FE0RE1_MASK (0x40000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT (30U) #define GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELFALL_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELFALL_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELFALL_UPD_FE0RE1_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELFALL_UPD_EN_MASK (0x80000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELFALL_UPD_EN_SHIFT (31U) #define GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELFALL_UPD_EN_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELFALL_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELFALL_UPD_EN_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH0_DTV_SR_RELFALL_UPD_EN_MASK) /*! @} */ /*! @name CDTM0_DTM5_CH1_DTV_SR - CDTM[i]_DTM[d] channel [x] dead time shadow values */ /*! @{ */ #define GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELRISE_SR_MASK (0x1FFFU) #define GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELRISE_SR_SHIFT (0U) #define GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELRISE_SR_WIDTH (13U) #define GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELRISE_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELRISE_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELRISE_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELRISE_UPD_FE0RE1_MASK (0x4000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT (14U) #define GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELRISE_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELRISE_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELRISE_UPD_FE0RE1_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELRISE_UPD_EN_MASK (0x8000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELRISE_UPD_EN_SHIFT (15U) #define GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELRISE_UPD_EN_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELRISE_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELRISE_UPD_EN_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELRISE_UPD_EN_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELFALL_SR_MASK (0x1FFF0000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELFALL_SR_SHIFT (16U) #define GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELFALL_SR_WIDTH (13U) #define GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELFALL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELFALL_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELFALL_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELFALL_UPD_FE0RE1_MASK (0x40000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT (30U) #define GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELFALL_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELFALL_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELFALL_UPD_FE0RE1_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELFALL_UPD_EN_MASK (0x80000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELFALL_UPD_EN_SHIFT (31U) #define GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELFALL_UPD_EN_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELFALL_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELFALL_UPD_EN_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH1_DTV_SR_RELFALL_UPD_EN_MASK) /*! @} */ /*! @name CDTM0_DTM5_CH2_DTV_SR - CDTM[i]_DTM[d] channel [x] dead time shadow values */ /*! @{ */ #define GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELRISE_SR_MASK (0x1FFFU) #define GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELRISE_SR_SHIFT (0U) #define GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELRISE_SR_WIDTH (13U) #define GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELRISE_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELRISE_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELRISE_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELRISE_UPD_FE0RE1_MASK (0x4000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT (14U) #define GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELRISE_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELRISE_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELRISE_UPD_FE0RE1_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELRISE_UPD_EN_MASK (0x8000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELRISE_UPD_EN_SHIFT (15U) #define GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELRISE_UPD_EN_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELRISE_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELRISE_UPD_EN_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELRISE_UPD_EN_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELFALL_SR_MASK (0x1FFF0000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELFALL_SR_SHIFT (16U) #define GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELFALL_SR_WIDTH (13U) #define GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELFALL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELFALL_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELFALL_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELFALL_UPD_FE0RE1_MASK (0x40000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT (30U) #define GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELFALL_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELFALL_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELFALL_UPD_FE0RE1_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELFALL_UPD_EN_MASK (0x80000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELFALL_UPD_EN_SHIFT (31U) #define GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELFALL_UPD_EN_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELFALL_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELFALL_UPD_EN_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH2_DTV_SR_RELFALL_UPD_EN_MASK) /*! @} */ /*! @name CDTM0_DTM5_CH3_DTV_SR - CDTM[i]_DTM[d] channel [x] dead time shadow values */ /*! @{ */ #define GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELRISE_SR_MASK (0x1FFFU) #define GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELRISE_SR_SHIFT (0U) #define GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELRISE_SR_WIDTH (13U) #define GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELRISE_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELRISE_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELRISE_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELRISE_UPD_FE0RE1_MASK (0x4000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT (14U) #define GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELRISE_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELRISE_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELRISE_UPD_FE0RE1_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELRISE_UPD_EN_MASK (0x8000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELRISE_UPD_EN_SHIFT (15U) #define GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELRISE_UPD_EN_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELRISE_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELRISE_UPD_EN_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELRISE_UPD_EN_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELFALL_SR_MASK (0x1FFF0000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELFALL_SR_SHIFT (16U) #define GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELFALL_SR_WIDTH (13U) #define GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELFALL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELFALL_SR_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELFALL_SR_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELFALL_UPD_FE0RE1_MASK (0x40000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT (30U) #define GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELFALL_UPD_FE0RE1_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELFALL_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELFALL_UPD_FE0RE1_MASK) #define GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELFALL_UPD_EN_MASK (0x80000000U) #define GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELFALL_UPD_EN_SHIFT (31U) #define GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELFALL_UPD_EN_WIDTH (1U) #define GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELFALL_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELFALL_UPD_EN_SHIFT)) & GTM_gtm_cls0_CDTM0_DTM5_CH3_DTV_SR_RELFALL_UPD_EN_MASK) /*! @} */ /*! @name F2A0_CH0_ARU_RD_FIFO - F2A[i] stream [x] ARU read register */ /*! @{ */ #define GTM_gtm_cls0_F2A0_CH0_ARU_RD_FIFO_ADDR_MASK (0x1FFU) #define GTM_gtm_cls0_F2A0_CH0_ARU_RD_FIFO_ADDR_SHIFT (0U) #define GTM_gtm_cls0_F2A0_CH0_ARU_RD_FIFO_ADDR_WIDTH (9U) #define GTM_gtm_cls0_F2A0_CH0_ARU_RD_FIFO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_CH0_ARU_RD_FIFO_ADDR_SHIFT)) & GTM_gtm_cls0_F2A0_CH0_ARU_RD_FIFO_ADDR_MASK) /*! @} */ /*! @name F2A0_CH1_ARU_RD_FIFO - F2A[i] stream [x] ARU read register */ /*! @{ */ #define GTM_gtm_cls0_F2A0_CH1_ARU_RD_FIFO_ADDR_MASK (0x1FFU) #define GTM_gtm_cls0_F2A0_CH1_ARU_RD_FIFO_ADDR_SHIFT (0U) #define GTM_gtm_cls0_F2A0_CH1_ARU_RD_FIFO_ADDR_WIDTH (9U) #define GTM_gtm_cls0_F2A0_CH1_ARU_RD_FIFO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_CH1_ARU_RD_FIFO_ADDR_SHIFT)) & GTM_gtm_cls0_F2A0_CH1_ARU_RD_FIFO_ADDR_MASK) /*! @} */ /*! @name F2A0_CH2_ARU_RD_FIFO - F2A[i] stream [x] ARU read register */ /*! @{ */ #define GTM_gtm_cls0_F2A0_CH2_ARU_RD_FIFO_ADDR_MASK (0x1FFU) #define GTM_gtm_cls0_F2A0_CH2_ARU_RD_FIFO_ADDR_SHIFT (0U) #define GTM_gtm_cls0_F2A0_CH2_ARU_RD_FIFO_ADDR_WIDTH (9U) #define GTM_gtm_cls0_F2A0_CH2_ARU_RD_FIFO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_CH2_ARU_RD_FIFO_ADDR_SHIFT)) & GTM_gtm_cls0_F2A0_CH2_ARU_RD_FIFO_ADDR_MASK) /*! @} */ /*! @name F2A0_CH3_ARU_RD_FIFO - F2A[i] stream [x] ARU read register */ /*! @{ */ #define GTM_gtm_cls0_F2A0_CH3_ARU_RD_FIFO_ADDR_MASK (0x1FFU) #define GTM_gtm_cls0_F2A0_CH3_ARU_RD_FIFO_ADDR_SHIFT (0U) #define GTM_gtm_cls0_F2A0_CH3_ARU_RD_FIFO_ADDR_WIDTH (9U) #define GTM_gtm_cls0_F2A0_CH3_ARU_RD_FIFO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_CH3_ARU_RD_FIFO_ADDR_SHIFT)) & GTM_gtm_cls0_F2A0_CH3_ARU_RD_FIFO_ADDR_MASK) /*! @} */ /*! @name F2A0_CH4_ARU_RD_FIFO - F2A[i] stream [x] ARU read register */ /*! @{ */ #define GTM_gtm_cls0_F2A0_CH4_ARU_RD_FIFO_ADDR_MASK (0x1FFU) #define GTM_gtm_cls0_F2A0_CH4_ARU_RD_FIFO_ADDR_SHIFT (0U) #define GTM_gtm_cls0_F2A0_CH4_ARU_RD_FIFO_ADDR_WIDTH (9U) #define GTM_gtm_cls0_F2A0_CH4_ARU_RD_FIFO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_CH4_ARU_RD_FIFO_ADDR_SHIFT)) & GTM_gtm_cls0_F2A0_CH4_ARU_RD_FIFO_ADDR_MASK) /*! @} */ /*! @name F2A0_CH5_ARU_RD_FIFO - F2A[i] stream [x] ARU read register */ /*! @{ */ #define GTM_gtm_cls0_F2A0_CH5_ARU_RD_FIFO_ADDR_MASK (0x1FFU) #define GTM_gtm_cls0_F2A0_CH5_ARU_RD_FIFO_ADDR_SHIFT (0U) #define GTM_gtm_cls0_F2A0_CH5_ARU_RD_FIFO_ADDR_WIDTH (9U) #define GTM_gtm_cls0_F2A0_CH5_ARU_RD_FIFO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_CH5_ARU_RD_FIFO_ADDR_SHIFT)) & GTM_gtm_cls0_F2A0_CH5_ARU_RD_FIFO_ADDR_MASK) /*! @} */ /*! @name F2A0_CH6_ARU_RD_FIFO - F2A[i] stream [x] ARU read register */ /*! @{ */ #define GTM_gtm_cls0_F2A0_CH6_ARU_RD_FIFO_ADDR_MASK (0x1FFU) #define GTM_gtm_cls0_F2A0_CH6_ARU_RD_FIFO_ADDR_SHIFT (0U) #define GTM_gtm_cls0_F2A0_CH6_ARU_RD_FIFO_ADDR_WIDTH (9U) #define GTM_gtm_cls0_F2A0_CH6_ARU_RD_FIFO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_CH6_ARU_RD_FIFO_ADDR_SHIFT)) & GTM_gtm_cls0_F2A0_CH6_ARU_RD_FIFO_ADDR_MASK) /*! @} */ /*! @name F2A0_CH7_ARU_RD_FIFO - F2A[i] stream [x] ARU read register */ /*! @{ */ #define GTM_gtm_cls0_F2A0_CH7_ARU_RD_FIFO_ADDR_MASK (0x1FFU) #define GTM_gtm_cls0_F2A0_CH7_ARU_RD_FIFO_ADDR_SHIFT (0U) #define GTM_gtm_cls0_F2A0_CH7_ARU_RD_FIFO_ADDR_WIDTH (9U) #define GTM_gtm_cls0_F2A0_CH7_ARU_RD_FIFO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_CH7_ARU_RD_FIFO_ADDR_SHIFT)) & GTM_gtm_cls0_F2A0_CH7_ARU_RD_FIFO_ADDR_MASK) /*! @} */ /*! @name F2A0_CH0_STR_CFG - F2A[i] stream [x] configuration register */ /*! @{ */ #define GTM_gtm_cls0_F2A0_CH0_STR_CFG_TMODE_MASK (0x30000U) #define GTM_gtm_cls0_F2A0_CH0_STR_CFG_TMODE_SHIFT (16U) #define GTM_gtm_cls0_F2A0_CH0_STR_CFG_TMODE_WIDTH (2U) #define GTM_gtm_cls0_F2A0_CH0_STR_CFG_TMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_CH0_STR_CFG_TMODE_SHIFT)) & GTM_gtm_cls0_F2A0_CH0_STR_CFG_TMODE_MASK) #define GTM_gtm_cls0_F2A0_CH0_STR_CFG_DIR_MASK (0x40000U) #define GTM_gtm_cls0_F2A0_CH0_STR_CFG_DIR_SHIFT (18U) #define GTM_gtm_cls0_F2A0_CH0_STR_CFG_DIR_WIDTH (1U) #define GTM_gtm_cls0_F2A0_CH0_STR_CFG_DIR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_CH0_STR_CFG_DIR_SHIFT)) & GTM_gtm_cls0_F2A0_CH0_STR_CFG_DIR_MASK) /*! @} */ /*! @name F2A0_CH1_STR_CFG - F2A[i] stream [x] configuration register */ /*! @{ */ #define GTM_gtm_cls0_F2A0_CH1_STR_CFG_TMODE_MASK (0x30000U) #define GTM_gtm_cls0_F2A0_CH1_STR_CFG_TMODE_SHIFT (16U) #define GTM_gtm_cls0_F2A0_CH1_STR_CFG_TMODE_WIDTH (2U) #define GTM_gtm_cls0_F2A0_CH1_STR_CFG_TMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_CH1_STR_CFG_TMODE_SHIFT)) & GTM_gtm_cls0_F2A0_CH1_STR_CFG_TMODE_MASK) #define GTM_gtm_cls0_F2A0_CH1_STR_CFG_DIR_MASK (0x40000U) #define GTM_gtm_cls0_F2A0_CH1_STR_CFG_DIR_SHIFT (18U) #define GTM_gtm_cls0_F2A0_CH1_STR_CFG_DIR_WIDTH (1U) #define GTM_gtm_cls0_F2A0_CH1_STR_CFG_DIR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_CH1_STR_CFG_DIR_SHIFT)) & GTM_gtm_cls0_F2A0_CH1_STR_CFG_DIR_MASK) /*! @} */ /*! @name F2A0_CH2_STR_CFG - F2A[i] stream [x] configuration register */ /*! @{ */ #define GTM_gtm_cls0_F2A0_CH2_STR_CFG_TMODE_MASK (0x30000U) #define GTM_gtm_cls0_F2A0_CH2_STR_CFG_TMODE_SHIFT (16U) #define GTM_gtm_cls0_F2A0_CH2_STR_CFG_TMODE_WIDTH (2U) #define GTM_gtm_cls0_F2A0_CH2_STR_CFG_TMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_CH2_STR_CFG_TMODE_SHIFT)) & GTM_gtm_cls0_F2A0_CH2_STR_CFG_TMODE_MASK) #define GTM_gtm_cls0_F2A0_CH2_STR_CFG_DIR_MASK (0x40000U) #define GTM_gtm_cls0_F2A0_CH2_STR_CFG_DIR_SHIFT (18U) #define GTM_gtm_cls0_F2A0_CH2_STR_CFG_DIR_WIDTH (1U) #define GTM_gtm_cls0_F2A0_CH2_STR_CFG_DIR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_CH2_STR_CFG_DIR_SHIFT)) & GTM_gtm_cls0_F2A0_CH2_STR_CFG_DIR_MASK) /*! @} */ /*! @name F2A0_CH3_STR_CFG - F2A[i] stream [x] configuration register */ /*! @{ */ #define GTM_gtm_cls0_F2A0_CH3_STR_CFG_TMODE_MASK (0x30000U) #define GTM_gtm_cls0_F2A0_CH3_STR_CFG_TMODE_SHIFT (16U) #define GTM_gtm_cls0_F2A0_CH3_STR_CFG_TMODE_WIDTH (2U) #define GTM_gtm_cls0_F2A0_CH3_STR_CFG_TMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_CH3_STR_CFG_TMODE_SHIFT)) & GTM_gtm_cls0_F2A0_CH3_STR_CFG_TMODE_MASK) #define GTM_gtm_cls0_F2A0_CH3_STR_CFG_DIR_MASK (0x40000U) #define GTM_gtm_cls0_F2A0_CH3_STR_CFG_DIR_SHIFT (18U) #define GTM_gtm_cls0_F2A0_CH3_STR_CFG_DIR_WIDTH (1U) #define GTM_gtm_cls0_F2A0_CH3_STR_CFG_DIR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_CH3_STR_CFG_DIR_SHIFT)) & GTM_gtm_cls0_F2A0_CH3_STR_CFG_DIR_MASK) /*! @} */ /*! @name F2A0_CH4_STR_CFG - F2A[i] stream [x] configuration register */ /*! @{ */ #define GTM_gtm_cls0_F2A0_CH4_STR_CFG_TMODE_MASK (0x30000U) #define GTM_gtm_cls0_F2A0_CH4_STR_CFG_TMODE_SHIFT (16U) #define GTM_gtm_cls0_F2A0_CH4_STR_CFG_TMODE_WIDTH (2U) #define GTM_gtm_cls0_F2A0_CH4_STR_CFG_TMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_CH4_STR_CFG_TMODE_SHIFT)) & GTM_gtm_cls0_F2A0_CH4_STR_CFG_TMODE_MASK) #define GTM_gtm_cls0_F2A0_CH4_STR_CFG_DIR_MASK (0x40000U) #define GTM_gtm_cls0_F2A0_CH4_STR_CFG_DIR_SHIFT (18U) #define GTM_gtm_cls0_F2A0_CH4_STR_CFG_DIR_WIDTH (1U) #define GTM_gtm_cls0_F2A0_CH4_STR_CFG_DIR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_CH4_STR_CFG_DIR_SHIFT)) & GTM_gtm_cls0_F2A0_CH4_STR_CFG_DIR_MASK) /*! @} */ /*! @name F2A0_CH5_STR_CFG - F2A[i] stream [x] configuration register */ /*! @{ */ #define GTM_gtm_cls0_F2A0_CH5_STR_CFG_TMODE_MASK (0x30000U) #define GTM_gtm_cls0_F2A0_CH5_STR_CFG_TMODE_SHIFT (16U) #define GTM_gtm_cls0_F2A0_CH5_STR_CFG_TMODE_WIDTH (2U) #define GTM_gtm_cls0_F2A0_CH5_STR_CFG_TMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_CH5_STR_CFG_TMODE_SHIFT)) & GTM_gtm_cls0_F2A0_CH5_STR_CFG_TMODE_MASK) #define GTM_gtm_cls0_F2A0_CH5_STR_CFG_DIR_MASK (0x40000U) #define GTM_gtm_cls0_F2A0_CH5_STR_CFG_DIR_SHIFT (18U) #define GTM_gtm_cls0_F2A0_CH5_STR_CFG_DIR_WIDTH (1U) #define GTM_gtm_cls0_F2A0_CH5_STR_CFG_DIR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_CH5_STR_CFG_DIR_SHIFT)) & GTM_gtm_cls0_F2A0_CH5_STR_CFG_DIR_MASK) /*! @} */ /*! @name F2A0_CH6_STR_CFG - F2A[i] stream [x] configuration register */ /*! @{ */ #define GTM_gtm_cls0_F2A0_CH6_STR_CFG_TMODE_MASK (0x30000U) #define GTM_gtm_cls0_F2A0_CH6_STR_CFG_TMODE_SHIFT (16U) #define GTM_gtm_cls0_F2A0_CH6_STR_CFG_TMODE_WIDTH (2U) #define GTM_gtm_cls0_F2A0_CH6_STR_CFG_TMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_CH6_STR_CFG_TMODE_SHIFT)) & GTM_gtm_cls0_F2A0_CH6_STR_CFG_TMODE_MASK) #define GTM_gtm_cls0_F2A0_CH6_STR_CFG_DIR_MASK (0x40000U) #define GTM_gtm_cls0_F2A0_CH6_STR_CFG_DIR_SHIFT (18U) #define GTM_gtm_cls0_F2A0_CH6_STR_CFG_DIR_WIDTH (1U) #define GTM_gtm_cls0_F2A0_CH6_STR_CFG_DIR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_CH6_STR_CFG_DIR_SHIFT)) & GTM_gtm_cls0_F2A0_CH6_STR_CFG_DIR_MASK) /*! @} */ /*! @name F2A0_CH7_STR_CFG - F2A[i] stream [x] configuration register */ /*! @{ */ #define GTM_gtm_cls0_F2A0_CH7_STR_CFG_TMODE_MASK (0x30000U) #define GTM_gtm_cls0_F2A0_CH7_STR_CFG_TMODE_SHIFT (16U) #define GTM_gtm_cls0_F2A0_CH7_STR_CFG_TMODE_WIDTH (2U) #define GTM_gtm_cls0_F2A0_CH7_STR_CFG_TMODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_CH7_STR_CFG_TMODE_SHIFT)) & GTM_gtm_cls0_F2A0_CH7_STR_CFG_TMODE_MASK) #define GTM_gtm_cls0_F2A0_CH7_STR_CFG_DIR_MASK (0x40000U) #define GTM_gtm_cls0_F2A0_CH7_STR_CFG_DIR_SHIFT (18U) #define GTM_gtm_cls0_F2A0_CH7_STR_CFG_DIR_WIDTH (1U) #define GTM_gtm_cls0_F2A0_CH7_STR_CFG_DIR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_CH7_STR_CFG_DIR_SHIFT)) & GTM_gtm_cls0_F2A0_CH7_STR_CFG_DIR_MASK) /*! @} */ /*! @name F2A0_ENABLE - F2A[i] stream activation register */ /*! @{ */ #define GTM_gtm_cls0_F2A0_ENABLE_STR0_EN_MASK (0x3U) #define GTM_gtm_cls0_F2A0_ENABLE_STR0_EN_SHIFT (0U) #define GTM_gtm_cls0_F2A0_ENABLE_STR0_EN_WIDTH (2U) #define GTM_gtm_cls0_F2A0_ENABLE_STR0_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_ENABLE_STR0_EN_SHIFT)) & GTM_gtm_cls0_F2A0_ENABLE_STR0_EN_MASK) #define GTM_gtm_cls0_F2A0_ENABLE_STR1_EN_MASK (0xCU) #define GTM_gtm_cls0_F2A0_ENABLE_STR1_EN_SHIFT (2U) #define GTM_gtm_cls0_F2A0_ENABLE_STR1_EN_WIDTH (2U) #define GTM_gtm_cls0_F2A0_ENABLE_STR1_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_ENABLE_STR1_EN_SHIFT)) & GTM_gtm_cls0_F2A0_ENABLE_STR1_EN_MASK) #define GTM_gtm_cls0_F2A0_ENABLE_STR2_EN_MASK (0x30U) #define GTM_gtm_cls0_F2A0_ENABLE_STR2_EN_SHIFT (4U) #define GTM_gtm_cls0_F2A0_ENABLE_STR2_EN_WIDTH (2U) #define GTM_gtm_cls0_F2A0_ENABLE_STR2_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_ENABLE_STR2_EN_SHIFT)) & GTM_gtm_cls0_F2A0_ENABLE_STR2_EN_MASK) #define GTM_gtm_cls0_F2A0_ENABLE_STR3_EN_MASK (0xC0U) #define GTM_gtm_cls0_F2A0_ENABLE_STR3_EN_SHIFT (6U) #define GTM_gtm_cls0_F2A0_ENABLE_STR3_EN_WIDTH (2U) #define GTM_gtm_cls0_F2A0_ENABLE_STR3_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_ENABLE_STR3_EN_SHIFT)) & GTM_gtm_cls0_F2A0_ENABLE_STR3_EN_MASK) #define GTM_gtm_cls0_F2A0_ENABLE_STR4_EN_MASK (0x300U) #define GTM_gtm_cls0_F2A0_ENABLE_STR4_EN_SHIFT (8U) #define GTM_gtm_cls0_F2A0_ENABLE_STR4_EN_WIDTH (2U) #define GTM_gtm_cls0_F2A0_ENABLE_STR4_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_ENABLE_STR4_EN_SHIFT)) & GTM_gtm_cls0_F2A0_ENABLE_STR4_EN_MASK) #define GTM_gtm_cls0_F2A0_ENABLE_STR5_EN_MASK (0xC00U) #define GTM_gtm_cls0_F2A0_ENABLE_STR5_EN_SHIFT (10U) #define GTM_gtm_cls0_F2A0_ENABLE_STR5_EN_WIDTH (2U) #define GTM_gtm_cls0_F2A0_ENABLE_STR5_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_ENABLE_STR5_EN_SHIFT)) & GTM_gtm_cls0_F2A0_ENABLE_STR5_EN_MASK) #define GTM_gtm_cls0_F2A0_ENABLE_STR6_EN_MASK (0x3000U) #define GTM_gtm_cls0_F2A0_ENABLE_STR6_EN_SHIFT (12U) #define GTM_gtm_cls0_F2A0_ENABLE_STR6_EN_WIDTH (2U) #define GTM_gtm_cls0_F2A0_ENABLE_STR6_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_ENABLE_STR6_EN_SHIFT)) & GTM_gtm_cls0_F2A0_ENABLE_STR6_EN_MASK) #define GTM_gtm_cls0_F2A0_ENABLE_STR7_EN_MASK (0xC000U) #define GTM_gtm_cls0_F2A0_ENABLE_STR7_EN_SHIFT (14U) #define GTM_gtm_cls0_F2A0_ENABLE_STR7_EN_WIDTH (2U) #define GTM_gtm_cls0_F2A0_ENABLE_STR7_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_ENABLE_STR7_EN_SHIFT)) & GTM_gtm_cls0_F2A0_ENABLE_STR7_EN_MASK) /*! @} */ /*! @name F2A0_CTRL - F2A[i] stream control register */ /*! @{ */ #define GTM_gtm_cls0_F2A0_CTRL_STR4_CONF_MASK (0x3U) #define GTM_gtm_cls0_F2A0_CTRL_STR4_CONF_SHIFT (0U) #define GTM_gtm_cls0_F2A0_CTRL_STR4_CONF_WIDTH (2U) #define GTM_gtm_cls0_F2A0_CTRL_STR4_CONF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_CTRL_STR4_CONF_SHIFT)) & GTM_gtm_cls0_F2A0_CTRL_STR4_CONF_MASK) #define GTM_gtm_cls0_F2A0_CTRL_STR5_CONF_MASK (0xCU) #define GTM_gtm_cls0_F2A0_CTRL_STR5_CONF_SHIFT (2U) #define GTM_gtm_cls0_F2A0_CTRL_STR5_CONF_WIDTH (2U) #define GTM_gtm_cls0_F2A0_CTRL_STR5_CONF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_CTRL_STR5_CONF_SHIFT)) & GTM_gtm_cls0_F2A0_CTRL_STR5_CONF_MASK) #define GTM_gtm_cls0_F2A0_CTRL_STR6_CONF_MASK (0x30U) #define GTM_gtm_cls0_F2A0_CTRL_STR6_CONF_SHIFT (4U) #define GTM_gtm_cls0_F2A0_CTRL_STR6_CONF_WIDTH (2U) #define GTM_gtm_cls0_F2A0_CTRL_STR6_CONF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_CTRL_STR6_CONF_SHIFT)) & GTM_gtm_cls0_F2A0_CTRL_STR6_CONF_MASK) #define GTM_gtm_cls0_F2A0_CTRL_STR7_CONF_MASK (0xC0U) #define GTM_gtm_cls0_F2A0_CTRL_STR7_CONF_SHIFT (6U) #define GTM_gtm_cls0_F2A0_CTRL_STR7_CONF_WIDTH (2U) #define GTM_gtm_cls0_F2A0_CTRL_STR7_CONF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_F2A0_CTRL_STR7_CONF_SHIFT)) & GTM_gtm_cls0_F2A0_CTRL_STR7_CONF_MASK) /*! @} */ /*! @name AFD0_CH0_BUF_ACC - AFD [i] FIFO [x] buffer access register */ /*! @{ */ #define GTM_gtm_cls0_AFD0_CH0_BUF_ACC_DATA_MASK (0x1FFFFFFFU) #define GTM_gtm_cls0_AFD0_CH0_BUF_ACC_DATA_SHIFT (0U) #define GTM_gtm_cls0_AFD0_CH0_BUF_ACC_DATA_WIDTH (29U) #define GTM_gtm_cls0_AFD0_CH0_BUF_ACC_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AFD0_CH0_BUF_ACC_DATA_SHIFT)) & GTM_gtm_cls0_AFD0_CH0_BUF_ACC_DATA_MASK) /*! @} */ /*! @name AFD0_CH1_BUF_ACC - AFD [i] FIFO [x] buffer access register */ /*! @{ */ #define GTM_gtm_cls0_AFD0_CH1_BUF_ACC_DATA_MASK (0x1FFFFFFFU) #define GTM_gtm_cls0_AFD0_CH1_BUF_ACC_DATA_SHIFT (0U) #define GTM_gtm_cls0_AFD0_CH1_BUF_ACC_DATA_WIDTH (29U) #define GTM_gtm_cls0_AFD0_CH1_BUF_ACC_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AFD0_CH1_BUF_ACC_DATA_SHIFT)) & GTM_gtm_cls0_AFD0_CH1_BUF_ACC_DATA_MASK) /*! @} */ /*! @name AFD0_CH2_BUF_ACC - AFD [i] FIFO [x] buffer access register */ /*! @{ */ #define GTM_gtm_cls0_AFD0_CH2_BUF_ACC_DATA_MASK (0x1FFFFFFFU) #define GTM_gtm_cls0_AFD0_CH2_BUF_ACC_DATA_SHIFT (0U) #define GTM_gtm_cls0_AFD0_CH2_BUF_ACC_DATA_WIDTH (29U) #define GTM_gtm_cls0_AFD0_CH2_BUF_ACC_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AFD0_CH2_BUF_ACC_DATA_SHIFT)) & GTM_gtm_cls0_AFD0_CH2_BUF_ACC_DATA_MASK) /*! @} */ /*! @name AFD0_CH3_BUF_ACC - AFD [i] FIFO [x] buffer access register */ /*! @{ */ #define GTM_gtm_cls0_AFD0_CH3_BUF_ACC_DATA_MASK (0x1FFFFFFFU) #define GTM_gtm_cls0_AFD0_CH3_BUF_ACC_DATA_SHIFT (0U) #define GTM_gtm_cls0_AFD0_CH3_BUF_ACC_DATA_WIDTH (29U) #define GTM_gtm_cls0_AFD0_CH3_BUF_ACC_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AFD0_CH3_BUF_ACC_DATA_SHIFT)) & GTM_gtm_cls0_AFD0_CH3_BUF_ACC_DATA_MASK) /*! @} */ /*! @name AFD0_CH4_BUF_ACC - AFD [i] FIFO [x] buffer access register */ /*! @{ */ #define GTM_gtm_cls0_AFD0_CH4_BUF_ACC_DATA_MASK (0x1FFFFFFFU) #define GTM_gtm_cls0_AFD0_CH4_BUF_ACC_DATA_SHIFT (0U) #define GTM_gtm_cls0_AFD0_CH4_BUF_ACC_DATA_WIDTH (29U) #define GTM_gtm_cls0_AFD0_CH4_BUF_ACC_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AFD0_CH4_BUF_ACC_DATA_SHIFT)) & GTM_gtm_cls0_AFD0_CH4_BUF_ACC_DATA_MASK) /*! @} */ /*! @name AFD0_CH5_BUF_ACC - AFD [i] FIFO [x] buffer access register */ /*! @{ */ #define GTM_gtm_cls0_AFD0_CH5_BUF_ACC_DATA_MASK (0x1FFFFFFFU) #define GTM_gtm_cls0_AFD0_CH5_BUF_ACC_DATA_SHIFT (0U) #define GTM_gtm_cls0_AFD0_CH5_BUF_ACC_DATA_WIDTH (29U) #define GTM_gtm_cls0_AFD0_CH5_BUF_ACC_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AFD0_CH5_BUF_ACC_DATA_SHIFT)) & GTM_gtm_cls0_AFD0_CH5_BUF_ACC_DATA_MASK) /*! @} */ /*! @name AFD0_CH6_BUF_ACC - AFD [i] FIFO [x] buffer access register */ /*! @{ */ #define GTM_gtm_cls0_AFD0_CH6_BUF_ACC_DATA_MASK (0x1FFFFFFFU) #define GTM_gtm_cls0_AFD0_CH6_BUF_ACC_DATA_SHIFT (0U) #define GTM_gtm_cls0_AFD0_CH6_BUF_ACC_DATA_WIDTH (29U) #define GTM_gtm_cls0_AFD0_CH6_BUF_ACC_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AFD0_CH6_BUF_ACC_DATA_SHIFT)) & GTM_gtm_cls0_AFD0_CH6_BUF_ACC_DATA_MASK) /*! @} */ /*! @name AFD0_CH7_BUF_ACC - AFD [i] FIFO [x] buffer access register */ /*! @{ */ #define GTM_gtm_cls0_AFD0_CH7_BUF_ACC_DATA_MASK (0x1FFFFFFFU) #define GTM_gtm_cls0_AFD0_CH7_BUF_ACC_DATA_SHIFT (0U) #define GTM_gtm_cls0_AFD0_CH7_BUF_ACC_DATA_WIDTH (29U) #define GTM_gtm_cls0_AFD0_CH7_BUF_ACC_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AFD0_CH7_BUF_ACC_DATA_SHIFT)) & GTM_gtm_cls0_AFD0_CH7_BUF_ACC_DATA_MASK) /*! @} */ /*! @name FIFO0_CH0_CTRL - FIFO[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH0_CTRL_RBM_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH0_CTRL_RBM_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH0_CTRL_RBM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH0_CTRL_RBM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_CTRL_RBM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_CTRL_RBM_MASK) #define GTM_gtm_cls0_FIFO0_CH0_CTRL_RAP_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH0_CTRL_RAP_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH0_CTRL_RAP_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH0_CTRL_RAP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_CTRL_RAP_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_CTRL_RAP_MASK) #define GTM_gtm_cls0_FIFO0_CH0_CTRL_FLUSH_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH0_CTRL_FLUSH_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH0_CTRL_FLUSH_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH0_CTRL_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_CTRL_FLUSH_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_CTRL_FLUSH_MASK) #define GTM_gtm_cls0_FIFO0_CH0_CTRL_WULOCK_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH0_CTRL_WULOCK_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH0_CTRL_WULOCK_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH0_CTRL_WULOCK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_CTRL_WULOCK_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_CTRL_WULOCK_MASK) /*! @} */ /*! @name FIFO0_CH0_END_ADDR - FIFO[i] channel [x] end address register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH0_END_ADDR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH0_END_ADDR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH0_END_ADDR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH0_END_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_END_ADDR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_END_ADDR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH0_START_ADDR - FIFO[i] channel [x] start address register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH0_START_ADDR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH0_START_ADDR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH0_START_ADDR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH0_START_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_START_ADDR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_START_ADDR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH0_UPPER_WM - FIFO[i] channel [x] upper watermark register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH0_UPPER_WM_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH0_UPPER_WM_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH0_UPPER_WM_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH0_UPPER_WM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_UPPER_WM_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_UPPER_WM_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH0_LOWER_WM - FIFO[i] channel [x] lower watermark register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH0_LOWER_WM_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH0_LOWER_WM_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH0_LOWER_WM_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH0_LOWER_WM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_LOWER_WM_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_LOWER_WM_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH0_STATUS - FIFO[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH0_STATUS_EMPTY_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH0_STATUS_EMPTY_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH0_STATUS_EMPTY_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH0_STATUS_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_STATUS_EMPTY_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_STATUS_EMPTY_MASK) #define GTM_gtm_cls0_FIFO0_CH0_STATUS_FULL_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH0_STATUS_FULL_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH0_STATUS_FULL_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH0_STATUS_FULL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_STATUS_FULL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_STATUS_FULL_MASK) #define GTM_gtm_cls0_FIFO0_CH0_STATUS_LOW_WM_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH0_STATUS_LOW_WM_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH0_STATUS_LOW_WM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH0_STATUS_LOW_WM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_STATUS_LOW_WM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_STATUS_LOW_WM_MASK) #define GTM_gtm_cls0_FIFO0_CH0_STATUS_UP_WM_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH0_STATUS_UP_WM_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH0_STATUS_UP_WM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH0_STATUS_UP_WM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_STATUS_UP_WM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_STATUS_UP_WM_MASK) /*! @} */ /*! @name FIFO0_CH0_FILL_LEVEL - FIFO[i] channel [x] fill level register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH0_FILL_LEVEL_LEVEL_MASK (0x7FFU) #define GTM_gtm_cls0_FIFO0_CH0_FILL_LEVEL_LEVEL_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH0_FILL_LEVEL_LEVEL_WIDTH (11U) #define GTM_gtm_cls0_FIFO0_CH0_FILL_LEVEL_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_FILL_LEVEL_LEVEL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_FILL_LEVEL_LEVEL_MASK) /*! @} */ /*! @name FIFO0_CH0_WR_PTR - FIFO[i] channel [x] write pointer register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH0_WR_PTR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH0_WR_PTR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH0_WR_PTR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH0_WR_PTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_WR_PTR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_WR_PTR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH0_RD_PTR - FIFO[i] channel [x] read pointer register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH0_RD_PTR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH0_RD_PTR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH0_RD_PTR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH0_RD_PTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_RD_PTR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_RD_PTR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH0_IRQ_NOTIFY - FIFO[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH0_IRQ_NOTIFY_FIFO_EMPTY_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_NOTIFY_FIFO_EMPTY_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_NOTIFY_FIFO_EMPTY_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_NOTIFY_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_IRQ_NOTIFY_FIFO_EMPTY_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_IRQ_NOTIFY_FIFO_EMPTY_MASK) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_NOTIFY_FIFO_FULL_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_NOTIFY_FIFO_FULL_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_NOTIFY_FIFO_FULL_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_NOTIFY_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_IRQ_NOTIFY_FIFO_FULL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_IRQ_NOTIFY_FIFO_FULL_MASK) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_NOTIFY_FIFO_LWM_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_NOTIFY_FIFO_LWM_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_NOTIFY_FIFO_LWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_NOTIFY_FIFO_LWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_IRQ_NOTIFY_FIFO_LWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_IRQ_NOTIFY_FIFO_LWM_MASK) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_NOTIFY_FIFO_UWM_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_NOTIFY_FIFO_UWM_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_NOTIFY_FIFO_UWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_NOTIFY_FIFO_UWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_IRQ_NOTIFY_FIFO_UWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_IRQ_NOTIFY_FIFO_UWM_MASK) /*! @} */ /*! @name FIFO0_CH0_IRQ_EN - FIFO[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH0_IRQ_EN_FIFO_EMPTY_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_EN_FIFO_EMPTY_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_EN_FIFO_EMPTY_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_EN_FIFO_EMPTY_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_IRQ_EN_FIFO_EMPTY_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_IRQ_EN_FIFO_EMPTY_IRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_EN_FIFO_FULL_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_EN_FIFO_FULL_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_EN_FIFO_FULL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_EN_FIFO_FULL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_IRQ_EN_FIFO_FULL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_IRQ_EN_FIFO_FULL_IRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_EN_FIFO_LWM_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_EN_FIFO_LWM_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_EN_FIFO_LWM_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_EN_FIFO_LWM_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_IRQ_EN_FIFO_LWM_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_IRQ_EN_FIFO_LWM_IRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_EN_FIFO_UWM_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_EN_FIFO_UWM_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_EN_FIFO_UWM_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_EN_FIFO_UWM_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_IRQ_EN_FIFO_UWM_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_IRQ_EN_FIFO_UWM_IRQ_EN_MASK) /*! @} */ /*! @name FIFO0_CH0_IRQ_FORCINT - FIFO[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH0_IRQ_FORCINT_TRG_FIFO_EMPTY_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_FORCINT_TRG_FIFO_EMPTY_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_FORCINT_TRG_FIFO_EMPTY_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_FORCINT_TRG_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_IRQ_FORCINT_TRG_FIFO_EMPTY_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_IRQ_FORCINT_TRG_FIFO_EMPTY_MASK) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_FORCINT_TRG_FIFO_FULL_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_FORCINT_TRG_FIFO_FULL_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_FORCINT_TRG_FIFO_FULL_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_FORCINT_TRG_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_IRQ_FORCINT_TRG_FIFO_FULL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_IRQ_FORCINT_TRG_FIFO_FULL_MASK) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_FORCINT_TRG_FIFO_LWM_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_FORCINT_TRG_FIFO_LWM_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_FORCINT_TRG_FIFO_LWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_FORCINT_TRG_FIFO_LWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_IRQ_FORCINT_TRG_FIFO_LWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_IRQ_FORCINT_TRG_FIFO_LWM_MASK) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_FORCINT_TRG_FIFO_UWM_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_FORCINT_TRG_FIFO_UWM_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_FORCINT_TRG_FIFO_UWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_FORCINT_TRG_FIFO_UWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_IRQ_FORCINT_TRG_FIFO_UWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_IRQ_FORCINT_TRG_FIFO_UWM_MASK) /*! @} */ /*! @name FIFO0_CH0_IRQ_MODE - FIFO[i] channel [x] interrupt mode control register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH0_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_IRQ_MODE_IRQ_MODE_MASK) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_MODE_DMA_HYSTERESIS_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_MODE_DMA_HYSTERESIS_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_MODE_DMA_HYSTERESIS_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_MODE_DMA_HYSTERESIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_IRQ_MODE_DMA_HYSTERESIS_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_IRQ_MODE_DMA_HYSTERESIS_MASK) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_MODE_DMA_HYST_DIR_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_MODE_DMA_HYST_DIR_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_MODE_DMA_HYST_DIR_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH0_IRQ_MODE_DMA_HYST_DIR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_IRQ_MODE_DMA_HYST_DIR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_IRQ_MODE_DMA_HYST_DIR_MASK) /*! @} */ /*! @name FIFO0_CH0_EIRQ_EN - FIFO[i] channel [x] error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH0_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH0_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH0_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH0_EIRQ_EN_FIFO_EMPTY_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH0_EIRQ_EN_FIFO_FULL_EIRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH0_EIRQ_EN_FIFO_FULL_EIRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH0_EIRQ_EN_FIFO_FULL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH0_EIRQ_EN_FIFO_FULL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_EIRQ_EN_FIFO_FULL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_EIRQ_EN_FIFO_FULL_EIRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH0_EIRQ_EN_FIFO_LWM_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH0_EIRQ_EN_FIFO_LWM_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH0_EIRQ_EN_FIFO_LWM_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH0_EIRQ_EN_FIFO_LWM_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_EIRQ_EN_FIFO_LWM_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_EIRQ_EN_FIFO_LWM_EIRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH0_EIRQ_EN_FIFO_UWM_EIRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH0_EIRQ_EN_FIFO_UWM_EIRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH0_EIRQ_EN_FIFO_UWM_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH0_EIRQ_EN_FIFO_UWM_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH0_EIRQ_EN_FIFO_UWM_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH0_EIRQ_EN_FIFO_UWM_EIRQ_EN_MASK) /*! @} */ /*! @name FIFO0_CH1_CTRL - FIFO[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH1_CTRL_RBM_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH1_CTRL_RBM_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH1_CTRL_RBM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH1_CTRL_RBM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_CTRL_RBM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_CTRL_RBM_MASK) #define GTM_gtm_cls0_FIFO0_CH1_CTRL_RAP_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH1_CTRL_RAP_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH1_CTRL_RAP_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH1_CTRL_RAP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_CTRL_RAP_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_CTRL_RAP_MASK) #define GTM_gtm_cls0_FIFO0_CH1_CTRL_FLUSH_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH1_CTRL_FLUSH_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH1_CTRL_FLUSH_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH1_CTRL_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_CTRL_FLUSH_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_CTRL_FLUSH_MASK) #define GTM_gtm_cls0_FIFO0_CH1_CTRL_WULOCK_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH1_CTRL_WULOCK_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH1_CTRL_WULOCK_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH1_CTRL_WULOCK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_CTRL_WULOCK_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_CTRL_WULOCK_MASK) /*! @} */ /*! @name FIFO0_CH1_END_ADDR - FIFO[i] channel [x] end address register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH1_END_ADDR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH1_END_ADDR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH1_END_ADDR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH1_END_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_END_ADDR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_END_ADDR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH1_START_ADDR - FIFO[i] channel [x] start address register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH1_START_ADDR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH1_START_ADDR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH1_START_ADDR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH1_START_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_START_ADDR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_START_ADDR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH1_UPPER_WM - FIFO[i] channel [x] upper watermark register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH1_UPPER_WM_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH1_UPPER_WM_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH1_UPPER_WM_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH1_UPPER_WM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_UPPER_WM_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_UPPER_WM_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH1_LOWER_WM - FIFO[i] channel [x] lower watermark register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH1_LOWER_WM_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH1_LOWER_WM_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH1_LOWER_WM_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH1_LOWER_WM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_LOWER_WM_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_LOWER_WM_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH1_STATUS - FIFO[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH1_STATUS_EMPTY_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH1_STATUS_EMPTY_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH1_STATUS_EMPTY_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH1_STATUS_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_STATUS_EMPTY_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_STATUS_EMPTY_MASK) #define GTM_gtm_cls0_FIFO0_CH1_STATUS_FULL_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH1_STATUS_FULL_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH1_STATUS_FULL_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH1_STATUS_FULL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_STATUS_FULL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_STATUS_FULL_MASK) #define GTM_gtm_cls0_FIFO0_CH1_STATUS_LOW_WM_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH1_STATUS_LOW_WM_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH1_STATUS_LOW_WM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH1_STATUS_LOW_WM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_STATUS_LOW_WM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_STATUS_LOW_WM_MASK) #define GTM_gtm_cls0_FIFO0_CH1_STATUS_UP_WM_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH1_STATUS_UP_WM_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH1_STATUS_UP_WM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH1_STATUS_UP_WM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_STATUS_UP_WM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_STATUS_UP_WM_MASK) /*! @} */ /*! @name FIFO0_CH1_FILL_LEVEL - FIFO[i] channel [x] fill level register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH1_FILL_LEVEL_LEVEL_MASK (0x7FFU) #define GTM_gtm_cls0_FIFO0_CH1_FILL_LEVEL_LEVEL_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH1_FILL_LEVEL_LEVEL_WIDTH (11U) #define GTM_gtm_cls0_FIFO0_CH1_FILL_LEVEL_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_FILL_LEVEL_LEVEL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_FILL_LEVEL_LEVEL_MASK) /*! @} */ /*! @name FIFO0_CH1_WR_PTR - FIFO[i] channel [x] write pointer register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH1_WR_PTR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH1_WR_PTR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH1_WR_PTR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH1_WR_PTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_WR_PTR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_WR_PTR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH1_RD_PTR - FIFO[i] channel [x] read pointer register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH1_RD_PTR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH1_RD_PTR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH1_RD_PTR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH1_RD_PTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_RD_PTR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_RD_PTR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH1_IRQ_NOTIFY - FIFO[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH1_IRQ_NOTIFY_FIFO_EMPTY_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_NOTIFY_FIFO_EMPTY_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_NOTIFY_FIFO_EMPTY_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_NOTIFY_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_IRQ_NOTIFY_FIFO_EMPTY_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_IRQ_NOTIFY_FIFO_EMPTY_MASK) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_NOTIFY_FIFO_FULL_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_NOTIFY_FIFO_FULL_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_NOTIFY_FIFO_FULL_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_NOTIFY_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_IRQ_NOTIFY_FIFO_FULL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_IRQ_NOTIFY_FIFO_FULL_MASK) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_NOTIFY_FIFO_LWM_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_NOTIFY_FIFO_LWM_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_NOTIFY_FIFO_LWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_NOTIFY_FIFO_LWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_IRQ_NOTIFY_FIFO_LWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_IRQ_NOTIFY_FIFO_LWM_MASK) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_NOTIFY_FIFO_UWM_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_NOTIFY_FIFO_UWM_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_NOTIFY_FIFO_UWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_NOTIFY_FIFO_UWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_IRQ_NOTIFY_FIFO_UWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_IRQ_NOTIFY_FIFO_UWM_MASK) /*! @} */ /*! @name FIFO0_CH1_IRQ_EN - FIFO[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH1_IRQ_EN_FIFO_EMPTY_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_EN_FIFO_EMPTY_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_EN_FIFO_EMPTY_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_EN_FIFO_EMPTY_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_IRQ_EN_FIFO_EMPTY_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_IRQ_EN_FIFO_EMPTY_IRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_EN_FIFO_FULL_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_EN_FIFO_FULL_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_EN_FIFO_FULL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_EN_FIFO_FULL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_IRQ_EN_FIFO_FULL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_IRQ_EN_FIFO_FULL_IRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_EN_FIFO_LWM_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_EN_FIFO_LWM_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_EN_FIFO_LWM_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_EN_FIFO_LWM_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_IRQ_EN_FIFO_LWM_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_IRQ_EN_FIFO_LWM_IRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_EN_FIFO_UWM_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_EN_FIFO_UWM_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_EN_FIFO_UWM_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_EN_FIFO_UWM_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_IRQ_EN_FIFO_UWM_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_IRQ_EN_FIFO_UWM_IRQ_EN_MASK) /*! @} */ /*! @name FIFO0_CH1_IRQ_FORCINT - FIFO[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH1_IRQ_FORCINT_TRG_FIFO_EMPTY_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_FORCINT_TRG_FIFO_EMPTY_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_FORCINT_TRG_FIFO_EMPTY_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_FORCINT_TRG_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_IRQ_FORCINT_TRG_FIFO_EMPTY_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_IRQ_FORCINT_TRG_FIFO_EMPTY_MASK) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_FORCINT_TRG_FIFO_FULL_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_FORCINT_TRG_FIFO_FULL_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_FORCINT_TRG_FIFO_FULL_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_FORCINT_TRG_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_IRQ_FORCINT_TRG_FIFO_FULL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_IRQ_FORCINT_TRG_FIFO_FULL_MASK) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_FORCINT_TRG_FIFO_LWM_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_FORCINT_TRG_FIFO_LWM_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_FORCINT_TRG_FIFO_LWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_FORCINT_TRG_FIFO_LWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_IRQ_FORCINT_TRG_FIFO_LWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_IRQ_FORCINT_TRG_FIFO_LWM_MASK) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_FORCINT_TRG_FIFO_UWM_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_FORCINT_TRG_FIFO_UWM_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_FORCINT_TRG_FIFO_UWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_FORCINT_TRG_FIFO_UWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_IRQ_FORCINT_TRG_FIFO_UWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_IRQ_FORCINT_TRG_FIFO_UWM_MASK) /*! @} */ /*! @name FIFO0_CH1_IRQ_MODE - FIFO[i] channel [x] interrupt mode control register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH1_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_IRQ_MODE_IRQ_MODE_MASK) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_MODE_DMA_HYSTERESIS_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_MODE_DMA_HYSTERESIS_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_MODE_DMA_HYSTERESIS_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_MODE_DMA_HYSTERESIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_IRQ_MODE_DMA_HYSTERESIS_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_IRQ_MODE_DMA_HYSTERESIS_MASK) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_MODE_DMA_HYST_DIR_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_MODE_DMA_HYST_DIR_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_MODE_DMA_HYST_DIR_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH1_IRQ_MODE_DMA_HYST_DIR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_IRQ_MODE_DMA_HYST_DIR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_IRQ_MODE_DMA_HYST_DIR_MASK) /*! @} */ /*! @name FIFO0_CH1_EIRQ_EN - FIFO[i] channel [x] error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH1_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH1_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH1_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH1_EIRQ_EN_FIFO_EMPTY_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH1_EIRQ_EN_FIFO_FULL_EIRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH1_EIRQ_EN_FIFO_FULL_EIRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH1_EIRQ_EN_FIFO_FULL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH1_EIRQ_EN_FIFO_FULL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_EIRQ_EN_FIFO_FULL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_EIRQ_EN_FIFO_FULL_EIRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH1_EIRQ_EN_FIFO_LWM_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH1_EIRQ_EN_FIFO_LWM_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH1_EIRQ_EN_FIFO_LWM_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH1_EIRQ_EN_FIFO_LWM_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_EIRQ_EN_FIFO_LWM_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_EIRQ_EN_FIFO_LWM_EIRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH1_EIRQ_EN_FIFO_UWM_EIRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH1_EIRQ_EN_FIFO_UWM_EIRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH1_EIRQ_EN_FIFO_UWM_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH1_EIRQ_EN_FIFO_UWM_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH1_EIRQ_EN_FIFO_UWM_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH1_EIRQ_EN_FIFO_UWM_EIRQ_EN_MASK) /*! @} */ /*! @name FIFO0_CH2_CTRL - FIFO[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH2_CTRL_RBM_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH2_CTRL_RBM_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH2_CTRL_RBM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH2_CTRL_RBM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_CTRL_RBM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_CTRL_RBM_MASK) #define GTM_gtm_cls0_FIFO0_CH2_CTRL_RAP_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH2_CTRL_RAP_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH2_CTRL_RAP_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH2_CTRL_RAP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_CTRL_RAP_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_CTRL_RAP_MASK) #define GTM_gtm_cls0_FIFO0_CH2_CTRL_FLUSH_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH2_CTRL_FLUSH_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH2_CTRL_FLUSH_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH2_CTRL_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_CTRL_FLUSH_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_CTRL_FLUSH_MASK) #define GTM_gtm_cls0_FIFO0_CH2_CTRL_WULOCK_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH2_CTRL_WULOCK_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH2_CTRL_WULOCK_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH2_CTRL_WULOCK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_CTRL_WULOCK_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_CTRL_WULOCK_MASK) /*! @} */ /*! @name FIFO0_CH2_END_ADDR - FIFO[i] channel [x] end address register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH2_END_ADDR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH2_END_ADDR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH2_END_ADDR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH2_END_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_END_ADDR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_END_ADDR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH2_START_ADDR - FIFO[i] channel [x] start address register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH2_START_ADDR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH2_START_ADDR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH2_START_ADDR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH2_START_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_START_ADDR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_START_ADDR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH2_UPPER_WM - FIFO[i] channel [x] upper watermark register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH2_UPPER_WM_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH2_UPPER_WM_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH2_UPPER_WM_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH2_UPPER_WM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_UPPER_WM_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_UPPER_WM_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH2_LOWER_WM - FIFO[i] channel [x] lower watermark register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH2_LOWER_WM_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH2_LOWER_WM_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH2_LOWER_WM_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH2_LOWER_WM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_LOWER_WM_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_LOWER_WM_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH2_STATUS - FIFO[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH2_STATUS_EMPTY_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH2_STATUS_EMPTY_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH2_STATUS_EMPTY_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH2_STATUS_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_STATUS_EMPTY_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_STATUS_EMPTY_MASK) #define GTM_gtm_cls0_FIFO0_CH2_STATUS_FULL_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH2_STATUS_FULL_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH2_STATUS_FULL_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH2_STATUS_FULL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_STATUS_FULL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_STATUS_FULL_MASK) #define GTM_gtm_cls0_FIFO0_CH2_STATUS_LOW_WM_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH2_STATUS_LOW_WM_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH2_STATUS_LOW_WM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH2_STATUS_LOW_WM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_STATUS_LOW_WM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_STATUS_LOW_WM_MASK) #define GTM_gtm_cls0_FIFO0_CH2_STATUS_UP_WM_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH2_STATUS_UP_WM_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH2_STATUS_UP_WM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH2_STATUS_UP_WM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_STATUS_UP_WM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_STATUS_UP_WM_MASK) /*! @} */ /*! @name FIFO0_CH2_FILL_LEVEL - FIFO[i] channel [x] fill level register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH2_FILL_LEVEL_LEVEL_MASK (0x7FFU) #define GTM_gtm_cls0_FIFO0_CH2_FILL_LEVEL_LEVEL_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH2_FILL_LEVEL_LEVEL_WIDTH (11U) #define GTM_gtm_cls0_FIFO0_CH2_FILL_LEVEL_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_FILL_LEVEL_LEVEL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_FILL_LEVEL_LEVEL_MASK) /*! @} */ /*! @name FIFO0_CH2_WR_PTR - FIFO[i] channel [x] write pointer register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH2_WR_PTR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH2_WR_PTR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH2_WR_PTR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH2_WR_PTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_WR_PTR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_WR_PTR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH2_RD_PTR - FIFO[i] channel [x] read pointer register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH2_RD_PTR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH2_RD_PTR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH2_RD_PTR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH2_RD_PTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_RD_PTR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_RD_PTR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH2_IRQ_NOTIFY - FIFO[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH2_IRQ_NOTIFY_FIFO_EMPTY_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_NOTIFY_FIFO_EMPTY_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_NOTIFY_FIFO_EMPTY_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_NOTIFY_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_IRQ_NOTIFY_FIFO_EMPTY_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_IRQ_NOTIFY_FIFO_EMPTY_MASK) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_NOTIFY_FIFO_FULL_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_NOTIFY_FIFO_FULL_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_NOTIFY_FIFO_FULL_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_NOTIFY_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_IRQ_NOTIFY_FIFO_FULL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_IRQ_NOTIFY_FIFO_FULL_MASK) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_NOTIFY_FIFO_LWM_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_NOTIFY_FIFO_LWM_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_NOTIFY_FIFO_LWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_NOTIFY_FIFO_LWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_IRQ_NOTIFY_FIFO_LWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_IRQ_NOTIFY_FIFO_LWM_MASK) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_NOTIFY_FIFO_UWM_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_NOTIFY_FIFO_UWM_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_NOTIFY_FIFO_UWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_NOTIFY_FIFO_UWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_IRQ_NOTIFY_FIFO_UWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_IRQ_NOTIFY_FIFO_UWM_MASK) /*! @} */ /*! @name FIFO0_CH2_IRQ_EN - FIFO[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH2_IRQ_EN_FIFO_EMPTY_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_EN_FIFO_EMPTY_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_EN_FIFO_EMPTY_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_EN_FIFO_EMPTY_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_IRQ_EN_FIFO_EMPTY_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_IRQ_EN_FIFO_EMPTY_IRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_EN_FIFO_FULL_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_EN_FIFO_FULL_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_EN_FIFO_FULL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_EN_FIFO_FULL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_IRQ_EN_FIFO_FULL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_IRQ_EN_FIFO_FULL_IRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_EN_FIFO_LWM_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_EN_FIFO_LWM_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_EN_FIFO_LWM_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_EN_FIFO_LWM_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_IRQ_EN_FIFO_LWM_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_IRQ_EN_FIFO_LWM_IRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_EN_FIFO_UWM_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_EN_FIFO_UWM_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_EN_FIFO_UWM_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_EN_FIFO_UWM_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_IRQ_EN_FIFO_UWM_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_IRQ_EN_FIFO_UWM_IRQ_EN_MASK) /*! @} */ /*! @name FIFO0_CH2_IRQ_FORCINT - FIFO[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH2_IRQ_FORCINT_TRG_FIFO_EMPTY_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_FORCINT_TRG_FIFO_EMPTY_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_FORCINT_TRG_FIFO_EMPTY_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_FORCINT_TRG_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_IRQ_FORCINT_TRG_FIFO_EMPTY_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_IRQ_FORCINT_TRG_FIFO_EMPTY_MASK) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_FORCINT_TRG_FIFO_FULL_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_FORCINT_TRG_FIFO_FULL_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_FORCINT_TRG_FIFO_FULL_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_FORCINT_TRG_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_IRQ_FORCINT_TRG_FIFO_FULL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_IRQ_FORCINT_TRG_FIFO_FULL_MASK) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_FORCINT_TRG_FIFO_LWM_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_FORCINT_TRG_FIFO_LWM_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_FORCINT_TRG_FIFO_LWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_FORCINT_TRG_FIFO_LWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_IRQ_FORCINT_TRG_FIFO_LWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_IRQ_FORCINT_TRG_FIFO_LWM_MASK) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_FORCINT_TRG_FIFO_UWM_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_FORCINT_TRG_FIFO_UWM_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_FORCINT_TRG_FIFO_UWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_FORCINT_TRG_FIFO_UWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_IRQ_FORCINT_TRG_FIFO_UWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_IRQ_FORCINT_TRG_FIFO_UWM_MASK) /*! @} */ /*! @name FIFO0_CH2_IRQ_MODE - FIFO[i] channel [x] interrupt mode control register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH2_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_IRQ_MODE_IRQ_MODE_MASK) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_MODE_DMA_HYSTERESIS_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_MODE_DMA_HYSTERESIS_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_MODE_DMA_HYSTERESIS_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_MODE_DMA_HYSTERESIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_IRQ_MODE_DMA_HYSTERESIS_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_IRQ_MODE_DMA_HYSTERESIS_MASK) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_MODE_DMA_HYST_DIR_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_MODE_DMA_HYST_DIR_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_MODE_DMA_HYST_DIR_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH2_IRQ_MODE_DMA_HYST_DIR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_IRQ_MODE_DMA_HYST_DIR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_IRQ_MODE_DMA_HYST_DIR_MASK) /*! @} */ /*! @name FIFO0_CH2_EIRQ_EN - FIFO[i] channel [x] error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH2_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH2_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH2_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH2_EIRQ_EN_FIFO_EMPTY_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH2_EIRQ_EN_FIFO_FULL_EIRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH2_EIRQ_EN_FIFO_FULL_EIRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH2_EIRQ_EN_FIFO_FULL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH2_EIRQ_EN_FIFO_FULL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_EIRQ_EN_FIFO_FULL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_EIRQ_EN_FIFO_FULL_EIRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH2_EIRQ_EN_FIFO_LWM_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH2_EIRQ_EN_FIFO_LWM_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH2_EIRQ_EN_FIFO_LWM_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH2_EIRQ_EN_FIFO_LWM_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_EIRQ_EN_FIFO_LWM_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_EIRQ_EN_FIFO_LWM_EIRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH2_EIRQ_EN_FIFO_UWM_EIRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH2_EIRQ_EN_FIFO_UWM_EIRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH2_EIRQ_EN_FIFO_UWM_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH2_EIRQ_EN_FIFO_UWM_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH2_EIRQ_EN_FIFO_UWM_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH2_EIRQ_EN_FIFO_UWM_EIRQ_EN_MASK) /*! @} */ /*! @name FIFO0_CH3_CTRL - FIFO[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH3_CTRL_RBM_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH3_CTRL_RBM_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH3_CTRL_RBM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH3_CTRL_RBM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_CTRL_RBM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_CTRL_RBM_MASK) #define GTM_gtm_cls0_FIFO0_CH3_CTRL_RAP_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH3_CTRL_RAP_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH3_CTRL_RAP_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH3_CTRL_RAP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_CTRL_RAP_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_CTRL_RAP_MASK) #define GTM_gtm_cls0_FIFO0_CH3_CTRL_FLUSH_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH3_CTRL_FLUSH_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH3_CTRL_FLUSH_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH3_CTRL_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_CTRL_FLUSH_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_CTRL_FLUSH_MASK) #define GTM_gtm_cls0_FIFO0_CH3_CTRL_WULOCK_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH3_CTRL_WULOCK_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH3_CTRL_WULOCK_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH3_CTRL_WULOCK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_CTRL_WULOCK_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_CTRL_WULOCK_MASK) /*! @} */ /*! @name FIFO0_CH3_END_ADDR - FIFO[i] channel [x] end address register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH3_END_ADDR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH3_END_ADDR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH3_END_ADDR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH3_END_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_END_ADDR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_END_ADDR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH3_START_ADDR - FIFO[i] channel [x] start address register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH3_START_ADDR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH3_START_ADDR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH3_START_ADDR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH3_START_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_START_ADDR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_START_ADDR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH3_UPPER_WM - FIFO[i] channel [x] upper watermark register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH3_UPPER_WM_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH3_UPPER_WM_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH3_UPPER_WM_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH3_UPPER_WM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_UPPER_WM_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_UPPER_WM_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH3_LOWER_WM - FIFO[i] channel [x] lower watermark register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH3_LOWER_WM_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH3_LOWER_WM_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH3_LOWER_WM_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH3_LOWER_WM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_LOWER_WM_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_LOWER_WM_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH3_STATUS - FIFO[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH3_STATUS_EMPTY_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH3_STATUS_EMPTY_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH3_STATUS_EMPTY_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH3_STATUS_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_STATUS_EMPTY_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_STATUS_EMPTY_MASK) #define GTM_gtm_cls0_FIFO0_CH3_STATUS_FULL_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH3_STATUS_FULL_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH3_STATUS_FULL_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH3_STATUS_FULL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_STATUS_FULL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_STATUS_FULL_MASK) #define GTM_gtm_cls0_FIFO0_CH3_STATUS_LOW_WM_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH3_STATUS_LOW_WM_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH3_STATUS_LOW_WM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH3_STATUS_LOW_WM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_STATUS_LOW_WM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_STATUS_LOW_WM_MASK) #define GTM_gtm_cls0_FIFO0_CH3_STATUS_UP_WM_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH3_STATUS_UP_WM_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH3_STATUS_UP_WM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH3_STATUS_UP_WM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_STATUS_UP_WM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_STATUS_UP_WM_MASK) /*! @} */ /*! @name FIFO0_CH3_FILL_LEVEL - FIFO[i] channel [x] fill level register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH3_FILL_LEVEL_LEVEL_MASK (0x7FFU) #define GTM_gtm_cls0_FIFO0_CH3_FILL_LEVEL_LEVEL_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH3_FILL_LEVEL_LEVEL_WIDTH (11U) #define GTM_gtm_cls0_FIFO0_CH3_FILL_LEVEL_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_FILL_LEVEL_LEVEL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_FILL_LEVEL_LEVEL_MASK) /*! @} */ /*! @name FIFO0_CH3_WR_PTR - FIFO[i] channel [x] write pointer register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH3_WR_PTR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH3_WR_PTR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH3_WR_PTR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH3_WR_PTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_WR_PTR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_WR_PTR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH3_RD_PTR - FIFO[i] channel [x] read pointer register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH3_RD_PTR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH3_RD_PTR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH3_RD_PTR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH3_RD_PTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_RD_PTR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_RD_PTR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH3_IRQ_NOTIFY - FIFO[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH3_IRQ_NOTIFY_FIFO_EMPTY_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_NOTIFY_FIFO_EMPTY_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_NOTIFY_FIFO_EMPTY_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_NOTIFY_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_IRQ_NOTIFY_FIFO_EMPTY_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_IRQ_NOTIFY_FIFO_EMPTY_MASK) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_NOTIFY_FIFO_FULL_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_NOTIFY_FIFO_FULL_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_NOTIFY_FIFO_FULL_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_NOTIFY_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_IRQ_NOTIFY_FIFO_FULL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_IRQ_NOTIFY_FIFO_FULL_MASK) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_NOTIFY_FIFO_LWM_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_NOTIFY_FIFO_LWM_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_NOTIFY_FIFO_LWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_NOTIFY_FIFO_LWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_IRQ_NOTIFY_FIFO_LWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_IRQ_NOTIFY_FIFO_LWM_MASK) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_NOTIFY_FIFO_UWM_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_NOTIFY_FIFO_UWM_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_NOTIFY_FIFO_UWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_NOTIFY_FIFO_UWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_IRQ_NOTIFY_FIFO_UWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_IRQ_NOTIFY_FIFO_UWM_MASK) /*! @} */ /*! @name FIFO0_CH3_IRQ_EN - FIFO[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH3_IRQ_EN_FIFO_EMPTY_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_EN_FIFO_EMPTY_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_EN_FIFO_EMPTY_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_EN_FIFO_EMPTY_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_IRQ_EN_FIFO_EMPTY_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_IRQ_EN_FIFO_EMPTY_IRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_EN_FIFO_FULL_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_EN_FIFO_FULL_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_EN_FIFO_FULL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_EN_FIFO_FULL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_IRQ_EN_FIFO_FULL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_IRQ_EN_FIFO_FULL_IRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_EN_FIFO_LWM_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_EN_FIFO_LWM_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_EN_FIFO_LWM_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_EN_FIFO_LWM_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_IRQ_EN_FIFO_LWM_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_IRQ_EN_FIFO_LWM_IRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_EN_FIFO_UWM_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_EN_FIFO_UWM_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_EN_FIFO_UWM_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_EN_FIFO_UWM_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_IRQ_EN_FIFO_UWM_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_IRQ_EN_FIFO_UWM_IRQ_EN_MASK) /*! @} */ /*! @name FIFO0_CH3_IRQ_FORCINT - FIFO[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH3_IRQ_FORCINT_TRG_FIFO_EMPTY_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_FORCINT_TRG_FIFO_EMPTY_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_FORCINT_TRG_FIFO_EMPTY_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_FORCINT_TRG_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_IRQ_FORCINT_TRG_FIFO_EMPTY_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_IRQ_FORCINT_TRG_FIFO_EMPTY_MASK) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_FORCINT_TRG_FIFO_FULL_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_FORCINT_TRG_FIFO_FULL_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_FORCINT_TRG_FIFO_FULL_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_FORCINT_TRG_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_IRQ_FORCINT_TRG_FIFO_FULL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_IRQ_FORCINT_TRG_FIFO_FULL_MASK) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_FORCINT_TRG_FIFO_LWM_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_FORCINT_TRG_FIFO_LWM_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_FORCINT_TRG_FIFO_LWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_FORCINT_TRG_FIFO_LWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_IRQ_FORCINT_TRG_FIFO_LWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_IRQ_FORCINT_TRG_FIFO_LWM_MASK) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_FORCINT_TRG_FIFO_UWM_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_FORCINT_TRG_FIFO_UWM_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_FORCINT_TRG_FIFO_UWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_FORCINT_TRG_FIFO_UWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_IRQ_FORCINT_TRG_FIFO_UWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_IRQ_FORCINT_TRG_FIFO_UWM_MASK) /*! @} */ /*! @name FIFO0_CH3_IRQ_MODE - FIFO[i] channel [x] interrupt mode control register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH3_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_IRQ_MODE_IRQ_MODE_MASK) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_MODE_DMA_HYSTERESIS_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_MODE_DMA_HYSTERESIS_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_MODE_DMA_HYSTERESIS_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_MODE_DMA_HYSTERESIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_IRQ_MODE_DMA_HYSTERESIS_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_IRQ_MODE_DMA_HYSTERESIS_MASK) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_MODE_DMA_HYST_DIR_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_MODE_DMA_HYST_DIR_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_MODE_DMA_HYST_DIR_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH3_IRQ_MODE_DMA_HYST_DIR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_IRQ_MODE_DMA_HYST_DIR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_IRQ_MODE_DMA_HYST_DIR_MASK) /*! @} */ /*! @name FIFO0_CH3_EIRQ_EN - FIFO[i] channel [x] error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH3_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH3_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH3_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH3_EIRQ_EN_FIFO_EMPTY_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH3_EIRQ_EN_FIFO_FULL_EIRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH3_EIRQ_EN_FIFO_FULL_EIRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH3_EIRQ_EN_FIFO_FULL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH3_EIRQ_EN_FIFO_FULL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_EIRQ_EN_FIFO_FULL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_EIRQ_EN_FIFO_FULL_EIRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH3_EIRQ_EN_FIFO_LWM_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH3_EIRQ_EN_FIFO_LWM_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH3_EIRQ_EN_FIFO_LWM_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH3_EIRQ_EN_FIFO_LWM_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_EIRQ_EN_FIFO_LWM_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_EIRQ_EN_FIFO_LWM_EIRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH3_EIRQ_EN_FIFO_UWM_EIRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH3_EIRQ_EN_FIFO_UWM_EIRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH3_EIRQ_EN_FIFO_UWM_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH3_EIRQ_EN_FIFO_UWM_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH3_EIRQ_EN_FIFO_UWM_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH3_EIRQ_EN_FIFO_UWM_EIRQ_EN_MASK) /*! @} */ /*! @name FIFO0_CH4_CTRL - FIFO[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH4_CTRL_RBM_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH4_CTRL_RBM_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH4_CTRL_RBM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH4_CTRL_RBM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_CTRL_RBM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_CTRL_RBM_MASK) #define GTM_gtm_cls0_FIFO0_CH4_CTRL_RAP_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH4_CTRL_RAP_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH4_CTRL_RAP_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH4_CTRL_RAP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_CTRL_RAP_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_CTRL_RAP_MASK) #define GTM_gtm_cls0_FIFO0_CH4_CTRL_FLUSH_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH4_CTRL_FLUSH_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH4_CTRL_FLUSH_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH4_CTRL_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_CTRL_FLUSH_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_CTRL_FLUSH_MASK) #define GTM_gtm_cls0_FIFO0_CH4_CTRL_WULOCK_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH4_CTRL_WULOCK_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH4_CTRL_WULOCK_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH4_CTRL_WULOCK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_CTRL_WULOCK_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_CTRL_WULOCK_MASK) /*! @} */ /*! @name FIFO0_CH4_END_ADDR - FIFO[i] channel [x] end address register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH4_END_ADDR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH4_END_ADDR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH4_END_ADDR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH4_END_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_END_ADDR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_END_ADDR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH4_START_ADDR - FIFO[i] channel [x] start address register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH4_START_ADDR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH4_START_ADDR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH4_START_ADDR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH4_START_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_START_ADDR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_START_ADDR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH4_UPPER_WM - FIFO[i] channel [x] upper watermark register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH4_UPPER_WM_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH4_UPPER_WM_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH4_UPPER_WM_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH4_UPPER_WM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_UPPER_WM_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_UPPER_WM_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH4_LOWER_WM - FIFO[i] channel [x] lower watermark register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH4_LOWER_WM_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH4_LOWER_WM_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH4_LOWER_WM_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH4_LOWER_WM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_LOWER_WM_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_LOWER_WM_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH4_STATUS - FIFO[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH4_STATUS_EMPTY_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH4_STATUS_EMPTY_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH4_STATUS_EMPTY_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH4_STATUS_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_STATUS_EMPTY_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_STATUS_EMPTY_MASK) #define GTM_gtm_cls0_FIFO0_CH4_STATUS_FULL_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH4_STATUS_FULL_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH4_STATUS_FULL_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH4_STATUS_FULL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_STATUS_FULL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_STATUS_FULL_MASK) #define GTM_gtm_cls0_FIFO0_CH4_STATUS_LOW_WM_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH4_STATUS_LOW_WM_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH4_STATUS_LOW_WM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH4_STATUS_LOW_WM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_STATUS_LOW_WM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_STATUS_LOW_WM_MASK) #define GTM_gtm_cls0_FIFO0_CH4_STATUS_UP_WM_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH4_STATUS_UP_WM_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH4_STATUS_UP_WM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH4_STATUS_UP_WM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_STATUS_UP_WM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_STATUS_UP_WM_MASK) /*! @} */ /*! @name FIFO0_CH4_FILL_LEVEL - FIFO[i] channel [x] fill level register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH4_FILL_LEVEL_LEVEL_MASK (0x7FFU) #define GTM_gtm_cls0_FIFO0_CH4_FILL_LEVEL_LEVEL_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH4_FILL_LEVEL_LEVEL_WIDTH (11U) #define GTM_gtm_cls0_FIFO0_CH4_FILL_LEVEL_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_FILL_LEVEL_LEVEL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_FILL_LEVEL_LEVEL_MASK) /*! @} */ /*! @name FIFO0_CH4_WR_PTR - FIFO[i] channel [x] write pointer register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH4_WR_PTR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH4_WR_PTR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH4_WR_PTR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH4_WR_PTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_WR_PTR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_WR_PTR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH4_RD_PTR - FIFO[i] channel [x] read pointer register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH4_RD_PTR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH4_RD_PTR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH4_RD_PTR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH4_RD_PTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_RD_PTR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_RD_PTR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH4_IRQ_NOTIFY - FIFO[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH4_IRQ_NOTIFY_FIFO_EMPTY_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_NOTIFY_FIFO_EMPTY_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_NOTIFY_FIFO_EMPTY_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_NOTIFY_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_IRQ_NOTIFY_FIFO_EMPTY_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_IRQ_NOTIFY_FIFO_EMPTY_MASK) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_NOTIFY_FIFO_FULL_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_NOTIFY_FIFO_FULL_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_NOTIFY_FIFO_FULL_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_NOTIFY_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_IRQ_NOTIFY_FIFO_FULL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_IRQ_NOTIFY_FIFO_FULL_MASK) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_NOTIFY_FIFO_LWM_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_NOTIFY_FIFO_LWM_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_NOTIFY_FIFO_LWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_NOTIFY_FIFO_LWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_IRQ_NOTIFY_FIFO_LWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_IRQ_NOTIFY_FIFO_LWM_MASK) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_NOTIFY_FIFO_UWM_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_NOTIFY_FIFO_UWM_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_NOTIFY_FIFO_UWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_NOTIFY_FIFO_UWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_IRQ_NOTIFY_FIFO_UWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_IRQ_NOTIFY_FIFO_UWM_MASK) /*! @} */ /*! @name FIFO0_CH4_IRQ_EN - FIFO[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH4_IRQ_EN_FIFO_EMPTY_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_EN_FIFO_EMPTY_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_EN_FIFO_EMPTY_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_EN_FIFO_EMPTY_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_IRQ_EN_FIFO_EMPTY_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_IRQ_EN_FIFO_EMPTY_IRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_EN_FIFO_FULL_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_EN_FIFO_FULL_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_EN_FIFO_FULL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_EN_FIFO_FULL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_IRQ_EN_FIFO_FULL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_IRQ_EN_FIFO_FULL_IRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_EN_FIFO_LWM_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_EN_FIFO_LWM_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_EN_FIFO_LWM_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_EN_FIFO_LWM_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_IRQ_EN_FIFO_LWM_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_IRQ_EN_FIFO_LWM_IRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_EN_FIFO_UWM_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_EN_FIFO_UWM_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_EN_FIFO_UWM_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_EN_FIFO_UWM_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_IRQ_EN_FIFO_UWM_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_IRQ_EN_FIFO_UWM_IRQ_EN_MASK) /*! @} */ /*! @name FIFO0_CH4_IRQ_FORCINT - FIFO[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH4_IRQ_FORCINT_TRG_FIFO_EMPTY_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_FORCINT_TRG_FIFO_EMPTY_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_FORCINT_TRG_FIFO_EMPTY_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_FORCINT_TRG_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_IRQ_FORCINT_TRG_FIFO_EMPTY_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_IRQ_FORCINT_TRG_FIFO_EMPTY_MASK) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_FORCINT_TRG_FIFO_FULL_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_FORCINT_TRG_FIFO_FULL_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_FORCINT_TRG_FIFO_FULL_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_FORCINT_TRG_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_IRQ_FORCINT_TRG_FIFO_FULL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_IRQ_FORCINT_TRG_FIFO_FULL_MASK) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_FORCINT_TRG_FIFO_LWM_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_FORCINT_TRG_FIFO_LWM_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_FORCINT_TRG_FIFO_LWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_FORCINT_TRG_FIFO_LWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_IRQ_FORCINT_TRG_FIFO_LWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_IRQ_FORCINT_TRG_FIFO_LWM_MASK) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_FORCINT_TRG_FIFO_UWM_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_FORCINT_TRG_FIFO_UWM_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_FORCINT_TRG_FIFO_UWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_FORCINT_TRG_FIFO_UWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_IRQ_FORCINT_TRG_FIFO_UWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_IRQ_FORCINT_TRG_FIFO_UWM_MASK) /*! @} */ /*! @name FIFO0_CH4_IRQ_MODE - FIFO[i] channel [x] interrupt mode control register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH4_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_IRQ_MODE_IRQ_MODE_MASK) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_MODE_DMA_HYSTERESIS_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_MODE_DMA_HYSTERESIS_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_MODE_DMA_HYSTERESIS_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_MODE_DMA_HYSTERESIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_IRQ_MODE_DMA_HYSTERESIS_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_IRQ_MODE_DMA_HYSTERESIS_MASK) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_MODE_DMA_HYST_DIR_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_MODE_DMA_HYST_DIR_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_MODE_DMA_HYST_DIR_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH4_IRQ_MODE_DMA_HYST_DIR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_IRQ_MODE_DMA_HYST_DIR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_IRQ_MODE_DMA_HYST_DIR_MASK) /*! @} */ /*! @name FIFO0_CH4_EIRQ_EN - FIFO[i] channel [x] error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH4_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH4_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH4_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH4_EIRQ_EN_FIFO_EMPTY_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH4_EIRQ_EN_FIFO_FULL_EIRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH4_EIRQ_EN_FIFO_FULL_EIRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH4_EIRQ_EN_FIFO_FULL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH4_EIRQ_EN_FIFO_FULL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_EIRQ_EN_FIFO_FULL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_EIRQ_EN_FIFO_FULL_EIRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH4_EIRQ_EN_FIFO_LWM_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH4_EIRQ_EN_FIFO_LWM_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH4_EIRQ_EN_FIFO_LWM_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH4_EIRQ_EN_FIFO_LWM_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_EIRQ_EN_FIFO_LWM_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_EIRQ_EN_FIFO_LWM_EIRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH4_EIRQ_EN_FIFO_UWM_EIRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH4_EIRQ_EN_FIFO_UWM_EIRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH4_EIRQ_EN_FIFO_UWM_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH4_EIRQ_EN_FIFO_UWM_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH4_EIRQ_EN_FIFO_UWM_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH4_EIRQ_EN_FIFO_UWM_EIRQ_EN_MASK) /*! @} */ /*! @name FIFO0_CH5_CTRL - FIFO[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH5_CTRL_RBM_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH5_CTRL_RBM_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH5_CTRL_RBM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH5_CTRL_RBM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_CTRL_RBM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_CTRL_RBM_MASK) #define GTM_gtm_cls0_FIFO0_CH5_CTRL_RAP_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH5_CTRL_RAP_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH5_CTRL_RAP_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH5_CTRL_RAP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_CTRL_RAP_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_CTRL_RAP_MASK) #define GTM_gtm_cls0_FIFO0_CH5_CTRL_FLUSH_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH5_CTRL_FLUSH_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH5_CTRL_FLUSH_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH5_CTRL_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_CTRL_FLUSH_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_CTRL_FLUSH_MASK) #define GTM_gtm_cls0_FIFO0_CH5_CTRL_WULOCK_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH5_CTRL_WULOCK_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH5_CTRL_WULOCK_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH5_CTRL_WULOCK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_CTRL_WULOCK_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_CTRL_WULOCK_MASK) /*! @} */ /*! @name FIFO0_CH5_END_ADDR - FIFO[i] channel [x] end address register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH5_END_ADDR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH5_END_ADDR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH5_END_ADDR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH5_END_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_END_ADDR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_END_ADDR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH5_START_ADDR - FIFO[i] channel [x] start address register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH5_START_ADDR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH5_START_ADDR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH5_START_ADDR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH5_START_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_START_ADDR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_START_ADDR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH5_UPPER_WM - FIFO[i] channel [x] upper watermark register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH5_UPPER_WM_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH5_UPPER_WM_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH5_UPPER_WM_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH5_UPPER_WM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_UPPER_WM_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_UPPER_WM_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH5_LOWER_WM - FIFO[i] channel [x] lower watermark register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH5_LOWER_WM_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH5_LOWER_WM_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH5_LOWER_WM_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH5_LOWER_WM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_LOWER_WM_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_LOWER_WM_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH5_STATUS - FIFO[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH5_STATUS_EMPTY_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH5_STATUS_EMPTY_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH5_STATUS_EMPTY_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH5_STATUS_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_STATUS_EMPTY_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_STATUS_EMPTY_MASK) #define GTM_gtm_cls0_FIFO0_CH5_STATUS_FULL_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH5_STATUS_FULL_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH5_STATUS_FULL_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH5_STATUS_FULL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_STATUS_FULL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_STATUS_FULL_MASK) #define GTM_gtm_cls0_FIFO0_CH5_STATUS_LOW_WM_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH5_STATUS_LOW_WM_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH5_STATUS_LOW_WM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH5_STATUS_LOW_WM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_STATUS_LOW_WM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_STATUS_LOW_WM_MASK) #define GTM_gtm_cls0_FIFO0_CH5_STATUS_UP_WM_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH5_STATUS_UP_WM_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH5_STATUS_UP_WM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH5_STATUS_UP_WM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_STATUS_UP_WM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_STATUS_UP_WM_MASK) /*! @} */ /*! @name FIFO0_CH5_FILL_LEVEL - FIFO[i] channel [x] fill level register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH5_FILL_LEVEL_LEVEL_MASK (0x7FFU) #define GTM_gtm_cls0_FIFO0_CH5_FILL_LEVEL_LEVEL_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH5_FILL_LEVEL_LEVEL_WIDTH (11U) #define GTM_gtm_cls0_FIFO0_CH5_FILL_LEVEL_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_FILL_LEVEL_LEVEL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_FILL_LEVEL_LEVEL_MASK) /*! @} */ /*! @name FIFO0_CH5_WR_PTR - FIFO[i] channel [x] write pointer register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH5_WR_PTR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH5_WR_PTR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH5_WR_PTR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH5_WR_PTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_WR_PTR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_WR_PTR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH5_RD_PTR - FIFO[i] channel [x] read pointer register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH5_RD_PTR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH5_RD_PTR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH5_RD_PTR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH5_RD_PTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_RD_PTR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_RD_PTR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH5_IRQ_NOTIFY - FIFO[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH5_IRQ_NOTIFY_FIFO_EMPTY_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_NOTIFY_FIFO_EMPTY_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_NOTIFY_FIFO_EMPTY_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_NOTIFY_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_IRQ_NOTIFY_FIFO_EMPTY_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_IRQ_NOTIFY_FIFO_EMPTY_MASK) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_NOTIFY_FIFO_FULL_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_NOTIFY_FIFO_FULL_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_NOTIFY_FIFO_FULL_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_NOTIFY_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_IRQ_NOTIFY_FIFO_FULL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_IRQ_NOTIFY_FIFO_FULL_MASK) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_NOTIFY_FIFO_LWM_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_NOTIFY_FIFO_LWM_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_NOTIFY_FIFO_LWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_NOTIFY_FIFO_LWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_IRQ_NOTIFY_FIFO_LWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_IRQ_NOTIFY_FIFO_LWM_MASK) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_NOTIFY_FIFO_UWM_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_NOTIFY_FIFO_UWM_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_NOTIFY_FIFO_UWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_NOTIFY_FIFO_UWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_IRQ_NOTIFY_FIFO_UWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_IRQ_NOTIFY_FIFO_UWM_MASK) /*! @} */ /*! @name FIFO0_CH5_IRQ_EN - FIFO[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH5_IRQ_EN_FIFO_EMPTY_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_EN_FIFO_EMPTY_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_EN_FIFO_EMPTY_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_EN_FIFO_EMPTY_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_IRQ_EN_FIFO_EMPTY_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_IRQ_EN_FIFO_EMPTY_IRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_EN_FIFO_FULL_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_EN_FIFO_FULL_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_EN_FIFO_FULL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_EN_FIFO_FULL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_IRQ_EN_FIFO_FULL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_IRQ_EN_FIFO_FULL_IRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_EN_FIFO_LWM_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_EN_FIFO_LWM_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_EN_FIFO_LWM_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_EN_FIFO_LWM_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_IRQ_EN_FIFO_LWM_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_IRQ_EN_FIFO_LWM_IRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_EN_FIFO_UWM_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_EN_FIFO_UWM_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_EN_FIFO_UWM_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_EN_FIFO_UWM_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_IRQ_EN_FIFO_UWM_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_IRQ_EN_FIFO_UWM_IRQ_EN_MASK) /*! @} */ /*! @name FIFO0_CH5_IRQ_FORCINT - FIFO[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH5_IRQ_FORCINT_TRG_FIFO_EMPTY_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_FORCINT_TRG_FIFO_EMPTY_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_FORCINT_TRG_FIFO_EMPTY_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_FORCINT_TRG_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_IRQ_FORCINT_TRG_FIFO_EMPTY_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_IRQ_FORCINT_TRG_FIFO_EMPTY_MASK) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_FORCINT_TRG_FIFO_FULL_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_FORCINT_TRG_FIFO_FULL_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_FORCINT_TRG_FIFO_FULL_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_FORCINT_TRG_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_IRQ_FORCINT_TRG_FIFO_FULL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_IRQ_FORCINT_TRG_FIFO_FULL_MASK) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_FORCINT_TRG_FIFO_LWM_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_FORCINT_TRG_FIFO_LWM_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_FORCINT_TRG_FIFO_LWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_FORCINT_TRG_FIFO_LWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_IRQ_FORCINT_TRG_FIFO_LWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_IRQ_FORCINT_TRG_FIFO_LWM_MASK) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_FORCINT_TRG_FIFO_UWM_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_FORCINT_TRG_FIFO_UWM_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_FORCINT_TRG_FIFO_UWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_FORCINT_TRG_FIFO_UWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_IRQ_FORCINT_TRG_FIFO_UWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_IRQ_FORCINT_TRG_FIFO_UWM_MASK) /*! @} */ /*! @name FIFO0_CH5_IRQ_MODE - FIFO[i] channel [x] interrupt mode control register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH5_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_IRQ_MODE_IRQ_MODE_MASK) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_MODE_DMA_HYSTERESIS_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_MODE_DMA_HYSTERESIS_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_MODE_DMA_HYSTERESIS_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_MODE_DMA_HYSTERESIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_IRQ_MODE_DMA_HYSTERESIS_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_IRQ_MODE_DMA_HYSTERESIS_MASK) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_MODE_DMA_HYST_DIR_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_MODE_DMA_HYST_DIR_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_MODE_DMA_HYST_DIR_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH5_IRQ_MODE_DMA_HYST_DIR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_IRQ_MODE_DMA_HYST_DIR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_IRQ_MODE_DMA_HYST_DIR_MASK) /*! @} */ /*! @name FIFO0_CH5_EIRQ_EN - FIFO[i] channel [x] error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH5_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH5_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH5_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH5_EIRQ_EN_FIFO_EMPTY_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH5_EIRQ_EN_FIFO_FULL_EIRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH5_EIRQ_EN_FIFO_FULL_EIRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH5_EIRQ_EN_FIFO_FULL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH5_EIRQ_EN_FIFO_FULL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_EIRQ_EN_FIFO_FULL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_EIRQ_EN_FIFO_FULL_EIRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH5_EIRQ_EN_FIFO_LWM_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH5_EIRQ_EN_FIFO_LWM_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH5_EIRQ_EN_FIFO_LWM_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH5_EIRQ_EN_FIFO_LWM_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_EIRQ_EN_FIFO_LWM_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_EIRQ_EN_FIFO_LWM_EIRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH5_EIRQ_EN_FIFO_UWM_EIRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH5_EIRQ_EN_FIFO_UWM_EIRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH5_EIRQ_EN_FIFO_UWM_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH5_EIRQ_EN_FIFO_UWM_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH5_EIRQ_EN_FIFO_UWM_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH5_EIRQ_EN_FIFO_UWM_EIRQ_EN_MASK) /*! @} */ /*! @name FIFO0_CH6_CTRL - FIFO[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH6_CTRL_RBM_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH6_CTRL_RBM_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH6_CTRL_RBM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH6_CTRL_RBM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_CTRL_RBM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_CTRL_RBM_MASK) #define GTM_gtm_cls0_FIFO0_CH6_CTRL_RAP_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH6_CTRL_RAP_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH6_CTRL_RAP_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH6_CTRL_RAP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_CTRL_RAP_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_CTRL_RAP_MASK) #define GTM_gtm_cls0_FIFO0_CH6_CTRL_FLUSH_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH6_CTRL_FLUSH_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH6_CTRL_FLUSH_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH6_CTRL_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_CTRL_FLUSH_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_CTRL_FLUSH_MASK) #define GTM_gtm_cls0_FIFO0_CH6_CTRL_WULOCK_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH6_CTRL_WULOCK_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH6_CTRL_WULOCK_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH6_CTRL_WULOCK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_CTRL_WULOCK_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_CTRL_WULOCK_MASK) /*! @} */ /*! @name FIFO0_CH6_END_ADDR - FIFO[i] channel [x] end address register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH6_END_ADDR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH6_END_ADDR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH6_END_ADDR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH6_END_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_END_ADDR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_END_ADDR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH6_START_ADDR - FIFO[i] channel [x] start address register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH6_START_ADDR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH6_START_ADDR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH6_START_ADDR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH6_START_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_START_ADDR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_START_ADDR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH6_UPPER_WM - FIFO[i] channel [x] upper watermark register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH6_UPPER_WM_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH6_UPPER_WM_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH6_UPPER_WM_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH6_UPPER_WM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_UPPER_WM_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_UPPER_WM_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH6_LOWER_WM - FIFO[i] channel [x] lower watermark register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH6_LOWER_WM_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH6_LOWER_WM_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH6_LOWER_WM_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH6_LOWER_WM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_LOWER_WM_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_LOWER_WM_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH6_STATUS - FIFO[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH6_STATUS_EMPTY_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH6_STATUS_EMPTY_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH6_STATUS_EMPTY_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH6_STATUS_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_STATUS_EMPTY_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_STATUS_EMPTY_MASK) #define GTM_gtm_cls0_FIFO0_CH6_STATUS_FULL_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH6_STATUS_FULL_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH6_STATUS_FULL_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH6_STATUS_FULL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_STATUS_FULL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_STATUS_FULL_MASK) #define GTM_gtm_cls0_FIFO0_CH6_STATUS_LOW_WM_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH6_STATUS_LOW_WM_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH6_STATUS_LOW_WM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH6_STATUS_LOW_WM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_STATUS_LOW_WM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_STATUS_LOW_WM_MASK) #define GTM_gtm_cls0_FIFO0_CH6_STATUS_UP_WM_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH6_STATUS_UP_WM_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH6_STATUS_UP_WM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH6_STATUS_UP_WM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_STATUS_UP_WM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_STATUS_UP_WM_MASK) /*! @} */ /*! @name FIFO0_CH6_FILL_LEVEL - FIFO[i] channel [x] fill level register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH6_FILL_LEVEL_LEVEL_MASK (0x7FFU) #define GTM_gtm_cls0_FIFO0_CH6_FILL_LEVEL_LEVEL_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH6_FILL_LEVEL_LEVEL_WIDTH (11U) #define GTM_gtm_cls0_FIFO0_CH6_FILL_LEVEL_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_FILL_LEVEL_LEVEL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_FILL_LEVEL_LEVEL_MASK) /*! @} */ /*! @name FIFO0_CH6_WR_PTR - FIFO[i] channel [x] write pointer register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH6_WR_PTR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH6_WR_PTR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH6_WR_PTR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH6_WR_PTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_WR_PTR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_WR_PTR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH6_RD_PTR - FIFO[i] channel [x] read pointer register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH6_RD_PTR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH6_RD_PTR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH6_RD_PTR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH6_RD_PTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_RD_PTR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_RD_PTR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH6_IRQ_NOTIFY - FIFO[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH6_IRQ_NOTIFY_FIFO_EMPTY_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_NOTIFY_FIFO_EMPTY_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_NOTIFY_FIFO_EMPTY_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_NOTIFY_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_IRQ_NOTIFY_FIFO_EMPTY_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_IRQ_NOTIFY_FIFO_EMPTY_MASK) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_NOTIFY_FIFO_FULL_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_NOTIFY_FIFO_FULL_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_NOTIFY_FIFO_FULL_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_NOTIFY_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_IRQ_NOTIFY_FIFO_FULL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_IRQ_NOTIFY_FIFO_FULL_MASK) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_NOTIFY_FIFO_LWM_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_NOTIFY_FIFO_LWM_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_NOTIFY_FIFO_LWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_NOTIFY_FIFO_LWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_IRQ_NOTIFY_FIFO_LWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_IRQ_NOTIFY_FIFO_LWM_MASK) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_NOTIFY_FIFO_UWM_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_NOTIFY_FIFO_UWM_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_NOTIFY_FIFO_UWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_NOTIFY_FIFO_UWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_IRQ_NOTIFY_FIFO_UWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_IRQ_NOTIFY_FIFO_UWM_MASK) /*! @} */ /*! @name FIFO0_CH6_IRQ_EN - FIFO[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH6_IRQ_EN_FIFO_EMPTY_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_EN_FIFO_EMPTY_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_EN_FIFO_EMPTY_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_EN_FIFO_EMPTY_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_IRQ_EN_FIFO_EMPTY_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_IRQ_EN_FIFO_EMPTY_IRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_EN_FIFO_FULL_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_EN_FIFO_FULL_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_EN_FIFO_FULL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_EN_FIFO_FULL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_IRQ_EN_FIFO_FULL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_IRQ_EN_FIFO_FULL_IRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_EN_FIFO_LWM_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_EN_FIFO_LWM_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_EN_FIFO_LWM_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_EN_FIFO_LWM_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_IRQ_EN_FIFO_LWM_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_IRQ_EN_FIFO_LWM_IRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_EN_FIFO_UWM_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_EN_FIFO_UWM_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_EN_FIFO_UWM_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_EN_FIFO_UWM_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_IRQ_EN_FIFO_UWM_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_IRQ_EN_FIFO_UWM_IRQ_EN_MASK) /*! @} */ /*! @name FIFO0_CH6_IRQ_FORCINT - FIFO[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH6_IRQ_FORCINT_TRG_FIFO_EMPTY_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_FORCINT_TRG_FIFO_EMPTY_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_FORCINT_TRG_FIFO_EMPTY_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_FORCINT_TRG_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_IRQ_FORCINT_TRG_FIFO_EMPTY_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_IRQ_FORCINT_TRG_FIFO_EMPTY_MASK) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_FORCINT_TRG_FIFO_FULL_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_FORCINT_TRG_FIFO_FULL_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_FORCINT_TRG_FIFO_FULL_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_FORCINT_TRG_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_IRQ_FORCINT_TRG_FIFO_FULL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_IRQ_FORCINT_TRG_FIFO_FULL_MASK) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_FORCINT_TRG_FIFO_LWM_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_FORCINT_TRG_FIFO_LWM_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_FORCINT_TRG_FIFO_LWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_FORCINT_TRG_FIFO_LWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_IRQ_FORCINT_TRG_FIFO_LWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_IRQ_FORCINT_TRG_FIFO_LWM_MASK) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_FORCINT_TRG_FIFO_UWM_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_FORCINT_TRG_FIFO_UWM_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_FORCINT_TRG_FIFO_UWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_FORCINT_TRG_FIFO_UWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_IRQ_FORCINT_TRG_FIFO_UWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_IRQ_FORCINT_TRG_FIFO_UWM_MASK) /*! @} */ /*! @name FIFO0_CH6_IRQ_MODE - FIFO[i] channel [x] interrupt mode control register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH6_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_IRQ_MODE_IRQ_MODE_MASK) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_MODE_DMA_HYSTERESIS_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_MODE_DMA_HYSTERESIS_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_MODE_DMA_HYSTERESIS_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_MODE_DMA_HYSTERESIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_IRQ_MODE_DMA_HYSTERESIS_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_IRQ_MODE_DMA_HYSTERESIS_MASK) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_MODE_DMA_HYST_DIR_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_MODE_DMA_HYST_DIR_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_MODE_DMA_HYST_DIR_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH6_IRQ_MODE_DMA_HYST_DIR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_IRQ_MODE_DMA_HYST_DIR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_IRQ_MODE_DMA_HYST_DIR_MASK) /*! @} */ /*! @name FIFO0_CH6_EIRQ_EN - FIFO[i] channel [x] error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH6_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH6_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH6_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH6_EIRQ_EN_FIFO_EMPTY_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH6_EIRQ_EN_FIFO_FULL_EIRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH6_EIRQ_EN_FIFO_FULL_EIRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH6_EIRQ_EN_FIFO_FULL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH6_EIRQ_EN_FIFO_FULL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_EIRQ_EN_FIFO_FULL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_EIRQ_EN_FIFO_FULL_EIRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH6_EIRQ_EN_FIFO_LWM_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH6_EIRQ_EN_FIFO_LWM_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH6_EIRQ_EN_FIFO_LWM_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH6_EIRQ_EN_FIFO_LWM_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_EIRQ_EN_FIFO_LWM_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_EIRQ_EN_FIFO_LWM_EIRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH6_EIRQ_EN_FIFO_UWM_EIRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH6_EIRQ_EN_FIFO_UWM_EIRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH6_EIRQ_EN_FIFO_UWM_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH6_EIRQ_EN_FIFO_UWM_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH6_EIRQ_EN_FIFO_UWM_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH6_EIRQ_EN_FIFO_UWM_EIRQ_EN_MASK) /*! @} */ /*! @name FIFO0_CH7_CTRL - FIFO[i] channel [x] control register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH7_CTRL_RBM_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH7_CTRL_RBM_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH7_CTRL_RBM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH7_CTRL_RBM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_CTRL_RBM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_CTRL_RBM_MASK) #define GTM_gtm_cls0_FIFO0_CH7_CTRL_RAP_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH7_CTRL_RAP_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH7_CTRL_RAP_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH7_CTRL_RAP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_CTRL_RAP_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_CTRL_RAP_MASK) #define GTM_gtm_cls0_FIFO0_CH7_CTRL_FLUSH_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH7_CTRL_FLUSH_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH7_CTRL_FLUSH_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH7_CTRL_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_CTRL_FLUSH_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_CTRL_FLUSH_MASK) #define GTM_gtm_cls0_FIFO0_CH7_CTRL_WULOCK_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH7_CTRL_WULOCK_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH7_CTRL_WULOCK_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH7_CTRL_WULOCK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_CTRL_WULOCK_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_CTRL_WULOCK_MASK) /*! @} */ /*! @name FIFO0_CH7_END_ADDR - FIFO[i] channel [x] end address register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH7_END_ADDR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH7_END_ADDR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH7_END_ADDR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH7_END_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_END_ADDR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_END_ADDR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH7_START_ADDR - FIFO[i] channel [x] start address register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH7_START_ADDR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH7_START_ADDR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH7_START_ADDR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH7_START_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_START_ADDR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_START_ADDR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH7_UPPER_WM - FIFO[i] channel [x] upper watermark register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH7_UPPER_WM_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH7_UPPER_WM_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH7_UPPER_WM_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH7_UPPER_WM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_UPPER_WM_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_UPPER_WM_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH7_LOWER_WM - FIFO[i] channel [x] lower watermark register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH7_LOWER_WM_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH7_LOWER_WM_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH7_LOWER_WM_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH7_LOWER_WM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_LOWER_WM_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_LOWER_WM_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH7_STATUS - FIFO[i] channel [x] status register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH7_STATUS_EMPTY_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH7_STATUS_EMPTY_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH7_STATUS_EMPTY_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH7_STATUS_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_STATUS_EMPTY_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_STATUS_EMPTY_MASK) #define GTM_gtm_cls0_FIFO0_CH7_STATUS_FULL_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH7_STATUS_FULL_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH7_STATUS_FULL_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH7_STATUS_FULL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_STATUS_FULL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_STATUS_FULL_MASK) #define GTM_gtm_cls0_FIFO0_CH7_STATUS_LOW_WM_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH7_STATUS_LOW_WM_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH7_STATUS_LOW_WM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH7_STATUS_LOW_WM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_STATUS_LOW_WM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_STATUS_LOW_WM_MASK) #define GTM_gtm_cls0_FIFO0_CH7_STATUS_UP_WM_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH7_STATUS_UP_WM_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH7_STATUS_UP_WM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH7_STATUS_UP_WM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_STATUS_UP_WM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_STATUS_UP_WM_MASK) /*! @} */ /*! @name FIFO0_CH7_FILL_LEVEL - FIFO[i] channel [x] fill level register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH7_FILL_LEVEL_LEVEL_MASK (0x7FFU) #define GTM_gtm_cls0_FIFO0_CH7_FILL_LEVEL_LEVEL_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH7_FILL_LEVEL_LEVEL_WIDTH (11U) #define GTM_gtm_cls0_FIFO0_CH7_FILL_LEVEL_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_FILL_LEVEL_LEVEL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_FILL_LEVEL_LEVEL_MASK) /*! @} */ /*! @name FIFO0_CH7_WR_PTR - FIFO[i] channel [x] write pointer register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH7_WR_PTR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH7_WR_PTR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH7_WR_PTR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH7_WR_PTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_WR_PTR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_WR_PTR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH7_RD_PTR - FIFO[i] channel [x] read pointer register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH7_RD_PTR_ADDR_MASK (0x3FFU) #define GTM_gtm_cls0_FIFO0_CH7_RD_PTR_ADDR_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH7_RD_PTR_ADDR_WIDTH (10U) #define GTM_gtm_cls0_FIFO0_CH7_RD_PTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_RD_PTR_ADDR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_RD_PTR_ADDR_MASK) /*! @} */ /*! @name FIFO0_CH7_IRQ_NOTIFY - FIFO[i] channel [x] interrupt notification register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH7_IRQ_NOTIFY_FIFO_EMPTY_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_NOTIFY_FIFO_EMPTY_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_NOTIFY_FIFO_EMPTY_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_NOTIFY_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_IRQ_NOTIFY_FIFO_EMPTY_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_IRQ_NOTIFY_FIFO_EMPTY_MASK) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_NOTIFY_FIFO_FULL_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_NOTIFY_FIFO_FULL_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_NOTIFY_FIFO_FULL_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_NOTIFY_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_IRQ_NOTIFY_FIFO_FULL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_IRQ_NOTIFY_FIFO_FULL_MASK) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_NOTIFY_FIFO_LWM_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_NOTIFY_FIFO_LWM_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_NOTIFY_FIFO_LWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_NOTIFY_FIFO_LWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_IRQ_NOTIFY_FIFO_LWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_IRQ_NOTIFY_FIFO_LWM_MASK) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_NOTIFY_FIFO_UWM_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_NOTIFY_FIFO_UWM_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_NOTIFY_FIFO_UWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_NOTIFY_FIFO_UWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_IRQ_NOTIFY_FIFO_UWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_IRQ_NOTIFY_FIFO_UWM_MASK) /*! @} */ /*! @name FIFO0_CH7_IRQ_EN - FIFO[i] channel [x] interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH7_IRQ_EN_FIFO_EMPTY_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_EN_FIFO_EMPTY_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_EN_FIFO_EMPTY_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_EN_FIFO_EMPTY_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_IRQ_EN_FIFO_EMPTY_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_IRQ_EN_FIFO_EMPTY_IRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_EN_FIFO_FULL_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_EN_FIFO_FULL_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_EN_FIFO_FULL_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_EN_FIFO_FULL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_IRQ_EN_FIFO_FULL_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_IRQ_EN_FIFO_FULL_IRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_EN_FIFO_LWM_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_EN_FIFO_LWM_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_EN_FIFO_LWM_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_EN_FIFO_LWM_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_IRQ_EN_FIFO_LWM_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_IRQ_EN_FIFO_LWM_IRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_EN_FIFO_UWM_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_EN_FIFO_UWM_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_EN_FIFO_UWM_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_EN_FIFO_UWM_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_IRQ_EN_FIFO_UWM_IRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_IRQ_EN_FIFO_UWM_IRQ_EN_MASK) /*! @} */ /*! @name FIFO0_CH7_IRQ_FORCINT - FIFO[i] channel [x] force interrupt register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH7_IRQ_FORCINT_TRG_FIFO_EMPTY_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_FORCINT_TRG_FIFO_EMPTY_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_FORCINT_TRG_FIFO_EMPTY_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_FORCINT_TRG_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_IRQ_FORCINT_TRG_FIFO_EMPTY_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_IRQ_FORCINT_TRG_FIFO_EMPTY_MASK) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_FORCINT_TRG_FIFO_FULL_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_FORCINT_TRG_FIFO_FULL_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_FORCINT_TRG_FIFO_FULL_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_FORCINT_TRG_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_IRQ_FORCINT_TRG_FIFO_FULL_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_IRQ_FORCINT_TRG_FIFO_FULL_MASK) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_FORCINT_TRG_FIFO_LWM_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_FORCINT_TRG_FIFO_LWM_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_FORCINT_TRG_FIFO_LWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_FORCINT_TRG_FIFO_LWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_IRQ_FORCINT_TRG_FIFO_LWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_IRQ_FORCINT_TRG_FIFO_LWM_MASK) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_FORCINT_TRG_FIFO_UWM_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_FORCINT_TRG_FIFO_UWM_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_FORCINT_TRG_FIFO_UWM_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_FORCINT_TRG_FIFO_UWM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_IRQ_FORCINT_TRG_FIFO_UWM_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_IRQ_FORCINT_TRG_FIFO_UWM_MASK) /*! @} */ /*! @name FIFO0_CH7_IRQ_MODE - FIFO[i] channel [x] interrupt mode control register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH7_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_IRQ_MODE_IRQ_MODE_MASK) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_MODE_DMA_HYSTERESIS_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_MODE_DMA_HYSTERESIS_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_MODE_DMA_HYSTERESIS_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_MODE_DMA_HYSTERESIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_IRQ_MODE_DMA_HYSTERESIS_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_IRQ_MODE_DMA_HYSTERESIS_MASK) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_MODE_DMA_HYST_DIR_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_MODE_DMA_HYST_DIR_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_MODE_DMA_HYST_DIR_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH7_IRQ_MODE_DMA_HYST_DIR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_IRQ_MODE_DMA_HYST_DIR_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_IRQ_MODE_DMA_HYST_DIR_MASK) /*! @} */ /*! @name FIFO0_CH7_EIRQ_EN - FIFO[i] channel [x] error interrupt enable register */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_CH7_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_FIFO0_CH7_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_CH7_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH7_EIRQ_EN_FIFO_EMPTY_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_EIRQ_EN_FIFO_EMPTY_EIRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH7_EIRQ_EN_FIFO_FULL_EIRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_FIFO0_CH7_EIRQ_EN_FIFO_FULL_EIRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_FIFO0_CH7_EIRQ_EN_FIFO_FULL_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH7_EIRQ_EN_FIFO_FULL_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_EIRQ_EN_FIFO_FULL_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_EIRQ_EN_FIFO_FULL_EIRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH7_EIRQ_EN_FIFO_LWM_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_FIFO0_CH7_EIRQ_EN_FIFO_LWM_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_FIFO0_CH7_EIRQ_EN_FIFO_LWM_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH7_EIRQ_EN_FIFO_LWM_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_EIRQ_EN_FIFO_LWM_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_EIRQ_EN_FIFO_LWM_EIRQ_EN_MASK) #define GTM_gtm_cls0_FIFO0_CH7_EIRQ_EN_FIFO_UWM_EIRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_FIFO0_CH7_EIRQ_EN_FIFO_UWM_EIRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_FIFO0_CH7_EIRQ_EN_FIFO_UWM_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_FIFO0_CH7_EIRQ_EN_FIFO_UWM_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_CH7_EIRQ_EN_FIFO_UWM_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_FIFO0_CH7_EIRQ_EN_FIFO_UWM_EIRQ_EN_MASK) /*! @} */ /*! @name SPE0_CTRL_STAT - SPE[i] Control Status Register */ /*! @{ */ #define GTM_gtm_cls0_SPE0_CTRL_STAT_EN_MASK (0x1U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_EN_SHIFT (0U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_EN_WIDTH (1U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_CTRL_STAT_EN_SHIFT)) & GTM_gtm_cls0_SPE0_CTRL_STAT_EN_MASK) #define GTM_gtm_cls0_SPE0_CTRL_STAT_SIE0_MASK (0x2U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_SIE0_SHIFT (1U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_SIE0_WIDTH (1U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_SIE0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_CTRL_STAT_SIE0_SHIFT)) & GTM_gtm_cls0_SPE0_CTRL_STAT_SIE0_MASK) #define GTM_gtm_cls0_SPE0_CTRL_STAT_SIE1_MASK (0x4U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_SIE1_SHIFT (2U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_SIE1_WIDTH (1U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_SIE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_CTRL_STAT_SIE1_SHIFT)) & GTM_gtm_cls0_SPE0_CTRL_STAT_SIE1_MASK) #define GTM_gtm_cls0_SPE0_CTRL_STAT_SIE2_MASK (0x8U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_SIE2_SHIFT (3U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_SIE2_WIDTH (1U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_SIE2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_CTRL_STAT_SIE2_SHIFT)) & GTM_gtm_cls0_SPE0_CTRL_STAT_SIE2_MASK) #define GTM_gtm_cls0_SPE0_CTRL_STAT_TRIG_SEL_MASK (0x30U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_TRIG_SEL_SHIFT (4U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_TRIG_SEL_WIDTH (2U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_TRIG_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_CTRL_STAT_TRIG_SEL_SHIFT)) & GTM_gtm_cls0_SPE0_CTRL_STAT_TRIG_SEL_MASK) #define GTM_gtm_cls0_SPE0_CTRL_STAT_TIM_SEL_MASK (0x40U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_TIM_SEL_SHIFT (6U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_TIM_SEL_WIDTH (1U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_TIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_CTRL_STAT_TIM_SEL_SHIFT)) & GTM_gtm_cls0_SPE0_CTRL_STAT_TIM_SEL_MASK) #define GTM_gtm_cls0_SPE0_CTRL_STAT_FSOM_MASK (0x80U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_FSOM_SHIFT (7U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_FSOM_WIDTH (1U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_FSOM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_CTRL_STAT_FSOM_SHIFT)) & GTM_gtm_cls0_SPE0_CTRL_STAT_FSOM_MASK) #define GTM_gtm_cls0_SPE0_CTRL_STAT_SPE_PAT_PTR_MASK (0x700U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_SPE_PAT_PTR_SHIFT (8U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_SPE_PAT_PTR_WIDTH (3U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_SPE_PAT_PTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_CTRL_STAT_SPE_PAT_PTR_SHIFT)) & GTM_gtm_cls0_SPE0_CTRL_STAT_SPE_PAT_PTR_MASK) #define GTM_gtm_cls0_SPE0_CTRL_STAT_AIP_MASK (0x7000U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_AIP_SHIFT (12U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_AIP_WIDTH (3U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_AIP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_CTRL_STAT_AIP_SHIFT)) & GTM_gtm_cls0_SPE0_CTRL_STAT_AIP_MASK) #define GTM_gtm_cls0_SPE0_CTRL_STAT_ADIR_MASK (0x8000U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_ADIR_SHIFT (15U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_ADIR_WIDTH (1U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_ADIR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_CTRL_STAT_ADIR_SHIFT)) & GTM_gtm_cls0_SPE0_CTRL_STAT_ADIR_MASK) #define GTM_gtm_cls0_SPE0_CTRL_STAT_PIP_MASK (0x70000U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_PIP_SHIFT (16U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_PIP_WIDTH (3U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_PIP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_CTRL_STAT_PIP_SHIFT)) & GTM_gtm_cls0_SPE0_CTRL_STAT_PIP_MASK) #define GTM_gtm_cls0_SPE0_CTRL_STAT_PDIR_MASK (0x80000U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_PDIR_SHIFT (19U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_PDIR_WIDTH (1U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_PDIR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_CTRL_STAT_PDIR_SHIFT)) & GTM_gtm_cls0_SPE0_CTRL_STAT_PDIR_MASK) #define GTM_gtm_cls0_SPE0_CTRL_STAT_NIP_MASK (0x700000U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_NIP_SHIFT (20U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_NIP_WIDTH (3U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_NIP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_CTRL_STAT_NIP_SHIFT)) & GTM_gtm_cls0_SPE0_CTRL_STAT_NIP_MASK) #define GTM_gtm_cls0_SPE0_CTRL_STAT_ETRIG_SEL_MASK (0x800000U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_ETRIG_SEL_SHIFT (23U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_ETRIG_SEL_WIDTH (1U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_ETRIG_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_CTRL_STAT_ETRIG_SEL_SHIFT)) & GTM_gtm_cls0_SPE0_CTRL_STAT_ETRIG_SEL_MASK) #define GTM_gtm_cls0_SPE0_CTRL_STAT_FSOL_MASK (0xFF000000U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_FSOL_SHIFT (24U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_FSOL_WIDTH (8U) #define GTM_gtm_cls0_SPE0_CTRL_STAT_FSOL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_CTRL_STAT_FSOL_SHIFT)) & GTM_gtm_cls0_SPE0_CTRL_STAT_FSOL_MASK) /*! @} */ /*! @name SPE0_PAT - SPE[i] Input Pattern Definition Register */ /*! @{ */ #define GTM_gtm_cls0_SPE0_PAT_IP0_VAL_MASK (0x1U) #define GTM_gtm_cls0_SPE0_PAT_IP0_VAL_SHIFT (0U) #define GTM_gtm_cls0_SPE0_PAT_IP0_VAL_WIDTH (1U) #define GTM_gtm_cls0_SPE0_PAT_IP0_VAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_PAT_IP0_VAL_SHIFT)) & GTM_gtm_cls0_SPE0_PAT_IP0_VAL_MASK) #define GTM_gtm_cls0_SPE0_PAT_IP0_PAT_MASK (0xEU) #define GTM_gtm_cls0_SPE0_PAT_IP0_PAT_SHIFT (1U) #define GTM_gtm_cls0_SPE0_PAT_IP0_PAT_WIDTH (3U) #define GTM_gtm_cls0_SPE0_PAT_IP0_PAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_PAT_IP0_PAT_SHIFT)) & GTM_gtm_cls0_SPE0_PAT_IP0_PAT_MASK) #define GTM_gtm_cls0_SPE0_PAT_IP1_VAL_MASK (0x10U) #define GTM_gtm_cls0_SPE0_PAT_IP1_VAL_SHIFT (4U) #define GTM_gtm_cls0_SPE0_PAT_IP1_VAL_WIDTH (1U) #define GTM_gtm_cls0_SPE0_PAT_IP1_VAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_PAT_IP1_VAL_SHIFT)) & GTM_gtm_cls0_SPE0_PAT_IP1_VAL_MASK) #define GTM_gtm_cls0_SPE0_PAT_IP1_PAT_MASK (0xE0U) #define GTM_gtm_cls0_SPE0_PAT_IP1_PAT_SHIFT (5U) #define GTM_gtm_cls0_SPE0_PAT_IP1_PAT_WIDTH (3U) #define GTM_gtm_cls0_SPE0_PAT_IP1_PAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_PAT_IP1_PAT_SHIFT)) & GTM_gtm_cls0_SPE0_PAT_IP1_PAT_MASK) #define GTM_gtm_cls0_SPE0_PAT_IP2_VAL_MASK (0x100U) #define GTM_gtm_cls0_SPE0_PAT_IP2_VAL_SHIFT (8U) #define GTM_gtm_cls0_SPE0_PAT_IP2_VAL_WIDTH (1U) #define GTM_gtm_cls0_SPE0_PAT_IP2_VAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_PAT_IP2_VAL_SHIFT)) & GTM_gtm_cls0_SPE0_PAT_IP2_VAL_MASK) #define GTM_gtm_cls0_SPE0_PAT_IP2_PAT_MASK (0xE00U) #define GTM_gtm_cls0_SPE0_PAT_IP2_PAT_SHIFT (9U) #define GTM_gtm_cls0_SPE0_PAT_IP2_PAT_WIDTH (3U) #define GTM_gtm_cls0_SPE0_PAT_IP2_PAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_PAT_IP2_PAT_SHIFT)) & GTM_gtm_cls0_SPE0_PAT_IP2_PAT_MASK) #define GTM_gtm_cls0_SPE0_PAT_IP3_VAL_MASK (0x1000U) #define GTM_gtm_cls0_SPE0_PAT_IP3_VAL_SHIFT (12U) #define GTM_gtm_cls0_SPE0_PAT_IP3_VAL_WIDTH (1U) #define GTM_gtm_cls0_SPE0_PAT_IP3_VAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_PAT_IP3_VAL_SHIFT)) & GTM_gtm_cls0_SPE0_PAT_IP3_VAL_MASK) #define GTM_gtm_cls0_SPE0_PAT_IP3_PAT_MASK (0xE000U) #define GTM_gtm_cls0_SPE0_PAT_IP3_PAT_SHIFT (13U) #define GTM_gtm_cls0_SPE0_PAT_IP3_PAT_WIDTH (3U) #define GTM_gtm_cls0_SPE0_PAT_IP3_PAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_PAT_IP3_PAT_SHIFT)) & GTM_gtm_cls0_SPE0_PAT_IP3_PAT_MASK) #define GTM_gtm_cls0_SPE0_PAT_IP4_VAL_MASK (0x10000U) #define GTM_gtm_cls0_SPE0_PAT_IP4_VAL_SHIFT (16U) #define GTM_gtm_cls0_SPE0_PAT_IP4_VAL_WIDTH (1U) #define GTM_gtm_cls0_SPE0_PAT_IP4_VAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_PAT_IP4_VAL_SHIFT)) & GTM_gtm_cls0_SPE0_PAT_IP4_VAL_MASK) #define GTM_gtm_cls0_SPE0_PAT_IP4_PAT_MASK (0xE0000U) #define GTM_gtm_cls0_SPE0_PAT_IP4_PAT_SHIFT (17U) #define GTM_gtm_cls0_SPE0_PAT_IP4_PAT_WIDTH (3U) #define GTM_gtm_cls0_SPE0_PAT_IP4_PAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_PAT_IP4_PAT_SHIFT)) & GTM_gtm_cls0_SPE0_PAT_IP4_PAT_MASK) #define GTM_gtm_cls0_SPE0_PAT_IP5_VAL_MASK (0x100000U) #define GTM_gtm_cls0_SPE0_PAT_IP5_VAL_SHIFT (20U) #define GTM_gtm_cls0_SPE0_PAT_IP5_VAL_WIDTH (1U) #define GTM_gtm_cls0_SPE0_PAT_IP5_VAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_PAT_IP5_VAL_SHIFT)) & GTM_gtm_cls0_SPE0_PAT_IP5_VAL_MASK) #define GTM_gtm_cls0_SPE0_PAT_IP5_PAT_MASK (0xE00000U) #define GTM_gtm_cls0_SPE0_PAT_IP5_PAT_SHIFT (21U) #define GTM_gtm_cls0_SPE0_PAT_IP5_PAT_WIDTH (3U) #define GTM_gtm_cls0_SPE0_PAT_IP5_PAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_PAT_IP5_PAT_SHIFT)) & GTM_gtm_cls0_SPE0_PAT_IP5_PAT_MASK) #define GTM_gtm_cls0_SPE0_PAT_IP6_VAL_MASK (0x1000000U) #define GTM_gtm_cls0_SPE0_PAT_IP6_VAL_SHIFT (24U) #define GTM_gtm_cls0_SPE0_PAT_IP6_VAL_WIDTH (1U) #define GTM_gtm_cls0_SPE0_PAT_IP6_VAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_PAT_IP6_VAL_SHIFT)) & GTM_gtm_cls0_SPE0_PAT_IP6_VAL_MASK) #define GTM_gtm_cls0_SPE0_PAT_IP6_PAT_MASK (0xE000000U) #define GTM_gtm_cls0_SPE0_PAT_IP6_PAT_SHIFT (25U) #define GTM_gtm_cls0_SPE0_PAT_IP6_PAT_WIDTH (3U) #define GTM_gtm_cls0_SPE0_PAT_IP6_PAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_PAT_IP6_PAT_SHIFT)) & GTM_gtm_cls0_SPE0_PAT_IP6_PAT_MASK) #define GTM_gtm_cls0_SPE0_PAT_IP7_VAL_MASK (0x10000000U) #define GTM_gtm_cls0_SPE0_PAT_IP7_VAL_SHIFT (28U) #define GTM_gtm_cls0_SPE0_PAT_IP7_VAL_WIDTH (1U) #define GTM_gtm_cls0_SPE0_PAT_IP7_VAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_PAT_IP7_VAL_SHIFT)) & GTM_gtm_cls0_SPE0_PAT_IP7_VAL_MASK) #define GTM_gtm_cls0_SPE0_PAT_IP7_PAT_MASK (0xE0000000U) #define GTM_gtm_cls0_SPE0_PAT_IP7_PAT_SHIFT (29U) #define GTM_gtm_cls0_SPE0_PAT_IP7_PAT_WIDTH (3U) #define GTM_gtm_cls0_SPE0_PAT_IP7_PAT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_PAT_IP7_PAT_SHIFT)) & GTM_gtm_cls0_SPE0_PAT_IP7_PAT_MASK) /*! @} */ /*! @name SPE0_OUT_PAT0 - SPE[i] Output Definition Register */ /*! @{ */ #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT0_MASK (0x3U) #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT0_SHIFT (0U) #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT0_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT0_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT0_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT1_MASK (0xCU) #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT1_SHIFT (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT1_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT1_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT1_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT2_MASK (0x30U) #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT2_SHIFT (4U) #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT2_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT2_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT2_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT3_MASK (0xC0U) #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT3_SHIFT (6U) #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT3_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT3_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT3_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT4_MASK (0x300U) #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT4_SHIFT (8U) #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT4_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT4_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT4_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT5_MASK (0xC00U) #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT5_SHIFT (10U) #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT5_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT5_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT5_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT6_MASK (0x3000U) #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT6_SHIFT (12U) #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT6_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT6_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT6_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT7_MASK (0xC000U) #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT7_SHIFT (14U) #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT7_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT7_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT0_SPE_OUT_PAT7_MASK) /*! @} */ /*! @name SPE0_OUT_PAT1 - SPE[i] Output Definition Register */ /*! @{ */ #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT0_MASK (0x3U) #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT0_SHIFT (0U) #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT0_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT0_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT0_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT1_MASK (0xCU) #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT1_SHIFT (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT1_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT1_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT1_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT2_MASK (0x30U) #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT2_SHIFT (4U) #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT2_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT2_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT2_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT3_MASK (0xC0U) #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT3_SHIFT (6U) #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT3_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT3_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT3_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT4_MASK (0x300U) #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT4_SHIFT (8U) #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT4_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT4_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT4_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT5_MASK (0xC00U) #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT5_SHIFT (10U) #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT5_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT5_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT5_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT6_MASK (0x3000U) #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT6_SHIFT (12U) #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT6_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT6_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT6_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT7_MASK (0xC000U) #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT7_SHIFT (14U) #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT7_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT7_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT1_SPE_OUT_PAT7_MASK) /*! @} */ /*! @name SPE0_OUT_PAT2 - SPE[i] Output Definition Register */ /*! @{ */ #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT0_MASK (0x3U) #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT0_SHIFT (0U) #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT0_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT0_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT0_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT1_MASK (0xCU) #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT1_SHIFT (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT1_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT1_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT1_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT2_MASK (0x30U) #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT2_SHIFT (4U) #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT2_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT2_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT2_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT3_MASK (0xC0U) #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT3_SHIFT (6U) #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT3_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT3_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT3_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT4_MASK (0x300U) #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT4_SHIFT (8U) #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT4_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT4_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT4_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT5_MASK (0xC00U) #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT5_SHIFT (10U) #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT5_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT5_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT5_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT6_MASK (0x3000U) #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT6_SHIFT (12U) #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT6_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT6_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT6_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT7_MASK (0xC000U) #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT7_SHIFT (14U) #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT7_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT7_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT2_SPE_OUT_PAT7_MASK) /*! @} */ /*! @name SPE0_OUT_PAT3 - SPE[i] Output Definition Register */ /*! @{ */ #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT0_MASK (0x3U) #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT0_SHIFT (0U) #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT0_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT0_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT0_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT1_MASK (0xCU) #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT1_SHIFT (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT1_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT1_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT1_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT2_MASK (0x30U) #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT2_SHIFT (4U) #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT2_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT2_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT2_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT3_MASK (0xC0U) #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT3_SHIFT (6U) #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT3_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT3_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT3_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT4_MASK (0x300U) #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT4_SHIFT (8U) #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT4_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT4_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT4_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT5_MASK (0xC00U) #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT5_SHIFT (10U) #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT5_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT5_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT5_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT6_MASK (0x3000U) #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT6_SHIFT (12U) #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT6_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT6_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT6_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT7_MASK (0xC000U) #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT7_SHIFT (14U) #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT7_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT7_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT3_SPE_OUT_PAT7_MASK) /*! @} */ /*! @name SPE0_OUT_PAT4 - SPE[i] Output Definition Register */ /*! @{ */ #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT0_MASK (0x3U) #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT0_SHIFT (0U) #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT0_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT0_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT0_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT1_MASK (0xCU) #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT1_SHIFT (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT1_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT1_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT1_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT2_MASK (0x30U) #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT2_SHIFT (4U) #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT2_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT2_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT2_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT3_MASK (0xC0U) #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT3_SHIFT (6U) #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT3_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT3_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT3_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT4_MASK (0x300U) #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT4_SHIFT (8U) #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT4_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT4_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT4_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT5_MASK (0xC00U) #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT5_SHIFT (10U) #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT5_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT5_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT5_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT6_MASK (0x3000U) #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT6_SHIFT (12U) #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT6_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT6_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT6_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT7_MASK (0xC000U) #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT7_SHIFT (14U) #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT7_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT7_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT4_SPE_OUT_PAT7_MASK) /*! @} */ /*! @name SPE0_OUT_PAT5 - SPE[i] Output Definition Register */ /*! @{ */ #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT0_MASK (0x3U) #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT0_SHIFT (0U) #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT0_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT0_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT0_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT1_MASK (0xCU) #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT1_SHIFT (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT1_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT1_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT1_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT2_MASK (0x30U) #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT2_SHIFT (4U) #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT2_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT2_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT2_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT3_MASK (0xC0U) #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT3_SHIFT (6U) #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT3_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT3_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT3_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT4_MASK (0x300U) #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT4_SHIFT (8U) #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT4_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT4_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT4_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT5_MASK (0xC00U) #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT5_SHIFT (10U) #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT5_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT5_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT5_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT6_MASK (0x3000U) #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT6_SHIFT (12U) #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT6_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT6_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT6_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT7_MASK (0xC000U) #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT7_SHIFT (14U) #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT7_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT7_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT5_SPE_OUT_PAT7_MASK) /*! @} */ /*! @name SPE0_OUT_PAT6 - SPE[i] Output Definition Register */ /*! @{ */ #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT0_MASK (0x3U) #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT0_SHIFT (0U) #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT0_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT0_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT0_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT1_MASK (0xCU) #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT1_SHIFT (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT1_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT1_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT1_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT2_MASK (0x30U) #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT2_SHIFT (4U) #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT2_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT2_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT2_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT3_MASK (0xC0U) #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT3_SHIFT (6U) #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT3_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT3_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT3_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT4_MASK (0x300U) #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT4_SHIFT (8U) #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT4_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT4_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT4_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT5_MASK (0xC00U) #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT5_SHIFT (10U) #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT5_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT5_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT5_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT6_MASK (0x3000U) #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT6_SHIFT (12U) #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT6_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT6_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT6_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT7_MASK (0xC000U) #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT7_SHIFT (14U) #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT7_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT7_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT6_SPE_OUT_PAT7_MASK) /*! @} */ /*! @name SPE0_OUT_PAT7 - SPE[i] Output Definition Register */ /*! @{ */ #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT0_MASK (0x3U) #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT0_SHIFT (0U) #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT0_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT0_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT0_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT1_MASK (0xCU) #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT1_SHIFT (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT1_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT1_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT1_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT2_MASK (0x30U) #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT2_SHIFT (4U) #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT2_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT2_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT2_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT3_MASK (0xC0U) #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT3_SHIFT (6U) #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT3_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT3_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT3_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT4_MASK (0x300U) #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT4_SHIFT (8U) #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT4_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT4_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT4_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT5_MASK (0xC00U) #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT5_SHIFT (10U) #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT5_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT5_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT5_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT6_MASK (0x3000U) #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT6_SHIFT (12U) #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT6_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT6_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT6_MASK) #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT7_MASK (0xC000U) #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT7_SHIFT (14U) #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT7_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT7_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_PAT7_SPE_OUT_PAT7_MASK) /*! @} */ /*! @name SPE0_OUT_CTRL - SPE[i] Output Control Register */ /*! @{ */ #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL0_MASK (0x3U) #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL0_SHIFT (0U) #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL0_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL0_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL0_MASK) #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL1_MASK (0xCU) #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL1_SHIFT (2U) #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL1_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL1_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL1_MASK) #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL2_MASK (0x30U) #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL2_SHIFT (4U) #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL2_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL2_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL2_MASK) #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL3_MASK (0xC0U) #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL3_SHIFT (6U) #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL3_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL3_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL3_MASK) #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL4_MASK (0x300U) #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL4_SHIFT (8U) #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL4_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL4_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL4_MASK) #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL5_MASK (0xC00U) #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL5_SHIFT (10U) #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL5_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL5_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL5_MASK) #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL6_MASK (0x3000U) #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL6_SHIFT (12U) #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL6_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL6_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL6_MASK) #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL7_MASK (0xC000U) #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL7_SHIFT (14U) #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL7_WIDTH (2U) #define GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL7_SHIFT)) & GTM_gtm_cls0_SPE0_OUT_CTRL_SPE_OUT_CTRL7_MASK) /*! @} */ /*! @name SPE0_IRQ_NOTIFY - SPE[i] Interrupt Notification Register */ /*! @{ */ #define GTM_gtm_cls0_SPE0_IRQ_NOTIFY_SPE_NIPD_MASK (0x1U) #define GTM_gtm_cls0_SPE0_IRQ_NOTIFY_SPE_NIPD_SHIFT (0U) #define GTM_gtm_cls0_SPE0_IRQ_NOTIFY_SPE_NIPD_WIDTH (1U) #define GTM_gtm_cls0_SPE0_IRQ_NOTIFY_SPE_NIPD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_IRQ_NOTIFY_SPE_NIPD_SHIFT)) & GTM_gtm_cls0_SPE0_IRQ_NOTIFY_SPE_NIPD_MASK) #define GTM_gtm_cls0_SPE0_IRQ_NOTIFY_SPE_DCHG_MASK (0x2U) #define GTM_gtm_cls0_SPE0_IRQ_NOTIFY_SPE_DCHG_SHIFT (1U) #define GTM_gtm_cls0_SPE0_IRQ_NOTIFY_SPE_DCHG_WIDTH (1U) #define GTM_gtm_cls0_SPE0_IRQ_NOTIFY_SPE_DCHG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_IRQ_NOTIFY_SPE_DCHG_SHIFT)) & GTM_gtm_cls0_SPE0_IRQ_NOTIFY_SPE_DCHG_MASK) #define GTM_gtm_cls0_SPE0_IRQ_NOTIFY_SPE_PERR_MASK (0x4U) #define GTM_gtm_cls0_SPE0_IRQ_NOTIFY_SPE_PERR_SHIFT (2U) #define GTM_gtm_cls0_SPE0_IRQ_NOTIFY_SPE_PERR_WIDTH (1U) #define GTM_gtm_cls0_SPE0_IRQ_NOTIFY_SPE_PERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_IRQ_NOTIFY_SPE_PERR_SHIFT)) & GTM_gtm_cls0_SPE0_IRQ_NOTIFY_SPE_PERR_MASK) #define GTM_gtm_cls0_SPE0_IRQ_NOTIFY_SPE_BIS_MASK (0x8U) #define GTM_gtm_cls0_SPE0_IRQ_NOTIFY_SPE_BIS_SHIFT (3U) #define GTM_gtm_cls0_SPE0_IRQ_NOTIFY_SPE_BIS_WIDTH (1U) #define GTM_gtm_cls0_SPE0_IRQ_NOTIFY_SPE_BIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_IRQ_NOTIFY_SPE_BIS_SHIFT)) & GTM_gtm_cls0_SPE0_IRQ_NOTIFY_SPE_BIS_MASK) #define GTM_gtm_cls0_SPE0_IRQ_NOTIFY_SPE_RCMP_MASK (0x10U) #define GTM_gtm_cls0_SPE0_IRQ_NOTIFY_SPE_RCMP_SHIFT (4U) #define GTM_gtm_cls0_SPE0_IRQ_NOTIFY_SPE_RCMP_WIDTH (1U) #define GTM_gtm_cls0_SPE0_IRQ_NOTIFY_SPE_RCMP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_IRQ_NOTIFY_SPE_RCMP_SHIFT)) & GTM_gtm_cls0_SPE0_IRQ_NOTIFY_SPE_RCMP_MASK) /*! @} */ /*! @name SPE0_IRQ_EN - SPE[i] Interrupt Enable Register */ /*! @{ */ #define GTM_gtm_cls0_SPE0_IRQ_EN_SPE_NIPD_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_SPE0_IRQ_EN_SPE_NIPD_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_SPE0_IRQ_EN_SPE_NIPD_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_SPE0_IRQ_EN_SPE_NIPD_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_IRQ_EN_SPE_NIPD_IRQ_EN_SHIFT)) & GTM_gtm_cls0_SPE0_IRQ_EN_SPE_NIPD_IRQ_EN_MASK) #define GTM_gtm_cls0_SPE0_IRQ_EN_SPE_DCHG_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_SPE0_IRQ_EN_SPE_DCHG_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_SPE0_IRQ_EN_SPE_DCHG_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_SPE0_IRQ_EN_SPE_DCHG_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_IRQ_EN_SPE_DCHG_IRQ_EN_SHIFT)) & GTM_gtm_cls0_SPE0_IRQ_EN_SPE_DCHG_IRQ_EN_MASK) #define GTM_gtm_cls0_SPE0_IRQ_EN_SPE_PERR_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_SPE0_IRQ_EN_SPE_PERR_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_SPE0_IRQ_EN_SPE_PERR_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_SPE0_IRQ_EN_SPE_PERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_IRQ_EN_SPE_PERR_IRQ_EN_SHIFT)) & GTM_gtm_cls0_SPE0_IRQ_EN_SPE_PERR_IRQ_EN_MASK) #define GTM_gtm_cls0_SPE0_IRQ_EN_SPE_BIS_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_SPE0_IRQ_EN_SPE_BIS_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_SPE0_IRQ_EN_SPE_BIS_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_SPE0_IRQ_EN_SPE_BIS_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_IRQ_EN_SPE_BIS_IRQ_EN_SHIFT)) & GTM_gtm_cls0_SPE0_IRQ_EN_SPE_BIS_IRQ_EN_MASK) #define GTM_gtm_cls0_SPE0_IRQ_EN_SPE_RCMP_IRQ_EN_MASK (0x10U) #define GTM_gtm_cls0_SPE0_IRQ_EN_SPE_RCMP_IRQ_EN_SHIFT (4U) #define GTM_gtm_cls0_SPE0_IRQ_EN_SPE_RCMP_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_SPE0_IRQ_EN_SPE_RCMP_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_IRQ_EN_SPE_RCMP_IRQ_EN_SHIFT)) & GTM_gtm_cls0_SPE0_IRQ_EN_SPE_RCMP_IRQ_EN_MASK) /*! @} */ /*! @name SPE0_IRQ_FORCINT - SPE[i] Interrupt Generation By Software */ /*! @{ */ #define GTM_gtm_cls0_SPE0_IRQ_FORCINT_TRG_SPE_NIPD_MASK (0x1U) #define GTM_gtm_cls0_SPE0_IRQ_FORCINT_TRG_SPE_NIPD_SHIFT (0U) #define GTM_gtm_cls0_SPE0_IRQ_FORCINT_TRG_SPE_NIPD_WIDTH (1U) #define GTM_gtm_cls0_SPE0_IRQ_FORCINT_TRG_SPE_NIPD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_IRQ_FORCINT_TRG_SPE_NIPD_SHIFT)) & GTM_gtm_cls0_SPE0_IRQ_FORCINT_TRG_SPE_NIPD_MASK) #define GTM_gtm_cls0_SPE0_IRQ_FORCINT_TRG_SPE_DCHG_MASK (0x2U) #define GTM_gtm_cls0_SPE0_IRQ_FORCINT_TRG_SPE_DCHG_SHIFT (1U) #define GTM_gtm_cls0_SPE0_IRQ_FORCINT_TRG_SPE_DCHG_WIDTH (1U) #define GTM_gtm_cls0_SPE0_IRQ_FORCINT_TRG_SPE_DCHG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_IRQ_FORCINT_TRG_SPE_DCHG_SHIFT)) & GTM_gtm_cls0_SPE0_IRQ_FORCINT_TRG_SPE_DCHG_MASK) #define GTM_gtm_cls0_SPE0_IRQ_FORCINT_TRG_SPE_PERR_MASK (0x4U) #define GTM_gtm_cls0_SPE0_IRQ_FORCINT_TRG_SPE_PERR_SHIFT (2U) #define GTM_gtm_cls0_SPE0_IRQ_FORCINT_TRG_SPE_PERR_WIDTH (1U) #define GTM_gtm_cls0_SPE0_IRQ_FORCINT_TRG_SPE_PERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_IRQ_FORCINT_TRG_SPE_PERR_SHIFT)) & GTM_gtm_cls0_SPE0_IRQ_FORCINT_TRG_SPE_PERR_MASK) #define GTM_gtm_cls0_SPE0_IRQ_FORCINT_TRG_SPE_BIS_MASK (0x8U) #define GTM_gtm_cls0_SPE0_IRQ_FORCINT_TRG_SPE_BIS_SHIFT (3U) #define GTM_gtm_cls0_SPE0_IRQ_FORCINT_TRG_SPE_BIS_WIDTH (1U) #define GTM_gtm_cls0_SPE0_IRQ_FORCINT_TRG_SPE_BIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_IRQ_FORCINT_TRG_SPE_BIS_SHIFT)) & GTM_gtm_cls0_SPE0_IRQ_FORCINT_TRG_SPE_BIS_MASK) #define GTM_gtm_cls0_SPE0_IRQ_FORCINT_TRG_SPE_RCMP_MASK (0x10U) #define GTM_gtm_cls0_SPE0_IRQ_FORCINT_TRG_SPE_RCMP_SHIFT (4U) #define GTM_gtm_cls0_SPE0_IRQ_FORCINT_TRG_SPE_RCMP_WIDTH (1U) #define GTM_gtm_cls0_SPE0_IRQ_FORCINT_TRG_SPE_RCMP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_IRQ_FORCINT_TRG_SPE_RCMP_SHIFT)) & GTM_gtm_cls0_SPE0_IRQ_FORCINT_TRG_SPE_RCMP_MASK) /*! @} */ /*! @name SPE0_IRQ_MODE - SPE[i] Interrupt Mode Configuration Register */ /*! @{ */ #define GTM_gtm_cls0_SPE0_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_SPE0_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_SPE0_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_SPE0_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_SPE0_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name SPE0_EIRQ_EN - SPE[i] Error Interrupt Enable Register */ /*! @{ */ #define GTM_gtm_cls0_SPE0_EIRQ_EN_SPE_NIPD_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_SPE0_EIRQ_EN_SPE_NIPD_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_SPE0_EIRQ_EN_SPE_NIPD_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_SPE0_EIRQ_EN_SPE_NIPD_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_EIRQ_EN_SPE_NIPD_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_SPE0_EIRQ_EN_SPE_NIPD_EIRQ_EN_MASK) #define GTM_gtm_cls0_SPE0_EIRQ_EN_SPE_DCHG_EIRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_SPE0_EIRQ_EN_SPE_DCHG_EIRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_SPE0_EIRQ_EN_SPE_DCHG_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_SPE0_EIRQ_EN_SPE_DCHG_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_EIRQ_EN_SPE_DCHG_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_SPE0_EIRQ_EN_SPE_DCHG_EIRQ_EN_MASK) #define GTM_gtm_cls0_SPE0_EIRQ_EN_SPE_PERR_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_SPE0_EIRQ_EN_SPE_PERR_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_SPE0_EIRQ_EN_SPE_PERR_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_SPE0_EIRQ_EN_SPE_PERR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_EIRQ_EN_SPE_PERR_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_SPE0_EIRQ_EN_SPE_PERR_EIRQ_EN_MASK) #define GTM_gtm_cls0_SPE0_EIRQ_EN_SPE_BIS_EIRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_SPE0_EIRQ_EN_SPE_BIS_EIRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_SPE0_EIRQ_EN_SPE_BIS_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_SPE0_EIRQ_EN_SPE_BIS_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_EIRQ_EN_SPE_BIS_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_SPE0_EIRQ_EN_SPE_BIS_EIRQ_EN_MASK) #define GTM_gtm_cls0_SPE0_EIRQ_EN_SPE_RCMP_EIRQ_EN_MASK (0x10U) #define GTM_gtm_cls0_SPE0_EIRQ_EN_SPE_RCMP_EIRQ_EN_SHIFT (4U) #define GTM_gtm_cls0_SPE0_EIRQ_EN_SPE_RCMP_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_SPE0_EIRQ_EN_SPE_RCMP_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_EIRQ_EN_SPE_RCMP_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_SPE0_EIRQ_EN_SPE_RCMP_EIRQ_EN_MASK) /*! @} */ /*! @name SPE0_REV_CNT - SPE[i] Input Revolution Counter */ /*! @{ */ #define GTM_gtm_cls0_SPE0_REV_CNT_REV_CNT_MASK (0xFFFFFFU) #define GTM_gtm_cls0_SPE0_REV_CNT_REV_CNT_SHIFT (0U) #define GTM_gtm_cls0_SPE0_REV_CNT_REV_CNT_WIDTH (24U) #define GTM_gtm_cls0_SPE0_REV_CNT_REV_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_REV_CNT_REV_CNT_SHIFT)) & GTM_gtm_cls0_SPE0_REV_CNT_REV_CNT_MASK) /*! @} */ /*! @name SPE0_REV_CMP - SPE[i] Revolution Counter Compare Value */ /*! @{ */ #define GTM_gtm_cls0_SPE0_REV_CMP_REV_CMP_MASK (0xFFFFFFU) #define GTM_gtm_cls0_SPE0_REV_CMP_REV_CMP_SHIFT (0U) #define GTM_gtm_cls0_SPE0_REV_CMP_REV_CMP_WIDTH (24U) #define GTM_gtm_cls0_SPE0_REV_CMP_REV_CMP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_REV_CMP_REV_CMP_SHIFT)) & GTM_gtm_cls0_SPE0_REV_CMP_REV_CMP_MASK) /*! @} */ /*! @name SPE0_CTRL_STAT2 - SPE[i] Control Status Register 2 */ /*! @{ */ #define GTM_gtm_cls0_SPE0_CTRL_STAT2_SPE_PAT_PTR_BWD_MASK (0x700U) #define GTM_gtm_cls0_SPE0_CTRL_STAT2_SPE_PAT_PTR_BWD_SHIFT (8U) #define GTM_gtm_cls0_SPE0_CTRL_STAT2_SPE_PAT_PTR_BWD_WIDTH (3U) #define GTM_gtm_cls0_SPE0_CTRL_STAT2_SPE_PAT_PTR_BWD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_CTRL_STAT2_SPE_PAT_PTR_BWD_SHIFT)) & GTM_gtm_cls0_SPE0_CTRL_STAT2_SPE_PAT_PTR_BWD_MASK) /*! @} */ /*! @name SPE0_CMD - SPE[i] Command Register */ /*! @{ */ #define GTM_gtm_cls0_SPE0_CMD_SPE_CTRL_CMD_MASK (0x3U) #define GTM_gtm_cls0_SPE0_CMD_SPE_CTRL_CMD_SHIFT (0U) #define GTM_gtm_cls0_SPE0_CMD_SPE_CTRL_CMD_WIDTH (2U) #define GTM_gtm_cls0_SPE0_CMD_SPE_CTRL_CMD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_CMD_SPE_CTRL_CMD_SHIFT)) & GTM_gtm_cls0_SPE0_CMD_SPE_CTRL_CMD_MASK) #define GTM_gtm_cls0_SPE0_CMD_SPE_UPD_TRIG_MASK (0x10000U) #define GTM_gtm_cls0_SPE0_CMD_SPE_UPD_TRIG_SHIFT (16U) #define GTM_gtm_cls0_SPE0_CMD_SPE_UPD_TRIG_WIDTH (1U) #define GTM_gtm_cls0_SPE0_CMD_SPE_UPD_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_SPE0_CMD_SPE_UPD_TRIG_SHIFT)) & GTM_gtm_cls0_SPE0_CMD_SPE_UPD_TRIG_MASK) /*! @} */ /*! @name AXIM0_FREE - AXIM[i] slot allocation status. */ /*! @{ */ #define GTM_gtm_cls0_AXIM0_FREE_FREE0_MASK (0x1U) #define GTM_gtm_cls0_AXIM0_FREE_FREE0_SHIFT (0U) #define GTM_gtm_cls0_AXIM0_FREE_FREE0_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_FREE_FREE0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_FREE_FREE0_SHIFT)) & GTM_gtm_cls0_AXIM0_FREE_FREE0_MASK) #define GTM_gtm_cls0_AXIM0_FREE_FREE1_MASK (0x2U) #define GTM_gtm_cls0_AXIM0_FREE_FREE1_SHIFT (1U) #define GTM_gtm_cls0_AXIM0_FREE_FREE1_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_FREE_FREE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_FREE_FREE1_SHIFT)) & GTM_gtm_cls0_AXIM0_FREE_FREE1_MASK) #define GTM_gtm_cls0_AXIM0_FREE_FREE2_MASK (0x4U) #define GTM_gtm_cls0_AXIM0_FREE_FREE2_SHIFT (2U) #define GTM_gtm_cls0_AXIM0_FREE_FREE2_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_FREE_FREE2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_FREE_FREE2_SHIFT)) & GTM_gtm_cls0_AXIM0_FREE_FREE2_MASK) #define GTM_gtm_cls0_AXIM0_FREE_FREE3_MASK (0x8U) #define GTM_gtm_cls0_AXIM0_FREE_FREE3_SHIFT (3U) #define GTM_gtm_cls0_AXIM0_FREE_FREE3_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_FREE_FREE3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_FREE_FREE3_SHIFT)) & GTM_gtm_cls0_AXIM0_FREE_FREE3_MASK) /*! @} */ /*! @name AXIM0_REQUEST - AXIM[i] slot request (allocation). */ /*! @{ */ #define GTM_gtm_cls0_AXIM0_REQUEST_REQ1HOT0_MASK (0x1U) #define GTM_gtm_cls0_AXIM0_REQUEST_REQ1HOT0_SHIFT (0U) #define GTM_gtm_cls0_AXIM0_REQUEST_REQ1HOT0_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_REQUEST_REQ1HOT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_REQUEST_REQ1HOT0_SHIFT)) & GTM_gtm_cls0_AXIM0_REQUEST_REQ1HOT0_MASK) #define GTM_gtm_cls0_AXIM0_REQUEST_REQ1HOT1_MASK (0x2U) #define GTM_gtm_cls0_AXIM0_REQUEST_REQ1HOT1_SHIFT (1U) #define GTM_gtm_cls0_AXIM0_REQUEST_REQ1HOT1_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_REQUEST_REQ1HOT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_REQUEST_REQ1HOT1_SHIFT)) & GTM_gtm_cls0_AXIM0_REQUEST_REQ1HOT1_MASK) #define GTM_gtm_cls0_AXIM0_REQUEST_REQ1HOT2_MASK (0x4U) #define GTM_gtm_cls0_AXIM0_REQUEST_REQ1HOT2_SHIFT (2U) #define GTM_gtm_cls0_AXIM0_REQUEST_REQ1HOT2_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_REQUEST_REQ1HOT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_REQUEST_REQ1HOT2_SHIFT)) & GTM_gtm_cls0_AXIM0_REQUEST_REQ1HOT2_MASK) #define GTM_gtm_cls0_AXIM0_REQUEST_REQ1HOT3_MASK (0x8U) #define GTM_gtm_cls0_AXIM0_REQUEST_REQ1HOT3_SHIFT (3U) #define GTM_gtm_cls0_AXIM0_REQUEST_REQ1HOT3_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_REQUEST_REQ1HOT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_REQUEST_REQ1HOT3_SHIFT)) & GTM_gtm_cls0_AXIM0_REQUEST_REQ1HOT3_MASK) #define GTM_gtm_cls0_AXIM0_REQUEST_REQID_MASK (0xFF000000U) #define GTM_gtm_cls0_AXIM0_REQUEST_REQID_SHIFT (24U) #define GTM_gtm_cls0_AXIM0_REQUEST_REQID_WIDTH (8U) #define GTM_gtm_cls0_AXIM0_REQUEST_REQID(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_REQUEST_REQID_SHIFT)) & GTM_gtm_cls0_AXIM0_REQUEST_REQID_MASK) /*! @} */ /*! @name AXIM0_RELEASE - AXIM[i] slot release (de-allocation). */ /*! @{ */ #define GTM_gtm_cls0_AXIM0_RELEASE_RELREQ0_MASK (0x1U) #define GTM_gtm_cls0_AXIM0_RELEASE_RELREQ0_SHIFT (0U) #define GTM_gtm_cls0_AXIM0_RELEASE_RELREQ0_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_RELEASE_RELREQ0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_RELEASE_RELREQ0_SHIFT)) & GTM_gtm_cls0_AXIM0_RELEASE_RELREQ0_MASK) #define GTM_gtm_cls0_AXIM0_RELEASE_RELREQ1_MASK (0x2U) #define GTM_gtm_cls0_AXIM0_RELEASE_RELREQ1_SHIFT (1U) #define GTM_gtm_cls0_AXIM0_RELEASE_RELREQ1_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_RELEASE_RELREQ1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_RELEASE_RELREQ1_SHIFT)) & GTM_gtm_cls0_AXIM0_RELEASE_RELREQ1_MASK) #define GTM_gtm_cls0_AXIM0_RELEASE_RELREQ2_MASK (0x4U) #define GTM_gtm_cls0_AXIM0_RELEASE_RELREQ2_SHIFT (2U) #define GTM_gtm_cls0_AXIM0_RELEASE_RELREQ2_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_RELEASE_RELREQ2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_RELEASE_RELREQ2_SHIFT)) & GTM_gtm_cls0_AXIM0_RELEASE_RELREQ2_MASK) #define GTM_gtm_cls0_AXIM0_RELEASE_RELREQ3_MASK (0x8U) #define GTM_gtm_cls0_AXIM0_RELEASE_RELREQ3_SHIFT (3U) #define GTM_gtm_cls0_AXIM0_RELEASE_RELREQ3_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_RELEASE_RELREQ3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_RELEASE_RELREQ3_SHIFT)) & GTM_gtm_cls0_AXIM0_RELEASE_RELREQ3_MASK) /*! @} */ /*! @name AXIM0_SLOT0_ADDR_LOW - AXIM[i] slot[s] address bits 31:0 of AXI transaction. */ /*! @{ */ #define GTM_gtm_cls0_AXIM0_SLOT0_ADDR_LOW_AXI_ADDR_MASK (0xFFFFFFFFU) #define GTM_gtm_cls0_AXIM0_SLOT0_ADDR_LOW_AXI_ADDR_SHIFT (0U) #define GTM_gtm_cls0_AXIM0_SLOT0_ADDR_LOW_AXI_ADDR_WIDTH (32U) #define GTM_gtm_cls0_AXIM0_SLOT0_ADDR_LOW_AXI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT0_ADDR_LOW_AXI_ADDR_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT0_ADDR_LOW_AXI_ADDR_MASK) /*! @} */ /*! @name AXIM0_SLOT0_DATA_LOW - AXIM[i] slot[s] data bits 31:0 of AXI transaction. */ /*! @{ */ #define GTM_gtm_cls0_AXIM0_SLOT0_DATA_LOW_AXI_DATA_LOW_MASK (0xFFFFFFFFU) #define GTM_gtm_cls0_AXIM0_SLOT0_DATA_LOW_AXI_DATA_LOW_SHIFT (0U) #define GTM_gtm_cls0_AXIM0_SLOT0_DATA_LOW_AXI_DATA_LOW_WIDTH (32U) #define GTM_gtm_cls0_AXIM0_SLOT0_DATA_LOW_AXI_DATA_LOW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT0_DATA_LOW_AXI_DATA_LOW_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT0_DATA_LOW_AXI_DATA_LOW_MASK) /*! @} */ /*! @name AXIM0_SLOT0_CFG1 - AXIM[i] slot [s] configuration 1 */ /*! @{ */ #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_INCR_MASK (0xFU) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_INCR_SHIFT (0U) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_INCR_WIDTH (4U) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_INCR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT0_CFG1_INCR_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT0_CFG1_INCR_MASK) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AUTO_INCR_MASK (0x10U) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AUTO_INCR_SHIFT (4U) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AUTO_INCR_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AUTO_INCR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AUTO_INCR_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AUTO_INCR_MASK) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_PRIO_MASK (0x60U) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_PRIO_SHIFT (5U) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_PRIO_WIDTH (2U) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_PRIO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT0_CFG1_PRIO_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT0_CFG1_PRIO_MASK) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AXI_PROT_MASK (0x3800U) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AXI_PROT_SHIFT (11U) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AXI_PROT_WIDTH (3U) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AXI_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AXI_PROT_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AXI_PROT_MASK) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AXI_CACHE_MASK (0x3C000U) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AXI_CACHE_SHIFT (14U) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AXI_CACHE_WIDTH (4U) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AXI_CACHE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AXI_CACHE_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AXI_CACHE_MASK) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AXI_LOCK_MASK (0xC0000U) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AXI_LOCK_SHIFT (18U) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AXI_LOCK_WIDTH (2U) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AXI_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AXI_LOCK_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AXI_LOCK_MASK) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AXI_SIZE_MASK (0x1C00000U) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AXI_SIZE_SHIFT (22U) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AXI_SIZE_WIDTH (3U) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AXI_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AXI_SIZE_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AXI_SIZE_MASK) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AXI_RW_MASK (0x2000000U) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AXI_RW_SHIFT (25U) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AXI_RW_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AXI_RW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AXI_RW_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT0_CFG1_AXI_RW_MASK) /*! @} */ /*! @name AXIM0_SLOT0_CFG2 - AXIM[i] slot[s] configuration 2 */ /*! @{ */ #define GTM_gtm_cls0_AXIM0_SLOT0_CFG2_AXI_ID_MASK (0xFFFFU) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG2_AXI_ID_SHIFT (0U) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG2_AXI_ID_WIDTH (16U) #define GTM_gtm_cls0_AXIM0_SLOT0_CFG2_AXI_ID(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT0_CFG2_AXI_ID_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT0_CFG2_AXI_ID_MASK) /*! @} */ /*! @name AXIM0_SLOT0_STATUS - AXIM[i] slot[s] status */ /*! @{ */ #define GTM_gtm_cls0_AXIM0_SLOT0_STATUS_ALLOC_MASK (0x1U) #define GTM_gtm_cls0_AXIM0_SLOT0_STATUS_ALLOC_SHIFT (0U) #define GTM_gtm_cls0_AXIM0_SLOT0_STATUS_ALLOC_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_SLOT0_STATUS_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT0_STATUS_ALLOC_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT0_STATUS_ALLOC_MASK) #define GTM_gtm_cls0_AXIM0_SLOT0_STATUS_QUEUED_MASK (0x2U) #define GTM_gtm_cls0_AXIM0_SLOT0_STATUS_QUEUED_SHIFT (1U) #define GTM_gtm_cls0_AXIM0_SLOT0_STATUS_QUEUED_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_SLOT0_STATUS_QUEUED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT0_STATUS_QUEUED_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT0_STATUS_QUEUED_MASK) #define GTM_gtm_cls0_AXIM0_SLOT0_STATUS_STARTED_MASK (0x4U) #define GTM_gtm_cls0_AXIM0_SLOT0_STATUS_STARTED_SHIFT (2U) #define GTM_gtm_cls0_AXIM0_SLOT0_STATUS_STARTED_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_SLOT0_STATUS_STARTED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT0_STATUS_STARTED_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT0_STATUS_STARTED_MASK) #define GTM_gtm_cls0_AXIM0_SLOT0_STATUS_READY_MASK (0x8U) #define GTM_gtm_cls0_AXIM0_SLOT0_STATUS_READY_SHIFT (3U) #define GTM_gtm_cls0_AXIM0_SLOT0_STATUS_READY_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_SLOT0_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT0_STATUS_READY_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT0_STATUS_READY_MASK) #define GTM_gtm_cls0_AXIM0_SLOT0_STATUS_RESP_MASK (0x30U) #define GTM_gtm_cls0_AXIM0_SLOT0_STATUS_RESP_SHIFT (4U) #define GTM_gtm_cls0_AXIM0_SLOT0_STATUS_RESP_WIDTH (2U) #define GTM_gtm_cls0_AXIM0_SLOT0_STATUS_RESP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT0_STATUS_RESP_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT0_STATUS_RESP_MASK) /*! @} */ /*! @name AXIM0_SLOT1_ADDR_LOW - AXIM[i] slot[s] address bits 31:0 of AXI transaction. */ /*! @{ */ #define GTM_gtm_cls0_AXIM0_SLOT1_ADDR_LOW_AXI_ADDR_MASK (0xFFFFFFFFU) #define GTM_gtm_cls0_AXIM0_SLOT1_ADDR_LOW_AXI_ADDR_SHIFT (0U) #define GTM_gtm_cls0_AXIM0_SLOT1_ADDR_LOW_AXI_ADDR_WIDTH (32U) #define GTM_gtm_cls0_AXIM0_SLOT1_ADDR_LOW_AXI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT1_ADDR_LOW_AXI_ADDR_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT1_ADDR_LOW_AXI_ADDR_MASK) /*! @} */ /*! @name AXIM0_SLOT1_DATA_LOW - AXIM[i] slot[s] data bits 31:0 of AXI transaction. */ /*! @{ */ #define GTM_gtm_cls0_AXIM0_SLOT1_DATA_LOW_AXI_DATA_LOW_MASK (0xFFFFFFFFU) #define GTM_gtm_cls0_AXIM0_SLOT1_DATA_LOW_AXI_DATA_LOW_SHIFT (0U) #define GTM_gtm_cls0_AXIM0_SLOT1_DATA_LOW_AXI_DATA_LOW_WIDTH (32U) #define GTM_gtm_cls0_AXIM0_SLOT1_DATA_LOW_AXI_DATA_LOW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT1_DATA_LOW_AXI_DATA_LOW_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT1_DATA_LOW_AXI_DATA_LOW_MASK) /*! @} */ /*! @name AXIM0_SLOT1_CFG1 - AXIM[i] slot [s] configuration 1 */ /*! @{ */ #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_INCR_MASK (0xFU) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_INCR_SHIFT (0U) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_INCR_WIDTH (4U) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_INCR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT1_CFG1_INCR_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT1_CFG1_INCR_MASK) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AUTO_INCR_MASK (0x10U) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AUTO_INCR_SHIFT (4U) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AUTO_INCR_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AUTO_INCR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AUTO_INCR_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AUTO_INCR_MASK) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_PRIO_MASK (0x60U) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_PRIO_SHIFT (5U) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_PRIO_WIDTH (2U) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_PRIO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT1_CFG1_PRIO_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT1_CFG1_PRIO_MASK) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AXI_PROT_MASK (0x3800U) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AXI_PROT_SHIFT (11U) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AXI_PROT_WIDTH (3U) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AXI_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AXI_PROT_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AXI_PROT_MASK) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AXI_CACHE_MASK (0x3C000U) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AXI_CACHE_SHIFT (14U) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AXI_CACHE_WIDTH (4U) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AXI_CACHE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AXI_CACHE_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AXI_CACHE_MASK) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AXI_LOCK_MASK (0xC0000U) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AXI_LOCK_SHIFT (18U) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AXI_LOCK_WIDTH (2U) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AXI_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AXI_LOCK_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AXI_LOCK_MASK) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AXI_SIZE_MASK (0x1C00000U) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AXI_SIZE_SHIFT (22U) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AXI_SIZE_WIDTH (3U) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AXI_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AXI_SIZE_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AXI_SIZE_MASK) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AXI_RW_MASK (0x2000000U) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AXI_RW_SHIFT (25U) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AXI_RW_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AXI_RW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AXI_RW_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT1_CFG1_AXI_RW_MASK) /*! @} */ /*! @name AXIM0_SLOT1_CFG2 - AXIM[i] slot[s] configuration 2 */ /*! @{ */ #define GTM_gtm_cls0_AXIM0_SLOT1_CFG2_AXI_ID_MASK (0xFFFFU) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG2_AXI_ID_SHIFT (0U) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG2_AXI_ID_WIDTH (16U) #define GTM_gtm_cls0_AXIM0_SLOT1_CFG2_AXI_ID(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT1_CFG2_AXI_ID_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT1_CFG2_AXI_ID_MASK) /*! @} */ /*! @name AXIM0_SLOT1_STATUS - AXIM[i] slot[s] status */ /*! @{ */ #define GTM_gtm_cls0_AXIM0_SLOT1_STATUS_ALLOC_MASK (0x1U) #define GTM_gtm_cls0_AXIM0_SLOT1_STATUS_ALLOC_SHIFT (0U) #define GTM_gtm_cls0_AXIM0_SLOT1_STATUS_ALLOC_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_SLOT1_STATUS_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT1_STATUS_ALLOC_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT1_STATUS_ALLOC_MASK) #define GTM_gtm_cls0_AXIM0_SLOT1_STATUS_QUEUED_MASK (0x2U) #define GTM_gtm_cls0_AXIM0_SLOT1_STATUS_QUEUED_SHIFT (1U) #define GTM_gtm_cls0_AXIM0_SLOT1_STATUS_QUEUED_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_SLOT1_STATUS_QUEUED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT1_STATUS_QUEUED_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT1_STATUS_QUEUED_MASK) #define GTM_gtm_cls0_AXIM0_SLOT1_STATUS_STARTED_MASK (0x4U) #define GTM_gtm_cls0_AXIM0_SLOT1_STATUS_STARTED_SHIFT (2U) #define GTM_gtm_cls0_AXIM0_SLOT1_STATUS_STARTED_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_SLOT1_STATUS_STARTED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT1_STATUS_STARTED_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT1_STATUS_STARTED_MASK) #define GTM_gtm_cls0_AXIM0_SLOT1_STATUS_READY_MASK (0x8U) #define GTM_gtm_cls0_AXIM0_SLOT1_STATUS_READY_SHIFT (3U) #define GTM_gtm_cls0_AXIM0_SLOT1_STATUS_READY_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_SLOT1_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT1_STATUS_READY_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT1_STATUS_READY_MASK) #define GTM_gtm_cls0_AXIM0_SLOT1_STATUS_RESP_MASK (0x30U) #define GTM_gtm_cls0_AXIM0_SLOT1_STATUS_RESP_SHIFT (4U) #define GTM_gtm_cls0_AXIM0_SLOT1_STATUS_RESP_WIDTH (2U) #define GTM_gtm_cls0_AXIM0_SLOT1_STATUS_RESP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT1_STATUS_RESP_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT1_STATUS_RESP_MASK) /*! @} */ /*! @name AXIM0_SLOT2_ADDR_LOW - AXIM[i] slot[s] address bits 31:0 of AXI transaction. */ /*! @{ */ #define GTM_gtm_cls0_AXIM0_SLOT2_ADDR_LOW_AXI_ADDR_MASK (0xFFFFFFFFU) #define GTM_gtm_cls0_AXIM0_SLOT2_ADDR_LOW_AXI_ADDR_SHIFT (0U) #define GTM_gtm_cls0_AXIM0_SLOT2_ADDR_LOW_AXI_ADDR_WIDTH (32U) #define GTM_gtm_cls0_AXIM0_SLOT2_ADDR_LOW_AXI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT2_ADDR_LOW_AXI_ADDR_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT2_ADDR_LOW_AXI_ADDR_MASK) /*! @} */ /*! @name AXIM0_SLOT2_DATA_LOW - AXIM[i] slot[s] data bits 31:0 of AXI transaction. */ /*! @{ */ #define GTM_gtm_cls0_AXIM0_SLOT2_DATA_LOW_AXI_DATA_LOW_MASK (0xFFFFFFFFU) #define GTM_gtm_cls0_AXIM0_SLOT2_DATA_LOW_AXI_DATA_LOW_SHIFT (0U) #define GTM_gtm_cls0_AXIM0_SLOT2_DATA_LOW_AXI_DATA_LOW_WIDTH (32U) #define GTM_gtm_cls0_AXIM0_SLOT2_DATA_LOW_AXI_DATA_LOW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT2_DATA_LOW_AXI_DATA_LOW_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT2_DATA_LOW_AXI_DATA_LOW_MASK) /*! @} */ /*! @name AXIM0_SLOT2_CFG1 - AXIM[i] slot [s] configuration 1 */ /*! @{ */ #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_INCR_MASK (0xFU) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_INCR_SHIFT (0U) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_INCR_WIDTH (4U) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_INCR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT2_CFG1_INCR_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT2_CFG1_INCR_MASK) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AUTO_INCR_MASK (0x10U) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AUTO_INCR_SHIFT (4U) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AUTO_INCR_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AUTO_INCR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AUTO_INCR_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AUTO_INCR_MASK) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_PRIO_MASK (0x60U) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_PRIO_SHIFT (5U) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_PRIO_WIDTH (2U) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_PRIO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT2_CFG1_PRIO_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT2_CFG1_PRIO_MASK) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AXI_PROT_MASK (0x3800U) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AXI_PROT_SHIFT (11U) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AXI_PROT_WIDTH (3U) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AXI_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AXI_PROT_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AXI_PROT_MASK) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AXI_CACHE_MASK (0x3C000U) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AXI_CACHE_SHIFT (14U) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AXI_CACHE_WIDTH (4U) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AXI_CACHE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AXI_CACHE_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AXI_CACHE_MASK) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AXI_LOCK_MASK (0xC0000U) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AXI_LOCK_SHIFT (18U) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AXI_LOCK_WIDTH (2U) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AXI_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AXI_LOCK_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AXI_LOCK_MASK) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AXI_SIZE_MASK (0x1C00000U) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AXI_SIZE_SHIFT (22U) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AXI_SIZE_WIDTH (3U) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AXI_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AXI_SIZE_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AXI_SIZE_MASK) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AXI_RW_MASK (0x2000000U) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AXI_RW_SHIFT (25U) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AXI_RW_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AXI_RW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AXI_RW_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT2_CFG1_AXI_RW_MASK) /*! @} */ /*! @name AXIM0_SLOT2_CFG2 - AXIM[i] slot[s] configuration 2 */ /*! @{ */ #define GTM_gtm_cls0_AXIM0_SLOT2_CFG2_AXI_ID_MASK (0xFFFFU) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG2_AXI_ID_SHIFT (0U) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG2_AXI_ID_WIDTH (16U) #define GTM_gtm_cls0_AXIM0_SLOT2_CFG2_AXI_ID(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT2_CFG2_AXI_ID_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT2_CFG2_AXI_ID_MASK) /*! @} */ /*! @name AXIM0_SLOT2_STATUS - AXIM[i] slot[s] status */ /*! @{ */ #define GTM_gtm_cls0_AXIM0_SLOT2_STATUS_ALLOC_MASK (0x1U) #define GTM_gtm_cls0_AXIM0_SLOT2_STATUS_ALLOC_SHIFT (0U) #define GTM_gtm_cls0_AXIM0_SLOT2_STATUS_ALLOC_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_SLOT2_STATUS_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT2_STATUS_ALLOC_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT2_STATUS_ALLOC_MASK) #define GTM_gtm_cls0_AXIM0_SLOT2_STATUS_QUEUED_MASK (0x2U) #define GTM_gtm_cls0_AXIM0_SLOT2_STATUS_QUEUED_SHIFT (1U) #define GTM_gtm_cls0_AXIM0_SLOT2_STATUS_QUEUED_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_SLOT2_STATUS_QUEUED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT2_STATUS_QUEUED_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT2_STATUS_QUEUED_MASK) #define GTM_gtm_cls0_AXIM0_SLOT2_STATUS_STARTED_MASK (0x4U) #define GTM_gtm_cls0_AXIM0_SLOT2_STATUS_STARTED_SHIFT (2U) #define GTM_gtm_cls0_AXIM0_SLOT2_STATUS_STARTED_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_SLOT2_STATUS_STARTED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT2_STATUS_STARTED_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT2_STATUS_STARTED_MASK) #define GTM_gtm_cls0_AXIM0_SLOT2_STATUS_READY_MASK (0x8U) #define GTM_gtm_cls0_AXIM0_SLOT2_STATUS_READY_SHIFT (3U) #define GTM_gtm_cls0_AXIM0_SLOT2_STATUS_READY_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_SLOT2_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT2_STATUS_READY_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT2_STATUS_READY_MASK) #define GTM_gtm_cls0_AXIM0_SLOT2_STATUS_RESP_MASK (0x30U) #define GTM_gtm_cls0_AXIM0_SLOT2_STATUS_RESP_SHIFT (4U) #define GTM_gtm_cls0_AXIM0_SLOT2_STATUS_RESP_WIDTH (2U) #define GTM_gtm_cls0_AXIM0_SLOT2_STATUS_RESP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT2_STATUS_RESP_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT2_STATUS_RESP_MASK) /*! @} */ /*! @name AXIM0_SLOT3_ADDR_LOW - AXIM[i] slot[s] address bits 31:0 of AXI transaction. */ /*! @{ */ #define GTM_gtm_cls0_AXIM0_SLOT3_ADDR_LOW_AXI_ADDR_MASK (0xFFFFFFFFU) #define GTM_gtm_cls0_AXIM0_SLOT3_ADDR_LOW_AXI_ADDR_SHIFT (0U) #define GTM_gtm_cls0_AXIM0_SLOT3_ADDR_LOW_AXI_ADDR_WIDTH (32U) #define GTM_gtm_cls0_AXIM0_SLOT3_ADDR_LOW_AXI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT3_ADDR_LOW_AXI_ADDR_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT3_ADDR_LOW_AXI_ADDR_MASK) /*! @} */ /*! @name AXIM0_SLOT3_DATA_LOW - AXIM[i] slot[s] data bits 31:0 of AXI transaction. */ /*! @{ */ #define GTM_gtm_cls0_AXIM0_SLOT3_DATA_LOW_AXI_DATA_LOW_MASK (0xFFFFFFFFU) #define GTM_gtm_cls0_AXIM0_SLOT3_DATA_LOW_AXI_DATA_LOW_SHIFT (0U) #define GTM_gtm_cls0_AXIM0_SLOT3_DATA_LOW_AXI_DATA_LOW_WIDTH (32U) #define GTM_gtm_cls0_AXIM0_SLOT3_DATA_LOW_AXI_DATA_LOW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT3_DATA_LOW_AXI_DATA_LOW_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT3_DATA_LOW_AXI_DATA_LOW_MASK) /*! @} */ /*! @name AXIM0_SLOT3_CFG1 - AXIM[i] slot [s] configuration 1 */ /*! @{ */ #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_INCR_MASK (0xFU) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_INCR_SHIFT (0U) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_INCR_WIDTH (4U) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_INCR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT3_CFG1_INCR_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT3_CFG1_INCR_MASK) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AUTO_INCR_MASK (0x10U) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AUTO_INCR_SHIFT (4U) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AUTO_INCR_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AUTO_INCR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AUTO_INCR_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AUTO_INCR_MASK) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_PRIO_MASK (0x60U) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_PRIO_SHIFT (5U) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_PRIO_WIDTH (2U) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_PRIO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT3_CFG1_PRIO_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT3_CFG1_PRIO_MASK) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AXI_PROT_MASK (0x3800U) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AXI_PROT_SHIFT (11U) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AXI_PROT_WIDTH (3U) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AXI_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AXI_PROT_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AXI_PROT_MASK) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AXI_CACHE_MASK (0x3C000U) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AXI_CACHE_SHIFT (14U) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AXI_CACHE_WIDTH (4U) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AXI_CACHE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AXI_CACHE_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AXI_CACHE_MASK) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AXI_LOCK_MASK (0xC0000U) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AXI_LOCK_SHIFT (18U) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AXI_LOCK_WIDTH (2U) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AXI_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AXI_LOCK_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AXI_LOCK_MASK) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AXI_SIZE_MASK (0x1C00000U) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AXI_SIZE_SHIFT (22U) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AXI_SIZE_WIDTH (3U) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AXI_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AXI_SIZE_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AXI_SIZE_MASK) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AXI_RW_MASK (0x2000000U) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AXI_RW_SHIFT (25U) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AXI_RW_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AXI_RW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AXI_RW_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT3_CFG1_AXI_RW_MASK) /*! @} */ /*! @name AXIM0_SLOT3_CFG2 - AXIM[i] slot[s] configuration 2 */ /*! @{ */ #define GTM_gtm_cls0_AXIM0_SLOT3_CFG2_AXI_ID_MASK (0xFFFFU) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG2_AXI_ID_SHIFT (0U) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG2_AXI_ID_WIDTH (16U) #define GTM_gtm_cls0_AXIM0_SLOT3_CFG2_AXI_ID(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT3_CFG2_AXI_ID_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT3_CFG2_AXI_ID_MASK) /*! @} */ /*! @name AXIM0_SLOT3_STATUS - AXIM[i] slot[s] status */ /*! @{ */ #define GTM_gtm_cls0_AXIM0_SLOT3_STATUS_ALLOC_MASK (0x1U) #define GTM_gtm_cls0_AXIM0_SLOT3_STATUS_ALLOC_SHIFT (0U) #define GTM_gtm_cls0_AXIM0_SLOT3_STATUS_ALLOC_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_SLOT3_STATUS_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT3_STATUS_ALLOC_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT3_STATUS_ALLOC_MASK) #define GTM_gtm_cls0_AXIM0_SLOT3_STATUS_QUEUED_MASK (0x2U) #define GTM_gtm_cls0_AXIM0_SLOT3_STATUS_QUEUED_SHIFT (1U) #define GTM_gtm_cls0_AXIM0_SLOT3_STATUS_QUEUED_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_SLOT3_STATUS_QUEUED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT3_STATUS_QUEUED_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT3_STATUS_QUEUED_MASK) #define GTM_gtm_cls0_AXIM0_SLOT3_STATUS_STARTED_MASK (0x4U) #define GTM_gtm_cls0_AXIM0_SLOT3_STATUS_STARTED_SHIFT (2U) #define GTM_gtm_cls0_AXIM0_SLOT3_STATUS_STARTED_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_SLOT3_STATUS_STARTED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT3_STATUS_STARTED_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT3_STATUS_STARTED_MASK) #define GTM_gtm_cls0_AXIM0_SLOT3_STATUS_READY_MASK (0x8U) #define GTM_gtm_cls0_AXIM0_SLOT3_STATUS_READY_SHIFT (3U) #define GTM_gtm_cls0_AXIM0_SLOT3_STATUS_READY_WIDTH (1U) #define GTM_gtm_cls0_AXIM0_SLOT3_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT3_STATUS_READY_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT3_STATUS_READY_MASK) #define GTM_gtm_cls0_AXIM0_SLOT3_STATUS_RESP_MASK (0x30U) #define GTM_gtm_cls0_AXIM0_SLOT3_STATUS_RESP_SHIFT (4U) #define GTM_gtm_cls0_AXIM0_SLOT3_STATUS_RESP_WIDTH (2U) #define GTM_gtm_cls0_AXIM0_SLOT3_STATUS_RESP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_AXIM0_SLOT3_STATUS_RESP_SHIFT)) & GTM_gtm_cls0_AXIM0_SLOT3_STATUS_RESP_MASK) /*! @} */ /*! @name FIFO0_MEMORY - FIFO data memory */ /*! @{ */ #define GTM_gtm_cls0_FIFO0_MEMORY_DATA_MASK (0x1FFFFFFFU) #define GTM_gtm_cls0_FIFO0_MEMORY_DATA_SHIFT (0U) #define GTM_gtm_cls0_FIFO0_MEMORY_DATA_WIDTH (29U) #define GTM_gtm_cls0_FIFO0_MEMORY_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_FIFO0_MEMORY_DATA_SHIFT)) & GTM_gtm_cls0_FIFO0_MEMORY_DATA_MASK) /*! @} */ /*! @name DPLL_CTRL_0 - Control Register 0 */ /*! @{ */ #define GTM_gtm_cls0_DPLL_CTRL_0_MLT_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_CTRL_0_MLT_SHIFT (0U) #define GTM_gtm_cls0_DPLL_CTRL_0_MLT_WIDTH (10U) #define GTM_gtm_cls0_DPLL_CTRL_0_MLT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_0_MLT_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_0_MLT_MASK) #define GTM_gtm_cls0_DPLL_CTRL_0_IFP_MASK (0x400U) #define GTM_gtm_cls0_DPLL_CTRL_0_IFP_SHIFT (10U) #define GTM_gtm_cls0_DPLL_CTRL_0_IFP_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_0_IFP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_0_IFP_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_0_IFP_MASK) #define GTM_gtm_cls0_DPLL_CTRL_0_SNU_MASK (0xF800U) #define GTM_gtm_cls0_DPLL_CTRL_0_SNU_SHIFT (11U) #define GTM_gtm_cls0_DPLL_CTRL_0_SNU_WIDTH (5U) #define GTM_gtm_cls0_DPLL_CTRL_0_SNU(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_0_SNU_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_0_SNU_MASK) #define GTM_gtm_cls0_DPLL_CTRL_0_TNU_MASK (0x1FF0000U) #define GTM_gtm_cls0_DPLL_CTRL_0_TNU_SHIFT (16U) #define GTM_gtm_cls0_DPLL_CTRL_0_TNU_WIDTH (9U) #define GTM_gtm_cls0_DPLL_CTRL_0_TNU(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_0_TNU_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_0_TNU_MASK) #define GTM_gtm_cls0_DPLL_CTRL_0_AMS_MASK (0x2000000U) #define GTM_gtm_cls0_DPLL_CTRL_0_AMS_SHIFT (25U) #define GTM_gtm_cls0_DPLL_CTRL_0_AMS_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_0_AMS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_0_AMS_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_0_AMS_MASK) #define GTM_gtm_cls0_DPLL_CTRL_0_AMT_MASK (0x4000000U) #define GTM_gtm_cls0_DPLL_CTRL_0_AMT_SHIFT (26U) #define GTM_gtm_cls0_DPLL_CTRL_0_AMT_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_0_AMT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_0_AMT_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_0_AMT_MASK) #define GTM_gtm_cls0_DPLL_CTRL_0_IDS_MASK (0x8000000U) #define GTM_gtm_cls0_DPLL_CTRL_0_IDS_SHIFT (27U) #define GTM_gtm_cls0_DPLL_CTRL_0_IDS_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_0_IDS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_0_IDS_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_0_IDS_MASK) #define GTM_gtm_cls0_DPLL_CTRL_0_IDT_MASK (0x10000000U) #define GTM_gtm_cls0_DPLL_CTRL_0_IDT_SHIFT (28U) #define GTM_gtm_cls0_DPLL_CTRL_0_IDT_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_0_IDT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_0_IDT_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_0_IDT_MASK) #define GTM_gtm_cls0_DPLL_CTRL_0_SEN_MASK (0x20000000U) #define GTM_gtm_cls0_DPLL_CTRL_0_SEN_SHIFT (29U) #define GTM_gtm_cls0_DPLL_CTRL_0_SEN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_0_SEN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_0_SEN_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_0_SEN_MASK) #define GTM_gtm_cls0_DPLL_CTRL_0_TEN_MASK (0x40000000U) #define GTM_gtm_cls0_DPLL_CTRL_0_TEN_SHIFT (30U) #define GTM_gtm_cls0_DPLL_CTRL_0_TEN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_0_TEN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_0_TEN_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_0_TEN_MASK) #define GTM_gtm_cls0_DPLL_CTRL_0_RMO_MASK (0x80000000U) #define GTM_gtm_cls0_DPLL_CTRL_0_RMO_SHIFT (31U) #define GTM_gtm_cls0_DPLL_CTRL_0_RMO_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_0_RMO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_0_RMO_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_0_RMO_MASK) /*! @} */ /*! @name DPLL_CTRL_1 - Control Register 1 */ /*! @{ */ #define GTM_gtm_cls0_DPLL_CTRL_1_DMO_MASK (0x1U) #define GTM_gtm_cls0_DPLL_CTRL_1_DMO_SHIFT (0U) #define GTM_gtm_cls0_DPLL_CTRL_1_DMO_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_DMO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_DMO_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_DMO_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_DEN_MASK (0x2U) #define GTM_gtm_cls0_DPLL_CTRL_1_DEN_SHIFT (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_DEN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_DEN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_DEN_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_DEN_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_IDDS_MASK (0x4U) #define GTM_gtm_cls0_DPLL_CTRL_1_IDDS_SHIFT (2U) #define GTM_gtm_cls0_DPLL_CTRL_1_IDDS_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_IDDS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_IDDS_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_IDDS_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_COA_MASK (0x8U) #define GTM_gtm_cls0_DPLL_CTRL_1_COA_SHIFT (3U) #define GTM_gtm_cls0_DPLL_CTRL_1_COA_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_COA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_COA_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_COA_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_PIT_MASK (0x10U) #define GTM_gtm_cls0_DPLL_CTRL_1_PIT_SHIFT (4U) #define GTM_gtm_cls0_DPLL_CTRL_1_PIT_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_PIT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_PIT_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_PIT_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_SGE1_MASK (0x20U) #define GTM_gtm_cls0_DPLL_CTRL_1_SGE1_SHIFT (5U) #define GTM_gtm_cls0_DPLL_CTRL_1_SGE1_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_SGE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_SGE1_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_SGE1_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_DLM1_MASK (0x40U) #define GTM_gtm_cls0_DPLL_CTRL_1_DLM1_SHIFT (6U) #define GTM_gtm_cls0_DPLL_CTRL_1_DLM1_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_DLM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_DLM1_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_DLM1_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_PCM1_MASK (0x80U) #define GTM_gtm_cls0_DPLL_CTRL_1_PCM1_SHIFT (7U) #define GTM_gtm_cls0_DPLL_CTRL_1_PCM1_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_PCM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_PCM1_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_PCM1_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_SGE2_MASK (0x100U) #define GTM_gtm_cls0_DPLL_CTRL_1_SGE2_SHIFT (8U) #define GTM_gtm_cls0_DPLL_CTRL_1_SGE2_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_SGE2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_SGE2_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_SGE2_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_DLM2_MASK (0x200U) #define GTM_gtm_cls0_DPLL_CTRL_1_DLM2_SHIFT (9U) #define GTM_gtm_cls0_DPLL_CTRL_1_DLM2_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_DLM2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_DLM2_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_DLM2_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_PCM2_MASK (0x400U) #define GTM_gtm_cls0_DPLL_CTRL_1_PCM2_SHIFT (10U) #define GTM_gtm_cls0_DPLL_CTRL_1_PCM2_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_PCM2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_PCM2_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_PCM2_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_SYN_NS_MASK (0xF800U) #define GTM_gtm_cls0_DPLL_CTRL_1_SYN_NS_SHIFT (11U) #define GTM_gtm_cls0_DPLL_CTRL_1_SYN_NS_WIDTH (5U) #define GTM_gtm_cls0_DPLL_CTRL_1_SYN_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_SYN_NS_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_SYN_NS_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_SYN_NT_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_CTRL_1_SYN_NT_SHIFT (16U) #define GTM_gtm_cls0_DPLL_CTRL_1_SYN_NT_WIDTH (6U) #define GTM_gtm_cls0_DPLL_CTRL_1_SYN_NT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_SYN_NT_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_SYN_NT_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_LCD_MASK (0x400000U) #define GTM_gtm_cls0_DPLL_CTRL_1_LCD_SHIFT (22U) #define GTM_gtm_cls0_DPLL_CTRL_1_LCD_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_LCD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_LCD_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_LCD_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_SWR_MASK (0x800000U) #define GTM_gtm_cls0_DPLL_CTRL_1_SWR_SHIFT (23U) #define GTM_gtm_cls0_DPLL_CTRL_1_SWR_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_SWR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_SWR_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_SWR_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_SYSF_MASK (0x1000000U) #define GTM_gtm_cls0_DPLL_CTRL_1_SYSF_SHIFT (24U) #define GTM_gtm_cls0_DPLL_CTRL_1_SYSF_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_SYSF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_SYSF_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_SYSF_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_TS0_HRS_MASK (0x2000000U) #define GTM_gtm_cls0_DPLL_CTRL_1_TS0_HRS_SHIFT (25U) #define GTM_gtm_cls0_DPLL_CTRL_1_TS0_HRS_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_TS0_HRS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_TS0_HRS_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_TS0_HRS_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_TS0_HRT_MASK (0x4000000U) #define GTM_gtm_cls0_DPLL_CTRL_1_TS0_HRT_SHIFT (26U) #define GTM_gtm_cls0_DPLL_CTRL_1_TS0_HRT_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_TS0_HRT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_TS0_HRT_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_TS0_HRT_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_SMC_MASK (0x8000000U) #define GTM_gtm_cls0_DPLL_CTRL_1_SMC_SHIFT (27U) #define GTM_gtm_cls0_DPLL_CTRL_1_SMC_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_SMC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_SMC_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_SMC_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_SSL_MASK (0x30000000U) #define GTM_gtm_cls0_DPLL_CTRL_1_SSL_SHIFT (28U) #define GTM_gtm_cls0_DPLL_CTRL_1_SSL_WIDTH (2U) #define GTM_gtm_cls0_DPLL_CTRL_1_SSL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_SSL_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_SSL_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_TSL_MASK (0xC0000000U) #define GTM_gtm_cls0_DPLL_CTRL_1_TSL_SHIFT (30U) #define GTM_gtm_cls0_DPLL_CTRL_1_TSL_WIDTH (2U) #define GTM_gtm_cls0_DPLL_CTRL_1_TSL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_TSL_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_TSL_MASK) /*! @} */ /*! @name DPLL_CTRL_2 - Action Enable Register */ /*! @{ */ #define GTM_gtm_cls0_DPLL_CTRL_2_AEN0_MASK (0x100U) #define GTM_gtm_cls0_DPLL_CTRL_2_AEN0_SHIFT (8U) #define GTM_gtm_cls0_DPLL_CTRL_2_AEN0_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_2_AEN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_2_AEN0_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_2_AEN0_MASK) #define GTM_gtm_cls0_DPLL_CTRL_2_AEN1_MASK (0x200U) #define GTM_gtm_cls0_DPLL_CTRL_2_AEN1_SHIFT (9U) #define GTM_gtm_cls0_DPLL_CTRL_2_AEN1_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_2_AEN1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_2_AEN1_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_2_AEN1_MASK) #define GTM_gtm_cls0_DPLL_CTRL_2_AEN2_MASK (0x400U) #define GTM_gtm_cls0_DPLL_CTRL_2_AEN2_SHIFT (10U) #define GTM_gtm_cls0_DPLL_CTRL_2_AEN2_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_2_AEN2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_2_AEN2_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_2_AEN2_MASK) #define GTM_gtm_cls0_DPLL_CTRL_2_AEN3_MASK (0x800U) #define GTM_gtm_cls0_DPLL_CTRL_2_AEN3_SHIFT (11U) #define GTM_gtm_cls0_DPLL_CTRL_2_AEN3_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_2_AEN3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_2_AEN3_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_2_AEN3_MASK) #define GTM_gtm_cls0_DPLL_CTRL_2_AEN4_MASK (0x1000U) #define GTM_gtm_cls0_DPLL_CTRL_2_AEN4_SHIFT (12U) #define GTM_gtm_cls0_DPLL_CTRL_2_AEN4_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_2_AEN4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_2_AEN4_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_2_AEN4_MASK) #define GTM_gtm_cls0_DPLL_CTRL_2_AEN5_MASK (0x2000U) #define GTM_gtm_cls0_DPLL_CTRL_2_AEN5_SHIFT (13U) #define GTM_gtm_cls0_DPLL_CTRL_2_AEN5_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_2_AEN5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_2_AEN5_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_2_AEN5_MASK) #define GTM_gtm_cls0_DPLL_CTRL_2_AEN6_MASK (0x4000U) #define GTM_gtm_cls0_DPLL_CTRL_2_AEN6_SHIFT (14U) #define GTM_gtm_cls0_DPLL_CTRL_2_AEN6_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_2_AEN6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_2_AEN6_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_2_AEN6_MASK) #define GTM_gtm_cls0_DPLL_CTRL_2_AEN7_MASK (0x8000U) #define GTM_gtm_cls0_DPLL_CTRL_2_AEN7_SHIFT (15U) #define GTM_gtm_cls0_DPLL_CTRL_2_AEN7_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_2_AEN7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_2_AEN7_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_2_AEN7_MASK) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD0_MASK (0x10000U) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD0_SHIFT (16U) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD0_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_2_WAD0_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_2_WAD0_MASK) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD1_MASK (0x20000U) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD1_SHIFT (17U) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD1_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_2_WAD1_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_2_WAD1_MASK) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD2_MASK (0x40000U) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD2_SHIFT (18U) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD2_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_2_WAD2_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_2_WAD2_MASK) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD3_MASK (0x80000U) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD3_SHIFT (19U) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD3_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_2_WAD3_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_2_WAD3_MASK) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD4_MASK (0x100000U) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD4_SHIFT (20U) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD4_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_2_WAD4_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_2_WAD4_MASK) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD5_MASK (0x200000U) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD5_SHIFT (21U) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD5_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_2_WAD5_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_2_WAD5_MASK) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD6_MASK (0x400000U) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD6_SHIFT (22U) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD6_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_2_WAD6_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_2_WAD6_MASK) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD7_MASK (0x800000U) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD7_SHIFT (23U) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD7_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_2_WAD7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_2_WAD7_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_2_WAD7_MASK) /*! @} */ /*! @name DPLL_CTRL_3 - Action Enable Register */ /*! @{ */ #define GTM_gtm_cls0_DPLL_CTRL_3_AEN8_MASK (0x100U) #define GTM_gtm_cls0_DPLL_CTRL_3_AEN8_SHIFT (8U) #define GTM_gtm_cls0_DPLL_CTRL_3_AEN8_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_3_AEN8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_3_AEN8_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_3_AEN8_MASK) #define GTM_gtm_cls0_DPLL_CTRL_3_AEN9_MASK (0x200U) #define GTM_gtm_cls0_DPLL_CTRL_3_AEN9_SHIFT (9U) #define GTM_gtm_cls0_DPLL_CTRL_3_AEN9_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_3_AEN9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_3_AEN9_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_3_AEN9_MASK) #define GTM_gtm_cls0_DPLL_CTRL_3_AEN10_MASK (0x400U) #define GTM_gtm_cls0_DPLL_CTRL_3_AEN10_SHIFT (10U) #define GTM_gtm_cls0_DPLL_CTRL_3_AEN10_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_3_AEN10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_3_AEN10_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_3_AEN10_MASK) #define GTM_gtm_cls0_DPLL_CTRL_3_AEN11_MASK (0x800U) #define GTM_gtm_cls0_DPLL_CTRL_3_AEN11_SHIFT (11U) #define GTM_gtm_cls0_DPLL_CTRL_3_AEN11_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_3_AEN11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_3_AEN11_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_3_AEN11_MASK) #define GTM_gtm_cls0_DPLL_CTRL_3_AEN12_MASK (0x1000U) #define GTM_gtm_cls0_DPLL_CTRL_3_AEN12_SHIFT (12U) #define GTM_gtm_cls0_DPLL_CTRL_3_AEN12_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_3_AEN12(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_3_AEN12_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_3_AEN12_MASK) #define GTM_gtm_cls0_DPLL_CTRL_3_AEN13_MASK (0x2000U) #define GTM_gtm_cls0_DPLL_CTRL_3_AEN13_SHIFT (13U) #define GTM_gtm_cls0_DPLL_CTRL_3_AEN13_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_3_AEN13(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_3_AEN13_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_3_AEN13_MASK) #define GTM_gtm_cls0_DPLL_CTRL_3_AEN14_MASK (0x4000U) #define GTM_gtm_cls0_DPLL_CTRL_3_AEN14_SHIFT (14U) #define GTM_gtm_cls0_DPLL_CTRL_3_AEN14_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_3_AEN14(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_3_AEN14_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_3_AEN14_MASK) #define GTM_gtm_cls0_DPLL_CTRL_3_AEN15_MASK (0x8000U) #define GTM_gtm_cls0_DPLL_CTRL_3_AEN15_SHIFT (15U) #define GTM_gtm_cls0_DPLL_CTRL_3_AEN15_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_3_AEN15(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_3_AEN15_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_3_AEN15_MASK) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD8_MASK (0x10000U) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD8_SHIFT (16U) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD8_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_3_WAD8_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_3_WAD8_MASK) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD9_MASK (0x20000U) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD9_SHIFT (17U) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD9_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_3_WAD9_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_3_WAD9_MASK) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD10_MASK (0x40000U) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD10_SHIFT (18U) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD10_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_3_WAD10_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_3_WAD10_MASK) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD11_MASK (0x80000U) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD11_SHIFT (19U) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD11_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_3_WAD11_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_3_WAD11_MASK) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD12_MASK (0x100000U) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD12_SHIFT (20U) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD12_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD12(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_3_WAD12_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_3_WAD12_MASK) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD13_MASK (0x200000U) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD13_SHIFT (21U) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD13_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD13(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_3_WAD13_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_3_WAD13_MASK) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD14_MASK (0x400000U) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD14_SHIFT (22U) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD14_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD14(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_3_WAD14_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_3_WAD14_MASK) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD15_MASK (0x800000U) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD15_SHIFT (23U) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD15_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_3_WAD15(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_3_WAD15_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_3_WAD15_MASK) /*! @} */ /*! @name DPLL_CTRL_4 - Action Enable Register */ /*! @{ */ #define GTM_gtm_cls0_DPLL_CTRL_4_AEN16_MASK (0x100U) #define GTM_gtm_cls0_DPLL_CTRL_4_AEN16_SHIFT (8U) #define GTM_gtm_cls0_DPLL_CTRL_4_AEN16_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_4_AEN16(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_4_AEN16_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_4_AEN16_MASK) #define GTM_gtm_cls0_DPLL_CTRL_4_AEN17_MASK (0x200U) #define GTM_gtm_cls0_DPLL_CTRL_4_AEN17_SHIFT (9U) #define GTM_gtm_cls0_DPLL_CTRL_4_AEN17_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_4_AEN17(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_4_AEN17_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_4_AEN17_MASK) #define GTM_gtm_cls0_DPLL_CTRL_4_AEN18_MASK (0x400U) #define GTM_gtm_cls0_DPLL_CTRL_4_AEN18_SHIFT (10U) #define GTM_gtm_cls0_DPLL_CTRL_4_AEN18_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_4_AEN18(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_4_AEN18_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_4_AEN18_MASK) #define GTM_gtm_cls0_DPLL_CTRL_4_AEN19_MASK (0x800U) #define GTM_gtm_cls0_DPLL_CTRL_4_AEN19_SHIFT (11U) #define GTM_gtm_cls0_DPLL_CTRL_4_AEN19_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_4_AEN19(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_4_AEN19_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_4_AEN19_MASK) #define GTM_gtm_cls0_DPLL_CTRL_4_AEN20_MASK (0x1000U) #define GTM_gtm_cls0_DPLL_CTRL_4_AEN20_SHIFT (12U) #define GTM_gtm_cls0_DPLL_CTRL_4_AEN20_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_4_AEN20(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_4_AEN20_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_4_AEN20_MASK) #define GTM_gtm_cls0_DPLL_CTRL_4_AEN21_MASK (0x2000U) #define GTM_gtm_cls0_DPLL_CTRL_4_AEN21_SHIFT (13U) #define GTM_gtm_cls0_DPLL_CTRL_4_AEN21_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_4_AEN21(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_4_AEN21_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_4_AEN21_MASK) #define GTM_gtm_cls0_DPLL_CTRL_4_AEN22_MASK (0x4000U) #define GTM_gtm_cls0_DPLL_CTRL_4_AEN22_SHIFT (14U) #define GTM_gtm_cls0_DPLL_CTRL_4_AEN22_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_4_AEN22(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_4_AEN22_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_4_AEN22_MASK) #define GTM_gtm_cls0_DPLL_CTRL_4_AEN23_MASK (0x8000U) #define GTM_gtm_cls0_DPLL_CTRL_4_AEN23_SHIFT (15U) #define GTM_gtm_cls0_DPLL_CTRL_4_AEN23_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_4_AEN23(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_4_AEN23_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_4_AEN23_MASK) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD16_MASK (0x10000U) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD16_SHIFT (16U) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD16_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD16(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_4_WAD16_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_4_WAD16_MASK) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD17_MASK (0x20000U) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD17_SHIFT (17U) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD17_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD17(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_4_WAD17_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_4_WAD17_MASK) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD18_MASK (0x40000U) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD18_SHIFT (18U) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD18_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD18(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_4_WAD18_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_4_WAD18_MASK) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD19_MASK (0x80000U) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD19_SHIFT (19U) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD19_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD19(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_4_WAD19_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_4_WAD19_MASK) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD20_MASK (0x100000U) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD20_SHIFT (20U) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD20_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD20(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_4_WAD20_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_4_WAD20_MASK) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD21_MASK (0x200000U) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD21_SHIFT (21U) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD21_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD21(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_4_WAD21_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_4_WAD21_MASK) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD22_MASK (0x400000U) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD22_SHIFT (22U) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD22_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD22(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_4_WAD22_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_4_WAD22_MASK) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD23_MASK (0x800000U) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD23_SHIFT (23U) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD23_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_4_WAD23(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_4_WAD23_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_4_WAD23_MASK) /*! @} */ /*! @name DPLL_CTRL_5 - Action Enable Register */ /*! @{ */ #define GTM_gtm_cls0_DPLL_CTRL_5_AEN24_MASK (0x100U) #define GTM_gtm_cls0_DPLL_CTRL_5_AEN24_SHIFT (8U) #define GTM_gtm_cls0_DPLL_CTRL_5_AEN24_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_5_AEN24(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_5_AEN24_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_5_AEN24_MASK) #define GTM_gtm_cls0_DPLL_CTRL_5_AEN25_MASK (0x200U) #define GTM_gtm_cls0_DPLL_CTRL_5_AEN25_SHIFT (9U) #define GTM_gtm_cls0_DPLL_CTRL_5_AEN25_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_5_AEN25(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_5_AEN25_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_5_AEN25_MASK) #define GTM_gtm_cls0_DPLL_CTRL_5_AEN26_MASK (0x400U) #define GTM_gtm_cls0_DPLL_CTRL_5_AEN26_SHIFT (10U) #define GTM_gtm_cls0_DPLL_CTRL_5_AEN26_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_5_AEN26(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_5_AEN26_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_5_AEN26_MASK) #define GTM_gtm_cls0_DPLL_CTRL_5_AEN27_MASK (0x800U) #define GTM_gtm_cls0_DPLL_CTRL_5_AEN27_SHIFT (11U) #define GTM_gtm_cls0_DPLL_CTRL_5_AEN27_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_5_AEN27(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_5_AEN27_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_5_AEN27_MASK) #define GTM_gtm_cls0_DPLL_CTRL_5_AEN28_MASK (0x1000U) #define GTM_gtm_cls0_DPLL_CTRL_5_AEN28_SHIFT (12U) #define GTM_gtm_cls0_DPLL_CTRL_5_AEN28_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_5_AEN28(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_5_AEN28_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_5_AEN28_MASK) #define GTM_gtm_cls0_DPLL_CTRL_5_AEN29_MASK (0x2000U) #define GTM_gtm_cls0_DPLL_CTRL_5_AEN29_SHIFT (13U) #define GTM_gtm_cls0_DPLL_CTRL_5_AEN29_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_5_AEN29(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_5_AEN29_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_5_AEN29_MASK) #define GTM_gtm_cls0_DPLL_CTRL_5_AEN30_MASK (0x4000U) #define GTM_gtm_cls0_DPLL_CTRL_5_AEN30_SHIFT (14U) #define GTM_gtm_cls0_DPLL_CTRL_5_AEN30_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_5_AEN30(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_5_AEN30_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_5_AEN30_MASK) #define GTM_gtm_cls0_DPLL_CTRL_5_AEN31_MASK (0x8000U) #define GTM_gtm_cls0_DPLL_CTRL_5_AEN31_SHIFT (15U) #define GTM_gtm_cls0_DPLL_CTRL_5_AEN31_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_5_AEN31(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_5_AEN31_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_5_AEN31_MASK) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD24_MASK (0x10000U) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD24_SHIFT (16U) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD24_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD24(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_5_WAD24_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_5_WAD24_MASK) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD25_MASK (0x20000U) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD25_SHIFT (17U) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD25_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD25(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_5_WAD25_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_5_WAD25_MASK) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD26_MASK (0x40000U) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD26_SHIFT (18U) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD26_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD26(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_5_WAD26_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_5_WAD26_MASK) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD27_MASK (0x80000U) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD27_SHIFT (19U) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD27_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD27(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_5_WAD27_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_5_WAD27_MASK) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD28_MASK (0x100000U) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD28_SHIFT (20U) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD28_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD28(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_5_WAD28_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_5_WAD28_MASK) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD29_MASK (0x200000U) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD29_SHIFT (21U) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD29_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD29(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_5_WAD29_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_5_WAD29_MASK) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD30_MASK (0x400000U) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD30_SHIFT (22U) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD30_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD30(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_5_WAD30_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_5_WAD30_MASK) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD31_MASK (0x800000U) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD31_SHIFT (23U) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD31_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_5_WAD31(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_5_WAD31_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_5_WAD31_MASK) /*! @} */ /*! @name DPLL_ACT_STA - Action Status Register including Shadow Register */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N0_MASK (0x1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N0_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N0_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N0_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N0_MASK) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N1_MASK (0x2U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N1_SHIFT (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N1_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N1_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N1_MASK) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N2_MASK (0x4U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N2_SHIFT (2U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N2_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N2_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N2_MASK) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N3_MASK (0x8U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N3_SHIFT (3U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N3_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N3_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N3_MASK) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N4_MASK (0x10U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N4_SHIFT (4U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N4_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N4_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N4_MASK) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N5_MASK (0x20U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N5_SHIFT (5U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N5_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N5_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N5_MASK) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N6_MASK (0x40U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N6_SHIFT (6U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N6_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N6_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N6_MASK) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N7_MASK (0x80U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N7_SHIFT (7U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N7_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N7_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N7_MASK) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N8_MASK (0x100U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N8_SHIFT (8U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N8_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N8(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N8_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N8_MASK) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N9_MASK (0x200U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N9_SHIFT (9U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N9_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N9(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N9_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N9_MASK) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N10_MASK (0x400U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N10_SHIFT (10U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N10_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N10(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N10_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N10_MASK) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N11_MASK (0x800U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N11_SHIFT (11U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N11_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N11(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N11_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N11_MASK) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N12_MASK (0x1000U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N12_SHIFT (12U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N12_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N12(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N12_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N12_MASK) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N13_MASK (0x2000U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N13_SHIFT (13U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N13_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N13(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N13_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N13_MASK) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N14_MASK (0x4000U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N14_SHIFT (14U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N14_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N14(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N14_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N14_MASK) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N15_MASK (0x8000U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N15_SHIFT (15U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N15_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N15(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N15_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N15_MASK) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N16_MASK (0x10000U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N16_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N16_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N16(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N16_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N16_MASK) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N17_MASK (0x20000U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N17_SHIFT (17U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N17_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N17(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N17_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N17_MASK) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N18_MASK (0x40000U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N18_SHIFT (18U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N18_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N18(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N18_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N18_MASK) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N19_MASK (0x80000U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N19_SHIFT (19U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N19_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N19(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N19_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N19_MASK) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N20_MASK (0x100000U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N20_SHIFT (20U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N20_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N20(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N20_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N20_MASK) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N21_MASK (0x200000U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N21_SHIFT (21U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N21_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N21(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N21_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N21_MASK) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N22_MASK (0x400000U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N22_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N22_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N22(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N22_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N22_MASK) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N23_MASK (0x800000U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N23_SHIFT (23U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N23_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N23(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N23_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N23_MASK) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N24_MASK (0x1000000U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N24_SHIFT (24U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N24_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N24(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N24_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N24_MASK) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N25_MASK (0x2000000U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N25_SHIFT (25U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N25_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N25(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N25_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N25_MASK) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N26_MASK (0x4000000U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N26_SHIFT (26U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N26_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N26(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N26_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N26_MASK) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N27_MASK (0x8000000U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N27_SHIFT (27U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N27_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N27(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N27_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N27_MASK) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N28_MASK (0x10000000U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N28_SHIFT (28U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N28_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N28(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N28_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N28_MASK) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N29_MASK (0x20000000U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N29_SHIFT (29U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N29_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N29(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N29_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N29_MASK) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N30_MASK (0x40000000U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N30_SHIFT (30U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N30_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N30(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N30_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N30_MASK) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N31_MASK (0x80000000U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N31_SHIFT (31U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N31_WIDTH (1U) #define GTM_gtm_cls0_DPLL_ACT_STA_ACT_N31(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACT_STA_ACT_N31_SHIFT)) & GTM_gtm_cls0_DPLL_ACT_STA_ACT_N31_MASK) /*! @} */ /*! @name DPLL_OSW - Offset and Switch old/new Address Register */ /*! @{ */ #define GTM_gtm_cls0_DPLL_OSW_SWON_S_MASK (0x1U) #define GTM_gtm_cls0_DPLL_OSW_SWON_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_OSW_SWON_S_WIDTH (1U) #define GTM_gtm_cls0_DPLL_OSW_SWON_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_OSW_SWON_S_SHIFT)) & GTM_gtm_cls0_DPLL_OSW_SWON_S_MASK) #define GTM_gtm_cls0_DPLL_OSW_SWON_T_MASK (0x2U) #define GTM_gtm_cls0_DPLL_OSW_SWON_T_SHIFT (1U) #define GTM_gtm_cls0_DPLL_OSW_SWON_T_WIDTH (1U) #define GTM_gtm_cls0_DPLL_OSW_SWON_T(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_OSW_SWON_T_SHIFT)) & GTM_gtm_cls0_DPLL_OSW_SWON_T_MASK) #define GTM_gtm_cls0_DPLL_OSW_OSS_MASK (0x300U) #define GTM_gtm_cls0_DPLL_OSW_OSS_SHIFT (8U) #define GTM_gtm_cls0_DPLL_OSW_OSS_WIDTH (2U) #define GTM_gtm_cls0_DPLL_OSW_OSS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_OSW_OSS_SHIFT)) & GTM_gtm_cls0_DPLL_OSW_OSS_MASK) /*! @} */ /*! @name DPLL_AOSV_2 - Address Offset Register of RAM 2 Regions */ /*! @{ */ #define GTM_gtm_cls0_DPLL_AOSV_2_AOSV_2A_MASK (0xFFU) #define GTM_gtm_cls0_DPLL_AOSV_2_AOSV_2A_SHIFT (0U) #define GTM_gtm_cls0_DPLL_AOSV_2_AOSV_2A_WIDTH (8U) #define GTM_gtm_cls0_DPLL_AOSV_2_AOSV_2A(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_AOSV_2_AOSV_2A_SHIFT)) & GTM_gtm_cls0_DPLL_AOSV_2_AOSV_2A_MASK) #define GTM_gtm_cls0_DPLL_AOSV_2_AOSV_2B_MASK (0xFF00U) #define GTM_gtm_cls0_DPLL_AOSV_2_AOSV_2B_SHIFT (8U) #define GTM_gtm_cls0_DPLL_AOSV_2_AOSV_2B_WIDTH (8U) #define GTM_gtm_cls0_DPLL_AOSV_2_AOSV_2B(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_AOSV_2_AOSV_2B_SHIFT)) & GTM_gtm_cls0_DPLL_AOSV_2_AOSV_2B_MASK) #define GTM_gtm_cls0_DPLL_AOSV_2_AOSV_2C_MASK (0xFF0000U) #define GTM_gtm_cls0_DPLL_AOSV_2_AOSV_2C_SHIFT (16U) #define GTM_gtm_cls0_DPLL_AOSV_2_AOSV_2C_WIDTH (8U) #define GTM_gtm_cls0_DPLL_AOSV_2_AOSV_2C(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_AOSV_2_AOSV_2C_SHIFT)) & GTM_gtm_cls0_DPLL_AOSV_2_AOSV_2C_MASK) #define GTM_gtm_cls0_DPLL_AOSV_2_AOSV_2D_MASK (0xFF000000U) #define GTM_gtm_cls0_DPLL_AOSV_2_AOSV_2D_SHIFT (24U) #define GTM_gtm_cls0_DPLL_AOSV_2_AOSV_2D_WIDTH (8U) #define GTM_gtm_cls0_DPLL_AOSV_2_AOSV_2D(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_AOSV_2_AOSV_2D_SHIFT)) & GTM_gtm_cls0_DPLL_AOSV_2_AOSV_2D_MASK) /*! @} */ /*! @name DPLL_APT - Actual RAM Pointer Address for TRIGGER */ /*! @{ */ #define GTM_gtm_cls0_DPLL_APT_WAPT_MASK (0x2U) #define GTM_gtm_cls0_DPLL_APT_WAPT_SHIFT (1U) #define GTM_gtm_cls0_DPLL_APT_WAPT_WIDTH (1U) #define GTM_gtm_cls0_DPLL_APT_WAPT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_APT_WAPT_SHIFT)) & GTM_gtm_cls0_DPLL_APT_WAPT_MASK) #define GTM_gtm_cls0_DPLL_APT_APT_MASK (0xFFCU) #define GTM_gtm_cls0_DPLL_APT_APT_SHIFT (2U) #define GTM_gtm_cls0_DPLL_APT_APT_WIDTH (10U) #define GTM_gtm_cls0_DPLL_APT_APT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_APT_APT_SHIFT)) & GTM_gtm_cls0_DPLL_APT_APT_MASK) #define GTM_gtm_cls0_DPLL_APT_WAPT_2B_MASK (0x2000U) #define GTM_gtm_cls0_DPLL_APT_WAPT_2B_SHIFT (13U) #define GTM_gtm_cls0_DPLL_APT_WAPT_2B_WIDTH (1U) #define GTM_gtm_cls0_DPLL_APT_WAPT_2B(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_APT_WAPT_2B_SHIFT)) & GTM_gtm_cls0_DPLL_APT_WAPT_2B_MASK) #define GTM_gtm_cls0_DPLL_APT_APT_2B_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_APT_APT_2B_SHIFT (14U) #define GTM_gtm_cls0_DPLL_APT_APT_2B_WIDTH (10U) #define GTM_gtm_cls0_DPLL_APT_APT_2B(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_APT_APT_2B_SHIFT)) & GTM_gtm_cls0_DPLL_APT_APT_2B_MASK) /*! @} */ /*! @name DPLL_APS - Actual RAM Pointer Address for STATE */ /*! @{ */ #define GTM_gtm_cls0_DPLL_APS_WAPS_MASK (0x2U) #define GTM_gtm_cls0_DPLL_APS_WAPS_SHIFT (1U) #define GTM_gtm_cls0_DPLL_APS_WAPS_WIDTH (1U) #define GTM_gtm_cls0_DPLL_APS_WAPS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_APS_WAPS_SHIFT)) & GTM_gtm_cls0_DPLL_APS_WAPS_MASK) #define GTM_gtm_cls0_DPLL_APS_APS_MASK (0xFCU) #define GTM_gtm_cls0_DPLL_APS_APS_SHIFT (2U) #define GTM_gtm_cls0_DPLL_APS_APS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_APS_APS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_APS_APS_SHIFT)) & GTM_gtm_cls0_DPLL_APS_APS_MASK) #define GTM_gtm_cls0_DPLL_APS_WAPS_1C2_MASK (0x2000U) #define GTM_gtm_cls0_DPLL_APS_WAPS_1C2_SHIFT (13U) #define GTM_gtm_cls0_DPLL_APS_WAPS_1C2_WIDTH (1U) #define GTM_gtm_cls0_DPLL_APS_WAPS_1C2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_APS_WAPS_1C2_SHIFT)) & GTM_gtm_cls0_DPLL_APS_WAPS_1C2_MASK) #define GTM_gtm_cls0_DPLL_APS_APS_1C2_MASK (0xFC000U) #define GTM_gtm_cls0_DPLL_APS_APS_1C2_SHIFT (14U) #define GTM_gtm_cls0_DPLL_APS_APS_1C2_WIDTH (6U) #define GTM_gtm_cls0_DPLL_APS_APS_1C2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_APS_APS_1C2_SHIFT)) & GTM_gtm_cls0_DPLL_APS_APS_1C2_MASK) /*! @} */ /*! @name DPLL_APT_2C - Actual RAM Pointer Address for Region 2c */ /*! @{ */ #define GTM_gtm_cls0_DPLL_APT_2C_APT_2C_MASK (0xFFCU) #define GTM_gtm_cls0_DPLL_APT_2C_APT_2C_SHIFT (2U) #define GTM_gtm_cls0_DPLL_APT_2C_APT_2C_WIDTH (10U) #define GTM_gtm_cls0_DPLL_APT_2C_APT_2C(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_APT_2C_APT_2C_SHIFT)) & GTM_gtm_cls0_DPLL_APT_2C_APT_2C_MASK) /*! @} */ /*! @name DPLL_APS_1C3 - Actual RAM Pointer Address for RAM region 1c3 */ /*! @{ */ #define GTM_gtm_cls0_DPLL_APS_1C3_APS_1C3_MASK (0xFCU) #define GTM_gtm_cls0_DPLL_APS_1C3_APS_1C3_SHIFT (2U) #define GTM_gtm_cls0_DPLL_APS_1C3_APS_1C3_WIDTH (6U) #define GTM_gtm_cls0_DPLL_APS_1C3_APS_1C3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_APS_1C3_APS_1C3_SHIFT)) & GTM_gtm_cls0_DPLL_APS_1C3_APS_1C3_MASK) /*! @} */ /*! @name DPLL_NUTC - Number of Recent TRIGGER Events used for Calculations */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NUTC_NUTE_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NUTC_NUTE_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NUTC_NUTE_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NUTC_NUTE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NUTC_NUTE_SHIFT)) & GTM_gtm_cls0_DPLL_NUTC_NUTE_MASK) #define GTM_gtm_cls0_DPLL_NUTC_FST_MASK (0x400U) #define GTM_gtm_cls0_DPLL_NUTC_FST_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NUTC_FST_WIDTH (1U) #define GTM_gtm_cls0_DPLL_NUTC_FST(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NUTC_FST_SHIFT)) & GTM_gtm_cls0_DPLL_NUTC_FST_MASK) #define GTM_gtm_cls0_DPLL_NUTC_SYN_T_MASK (0xE000U) #define GTM_gtm_cls0_DPLL_NUTC_SYN_T_SHIFT (13U) #define GTM_gtm_cls0_DPLL_NUTC_SYN_T_WIDTH (3U) #define GTM_gtm_cls0_DPLL_NUTC_SYN_T(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NUTC_SYN_T_SHIFT)) & GTM_gtm_cls0_DPLL_NUTC_SYN_T_MASK) #define GTM_gtm_cls0_DPLL_NUTC_SYN_T_OLD_MASK (0x70000U) #define GTM_gtm_cls0_DPLL_NUTC_SYN_T_OLD_SHIFT (16U) #define GTM_gtm_cls0_DPLL_NUTC_SYN_T_OLD_WIDTH (3U) #define GTM_gtm_cls0_DPLL_NUTC_SYN_T_OLD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NUTC_SYN_T_OLD_SHIFT)) & GTM_gtm_cls0_DPLL_NUTC_SYN_T_OLD_MASK) #define GTM_gtm_cls0_DPLL_NUTC_VTN_MASK (0x1F80000U) #define GTM_gtm_cls0_DPLL_NUTC_VTN_SHIFT (19U) #define GTM_gtm_cls0_DPLL_NUTC_VTN_WIDTH (6U) #define GTM_gtm_cls0_DPLL_NUTC_VTN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NUTC_VTN_SHIFT)) & GTM_gtm_cls0_DPLL_NUTC_VTN_MASK) #define GTM_gtm_cls0_DPLL_NUTC_WNUT_MASK (0x20000000U) #define GTM_gtm_cls0_DPLL_NUTC_WNUT_SHIFT (29U) #define GTM_gtm_cls0_DPLL_NUTC_WNUT_WIDTH (1U) #define GTM_gtm_cls0_DPLL_NUTC_WNUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NUTC_WNUT_SHIFT)) & GTM_gtm_cls0_DPLL_NUTC_WNUT_MASK) #define GTM_gtm_cls0_DPLL_NUTC_WSYN_MASK (0x40000000U) #define GTM_gtm_cls0_DPLL_NUTC_WSYN_SHIFT (30U) #define GTM_gtm_cls0_DPLL_NUTC_WSYN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_NUTC_WSYN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NUTC_WSYN_SHIFT)) & GTM_gtm_cls0_DPLL_NUTC_WSYN_MASK) #define GTM_gtm_cls0_DPLL_NUTC_WVTN_MASK (0x80000000U) #define GTM_gtm_cls0_DPLL_NUTC_WVTN_SHIFT (31U) #define GTM_gtm_cls0_DPLL_NUTC_WVTN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_NUTC_WVTN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NUTC_WVTN_SHIFT)) & GTM_gtm_cls0_DPLL_NUTC_WVTN_MASK) /*! @} */ /*! @name DPLL_NUSC - Number of Recent STATE Events used for Calculations */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NUSC_NUSE_MASK (0x3FU) #define GTM_gtm_cls0_DPLL_NUSC_NUSE_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NUSC_NUSE_WIDTH (6U) #define GTM_gtm_cls0_DPLL_NUSC_NUSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NUSC_NUSE_SHIFT)) & GTM_gtm_cls0_DPLL_NUSC_NUSE_MASK) #define GTM_gtm_cls0_DPLL_NUSC_FSS_MASK (0x40U) #define GTM_gtm_cls0_DPLL_NUSC_FSS_SHIFT (6U) #define GTM_gtm_cls0_DPLL_NUSC_FSS_WIDTH (1U) #define GTM_gtm_cls0_DPLL_NUSC_FSS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NUSC_FSS_SHIFT)) & GTM_gtm_cls0_DPLL_NUSC_FSS_MASK) #define GTM_gtm_cls0_DPLL_NUSC_SYN_S_MASK (0x1F80U) #define GTM_gtm_cls0_DPLL_NUSC_SYN_S_SHIFT (7U) #define GTM_gtm_cls0_DPLL_NUSC_SYN_S_WIDTH (6U) #define GTM_gtm_cls0_DPLL_NUSC_SYN_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NUSC_SYN_S_SHIFT)) & GTM_gtm_cls0_DPLL_NUSC_SYN_S_MASK) #define GTM_gtm_cls0_DPLL_NUSC_SYN_S_OLD_MASK (0x7E000U) #define GTM_gtm_cls0_DPLL_NUSC_SYN_S_OLD_SHIFT (13U) #define GTM_gtm_cls0_DPLL_NUSC_SYN_S_OLD_WIDTH (6U) #define GTM_gtm_cls0_DPLL_NUSC_SYN_S_OLD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NUSC_SYN_S_OLD_SHIFT)) & GTM_gtm_cls0_DPLL_NUSC_SYN_S_OLD_MASK) #define GTM_gtm_cls0_DPLL_NUSC_VSN_MASK (0x1F80000U) #define GTM_gtm_cls0_DPLL_NUSC_VSN_SHIFT (19U) #define GTM_gtm_cls0_DPLL_NUSC_VSN_WIDTH (6U) #define GTM_gtm_cls0_DPLL_NUSC_VSN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NUSC_VSN_SHIFT)) & GTM_gtm_cls0_DPLL_NUSC_VSN_MASK) #define GTM_gtm_cls0_DPLL_NUSC_WNUS_MASK (0x20000000U) #define GTM_gtm_cls0_DPLL_NUSC_WNUS_SHIFT (29U) #define GTM_gtm_cls0_DPLL_NUSC_WNUS_WIDTH (1U) #define GTM_gtm_cls0_DPLL_NUSC_WNUS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NUSC_WNUS_SHIFT)) & GTM_gtm_cls0_DPLL_NUSC_WNUS_MASK) #define GTM_gtm_cls0_DPLL_NUSC_WSYN_MASK (0x40000000U) #define GTM_gtm_cls0_DPLL_NUSC_WSYN_SHIFT (30U) #define GTM_gtm_cls0_DPLL_NUSC_WSYN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_NUSC_WSYN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NUSC_WSYN_SHIFT)) & GTM_gtm_cls0_DPLL_NUSC_WSYN_MASK) #define GTM_gtm_cls0_DPLL_NUSC_WVSN_MASK (0x80000000U) #define GTM_gtm_cls0_DPLL_NUSC_WVSN_SHIFT (31U) #define GTM_gtm_cls0_DPLL_NUSC_WVSN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_NUSC_WVSN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NUSC_WVSN_SHIFT)) & GTM_gtm_cls0_DPLL_NUSC_WVSN_MASK) /*! @} */ /*! @name DPLL_NTI_CNT - Number of Active TRIGGER Events to Interrupt */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NTI_CNT_NTI_CNT_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NTI_CNT_NTI_CNT_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NTI_CNT_NTI_CNT_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NTI_CNT_NTI_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NTI_CNT_NTI_CNT_SHIFT)) & GTM_gtm_cls0_DPLL_NTI_CNT_NTI_CNT_MASK) /*! @} */ /*! @name DPLL_IRQ_NOTIFY - Interrupt Register */ /*! @{ */ #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_PDI_MASK (0x1U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_PDI_SHIFT (0U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_PDI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_PDI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_NOTIFY_PDI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_NOTIFY_PDI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_PEI_MASK (0x2U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_PEI_SHIFT (1U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_PEI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_PEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_NOTIFY_PEI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_NOTIFY_PEI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TINI_MASK (0x4U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TINI_SHIFT (2U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TINI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TINI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TINI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TINI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TAXI_MASK (0x8U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TAXI_SHIFT (3U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TAXI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TAXI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TAXI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TAXI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_SISI_MASK (0x10U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_SISI_SHIFT (4U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_SISI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_SISI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_NOTIFY_SISI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_NOTIFY_SISI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TISI_MASK (0x20U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TISI_SHIFT (5U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TISI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TISI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TISI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TISI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_MSI_MASK (0x40U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_MSI_SHIFT (6U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_MSI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_MSI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_NOTIFY_MSI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_NOTIFY_MSI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_MTI_MASK (0x80U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_MTI_SHIFT (7U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_MTI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_MTI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_NOTIFY_MTI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_NOTIFY_MTI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_SASI_MASK (0x100U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_SASI_SHIFT (8U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_SASI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_SASI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_NOTIFY_SASI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_NOTIFY_SASI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TASI_MASK (0x200U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TASI_SHIFT (9U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TASI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TASI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TASI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TASI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_PWI_MASK (0x400U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_PWI_SHIFT (10U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_PWI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_PWI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_NOTIFY_PWI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_NOTIFY_PWI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_W2I_MASK (0x800U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_W2I_SHIFT (11U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_W2I_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_W2I(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_NOTIFY_W2I_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_NOTIFY_W2I_MASK) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_W1I_MASK (0x1000U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_W1I_SHIFT (12U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_W1I_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_W1I(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_NOTIFY_W1I_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_NOTIFY_W1I_MASK) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_GL1I_MASK (0x2000U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_GL1I_SHIFT (13U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_GL1I_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_GL1I(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_NOTIFY_GL1I_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_NOTIFY_GL1I_MASK) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_LL1I_MASK (0x4000U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_LL1I_SHIFT (14U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_LL1I_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_LL1I(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_NOTIFY_LL1I_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_NOTIFY_LL1I_MASK) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_EI_MASK (0x8000U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_EI_SHIFT (15U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_EI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_EI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_NOTIFY_EI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_NOTIFY_EI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_GL2I_MASK (0x10000U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_GL2I_SHIFT (16U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_GL2I_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_GL2I(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_NOTIFY_GL2I_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_NOTIFY_GL2I_MASK) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_LL2I_MASK (0x20000U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_LL2I_SHIFT (17U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_LL2I_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_LL2I(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_NOTIFY_LL2I_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_NOTIFY_LL2I_MASK) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TE0I_MASK (0x40000U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TE0I_SHIFT (18U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TE0I_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TE0I(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TE0I_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TE0I_MASK) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TE1I_MASK (0x80000U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TE1I_SHIFT (19U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TE1I_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TE1I(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TE1I_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TE1I_MASK) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TE2I_MASK (0x100000U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TE2I_SHIFT (20U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TE2I_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TE2I(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TE2I_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TE2I_MASK) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TE3I_MASK (0x200000U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TE3I_SHIFT (21U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TE3I_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TE3I(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TE3I_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TE3I_MASK) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TE4I_MASK (0x400000U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TE4I_SHIFT (22U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TE4I_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TE4I(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TE4I_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TE4I_MASK) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_CDTI_MASK (0x800000U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_CDTI_SHIFT (23U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_CDTI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_CDTI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_NOTIFY_CDTI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_NOTIFY_CDTI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_CDSI_MASK (0x1000000U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_CDSI_SHIFT (24U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_CDSI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_CDSI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_NOTIFY_CDSI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_NOTIFY_CDSI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TORI_MASK (0x2000000U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TORI_SHIFT (25U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TORI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TORI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TORI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_NOTIFY_TORI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_SORI_MASK (0x4000000U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_SORI_SHIFT (26U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_SORI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_SORI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_NOTIFY_SORI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_NOTIFY_SORI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_DCGI_MASK (0x8000000U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_DCGI_SHIFT (27U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_DCGI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_NOTIFY_DCGI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_NOTIFY_DCGI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_NOTIFY_DCGI_MASK) /*! @} */ /*! @name DPLL_IRQ_EN - Interrupt Enable Register */ /*! @{ */ #define GTM_gtm_cls0_DPLL_IRQ_EN_PDI_IRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_DPLL_IRQ_EN_PDI_IRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_DPLL_IRQ_EN_PDI_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_EN_PDI_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_EN_PDI_IRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_EN_PDI_IRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_IRQ_EN_PEI_IRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_DPLL_IRQ_EN_PEI_IRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_DPLL_IRQ_EN_PEI_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_EN_PEI_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_EN_PEI_IRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_EN_PEI_IRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_IRQ_EN_TINI_IRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_DPLL_IRQ_EN_TINI_IRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_DPLL_IRQ_EN_TINI_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_EN_TINI_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_EN_TINI_IRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_EN_TINI_IRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_IRQ_EN_TAXI_IRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_DPLL_IRQ_EN_TAXI_IRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_DPLL_IRQ_EN_TAXI_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_EN_TAXI_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_EN_TAXI_IRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_EN_TAXI_IRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_IRQ_EN_SISI_IRQ_EN_MASK (0x10U) #define GTM_gtm_cls0_DPLL_IRQ_EN_SISI_IRQ_EN_SHIFT (4U) #define GTM_gtm_cls0_DPLL_IRQ_EN_SISI_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_EN_SISI_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_EN_SISI_IRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_EN_SISI_IRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_IRQ_EN_TISI_IRQ_EN_MASK (0x20U) #define GTM_gtm_cls0_DPLL_IRQ_EN_TISI_IRQ_EN_SHIFT (5U) #define GTM_gtm_cls0_DPLL_IRQ_EN_TISI_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_EN_TISI_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_EN_TISI_IRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_EN_TISI_IRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_IRQ_EN_MSI_IRQ_EN_MASK (0x40U) #define GTM_gtm_cls0_DPLL_IRQ_EN_MSI_IRQ_EN_SHIFT (6U) #define GTM_gtm_cls0_DPLL_IRQ_EN_MSI_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_EN_MSI_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_EN_MSI_IRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_EN_MSI_IRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_IRQ_EN_MTI_IRQ_EN_MASK (0x80U) #define GTM_gtm_cls0_DPLL_IRQ_EN_MTI_IRQ_EN_SHIFT (7U) #define GTM_gtm_cls0_DPLL_IRQ_EN_MTI_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_EN_MTI_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_EN_MTI_IRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_EN_MTI_IRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_IRQ_EN_SASI_IRQ_EN_MASK (0x100U) #define GTM_gtm_cls0_DPLL_IRQ_EN_SASI_IRQ_EN_SHIFT (8U) #define GTM_gtm_cls0_DPLL_IRQ_EN_SASI_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_EN_SASI_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_EN_SASI_IRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_EN_SASI_IRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_IRQ_EN_TASI_IRQ_EN_MASK (0x200U) #define GTM_gtm_cls0_DPLL_IRQ_EN_TASI_IRQ_EN_SHIFT (9U) #define GTM_gtm_cls0_DPLL_IRQ_EN_TASI_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_EN_TASI_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_EN_TASI_IRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_EN_TASI_IRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_IRQ_EN_PWI_IRQ_EN_MASK (0x400U) #define GTM_gtm_cls0_DPLL_IRQ_EN_PWI_IRQ_EN_SHIFT (10U) #define GTM_gtm_cls0_DPLL_IRQ_EN_PWI_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_EN_PWI_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_EN_PWI_IRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_EN_PWI_IRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_IRQ_EN_W2I_IRQ_EN_MASK (0x800U) #define GTM_gtm_cls0_DPLL_IRQ_EN_W2I_IRQ_EN_SHIFT (11U) #define GTM_gtm_cls0_DPLL_IRQ_EN_W2I_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_EN_W2I_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_EN_W2I_IRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_EN_W2I_IRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_IRQ_EN_W1I_IRQ_EN_MASK (0x1000U) #define GTM_gtm_cls0_DPLL_IRQ_EN_W1I_IRQ_EN_SHIFT (12U) #define GTM_gtm_cls0_DPLL_IRQ_EN_W1I_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_EN_W1I_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_EN_W1I_IRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_EN_W1I_IRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_IRQ_EN_GL1I_IRQ_EN_MASK (0x2000U) #define GTM_gtm_cls0_DPLL_IRQ_EN_GL1I_IRQ_EN_SHIFT (13U) #define GTM_gtm_cls0_DPLL_IRQ_EN_GL1I_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_EN_GL1I_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_EN_GL1I_IRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_EN_GL1I_IRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_IRQ_EN_LL1I_IRQ_EN_MASK (0x4000U) #define GTM_gtm_cls0_DPLL_IRQ_EN_LL1I_IRQ_EN_SHIFT (14U) #define GTM_gtm_cls0_DPLL_IRQ_EN_LL1I_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_EN_LL1I_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_EN_LL1I_IRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_EN_LL1I_IRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_IRQ_EN_EI_IRQ_EN_MASK (0x8000U) #define GTM_gtm_cls0_DPLL_IRQ_EN_EI_IRQ_EN_SHIFT (15U) #define GTM_gtm_cls0_DPLL_IRQ_EN_EI_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_EN_EI_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_EN_EI_IRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_EN_EI_IRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_IRQ_EN_GL2I_IRQ_EN_MASK (0x10000U) #define GTM_gtm_cls0_DPLL_IRQ_EN_GL2I_IRQ_EN_SHIFT (16U) #define GTM_gtm_cls0_DPLL_IRQ_EN_GL2I_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_EN_GL2I_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_EN_GL2I_IRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_EN_GL2I_IRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_IRQ_EN_LL2I_IRQ_EN_MASK (0x20000U) #define GTM_gtm_cls0_DPLL_IRQ_EN_LL2I_IRQ_EN_SHIFT (17U) #define GTM_gtm_cls0_DPLL_IRQ_EN_LL2I_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_EN_LL2I_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_EN_LL2I_IRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_EN_LL2I_IRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_IRQ_EN_TE0I_IRQ_EN_MASK (0x40000U) #define GTM_gtm_cls0_DPLL_IRQ_EN_TE0I_IRQ_EN_SHIFT (18U) #define GTM_gtm_cls0_DPLL_IRQ_EN_TE0I_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_EN_TE0I_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_EN_TE0I_IRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_EN_TE0I_IRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_IRQ_EN_TE1I_IRQ_EN_MASK (0x80000U) #define GTM_gtm_cls0_DPLL_IRQ_EN_TE1I_IRQ_EN_SHIFT (19U) #define GTM_gtm_cls0_DPLL_IRQ_EN_TE1I_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_EN_TE1I_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_EN_TE1I_IRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_EN_TE1I_IRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_IRQ_EN_TE2I_IRQ_EN_MASK (0x100000U) #define GTM_gtm_cls0_DPLL_IRQ_EN_TE2I_IRQ_EN_SHIFT (20U) #define GTM_gtm_cls0_DPLL_IRQ_EN_TE2I_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_EN_TE2I_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_EN_TE2I_IRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_EN_TE2I_IRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_IRQ_EN_TE3I_IRQ_EN_MASK (0x200000U) #define GTM_gtm_cls0_DPLL_IRQ_EN_TE3I_IRQ_EN_SHIFT (21U) #define GTM_gtm_cls0_DPLL_IRQ_EN_TE3I_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_EN_TE3I_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_EN_TE3I_IRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_EN_TE3I_IRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_IRQ_EN_TE4I_IRQ_EN_MASK (0x400000U) #define GTM_gtm_cls0_DPLL_IRQ_EN_TE4I_IRQ_EN_SHIFT (22U) #define GTM_gtm_cls0_DPLL_IRQ_EN_TE4I_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_EN_TE4I_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_EN_TE4I_IRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_EN_TE4I_IRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_IRQ_EN_CDTI_IRQ_EN_MASK (0x800000U) #define GTM_gtm_cls0_DPLL_IRQ_EN_CDTI_IRQ_EN_SHIFT (23U) #define GTM_gtm_cls0_DPLL_IRQ_EN_CDTI_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_EN_CDTI_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_EN_CDTI_IRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_EN_CDTI_IRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_IRQ_EN_CDSI_IRQ_EN_MASK (0x1000000U) #define GTM_gtm_cls0_DPLL_IRQ_EN_CDSI_IRQ_EN_SHIFT (24U) #define GTM_gtm_cls0_DPLL_IRQ_EN_CDSI_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_EN_CDSI_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_EN_CDSI_IRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_EN_CDSI_IRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_IRQ_EN_TORI_IRQ_EN_MASK (0x2000000U) #define GTM_gtm_cls0_DPLL_IRQ_EN_TORI_IRQ_EN_SHIFT (25U) #define GTM_gtm_cls0_DPLL_IRQ_EN_TORI_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_EN_TORI_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_EN_TORI_IRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_EN_TORI_IRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_IRQ_EN_SORI_IRQ_EN_MASK (0x4000000U) #define GTM_gtm_cls0_DPLL_IRQ_EN_SORI_IRQ_EN_SHIFT (26U) #define GTM_gtm_cls0_DPLL_IRQ_EN_SORI_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_EN_SORI_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_EN_SORI_IRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_EN_SORI_IRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_IRQ_EN_DCGI_IRQ_EN_MASK (0x8000000U) #define GTM_gtm_cls0_DPLL_IRQ_EN_DCGI_IRQ_EN_SHIFT (27U) #define GTM_gtm_cls0_DPLL_IRQ_EN_DCGI_IRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_EN_DCGI_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_EN_DCGI_IRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_EN_DCGI_IRQ_EN_MASK) /*! @} */ /*! @name DPLL_IRQ_FORCINT - Force Interrupt Register */ /*! @{ */ #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_PDI_MASK (0x1U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_PDI_SHIFT (0U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_PDI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_PDI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_PDI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_PDI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_PEI_MASK (0x2U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_PEI_SHIFT (1U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_PEI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_PEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_PEI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_PEI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TINI_MASK (0x4U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TINI_SHIFT (2U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TINI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TINI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TINI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TINI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TAXI_MASK (0x8U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TAXI_SHIFT (3U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TAXI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TAXI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TAXI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TAXI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_SISI_MASK (0x10U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_SISI_SHIFT (4U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_SISI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_SISI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_SISI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_SISI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TISI_MASK (0x20U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TISI_SHIFT (5U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TISI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TISI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TISI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TISI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_MSI_MASK (0x40U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_MSI_SHIFT (6U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_MSI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_MSI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_MSI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_MSI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_MTI_MASK (0x80U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_MTI_SHIFT (7U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_MTI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_MTI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_MTI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_MTI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_SASI_MASK (0x100U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_SASI_SHIFT (8U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_SASI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_SASI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_SASI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_SASI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TASI_MASK (0x200U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TASI_SHIFT (9U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TASI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TASI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TASI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TASI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_PWI_MASK (0x400U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_PWI_SHIFT (10U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_PWI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_PWI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_PWI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_PWI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_W2I_MASK (0x800U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_W2I_SHIFT (11U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_W2I_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_W2I(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_W2I_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_W2I_MASK) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_W1I_MASK (0x1000U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_W1I_SHIFT (12U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_W1I_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_W1I(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_W1I_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_W1I_MASK) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_GL1I_MASK (0x2000U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_GL1I_SHIFT (13U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_GL1I_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_GL1I(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_GL1I_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_GL1I_MASK) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_LL1I_MASK (0x4000U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_LL1I_SHIFT (14U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_LL1I_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_LL1I(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_LL1I_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_LL1I_MASK) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_EI_MASK (0x8000U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_EI_SHIFT (15U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_EI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_EI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_EI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_EI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_GL2I_MASK (0x10000U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_GL2I_SHIFT (16U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_GL2I_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_GL2I(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_GL2I_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_GL2I_MASK) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_LL2I_MASK (0x20000U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_LL2I_SHIFT (17U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_LL2I_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_LL2I(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_LL2I_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_LL2I_MASK) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TE0I_MASK (0x40000U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TE0I_SHIFT (18U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TE0I_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TE0I(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TE0I_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TE0I_MASK) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TE1I_MASK (0x80000U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TE1I_SHIFT (19U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TE1I_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TE1I(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TE1I_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TE1I_MASK) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TE2I_MASK (0x100000U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TE2I_SHIFT (20U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TE2I_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TE2I(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TE2I_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TE2I_MASK) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TE3I_MASK (0x200000U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TE3I_SHIFT (21U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TE3I_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TE3I(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TE3I_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TE3I_MASK) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TE4I_MASK (0x400000U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TE4I_SHIFT (22U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TE4I_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TE4I(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TE4I_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TE4I_MASK) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_CDTI_MASK (0x800000U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_CDTI_SHIFT (23U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_CDTI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_CDTI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_CDTI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_CDTI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_CDSI_MASK (0x1000000U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_CDSI_SHIFT (24U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_CDSI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_CDSI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_CDSI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_CDSI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TORI_MASK (0x2000000U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TORI_SHIFT (25U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TORI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TORI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TORI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_TORI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_SORI_MASK (0x4000000U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_SORI_SHIFT (26U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_SORI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_SORI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_SORI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_SORI_MASK) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_DCGI_MASK (0x8000000U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_DCGI_SHIFT (27U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_DCGI_WIDTH (1U) #define GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_DCGI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_DCGI_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_FORCINT_TRG_DCGI_MASK) /*! @} */ /*! @name DPLL_IRQ_MODE - Interrupt Request Mode */ /*! @{ */ #define GTM_gtm_cls0_DPLL_IRQ_MODE_IRQ_MODE_MASK (0x3U) #define GTM_gtm_cls0_DPLL_IRQ_MODE_IRQ_MODE_SHIFT (0U) #define GTM_gtm_cls0_DPLL_IRQ_MODE_IRQ_MODE_WIDTH (2U) #define GTM_gtm_cls0_DPLL_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls0_DPLL_IRQ_MODE_IRQ_MODE_MASK) /*! @} */ /*! @name DPLL_EIRQ_EN - Error Interrupt Enable Register */ /*! @{ */ #define GTM_gtm_cls0_DPLL_EIRQ_EN_PDI_EIRQ_EN_MASK (0x1U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_PDI_EIRQ_EN_SHIFT (0U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_PDI_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_PDI_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_EIRQ_EN_PDI_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_EIRQ_EN_PDI_EIRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_EIRQ_EN_PEI_EIRQ_EN_MASK (0x2U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_PEI_EIRQ_EN_SHIFT (1U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_PEI_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_PEI_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_EIRQ_EN_PEI_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_EIRQ_EN_PEI_EIRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TINI_EIRQ_EN_MASK (0x4U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TINI_EIRQ_EN_SHIFT (2U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TINI_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TINI_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_EIRQ_EN_TINI_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_EIRQ_EN_TINI_EIRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TAXI_EIRQ_EN_MASK (0x8U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TAXI_EIRQ_EN_SHIFT (3U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TAXI_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TAXI_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_EIRQ_EN_TAXI_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_EIRQ_EN_TAXI_EIRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_EIRQ_EN_SISI_EIRQ_EN_MASK (0x10U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_SISI_EIRQ_EN_SHIFT (4U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_SISI_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_SISI_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_EIRQ_EN_SISI_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_EIRQ_EN_SISI_EIRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TISI_EIRQ_EN_MASK (0x20U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TISI_EIRQ_EN_SHIFT (5U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TISI_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TISI_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_EIRQ_EN_TISI_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_EIRQ_EN_TISI_EIRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_EIRQ_EN_MSI_EIRQ_EN_MASK (0x40U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_MSI_EIRQ_EN_SHIFT (6U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_MSI_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_MSI_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_EIRQ_EN_MSI_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_EIRQ_EN_MSI_EIRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_EIRQ_EN_MTI_EIRQ_EN_MASK (0x80U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_MTI_EIRQ_EN_SHIFT (7U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_MTI_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_MTI_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_EIRQ_EN_MTI_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_EIRQ_EN_MTI_EIRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_EIRQ_EN_SASI_EIRQ_EN_MASK (0x100U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_SASI_EIRQ_EN_SHIFT (8U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_SASI_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_SASI_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_EIRQ_EN_SASI_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_EIRQ_EN_SASI_EIRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TASI_EIRQ_EN_MASK (0x200U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TASI_EIRQ_EN_SHIFT (9U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TASI_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TASI_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_EIRQ_EN_TASI_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_EIRQ_EN_TASI_EIRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_EIRQ_EN_PWI_EIRQ_EN_MASK (0x400U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_PWI_EIRQ_EN_SHIFT (10U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_PWI_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_PWI_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_EIRQ_EN_PWI_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_EIRQ_EN_PWI_EIRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_EIRQ_EN_W2I_EIRQ_EN_MASK (0x800U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_W2I_EIRQ_EN_SHIFT (11U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_W2I_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_W2I_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_EIRQ_EN_W2I_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_EIRQ_EN_W2I_EIRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_EIRQ_EN_W1I_EIRQ_EN_MASK (0x1000U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_W1I_EIRQ_EN_SHIFT (12U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_W1I_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_W1I_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_EIRQ_EN_W1I_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_EIRQ_EN_W1I_EIRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_EIRQ_EN_GL1I_EIRQ_EN_MASK (0x2000U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_GL1I_EIRQ_EN_SHIFT (13U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_GL1I_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_GL1I_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_EIRQ_EN_GL1I_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_EIRQ_EN_GL1I_EIRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_EIRQ_EN_LL1I_EIRQ_EN_MASK (0x4000U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_LL1I_EIRQ_EN_SHIFT (14U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_LL1I_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_LL1I_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_EIRQ_EN_LL1I_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_EIRQ_EN_LL1I_EIRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_EIRQ_EN_EI_EIRQ_EN_MASK (0x8000U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_EI_EIRQ_EN_SHIFT (15U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_EI_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_EI_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_EIRQ_EN_EI_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_EIRQ_EN_EI_EIRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_EIRQ_EN_GL2I_EIRQ_EN_MASK (0x10000U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_GL2I_EIRQ_EN_SHIFT (16U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_GL2I_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_GL2I_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_EIRQ_EN_GL2I_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_EIRQ_EN_GL2I_EIRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_EIRQ_EN_LL2I_EIRQ_EN_MASK (0x20000U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_LL2I_EIRQ_EN_SHIFT (17U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_LL2I_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_LL2I_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_EIRQ_EN_LL2I_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_EIRQ_EN_LL2I_EIRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TE0I_EIRQ_EN_MASK (0x40000U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TE0I_EIRQ_EN_SHIFT (18U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TE0I_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TE0I_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_EIRQ_EN_TE0I_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_EIRQ_EN_TE0I_EIRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TE1I_EIRQ_EN_MASK (0x80000U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TE1I_EIRQ_EN_SHIFT (19U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TE1I_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TE1I_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_EIRQ_EN_TE1I_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_EIRQ_EN_TE1I_EIRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TE2I_EIRQ_EN_MASK (0x100000U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TE2I_EIRQ_EN_SHIFT (20U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TE2I_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TE2I_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_EIRQ_EN_TE2I_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_EIRQ_EN_TE2I_EIRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TE3I_EIRQ_EN_MASK (0x200000U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TE3I_EIRQ_EN_SHIFT (21U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TE3I_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TE3I_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_EIRQ_EN_TE3I_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_EIRQ_EN_TE3I_EIRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TE4I_EIRQ_EN_MASK (0x400000U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TE4I_EIRQ_EN_SHIFT (22U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TE4I_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TE4I_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_EIRQ_EN_TE4I_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_EIRQ_EN_TE4I_EIRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_EIRQ_EN_CDTI_EIRQ_EN_MASK (0x800000U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_CDTI_EIRQ_EN_SHIFT (23U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_CDTI_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_CDTI_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_EIRQ_EN_CDTI_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_EIRQ_EN_CDTI_EIRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_EIRQ_EN_CDSI_EIRQ_EN_MASK (0x1000000U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_CDSI_EIRQ_EN_SHIFT (24U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_CDSI_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_CDSI_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_EIRQ_EN_CDSI_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_EIRQ_EN_CDSI_EIRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TORI_EIRQ_EN_MASK (0x2000000U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TORI_EIRQ_EN_SHIFT (25U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TORI_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_TORI_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_EIRQ_EN_TORI_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_EIRQ_EN_TORI_EIRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_EIRQ_EN_SORI_EIRQ_EN_MASK (0x4000000U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_SORI_EIRQ_EN_SHIFT (26U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_SORI_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_SORI_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_EIRQ_EN_SORI_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_EIRQ_EN_SORI_EIRQ_EN_MASK) #define GTM_gtm_cls0_DPLL_EIRQ_EN_DCGI_EIRQ_EN_MASK (0x8000000U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_DCGI_EIRQ_EN_SHIFT (27U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_DCGI_EIRQ_EN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_EIRQ_EN_DCGI_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_EIRQ_EN_DCGI_EIRQ_EN_SHIFT)) & GTM_gtm_cls0_DPLL_EIRQ_EN_DCGI_EIRQ_EN_MASK) /*! @} */ /*! @name DPLL_INC_CNT1 - Counter Value of Sent SUB_INC1 Pulses */ /*! @{ */ #define GTM_gtm_cls0_DPLL_INC_CNT1_INC_CNT1_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_INC_CNT1_INC_CNT1_SHIFT (0U) #define GTM_gtm_cls0_DPLL_INC_CNT1_INC_CNT1_WIDTH (24U) #define GTM_gtm_cls0_DPLL_INC_CNT1_INC_CNT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_INC_CNT1_INC_CNT1_SHIFT)) & GTM_gtm_cls0_DPLL_INC_CNT1_INC_CNT1_MASK) /*! @} */ /*! @name DPLL_INC_CNT2 - Counter Value of sent SUB_INC2 values (for DPLL_CTRL_1.SMC=1 and DPLL_CTRL_0.RMO=1) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_INC_CNT2_INC_CNT2_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_INC_CNT2_INC_CNT2_SHIFT (0U) #define GTM_gtm_cls0_DPLL_INC_CNT2_INC_CNT2_WIDTH (24U) #define GTM_gtm_cls0_DPLL_INC_CNT2_INC_CNT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_INC_CNT2_INC_CNT2_SHIFT)) & GTM_gtm_cls0_DPLL_INC_CNT2_INC_CNT2_MASK) /*! @} */ /*! @name DPLL_APT_SYNC - TRIGGER Time Stamp Field Offset at Synchronization Time */ /*! @{ */ #define GTM_gtm_cls0_DPLL_APT_SYNC_APT_2B_EXT_MASK (0x3FU) #define GTM_gtm_cls0_DPLL_APT_SYNC_APT_2B_EXT_SHIFT (0U) #define GTM_gtm_cls0_DPLL_APT_SYNC_APT_2B_EXT_WIDTH (6U) #define GTM_gtm_cls0_DPLL_APT_SYNC_APT_2B_EXT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_APT_SYNC_APT_2B_EXT_SHIFT)) & GTM_gtm_cls0_DPLL_APT_SYNC_APT_2B_EXT_MASK) #define GTM_gtm_cls0_DPLL_APT_SYNC_APT_2B_STATUS_MASK (0x40U) #define GTM_gtm_cls0_DPLL_APT_SYNC_APT_2B_STATUS_SHIFT (6U) #define GTM_gtm_cls0_DPLL_APT_SYNC_APT_2B_STATUS_WIDTH (1U) #define GTM_gtm_cls0_DPLL_APT_SYNC_APT_2B_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_APT_SYNC_APT_2B_STATUS_SHIFT)) & GTM_gtm_cls0_DPLL_APT_SYNC_APT_2B_STATUS_MASK) #define GTM_gtm_cls0_DPLL_APT_SYNC_APT_2B_OLD_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_APT_SYNC_APT_2B_OLD_SHIFT (14U) #define GTM_gtm_cls0_DPLL_APT_SYNC_APT_2B_OLD_WIDTH (10U) #define GTM_gtm_cls0_DPLL_APT_SYNC_APT_2B_OLD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_APT_SYNC_APT_2B_OLD_SHIFT)) & GTM_gtm_cls0_DPLL_APT_SYNC_APT_2B_OLD_MASK) /*! @} */ /*! @name DPLL_APS_SYNC - STATE Time Stamp Field Offset at Synchronization Time */ /*! @{ */ #define GTM_gtm_cls0_DPLL_APS_SYNC_APS_1C2_EXT_MASK (0x3FU) #define GTM_gtm_cls0_DPLL_APS_SYNC_APS_1C2_EXT_SHIFT (0U) #define GTM_gtm_cls0_DPLL_APS_SYNC_APS_1C2_EXT_WIDTH (6U) #define GTM_gtm_cls0_DPLL_APS_SYNC_APS_1C2_EXT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_APS_SYNC_APS_1C2_EXT_SHIFT)) & GTM_gtm_cls0_DPLL_APS_SYNC_APS_1C2_EXT_MASK) #define GTM_gtm_cls0_DPLL_APS_SYNC_APS_1C2_STATUS_MASK (0x40U) #define GTM_gtm_cls0_DPLL_APS_SYNC_APS_1C2_STATUS_SHIFT (6U) #define GTM_gtm_cls0_DPLL_APS_SYNC_APS_1C2_STATUS_WIDTH (1U) #define GTM_gtm_cls0_DPLL_APS_SYNC_APS_1C2_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_APS_SYNC_APS_1C2_STATUS_SHIFT)) & GTM_gtm_cls0_DPLL_APS_SYNC_APS_1C2_STATUS_MASK) #define GTM_gtm_cls0_DPLL_APS_SYNC_APS_1C2_OLD_MASK (0xFC000U) #define GTM_gtm_cls0_DPLL_APS_SYNC_APS_1C2_OLD_SHIFT (14U) #define GTM_gtm_cls0_DPLL_APS_SYNC_APS_1C2_OLD_WIDTH (6U) #define GTM_gtm_cls0_DPLL_APS_SYNC_APS_1C2_OLD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_APS_SYNC_APS_1C2_OLD_SHIFT)) & GTM_gtm_cls0_DPLL_APS_SYNC_APS_1C2_OLD_MASK) /*! @} */ /*! @name DPLL_TBU_TS0_T - Time Stamp Value for the last active TRIGGER */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TBU_TS0_T_DPLL_TBU_TS0_T_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TBU_TS0_T_DPLL_TBU_TS0_T_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TBU_TS0_T_DPLL_TBU_TS0_T_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TBU_TS0_T_DPLL_TBU_TS0_T(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TBU_TS0_T_DPLL_TBU_TS0_T_SHIFT)) & GTM_gtm_cls0_DPLL_TBU_TS0_T_DPLL_TBU_TS0_T_MASK) /*! @} */ /*! @name DPLL_TBU_TS0_S - Time Stamp Value for the last active STATE */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TBU_TS0_S_DPLL_TBU_TS0_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TBU_TS0_S_DPLL_TBU_TS0_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TBU_TS0_S_DPLL_TBU_TS0_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TBU_TS0_S_DPLL_TBU_TS0_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TBU_TS0_S_DPLL_TBU_TS0_S_SHIFT)) & GTM_gtm_cls0_DPLL_TBU_TS0_S_DPLL_TBU_TS0_S_MASK) /*! @} */ /*! @name DPLL_ADD_IN_LD1 - ADD_IN Value in Direct Load Mode for TRIGGER */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADD_IN_LD1_ADD_IN_LD1_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_ADD_IN_LD1_ADD_IN_LD1_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADD_IN_LD1_ADD_IN_LD1_WIDTH (24U) #define GTM_gtm_cls0_DPLL_ADD_IN_LD1_ADD_IN_LD1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADD_IN_LD1_ADD_IN_LD1_SHIFT)) & GTM_gtm_cls0_DPLL_ADD_IN_LD1_ADD_IN_LD1_MASK) /*! @} */ /*! @name DPLL_ADD_IN_LD2 - ADD_IN Value in Direct Load Mode for STATE */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADD_IN_LD2_ADD_IN_LD2_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_ADD_IN_LD2_ADD_IN_LD2_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADD_IN_LD2_ADD_IN_LD2_WIDTH (24U) #define GTM_gtm_cls0_DPLL_ADD_IN_LD2_ADD_IN_LD2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADD_IN_LD2_ADD_IN_LD2_SHIFT)) & GTM_gtm_cls0_DPLL_ADD_IN_LD2_ADD_IN_LD2_MASK) /*! @} */ /*! @name DPLL_STATUS - Status Register */ /*! @{ */ #define GTM_gtm_cls0_DPLL_STATUS_FPCE_MASK (0x1U) #define GTM_gtm_cls0_DPLL_STATUS_FPCE_SHIFT (0U) #define GTM_gtm_cls0_DPLL_STATUS_FPCE_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STATUS_FPCE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STATUS_FPCE_SHIFT)) & GTM_gtm_cls0_DPLL_STATUS_FPCE_MASK) #define GTM_gtm_cls0_DPLL_STATUS_CSO_MASK (0x2U) #define GTM_gtm_cls0_DPLL_STATUS_CSO_SHIFT (1U) #define GTM_gtm_cls0_DPLL_STATUS_CSO_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STATUS_CSO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STATUS_CSO_SHIFT)) & GTM_gtm_cls0_DPLL_STATUS_CSO_MASK) #define GTM_gtm_cls0_DPLL_STATUS_CTO_MASK (0x8U) #define GTM_gtm_cls0_DPLL_STATUS_CTO_SHIFT (3U) #define GTM_gtm_cls0_DPLL_STATUS_CTO_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STATUS_CTO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STATUS_CTO_SHIFT)) & GTM_gtm_cls0_DPLL_STATUS_CTO_MASK) #define GTM_gtm_cls0_DPLL_STATUS_CRO_MASK (0x10U) #define GTM_gtm_cls0_DPLL_STATUS_CRO_SHIFT (4U) #define GTM_gtm_cls0_DPLL_STATUS_CRO_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STATUS_CRO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STATUS_CRO_SHIFT)) & GTM_gtm_cls0_DPLL_STATUS_CRO_MASK) #define GTM_gtm_cls0_DPLL_STATUS_RCS_MASK (0x20U) #define GTM_gtm_cls0_DPLL_STATUS_RCS_SHIFT (5U) #define GTM_gtm_cls0_DPLL_STATUS_RCS_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STATUS_RCS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STATUS_RCS_SHIFT)) & GTM_gtm_cls0_DPLL_STATUS_RCS_MASK) #define GTM_gtm_cls0_DPLL_STATUS_RCT_MASK (0x40U) #define GTM_gtm_cls0_DPLL_STATUS_RCT_SHIFT (6U) #define GTM_gtm_cls0_DPLL_STATUS_RCT_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STATUS_RCT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STATUS_RCT_SHIFT)) & GTM_gtm_cls0_DPLL_STATUS_RCT_MASK) #define GTM_gtm_cls0_DPLL_STATUS_PSE_MASK (0x80U) #define GTM_gtm_cls0_DPLL_STATUS_PSE_SHIFT (7U) #define GTM_gtm_cls0_DPLL_STATUS_PSE_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STATUS_PSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STATUS_PSE_SHIFT)) & GTM_gtm_cls0_DPLL_STATUS_PSE_MASK) #define GTM_gtm_cls0_DPLL_STATUS_SOR_MASK (0x100U) #define GTM_gtm_cls0_DPLL_STATUS_SOR_SHIFT (8U) #define GTM_gtm_cls0_DPLL_STATUS_SOR_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STATUS_SOR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STATUS_SOR_SHIFT)) & GTM_gtm_cls0_DPLL_STATUS_SOR_MASK) #define GTM_gtm_cls0_DPLL_STATUS_MS_MASK (0x200U) #define GTM_gtm_cls0_DPLL_STATUS_MS_SHIFT (9U) #define GTM_gtm_cls0_DPLL_STATUS_MS_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STATUS_MS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STATUS_MS_SHIFT)) & GTM_gtm_cls0_DPLL_STATUS_MS_MASK) #define GTM_gtm_cls0_DPLL_STATUS_TOR_MASK (0x400U) #define GTM_gtm_cls0_DPLL_STATUS_TOR_SHIFT (10U) #define GTM_gtm_cls0_DPLL_STATUS_TOR_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STATUS_TOR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STATUS_TOR_SHIFT)) & GTM_gtm_cls0_DPLL_STATUS_TOR_MASK) #define GTM_gtm_cls0_DPLL_STATUS_MT_MASK (0x800U) #define GTM_gtm_cls0_DPLL_STATUS_MT_SHIFT (11U) #define GTM_gtm_cls0_DPLL_STATUS_MT_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STATUS_MT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STATUS_MT_SHIFT)) & GTM_gtm_cls0_DPLL_STATUS_MT_MASK) #define GTM_gtm_cls0_DPLL_STATUS_RAM2_ERR_MASK (0x1000U) #define GTM_gtm_cls0_DPLL_STATUS_RAM2_ERR_SHIFT (12U) #define GTM_gtm_cls0_DPLL_STATUS_RAM2_ERR_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STATUS_RAM2_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STATUS_RAM2_ERR_SHIFT)) & GTM_gtm_cls0_DPLL_STATUS_RAM2_ERR_MASK) #define GTM_gtm_cls0_DPLL_STATUS_LOW_RES_MASK (0x8000U) #define GTM_gtm_cls0_DPLL_STATUS_LOW_RES_SHIFT (15U) #define GTM_gtm_cls0_DPLL_STATUS_LOW_RES_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STATUS_LOW_RES(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STATUS_LOW_RES_SHIFT)) & GTM_gtm_cls0_DPLL_STATUS_LOW_RES_MASK) #define GTM_gtm_cls0_DPLL_STATUS_CSVS_MASK (0x10000U) #define GTM_gtm_cls0_DPLL_STATUS_CSVS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_STATUS_CSVS_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STATUS_CSVS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STATUS_CSVS_SHIFT)) & GTM_gtm_cls0_DPLL_STATUS_CSVS_MASK) #define GTM_gtm_cls0_DPLL_STATUS_CSVT_MASK (0x20000U) #define GTM_gtm_cls0_DPLL_STATUS_CSVT_SHIFT (17U) #define GTM_gtm_cls0_DPLL_STATUS_CSVT_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STATUS_CSVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STATUS_CSVT_SHIFT)) & GTM_gtm_cls0_DPLL_STATUS_CSVT_MASK) #define GTM_gtm_cls0_DPLL_STATUS_CAIP2_MASK (0x40000U) #define GTM_gtm_cls0_DPLL_STATUS_CAIP2_SHIFT (18U) #define GTM_gtm_cls0_DPLL_STATUS_CAIP2_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STATUS_CAIP2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STATUS_CAIP2_SHIFT)) & GTM_gtm_cls0_DPLL_STATUS_CAIP2_MASK) #define GTM_gtm_cls0_DPLL_STATUS_CAIP1_MASK (0x80000U) #define GTM_gtm_cls0_DPLL_STATUS_CAIP1_SHIFT (19U) #define GTM_gtm_cls0_DPLL_STATUS_CAIP1_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STATUS_CAIP1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STATUS_CAIP1_SHIFT)) & GTM_gtm_cls0_DPLL_STATUS_CAIP1_MASK) #define GTM_gtm_cls0_DPLL_STATUS_ISN_MASK (0x100000U) #define GTM_gtm_cls0_DPLL_STATUS_ISN_SHIFT (20U) #define GTM_gtm_cls0_DPLL_STATUS_ISN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STATUS_ISN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STATUS_ISN_SHIFT)) & GTM_gtm_cls0_DPLL_STATUS_ISN_MASK) #define GTM_gtm_cls0_DPLL_STATUS_ITN_MASK (0x200000U) #define GTM_gtm_cls0_DPLL_STATUS_ITN_SHIFT (21U) #define GTM_gtm_cls0_DPLL_STATUS_ITN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STATUS_ITN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STATUS_ITN_SHIFT)) & GTM_gtm_cls0_DPLL_STATUS_ITN_MASK) #define GTM_gtm_cls0_DPLL_STATUS_BWD2_MASK (0x400000U) #define GTM_gtm_cls0_DPLL_STATUS_BWD2_SHIFT (22U) #define GTM_gtm_cls0_DPLL_STATUS_BWD2_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STATUS_BWD2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STATUS_BWD2_SHIFT)) & GTM_gtm_cls0_DPLL_STATUS_BWD2_MASK) #define GTM_gtm_cls0_DPLL_STATUS_BWD1_MASK (0x800000U) #define GTM_gtm_cls0_DPLL_STATUS_BWD1_SHIFT (23U) #define GTM_gtm_cls0_DPLL_STATUS_BWD1_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STATUS_BWD1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STATUS_BWD1_SHIFT)) & GTM_gtm_cls0_DPLL_STATUS_BWD1_MASK) #define GTM_gtm_cls0_DPLL_STATUS_LOCK2_MASK (0x2000000U) #define GTM_gtm_cls0_DPLL_STATUS_LOCK2_SHIFT (25U) #define GTM_gtm_cls0_DPLL_STATUS_LOCK2_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STATUS_LOCK2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STATUS_LOCK2_SHIFT)) & GTM_gtm_cls0_DPLL_STATUS_LOCK2_MASK) #define GTM_gtm_cls0_DPLL_STATUS_SYS_MASK (0x4000000U) #define GTM_gtm_cls0_DPLL_STATUS_SYS_SHIFT (26U) #define GTM_gtm_cls0_DPLL_STATUS_SYS_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STATUS_SYS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STATUS_SYS_SHIFT)) & GTM_gtm_cls0_DPLL_STATUS_SYS_MASK) #define GTM_gtm_cls0_DPLL_STATUS_SYT_MASK (0x8000000U) #define GTM_gtm_cls0_DPLL_STATUS_SYT_SHIFT (27U) #define GTM_gtm_cls0_DPLL_STATUS_SYT_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STATUS_SYT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STATUS_SYT_SHIFT)) & GTM_gtm_cls0_DPLL_STATUS_SYT_MASK) #define GTM_gtm_cls0_DPLL_STATUS_FSD_MASK (0x10000000U) #define GTM_gtm_cls0_DPLL_STATUS_FSD_SHIFT (28U) #define GTM_gtm_cls0_DPLL_STATUS_FSD_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STATUS_FSD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STATUS_FSD_SHIFT)) & GTM_gtm_cls0_DPLL_STATUS_FSD_MASK) #define GTM_gtm_cls0_DPLL_STATUS_FTD_MASK (0x20000000U) #define GTM_gtm_cls0_DPLL_STATUS_FTD_SHIFT (29U) #define GTM_gtm_cls0_DPLL_STATUS_FTD_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STATUS_FTD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STATUS_FTD_SHIFT)) & GTM_gtm_cls0_DPLL_STATUS_FTD_MASK) #define GTM_gtm_cls0_DPLL_STATUS_LOCK1_MASK (0x40000000U) #define GTM_gtm_cls0_DPLL_STATUS_LOCK1_SHIFT (30U) #define GTM_gtm_cls0_DPLL_STATUS_LOCK1_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STATUS_LOCK1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STATUS_LOCK1_SHIFT)) & GTM_gtm_cls0_DPLL_STATUS_LOCK1_MASK) #define GTM_gtm_cls0_DPLL_STATUS_ERR_MASK (0x80000000U) #define GTM_gtm_cls0_DPLL_STATUS_ERR_SHIFT (31U) #define GTM_gtm_cls0_DPLL_STATUS_ERR_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STATUS_ERR_SHIFT)) & GTM_gtm_cls0_DPLL_STATUS_ERR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_0 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_0_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_0_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_0_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_0_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_0_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_0_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_1 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_1_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_1_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_1_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_1_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_1_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_1_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_2 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_2_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_2_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_2_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_2_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_2_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_2_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_3 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_3_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_3_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_3_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_3_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_3_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_3_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_4 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_4_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_4_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_4_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_4_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_4_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_4_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_5 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_5_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_5_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_5_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_5_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_5_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_5_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_6 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_6_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_6_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_6_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_6_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_6_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_6_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_7 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_7_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_7_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_7_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_7_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_7_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_7_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_8 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_8_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_8_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_8_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_8_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_8_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_8_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_9 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_9_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_9_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_9_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_9_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_9_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_9_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_10 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_10_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_10_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_10_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_10_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_10_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_10_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_11 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_11_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_11_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_11_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_11_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_11_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_11_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_12 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_12_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_12_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_12_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_12_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_12_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_12_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_13 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_13_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_13_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_13_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_13_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_13_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_13_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_14 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_14_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_14_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_14_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_14_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_14_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_14_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_15 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_15_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_15_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_15_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_15_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_15_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_15_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_16 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_16_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_16_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_16_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_16_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_16_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_16_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_17 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_17_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_17_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_17_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_17_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_17_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_17_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_18 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_18_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_18_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_18_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_18_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_18_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_18_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_19 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_19_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_19_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_19_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_19_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_19_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_19_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_20 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_20_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_20_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_20_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_20_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_20_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_20_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_21 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_21_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_21_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_21_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_21_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_21_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_21_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_22 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_22_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_22_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_22_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_22_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_22_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_22_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_23 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_23_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_23_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_23_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_23_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_23_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_23_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_24 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_24_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_24_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_24_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_24_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_24_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_24_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_25 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_25_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_25_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_25_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_25_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_25_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_25_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_26 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_26_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_26_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_26_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_26_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_26_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_26_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_27 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_27_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_27_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_27_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_27_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_27_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_27_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_28 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_28_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_28_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_28_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_28_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_28_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_28_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_29 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_29_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_29_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_29_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_29_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_29_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_29_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_30 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_30_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_30_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_30_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_30_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_30_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_30_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_ID_PMTR_31 - ID Information for Input Signal PMTR[n] (Position minus Time Request) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ID_PMTR_31_ID_PMTR_MASK (0x1FFU) #define GTM_gtm_cls0_DPLL_ID_PMTR_31_ID_PMTR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ID_PMTR_31_ID_PMTR_WIDTH (9U) #define GTM_gtm_cls0_DPLL_ID_PMTR_31_ID_PMTR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ID_PMTR_31_ID_PMTR_SHIFT)) & GTM_gtm_cls0_DPLL_ID_PMTR_31_ID_PMTR_MASK) /*! @} */ /*! @name DPLL_CTRL_0_SHADOW_TRIGGER - Shadow Register of DPLL_CTRL_0 controlled by an active TRIGGER Slope */ /*! @{ */ #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_TRIGGER_MLT_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_TRIGGER_MLT_SHIFT (0U) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_TRIGGER_MLT_WIDTH (10U) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_TRIGGER_MLT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_TRIGGER_MLT_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_TRIGGER_MLT_MASK) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_TRIGGER_IFP_MASK (0x400U) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_TRIGGER_IFP_SHIFT (10U) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_TRIGGER_IFP_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_TRIGGER_IFP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_TRIGGER_IFP_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_TRIGGER_IFP_MASK) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_TRIGGER_AMT_MASK (0x4000000U) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_TRIGGER_AMT_SHIFT (26U) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_TRIGGER_AMT_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_TRIGGER_AMT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_TRIGGER_AMT_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_TRIGGER_AMT_MASK) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_TRIGGER_IDT_MASK (0x10000000U) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_TRIGGER_IDT_SHIFT (28U) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_TRIGGER_IDT_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_TRIGGER_IDT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_TRIGGER_IDT_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_TRIGGER_IDT_MASK) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_TRIGGER_RMO_MASK (0x80000000U) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_TRIGGER_RMO_SHIFT (31U) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_TRIGGER_RMO_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_TRIGGER_RMO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_TRIGGER_RMO_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_TRIGGER_RMO_MASK) /*! @} */ /*! @name DPLL_CTRL_0_SHADOW_STATE - Shadow Register of DPLL_CTRL_0 controlled by an active STATE Slope */ /*! @{ */ #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_STATE_IFP_MASK (0x400U) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_STATE_IFP_SHIFT (10U) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_STATE_IFP_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_STATE_IFP(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_STATE_IFP_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_STATE_IFP_MASK) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_STATE_AMS_MASK (0x2000000U) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_STATE_AMS_SHIFT (25U) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_STATE_AMS_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_STATE_AMS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_STATE_AMS_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_STATE_AMS_MASK) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_STATE_IDS_MASK (0x8000000U) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_STATE_IDS_SHIFT (27U) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_STATE_IDS_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_STATE_IDS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_STATE_IDS_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_STATE_IDS_MASK) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_STATE_RMO_MASK (0x80000000U) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_STATE_RMO_SHIFT (31U) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_STATE_RMO_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_STATE_RMO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_STATE_RMO_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_0_SHADOW_STATE_RMO_MASK) /*! @} */ /*! @name DPLL_CTRL_1_SHADOW_TRIGGER - Shadow Register of DPLL_CTRL_1 controlled by an active TRIGGER Slope */ /*! @{ */ #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_DMO_MASK (0x1U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_DMO_SHIFT (0U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_DMO_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_DMO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_DMO_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_DMO_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_COA_MASK (0x8U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_COA_SHIFT (3U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_COA_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_COA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_COA_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_COA_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_PIT_MASK (0x10U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_PIT_SHIFT (4U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_PIT_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_PIT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_PIT_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_PIT_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_SGE1_MASK (0x20U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_SGE1_SHIFT (5U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_SGE1_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_SGE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_SGE1_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_SGE1_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_DLM1_MASK (0x40U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_DLM1_SHIFT (6U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_DLM1_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_DLM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_DLM1_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_DLM1_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_PCM1_MASK (0x80U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_PCM1_SHIFT (7U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_PCM1_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_PCM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_PCM1_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_TRIGGER_PCM1_MASK) /*! @} */ /*! @name DPLL_CTRL_1_SHADOW_STATE - DPLL Shadow Register of DPLL_CTRL_1 controlled by an active STATE Slope */ /*! @{ */ #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_DMO_MASK (0x1U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_DMO_SHIFT (0U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_DMO_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_DMO(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_DMO_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_DMO_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_COA_MASK (0x8U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_COA_SHIFT (3U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_COA_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_COA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_COA_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_COA_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_SGE1_MASK (0x20U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_SGE1_SHIFT (5U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_SGE1_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_SGE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_SGE1_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_SGE1_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_DLM1_MASK (0x40U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_DLM1_SHIFT (6U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_DLM1_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_DLM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_DLM1_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_DLM1_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_PCM1_MASK (0x80U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_PCM1_SHIFT (7U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_PCM1_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_PCM1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_PCM1_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_PCM1_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_SGE2_MASK (0x100U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_SGE2_SHIFT (8U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_SGE2_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_SGE2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_SGE2_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_SGE2_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_DLM2_MASK (0x200U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_DLM2_SHIFT (9U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_DLM2_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_DLM2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_DLM2_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_DLM2_MASK) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_PCM2_MASK (0x400U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_PCM2_SHIFT (10U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_PCM2_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_PCM2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_PCM2_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_1_SHADOW_STATE_PCM2_MASK) /*! @} */ /*! @name DPLL_RAM_INI - Register to control the RAM Initialization */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM_INI_INIT_1A_MASK (0x1U) #define GTM_gtm_cls0_DPLL_RAM_INI_INIT_1A_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM_INI_INIT_1A_WIDTH (1U) #define GTM_gtm_cls0_DPLL_RAM_INI_INIT_1A(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM_INI_INIT_1A_SHIFT)) & GTM_gtm_cls0_DPLL_RAM_INI_INIT_1A_MASK) #define GTM_gtm_cls0_DPLL_RAM_INI_INIT_1BC_MASK (0x2U) #define GTM_gtm_cls0_DPLL_RAM_INI_INIT_1BC_SHIFT (1U) #define GTM_gtm_cls0_DPLL_RAM_INI_INIT_1BC_WIDTH (1U) #define GTM_gtm_cls0_DPLL_RAM_INI_INIT_1BC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM_INI_INIT_1BC_SHIFT)) & GTM_gtm_cls0_DPLL_RAM_INI_INIT_1BC_MASK) #define GTM_gtm_cls0_DPLL_RAM_INI_INIT_2_MASK (0x4U) #define GTM_gtm_cls0_DPLL_RAM_INI_INIT_2_SHIFT (2U) #define GTM_gtm_cls0_DPLL_RAM_INI_INIT_2_WIDTH (1U) #define GTM_gtm_cls0_DPLL_RAM_INI_INIT_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM_INI_INIT_2_SHIFT)) & GTM_gtm_cls0_DPLL_RAM_INI_INIT_2_MASK) #define GTM_gtm_cls0_DPLL_RAM_INI_INIT_RAM_MASK (0x10U) #define GTM_gtm_cls0_DPLL_RAM_INI_INIT_RAM_SHIFT (4U) #define GTM_gtm_cls0_DPLL_RAM_INI_INIT_RAM_WIDTH (1U) #define GTM_gtm_cls0_DPLL_RAM_INI_INIT_RAM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM_INI_INIT_RAM_SHIFT)) & GTM_gtm_cls0_DPLL_RAM_INI_INIT_RAM_MASK) /*! @} */ /*! @name DPLL_PSA0 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA0_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA0_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA0_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA0_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA0_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA0_PSA_MASK) /*! @} */ /*! @name DPLL_PSA1 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA1_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA1_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA1_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA1_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA1_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA1_PSA_MASK) /*! @} */ /*! @name DPLL_PSA2 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA2_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA2_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA2_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA2_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA2_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA2_PSA_MASK) /*! @} */ /*! @name DPLL_PSA3 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA3_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA3_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA3_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA3_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA3_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA3_PSA_MASK) /*! @} */ /*! @name DPLL_PSA4 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA4_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA4_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA4_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA4_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA4_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA4_PSA_MASK) /*! @} */ /*! @name DPLL_PSA5 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA5_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA5_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA5_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA5_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA5_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA5_PSA_MASK) /*! @} */ /*! @name DPLL_PSA6 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA6_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA6_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA6_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA6_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA6_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA6_PSA_MASK) /*! @} */ /*! @name DPLL_PSA7 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA7_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA7_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA7_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA7_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA7_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA7_PSA_MASK) /*! @} */ /*! @name DPLL_PSA8 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA8_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA8_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA8_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA8_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA8_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA8_PSA_MASK) /*! @} */ /*! @name DPLL_PSA9 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA9_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA9_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA9_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA9_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA9_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA9_PSA_MASK) /*! @} */ /*! @name DPLL_PSA10 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA10_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA10_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA10_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA10_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA10_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA10_PSA_MASK) /*! @} */ /*! @name DPLL_PSA11 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA11_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA11_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA11_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA11_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA11_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA11_PSA_MASK) /*! @} */ /*! @name DPLL_PSA12 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA12_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA12_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA12_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA12_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA12_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA12_PSA_MASK) /*! @} */ /*! @name DPLL_PSA13 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA13_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA13_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA13_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA13_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA13_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA13_PSA_MASK) /*! @} */ /*! @name DPLL_PSA14 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA14_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA14_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA14_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA14_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA14_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA14_PSA_MASK) /*! @} */ /*! @name DPLL_PSA15 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA15_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA15_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA15_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA15_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA15_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA15_PSA_MASK) /*! @} */ /*! @name DPLL_PSA16 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA16_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA16_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA16_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA16_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA16_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA16_PSA_MASK) /*! @} */ /*! @name DPLL_PSA17 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA17_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA17_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA17_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA17_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA17_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA17_PSA_MASK) /*! @} */ /*! @name DPLL_PSA18 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA18_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA18_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA18_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA18_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA18_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA18_PSA_MASK) /*! @} */ /*! @name DPLL_PSA19 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA19_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA19_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA19_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA19_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA19_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA19_PSA_MASK) /*! @} */ /*! @name DPLL_PSA20 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA20_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA20_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA20_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA20_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA20_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA20_PSA_MASK) /*! @} */ /*! @name DPLL_PSA21 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA21_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA21_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA21_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA21_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA21_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA21_PSA_MASK) /*! @} */ /*! @name DPLL_PSA22 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA22_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA22_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA22_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA22_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA22_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA22_PSA_MASK) /*! @} */ /*! @name DPLL_PSA23 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA23_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA23_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA23_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA23_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA23_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA23_PSA_MASK) /*! @} */ /*! @name DPLL_PSA24 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA24_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA24_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA24_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA24_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA24_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA24_PSA_MASK) /*! @} */ /*! @name DPLL_PSA25 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA25_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA25_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA25_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA25_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA25_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA25_PSA_MASK) /*! @} */ /*! @name DPLL_PSA26 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA26_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA26_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA26_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA26_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA26_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA26_PSA_MASK) /*! @} */ /*! @name DPLL_PSA27 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA27_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA27_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA27_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA27_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA27_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA27_PSA_MASK) /*! @} */ /*! @name DPLL_PSA28 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA28_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA28_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA28_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA28_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA28_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA28_PSA_MASK) /*! @} */ /*! @name DPLL_PSA29 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA29_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA29_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA29_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA29_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA29_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA29_PSA_MASK) /*! @} */ /*! @name DPLL_PSA30 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA30_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA30_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA30_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA30_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA30_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA30_PSA_MASK) /*! @} */ /*! @name DPLL_PSA31 - Position Request for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSA31_PSA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSA31_PSA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSA31_PSA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSA31_PSA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSA31_PSA_SHIFT)) & GTM_gtm_cls0_DPLL_PSA31_PSA_MASK) /*! @} */ /*! @name DPLL_DLA0 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA0_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA0_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA0_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA0_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA0_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA0_DLA_MASK) /*! @} */ /*! @name DPLL_DLA1 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA1_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA1_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA1_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA1_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA1_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA1_DLA_MASK) /*! @} */ /*! @name DPLL_DLA2 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA2_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA2_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA2_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA2_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA2_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA2_DLA_MASK) /*! @} */ /*! @name DPLL_DLA3 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA3_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA3_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA3_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA3_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA3_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA3_DLA_MASK) /*! @} */ /*! @name DPLL_DLA4 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA4_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA4_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA4_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA4_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA4_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA4_DLA_MASK) /*! @} */ /*! @name DPLL_DLA5 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA5_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA5_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA5_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA5_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA5_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA5_DLA_MASK) /*! @} */ /*! @name DPLL_DLA6 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA6_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA6_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA6_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA6_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA6_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA6_DLA_MASK) /*! @} */ /*! @name DPLL_DLA7 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA7_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA7_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA7_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA7_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA7_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA7_DLA_MASK) /*! @} */ /*! @name DPLL_DLA8 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA8_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA8_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA8_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA8_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA8_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA8_DLA_MASK) /*! @} */ /*! @name DPLL_DLA9 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA9_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA9_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA9_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA9_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA9_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA9_DLA_MASK) /*! @} */ /*! @name DPLL_DLA10 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA10_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA10_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA10_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA10_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA10_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA10_DLA_MASK) /*! @} */ /*! @name DPLL_DLA11 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA11_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA11_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA11_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA11_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA11_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA11_DLA_MASK) /*! @} */ /*! @name DPLL_DLA12 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA12_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA12_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA12_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA12_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA12_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA12_DLA_MASK) /*! @} */ /*! @name DPLL_DLA13 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA13_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA13_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA13_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA13_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA13_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA13_DLA_MASK) /*! @} */ /*! @name DPLL_DLA14 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA14_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA14_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA14_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA14_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA14_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA14_DLA_MASK) /*! @} */ /*! @name DPLL_DLA15 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA15_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA15_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA15_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA15_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA15_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA15_DLA_MASK) /*! @} */ /*! @name DPLL_DLA16 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA16_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA16_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA16_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA16_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA16_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA16_DLA_MASK) /*! @} */ /*! @name DPLL_DLA17 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA17_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA17_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA17_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA17_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA17_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA17_DLA_MASK) /*! @} */ /*! @name DPLL_DLA18 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA18_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA18_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA18_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA18_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA18_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA18_DLA_MASK) /*! @} */ /*! @name DPLL_DLA19 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA19_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA19_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA19_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA19_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA19_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA19_DLA_MASK) /*! @} */ /*! @name DPLL_DLA20 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA20_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA20_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA20_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA20_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA20_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA20_DLA_MASK) /*! @} */ /*! @name DPLL_DLA21 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA21_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA21_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA21_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA21_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA21_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA21_DLA_MASK) /*! @} */ /*! @name DPLL_DLA22 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA22_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA22_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA22_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA22_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA22_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA22_DLA_MASK) /*! @} */ /*! @name DPLL_DLA23 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA23_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA23_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA23_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA23_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA23_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA23_DLA_MASK) /*! @} */ /*! @name DPLL_DLA24 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA24_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA24_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA24_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA24_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA24_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA24_DLA_MASK) /*! @} */ /*! @name DPLL_DLA25 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA25_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA25_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA25_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA25_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA25_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA25_DLA_MASK) /*! @} */ /*! @name DPLL_DLA26 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA26_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA26_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA26_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA26_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA26_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA26_DLA_MASK) /*! @} */ /*! @name DPLL_DLA27 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA27_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA27_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA27_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA27_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA27_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA27_DLA_MASK) /*! @} */ /*! @name DPLL_DLA28 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA28_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA28_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA28_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA28_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA28_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA28_DLA_MASK) /*! @} */ /*! @name DPLL_DLA29 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA29_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA29_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA29_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA29_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA29_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA29_DLA_MASK) /*! @} */ /*! @name DPLL_DLA30 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA30_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA30_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA30_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA30_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA30_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA30_DLA_MASK) /*! @} */ /*! @name DPLL_DLA31 - Time to React for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DLA31_DLA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DLA31_DLA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DLA31_DLA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DLA31_DLA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DLA31_DLA_SHIFT)) & GTM_gtm_cls0_DPLL_DLA31_DLA_MASK) /*! @} */ /*! @name DPLL_NA0 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA0_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA0_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA0_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA0_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA0_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA0_DB_MASK) #define GTM_gtm_cls0_DPLL_NA0_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA0_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA0_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA0_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA0_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA0_DW_MASK) #define GTM_gtm_cls0_DPLL_NA0_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA0_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA0_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA0_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA0_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA0_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NA1 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA1_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA1_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA1_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA1_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA1_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA1_DB_MASK) #define GTM_gtm_cls0_DPLL_NA1_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA1_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA1_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA1_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA1_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA1_DW_MASK) #define GTM_gtm_cls0_DPLL_NA1_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA1_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA1_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA1_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA1_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA1_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NA2 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA2_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA2_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA2_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA2_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA2_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA2_DB_MASK) #define GTM_gtm_cls0_DPLL_NA2_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA2_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA2_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA2_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA2_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA2_DW_MASK) #define GTM_gtm_cls0_DPLL_NA2_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA2_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA2_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA2_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA2_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA2_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NA3 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA3_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA3_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA3_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA3_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA3_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA3_DB_MASK) #define GTM_gtm_cls0_DPLL_NA3_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA3_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA3_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA3_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA3_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA3_DW_MASK) #define GTM_gtm_cls0_DPLL_NA3_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA3_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA3_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA3_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA3_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA3_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NA4 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA4_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA4_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA4_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA4_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA4_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA4_DB_MASK) #define GTM_gtm_cls0_DPLL_NA4_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA4_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA4_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA4_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA4_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA4_DW_MASK) #define GTM_gtm_cls0_DPLL_NA4_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA4_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA4_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA4_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA4_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA4_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NA5 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA5_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA5_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA5_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA5_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA5_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA5_DB_MASK) #define GTM_gtm_cls0_DPLL_NA5_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA5_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA5_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA5_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA5_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA5_DW_MASK) #define GTM_gtm_cls0_DPLL_NA5_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA5_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA5_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA5_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA5_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA5_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NA6 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA6_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA6_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA6_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA6_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA6_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA6_DB_MASK) #define GTM_gtm_cls0_DPLL_NA6_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA6_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA6_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA6_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA6_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA6_DW_MASK) #define GTM_gtm_cls0_DPLL_NA6_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA6_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA6_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA6_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA6_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA6_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NA7 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA7_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA7_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA7_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA7_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA7_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA7_DB_MASK) #define GTM_gtm_cls0_DPLL_NA7_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA7_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA7_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA7_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA7_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA7_DW_MASK) #define GTM_gtm_cls0_DPLL_NA7_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA7_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA7_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA7_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA7_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA7_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NA8 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA8_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA8_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA8_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA8_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA8_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA8_DB_MASK) #define GTM_gtm_cls0_DPLL_NA8_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA8_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA8_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA8_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA8_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA8_DW_MASK) #define GTM_gtm_cls0_DPLL_NA8_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA8_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA8_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA8_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA8_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA8_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NA9 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA9_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA9_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA9_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA9_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA9_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA9_DB_MASK) #define GTM_gtm_cls0_DPLL_NA9_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA9_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA9_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA9_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA9_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA9_DW_MASK) #define GTM_gtm_cls0_DPLL_NA9_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA9_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA9_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA9_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA9_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA9_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NA10 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA10_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA10_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA10_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA10_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA10_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA10_DB_MASK) #define GTM_gtm_cls0_DPLL_NA10_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA10_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA10_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA10_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA10_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA10_DW_MASK) #define GTM_gtm_cls0_DPLL_NA10_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA10_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA10_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA10_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA10_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA10_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NA11 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA11_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA11_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA11_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA11_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA11_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA11_DB_MASK) #define GTM_gtm_cls0_DPLL_NA11_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA11_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA11_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA11_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA11_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA11_DW_MASK) #define GTM_gtm_cls0_DPLL_NA11_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA11_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA11_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA11_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA11_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA11_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NA12 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA12_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA12_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA12_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA12_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA12_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA12_DB_MASK) #define GTM_gtm_cls0_DPLL_NA12_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA12_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA12_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA12_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA12_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA12_DW_MASK) #define GTM_gtm_cls0_DPLL_NA12_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA12_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA12_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA12_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA12_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA12_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NA13 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA13_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA13_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA13_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA13_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA13_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA13_DB_MASK) #define GTM_gtm_cls0_DPLL_NA13_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA13_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA13_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA13_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA13_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA13_DW_MASK) #define GTM_gtm_cls0_DPLL_NA13_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA13_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA13_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA13_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA13_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA13_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NA14 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA14_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA14_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA14_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA14_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA14_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA14_DB_MASK) #define GTM_gtm_cls0_DPLL_NA14_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA14_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA14_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA14_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA14_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA14_DW_MASK) #define GTM_gtm_cls0_DPLL_NA14_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA14_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA14_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA14_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA14_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA14_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NA15 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA15_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA15_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA15_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA15_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA15_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA15_DB_MASK) #define GTM_gtm_cls0_DPLL_NA15_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA15_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA15_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA15_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA15_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA15_DW_MASK) #define GTM_gtm_cls0_DPLL_NA15_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA15_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA15_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA15_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA15_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA15_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NA16 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA16_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA16_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA16_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA16_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA16_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA16_DB_MASK) #define GTM_gtm_cls0_DPLL_NA16_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA16_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA16_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA16_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA16_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA16_DW_MASK) #define GTM_gtm_cls0_DPLL_NA16_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA16_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA16_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA16_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA16_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA16_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NA17 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA17_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA17_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA17_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA17_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA17_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA17_DB_MASK) #define GTM_gtm_cls0_DPLL_NA17_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA17_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA17_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA17_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA17_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA17_DW_MASK) #define GTM_gtm_cls0_DPLL_NA17_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA17_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA17_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA17_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA17_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA17_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NA18 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA18_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA18_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA18_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA18_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA18_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA18_DB_MASK) #define GTM_gtm_cls0_DPLL_NA18_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA18_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA18_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA18_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA18_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA18_DW_MASK) #define GTM_gtm_cls0_DPLL_NA18_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA18_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA18_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA18_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA18_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA18_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NA19 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA19_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA19_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA19_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA19_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA19_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA19_DB_MASK) #define GTM_gtm_cls0_DPLL_NA19_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA19_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA19_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA19_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA19_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA19_DW_MASK) #define GTM_gtm_cls0_DPLL_NA19_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA19_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA19_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA19_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA19_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA19_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NA20 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA20_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA20_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA20_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA20_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA20_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA20_DB_MASK) #define GTM_gtm_cls0_DPLL_NA20_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA20_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA20_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA20_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA20_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA20_DW_MASK) #define GTM_gtm_cls0_DPLL_NA20_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA20_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA20_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA20_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA20_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA20_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NA21 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA21_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA21_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA21_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA21_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA21_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA21_DB_MASK) #define GTM_gtm_cls0_DPLL_NA21_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA21_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA21_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA21_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA21_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA21_DW_MASK) #define GTM_gtm_cls0_DPLL_NA21_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA21_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA21_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA21_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA21_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA21_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NA22 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA22_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA22_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA22_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA22_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA22_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA22_DB_MASK) #define GTM_gtm_cls0_DPLL_NA22_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA22_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA22_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA22_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA22_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA22_DW_MASK) #define GTM_gtm_cls0_DPLL_NA22_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA22_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA22_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA22_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA22_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA22_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NA23 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA23_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA23_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA23_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA23_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA23_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA23_DB_MASK) #define GTM_gtm_cls0_DPLL_NA23_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA23_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA23_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA23_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA23_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA23_DW_MASK) #define GTM_gtm_cls0_DPLL_NA23_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA23_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA23_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA23_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA23_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA23_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NA24 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA24_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA24_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA24_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA24_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA24_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA24_DB_MASK) #define GTM_gtm_cls0_DPLL_NA24_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA24_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA24_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA24_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA24_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA24_DW_MASK) #define GTM_gtm_cls0_DPLL_NA24_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA24_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA24_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA24_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA24_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA24_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NA25 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA25_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA25_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA25_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA25_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA25_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA25_DB_MASK) #define GTM_gtm_cls0_DPLL_NA25_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA25_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA25_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA25_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA25_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA25_DW_MASK) #define GTM_gtm_cls0_DPLL_NA25_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA25_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA25_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA25_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA25_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA25_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NA26 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA26_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA26_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA26_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA26_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA26_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA26_DB_MASK) #define GTM_gtm_cls0_DPLL_NA26_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA26_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA26_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA26_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA26_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA26_DW_MASK) #define GTM_gtm_cls0_DPLL_NA26_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA26_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA26_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA26_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA26_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA26_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NA27 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA27_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA27_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA27_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA27_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA27_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA27_DB_MASK) #define GTM_gtm_cls0_DPLL_NA27_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA27_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA27_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA27_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA27_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA27_DW_MASK) #define GTM_gtm_cls0_DPLL_NA27_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA27_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA27_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA27_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA27_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA27_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NA28 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA28_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA28_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA28_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA28_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA28_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA28_DB_MASK) #define GTM_gtm_cls0_DPLL_NA28_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA28_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA28_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA28_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA28_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA28_DW_MASK) #define GTM_gtm_cls0_DPLL_NA28_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA28_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA28_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA28_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA28_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA28_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NA29 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA29_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA29_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA29_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA29_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA29_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA29_DB_MASK) #define GTM_gtm_cls0_DPLL_NA29_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA29_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA29_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA29_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA29_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA29_DW_MASK) #define GTM_gtm_cls0_DPLL_NA29_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA29_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA29_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA29_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA29_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA29_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NA30 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA30_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA30_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA30_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA30_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA30_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA30_DB_MASK) #define GTM_gtm_cls0_DPLL_NA30_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA30_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA30_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA30_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA30_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA30_DW_MASK) #define GTM_gtm_cls0_DPLL_NA30_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA30_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA30_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA30_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA30_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA30_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NA31 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NA31_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_NA31_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NA31_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA31_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA31_DB_SHIFT)) & GTM_gtm_cls0_DPLL_NA31_DB_MASK) #define GTM_gtm_cls0_DPLL_NA31_DW_MASK (0xFFC00U) #define GTM_gtm_cls0_DPLL_NA31_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_NA31_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_NA31_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA31_DW_SHIFT)) & GTM_gtm_cls0_DPLL_NA31_DW_MASK) #define GTM_gtm_cls0_DPLL_NA31_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NA31_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NA31_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NA31_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NA31_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NA31_NOT_USED_MASK) /*! @} */ /*! @name DPLL_DTA0 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA0_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA0_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA0_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA0_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA0_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA0_DTA_MASK) /*! @} */ /*! @name DPLL_DTA1 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA1_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA1_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA1_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA1_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA1_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA1_DTA_MASK) /*! @} */ /*! @name DPLL_DTA2 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA2_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA2_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA2_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA2_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA2_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA2_DTA_MASK) /*! @} */ /*! @name DPLL_DTA3 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA3_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA3_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA3_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA3_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA3_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA3_DTA_MASK) /*! @} */ /*! @name DPLL_DTA4 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA4_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA4_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA4_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA4_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA4_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA4_DTA_MASK) /*! @} */ /*! @name DPLL_DTA5 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA5_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA5_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA5_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA5_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA5_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA5_DTA_MASK) /*! @} */ /*! @name DPLL_DTA6 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA6_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA6_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA6_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA6_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA6_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA6_DTA_MASK) /*! @} */ /*! @name DPLL_DTA7 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA7_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA7_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA7_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA7_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA7_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA7_DTA_MASK) /*! @} */ /*! @name DPLL_DTA8 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA8_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA8_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA8_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA8_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA8_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA8_DTA_MASK) /*! @} */ /*! @name DPLL_DTA9 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA9_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA9_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA9_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA9_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA9_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA9_DTA_MASK) /*! @} */ /*! @name DPLL_DTA10 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA10_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA10_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA10_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA10_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA10_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA10_DTA_MASK) /*! @} */ /*! @name DPLL_DTA11 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA11_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA11_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA11_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA11_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA11_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA11_DTA_MASK) /*! @} */ /*! @name DPLL_DTA12 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA12_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA12_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA12_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA12_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA12_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA12_DTA_MASK) /*! @} */ /*! @name DPLL_DTA13 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA13_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA13_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA13_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA13_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA13_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA13_DTA_MASK) /*! @} */ /*! @name DPLL_DTA14 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA14_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA14_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA14_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA14_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA14_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA14_DTA_MASK) /*! @} */ /*! @name DPLL_DTA15 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA15_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA15_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA15_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA15_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA15_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA15_DTA_MASK) /*! @} */ /*! @name DPLL_DTA16 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA16_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA16_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA16_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA16_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA16_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA16_DTA_MASK) /*! @} */ /*! @name DPLL_DTA17 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA17_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA17_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA17_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA17_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA17_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA17_DTA_MASK) /*! @} */ /*! @name DPLL_DTA18 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA18_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA18_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA18_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA18_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA18_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA18_DTA_MASK) /*! @} */ /*! @name DPLL_DTA19 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA19_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA19_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA19_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA19_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA19_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA19_DTA_MASK) /*! @} */ /*! @name DPLL_DTA20 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA20_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA20_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA20_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA20_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA20_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA20_DTA_MASK) /*! @} */ /*! @name DPLL_DTA21 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA21_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA21_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA21_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA21_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA21_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA21_DTA_MASK) /*! @} */ /*! @name DPLL_DTA22 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA22_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA22_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA22_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA22_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA22_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA22_DTA_MASK) /*! @} */ /*! @name DPLL_DTA23 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA23_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA23_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA23_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA23_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA23_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA23_DTA_MASK) /*! @} */ /*! @name DPLL_DTA24 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA24_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA24_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA24_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA24_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA24_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA24_DTA_MASK) /*! @} */ /*! @name DPLL_DTA25 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA25_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA25_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA25_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA25_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA25_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA25_DTA_MASK) /*! @} */ /*! @name DPLL_DTA26 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA26_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA26_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA26_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA26_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA26_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA26_DTA_MASK) /*! @} */ /*! @name DPLL_DTA27 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA27_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA27_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA27_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA27_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA27_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA27_DTA_MASK) /*! @} */ /*! @name DPLL_DTA28 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA28_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA28_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA28_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA28_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA28_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA28_DTA_MASK) /*! @} */ /*! @name DPLL_DTA29 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA29_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA29_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA29_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA29_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA29_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA29_DTA_MASK) /*! @} */ /*! @name DPLL_DTA30 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA30_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA30_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA30_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA30_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA30_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA30_DTA_MASK) /*! @} */ /*! @name DPLL_DTA31 - Calculated Relative Time to Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DTA31_DTA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DTA31_DTA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DTA31_DTA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DTA31_DTA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DTA31_DTA_SHIFT)) & GTM_gtm_cls0_DPLL_DTA31_DTA_MASK) /*! @} */ /*! @name DPLL_TS_T - Actual TRIGGER Time Stamp Value */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TS_T_TRIGGER_TS_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TS_T_TRIGGER_TS_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TS_T_TRIGGER_TS_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TS_T_TRIGGER_TS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TS_T_TRIGGER_TS_SHIFT)) & GTM_gtm_cls0_DPLL_TS_T_TRIGGER_TS_MASK) /*! @} */ /*! @name DPLL_TS_T_OLD - Previous TRIGGER Time Stamp Value */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TS_T_OLD_TRIGGER_TS_OLD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TS_T_OLD_TRIGGER_TS_OLD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TS_T_OLD_TRIGGER_TS_OLD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TS_T_OLD_TRIGGER_TS_OLD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TS_T_OLD_TRIGGER_TS_OLD_SHIFT)) & GTM_gtm_cls0_DPLL_TS_T_OLD_TRIGGER_TS_OLD_MASK) /*! @} */ /*! @name DPLL_FTV_T - Actual TRIGGER Filter value */ /*! @{ */ #define GTM_gtm_cls0_DPLL_FTV_T_TRIGGER_FT_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_FTV_T_TRIGGER_FT_SHIFT (0U) #define GTM_gtm_cls0_DPLL_FTV_T_TRIGGER_FT_WIDTH (24U) #define GTM_gtm_cls0_DPLL_FTV_T_TRIGGER_FT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_FTV_T_TRIGGER_FT_SHIFT)) & GTM_gtm_cls0_DPLL_FTV_T_TRIGGER_FT_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_0 - DPLL RAM1B reserved data */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_0_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_0_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_0_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_0_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_0_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_0_RSVD_MASK) /*! @} */ /*! @name DPLL_TS_S - Actual STATE Time Stamp Register */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TS_S_STATE_TS_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TS_S_STATE_TS_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TS_S_STATE_TS_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TS_S_STATE_TS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TS_S_STATE_TS_SHIFT)) & GTM_gtm_cls0_DPLL_TS_S_STATE_TS_MASK) /*! @} */ /*! @name DPLL_TS_S_OLD - Previous STATE Time Stamp Register */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TS_S_OLD_STATE_TS_OLD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TS_S_OLD_STATE_TS_OLD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TS_S_OLD_STATE_TS_OLD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TS_S_OLD_STATE_TS_OLD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TS_S_OLD_STATE_TS_OLD_SHIFT)) & GTM_gtm_cls0_DPLL_TS_S_OLD_STATE_TS_OLD_MASK) /*! @} */ /*! @name DPLL_FTV_S - Actual STATE Filter Value */ /*! @{ */ #define GTM_gtm_cls0_DPLL_FTV_S_STATE_FT_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_FTV_S_STATE_FT_SHIFT (0U) #define GTM_gtm_cls0_DPLL_FTV_S_STATE_FT_WIDTH (24U) #define GTM_gtm_cls0_DPLL_FTV_S_STATE_FT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_FTV_S_STATE_FT_SHIFT)) & GTM_gtm_cls0_DPLL_FTV_S_STATE_FT_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_1 - DPLL RAM1B reserved data */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_1_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_1_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_1_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_1_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_1_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_1_RSVD_MASK) /*! @} */ /*! @name DPLL_THMI - TRIGGER Hold Time Min. Value */ /*! @{ */ #define GTM_gtm_cls0_DPLL_THMI_THMI_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_THMI_THMI_SHIFT (0U) #define GTM_gtm_cls0_DPLL_THMI_THMI_WIDTH (16U) #define GTM_gtm_cls0_DPLL_THMI_THMI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_THMI_THMI_SHIFT)) & GTM_gtm_cls0_DPLL_THMI_THMI_MASK) #define GTM_gtm_cls0_DPLL_THMI_NOT_USED_MASK (0xFF0000U) #define GTM_gtm_cls0_DPLL_THMI_NOT_USED_SHIFT (16U) #define GTM_gtm_cls0_DPLL_THMI_NOT_USED_WIDTH (8U) #define GTM_gtm_cls0_DPLL_THMI_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_THMI_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_THMI_NOT_USED_MASK) /*! @} */ /*! @name DPLL_THMA - TRIGGER Hold Time Max. Value */ /*! @{ */ #define GTM_gtm_cls0_DPLL_THMA_THMA_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_THMA_THMA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_THMA_THMA_WIDTH (16U) #define GTM_gtm_cls0_DPLL_THMA_THMA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_THMA_THMA_SHIFT)) & GTM_gtm_cls0_DPLL_THMA_THMA_MASK) #define GTM_gtm_cls0_DPLL_THMA_NOT_USED_MASK (0xFF0000U) #define GTM_gtm_cls0_DPLL_THMA_NOT_USED_SHIFT (16U) #define GTM_gtm_cls0_DPLL_THMA_NOT_USED_WIDTH (8U) #define GTM_gtm_cls0_DPLL_THMA_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_THMA_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_THMA_NOT_USED_MASK) /*! @} */ /*! @name DPLL_THVAL - Measured TRIGGER Hold Time Value */ /*! @{ */ #define GTM_gtm_cls0_DPLL_THVAL_THVAL_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_THVAL_THVAL_SHIFT (0U) #define GTM_gtm_cls0_DPLL_THVAL_THVAL_WIDTH (24U) #define GTM_gtm_cls0_DPLL_THVAL_THVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_THVAL_THVAL_SHIFT)) & GTM_gtm_cls0_DPLL_THVAL_THVAL_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_2 - DPLL RAM1B reserved data */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_2_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_2_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_2_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_2_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_2_RSVD_MASK) /*! @} */ /*! @name DPLL_TOV - Time Out Value of Active TRIGGER Slope (for missing TRIGGER generation) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TOV_TOV_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_TOV_TOV_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TOV_TOV_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_TOV_TOV_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TOV_TOV_DB_SHIFT)) & GTM_gtm_cls0_DPLL_TOV_TOV_DB_MASK) #define GTM_gtm_cls0_DPLL_TOV_TOV_DW_MASK (0xFC00U) #define GTM_gtm_cls0_DPLL_TOV_TOV_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_TOV_TOV_DW_WIDTH (6U) #define GTM_gtm_cls0_DPLL_TOV_TOV_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TOV_TOV_DW_SHIFT)) & GTM_gtm_cls0_DPLL_TOV_TOV_DW_MASK) #define GTM_gtm_cls0_DPLL_TOV_NOT_USED_MASK (0xFF0000U) #define GTM_gtm_cls0_DPLL_TOV_NOT_USED_SHIFT (16U) #define GTM_gtm_cls0_DPLL_TOV_NOT_USED_WIDTH (8U) #define GTM_gtm_cls0_DPLL_TOV_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TOV_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_TOV_NOT_USED_MASK) /*! @} */ /*! @name DPLL_TOV_S - Time Out Value of active STATE Slope (for missing STATE generation) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TOV_S_DB_MASK (0x3FFU) #define GTM_gtm_cls0_DPLL_TOV_S_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TOV_S_DB_WIDTH (10U) #define GTM_gtm_cls0_DPLL_TOV_S_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TOV_S_DB_SHIFT)) & GTM_gtm_cls0_DPLL_TOV_S_DB_MASK) #define GTM_gtm_cls0_DPLL_TOV_S_DW_MASK (0xFC00U) #define GTM_gtm_cls0_DPLL_TOV_S_DW_SHIFT (10U) #define GTM_gtm_cls0_DPLL_TOV_S_DW_WIDTH (6U) #define GTM_gtm_cls0_DPLL_TOV_S_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TOV_S_DW_SHIFT)) & GTM_gtm_cls0_DPLL_TOV_S_DW_MASK) #define GTM_gtm_cls0_DPLL_TOV_S_NOT_USED_MASK (0xFF0000U) #define GTM_gtm_cls0_DPLL_TOV_S_NOT_USED_SHIFT (16U) #define GTM_gtm_cls0_DPLL_TOV_S_NOT_USED_WIDTH (8U) #define GTM_gtm_cls0_DPLL_TOV_S_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TOV_S_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_TOV_S_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADD_IN_CAL1 - Calculated ADD_IN Value for SUB_INC1 Generation */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADD_IN_CAL1_ADD_IN_CAL1_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_ADD_IN_CAL1_ADD_IN_CAL1_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADD_IN_CAL1_ADD_IN_CAL1_WIDTH (24U) #define GTM_gtm_cls0_DPLL_ADD_IN_CAL1_ADD_IN_CAL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADD_IN_CAL1_ADD_IN_CAL1_SHIFT)) & GTM_gtm_cls0_DPLL_ADD_IN_CAL1_ADD_IN_CAL1_MASK) /*! @} */ /*! @name DPLL_ADD_IN_CAL2 - Calculated ADD_IN Value for SUB_INC2 Generation */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADD_IN_CAL2_ADD_IN_CAL2_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_ADD_IN_CAL2_ADD_IN_CAL2_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADD_IN_CAL2_ADD_IN_CAL2_WIDTH (24U) #define GTM_gtm_cls0_DPLL_ADD_IN_CAL2_ADD_IN_CAL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADD_IN_CAL2_ADD_IN_CAL2_SHIFT)) & GTM_gtm_cls0_DPLL_ADD_IN_CAL2_ADD_IN_CAL2_MASK) /*! @} */ /*! @name DPLL_MPVAL1 - Missing Pulses to be Added or Subtracted Directly */ /*! @{ */ #define GTM_gtm_cls0_DPLL_MPVAL1_MPVAL1_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_MPVAL1_MPVAL1_SHIFT (0U) #define GTM_gtm_cls0_DPLL_MPVAL1_MPVAL1_WIDTH (16U) #define GTM_gtm_cls0_DPLL_MPVAL1_MPVAL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_MPVAL1_MPVAL1_SHIFT)) & GTM_gtm_cls0_DPLL_MPVAL1_MPVAL1_MASK) #define GTM_gtm_cls0_DPLL_MPVAL1_SIX1_MASK (0xFF0000U) #define GTM_gtm_cls0_DPLL_MPVAL1_SIX1_SHIFT (16U) #define GTM_gtm_cls0_DPLL_MPVAL1_SIX1_WIDTH (8U) #define GTM_gtm_cls0_DPLL_MPVAL1_SIX1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_MPVAL1_SIX1_SHIFT)) & GTM_gtm_cls0_DPLL_MPVAL1_SIX1_MASK) /*! @} */ /*! @name DPLL_MPVAL2 - Missing Pulses to be Added or Subtracted Directly */ /*! @{ */ #define GTM_gtm_cls0_DPLL_MPVAL2_MPVAL2_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_MPVAL2_MPVAL2_SHIFT (0U) #define GTM_gtm_cls0_DPLL_MPVAL2_MPVAL2_WIDTH (16U) #define GTM_gtm_cls0_DPLL_MPVAL2_MPVAL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_MPVAL2_MPVAL2_SHIFT)) & GTM_gtm_cls0_DPLL_MPVAL2_MPVAL2_MASK) #define GTM_gtm_cls0_DPLL_MPVAL2_SIX2_MASK (0xFF0000U) #define GTM_gtm_cls0_DPLL_MPVAL2_SIX2_SHIFT (16U) #define GTM_gtm_cls0_DPLL_MPVAL2_SIX2_WIDTH (8U) #define GTM_gtm_cls0_DPLL_MPVAL2_SIX2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_MPVAL2_SIX2_SHIFT)) & GTM_gtm_cls0_DPLL_MPVAL2_SIX2_MASK) /*! @} */ /*! @name DPLL_NMB_T_TAR - Target Number of Pulses to be sent in Normal Mode */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NMB_T_TAR_NMB_T_TAR_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_NMB_T_TAR_NMB_T_TAR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NMB_T_TAR_NMB_T_TAR_WIDTH (16U) #define GTM_gtm_cls0_DPLL_NMB_T_TAR_NMB_T_TAR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NMB_T_TAR_NMB_T_TAR_SHIFT)) & GTM_gtm_cls0_DPLL_NMB_T_TAR_NMB_T_TAR_MASK) #define GTM_gtm_cls0_DPLL_NMB_T_TAR_NOT_USED_MASK (0xFF0000U) #define GTM_gtm_cls0_DPLL_NMB_T_TAR_NOT_USED_SHIFT (16U) #define GTM_gtm_cls0_DPLL_NMB_T_TAR_NOT_USED_WIDTH (8U) #define GTM_gtm_cls0_DPLL_NMB_T_TAR_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NMB_T_TAR_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NMB_T_TAR_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NMB_T_TAR_OLD - Last but one Target Number of Pulses to be sent in Normal Mode */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NMB_T_TAR_OLD_NMB_T_TAR_OLD_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_NMB_T_TAR_OLD_NMB_T_TAR_OLD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NMB_T_TAR_OLD_NMB_T_TAR_OLD_WIDTH (16U) #define GTM_gtm_cls0_DPLL_NMB_T_TAR_OLD_NMB_T_TAR_OLD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NMB_T_TAR_OLD_NMB_T_TAR_OLD_SHIFT)) & GTM_gtm_cls0_DPLL_NMB_T_TAR_OLD_NMB_T_TAR_OLD_MASK) #define GTM_gtm_cls0_DPLL_NMB_T_TAR_OLD_NOT_USED_MASK (0xFF0000U) #define GTM_gtm_cls0_DPLL_NMB_T_TAR_OLD_NOT_USED_SHIFT (16U) #define GTM_gtm_cls0_DPLL_NMB_T_TAR_OLD_NOT_USED_WIDTH (8U) #define GTM_gtm_cls0_DPLL_NMB_T_TAR_OLD_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NMB_T_TAR_OLD_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NMB_T_TAR_OLD_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NMB_S_TAR - Target Number of Pulses to be sent in Emergency Mode */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NMB_S_TAR_NMB_S_TAR_MASK (0xFFFFFU) #define GTM_gtm_cls0_DPLL_NMB_S_TAR_NMB_S_TAR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NMB_S_TAR_NMB_S_TAR_WIDTH (20U) #define GTM_gtm_cls0_DPLL_NMB_S_TAR_NMB_S_TAR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NMB_S_TAR_NMB_S_TAR_SHIFT)) & GTM_gtm_cls0_DPLL_NMB_S_TAR_NMB_S_TAR_MASK) #define GTM_gtm_cls0_DPLL_NMB_S_TAR_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NMB_S_TAR_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NMB_S_TAR_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NMB_S_TAR_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NMB_S_TAR_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NMB_S_TAR_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NMB_S_TAR_OLD - Last but one Target Number of Pulses to be sent in Emergency Mode */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NMB_S_TAR_OLD_NMB_S_TAR_OLD_MASK (0xFFFFFU) #define GTM_gtm_cls0_DPLL_NMB_S_TAR_OLD_NMB_S_TAR_OLD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NMB_S_TAR_OLD_NMB_S_TAR_OLD_WIDTH (20U) #define GTM_gtm_cls0_DPLL_NMB_S_TAR_OLD_NMB_S_TAR_OLD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NMB_S_TAR_OLD_NMB_S_TAR_OLD_SHIFT)) & GTM_gtm_cls0_DPLL_NMB_S_TAR_OLD_NMB_S_TAR_OLD_MASK) #define GTM_gtm_cls0_DPLL_NMB_S_TAR_OLD_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NMB_S_TAR_OLD_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NMB_S_TAR_OLD_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NMB_S_TAR_OLD_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NMB_S_TAR_OLD_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NMB_S_TAR_OLD_NOT_USED_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_3_0 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_3_0_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_3_0_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_3_0_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_3_0_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_3_0_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_3_0_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_3_1 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_3_1_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_3_1_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_3_1_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_3_1_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_3_1_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_3_1_RSVD_MASK) /*! @} */ /*! @name DPLL_RCDT_TX - Reciprocal Value of the Expected Increment Duration of TRIGGER */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RCDT_TX_RCDT_TX_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RCDT_TX_RCDT_TX_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RCDT_TX_RCDT_TX_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RCDT_TX_RCDT_TX(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RCDT_TX_RCDT_TX_SHIFT)) & GTM_gtm_cls0_DPLL_RCDT_TX_RCDT_TX_MASK) /*! @} */ /*! @name DPLL_RCDT_SX - Reciprocal Value of the Expected Increment Duration of STATE */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RCDT_SX_RCDT_SX_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RCDT_SX_RCDT_SX_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RCDT_SX_RCDT_SX_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RCDT_SX_RCDT_SX(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RCDT_SX_RCDT_SX_SHIFT)) & GTM_gtm_cls0_DPLL_RCDT_SX_RCDT_SX_MASK) /*! @} */ /*! @name DPLL_RCDT_TX_NOM - Reciprocal Value of the Expected Nominal Increment Duration of TRIGGER */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RCDT_TX_NOM_RCDT_TX_NOM_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RCDT_TX_NOM_RCDT_TX_NOM_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RCDT_TX_NOM_RCDT_TX_NOM_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RCDT_TX_NOM_RCDT_TX_NOM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RCDT_TX_NOM_RCDT_TX_NOM_SHIFT)) & GTM_gtm_cls0_DPLL_RCDT_TX_NOM_RCDT_TX_NOM_MASK) /*! @} */ /*! @name DPLL_RCDT_SX_NOM - Reciprocal Value of the Expected Nominal Increment Duration of STATE */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RCDT_SX_NOM_RCDT_SX_NOM_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RCDT_SX_NOM_RCDT_SX_NOM_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RCDT_SX_NOM_RCDT_SX_NOM_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RCDT_SX_NOM_RCDT_SX_NOM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RCDT_SX_NOM_RCDT_SX_NOM_SHIFT)) & GTM_gtm_cls0_DPLL_RCDT_SX_NOM_RCDT_SX_NOM_MASK) /*! @} */ /*! @name DPLL_RDT_T_ACT - Reciprocal Value of the Last Increment of TRIGGER */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_T_ACT_RDT_T_ACT_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_T_ACT_RDT_T_ACT_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_T_ACT_RDT_T_ACT_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_T_ACT_RDT_T_ACT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_T_ACT_RDT_T_ACT_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_T_ACT_RDT_T_ACT_MASK) /*! @} */ /*! @name DPLL_RDT_S_ACT - Reciprocal Value of the Last Increment of STATE */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S_ACT_RDT_S_ACT_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S_ACT_RDT_S_ACT_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S_ACT_RDT_S_ACT_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S_ACT_RDT_S_ACT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S_ACT_RDT_S_ACT_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S_ACT_RDT_S_ACT_MASK) /*! @} */ /*! @name DPLL_DT_T_ACT - Duration of the Last TRIGGER Increment */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_T_ACT_DT_T_ACT_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_T_ACT_DT_T_ACT_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_T_ACT_DT_T_ACT_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_T_ACT_DT_T_ACT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_T_ACT_DT_T_ACT_SHIFT)) & GTM_gtm_cls0_DPLL_DT_T_ACT_DT_T_ACT_MASK) /*! @} */ /*! @name DPLL_DT_S_ACT - Duration of the Last STATE Increment */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S_ACT_DT_S_ACT_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S_ACT_DT_S_ACT_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S_ACT_DT_S_ACT_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S_ACT_DT_S_ACT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S_ACT_DT_S_ACT_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S_ACT_DT_S_ACT_MASK) /*! @} */ /*! @name DPLL_EDT_T - Difference of Prediction to Actual Value of the Last TRIGGER Increment */ /*! @{ */ #define GTM_gtm_cls0_DPLL_EDT_T_EDT_T_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_EDT_T_EDT_T_SHIFT (0U) #define GTM_gtm_cls0_DPLL_EDT_T_EDT_T_WIDTH (24U) #define GTM_gtm_cls0_DPLL_EDT_T_EDT_T(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_EDT_T_EDT_T_SHIFT)) & GTM_gtm_cls0_DPLL_EDT_T_EDT_T_MASK) /*! @} */ /*! @name DPLL_MEDT_T - Weighted Difference of Prediction Errors of TRIGGER */ /*! @{ */ #define GTM_gtm_cls0_DPLL_MEDT_T_MEDT_T_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_MEDT_T_MEDT_T_SHIFT (0U) #define GTM_gtm_cls0_DPLL_MEDT_T_MEDT_T_WIDTH (24U) #define GTM_gtm_cls0_DPLL_MEDT_T_MEDT_T(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_MEDT_T_MEDT_T_SHIFT)) & GTM_gtm_cls0_DPLL_MEDT_T_MEDT_T_MASK) /*! @} */ /*! @name DPLL_EDT_S - Difference of Prediction to Actual Value of the Last STATE Increment */ /*! @{ */ #define GTM_gtm_cls0_DPLL_EDT_S_EDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_EDT_S_EDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_EDT_S_EDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_EDT_S_EDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_EDT_S_EDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_EDT_S_EDT_S_MASK) /*! @} */ /*! @name DPLL_MEDT_S - Weighted Difference of Prediction Errors of STATE */ /*! @{ */ #define GTM_gtm_cls0_DPLL_MEDT_S_MEDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_MEDT_S_MEDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_MEDT_S_MEDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_MEDT_S_MEDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_MEDT_S_MEDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_MEDT_S_MEDT_S_MASK) /*! @} */ /*! @name DPLL_CDT_TX - Prediction of the Actual TRIGGER Increment Duration */ /*! @{ */ #define GTM_gtm_cls0_DPLL_CDT_TX_CDT_TX_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_CDT_TX_CDT_TX_SHIFT (0U) #define GTM_gtm_cls0_DPLL_CDT_TX_CDT_TX_WIDTH (24U) #define GTM_gtm_cls0_DPLL_CDT_TX_CDT_TX(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CDT_TX_CDT_TX_SHIFT)) & GTM_gtm_cls0_DPLL_CDT_TX_CDT_TX_MASK) /*! @} */ /*! @name DPLL_CDT_SX - Prediction of the Actual STATE Increment Duration */ /*! @{ */ #define GTM_gtm_cls0_DPLL_CDT_SX_CDT_SX_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_CDT_SX_CDT_SX_SHIFT (0U) #define GTM_gtm_cls0_DPLL_CDT_SX_CDT_SX_WIDTH (24U) #define GTM_gtm_cls0_DPLL_CDT_SX_CDT_SX(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CDT_SX_CDT_SX_SHIFT)) & GTM_gtm_cls0_DPLL_CDT_SX_CDT_SX_MASK) /*! @} */ /*! @name DPLL_CDT_TX_NOM - Prediction of the Nominal TRIGGER Increment Duration */ /*! @{ */ #define GTM_gtm_cls0_DPLL_CDT_TX_NOM_CDT_TX_NOM_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_CDT_TX_NOM_CDT_TX_NOM_SHIFT (0U) #define GTM_gtm_cls0_DPLL_CDT_TX_NOM_CDT_TX_NOM_WIDTH (24U) #define GTM_gtm_cls0_DPLL_CDT_TX_NOM_CDT_TX_NOM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CDT_TX_NOM_CDT_TX_NOM_SHIFT)) & GTM_gtm_cls0_DPLL_CDT_TX_NOM_CDT_TX_NOM_MASK) /*! @} */ /*! @name DPLL_CDT_SX_NOM - Prediction of the Nominal STATE Increment Duration */ /*! @{ */ #define GTM_gtm_cls0_DPLL_CDT_SX_NOM_CDT_SX_NOM_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_CDT_SX_NOM_CDT_SX_NOM_SHIFT (0U) #define GTM_gtm_cls0_DPLL_CDT_SX_NOM_CDT_SX_NOM_WIDTH (24U) #define GTM_gtm_cls0_DPLL_CDT_SX_NOM_CDT_SX_NOM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CDT_SX_NOM_CDT_SX_NOM_SHIFT)) & GTM_gtm_cls0_DPLL_CDT_SX_NOM_CDT_SX_NOM_MASK) /*! @} */ /*! @name DPLL_TLR - TRIGGER Locking Range */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TLR_TLR_MASK (0xFFU) #define GTM_gtm_cls0_DPLL_TLR_TLR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TLR_TLR_WIDTH (8U) #define GTM_gtm_cls0_DPLL_TLR_TLR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TLR_TLR_SHIFT)) & GTM_gtm_cls0_DPLL_TLR_TLR_MASK) #define GTM_gtm_cls0_DPLL_TLR_NOT_USED_MASK (0xFFFF00U) #define GTM_gtm_cls0_DPLL_TLR_NOT_USED_SHIFT (8U) #define GTM_gtm_cls0_DPLL_TLR_NOT_USED_WIDTH (16U) #define GTM_gtm_cls0_DPLL_TLR_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TLR_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_TLR_NOT_USED_MASK) /*! @} */ /*! @name DPLL_SLR - STATE Locking Range */ /*! @{ */ #define GTM_gtm_cls0_DPLL_SLR_SLR_MASK (0xFFU) #define GTM_gtm_cls0_DPLL_SLR_SLR_SHIFT (0U) #define GTM_gtm_cls0_DPLL_SLR_SLR_WIDTH (8U) #define GTM_gtm_cls0_DPLL_SLR_SLR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_SLR_SLR_SHIFT)) & GTM_gtm_cls0_DPLL_SLR_SLR_MASK) #define GTM_gtm_cls0_DPLL_SLR_NOT_USED_MASK (0xFFFF00U) #define GTM_gtm_cls0_DPLL_SLR_NOT_USED_SHIFT (8U) #define GTM_gtm_cls0_DPLL_SLR_NOT_USED_WIDTH (16U) #define GTM_gtm_cls0_DPLL_SLR_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_SLR_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_SLR_NOT_USED_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_4_0 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_0_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_0_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_0_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_0_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_0_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_0_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_4_1 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_1_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_1_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_1_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_1_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_1_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_1_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_4_2 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_2_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_2_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_2_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_2_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_2_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_4_3 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_3_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_3_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_3_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_3_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_3_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_3_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_4_4 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_4_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_4_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_4_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_4_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_4_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_4_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_4_5 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_5_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_5_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_5_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_5_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_5_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_5_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_4_6 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_6_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_6_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_6_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_6_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_6_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_6_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_4_7 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_7_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_7_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_7_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_7_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_7_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_7_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_4_8 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_8_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_8_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_8_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_8_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_8_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_8_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_4_9 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_9_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_9_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_9_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_9_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_9_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_9_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_4_10 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_10_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_10_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_10_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_10_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_10_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_10_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_4_11 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_11_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_11_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_11_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_11_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_11_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_11_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_4_12 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_12_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_12_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_12_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_12_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_12_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_12_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_4_13 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_13_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_13_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_13_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_13_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_13_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_13_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_4_14 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_14_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_14_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_14_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_14_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_14_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_14_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_4_15 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_15_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_15_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_15_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_15_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_15_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_15_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_4_16 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_16_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_16_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_16_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_16_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_16_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_16_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_4_17 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_17_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_17_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_17_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_17_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_17_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_17_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_4_18 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_18_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_18_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_18_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_18_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_18_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_18_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_4_19 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_19_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_19_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_19_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_19_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_19_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_19_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_4_20 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_20_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_20_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_20_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_20_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_20_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_20_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_4_21 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_21_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_21_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_21_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_21_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_21_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_4_21_RSVD_MASK) /*! @} */ /*! @name DPLL_PDT_0 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_0_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_0_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_0_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_0_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_0_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_0_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_0_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_0_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_0_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_0_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_0_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_0_DW_MASK) /*! @} */ /*! @name DPLL_PDT_1 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_1_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_1_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_1_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_1_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_1_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_1_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_1_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_1_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_1_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_1_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_1_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_1_DW_MASK) /*! @} */ /*! @name DPLL_PDT_2 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_2_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_2_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_2_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_2_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_2_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_2_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_2_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_2_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_2_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_2_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_2_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_2_DW_MASK) /*! @} */ /*! @name DPLL_PDT_3 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_3_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_3_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_3_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_3_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_3_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_3_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_3_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_3_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_3_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_3_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_3_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_3_DW_MASK) /*! @} */ /*! @name DPLL_PDT_4 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_4_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_4_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_4_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_4_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_4_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_4_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_4_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_4_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_4_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_4_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_4_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_4_DW_MASK) /*! @} */ /*! @name DPLL_PDT_5 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_5_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_5_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_5_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_5_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_5_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_5_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_5_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_5_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_5_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_5_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_5_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_5_DW_MASK) /*! @} */ /*! @name DPLL_PDT_6 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_6_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_6_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_6_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_6_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_6_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_6_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_6_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_6_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_6_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_6_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_6_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_6_DW_MASK) /*! @} */ /*! @name DPLL_PDT_7 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_7_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_7_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_7_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_7_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_7_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_7_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_7_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_7_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_7_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_7_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_7_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_7_DW_MASK) /*! @} */ /*! @name DPLL_PDT_8 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_8_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_8_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_8_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_8_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_8_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_8_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_8_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_8_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_8_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_8_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_8_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_8_DW_MASK) /*! @} */ /*! @name DPLL_PDT_9 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_9_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_9_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_9_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_9_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_9_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_9_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_9_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_9_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_9_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_9_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_9_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_9_DW_MASK) /*! @} */ /*! @name DPLL_PDT_10 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_10_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_10_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_10_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_10_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_10_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_10_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_10_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_10_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_10_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_10_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_10_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_10_DW_MASK) /*! @} */ /*! @name DPLL_PDT_11 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_11_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_11_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_11_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_11_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_11_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_11_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_11_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_11_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_11_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_11_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_11_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_11_DW_MASK) /*! @} */ /*! @name DPLL_PDT_12 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_12_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_12_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_12_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_12_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_12_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_12_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_12_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_12_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_12_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_12_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_12_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_12_DW_MASK) /*! @} */ /*! @name DPLL_PDT_13 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_13_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_13_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_13_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_13_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_13_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_13_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_13_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_13_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_13_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_13_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_13_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_13_DW_MASK) /*! @} */ /*! @name DPLL_PDT_14 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_14_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_14_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_14_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_14_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_14_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_14_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_14_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_14_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_14_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_14_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_14_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_14_DW_MASK) /*! @} */ /*! @name DPLL_PDT_15 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_15_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_15_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_15_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_15_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_15_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_15_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_15_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_15_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_15_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_15_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_15_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_15_DW_MASK) /*! @} */ /*! @name DPLL_PDT_16 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_16_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_16_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_16_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_16_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_16_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_16_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_16_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_16_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_16_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_16_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_16_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_16_DW_MASK) /*! @} */ /*! @name DPLL_PDT_17 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_17_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_17_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_17_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_17_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_17_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_17_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_17_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_17_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_17_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_17_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_17_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_17_DW_MASK) /*! @} */ /*! @name DPLL_PDT_18 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_18_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_18_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_18_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_18_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_18_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_18_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_18_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_18_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_18_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_18_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_18_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_18_DW_MASK) /*! @} */ /*! @name DPLL_PDT_19 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_19_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_19_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_19_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_19_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_19_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_19_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_19_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_19_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_19_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_19_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_19_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_19_DW_MASK) /*! @} */ /*! @name DPLL_PDT_20 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_20_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_20_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_20_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_20_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_20_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_20_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_20_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_20_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_20_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_20_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_20_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_20_DW_MASK) /*! @} */ /*! @name DPLL_PDT_21 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_21_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_21_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_21_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_21_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_21_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_21_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_21_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_21_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_21_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_21_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_21_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_21_DW_MASK) /*! @} */ /*! @name DPLL_PDT_22 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_22_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_22_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_22_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_22_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_22_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_22_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_22_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_22_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_22_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_22_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_22_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_22_DW_MASK) /*! @} */ /*! @name DPLL_PDT_23 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_23_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_23_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_23_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_23_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_23_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_23_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_23_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_23_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_23_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_23_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_23_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_23_DW_MASK) /*! @} */ /*! @name DPLL_PDT_24 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_24_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_24_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_24_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_24_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_24_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_24_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_24_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_24_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_24_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_24_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_24_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_24_DW_MASK) /*! @} */ /*! @name DPLL_PDT_25 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_25_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_25_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_25_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_25_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_25_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_25_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_25_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_25_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_25_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_25_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_25_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_25_DW_MASK) /*! @} */ /*! @name DPLL_PDT_26 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_26_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_26_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_26_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_26_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_26_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_26_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_26_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_26_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_26_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_26_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_26_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_26_DW_MASK) /*! @} */ /*! @name DPLL_PDT_27 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_27_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_27_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_27_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_27_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_27_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_27_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_27_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_27_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_27_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_27_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_27_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_27_DW_MASK) /*! @} */ /*! @name DPLL_PDT_28 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_28_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_28_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_28_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_28_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_28_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_28_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_28_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_28_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_28_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_28_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_28_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_28_DW_MASK) /*! @} */ /*! @name DPLL_PDT_29 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_29_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_29_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_29_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_29_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_29_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_29_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_29_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_29_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_29_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_29_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_29_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_29_DW_MASK) /*! @} */ /*! @name DPLL_PDT_30 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_30_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_30_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_30_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_30_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_30_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_30_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_30_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_30_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_30_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_30_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_30_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_30_DW_MASK) /*! @} */ /*! @name DPLL_PDT_31 - Projected Increment Sum Relations for Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PDT_31_DB_MASK (0x3FFFU) #define GTM_gtm_cls0_DPLL_PDT_31_DB_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PDT_31_DB_WIDTH (14U) #define GTM_gtm_cls0_DPLL_PDT_31_DB(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_31_DB_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_31_DB_MASK) #define GTM_gtm_cls0_DPLL_PDT_31_DW_MASK (0xFFC000U) #define GTM_gtm_cls0_DPLL_PDT_31_DW_SHIFT (14U) #define GTM_gtm_cls0_DPLL_PDT_31_DW_WIDTH (10U) #define GTM_gtm_cls0_DPLL_PDT_31_DW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PDT_31_DW_SHIFT)) & GTM_gtm_cls0_DPLL_PDT_31_DW_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_5_0 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_0_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_0_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_0_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_0_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_0_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_0_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_5_1 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_1_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_1_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_1_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_1_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_1_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_1_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_5_2 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_2_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_2_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_2_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_2_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_2_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_5_3 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_3_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_3_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_3_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_3_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_3_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_3_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_5_4 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_4_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_4_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_4_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_4_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_4_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_4_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_5_5 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_5_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_5_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_5_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_5_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_5_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_5_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_5_6 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_6_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_6_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_6_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_6_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_6_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_6_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_5_7 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_7_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_7_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_7_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_7_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_7_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_7_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_5_8 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_8_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_8_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_8_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_8_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_8_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_8_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_5_9 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_9_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_9_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_9_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_9_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_9_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_9_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_5_10 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_10_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_10_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_10_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_10_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_10_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_10_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_5_11 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_11_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_11_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_11_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_11_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_11_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_11_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_5_12 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_12_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_12_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_12_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_12_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_12_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_12_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_5_13 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_13_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_13_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_13_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_13_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_13_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_13_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_5_14 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_14_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_14_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_14_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_14_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_14_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_14_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_5_15 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_15_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_15_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_15_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_15_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_15_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_5_15_RSVD_MASK) /*! @} */ /*! @name DPLL_MLS1 - Calculated Number of Sub-Pulses between two nominal STATE Events for DPLL_CTRL_1.SMC = 0 */ /*! @{ */ #define GTM_gtm_cls0_DPLL_MLS1_MLS1_MASK (0x3FFFFU) #define GTM_gtm_cls0_DPLL_MLS1_MLS1_SHIFT (0U) #define GTM_gtm_cls0_DPLL_MLS1_MLS1_WIDTH (18U) #define GTM_gtm_cls0_DPLL_MLS1_MLS1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_MLS1_MLS1_SHIFT)) & GTM_gtm_cls0_DPLL_MLS1_MLS1_MASK) #define GTM_gtm_cls0_DPLL_MLS1_NOT_USED_MASK (0xFC0000U) #define GTM_gtm_cls0_DPLL_MLS1_NOT_USED_SHIFT (18U) #define GTM_gtm_cls0_DPLL_MLS1_NOT_USED_WIDTH (6U) #define GTM_gtm_cls0_DPLL_MLS1_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_MLS1_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_MLS1_NOT_USED_MASK) /*! @} */ /*! @name DPLL_MLS2 - Calculated Number of Sub-Pulses between two nominal STATE Events for DPLL_CTRL_1.SMC=1 and RMO=1 */ /*! @{ */ #define GTM_gtm_cls0_DPLL_MLS2_MLS2_MASK (0x3FFFFU) #define GTM_gtm_cls0_DPLL_MLS2_MLS2_SHIFT (0U) #define GTM_gtm_cls0_DPLL_MLS2_MLS2_WIDTH (18U) #define GTM_gtm_cls0_DPLL_MLS2_MLS2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_MLS2_MLS2_SHIFT)) & GTM_gtm_cls0_DPLL_MLS2_MLS2_MASK) #define GTM_gtm_cls0_DPLL_MLS2_NOT_USED_MASK (0xFC0000U) #define GTM_gtm_cls0_DPLL_MLS2_NOT_USED_SHIFT (18U) #define GTM_gtm_cls0_DPLL_MLS2_NOT_USED_WIDTH (6U) #define GTM_gtm_cls0_DPLL_MLS2_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_MLS2_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_MLS2_NOT_USED_MASK) /*! @} */ /*! @name DPLL_CNT_NUM_1 - Number of SUB_INC1 pulses in continuous mode */ /*! @{ */ #define GTM_gtm_cls0_DPLL_CNT_NUM_1_CNT_NUM_1_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_CNT_NUM_1_CNT_NUM_1_SHIFT (0U) #define GTM_gtm_cls0_DPLL_CNT_NUM_1_CNT_NUM_1_WIDTH (24U) #define GTM_gtm_cls0_DPLL_CNT_NUM_1_CNT_NUM_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CNT_NUM_1_CNT_NUM_1_SHIFT)) & GTM_gtm_cls0_DPLL_CNT_NUM_1_CNT_NUM_1_MASK) /*! @} */ /*! @name DPLL_CNT_NUM_2 - Number of SUB_INC2 pulses in continuous mode */ /*! @{ */ #define GTM_gtm_cls0_DPLL_CNT_NUM_2_CNT_NUM_2_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_CNT_NUM_2_CNT_NUM_2_SHIFT (0U) #define GTM_gtm_cls0_DPLL_CNT_NUM_2_CNT_NUM_2_WIDTH (24U) #define GTM_gtm_cls0_DPLL_CNT_NUM_2_CNT_NUM_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CNT_NUM_2_CNT_NUM_2_SHIFT)) & GTM_gtm_cls0_DPLL_CNT_NUM_2_CNT_NUM_2_MASK) /*! @} */ /*! @name DPLL_PVT - Plausibility Value of Next TRIGGER Slope */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PVT_PVT_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PVT_PVT_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PVT_PVT_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PVT_PVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PVT_PVT_SHIFT)) & GTM_gtm_cls0_DPLL_PVT_PVT_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_6_0 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_6_0_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_6_0_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_6_0_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_6_0_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_6_0_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_6_0_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_6_1 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_6_1_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_6_1_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_6_1_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_6_1_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_6_1_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_6_1_RSVD_MASK) /*! @} */ /*! @name DPLL_RAM1B_RSVD_6_2 - DPLL RAM1B reserved data [k] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_6_2_RSVD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_6_2_RSVD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_6_2_RSVD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RAM1B_RSVD_6_2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RAM1B_RSVD_6_2_RSVD_SHIFT)) & GTM_gtm_cls0_DPLL_RAM1B_RSVD_6_2_RSVD_MASK) /*! @} */ /*! @name DPLL_PSTC - Actual Calculated Position Stamp of TRIGGER */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSTC_PSTC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSTC_PSTC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSTC_PSTC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSTC_PSTC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSTC_PSTC_SHIFT)) & GTM_gtm_cls0_DPLL_PSTC_PSTC_MASK) /*! @} */ /*! @name DPLL_PSSC - Actual Calculated Position Stamp of STATE */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSSC_PSSC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSSC_PSSC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSSC_PSSC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSSC_PSSC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSSC_PSSC_SHIFT)) & GTM_gtm_cls0_DPLL_PSSC_PSSC_MASK) /*! @} */ /*! @name DPLL_PSTM - Measured Position Stamp at Last TRIGGER Input */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSTM_PSTM_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSTM_PSTM_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSTM_PSTM_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSTM_PSTM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSTM_PSTM_SHIFT)) & GTM_gtm_cls0_DPLL_PSTM_PSTM_MASK) /*! @} */ /*! @name DPLL_PSTM_OLD - Measured Position Stamp at Last but one TRIGGER Input */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSTM_OLD_PSTM_OLD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSTM_OLD_PSTM_OLD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSTM_OLD_PSTM_OLD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSTM_OLD_PSTM_OLD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSTM_OLD_PSTM_OLD_SHIFT)) & GTM_gtm_cls0_DPLL_PSTM_OLD_PSTM_OLD_MASK) /*! @} */ /*! @name DPLL_PSSM - Measured Position Stamp at Last STATE Input */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSSM_PSSM_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSSM_PSSM_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSSM_PSSM_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSSM_PSSM(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSSM_PSSM_SHIFT)) & GTM_gtm_cls0_DPLL_PSSM_PSSM_MASK) /*! @} */ /*! @name DPLL_PSSM_OLD - Measured Position Stamp at Last but one STATE Input */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSSM_OLD_PSSM_OLD_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSSM_OLD_PSSM_OLD_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSSM_OLD_PSSM_OLD_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSSM_OLD_PSSM_OLD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSSM_OLD_PSSM_OLD_SHIFT)) & GTM_gtm_cls0_DPLL_PSSM_OLD_PSSM_OLD_MASK) /*! @} */ /*! @name DPLL_NMB_T - Number of Pulses to be sent in Normal Mode */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NMB_T_NMB_T_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_NMB_T_NMB_T_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NMB_T_NMB_T_WIDTH (16U) #define GTM_gtm_cls0_DPLL_NMB_T_NMB_T(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NMB_T_NMB_T_SHIFT)) & GTM_gtm_cls0_DPLL_NMB_T_NMB_T_MASK) #define GTM_gtm_cls0_DPLL_NMB_T_NOT_USED_MASK (0xFF0000U) #define GTM_gtm_cls0_DPLL_NMB_T_NOT_USED_SHIFT (16U) #define GTM_gtm_cls0_DPLL_NMB_T_NOT_USED_WIDTH (8U) #define GTM_gtm_cls0_DPLL_NMB_T_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NMB_T_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NMB_T_NOT_USED_MASK) /*! @} */ /*! @name DPLL_NMB_S - Number of Pulses to be sent in Emergency Mode */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NMB_S_NMB_S_MASK (0xFFFFFU) #define GTM_gtm_cls0_DPLL_NMB_S_NMB_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NMB_S_NMB_S_WIDTH (20U) #define GTM_gtm_cls0_DPLL_NMB_S_NMB_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NMB_S_NMB_S_SHIFT)) & GTM_gtm_cls0_DPLL_NMB_S_NMB_S_MASK) #define GTM_gtm_cls0_DPLL_NMB_S_NOT_USED_MASK (0xF00000U) #define GTM_gtm_cls0_DPLL_NMB_S_NOT_USED_SHIFT (20U) #define GTM_gtm_cls0_DPLL_NMB_S_NOT_USED_WIDTH (4U) #define GTM_gtm_cls0_DPLL_NMB_S_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NMB_S_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_NMB_S_NOT_USED_MASK) /*! @} */ /*! @name DPLL_RDT_S0 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S0_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S0_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S0_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S0_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S0_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S0_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S1 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S1_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S1_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S1_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S1_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S1_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S1_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S2 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S2_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S2_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S2_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S2_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S2_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S2_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S3 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S3_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S3_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S3_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S3_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S3_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S3_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S4 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S4_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S4_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S4_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S4_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S4_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S4_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S5 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S5_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S5_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S5_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S5_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S5_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S5_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S6 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S6_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S6_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S6_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S6_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S6_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S6_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S7 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S7_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S7_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S7_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S7_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S7_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S7_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S8 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S8_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S8_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S8_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S8_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S8_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S8_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S9 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S9_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S9_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S9_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S9_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S9_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S9_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S10 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S10_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S10_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S10_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S10_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S10_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S10_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S11 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S11_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S11_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S11_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S11_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S11_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S11_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S12 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S12_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S12_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S12_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S12_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S12_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S12_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S13 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S13_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S13_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S13_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S13_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S13_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S13_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S14 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S14_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S14_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S14_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S14_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S14_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S14_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S15 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S15_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S15_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S15_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S15_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S15_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S15_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S16 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S16_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S16_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S16_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S16_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S16_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S16_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S17 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S17_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S17_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S17_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S17_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S17_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S17_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S18 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S18_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S18_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S18_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S18_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S18_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S18_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S19 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S19_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S19_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S19_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S19_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S19_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S19_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S20 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S20_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S20_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S20_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S20_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S20_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S20_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S21 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S21_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S21_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S21_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S21_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S21_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S21_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S22 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S22_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S22_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S22_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S22_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S22_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S22_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S23 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S23_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S23_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S23_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S23_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S23_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S23_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S24 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S24_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S24_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S24_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S24_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S24_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S24_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S25 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S25_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S25_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S25_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S25_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S25_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S25_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S26 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S26_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S26_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S26_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S26_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S26_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S26_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S27 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S27_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S27_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S27_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S27_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S27_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S27_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S28 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S28_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S28_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S28_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S28_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S28_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S28_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S29 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S29_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S29_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S29_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S29_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S29_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S29_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S30 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S30_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S30_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S30_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S30_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S30_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S30_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S31 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S31_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S31_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S31_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S31_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S31_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S31_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S32 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S32_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S32_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S32_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S32_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S32_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S32_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S33 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S33_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S33_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S33_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S33_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S33_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S33_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S34 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S34_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S34_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S34_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S34_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S34_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S34_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S35 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S35_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S35_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S35_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S35_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S35_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S35_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S36 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S36_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S36_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S36_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S36_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S36_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S36_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S37 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S37_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S37_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S37_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S37_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S37_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S37_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S38 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S38_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S38_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S38_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S38_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S38_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S38_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S39 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S39_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S39_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S39_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S39_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S39_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S39_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S40 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S40_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S40_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S40_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S40_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S40_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S40_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S41 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S41_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S41_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S41_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S41_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S41_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S41_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S42 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S42_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S42_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S42_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S42_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S42_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S42_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S43 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S43_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S43_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S43_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S43_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S43_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S43_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S44 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S44_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S44_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S44_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S44_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S44_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S44_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S45 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S45_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S45_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S45_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S45_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S45_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S45_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S46 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S46_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S46_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S46_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S46_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S46_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S46_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S47 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S47_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S47_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S47_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S47_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S47_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S47_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S48 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S48_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S48_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S48_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S48_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S48_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S48_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S49 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S49_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S49_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S49_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S49_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S49_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S49_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S50 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S50_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S50_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S50_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S50_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S50_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S50_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S51 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S51_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S51_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S51_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S51_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S51_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S51_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S52 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S52_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S52_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S52_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S52_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S52_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S52_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S53 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S53_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S53_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S53_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S53_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S53_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S53_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S54 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S54_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S54_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S54_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S54_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S54_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S54_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S55 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S55_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S55_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S55_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S55_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S55_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S55_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S56 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S56_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S56_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S56_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S56_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S56_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S56_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S57 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S57_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S57_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S57_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S57_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S57_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S57_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S58 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S58_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S58_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S58_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S58_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S58_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S58_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S59 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S59_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S59_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S59_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S59_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S59_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S59_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S60 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S60_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S60_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S60_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S60_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S60_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S60_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S61 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S61_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S61_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S61_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S61_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S61_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S61_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S62 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S62_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S62_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S62_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S62_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S62_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S62_RDT_S_MASK) /*! @} */ /*! @name DPLL_RDT_S63 - Reciprocal Values of the Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RDT_S63_RDT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RDT_S63_RDT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RDT_S63_RDT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RDT_S63_RDT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RDT_S63_RDT_S_SHIFT)) & GTM_gtm_cls0_DPLL_RDT_S63_RDT_S_MASK) /*! @} */ /*! @name DPLL_TSF_S0 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S0_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S0_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S0_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S0_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S0_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S0_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S1 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S1_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S1_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S1_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S1_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S1_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S1_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S2 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S2_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S2_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S2_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S2_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S2_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S2_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S3 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S3_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S3_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S3_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S3_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S3_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S3_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S4 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S4_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S4_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S4_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S4_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S4_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S4_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S5 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S5_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S5_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S5_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S5_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S5_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S5_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S6 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S6_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S6_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S6_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S6_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S6_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S6_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S7 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S7_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S7_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S7_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S7_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S7_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S7_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S8 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S8_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S8_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S8_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S8_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S8_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S8_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S9 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S9_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S9_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S9_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S9_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S9_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S9_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S10 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S10_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S10_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S10_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S10_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S10_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S10_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S11 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S11_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S11_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S11_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S11_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S11_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S11_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S12 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S12_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S12_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S12_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S12_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S12_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S12_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S13 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S13_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S13_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S13_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S13_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S13_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S13_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S14 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S14_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S14_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S14_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S14_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S14_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S14_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S15 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S15_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S15_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S15_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S15_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S15_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S15_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S16 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S16_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S16_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S16_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S16_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S16_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S16_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S17 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S17_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S17_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S17_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S17_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S17_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S17_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S18 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S18_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S18_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S18_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S18_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S18_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S18_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S19 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S19_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S19_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S19_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S19_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S19_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S19_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S20 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S20_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S20_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S20_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S20_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S20_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S20_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S21 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S21_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S21_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S21_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S21_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S21_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S21_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S22 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S22_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S22_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S22_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S22_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S22_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S22_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S23 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S23_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S23_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S23_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S23_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S23_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S23_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S24 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S24_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S24_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S24_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S24_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S24_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S24_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S25 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S25_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S25_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S25_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S25_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S25_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S25_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S26 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S26_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S26_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S26_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S26_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S26_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S26_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S27 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S27_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S27_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S27_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S27_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S27_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S27_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S28 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S28_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S28_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S28_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S28_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S28_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S28_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S29 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S29_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S29_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S29_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S29_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S29_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S29_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S30 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S30_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S30_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S30_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S30_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S30_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S30_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S31 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S31_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S31_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S31_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S31_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S31_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S31_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S32 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S32_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S32_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S32_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S32_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S32_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S32_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S33 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S33_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S33_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S33_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S33_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S33_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S33_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S34 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S34_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S34_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S34_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S34_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S34_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S34_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S35 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S35_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S35_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S35_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S35_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S35_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S35_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S36 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S36_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S36_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S36_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S36_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S36_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S36_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S37 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S37_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S37_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S37_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S37_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S37_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S37_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S38 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S38_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S38_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S38_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S38_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S38_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S38_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S39 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S39_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S39_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S39_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S39_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S39_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S39_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S40 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S40_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S40_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S40_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S40_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S40_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S40_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S41 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S41_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S41_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S41_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S41_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S41_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S41_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S42 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S42_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S42_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S42_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S42_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S42_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S42_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S43 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S43_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S43_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S43_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S43_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S43_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S43_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S44 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S44_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S44_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S44_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S44_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S44_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S44_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S45 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S45_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S45_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S45_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S45_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S45_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S45_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S46 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S46_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S46_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S46_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S46_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S46_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S46_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S47 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S47_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S47_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S47_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S47_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S47_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S47_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S48 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S48_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S48_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S48_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S48_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S48_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S48_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S49 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S49_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S49_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S49_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S49_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S49_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S49_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S50 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S50_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S50_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S50_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S50_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S50_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S50_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S51 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S51_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S51_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S51_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S51_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S51_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S51_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S52 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S52_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S52_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S52_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S52_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S52_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S52_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S53 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S53_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S53_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S53_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S53_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S53_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S53_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S54 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S54_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S54_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S54_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S54_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S54_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S54_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S55 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S55_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S55_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S55_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S55_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S55_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S55_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S56 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S56_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S56_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S56_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S56_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S56_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S56_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S57 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S57_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S57_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S57_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S57_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S57_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S57_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S58 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S58_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S58_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S58_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S58_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S58_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S58_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S59 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S59_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S59_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S59_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S59_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S59_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S59_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S60 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S60_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S60_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S60_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S60_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S60_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S60_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S61 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S61_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S61_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S61_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S61_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S61_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S61_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S62 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S62_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S62_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S62_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S62_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S62_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S62_TSF_S_MASK) /*! @} */ /*! @name DPLL_TSF_S63 - Time Stamp Values of the Nominal STATE Events in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSF_S63_TSF_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSF_S63_TSF_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSF_S63_TSF_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSF_S63_TSF_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSF_S63_TSF_S_SHIFT)) & GTM_gtm_cls0_DPLL_TSF_S63_TSF_S_MASK) /*! @} */ /*! @name DPLL_ADT_S0 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S0_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S0_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S0_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S0_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S0_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S0_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S0_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S0_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S0_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S0_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S0_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S0_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S0_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S0_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S0_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S0_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S0_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S0_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S1 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S1_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S1_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S1_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S1_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S1_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S1_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S1_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S1_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S1_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S1_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S1_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S1_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S1_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S1_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S1_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S1_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S1_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S1_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S2 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S2_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S2_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S2_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S2_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S2_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S2_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S2_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S2_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S2_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S2_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S2_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S2_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S2_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S2_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S2_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S2_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S2_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S2_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S3 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S3_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S3_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S3_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S3_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S3_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S3_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S3_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S3_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S3_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S3_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S3_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S3_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S3_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S3_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S3_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S3_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S3_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S3_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S4 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S4_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S4_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S4_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S4_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S4_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S4_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S4_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S4_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S4_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S4_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S4_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S4_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S4_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S4_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S4_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S4_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S4_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S4_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S5 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S5_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S5_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S5_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S5_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S5_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S5_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S5_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S5_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S5_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S5_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S5_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S5_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S5_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S5_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S5_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S5_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S5_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S5_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S6 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S6_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S6_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S6_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S6_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S6_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S6_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S6_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S6_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S6_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S6_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S6_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S6_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S6_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S6_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S6_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S6_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S6_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S6_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S7 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S7_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S7_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S7_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S7_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S7_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S7_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S7_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S7_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S7_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S7_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S7_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S7_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S7_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S7_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S7_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S7_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S7_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S7_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S8 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S8_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S8_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S8_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S8_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S8_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S8_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S8_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S8_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S8_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S8_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S8_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S8_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S8_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S8_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S8_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S8_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S8_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S8_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S9 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S9_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S9_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S9_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S9_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S9_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S9_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S9_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S9_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S9_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S9_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S9_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S9_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S9_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S9_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S9_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S9_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S9_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S9_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S10 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S10_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S10_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S10_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S10_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S10_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S10_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S10_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S10_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S10_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S10_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S10_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S10_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S10_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S10_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S10_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S10_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S10_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S10_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S11 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S11_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S11_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S11_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S11_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S11_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S11_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S11_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S11_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S11_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S11_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S11_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S11_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S11_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S11_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S11_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S11_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S11_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S11_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S12 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S12_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S12_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S12_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S12_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S12_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S12_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S12_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S12_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S12_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S12_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S12_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S12_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S12_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S12_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S12_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S12_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S12_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S12_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S13 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S13_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S13_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S13_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S13_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S13_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S13_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S13_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S13_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S13_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S13_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S13_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S13_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S13_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S13_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S13_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S13_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S13_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S13_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S14 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S14_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S14_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S14_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S14_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S14_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S14_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S14_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S14_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S14_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S14_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S14_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S14_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S14_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S14_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S14_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S14_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S14_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S14_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S15 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S15_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S15_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S15_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S15_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S15_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S15_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S15_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S15_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S15_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S15_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S15_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S15_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S15_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S15_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S15_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S15_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S15_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S15_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S16 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S16_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S16_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S16_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S16_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S16_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S16_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S16_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S16_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S16_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S16_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S16_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S16_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S16_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S16_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S16_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S16_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S16_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S16_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S17 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S17_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S17_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S17_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S17_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S17_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S17_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S17_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S17_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S17_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S17_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S17_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S17_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S17_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S17_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S17_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S17_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S17_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S17_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S18 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S18_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S18_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S18_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S18_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S18_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S18_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S18_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S18_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S18_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S18_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S18_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S18_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S18_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S18_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S18_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S18_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S18_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S18_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S19 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S19_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S19_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S19_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S19_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S19_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S19_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S19_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S19_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S19_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S19_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S19_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S19_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S19_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S19_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S19_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S19_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S19_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S19_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S20 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S20_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S20_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S20_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S20_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S20_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S20_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S20_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S20_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S20_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S20_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S20_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S20_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S20_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S20_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S20_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S20_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S20_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S20_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S21 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S21_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S21_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S21_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S21_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S21_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S21_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S21_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S21_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S21_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S21_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S21_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S21_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S21_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S21_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S21_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S21_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S21_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S21_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S22 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S22_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S22_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S22_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S22_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S22_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S22_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S22_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S22_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S22_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S22_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S22_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S22_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S22_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S22_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S22_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S22_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S22_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S22_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S23 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S23_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S23_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S23_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S23_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S23_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S23_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S23_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S23_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S23_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S23_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S23_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S23_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S23_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S23_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S23_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S23_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S23_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S23_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S24 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S24_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S24_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S24_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S24_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S24_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S24_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S24_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S24_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S24_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S24_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S24_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S24_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S24_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S24_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S24_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S24_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S24_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S24_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S25 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S25_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S25_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S25_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S25_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S25_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S25_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S25_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S25_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S25_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S25_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S25_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S25_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S25_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S25_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S25_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S25_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S25_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S25_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S26 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S26_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S26_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S26_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S26_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S26_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S26_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S26_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S26_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S26_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S26_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S26_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S26_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S26_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S26_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S26_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S26_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S26_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S26_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S27 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S27_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S27_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S27_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S27_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S27_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S27_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S27_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S27_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S27_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S27_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S27_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S27_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S27_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S27_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S27_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S27_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S27_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S27_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S28 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S28_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S28_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S28_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S28_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S28_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S28_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S28_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S28_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S28_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S28_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S28_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S28_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S28_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S28_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S28_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S28_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S28_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S28_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S29 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S29_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S29_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S29_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S29_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S29_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S29_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S29_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S29_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S29_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S29_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S29_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S29_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S29_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S29_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S29_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S29_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S29_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S29_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S30 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S30_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S30_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S30_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S30_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S30_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S30_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S30_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S30_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S30_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S30_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S30_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S30_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S30_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S30_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S30_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S30_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S30_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S30_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S31 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S31_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S31_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S31_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S31_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S31_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S31_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S31_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S31_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S31_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S31_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S31_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S31_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S31_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S31_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S31_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S31_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S31_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S31_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S32 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S32_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S32_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S32_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S32_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S32_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S32_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S32_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S32_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S32_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S32_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S32_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S32_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S32_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S32_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S32_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S32_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S32_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S32_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S33 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S33_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S33_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S33_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S33_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S33_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S33_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S33_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S33_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S33_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S33_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S33_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S33_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S33_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S33_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S33_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S33_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S33_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S33_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S34 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S34_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S34_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S34_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S34_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S34_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S34_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S34_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S34_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S34_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S34_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S34_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S34_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S34_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S34_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S34_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S34_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S34_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S34_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S35 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S35_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S35_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S35_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S35_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S35_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S35_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S35_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S35_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S35_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S35_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S35_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S35_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S35_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S35_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S35_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S35_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S35_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S35_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S36 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S36_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S36_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S36_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S36_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S36_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S36_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S36_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S36_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S36_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S36_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S36_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S36_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S36_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S36_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S36_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S36_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S36_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S36_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S37 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S37_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S37_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S37_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S37_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S37_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S37_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S37_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S37_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S37_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S37_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S37_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S37_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S37_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S37_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S37_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S37_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S37_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S37_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S38 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S38_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S38_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S38_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S38_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S38_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S38_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S38_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S38_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S38_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S38_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S38_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S38_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S38_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S38_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S38_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S38_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S38_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S38_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S39 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S39_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S39_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S39_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S39_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S39_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S39_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S39_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S39_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S39_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S39_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S39_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S39_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S39_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S39_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S39_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S39_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S39_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S39_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S40 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S40_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S40_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S40_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S40_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S40_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S40_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S40_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S40_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S40_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S40_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S40_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S40_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S40_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S40_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S40_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S40_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S40_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S40_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S41 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S41_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S41_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S41_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S41_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S41_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S41_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S41_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S41_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S41_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S41_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S41_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S41_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S41_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S41_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S41_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S41_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S41_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S41_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S42 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S42_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S42_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S42_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S42_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S42_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S42_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S42_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S42_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S42_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S42_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S42_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S42_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S42_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S42_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S42_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S42_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S42_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S42_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S43 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S43_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S43_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S43_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S43_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S43_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S43_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S43_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S43_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S43_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S43_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S43_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S43_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S43_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S43_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S43_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S43_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S43_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S43_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S44 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S44_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S44_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S44_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S44_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S44_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S44_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S44_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S44_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S44_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S44_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S44_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S44_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S44_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S44_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S44_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S44_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S44_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S44_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S45 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S45_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S45_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S45_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S45_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S45_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S45_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S45_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S45_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S45_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S45_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S45_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S45_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S45_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S45_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S45_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S45_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S45_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S45_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S46 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S46_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S46_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S46_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S46_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S46_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S46_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S46_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S46_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S46_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S46_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S46_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S46_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S46_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S46_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S46_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S46_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S46_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S46_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S47 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S47_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S47_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S47_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S47_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S47_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S47_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S47_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S47_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S47_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S47_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S47_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S47_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S47_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S47_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S47_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S47_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S47_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S47_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S48 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S48_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S48_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S48_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S48_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S48_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S48_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S48_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S48_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S48_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S48_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S48_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S48_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S48_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S48_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S48_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S48_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S48_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S48_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S49 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S49_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S49_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S49_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S49_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S49_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S49_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S49_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S49_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S49_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S49_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S49_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S49_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S49_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S49_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S49_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S49_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S49_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S49_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S50 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S50_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S50_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S50_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S50_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S50_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S50_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S50_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S50_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S50_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S50_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S50_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S50_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S50_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S50_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S50_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S50_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S50_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S50_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S51 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S51_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S51_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S51_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S51_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S51_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S51_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S51_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S51_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S51_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S51_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S51_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S51_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S51_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S51_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S51_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S51_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S51_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S51_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S52 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S52_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S52_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S52_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S52_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S52_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S52_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S52_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S52_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S52_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S52_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S52_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S52_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S52_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S52_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S52_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S52_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S52_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S52_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S53 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S53_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S53_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S53_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S53_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S53_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S53_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S53_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S53_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S53_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S53_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S53_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S53_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S53_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S53_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S53_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S53_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S53_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S53_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S54 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S54_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S54_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S54_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S54_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S54_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S54_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S54_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S54_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S54_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S54_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S54_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S54_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S54_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S54_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S54_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S54_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S54_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S54_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S55 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S55_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S55_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S55_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S55_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S55_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S55_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S55_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S55_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S55_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S55_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S55_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S55_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S55_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S55_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S55_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S55_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S55_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S55_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S56 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S56_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S56_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S56_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S56_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S56_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S56_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S56_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S56_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S56_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S56_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S56_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S56_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S56_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S56_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S56_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S56_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S56_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S56_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S57 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S57_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S57_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S57_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S57_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S57_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S57_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S57_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S57_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S57_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S57_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S57_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S57_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S57_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S57_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S57_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S57_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S57_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S57_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S58 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S58_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S58_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S58_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S58_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S58_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S58_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S58_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S58_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S58_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S58_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S58_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S58_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S58_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S58_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S58_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S58_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S58_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S58_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S59 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S59_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S59_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S59_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S59_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S59_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S59_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S59_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S59_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S59_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S59_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S59_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S59_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S59_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S59_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S59_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S59_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S59_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S59_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S60 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S60_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S60_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S60_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S60_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S60_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S60_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S60_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S60_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S60_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S60_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S60_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S60_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S60_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S60_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S60_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S60_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S60_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S60_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S61 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S61_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S61_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S61_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S61_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S61_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S61_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S61_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S61_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S61_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S61_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S61_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S61_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S61_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S61_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S61_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S61_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S61_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S61_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S62 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S62_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S62_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S62_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S62_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S62_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S62_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S62_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S62_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S62_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S62_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S62_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S62_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S62_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S62_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S62_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S62_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S62_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S62_NOT_USED_MASK) /*! @} */ /*! @name DPLL_ADT_S63 - Adapt and Profile Values of the STATE Increments in FULL_SCALE for maximum [p] entries */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ADT_S63_PD_S_MASK (0xFFFFU) #define GTM_gtm_cls0_DPLL_ADT_S63_PD_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ADT_S63_PD_S_WIDTH (16U) #define GTM_gtm_cls0_DPLL_ADT_S63_PD_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S63_PD_S_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S63_PD_S_MASK) #define GTM_gtm_cls0_DPLL_ADT_S63_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_ADT_S63_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ADT_S63_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_ADT_S63_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S63_NS_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S63_NS_MASK) #define GTM_gtm_cls0_DPLL_ADT_S63_NOT_USED_MASK (0xC00000U) #define GTM_gtm_cls0_DPLL_ADT_S63_NOT_USED_SHIFT (22U) #define GTM_gtm_cls0_DPLL_ADT_S63_NOT_USED_WIDTH (2U) #define GTM_gtm_cls0_DPLL_ADT_S63_NOT_USED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ADT_S63_NOT_USED_SHIFT)) & GTM_gtm_cls0_DPLL_ADT_S63_NOT_USED_MASK) /*! @} */ /*! @name DPLL_DT_S0 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S0_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S0_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S0_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S0_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S0_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S0_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S1 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S1_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S1_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S1_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S1_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S1_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S1_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S2 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S2_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S2_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S2_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S2_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S2_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S2_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S3 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S3_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S3_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S3_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S3_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S3_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S3_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S4 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S4_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S4_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S4_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S4_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S4_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S4_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S5 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S5_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S5_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S5_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S5_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S5_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S5_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S6 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S6_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S6_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S6_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S6_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S6_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S6_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S7 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S7_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S7_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S7_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S7_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S7_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S7_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S8 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S8_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S8_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S8_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S8_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S8_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S8_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S9 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S9_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S9_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S9_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S9_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S9_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S9_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S10 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S10_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S10_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S10_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S10_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S10_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S10_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S11 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S11_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S11_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S11_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S11_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S11_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S11_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S12 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S12_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S12_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S12_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S12_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S12_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S12_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S13 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S13_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S13_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S13_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S13_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S13_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S13_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S14 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S14_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S14_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S14_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S14_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S14_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S14_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S15 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S15_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S15_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S15_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S15_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S15_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S15_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S16 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S16_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S16_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S16_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S16_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S16_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S16_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S17 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S17_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S17_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S17_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S17_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S17_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S17_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S18 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S18_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S18_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S18_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S18_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S18_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S18_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S19 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S19_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S19_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S19_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S19_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S19_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S19_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S20 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S20_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S20_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S20_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S20_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S20_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S20_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S21 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S21_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S21_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S21_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S21_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S21_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S21_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S22 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S22_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S22_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S22_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S22_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S22_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S22_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S23 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S23_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S23_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S23_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S23_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S23_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S23_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S24 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S24_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S24_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S24_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S24_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S24_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S24_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S25 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S25_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S25_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S25_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S25_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S25_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S25_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S26 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S26_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S26_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S26_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S26_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S26_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S26_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S27 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S27_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S27_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S27_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S27_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S27_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S27_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S28 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S28_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S28_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S28_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S28_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S28_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S28_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S29 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S29_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S29_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S29_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S29_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S29_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S29_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S30 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S30_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S30_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S30_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S30_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S30_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S30_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S31 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S31_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S31_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S31_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S31_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S31_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S31_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S32 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S32_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S32_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S32_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S32_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S32_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S32_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S33 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S33_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S33_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S33_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S33_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S33_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S33_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S34 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S34_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S34_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S34_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S34_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S34_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S34_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S35 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S35_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S35_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S35_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S35_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S35_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S35_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S36 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S36_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S36_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S36_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S36_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S36_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S36_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S37 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S37_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S37_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S37_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S37_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S37_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S37_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S38 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S38_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S38_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S38_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S38_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S38_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S38_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S39 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S39_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S39_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S39_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S39_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S39_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S39_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S40 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S40_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S40_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S40_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S40_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S40_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S40_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S41 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S41_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S41_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S41_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S41_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S41_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S41_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S42 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S42_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S42_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S42_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S42_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S42_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S42_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S43 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S43_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S43_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S43_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S43_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S43_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S43_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S44 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S44_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S44_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S44_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S44_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S44_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S44_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S45 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S45_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S45_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S45_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S45_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S45_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S45_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S46 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S46_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S46_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S46_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S46_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S46_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S46_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S47 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S47_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S47_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S47_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S47_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S47_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S47_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S48 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S48_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S48_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S48_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S48_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S48_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S48_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S49 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S49_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S49_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S49_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S49_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S49_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S49_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S50 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S50_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S50_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S50_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S50_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S50_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S50_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S51 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S51_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S51_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S51_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S51_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S51_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S51_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S52 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S52_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S52_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S52_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S52_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S52_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S52_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S53 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S53_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S53_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S53_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S53_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S53_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S53_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S54 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S54_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S54_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S54_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S54_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S54_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S54_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S55 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S55_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S55_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S55_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S55_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S55_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S55_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S56 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S56_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S56_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S56_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S56_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S56_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S56_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S57 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S57_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S57_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S57_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S57_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S57_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S57_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S58 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S58_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S58_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S58_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S58_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S58_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S58_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S59 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S59_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S59_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S59_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S59_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S59_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S59_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S60 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S60_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S60_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S60_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S60_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S60_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S60_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S61 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S61_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S61_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S61_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S61_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S61_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S61_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S62 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S62_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S62_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S62_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S62_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S62_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S62_DT_S_MASK) /*! @} */ /*! @name DPLL_DT_S63 - Nominal STATE Increment Duration in FULL_SCALE for maximum [p] entries in profile for STATE (DPLL_ADT_S[p]) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S63_DT_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S63_DT_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S63_DT_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S63_DT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S63_DT_S_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S63_DT_S_MASK) /*! @} */ /*! @name DPLL_TSAC0 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC0_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC0_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC0_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC0_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC0_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC0_TSAC_MASK) /*! @} */ /*! @name DPLL_TSAC1 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC1_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC1_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC1_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC1_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC1_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC1_TSAC_MASK) /*! @} */ /*! @name DPLL_TSAC2 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC2_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC2_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC2_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC2_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC2_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC2_TSAC_MASK) /*! @} */ /*! @name DPLL_TSAC3 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC3_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC3_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC3_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC3_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC3_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC3_TSAC_MASK) /*! @} */ /*! @name DPLL_TSAC4 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC4_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC4_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC4_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC4_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC4_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC4_TSAC_MASK) /*! @} */ /*! @name DPLL_TSAC5 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC5_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC5_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC5_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC5_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC5_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC5_TSAC_MASK) /*! @} */ /*! @name DPLL_TSAC6 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC6_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC6_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC6_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC6_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC6_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC6_TSAC_MASK) /*! @} */ /*! @name DPLL_TSAC7 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC7_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC7_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC7_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC7_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC7_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC7_TSAC_MASK) /*! @} */ /*! @name DPLL_TSAC8 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC8_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC8_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC8_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC8_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC8_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC8_TSAC_MASK) /*! @} */ /*! @name DPLL_TSAC9 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC9_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC9_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC9_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC9_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC9_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC9_TSAC_MASK) /*! @} */ /*! @name DPLL_TSAC10 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC10_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC10_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC10_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC10_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC10_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC10_TSAC_MASK) /*! @} */ /*! @name DPLL_TSAC11 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC11_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC11_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC11_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC11_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC11_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC11_TSAC_MASK) /*! @} */ /*! @name DPLL_TSAC12 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC12_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC12_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC12_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC12_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC12_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC12_TSAC_MASK) /*! @} */ /*! @name DPLL_TSAC13 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC13_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC13_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC13_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC13_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC13_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC13_TSAC_MASK) /*! @} */ /*! @name DPLL_TSAC14 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC14_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC14_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC14_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC14_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC14_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC14_TSAC_MASK) /*! @} */ /*! @name DPLL_TSAC15 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC15_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC15_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC15_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC15_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC15_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC15_TSAC_MASK) /*! @} */ /*! @name DPLL_TSAC16 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC16_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC16_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC16_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC16_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC16_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC16_TSAC_MASK) /*! @} */ /*! @name DPLL_TSAC17 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC17_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC17_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC17_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC17_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC17_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC17_TSAC_MASK) /*! @} */ /*! @name DPLL_TSAC18 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC18_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC18_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC18_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC18_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC18_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC18_TSAC_MASK) /*! @} */ /*! @name DPLL_TSAC19 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC19_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC19_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC19_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC19_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC19_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC19_TSAC_MASK) /*! @} */ /*! @name DPLL_TSAC20 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC20_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC20_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC20_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC20_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC20_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC20_TSAC_MASK) /*! @} */ /*! @name DPLL_TSAC21 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC21_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC21_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC21_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC21_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC21_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC21_TSAC_MASK) /*! @} */ /*! @name DPLL_TSAC22 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC22_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC22_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC22_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC22_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC22_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC22_TSAC_MASK) /*! @} */ /*! @name DPLL_TSAC23 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC23_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC23_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC23_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC23_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC23_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC23_TSAC_MASK) /*! @} */ /*! @name DPLL_TSAC24 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC24_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC24_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC24_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC24_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC24_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC24_TSAC_MASK) /*! @} */ /*! @name DPLL_TSAC25 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC25_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC25_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC25_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC25_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC25_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC25_TSAC_MASK) /*! @} */ /*! @name DPLL_TSAC26 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC26_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC26_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC26_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC26_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC26_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC26_TSAC_MASK) /*! @} */ /*! @name DPLL_TSAC27 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC27_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC27_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC27_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC27_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC27_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC27_TSAC_MASK) /*! @} */ /*! @name DPLL_TSAC28 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC28_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC28_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC28_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC28_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC28_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC28_TSAC_MASK) /*! @} */ /*! @name DPLL_TSAC29 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC29_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC29_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC29_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC29_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC29_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC29_TSAC_MASK) /*! @} */ /*! @name DPLL_TSAC30 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC30_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC30_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC30_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC30_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC30_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC30_TSAC_MASK) /*! @} */ /*! @name DPLL_TSAC31 - Calculated Time Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TSAC31_TSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TSAC31_TSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TSAC31_TSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TSAC31_TSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TSAC31_TSAC_SHIFT)) & GTM_gtm_cls0_DPLL_TSAC31_TSAC_MASK) /*! @} */ /*! @name DPLL_PSAC0 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC0_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC0_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC0_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC0_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC0_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC0_PSAC_MASK) /*! @} */ /*! @name DPLL_PSAC1 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC1_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC1_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC1_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC1_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC1_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC1_PSAC_MASK) /*! @} */ /*! @name DPLL_PSAC2 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC2_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC2_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC2_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC2_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC2_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC2_PSAC_MASK) /*! @} */ /*! @name DPLL_PSAC3 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC3_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC3_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC3_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC3_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC3_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC3_PSAC_MASK) /*! @} */ /*! @name DPLL_PSAC4 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC4_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC4_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC4_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC4_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC4_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC4_PSAC_MASK) /*! @} */ /*! @name DPLL_PSAC5 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC5_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC5_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC5_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC5_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC5_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC5_PSAC_MASK) /*! @} */ /*! @name DPLL_PSAC6 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC6_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC6_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC6_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC6_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC6_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC6_PSAC_MASK) /*! @} */ /*! @name DPLL_PSAC7 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC7_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC7_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC7_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC7_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC7_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC7_PSAC_MASK) /*! @} */ /*! @name DPLL_PSAC8 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC8_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC8_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC8_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC8_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC8_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC8_PSAC_MASK) /*! @} */ /*! @name DPLL_PSAC9 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC9_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC9_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC9_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC9_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC9_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC9_PSAC_MASK) /*! @} */ /*! @name DPLL_PSAC10 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC10_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC10_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC10_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC10_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC10_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC10_PSAC_MASK) /*! @} */ /*! @name DPLL_PSAC11 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC11_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC11_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC11_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC11_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC11_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC11_PSAC_MASK) /*! @} */ /*! @name DPLL_PSAC12 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC12_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC12_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC12_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC12_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC12_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC12_PSAC_MASK) /*! @} */ /*! @name DPLL_PSAC13 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC13_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC13_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC13_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC13_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC13_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC13_PSAC_MASK) /*! @} */ /*! @name DPLL_PSAC14 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC14_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC14_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC14_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC14_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC14_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC14_PSAC_MASK) /*! @} */ /*! @name DPLL_PSAC15 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC15_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC15_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC15_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC15_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC15_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC15_PSAC_MASK) /*! @} */ /*! @name DPLL_PSAC16 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC16_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC16_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC16_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC16_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC16_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC16_PSAC_MASK) /*! @} */ /*! @name DPLL_PSAC17 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC17_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC17_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC17_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC17_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC17_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC17_PSAC_MASK) /*! @} */ /*! @name DPLL_PSAC18 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC18_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC18_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC18_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC18_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC18_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC18_PSAC_MASK) /*! @} */ /*! @name DPLL_PSAC19 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC19_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC19_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC19_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC19_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC19_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC19_PSAC_MASK) /*! @} */ /*! @name DPLL_PSAC20 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC20_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC20_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC20_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC20_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC20_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC20_PSAC_MASK) /*! @} */ /*! @name DPLL_PSAC21 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC21_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC21_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC21_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC21_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC21_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC21_PSAC_MASK) /*! @} */ /*! @name DPLL_PSAC22 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC22_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC22_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC22_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC22_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC22_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC22_PSAC_MASK) /*! @} */ /*! @name DPLL_PSAC23 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC23_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC23_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC23_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC23_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC23_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC23_PSAC_MASK) /*! @} */ /*! @name DPLL_PSAC24 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC24_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC24_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC24_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC24_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC24_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC24_PSAC_MASK) /*! @} */ /*! @name DPLL_PSAC25 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC25_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC25_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC25_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC25_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC25_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC25_PSAC_MASK) /*! @} */ /*! @name DPLL_PSAC26 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC26_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC26_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC26_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC26_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC26_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC26_PSAC_MASK) /*! @} */ /*! @name DPLL_PSAC27 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC27_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC27_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC27_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC27_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC27_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC27_PSAC_MASK) /*! @} */ /*! @name DPLL_PSAC28 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC28_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC28_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC28_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC28_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC28_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC28_PSAC_MASK) /*! @} */ /*! @name DPLL_PSAC29 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC29_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC29_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC29_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC29_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC29_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC29_PSAC_MASK) /*! @} */ /*! @name DPLL_PSAC30 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC30_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC30_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC30_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC30_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC30_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC30_PSAC_MASK) /*! @} */ /*! @name DPLL_PSAC31 - Calculated Position Value to start Action [n] */ /*! @{ */ #define GTM_gtm_cls0_DPLL_PSAC31_PSAC_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_PSAC31_PSAC_SHIFT (0U) #define GTM_gtm_cls0_DPLL_PSAC31_PSAC_WIDTH (24U) #define GTM_gtm_cls0_DPLL_PSAC31_PSAC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_PSAC31_PSAC_SHIFT)) & GTM_gtm_cls0_DPLL_PSAC31_PSAC_MASK) /*! @} */ /*! @name DPLL_ACB_0 - Control Bits for NOAC Actions */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ACB_0_ACB_0_MASK (0x1FU) #define GTM_gtm_cls0_DPLL_ACB_0_ACB_0_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ACB_0_ACB_0_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_0_ACB_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_0_ACB_0_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_0_ACB_0_MASK) #define GTM_gtm_cls0_DPLL_ACB_0_ACB_1_MASK (0x1F00U) #define GTM_gtm_cls0_DPLL_ACB_0_ACB_1_SHIFT (8U) #define GTM_gtm_cls0_DPLL_ACB_0_ACB_1_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_0_ACB_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_0_ACB_1_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_0_ACB_1_MASK) #define GTM_gtm_cls0_DPLL_ACB_0_ACB_2_MASK (0x1F0000U) #define GTM_gtm_cls0_DPLL_ACB_0_ACB_2_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ACB_0_ACB_2_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_0_ACB_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_0_ACB_2_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_0_ACB_2_MASK) #define GTM_gtm_cls0_DPLL_ACB_0_ACB_3_MASK (0x1F000000U) #define GTM_gtm_cls0_DPLL_ACB_0_ACB_3_SHIFT (24U) #define GTM_gtm_cls0_DPLL_ACB_0_ACB_3_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_0_ACB_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_0_ACB_3_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_0_ACB_3_MASK) /*! @} */ /*! @name DPLL_ACB_1 - Control Bits for NOAC Actions */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ACB_1_ACB_0_MASK (0x1FU) #define GTM_gtm_cls0_DPLL_ACB_1_ACB_0_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ACB_1_ACB_0_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_1_ACB_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_1_ACB_0_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_1_ACB_0_MASK) #define GTM_gtm_cls0_DPLL_ACB_1_ACB_1_MASK (0x1F00U) #define GTM_gtm_cls0_DPLL_ACB_1_ACB_1_SHIFT (8U) #define GTM_gtm_cls0_DPLL_ACB_1_ACB_1_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_1_ACB_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_1_ACB_1_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_1_ACB_1_MASK) #define GTM_gtm_cls0_DPLL_ACB_1_ACB_2_MASK (0x1F0000U) #define GTM_gtm_cls0_DPLL_ACB_1_ACB_2_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ACB_1_ACB_2_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_1_ACB_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_1_ACB_2_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_1_ACB_2_MASK) #define GTM_gtm_cls0_DPLL_ACB_1_ACB_3_MASK (0x1F000000U) #define GTM_gtm_cls0_DPLL_ACB_1_ACB_3_SHIFT (24U) #define GTM_gtm_cls0_DPLL_ACB_1_ACB_3_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_1_ACB_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_1_ACB_3_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_1_ACB_3_MASK) /*! @} */ /*! @name DPLL_ACB_2 - Control Bits for NOAC Actions */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ACB_2_ACB_0_MASK (0x1FU) #define GTM_gtm_cls0_DPLL_ACB_2_ACB_0_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ACB_2_ACB_0_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_2_ACB_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_2_ACB_0_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_2_ACB_0_MASK) #define GTM_gtm_cls0_DPLL_ACB_2_ACB_1_MASK (0x1F00U) #define GTM_gtm_cls0_DPLL_ACB_2_ACB_1_SHIFT (8U) #define GTM_gtm_cls0_DPLL_ACB_2_ACB_1_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_2_ACB_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_2_ACB_1_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_2_ACB_1_MASK) #define GTM_gtm_cls0_DPLL_ACB_2_ACB_2_MASK (0x1F0000U) #define GTM_gtm_cls0_DPLL_ACB_2_ACB_2_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ACB_2_ACB_2_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_2_ACB_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_2_ACB_2_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_2_ACB_2_MASK) #define GTM_gtm_cls0_DPLL_ACB_2_ACB_3_MASK (0x1F000000U) #define GTM_gtm_cls0_DPLL_ACB_2_ACB_3_SHIFT (24U) #define GTM_gtm_cls0_DPLL_ACB_2_ACB_3_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_2_ACB_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_2_ACB_3_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_2_ACB_3_MASK) /*! @} */ /*! @name DPLL_ACB_3 - Control Bits for NOAC Actions */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ACB_3_ACB_0_MASK (0x1FU) #define GTM_gtm_cls0_DPLL_ACB_3_ACB_0_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ACB_3_ACB_0_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_3_ACB_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_3_ACB_0_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_3_ACB_0_MASK) #define GTM_gtm_cls0_DPLL_ACB_3_ACB_1_MASK (0x1F00U) #define GTM_gtm_cls0_DPLL_ACB_3_ACB_1_SHIFT (8U) #define GTM_gtm_cls0_DPLL_ACB_3_ACB_1_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_3_ACB_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_3_ACB_1_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_3_ACB_1_MASK) #define GTM_gtm_cls0_DPLL_ACB_3_ACB_2_MASK (0x1F0000U) #define GTM_gtm_cls0_DPLL_ACB_3_ACB_2_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ACB_3_ACB_2_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_3_ACB_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_3_ACB_2_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_3_ACB_2_MASK) #define GTM_gtm_cls0_DPLL_ACB_3_ACB_3_MASK (0x1F000000U) #define GTM_gtm_cls0_DPLL_ACB_3_ACB_3_SHIFT (24U) #define GTM_gtm_cls0_DPLL_ACB_3_ACB_3_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_3_ACB_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_3_ACB_3_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_3_ACB_3_MASK) /*! @} */ /*! @name DPLL_ACB_4 - Control Bits for NOAC Actions */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ACB_4_ACB_0_MASK (0x1FU) #define GTM_gtm_cls0_DPLL_ACB_4_ACB_0_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ACB_4_ACB_0_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_4_ACB_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_4_ACB_0_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_4_ACB_0_MASK) #define GTM_gtm_cls0_DPLL_ACB_4_ACB_1_MASK (0x1F00U) #define GTM_gtm_cls0_DPLL_ACB_4_ACB_1_SHIFT (8U) #define GTM_gtm_cls0_DPLL_ACB_4_ACB_1_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_4_ACB_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_4_ACB_1_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_4_ACB_1_MASK) #define GTM_gtm_cls0_DPLL_ACB_4_ACB_2_MASK (0x1F0000U) #define GTM_gtm_cls0_DPLL_ACB_4_ACB_2_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ACB_4_ACB_2_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_4_ACB_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_4_ACB_2_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_4_ACB_2_MASK) #define GTM_gtm_cls0_DPLL_ACB_4_ACB_3_MASK (0x1F000000U) #define GTM_gtm_cls0_DPLL_ACB_4_ACB_3_SHIFT (24U) #define GTM_gtm_cls0_DPLL_ACB_4_ACB_3_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_4_ACB_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_4_ACB_3_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_4_ACB_3_MASK) /*! @} */ /*! @name DPLL_ACB_5 - Control Bits for NOAC Actions */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ACB_5_ACB_0_MASK (0x1FU) #define GTM_gtm_cls0_DPLL_ACB_5_ACB_0_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ACB_5_ACB_0_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_5_ACB_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_5_ACB_0_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_5_ACB_0_MASK) #define GTM_gtm_cls0_DPLL_ACB_5_ACB_1_MASK (0x1F00U) #define GTM_gtm_cls0_DPLL_ACB_5_ACB_1_SHIFT (8U) #define GTM_gtm_cls0_DPLL_ACB_5_ACB_1_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_5_ACB_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_5_ACB_1_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_5_ACB_1_MASK) #define GTM_gtm_cls0_DPLL_ACB_5_ACB_2_MASK (0x1F0000U) #define GTM_gtm_cls0_DPLL_ACB_5_ACB_2_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ACB_5_ACB_2_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_5_ACB_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_5_ACB_2_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_5_ACB_2_MASK) #define GTM_gtm_cls0_DPLL_ACB_5_ACB_3_MASK (0x1F000000U) #define GTM_gtm_cls0_DPLL_ACB_5_ACB_3_SHIFT (24U) #define GTM_gtm_cls0_DPLL_ACB_5_ACB_3_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_5_ACB_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_5_ACB_3_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_5_ACB_3_MASK) /*! @} */ /*! @name DPLL_ACB_6 - Control Bits for NOAC Actions */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ACB_6_ACB_0_MASK (0x1FU) #define GTM_gtm_cls0_DPLL_ACB_6_ACB_0_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ACB_6_ACB_0_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_6_ACB_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_6_ACB_0_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_6_ACB_0_MASK) #define GTM_gtm_cls0_DPLL_ACB_6_ACB_1_MASK (0x1F00U) #define GTM_gtm_cls0_DPLL_ACB_6_ACB_1_SHIFT (8U) #define GTM_gtm_cls0_DPLL_ACB_6_ACB_1_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_6_ACB_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_6_ACB_1_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_6_ACB_1_MASK) #define GTM_gtm_cls0_DPLL_ACB_6_ACB_2_MASK (0x1F0000U) #define GTM_gtm_cls0_DPLL_ACB_6_ACB_2_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ACB_6_ACB_2_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_6_ACB_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_6_ACB_2_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_6_ACB_2_MASK) #define GTM_gtm_cls0_DPLL_ACB_6_ACB_3_MASK (0x1F000000U) #define GTM_gtm_cls0_DPLL_ACB_6_ACB_3_SHIFT (24U) #define GTM_gtm_cls0_DPLL_ACB_6_ACB_3_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_6_ACB_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_6_ACB_3_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_6_ACB_3_MASK) /*! @} */ /*! @name DPLL_ACB_7 - Control Bits for NOAC Actions */ /*! @{ */ #define GTM_gtm_cls0_DPLL_ACB_7_ACB_0_MASK (0x1FU) #define GTM_gtm_cls0_DPLL_ACB_7_ACB_0_SHIFT (0U) #define GTM_gtm_cls0_DPLL_ACB_7_ACB_0_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_7_ACB_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_7_ACB_0_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_7_ACB_0_MASK) #define GTM_gtm_cls0_DPLL_ACB_7_ACB_1_MASK (0x1F00U) #define GTM_gtm_cls0_DPLL_ACB_7_ACB_1_SHIFT (8U) #define GTM_gtm_cls0_DPLL_ACB_7_ACB_1_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_7_ACB_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_7_ACB_1_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_7_ACB_1_MASK) #define GTM_gtm_cls0_DPLL_ACB_7_ACB_2_MASK (0x1F0000U) #define GTM_gtm_cls0_DPLL_ACB_7_ACB_2_SHIFT (16U) #define GTM_gtm_cls0_DPLL_ACB_7_ACB_2_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_7_ACB_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_7_ACB_2_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_7_ACB_2_MASK) #define GTM_gtm_cls0_DPLL_ACB_7_ACB_3_MASK (0x1F000000U) #define GTM_gtm_cls0_DPLL_ACB_7_ACB_3_SHIFT (24U) #define GTM_gtm_cls0_DPLL_ACB_7_ACB_3_WIDTH (5U) #define GTM_gtm_cls0_DPLL_ACB_7_ACB_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_ACB_7_ACB_3_SHIFT)) & GTM_gtm_cls0_DPLL_ACB_7_ACB_3_MASK) /*! @} */ /*! @name DPLL_CTRL_11 - Control Register 11 */ /*! @{ */ #define GTM_gtm_cls0_DPLL_CTRL_11_SIP1_MASK (0x1U) #define GTM_gtm_cls0_DPLL_CTRL_11_SIP1_SHIFT (0U) #define GTM_gtm_cls0_DPLL_CTRL_11_SIP1_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_SIP1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_SIP1_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_SIP1_MASK) #define GTM_gtm_cls0_DPLL_CTRL_11_ERZ1_MASK (0x2U) #define GTM_gtm_cls0_DPLL_CTRL_11_ERZ1_SHIFT (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_ERZ1_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_ERZ1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_ERZ1_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_ERZ1_MASK) #define GTM_gtm_cls0_DPLL_CTRL_11_PCMF1_MASK (0x4U) #define GTM_gtm_cls0_DPLL_CTRL_11_PCMF1_SHIFT (2U) #define GTM_gtm_cls0_DPLL_CTRL_11_PCMF1_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_PCMF1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_PCMF1_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_PCMF1_MASK) #define GTM_gtm_cls0_DPLL_CTRL_11_FSYL1_MASK (0x8U) #define GTM_gtm_cls0_DPLL_CTRL_11_FSYL1_SHIFT (3U) #define GTM_gtm_cls0_DPLL_CTRL_11_FSYL1_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_FSYL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_FSYL1_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_FSYL1_MASK) #define GTM_gtm_cls0_DPLL_CTRL_11_INCF1_MASK (0x10U) #define GTM_gtm_cls0_DPLL_CTRL_11_INCF1_SHIFT (4U) #define GTM_gtm_cls0_DPLL_CTRL_11_INCF1_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_INCF1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_INCF1_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_INCF1_MASK) #define GTM_gtm_cls0_DPLL_CTRL_11_PCMF1_INCCNT_B_MASK (0x20U) #define GTM_gtm_cls0_DPLL_CTRL_11_PCMF1_INCCNT_B_SHIFT (5U) #define GTM_gtm_cls0_DPLL_CTRL_11_PCMF1_INCCNT_B_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_PCMF1_INCCNT_B(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_PCMF1_INCCNT_B_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_PCMF1_INCCNT_B_MASK) #define GTM_gtm_cls0_DPLL_CTRL_11_ADT_MASK (0x40U) #define GTM_gtm_cls0_DPLL_CTRL_11_ADT_SHIFT (6U) #define GTM_gtm_cls0_DPLL_CTRL_11_ADT_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_ADT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_ADT_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_ADT_MASK) #define GTM_gtm_cls0_DPLL_CTRL_11_ADS_MASK (0x80U) #define GTM_gtm_cls0_DPLL_CTRL_11_ADS_SHIFT (7U) #define GTM_gtm_cls0_DPLL_CTRL_11_ADS_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_ADS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_ADS_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_ADS_MASK) #define GTM_gtm_cls0_DPLL_CTRL_11_SIP2_MASK (0x100U) #define GTM_gtm_cls0_DPLL_CTRL_11_SIP2_SHIFT (8U) #define GTM_gtm_cls0_DPLL_CTRL_11_SIP2_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_SIP2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_SIP2_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_SIP2_MASK) #define GTM_gtm_cls0_DPLL_CTRL_11_ERZ2_MASK (0x200U) #define GTM_gtm_cls0_DPLL_CTRL_11_ERZ2_SHIFT (9U) #define GTM_gtm_cls0_DPLL_CTRL_11_ERZ2_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_ERZ2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_ERZ2_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_ERZ2_MASK) #define GTM_gtm_cls0_DPLL_CTRL_11_PCMF2_MASK (0x400U) #define GTM_gtm_cls0_DPLL_CTRL_11_PCMF2_SHIFT (10U) #define GTM_gtm_cls0_DPLL_CTRL_11_PCMF2_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_PCMF2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_PCMF2_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_PCMF2_MASK) #define GTM_gtm_cls0_DPLL_CTRL_11_FSYL2_MASK (0x800U) #define GTM_gtm_cls0_DPLL_CTRL_11_FSYL2_SHIFT (11U) #define GTM_gtm_cls0_DPLL_CTRL_11_FSYL2_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_FSYL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_FSYL2_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_FSYL2_MASK) #define GTM_gtm_cls0_DPLL_CTRL_11_INCF2_MASK (0x1000U) #define GTM_gtm_cls0_DPLL_CTRL_11_INCF2_SHIFT (12U) #define GTM_gtm_cls0_DPLL_CTRL_11_INCF2_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_INCF2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_INCF2_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_INCF2_MASK) #define GTM_gtm_cls0_DPLL_CTRL_11_PCMF2_INCCNT_B_MASK (0x2000U) #define GTM_gtm_cls0_DPLL_CTRL_11_PCMF2_INCCNT_B_SHIFT (13U) #define GTM_gtm_cls0_DPLL_CTRL_11_PCMF2_INCCNT_B_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_PCMF2_INCCNT_B(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_PCMF2_INCCNT_B_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_PCMF2_INCCNT_B_MASK) #define GTM_gtm_cls0_DPLL_CTRL_11_STATE_EXT_MASK (0x4000U) #define GTM_gtm_cls0_DPLL_CTRL_11_STATE_EXT_SHIFT (14U) #define GTM_gtm_cls0_DPLL_CTRL_11_STATE_EXT_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_STATE_EXT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_STATE_EXT_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_STATE_EXT_MASK) #define GTM_gtm_cls0_DPLL_CTRL_11_ACBU_MASK (0x8000U) #define GTM_gtm_cls0_DPLL_CTRL_11_ACBU_SHIFT (15U) #define GTM_gtm_cls0_DPLL_CTRL_11_ACBU_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_ACBU(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_ACBU_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_ACBU_MASK) #define GTM_gtm_cls0_DPLL_CTRL_11_WSIP1_MASK (0x10000U) #define GTM_gtm_cls0_DPLL_CTRL_11_WSIP1_SHIFT (16U) #define GTM_gtm_cls0_DPLL_CTRL_11_WSIP1_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_WSIP1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_WSIP1_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_WSIP1_MASK) #define GTM_gtm_cls0_DPLL_CTRL_11_WERZ1_MASK (0x20000U) #define GTM_gtm_cls0_DPLL_CTRL_11_WERZ1_SHIFT (17U) #define GTM_gtm_cls0_DPLL_CTRL_11_WERZ1_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_WERZ1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_WERZ1_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_WERZ1_MASK) #define GTM_gtm_cls0_DPLL_CTRL_11_WPCMF1_MASK (0x40000U) #define GTM_gtm_cls0_DPLL_CTRL_11_WPCMF1_SHIFT (18U) #define GTM_gtm_cls0_DPLL_CTRL_11_WPCMF1_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_WPCMF1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_WPCMF1_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_WPCMF1_MASK) #define GTM_gtm_cls0_DPLL_CTRL_11_WFSYL1_MASK (0x80000U) #define GTM_gtm_cls0_DPLL_CTRL_11_WFSYL1_SHIFT (19U) #define GTM_gtm_cls0_DPLL_CTRL_11_WFSYL1_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_WFSYL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_WFSYL1_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_WFSYL1_MASK) #define GTM_gtm_cls0_DPLL_CTRL_11_WINCF1_MASK (0x100000U) #define GTM_gtm_cls0_DPLL_CTRL_11_WINCF1_SHIFT (20U) #define GTM_gtm_cls0_DPLL_CTRL_11_WINCF1_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_WINCF1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_WINCF1_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_WINCF1_MASK) #define GTM_gtm_cls0_DPLL_CTRL_11_WPCMF1_INCCNT_B_MASK (0x200000U) #define GTM_gtm_cls0_DPLL_CTRL_11_WPCMF1_INCCNT_B_SHIFT (21U) #define GTM_gtm_cls0_DPLL_CTRL_11_WPCMF1_INCCNT_B_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_WPCMF1_INCCNT_B(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_WPCMF1_INCCNT_B_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_WPCMF1_INCCNT_B_MASK) #define GTM_gtm_cls0_DPLL_CTRL_11_WADT_MASK (0x400000U) #define GTM_gtm_cls0_DPLL_CTRL_11_WADT_SHIFT (22U) #define GTM_gtm_cls0_DPLL_CTRL_11_WADT_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_WADT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_WADT_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_WADT_MASK) #define GTM_gtm_cls0_DPLL_CTRL_11_WADS_MASK (0x800000U) #define GTM_gtm_cls0_DPLL_CTRL_11_WADS_SHIFT (23U) #define GTM_gtm_cls0_DPLL_CTRL_11_WADS_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_WADS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_WADS_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_WADS_MASK) #define GTM_gtm_cls0_DPLL_CTRL_11_WSIP2_MASK (0x1000000U) #define GTM_gtm_cls0_DPLL_CTRL_11_WSIP2_SHIFT (24U) #define GTM_gtm_cls0_DPLL_CTRL_11_WSIP2_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_WSIP2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_WSIP2_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_WSIP2_MASK) #define GTM_gtm_cls0_DPLL_CTRL_11_WERZ2_MASK (0x2000000U) #define GTM_gtm_cls0_DPLL_CTRL_11_WERZ2_SHIFT (25U) #define GTM_gtm_cls0_DPLL_CTRL_11_WERZ2_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_WERZ2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_WERZ2_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_WERZ2_MASK) #define GTM_gtm_cls0_DPLL_CTRL_11_WPCMF2_MASK (0x4000000U) #define GTM_gtm_cls0_DPLL_CTRL_11_WPCMF2_SHIFT (26U) #define GTM_gtm_cls0_DPLL_CTRL_11_WPCMF2_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_WPCMF2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_WPCMF2_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_WPCMF2_MASK) #define GTM_gtm_cls0_DPLL_CTRL_11_WFSYL2_MASK (0x8000000U) #define GTM_gtm_cls0_DPLL_CTRL_11_WFSYL2_SHIFT (27U) #define GTM_gtm_cls0_DPLL_CTRL_11_WFSYL2_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_WFSYL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_WFSYL2_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_WFSYL2_MASK) #define GTM_gtm_cls0_DPLL_CTRL_11_WINCF2_MASK (0x10000000U) #define GTM_gtm_cls0_DPLL_CTRL_11_WINCF2_SHIFT (28U) #define GTM_gtm_cls0_DPLL_CTRL_11_WINCF2_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_WINCF2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_WINCF2_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_WINCF2_MASK) #define GTM_gtm_cls0_DPLL_CTRL_11_WPCMF2_INCCNT_B_MASK (0x20000000U) #define GTM_gtm_cls0_DPLL_CTRL_11_WPCMF2_INCCNT_B_SHIFT (29U) #define GTM_gtm_cls0_DPLL_CTRL_11_WPCMF2_INCCNT_B_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_WPCMF2_INCCNT_B(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_WPCMF2_INCCNT_B_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_WPCMF2_INCCNT_B_MASK) #define GTM_gtm_cls0_DPLL_CTRL_11_WSTATE_EXT_MASK (0x40000000U) #define GTM_gtm_cls0_DPLL_CTRL_11_WSTATE_EXT_SHIFT (30U) #define GTM_gtm_cls0_DPLL_CTRL_11_WSTATE_EXT_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_WSTATE_EXT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_WSTATE_EXT_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_WSTATE_EXT_MASK) #define GTM_gtm_cls0_DPLL_CTRL_11_WACBU_MASK (0x80000000U) #define GTM_gtm_cls0_DPLL_CTRL_11_WACBU_SHIFT (31U) #define GTM_gtm_cls0_DPLL_CTRL_11_WACBU_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_11_WACBU(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_11_WACBU_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_11_WACBU_MASK) /*! @} */ /*! @name DPLL_THVAL2 - Measured TRIGGER Hold Time Value 2 */ /*! @{ */ #define GTM_gtm_cls0_DPLL_THVAL2_THVAL_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_THVAL2_THVAL_SHIFT (0U) #define GTM_gtm_cls0_DPLL_THVAL2_THVAL_WIDTH (24U) #define GTM_gtm_cls0_DPLL_THVAL2_THVAL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_THVAL2_THVAL_SHIFT)) & GTM_gtm_cls0_DPLL_THVAL2_THVAL_MASK) /*! @} */ /*! @name DPLL_TIDEL - TRIGGER input delay */ /*! @{ */ #define GTM_gtm_cls0_DPLL_TIDEL_TIDEL_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_TIDEL_TIDEL_SHIFT (0U) #define GTM_gtm_cls0_DPLL_TIDEL_TIDEL_WIDTH (24U) #define GTM_gtm_cls0_DPLL_TIDEL_TIDEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_TIDEL_TIDEL_SHIFT)) & GTM_gtm_cls0_DPLL_TIDEL_TIDEL_MASK) /*! @} */ /*! @name DPLL_SIDEL - STATE input delay */ /*! @{ */ #define GTM_gtm_cls0_DPLL_SIDEL_SIDEL_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_SIDEL_SIDEL_SHIFT (0U) #define GTM_gtm_cls0_DPLL_SIDEL_SIDEL_WIDTH (24U) #define GTM_gtm_cls0_DPLL_SIDEL_SIDEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_SIDEL_SIDEL_SHIFT)) & GTM_gtm_cls0_DPLL_SIDEL_SIDEL_MASK) /*! @} */ /*! @name DPLL_APS_SYNC_EXT - STATE Time Stamp Field Offset at Synchronization Time */ /*! @{ */ #define GTM_gtm_cls0_DPLL_APS_SYNC_EXT_APS_1C2_EXT_MASK (0x7FU) #define GTM_gtm_cls0_DPLL_APS_SYNC_EXT_APS_1C2_EXT_SHIFT (0U) #define GTM_gtm_cls0_DPLL_APS_SYNC_EXT_APS_1C2_EXT_WIDTH (7U) #define GTM_gtm_cls0_DPLL_APS_SYNC_EXT_APS_1C2_EXT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_APS_SYNC_EXT_APS_1C2_EXT_SHIFT)) & GTM_gtm_cls0_DPLL_APS_SYNC_EXT_APS_1C2_EXT_MASK) #define GTM_gtm_cls0_DPLL_APS_SYNC_EXT_APS_1C2_STATUS_MASK (0x8000U) #define GTM_gtm_cls0_DPLL_APS_SYNC_EXT_APS_1C2_STATUS_SHIFT (15U) #define GTM_gtm_cls0_DPLL_APS_SYNC_EXT_APS_1C2_STATUS_WIDTH (1U) #define GTM_gtm_cls0_DPLL_APS_SYNC_EXT_APS_1C2_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_APS_SYNC_EXT_APS_1C2_STATUS_SHIFT)) & GTM_gtm_cls0_DPLL_APS_SYNC_EXT_APS_1C2_STATUS_MASK) #define GTM_gtm_cls0_DPLL_APS_SYNC_EXT_APS_1C2_OLD_MASK (0x7F0000U) #define GTM_gtm_cls0_DPLL_APS_SYNC_EXT_APS_1C2_OLD_SHIFT (16U) #define GTM_gtm_cls0_DPLL_APS_SYNC_EXT_APS_1C2_OLD_WIDTH (7U) #define GTM_gtm_cls0_DPLL_APS_SYNC_EXT_APS_1C2_OLD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_APS_SYNC_EXT_APS_1C2_OLD_SHIFT)) & GTM_gtm_cls0_DPLL_APS_SYNC_EXT_APS_1C2_OLD_MASK) /*! @} */ /*! @name DPLL_CTRL_EXT - STATE Time Stamp Field Offset at Synchronization Time */ /*! @{ */ #define GTM_gtm_cls0_DPLL_CTRL_EXT_SNU_MASK (0x3FU) #define GTM_gtm_cls0_DPLL_CTRL_EXT_SNU_SHIFT (0U) #define GTM_gtm_cls0_DPLL_CTRL_EXT_SNU_WIDTH (6U) #define GTM_gtm_cls0_DPLL_CTRL_EXT_SNU(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_EXT_SNU_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_EXT_SNU_MASK) #define GTM_gtm_cls0_DPLL_CTRL_EXT_SYN_NS_MASK (0x3F0000U) #define GTM_gtm_cls0_DPLL_CTRL_EXT_SYN_NS_SHIFT (16U) #define GTM_gtm_cls0_DPLL_CTRL_EXT_SYN_NS_WIDTH (6U) #define GTM_gtm_cls0_DPLL_CTRL_EXT_SYN_NS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_EXT_SYN_NS_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_EXT_SYN_NS_MASK) /*! @} */ /*! @name DPLL_APS_EXT - Actual RAM Pointer Address for STATE */ /*! @{ */ #define GTM_gtm_cls0_DPLL_APS_EXT_WAPS_MASK (0x2U) #define GTM_gtm_cls0_DPLL_APS_EXT_WAPS_SHIFT (1U) #define GTM_gtm_cls0_DPLL_APS_EXT_WAPS_WIDTH (1U) #define GTM_gtm_cls0_DPLL_APS_EXT_WAPS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_APS_EXT_WAPS_SHIFT)) & GTM_gtm_cls0_DPLL_APS_EXT_WAPS_MASK) #define GTM_gtm_cls0_DPLL_APS_EXT_APS_MASK (0x1FCU) #define GTM_gtm_cls0_DPLL_APS_EXT_APS_SHIFT (2U) #define GTM_gtm_cls0_DPLL_APS_EXT_APS_WIDTH (7U) #define GTM_gtm_cls0_DPLL_APS_EXT_APS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_APS_EXT_APS_SHIFT)) & GTM_gtm_cls0_DPLL_APS_EXT_APS_MASK) #define GTM_gtm_cls0_DPLL_APS_EXT_WAPS_1C2_MASK (0x2000U) #define GTM_gtm_cls0_DPLL_APS_EXT_WAPS_1C2_SHIFT (13U) #define GTM_gtm_cls0_DPLL_APS_EXT_WAPS_1C2_WIDTH (1U) #define GTM_gtm_cls0_DPLL_APS_EXT_WAPS_1C2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_APS_EXT_WAPS_1C2_SHIFT)) & GTM_gtm_cls0_DPLL_APS_EXT_WAPS_1C2_MASK) #define GTM_gtm_cls0_DPLL_APS_EXT_APS_1C2_MASK (0x1FC000U) #define GTM_gtm_cls0_DPLL_APS_EXT_APS_1C2_SHIFT (14U) #define GTM_gtm_cls0_DPLL_APS_EXT_APS_1C2_WIDTH (7U) #define GTM_gtm_cls0_DPLL_APS_EXT_APS_1C2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_APS_EXT_APS_1C2_SHIFT)) & GTM_gtm_cls0_DPLL_APS_EXT_APS_1C2_MASK) /*! @} */ /*! @name DPLL_APS_1C3_EXT - Actual RAM Pointer Address for RAM region 1c3 (DPLL_CTRL_11.STATE_EXT=1) */ /*! @{ */ #define GTM_gtm_cls0_DPLL_APS_1C3_EXT_APS_1C3_MASK (0x1FCU) #define GTM_gtm_cls0_DPLL_APS_1C3_EXT_APS_1C3_SHIFT (2U) #define GTM_gtm_cls0_DPLL_APS_1C3_EXT_APS_1C3_WIDTH (7U) #define GTM_gtm_cls0_DPLL_APS_1C3_EXT_APS_1C3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_APS_1C3_EXT_APS_1C3_SHIFT)) & GTM_gtm_cls0_DPLL_APS_1C3_EXT_APS_1C3_MASK) /*! @} */ /*! @name DPLL_STA - Status of the state machine states */ /*! @{ */ #define GTM_gtm_cls0_DPLL_STA_STA_T_MASK (0xFFU) #define GTM_gtm_cls0_DPLL_STA_STA_T_SHIFT (0U) #define GTM_gtm_cls0_DPLL_STA_STA_T_WIDTH (8U) #define GTM_gtm_cls0_DPLL_STA_STA_T(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STA_STA_T_SHIFT)) & GTM_gtm_cls0_DPLL_STA_STA_T_MASK) #define GTM_gtm_cls0_DPLL_STA_CNT_T_MASK (0xE00U) #define GTM_gtm_cls0_DPLL_STA_CNT_T_SHIFT (9U) #define GTM_gtm_cls0_DPLL_STA_CNT_T_WIDTH (3U) #define GTM_gtm_cls0_DPLL_STA_CNT_T(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STA_CNT_T_SHIFT)) & GTM_gtm_cls0_DPLL_STA_CNT_T_MASK) #define GTM_gtm_cls0_DPLL_STA_STA_S_MASK (0xFF000U) #define GTM_gtm_cls0_DPLL_STA_STA_S_SHIFT (12U) #define GTM_gtm_cls0_DPLL_STA_STA_S_WIDTH (8U) #define GTM_gtm_cls0_DPLL_STA_STA_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STA_STA_S_SHIFT)) & GTM_gtm_cls0_DPLL_STA_STA_S_MASK) #define GTM_gtm_cls0_DPLL_STA_CNT_S_MASK (0xE00000U) #define GTM_gtm_cls0_DPLL_STA_CNT_S_SHIFT (21U) #define GTM_gtm_cls0_DPLL_STA_CNT_S_WIDTH (3U) #define GTM_gtm_cls0_DPLL_STA_CNT_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STA_CNT_S_SHIFT)) & GTM_gtm_cls0_DPLL_STA_CNT_S_MASK) /*! @} */ /*! @name DPLL_INCF1_OFFSET - Start value of ADD_IN_ADDER1 */ /*! @{ */ #define GTM_gtm_cls0_DPLL_INCF1_OFFSET_INCF1_OFFSET_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_INCF1_OFFSET_INCF1_OFFSET_SHIFT (0U) #define GTM_gtm_cls0_DPLL_INCF1_OFFSET_INCF1_OFFSET_WIDTH (24U) #define GTM_gtm_cls0_DPLL_INCF1_OFFSET_INCF1_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_INCF1_OFFSET_INCF1_OFFSET_SHIFT)) & GTM_gtm_cls0_DPLL_INCF1_OFFSET_INCF1_OFFSET_MASK) /*! @} */ /*! @name DPLL_INCF2_OFFSET - Start value of the ADD_IN_ADDER2 */ /*! @{ */ #define GTM_gtm_cls0_DPLL_INCF2_OFFSET_INCF2_OFFSET_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_INCF2_OFFSET_INCF2_OFFSET_SHIFT (0U) #define GTM_gtm_cls0_DPLL_INCF2_OFFSET_INCF2_OFFSET_WIDTH (24U) #define GTM_gtm_cls0_DPLL_INCF2_OFFSET_INCF2_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_INCF2_OFFSET_INCF2_OFFSET_SHIFT)) & GTM_gtm_cls0_DPLL_INCF2_OFFSET_INCF2_OFFSET_MASK) /*! @} */ /*! @name DPLL_DT_T_START - Start value of DT_T_ACT */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_T_START_DT_T_START_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_T_START_DT_T_START_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_T_START_DT_T_START_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_T_START_DT_T_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_T_START_DT_T_START_SHIFT)) & GTM_gtm_cls0_DPLL_DT_T_START_DT_T_START_MASK) /*! @} */ /*! @name DPLL_DT_S_START - Start value of DT_S_ACT */ /*! @{ */ #define GTM_gtm_cls0_DPLL_DT_S_START_DT_S_START_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_DT_S_START_DT_S_START_SHIFT (0U) #define GTM_gtm_cls0_DPLL_DT_S_START_DT_S_START_WIDTH (24U) #define GTM_gtm_cls0_DPLL_DT_S_START_DT_S_START(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_DT_S_START_DT_S_START_SHIFT)) & GTM_gtm_cls0_DPLL_DT_S_START_DT_S_START_MASK) /*! @} */ /*! @name DPLL_STA_MASK - Notify values for DPLL_STA */ /*! @{ */ #define GTM_gtm_cls0_DPLL_STA_MASK_STA_NOTIFY_T_MASK (0xFFU) #define GTM_gtm_cls0_DPLL_STA_MASK_STA_NOTIFY_T_SHIFT (0U) #define GTM_gtm_cls0_DPLL_STA_MASK_STA_NOTIFY_T_WIDTH (8U) #define GTM_gtm_cls0_DPLL_STA_MASK_STA_NOTIFY_T(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STA_MASK_STA_NOTIFY_T_SHIFT)) & GTM_gtm_cls0_DPLL_STA_MASK_STA_NOTIFY_T_MASK) #define GTM_gtm_cls0_DPLL_STA_MASK_STA_NOTIFY_S_MASK (0xFF00U) #define GTM_gtm_cls0_DPLL_STA_MASK_STA_NOTIFY_S_SHIFT (8U) #define GTM_gtm_cls0_DPLL_STA_MASK_STA_NOTIFY_S_WIDTH (8U) #define GTM_gtm_cls0_DPLL_STA_MASK_STA_NOTIFY_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STA_MASK_STA_NOTIFY_S_SHIFT)) & GTM_gtm_cls0_DPLL_STA_MASK_STA_NOTIFY_S_MASK) /*! @} */ /*! @name DPLL_STA_FLAG - DPLL STA Flags */ /*! @{ */ #define GTM_gtm_cls0_DPLL_STA_FLAG_STA_FLAG_T_MASK (0x1U) #define GTM_gtm_cls0_DPLL_STA_FLAG_STA_FLAG_T_SHIFT (0U) #define GTM_gtm_cls0_DPLL_STA_FLAG_STA_FLAG_T_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STA_FLAG_STA_FLAG_T(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STA_FLAG_STA_FLAG_T_SHIFT)) & GTM_gtm_cls0_DPLL_STA_FLAG_STA_FLAG_T_MASK) #define GTM_gtm_cls0_DPLL_STA_FLAG_STA_FLAG_S_MASK (0x100U) #define GTM_gtm_cls0_DPLL_STA_FLAG_STA_FLAG_S_SHIFT (8U) #define GTM_gtm_cls0_DPLL_STA_FLAG_STA_FLAG_S_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STA_FLAG_STA_FLAG_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STA_FLAG_STA_FLAG_S_SHIFT)) & GTM_gtm_cls0_DPLL_STA_FLAG_STA_FLAG_S_MASK) #define GTM_gtm_cls0_DPLL_STA_FLAG_INC_CNT1_FLAG_MASK (0x200U) #define GTM_gtm_cls0_DPLL_STA_FLAG_INC_CNT1_FLAG_SHIFT (9U) #define GTM_gtm_cls0_DPLL_STA_FLAG_INC_CNT1_FLAG_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STA_FLAG_INC_CNT1_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STA_FLAG_INC_CNT1_FLAG_SHIFT)) & GTM_gtm_cls0_DPLL_STA_FLAG_INC_CNT1_FLAG_MASK) #define GTM_gtm_cls0_DPLL_STA_FLAG_INC_CNT2_FLAG_MASK (0x400U) #define GTM_gtm_cls0_DPLL_STA_FLAG_INC_CNT2_FLAG_SHIFT (10U) #define GTM_gtm_cls0_DPLL_STA_FLAG_INC_CNT2_FLAG_WIDTH (1U) #define GTM_gtm_cls0_DPLL_STA_FLAG_INC_CNT2_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_STA_FLAG_INC_CNT2_FLAG_SHIFT)) & GTM_gtm_cls0_DPLL_STA_FLAG_INC_CNT2_FLAG_MASK) /*! @} */ /*! @name DPLL_INC_CNT1_MASK - Notify value of DPLL_INC_CNT1 */ /*! @{ */ #define GTM_gtm_cls0_DPLL_INC_CNT1_MASK_INC_CNT1_NOTIFY_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_INC_CNT1_MASK_INC_CNT1_NOTIFY_SHIFT (0U) #define GTM_gtm_cls0_DPLL_INC_CNT1_MASK_INC_CNT1_NOTIFY_WIDTH (24U) #define GTM_gtm_cls0_DPLL_INC_CNT1_MASK_INC_CNT1_NOTIFY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_INC_CNT1_MASK_INC_CNT1_NOTIFY_SHIFT)) & GTM_gtm_cls0_DPLL_INC_CNT1_MASK_INC_CNT1_NOTIFY_MASK) /*! @} */ /*! @name DPLL_INC_CNT2_MASK - Notify value of DPLL_INC_CNT2 */ /*! @{ */ #define GTM_gtm_cls0_DPLL_INC_CNT2_MASK_INC_CNT2_NOTIFY_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_INC_CNT2_MASK_INC_CNT2_NOTIFY_SHIFT (0U) #define GTM_gtm_cls0_DPLL_INC_CNT2_MASK_INC_CNT2_NOTIFY_WIDTH (24U) #define GTM_gtm_cls0_DPLL_INC_CNT2_MASK_INC_CNT2_NOTIFY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_INC_CNT2_MASK_INC_CNT2_NOTIFY_SHIFT)) & GTM_gtm_cls0_DPLL_INC_CNT2_MASK_INC_CNT2_NOTIFY_MASK) /*! @} */ /*! @name DPLL_NUSC_EXT1 - Number of Recent STATE Events used for Calculations */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NUSC_EXT1_SYN_S_MASK (0x7FU) #define GTM_gtm_cls0_DPLL_NUSC_EXT1_SYN_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NUSC_EXT1_SYN_S_WIDTH (7U) #define GTM_gtm_cls0_DPLL_NUSC_EXT1_SYN_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NUSC_EXT1_SYN_S_SHIFT)) & GTM_gtm_cls0_DPLL_NUSC_EXT1_SYN_S_MASK) #define GTM_gtm_cls0_DPLL_NUSC_EXT1_SYN_S_OLD_MASK (0x7F0000U) #define GTM_gtm_cls0_DPLL_NUSC_EXT1_SYN_S_OLD_SHIFT (16U) #define GTM_gtm_cls0_DPLL_NUSC_EXT1_SYN_S_OLD_WIDTH (7U) #define GTM_gtm_cls0_DPLL_NUSC_EXT1_SYN_S_OLD(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NUSC_EXT1_SYN_S_OLD_SHIFT)) & GTM_gtm_cls0_DPLL_NUSC_EXT1_SYN_S_OLD_MASK) #define GTM_gtm_cls0_DPLL_NUSC_EXT1_WSYN_MASK (0x40000000U) #define GTM_gtm_cls0_DPLL_NUSC_EXT1_WSYN_SHIFT (30U) #define GTM_gtm_cls0_DPLL_NUSC_EXT1_WSYN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_NUSC_EXT1_WSYN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NUSC_EXT1_WSYN_SHIFT)) & GTM_gtm_cls0_DPLL_NUSC_EXT1_WSYN_MASK) /*! @} */ /*! @name DPLL_NUSC_EXT2 - Number of Recent STATE Events used for Calculations */ /*! @{ */ #define GTM_gtm_cls0_DPLL_NUSC_EXT2_NUSE_MASK (0x7FU) #define GTM_gtm_cls0_DPLL_NUSC_EXT2_NUSE_SHIFT (0U) #define GTM_gtm_cls0_DPLL_NUSC_EXT2_NUSE_WIDTH (7U) #define GTM_gtm_cls0_DPLL_NUSC_EXT2_NUSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NUSC_EXT2_NUSE_SHIFT)) & GTM_gtm_cls0_DPLL_NUSC_EXT2_NUSE_MASK) #define GTM_gtm_cls0_DPLL_NUSC_EXT2_FSS_MASK (0x8000U) #define GTM_gtm_cls0_DPLL_NUSC_EXT2_FSS_SHIFT (15U) #define GTM_gtm_cls0_DPLL_NUSC_EXT2_FSS_WIDTH (1U) #define GTM_gtm_cls0_DPLL_NUSC_EXT2_FSS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NUSC_EXT2_FSS_SHIFT)) & GTM_gtm_cls0_DPLL_NUSC_EXT2_FSS_MASK) #define GTM_gtm_cls0_DPLL_NUSC_EXT2_VSN_MASK (0x7F0000U) #define GTM_gtm_cls0_DPLL_NUSC_EXT2_VSN_SHIFT (16U) #define GTM_gtm_cls0_DPLL_NUSC_EXT2_VSN_WIDTH (7U) #define GTM_gtm_cls0_DPLL_NUSC_EXT2_VSN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NUSC_EXT2_VSN_SHIFT)) & GTM_gtm_cls0_DPLL_NUSC_EXT2_VSN_MASK) #define GTM_gtm_cls0_DPLL_NUSC_EXT2_WNUS_MASK (0x20000000U) #define GTM_gtm_cls0_DPLL_NUSC_EXT2_WNUS_SHIFT (29U) #define GTM_gtm_cls0_DPLL_NUSC_EXT2_WNUS_WIDTH (1U) #define GTM_gtm_cls0_DPLL_NUSC_EXT2_WNUS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NUSC_EXT2_WNUS_SHIFT)) & GTM_gtm_cls0_DPLL_NUSC_EXT2_WNUS_MASK) #define GTM_gtm_cls0_DPLL_NUSC_EXT2_WVSN_MASK (0x80000000U) #define GTM_gtm_cls0_DPLL_NUSC_EXT2_WVSN_SHIFT (31U) #define GTM_gtm_cls0_DPLL_NUSC_EXT2_WVSN_WIDTH (1U) #define GTM_gtm_cls0_DPLL_NUSC_EXT2_WVSN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_NUSC_EXT2_WVSN_SHIFT)) & GTM_gtm_cls0_DPLL_NUSC_EXT2_WVSN_MASK) /*! @} */ /*! @name DPLL_CTN_MIN - Minimum value of predicted nominal increment of TRIGGER */ /*! @{ */ #define GTM_gtm_cls0_DPLL_CTN_MIN_CTN_MIN_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_CTN_MIN_CTN_MIN_SHIFT (0U) #define GTM_gtm_cls0_DPLL_CTN_MIN_CTN_MIN_WIDTH (24U) #define GTM_gtm_cls0_DPLL_CTN_MIN_CTN_MIN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTN_MIN_CTN_MIN_SHIFT)) & GTM_gtm_cls0_DPLL_CTN_MIN_CTN_MIN_MASK) /*! @} */ /*! @name DPLL_CTN_MAX - Maximum value of predicted nominal increment of TRIGGER */ /*! @{ */ #define GTM_gtm_cls0_DPLL_CTN_MAX_CTN_MAX_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_CTN_MAX_CTN_MAX_SHIFT (0U) #define GTM_gtm_cls0_DPLL_CTN_MAX_CTN_MAX_WIDTH (24U) #define GTM_gtm_cls0_DPLL_CTN_MAX_CTN_MAX(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTN_MAX_CTN_MAX_SHIFT)) & GTM_gtm_cls0_DPLL_CTN_MAX_CTN_MAX_MASK) /*! @} */ /*! @name DPLL_CSN_MIN - Minimum value of predicted nominal increment of STATE */ /*! @{ */ #define GTM_gtm_cls0_DPLL_CSN_MIN_CSN_MIN_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_CSN_MIN_CSN_MIN_SHIFT (0U) #define GTM_gtm_cls0_DPLL_CSN_MIN_CSN_MIN_WIDTH (24U) #define GTM_gtm_cls0_DPLL_CSN_MIN_CSN_MIN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CSN_MIN_CSN_MIN_SHIFT)) & GTM_gtm_cls0_DPLL_CSN_MIN_CSN_MIN_MASK) /*! @} */ /*! @name DPLL_CSN_MAX - Maximum value of predicted nominal increment of STATE */ /*! @{ */ #define GTM_gtm_cls0_DPLL_CSN_MAX_CSN_MAX_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_CSN_MAX_CSN_MAX_SHIFT (0U) #define GTM_gtm_cls0_DPLL_CSN_MAX_CSN_MAX_WIDTH (24U) #define GTM_gtm_cls0_DPLL_CSN_MAX_CSN_MAX(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CSN_MAX_CSN_MAX_SHIFT)) & GTM_gtm_cls0_DPLL_CSN_MAX_CSN_MAX_MASK) /*! @} */ /*! @name DPLL_SW_TRIG - Software triggered input events */ /*! @{ */ #define GTM_gtm_cls0_DPLL_SW_TRIG_TRIG_EVENT_MASK (0x1U) #define GTM_gtm_cls0_DPLL_SW_TRIG_TRIG_EVENT_SHIFT (0U) #define GTM_gtm_cls0_DPLL_SW_TRIG_TRIG_EVENT_WIDTH (1U) #define GTM_gtm_cls0_DPLL_SW_TRIG_TRIG_EVENT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_SW_TRIG_TRIG_EVENT_SHIFT)) & GTM_gtm_cls0_DPLL_SW_TRIG_TRIG_EVENT_MASK) #define GTM_gtm_cls0_DPLL_SW_TRIG_WTRIG_EVENT_MASK (0x2U) #define GTM_gtm_cls0_DPLL_SW_TRIG_WTRIG_EVENT_SHIFT (1U) #define GTM_gtm_cls0_DPLL_SW_TRIG_WTRIG_EVENT_WIDTH (1U) #define GTM_gtm_cls0_DPLL_SW_TRIG_WTRIG_EVENT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_SW_TRIG_WTRIG_EVENT_SHIFT)) & GTM_gtm_cls0_DPLL_SW_TRIG_WTRIG_EVENT_MASK) #define GTM_gtm_cls0_DPLL_SW_TRIG_TRIG_LEVEL_MASK (0x4U) #define GTM_gtm_cls0_DPLL_SW_TRIG_TRIG_LEVEL_SHIFT (2U) #define GTM_gtm_cls0_DPLL_SW_TRIG_TRIG_LEVEL_WIDTH (1U) #define GTM_gtm_cls0_DPLL_SW_TRIG_TRIG_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_SW_TRIG_TRIG_LEVEL_SHIFT)) & GTM_gtm_cls0_DPLL_SW_TRIG_TRIG_LEVEL_MASK) #define GTM_gtm_cls0_DPLL_SW_TRIG_WTRIG_LEVEL_MASK (0x8U) #define GTM_gtm_cls0_DPLL_SW_TRIG_WTRIG_LEVEL_SHIFT (3U) #define GTM_gtm_cls0_DPLL_SW_TRIG_WTRIG_LEVEL_WIDTH (1U) #define GTM_gtm_cls0_DPLL_SW_TRIG_WTRIG_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_SW_TRIG_WTRIG_LEVEL_SHIFT)) & GTM_gtm_cls0_DPLL_SW_TRIG_WTRIG_LEVEL_MASK) #define GTM_gtm_cls0_DPLL_SW_TRIG_STATE_EVENT_MASK (0x10U) #define GTM_gtm_cls0_DPLL_SW_TRIG_STATE_EVENT_SHIFT (4U) #define GTM_gtm_cls0_DPLL_SW_TRIG_STATE_EVENT_WIDTH (1U) #define GTM_gtm_cls0_DPLL_SW_TRIG_STATE_EVENT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_SW_TRIG_STATE_EVENT_SHIFT)) & GTM_gtm_cls0_DPLL_SW_TRIG_STATE_EVENT_MASK) #define GTM_gtm_cls0_DPLL_SW_TRIG_WSTATE_EVENT_MASK (0x20U) #define GTM_gtm_cls0_DPLL_SW_TRIG_WSTATE_EVENT_SHIFT (5U) #define GTM_gtm_cls0_DPLL_SW_TRIG_WSTATE_EVENT_WIDTH (1U) #define GTM_gtm_cls0_DPLL_SW_TRIG_WSTATE_EVENT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_SW_TRIG_WSTATE_EVENT_SHIFT)) & GTM_gtm_cls0_DPLL_SW_TRIG_WSTATE_EVENT_MASK) #define GTM_gtm_cls0_DPLL_SW_TRIG_STATE_LEVEL_MASK (0x40U) #define GTM_gtm_cls0_DPLL_SW_TRIG_STATE_LEVEL_SHIFT (6U) #define GTM_gtm_cls0_DPLL_SW_TRIG_STATE_LEVEL_WIDTH (1U) #define GTM_gtm_cls0_DPLL_SW_TRIG_STATE_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_SW_TRIG_STATE_LEVEL_SHIFT)) & GTM_gtm_cls0_DPLL_SW_TRIG_STATE_LEVEL_MASK) #define GTM_gtm_cls0_DPLL_SW_TRIG_WSTATE_LEVEL_MASK (0x80U) #define GTM_gtm_cls0_DPLL_SW_TRIG_WSTATE_LEVEL_SHIFT (7U) #define GTM_gtm_cls0_DPLL_SW_TRIG_WSTATE_LEVEL_WIDTH (1U) #define GTM_gtm_cls0_DPLL_SW_TRIG_WSTATE_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_SW_TRIG_WSTATE_LEVEL_SHIFT)) & GTM_gtm_cls0_DPLL_SW_TRIG_WSTATE_LEVEL_MASK) /*! @} */ /*! @name DPLL_MP_T - Missing pulses of TRIGGER */ /*! @{ */ #define GTM_gtm_cls0_DPLL_MP_T_MP_T_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_MP_T_MP_T_SHIFT (0U) #define GTM_gtm_cls0_DPLL_MP_T_MP_T_WIDTH (24U) #define GTM_gtm_cls0_DPLL_MP_T_MP_T(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_MP_T_MP_T_SHIFT)) & GTM_gtm_cls0_DPLL_MP_T_MP_T_MASK) /*! @} */ /*! @name DPLL_MP_S - Missing pulses of STATE */ /*! @{ */ #define GTM_gtm_cls0_DPLL_MP_S_MP_S_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_MP_S_MP_S_SHIFT (0U) #define GTM_gtm_cls0_DPLL_MP_S_MP_S_WIDTH (24U) #define GTM_gtm_cls0_DPLL_MP_S_MP_S(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_MP_S_MP_S_SHIFT)) & GTM_gtm_cls0_DPLL_MP_S_MP_S_MASK) /*! @} */ /*! @name DPLL_CTRL_12 - DPLL control register 12 */ /*! @{ */ #define GTM_gtm_cls0_DPLL_CTRL_12_SUBINC_MUX_SEL_MASK (0x1U) #define GTM_gtm_cls0_DPLL_CTRL_12_SUBINC_MUX_SEL_SHIFT (0U) #define GTM_gtm_cls0_DPLL_CTRL_12_SUBINC_MUX_SEL_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_12_SUBINC_MUX_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_12_SUBINC_MUX_SEL_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_12_SUBINC_MUX_SEL_MASK) #define GTM_gtm_cls0_DPLL_CTRL_12_WSUBINC_MUX_SEL_MASK (0x10000U) #define GTM_gtm_cls0_DPLL_CTRL_12_WSUBINC_MUX_SEL_SHIFT (16U) #define GTM_gtm_cls0_DPLL_CTRL_12_WSUBINC_MUX_SEL_WIDTH (1U) #define GTM_gtm_cls0_DPLL_CTRL_12_WSUBINC_MUX_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_CTRL_12_WSUBINC_MUX_SEL_SHIFT)) & GTM_gtm_cls0_DPLL_CTRL_12_WSUBINC_MUX_SEL_MASK) /*! @} */ /*! @name DPLL_RR2 - DPLL memory RR2 */ /*! @{ */ #define GTM_gtm_cls0_DPLL_RR2_DATA_MASK (0xFFFFFFU) #define GTM_gtm_cls0_DPLL_RR2_DATA_SHIFT (0U) #define GTM_gtm_cls0_DPLL_RR2_DATA_WIDTH (24U) #define GTM_gtm_cls0_DPLL_RR2_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_DPLL_RR2_DATA_SHIFT)) & GTM_gtm_cls0_DPLL_RR2_DATA_MASK) /*! @} */ /*! @name MCS0_MEM - MCS[i] memory region */ /*! @{ */ #define GTM_gtm_cls0_MCS0_MEM_DATA_MASK (0xFFFFFFFFU) #define GTM_gtm_cls0_MCS0_MEM_DATA_SHIFT (0U) #define GTM_gtm_cls0_MCS0_MEM_DATA_WIDTH (32U) #define GTM_gtm_cls0_MCS0_MEM_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls0_MCS0_MEM_DATA_SHIFT)) & GTM_gtm_cls0_MCS0_MEM_DATA_MASK) /*! @} */ /*! * @} */ /* end of group GTM_gtm_cls0_Register_Masks */ /*! * @} */ /* end of group GTM_gtm_cls0_Peripheral_Access_Layer */ #endif /* #if !defined(S32Z2_GTM_gtm_cls0_H_) */