/* * Copyright 1997-2016 Freescale Semiconductor, Inc. * Copyright 2016-2022 NXP * * SPDX-License-Identifier: BSD-3-Clause */ /*! * @file S32K144_WDOG.h * @version 1.1 * @date 2022-02-07 * @brief Peripheral Access Layer for S32K144_WDOG * * This file contains register definitions and macros for easy access to their * bit fields. * * This file assumes LITTLE endian system. */ /** * @page misra_violations MISRA-C:2012 violations * * @section [global] * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced * The SoC header defines typedef for all modules. * * @section [global] * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced * The SoC header defines macros for all modules and registers. * * @section [global] * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro * These are generated macros used for accessing the bit-fields from registers. * * @section [global] * Violates MISRA 2012 Required Rule 5.1, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.2, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.4, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.5, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler * This type qualifier is needed to ensure correct I/O access and addressing. */ /* Prevention from multiple including the same memory map */ #if !defined(S32K144_WDOG_H_) /* Check if memory map has not been already included */ #define S32K144_WDOG_H_ #include "S32K144_COMMON.h" /* ---------------------------------------------------------------------------- -- WDOG Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer * @{ */ /** WDOG - Register Layout Typedef */ typedef struct { __IO uint32_t CS; /**< Watchdog Control and Status Register, offset: 0x0 */ __IO uint32_t CNT; /**< Watchdog Counter Register, offset: 0x4 */ __IO uint32_t TOVAL; /**< Watchdog Timeout Value Register, offset: 0x8 */ __IO uint32_t WIN; /**< Watchdog Window Register, offset: 0xC */ } WDOG_Type, *WDOG_MemMapPtr; /** Number of instances of the WDOG module. */ #define WDOG_INSTANCE_COUNT (1u) /* WDOG - Peripheral instance base addresses */ /** Peripheral WDOG base address */ #define IP_WDOG_BASE (0x40052000u) /** Peripheral WDOG base pointer */ #define IP_WDOG ((WDOG_Type *)IP_WDOG_BASE) /** Array initializer of WDOG peripheral base addresses */ #define IP_WDOG_BASE_ADDRS { IP_WDOG_BASE } /** Array initializer of WDOG peripheral base pointers */ #define IP_WDOG_BASE_PTRS { IP_WDOG } /* ---------------------------------------------------------------------------- -- WDOG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup WDOG_Register_Masks WDOG Register Masks * @{ */ /*! @name CS - Watchdog Control and Status Register */ /*! @{ */ #define WDOG_CS_STOP_MASK (0x1U) #define WDOG_CS_STOP_SHIFT (0U) #define WDOG_CS_STOP_WIDTH (1U) #define WDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_STOP_SHIFT)) & WDOG_CS_STOP_MASK) #define WDOG_CS_WAIT_MASK (0x2U) #define WDOG_CS_WAIT_SHIFT (1U) #define WDOG_CS_WAIT_WIDTH (1U) #define WDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WAIT_SHIFT)) & WDOG_CS_WAIT_MASK) #define WDOG_CS_DBG_MASK (0x4U) #define WDOG_CS_DBG_SHIFT (2U) #define WDOG_CS_DBG_WIDTH (1U) #define WDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_DBG_SHIFT)) & WDOG_CS_DBG_MASK) #define WDOG_CS_TST_MASK (0x18U) #define WDOG_CS_TST_SHIFT (3U) #define WDOG_CS_TST_WIDTH (2U) #define WDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_TST_SHIFT)) & WDOG_CS_TST_MASK) #define WDOG_CS_UPDATE_MASK (0x20U) #define WDOG_CS_UPDATE_SHIFT (5U) #define WDOG_CS_UPDATE_WIDTH (1U) #define WDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_UPDATE_SHIFT)) & WDOG_CS_UPDATE_MASK) #define WDOG_CS_INT_MASK (0x40U) #define WDOG_CS_INT_SHIFT (6U) #define WDOG_CS_INT_WIDTH (1U) #define WDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_INT_SHIFT)) & WDOG_CS_INT_MASK) #define WDOG_CS_EN_MASK (0x80U) #define WDOG_CS_EN_SHIFT (7U) #define WDOG_CS_EN_WIDTH (1U) #define WDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_EN_SHIFT)) & WDOG_CS_EN_MASK) #define WDOG_CS_CLK_MASK (0x300U) #define WDOG_CS_CLK_SHIFT (8U) #define WDOG_CS_CLK_WIDTH (2U) #define WDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CLK_SHIFT)) & WDOG_CS_CLK_MASK) #define WDOG_CS_RCS_MASK (0x400U) #define WDOG_CS_RCS_SHIFT (10U) #define WDOG_CS_RCS_WIDTH (1U) #define WDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_RCS_SHIFT)) & WDOG_CS_RCS_MASK) #define WDOG_CS_ULK_MASK (0x800U) #define WDOG_CS_ULK_SHIFT (11U) #define WDOG_CS_ULK_WIDTH (1U) #define WDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_ULK_SHIFT)) & WDOG_CS_ULK_MASK) #define WDOG_CS_PRES_MASK (0x1000U) #define WDOG_CS_PRES_SHIFT (12U) #define WDOG_CS_PRES_WIDTH (1U) #define WDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_PRES_SHIFT)) & WDOG_CS_PRES_MASK) #define WDOG_CS_CMD32EN_MASK (0x2000U) #define WDOG_CS_CMD32EN_SHIFT (13U) #define WDOG_CS_CMD32EN_WIDTH (1U) #define WDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CMD32EN_SHIFT)) & WDOG_CS_CMD32EN_MASK) #define WDOG_CS_FLG_MASK (0x4000U) #define WDOG_CS_FLG_SHIFT (14U) #define WDOG_CS_FLG_WIDTH (1U) #define WDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_FLG_SHIFT)) & WDOG_CS_FLG_MASK) #define WDOG_CS_WIN_MASK (0x8000U) #define WDOG_CS_WIN_SHIFT (15U) #define WDOG_CS_WIN_WIDTH (1U) #define WDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WIN_SHIFT)) & WDOG_CS_WIN_MASK) /*! @} */ /*! @name CNT - Watchdog Counter Register */ /*! @{ */ #define WDOG_CNT_CNTLOW_MASK (0xFFU) #define WDOG_CNT_CNTLOW_SHIFT (0U) #define WDOG_CNT_CNTLOW_WIDTH (8U) #define WDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTLOW_SHIFT)) & WDOG_CNT_CNTLOW_MASK) #define WDOG_CNT_CNTHIGH_MASK (0xFF00U) #define WDOG_CNT_CNTHIGH_SHIFT (8U) #define WDOG_CNT_CNTHIGH_WIDTH (8U) #define WDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTHIGH_SHIFT)) & WDOG_CNT_CNTHIGH_MASK) /*! @} */ /*! @name TOVAL - Watchdog Timeout Value Register */ /*! @{ */ #define WDOG_TOVAL_TOVALLOW_MASK (0xFFU) #define WDOG_TOVAL_TOVALLOW_SHIFT (0U) #define WDOG_TOVAL_TOVALLOW_WIDTH (8U) #define WDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALLOW_SHIFT)) & WDOG_TOVAL_TOVALLOW_MASK) #define WDOG_TOVAL_TOVALHIGH_MASK (0xFF00U) #define WDOG_TOVAL_TOVALHIGH_SHIFT (8U) #define WDOG_TOVAL_TOVALHIGH_WIDTH (8U) #define WDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALHIGH_SHIFT)) & WDOG_TOVAL_TOVALHIGH_MASK) /*! @} */ /*! @name WIN - Watchdog Window Register */ /*! @{ */ #define WDOG_WIN_WINLOW_MASK (0xFFU) #define WDOG_WIN_WINLOW_SHIFT (0U) #define WDOG_WIN_WINLOW_WIDTH (8U) #define WDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINLOW_SHIFT)) & WDOG_WIN_WINLOW_MASK) #define WDOG_WIN_WINHIGH_MASK (0xFF00U) #define WDOG_WIN_WINHIGH_SHIFT (8U) #define WDOG_WIN_WINHIGH_WIDTH (8U) #define WDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINHIGH_SHIFT)) & WDOG_WIN_WINHIGH_MASK) /*! @} */ /*! * @} */ /* end of group WDOG_Register_Masks */ /*! * @} */ /* end of group WDOG_Peripheral_Access_Layer */ #endif /* #if !defined(S32K144_WDOG_H_) */