/* * Copyright 1997-2016 Freescale Semiconductor, Inc. * Copyright 2016-2022 NXP * * SPDX-License-Identifier: BSD-3-Clause */ /*! * @file S32K144W_SMC.h * @version 1.4 * @date 2022-02-09 * @brief Peripheral Access Layer for S32K144W_SMC * * This file contains register definitions and macros for easy access to their * bit fields. * * This file assumes LITTLE endian system. */ /** * @page misra_violations MISRA-C:2012 violations * * @section [global] * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced * The SoC header defines typedef for all modules. * * @section [global] * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced * The SoC header defines macros for all modules and registers. * * @section [global] * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro * These are generated macros used for accessing the bit-fields from registers. * * @section [global] * Violates MISRA 2012 Required Rule 5.1, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.2, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.4, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.5, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler * This type qualifier is needed to ensure correct I/O access and addressing. */ /* Prevention from multiple including the same memory map */ #if !defined(S32K144W_SMC_H_) /* Check if memory map has not been already included */ #define S32K144W_SMC_H_ #include "S32K144W_COMMON.h" /* ---------------------------------------------------------------------------- -- SMC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer * @{ */ /** SMC - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< SMC Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< SMC Parameter Register, offset: 0x4 */ __IO uint32_t PMPROT; /**< Power Mode Protection register, offset: 0x8 */ __IO uint32_t PMCTRL; /**< Power Mode Control register, offset: 0xC */ __IO uint32_t STOPCTRL; /**< Stop Control Register, offset: 0x10 */ __I uint32_t PMSTAT; /**< Power Mode Status register, offset: 0x14 */ } SMC_Type, *SMC_MemMapPtr; /** Number of instances of the SMC module. */ #define SMC_INSTANCE_COUNT (1u) /* SMC - Peripheral instance base addresses */ /** Peripheral SMC base address */ #define IP_SMC_BASE (0x4007E000u) /** Peripheral SMC base pointer */ #define IP_SMC ((SMC_Type *)IP_SMC_BASE) /** Array initializer of SMC peripheral base addresses */ #define IP_SMC_BASE_ADDRS { IP_SMC_BASE } /** Array initializer of SMC peripheral base pointers */ #define IP_SMC_BASE_PTRS { IP_SMC } /* ---------------------------------------------------------------------------- -- SMC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SMC_Register_Masks SMC Register Masks * @{ */ /*! @name VERID - SMC Version ID Register */ /*! @{ */ #define SMC_VERID_FEATURE_MASK (0xFFFFU) #define SMC_VERID_FEATURE_SHIFT (0U) #define SMC_VERID_FEATURE_WIDTH (16U) #define SMC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << SMC_VERID_FEATURE_SHIFT)) & SMC_VERID_FEATURE_MASK) #define SMC_VERID_MINOR_MASK (0xFF0000U) #define SMC_VERID_MINOR_SHIFT (16U) #define SMC_VERID_MINOR_WIDTH (8U) #define SMC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SMC_VERID_MINOR_SHIFT)) & SMC_VERID_MINOR_MASK) #define SMC_VERID_MAJOR_MASK (0xFF000000U) #define SMC_VERID_MAJOR_SHIFT (24U) #define SMC_VERID_MAJOR_WIDTH (8U) #define SMC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << SMC_VERID_MAJOR_SHIFT)) & SMC_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - SMC Parameter Register */ /*! @{ */ #define SMC_PARAM_EHSRUN_MASK (0x1U) #define SMC_PARAM_EHSRUN_SHIFT (0U) #define SMC_PARAM_EHSRUN_WIDTH (1U) #define SMC_PARAM_EHSRUN(x) (((uint32_t)(((uint32_t)(x)) << SMC_PARAM_EHSRUN_SHIFT)) & SMC_PARAM_EHSRUN_MASK) #define SMC_PARAM_ELLS_MASK (0x8U) #define SMC_PARAM_ELLS_SHIFT (3U) #define SMC_PARAM_ELLS_WIDTH (1U) #define SMC_PARAM_ELLS(x) (((uint32_t)(((uint32_t)(x)) << SMC_PARAM_ELLS_SHIFT)) & SMC_PARAM_ELLS_MASK) #define SMC_PARAM_ELLS2_MASK (0x20U) #define SMC_PARAM_ELLS2_SHIFT (5U) #define SMC_PARAM_ELLS2_WIDTH (1U) #define SMC_PARAM_ELLS2(x) (((uint32_t)(((uint32_t)(x)) << SMC_PARAM_ELLS2_SHIFT)) & SMC_PARAM_ELLS2_MASK) #define SMC_PARAM_EVLLS0_MASK (0x40U) #define SMC_PARAM_EVLLS0_SHIFT (6U) #define SMC_PARAM_EVLLS0_WIDTH (1U) #define SMC_PARAM_EVLLS0(x) (((uint32_t)(((uint32_t)(x)) << SMC_PARAM_EVLLS0_SHIFT)) & SMC_PARAM_EVLLS0_MASK) /*! @} */ /*! @name PMPROT - Power Mode Protection register */ /*! @{ */ #define SMC_PMPROT_AVLP_MASK (0x20U) #define SMC_PMPROT_AVLP_SHIFT (5U) #define SMC_PMPROT_AVLP_WIDTH (1U) #define SMC_PMPROT_AVLP(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK) /*! @} */ /*! @name PMCTRL - Power Mode Control register */ /*! @{ */ #define SMC_PMCTRL_STOPM_MASK (0x7U) #define SMC_PMCTRL_STOPM_SHIFT (0U) #define SMC_PMCTRL_STOPM_WIDTH (3U) #define SMC_PMCTRL_STOPM(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK) #define SMC_PMCTRL_VLPSA_MASK (0x8U) #define SMC_PMCTRL_VLPSA_SHIFT (3U) #define SMC_PMCTRL_VLPSA_WIDTH (1U) #define SMC_PMCTRL_VLPSA(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_VLPSA_SHIFT)) & SMC_PMCTRL_VLPSA_MASK) #define SMC_PMCTRL_RUNM_MASK (0x60U) #define SMC_PMCTRL_RUNM_SHIFT (5U) #define SMC_PMCTRL_RUNM_WIDTH (2U) #define SMC_PMCTRL_RUNM(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK) /*! @} */ /*! @name STOPCTRL - Stop Control Register */ /*! @{ */ #define SMC_STOPCTRL_STOPO_MASK (0xC0U) #define SMC_STOPCTRL_STOPO_SHIFT (6U) #define SMC_STOPCTRL_STOPO_WIDTH (2U) #define SMC_STOPCTRL_STOPO(x) (((uint32_t)(((uint32_t)(x)) << SMC_STOPCTRL_STOPO_SHIFT)) & SMC_STOPCTRL_STOPO_MASK) /*! @} */ /*! @name PMSTAT - Power Mode Status register */ /*! @{ */ #define SMC_PMSTAT_PMSTAT_MASK (0xFFU) #define SMC_PMSTAT_PMSTAT_SHIFT (0U) #define SMC_PMSTAT_PMSTAT_WIDTH (8U) #define SMC_PMSTAT_PMSTAT(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK) /*! @} */ /*! * @} */ /* end of group SMC_Register_Masks */ /*! * @} */ /* end of group SMC_Peripheral_Access_Layer */ #endif /* #if !defined(S32K144W_SMC_H_) */