/* * Copyright 1997-2016 Freescale Semiconductor, Inc. * Copyright 2016-2022 NXP * * SPDX-License-Identifier: BSD-3-Clause */ /*! * @file S32K142_PORT.h * @version 1.1 * @date 2022-02-01 * @brief Peripheral Access Layer for S32K142_PORT * * This file contains register definitions and macros for easy access to their * bit fields. * * This file assumes LITTLE endian system. */ /** * @page misra_violations MISRA-C:2012 violations * * @section [global] * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced * The SoC header defines typedef for all modules. * * @section [global] * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced * The SoC header defines macros for all modules and registers. * * @section [global] * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro * These are generated macros used for accessing the bit-fields from registers. * * @section [global] * Violates MISRA 2012 Required Rule 5.1, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.2, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.4, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.5, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler * This type qualifier is needed to ensure correct I/O access and addressing. */ /* Prevention from multiple including the same memory map */ #if !defined(S32K142_PORT_H_) /* Check if memory map has not been already included */ #define S32K142_PORT_H_ #include "S32K142_COMMON.h" /* ---------------------------------------------------------------------------- -- PORT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer * @{ */ /** PORT - Size of Registers Arrays */ #define PORT_PCR_COUNT 32u /** PORT - Register Layout Typedef */ typedef struct { __IO uint32_t PCR[PORT_PCR_COUNT]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */ __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */ __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */ __O uint32_t GICLR; /**< Global Interrupt Control Low Register, offset: 0x88 */ __O uint32_t GICHR; /**< Global Interrupt Control High Register, offset: 0x8C */ uint8_t RESERVED_0[16]; __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */ uint8_t RESERVED_1[28]; __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */ __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */ __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */ } PORT_Type, *PORT_MemMapPtr; /** Number of instances of the PORT module. */ #define PORT_INSTANCE_COUNT (5u) /* PORT - Peripheral instance base addresses */ /** Peripheral PORTA base address */ #define IP_PORTA_BASE (0x40049000u) /** Peripheral PORTA base pointer */ #define IP_PORTA ((PORT_Type *)IP_PORTA_BASE) /** Peripheral PORTB base address */ #define IP_PORTB_BASE (0x4004A000u) /** Peripheral PORTB base pointer */ #define IP_PORTB ((PORT_Type *)IP_PORTB_BASE) /** Peripheral PORTC base address */ #define IP_PORTC_BASE (0x4004B000u) /** Peripheral PORTC base pointer */ #define IP_PORTC ((PORT_Type *)IP_PORTC_BASE) /** Peripheral PORTD base address */ #define IP_PORTD_BASE (0x4004C000u) /** Peripheral PORTD base pointer */ #define IP_PORTD ((PORT_Type *)IP_PORTD_BASE) /** Peripheral PORTE base address */ #define IP_PORTE_BASE (0x4004D000u) /** Peripheral PORTE base pointer */ #define IP_PORTE ((PORT_Type *)IP_PORTE_BASE) /** Array initializer of PORT peripheral base addresses */ #define IP_PORT_BASE_ADDRS { IP_PORTA_BASE, IP_PORTB_BASE, IP_PORTC_BASE, IP_PORTD_BASE, IP_PORTE_BASE } /** Array initializer of PORT peripheral base pointers */ #define IP_PORT_BASE_PTRS { IP_PORTA, IP_PORTB, IP_PORTC, IP_PORTD, IP_PORTE } /* ---------------------------------------------------------------------------- -- PORT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PORT_Register_Masks PORT Register Masks * @{ */ /*! @name PCR - Pin Control Register n */ /*! @{ */ #define PORT_PCR_PS_MASK (0x1U) #define PORT_PCR_PS_SHIFT (0U) #define PORT_PCR_PS_WIDTH (1U) #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK) #define PORT_PCR_PE_MASK (0x2U) #define PORT_PCR_PE_SHIFT (1U) #define PORT_PCR_PE_WIDTH (1U) #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK) #define PORT_PCR_PFE_MASK (0x10U) #define PORT_PCR_PFE_SHIFT (4U) #define PORT_PCR_PFE_WIDTH (1U) #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK) #define PORT_PCR_DSE_MASK (0x40U) #define PORT_PCR_DSE_SHIFT (6U) #define PORT_PCR_DSE_WIDTH (1U) #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK) #define PORT_PCR_MUX_MASK (0x700U) #define PORT_PCR_MUX_SHIFT (8U) #define PORT_PCR_MUX_WIDTH (3U) #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) #define PORT_PCR_LK_MASK (0x8000U) #define PORT_PCR_LK_SHIFT (15U) #define PORT_PCR_LK_WIDTH (1U) #define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK) #define PORT_PCR_IRQC_MASK (0xF0000U) #define PORT_PCR_IRQC_SHIFT (16U) #define PORT_PCR_IRQC_WIDTH (4U) #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK) #define PORT_PCR_ISF_MASK (0x1000000U) #define PORT_PCR_ISF_SHIFT (24U) #define PORT_PCR_ISF_WIDTH (1U) #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK) /*! @} */ /*! @name GPCLR - Global Pin Control Low Register */ /*! @{ */ #define PORT_GPCLR_GPWD_MASK (0xFFFFU) #define PORT_GPCLR_GPWD_SHIFT (0U) #define PORT_GPCLR_GPWD_WIDTH (16U) #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK) #define PORT_GPCLR_GPWE_MASK (0xFFFF0000U) #define PORT_GPCLR_GPWE_SHIFT (16U) #define PORT_GPCLR_GPWE_WIDTH (16U) #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK) /*! @} */ /*! @name GPCHR - Global Pin Control High Register */ /*! @{ */ #define PORT_GPCHR_GPWD_MASK (0xFFFFU) #define PORT_GPCHR_GPWD_SHIFT (0U) #define PORT_GPCHR_GPWD_WIDTH (16U) #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK) #define PORT_GPCHR_GPWE_MASK (0xFFFF0000U) #define PORT_GPCHR_GPWE_SHIFT (16U) #define PORT_GPCHR_GPWE_WIDTH (16U) #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK) /*! @} */ /*! @name GICLR - Global Interrupt Control Low Register */ /*! @{ */ #define PORT_GICLR_GIWE_MASK (0xFFFFU) #define PORT_GICLR_GIWE_SHIFT (0U) #define PORT_GICLR_GIWE_WIDTH (16U) #define PORT_GICLR_GIWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICLR_GIWE_SHIFT)) & PORT_GICLR_GIWE_MASK) #define PORT_GICLR_GIWD_MASK (0xFFFF0000U) #define PORT_GICLR_GIWD_SHIFT (16U) #define PORT_GICLR_GIWD_WIDTH (16U) #define PORT_GICLR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICLR_GIWD_SHIFT)) & PORT_GICLR_GIWD_MASK) /*! @} */ /*! @name GICHR - Global Interrupt Control High Register */ /*! @{ */ #define PORT_GICHR_GIWE_MASK (0xFFFFU) #define PORT_GICHR_GIWE_SHIFT (0U) #define PORT_GICHR_GIWE_WIDTH (16U) #define PORT_GICHR_GIWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICHR_GIWE_SHIFT)) & PORT_GICHR_GIWE_MASK) #define PORT_GICHR_GIWD_MASK (0xFFFF0000U) #define PORT_GICHR_GIWD_SHIFT (16U) #define PORT_GICHR_GIWD_WIDTH (16U) #define PORT_GICHR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICHR_GIWD_SHIFT)) & PORT_GICHR_GIWD_MASK) /*! @} */ /*! @name ISFR - Interrupt Status Flag Register */ /*! @{ */ #define PORT_ISFR_ISF_MASK (0xFFFFFFFFU) #define PORT_ISFR_ISF_SHIFT (0U) #define PORT_ISFR_ISF_WIDTH (32U) #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK) /*! @} */ /*! @name DFER - Digital Filter Enable Register */ /*! @{ */ #define PORT_DFER_DFE_MASK (0xFFFFFFFFU) #define PORT_DFER_DFE_SHIFT (0U) #define PORT_DFER_DFE_WIDTH (32U) #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK) /*! @} */ /*! @name DFCR - Digital Filter Clock Register */ /*! @{ */ #define PORT_DFCR_CS_MASK (0x1U) #define PORT_DFCR_CS_SHIFT (0U) #define PORT_DFCR_CS_WIDTH (1U) #define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK) /*! @} */ /*! @name DFWR - Digital Filter Width Register */ /*! @{ */ #define PORT_DFWR_FILT_MASK (0x1FU) #define PORT_DFWR_FILT_SHIFT (0U) #define PORT_DFWR_FILT_WIDTH (5U) #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK) /*! @} */ /*! * @} */ /* end of group PORT_Register_Masks */ /*! * @} */ /* end of group PORT_Peripheral_Access_Layer */ #endif /* #if !defined(S32K142_PORT_H_) */