/* * Copyright 1997-2016 Freescale Semiconductor, Inc. * Copyright 2016-2022 NXP * * SPDX-License-Identifier: BSD-3-Clause */ /*! * @file S32K142_ADC.h * @version 1.1 * @date 2022-02-01 * @brief Peripheral Access Layer for S32K142_ADC * * This file contains register definitions and macros for easy access to their * bit fields. * * This file assumes LITTLE endian system. */ /** * @page misra_violations MISRA-C:2012 violations * * @section [global] * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced * The SoC header defines typedef for all modules. * * @section [global] * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced * The SoC header defines macros for all modules and registers. * * @section [global] * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro * These are generated macros used for accessing the bit-fields from registers. * * @section [global] * Violates MISRA 2012 Required Rule 5.1, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.2, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.4, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.5, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler * This type qualifier is needed to ensure correct I/O access and addressing. */ /* Prevention from multiple including the same memory map */ #if !defined(S32K142_ADC_H_) /* Check if memory map has not been already included */ #define S32K142_ADC_H_ #include "S32K142_COMMON.h" /* ---------------------------------------------------------------------------- -- ADC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer * @{ */ /** ADC - Size of Registers Arrays */ #define ADC_SC1_COUNT 16u #define ADC_R_COUNT 16u #define ADC_CV_COUNT 2u /** ADC - Register Layout Typedef */ typedef struct { __IO uint32_t SC1[ADC_SC1_COUNT]; /**< ADC Status and Control Register 1, array offset: 0x0, array step: 0x4 */ __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x40 */ __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0x44 */ __I uint32_t R[ADC_R_COUNT]; /**< ADC Data Result Registers, array offset: 0x48, array step: 0x4 */ __IO uint32_t CV[ADC_CV_COUNT]; /**< Compare Value Registers, array offset: 0x88, array step: 0x4 */ __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x90 */ __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x94 */ __IO uint32_t BASE_OFS; /**< BASE Offset Register, offset: 0x98 */ __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x9C */ __IO uint32_t USR_OFS; /**< USER Offset Correction Register, offset: 0xA0 */ __IO uint32_t XOFS; /**< ADC X Offset Correction Register, offset: 0xA4 */ __IO uint32_t YOFS; /**< ADC Y Offset Correction Register, offset: 0xA8 */ __IO uint32_t G; /**< ADC Gain Register, offset: 0xAC */ __IO uint32_t UG; /**< ADC User Gain Register, offset: 0xB0 */ __IO uint32_t CLPS; /**< ADC General Calibration Value Register S, offset: 0xB4 */ __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register 3, offset: 0xB8 */ __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register 2, offset: 0xBC */ __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register 1, offset: 0xC0 */ __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register 0, offset: 0xC4 */ __IO uint32_t CLPX; /**< ADC Plus-Side General Calibration Value Register X, offset: 0xC8 */ __IO uint32_t CLP9; /**< ADC Plus-Side General Calibration Value Register 9, offset: 0xCC */ __IO uint32_t CLPS_OFS; /**< ADC General Calibration Offset Value Register S, offset: 0xD0 */ __IO uint32_t CLP3_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 3, offset: 0xD4 */ __IO uint32_t CLP2_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 2, offset: 0xD8 */ __IO uint32_t CLP1_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 1, offset: 0xDC */ __IO uint32_t CLP0_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 0, offset: 0xE0 */ __IO uint32_t CLPX_OFS; /**< ADC Plus-Side General Calibration Offset Value Register X, offset: 0xE4 */ __IO uint32_t CLP9_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 9, offset: 0xE8 */ } ADC_Type, *ADC_MemMapPtr; /** Number of instances of the ADC module. */ #define ADC_INSTANCE_COUNT (2u) /* ADC - Peripheral instance base addresses */ /** Peripheral ADC0 base address */ #define IP_ADC0_BASE (0x4003B000u) /** Peripheral ADC0 base pointer */ #define IP_ADC0 ((ADC_Type *)IP_ADC0_BASE) /** Peripheral ADC1 base address */ #define IP_ADC1_BASE (0x40027000u) /** Peripheral ADC1 base pointer */ #define IP_ADC1 ((ADC_Type *)IP_ADC1_BASE) /** Array initializer of ADC peripheral base addresses */ #define IP_ADC_BASE_ADDRS { IP_ADC0_BASE, IP_ADC1_BASE } /** Array initializer of ADC peripheral base pointers */ #define IP_ADC_BASE_PTRS { IP_ADC0, IP_ADC1 } /* ---------------------------------------------------------------------------- -- ADC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Register_Masks ADC Register Masks * @{ */ /*! @name SC1 - ADC Status and Control Register 1 */ /*! @{ */ #define ADC_SC1_ADCH_MASK (0x1FU) #define ADC_SC1_ADCH_SHIFT (0U) #define ADC_SC1_ADCH_WIDTH (5U) #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK) #define ADC_SC1_AIEN_MASK (0x40U) #define ADC_SC1_AIEN_SHIFT (6U) #define ADC_SC1_AIEN_WIDTH (1U) #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK) #define ADC_SC1_COCO_MASK (0x80U) #define ADC_SC1_COCO_SHIFT (7U) #define ADC_SC1_COCO_WIDTH (1U) #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK) /*! @} */ /*! @name CFG1 - ADC Configuration Register 1 */ /*! @{ */ #define ADC_CFG1_ADICLK_MASK (0x3U) #define ADC_CFG1_ADICLK_SHIFT (0U) #define ADC_CFG1_ADICLK_WIDTH (2U) #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK) #define ADC_CFG1_MODE_MASK (0xCU) #define ADC_CFG1_MODE_SHIFT (2U) #define ADC_CFG1_MODE_WIDTH (2U) #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK) #define ADC_CFG1_ADIV_MASK (0x60U) #define ADC_CFG1_ADIV_SHIFT (5U) #define ADC_CFG1_ADIV_WIDTH (2U) #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK) #define ADC_CFG1_CLRLTRG_MASK (0x100U) #define ADC_CFG1_CLRLTRG_SHIFT (8U) #define ADC_CFG1_CLRLTRG_WIDTH (1U) #define ADC_CFG1_CLRLTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_CLRLTRG_SHIFT)) & ADC_CFG1_CLRLTRG_MASK) /*! @} */ /*! @name CFG2 - ADC Configuration Register 2 */ /*! @{ */ #define ADC_CFG2_SMPLTS_MASK (0xFFU) #define ADC_CFG2_SMPLTS_SHIFT (0U) #define ADC_CFG2_SMPLTS_WIDTH (8U) #define ADC_CFG2_SMPLTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_SMPLTS_SHIFT)) & ADC_CFG2_SMPLTS_MASK) /*! @} */ /*! @name R - ADC Data Result Registers */ /*! @{ */ #define ADC_R_D_MASK (0xFFFU) #define ADC_R_D_SHIFT (0U) #define ADC_R_D_WIDTH (12U) #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK) /*! @} */ /*! @name CV - Compare Value Registers */ /*! @{ */ #define ADC_CV_CV_MASK (0xFFFFU) #define ADC_CV_CV_SHIFT (0U) #define ADC_CV_CV_WIDTH (16U) #define ADC_CV_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV_SHIFT)) & ADC_CV_CV_MASK) /*! @} */ /*! @name SC2 - Status and Control Register 2 */ /*! @{ */ #define ADC_SC2_REFSEL_MASK (0x3U) #define ADC_SC2_REFSEL_SHIFT (0U) #define ADC_SC2_REFSEL_WIDTH (2U) #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK) #define ADC_SC2_DMAEN_MASK (0x4U) #define ADC_SC2_DMAEN_SHIFT (2U) #define ADC_SC2_DMAEN_WIDTH (1U) #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK) #define ADC_SC2_ACREN_MASK (0x8U) #define ADC_SC2_ACREN_SHIFT (3U) #define ADC_SC2_ACREN_WIDTH (1U) #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK) #define ADC_SC2_ACFGT_MASK (0x10U) #define ADC_SC2_ACFGT_SHIFT (4U) #define ADC_SC2_ACFGT_WIDTH (1U) #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK) #define ADC_SC2_ACFE_MASK (0x20U) #define ADC_SC2_ACFE_SHIFT (5U) #define ADC_SC2_ACFE_WIDTH (1U) #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK) #define ADC_SC2_ADTRG_MASK (0x40U) #define ADC_SC2_ADTRG_SHIFT (6U) #define ADC_SC2_ADTRG_WIDTH (1U) #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK) #define ADC_SC2_ADACT_MASK (0x80U) #define ADC_SC2_ADACT_SHIFT (7U) #define ADC_SC2_ADACT_WIDTH (1U) #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK) #define ADC_SC2_TRGPRNUM_MASK (0x6000U) #define ADC_SC2_TRGPRNUM_SHIFT (13U) #define ADC_SC2_TRGPRNUM_WIDTH (2U) #define ADC_SC2_TRGPRNUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_TRGPRNUM_SHIFT)) & ADC_SC2_TRGPRNUM_MASK) #define ADC_SC2_TRGSTLAT_MASK (0xF0000U) #define ADC_SC2_TRGSTLAT_SHIFT (16U) #define ADC_SC2_TRGSTLAT_WIDTH (4U) #define ADC_SC2_TRGSTLAT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_TRGSTLAT_SHIFT)) & ADC_SC2_TRGSTLAT_MASK) #define ADC_SC2_TRGSTERR_MASK (0xF000000U) #define ADC_SC2_TRGSTERR_SHIFT (24U) #define ADC_SC2_TRGSTERR_WIDTH (4U) #define ADC_SC2_TRGSTERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_TRGSTERR_SHIFT)) & ADC_SC2_TRGSTERR_MASK) /*! @} */ /*! @name SC3 - Status and Control Register 3 */ /*! @{ */ #define ADC_SC3_AVGS_MASK (0x3U) #define ADC_SC3_AVGS_SHIFT (0U) #define ADC_SC3_AVGS_WIDTH (2U) #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK) #define ADC_SC3_AVGE_MASK (0x4U) #define ADC_SC3_AVGE_SHIFT (2U) #define ADC_SC3_AVGE_WIDTH (1U) #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK) #define ADC_SC3_ADCO_MASK (0x8U) #define ADC_SC3_ADCO_SHIFT (3U) #define ADC_SC3_ADCO_WIDTH (1U) #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK) #define ADC_SC3_CAL_MASK (0x80U) #define ADC_SC3_CAL_SHIFT (7U) #define ADC_SC3_CAL_WIDTH (1U) #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK) /*! @} */ /*! @name BASE_OFS - BASE Offset Register */ /*! @{ */ #define ADC_BASE_OFS_BA_OFS_MASK (0xFFU) #define ADC_BASE_OFS_BA_OFS_SHIFT (0U) #define ADC_BASE_OFS_BA_OFS_WIDTH (8U) #define ADC_BASE_OFS_BA_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_BASE_OFS_BA_OFS_SHIFT)) & ADC_BASE_OFS_BA_OFS_MASK) /*! @} */ /*! @name OFS - ADC Offset Correction Register */ /*! @{ */ #define ADC_OFS_OFS_MASK (0xFFFFU) #define ADC_OFS_OFS_SHIFT (0U) #define ADC_OFS_OFS_WIDTH (16U) #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) /*! @} */ /*! @name USR_OFS - USER Offset Correction Register */ /*! @{ */ #define ADC_USR_OFS_USR_OFS_MASK (0xFFU) #define ADC_USR_OFS_USR_OFS_SHIFT (0U) #define ADC_USR_OFS_USR_OFS_WIDTH (8U) #define ADC_USR_OFS_USR_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_USR_OFS_USR_OFS_SHIFT)) & ADC_USR_OFS_USR_OFS_MASK) /*! @} */ /*! @name XOFS - ADC X Offset Correction Register */ /*! @{ */ #define ADC_XOFS_XOFS_MASK (0x3FU) #define ADC_XOFS_XOFS_SHIFT (0U) #define ADC_XOFS_XOFS_WIDTH (6U) #define ADC_XOFS_XOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_XOFS_XOFS_SHIFT)) & ADC_XOFS_XOFS_MASK) /*! @} */ /*! @name YOFS - ADC Y Offset Correction Register */ /*! @{ */ #define ADC_YOFS_YOFS_MASK (0xFFU) #define ADC_YOFS_YOFS_SHIFT (0U) #define ADC_YOFS_YOFS_WIDTH (8U) #define ADC_YOFS_YOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_YOFS_YOFS_SHIFT)) & ADC_YOFS_YOFS_MASK) /*! @} */ /*! @name G - ADC Gain Register */ /*! @{ */ #define ADC_G_G_MASK (0x7FFU) #define ADC_G_G_SHIFT (0U) #define ADC_G_G_WIDTH (11U) #define ADC_G_G(x) (((uint32_t)(((uint32_t)(x)) << ADC_G_G_SHIFT)) & ADC_G_G_MASK) /*! @} */ /*! @name UG - ADC User Gain Register */ /*! @{ */ #define ADC_UG_UG_MASK (0x3FFU) #define ADC_UG_UG_SHIFT (0U) #define ADC_UG_UG_WIDTH (10U) #define ADC_UG_UG(x) (((uint32_t)(((uint32_t)(x)) << ADC_UG_UG_SHIFT)) & ADC_UG_UG_MASK) /*! @} */ /*! @name CLPS - ADC General Calibration Value Register S */ /*! @{ */ #define ADC_CLPS_CLPS_MASK (0x7FU) #define ADC_CLPS_CLPS_SHIFT (0U) #define ADC_CLPS_CLPS_WIDTH (7U) #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK) /*! @} */ /*! @name CLP3 - ADC Plus-Side General Calibration Value Register 3 */ /*! @{ */ #define ADC_CLP3_CLP3_MASK (0x3FFU) #define ADC_CLP3_CLP3_SHIFT (0U) #define ADC_CLP3_CLP3_WIDTH (10U) #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK) /*! @} */ /*! @name CLP2 - ADC Plus-Side General Calibration Value Register 2 */ /*! @{ */ #define ADC_CLP2_CLP2_MASK (0x3FFU) #define ADC_CLP2_CLP2_SHIFT (0U) #define ADC_CLP2_CLP2_WIDTH (10U) #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK) /*! @} */ /*! @name CLP1 - ADC Plus-Side General Calibration Value Register 1 */ /*! @{ */ #define ADC_CLP1_CLP1_MASK (0x1FFU) #define ADC_CLP1_CLP1_SHIFT (0U) #define ADC_CLP1_CLP1_WIDTH (9U) #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK) /*! @} */ /*! @name CLP0 - ADC Plus-Side General Calibration Value Register 0 */ /*! @{ */ #define ADC_CLP0_CLP0_MASK (0xFFU) #define ADC_CLP0_CLP0_SHIFT (0U) #define ADC_CLP0_CLP0_WIDTH (8U) #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK) /*! @} */ /*! @name CLPX - ADC Plus-Side General Calibration Value Register X */ /*! @{ */ #define ADC_CLPX_CLPX_MASK (0x7FU) #define ADC_CLPX_CLPX_SHIFT (0U) #define ADC_CLPX_CLPX_WIDTH (7U) #define ADC_CLPX_CLPX(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPX_CLPX_SHIFT)) & ADC_CLPX_CLPX_MASK) /*! @} */ /*! @name CLP9 - ADC Plus-Side General Calibration Value Register 9 */ /*! @{ */ #define ADC_CLP9_CLP9_MASK (0x7FU) #define ADC_CLP9_CLP9_SHIFT (0U) #define ADC_CLP9_CLP9_WIDTH (7U) #define ADC_CLP9_CLP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP9_CLP9_SHIFT)) & ADC_CLP9_CLP9_MASK) /*! @} */ /*! @name CLPS_OFS - ADC General Calibration Offset Value Register S */ /*! @{ */ #define ADC_CLPS_OFS_CLPS_OFS_MASK (0xFU) #define ADC_CLPS_OFS_CLPS_OFS_SHIFT (0U) #define ADC_CLPS_OFS_CLPS_OFS_WIDTH (4U) #define ADC_CLPS_OFS_CLPS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_OFS_CLPS_OFS_SHIFT)) & ADC_CLPS_OFS_CLPS_OFS_MASK) /*! @} */ /*! @name CLP3_OFS - ADC Plus-Side General Calibration Offset Value Register 3 */ /*! @{ */ #define ADC_CLP3_OFS_CLP3_OFS_MASK (0xFU) #define ADC_CLP3_OFS_CLP3_OFS_SHIFT (0U) #define ADC_CLP3_OFS_CLP3_OFS_WIDTH (4U) #define ADC_CLP3_OFS_CLP3_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_OFS_CLP3_OFS_SHIFT)) & ADC_CLP3_OFS_CLP3_OFS_MASK) /*! @} */ /*! @name CLP2_OFS - ADC Plus-Side General Calibration Offset Value Register 2 */ /*! @{ */ #define ADC_CLP2_OFS_CLP2_OFS_MASK (0xFU) #define ADC_CLP2_OFS_CLP2_OFS_SHIFT (0U) #define ADC_CLP2_OFS_CLP2_OFS_WIDTH (4U) #define ADC_CLP2_OFS_CLP2_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_OFS_CLP2_OFS_SHIFT)) & ADC_CLP2_OFS_CLP2_OFS_MASK) /*! @} */ /*! @name CLP1_OFS - ADC Plus-Side General Calibration Offset Value Register 1 */ /*! @{ */ #define ADC_CLP1_OFS_CLP1_OFS_MASK (0xFU) #define ADC_CLP1_OFS_CLP1_OFS_SHIFT (0U) #define ADC_CLP1_OFS_CLP1_OFS_WIDTH (4U) #define ADC_CLP1_OFS_CLP1_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_OFS_CLP1_OFS_SHIFT)) & ADC_CLP1_OFS_CLP1_OFS_MASK) /*! @} */ /*! @name CLP0_OFS - ADC Plus-Side General Calibration Offset Value Register 0 */ /*! @{ */ #define ADC_CLP0_OFS_CLP0_OFS_MASK (0xFU) #define ADC_CLP0_OFS_CLP0_OFS_SHIFT (0U) #define ADC_CLP0_OFS_CLP0_OFS_WIDTH (4U) #define ADC_CLP0_OFS_CLP0_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_OFS_CLP0_OFS_SHIFT)) & ADC_CLP0_OFS_CLP0_OFS_MASK) /*! @} */ /*! @name CLPX_OFS - ADC Plus-Side General Calibration Offset Value Register X */ /*! @{ */ #define ADC_CLPX_OFS_CLPX_OFS_MASK (0xFFFU) #define ADC_CLPX_OFS_CLPX_OFS_SHIFT (0U) #define ADC_CLPX_OFS_CLPX_OFS_WIDTH (12U) #define ADC_CLPX_OFS_CLPX_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPX_OFS_CLPX_OFS_SHIFT)) & ADC_CLPX_OFS_CLPX_OFS_MASK) /*! @} */ /*! @name CLP9_OFS - ADC Plus-Side General Calibration Offset Value Register 9 */ /*! @{ */ #define ADC_CLP9_OFS_CLP9_OFS_MASK (0xFFFU) #define ADC_CLP9_OFS_CLP9_OFS_SHIFT (0U) #define ADC_CLP9_OFS_CLP9_OFS_WIDTH (12U) #define ADC_CLP9_OFS_CLP9_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP9_OFS_CLP9_OFS_SHIFT)) & ADC_CLP9_OFS_CLP9_OFS_MASK) /*! @} */ /*! * @} */ /* end of group ADC_Register_Masks */ /*! * @} */ /* end of group ADC_Peripheral_Access_Layer */ #endif /* #if !defined(S32K142_ADC_H_) */