/* * Copyright 1997-2016 Freescale Semiconductor, Inc. * Copyright 2016-2022 NXP * * SPDX-License-Identifier: BSD-3-Clause */ /*! * @file S32K118_CMP.h * @version 1.1 * @date 2022-01-24 * @brief Peripheral Access Layer for S32K118_CMP * * This file contains register definitions and macros for easy access to their * bit fields. * * This file assumes LITTLE endian system. */ /** * @page misra_violations MISRA-C:2012 violations * * @section [global] * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced * The SoC header defines typedef for all modules. * * @section [global] * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced * The SoC header defines macros for all modules and registers. * * @section [global] * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro * These are generated macros used for accessing the bit-fields from registers. * * @section [global] * Violates MISRA 2012 Required Rule 5.1, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.2, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.4, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.5, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler * This type qualifier is needed to ensure correct I/O access and addressing. */ /* Prevention from multiple including the same memory map */ #if !defined(S32K118_CMP_H_) /* Check if memory map has not been already included */ #define S32K118_CMP_H_ #include "S32K118_COMMON.h" /* ---------------------------------------------------------------------------- -- CMP Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer * @{ */ /** CMP - Register Layout Typedef */ typedef struct { __IO uint32_t C0; /**< CMP Control Register 0, offset: 0x0 */ __IO uint32_t C1; /**< CMP Control Register 1, offset: 0x4 */ __IO uint32_t C2; /**< CMP Control Register 2, offset: 0x8 */ } CMP_Type, *CMP_MemMapPtr; /** Number of instances of the CMP module. */ #define CMP_INSTANCE_COUNT (1u) /* CMP - Peripheral instance base addresses */ /** Peripheral CMP0 base address */ #define IP_CMP0_BASE (0x40073000u) /** Peripheral CMP0 base pointer */ #define IP_CMP0 ((CMP_Type *)IP_CMP0_BASE) /** Array initializer of CMP peripheral base addresses */ #define IP_CMP_BASE_ADDRS { IP_CMP0_BASE } /** Array initializer of CMP peripheral base pointers */ #define IP_CMP_BASE_PTRS { IP_CMP0 } /* ---------------------------------------------------------------------------- -- CMP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CMP_Register_Masks CMP Register Masks * @{ */ /*! @name C0 - CMP Control Register 0 */ /*! @{ */ #define CMP_C0_HYSTCTR_MASK (0x3U) #define CMP_C0_HYSTCTR_SHIFT (0U) #define CMP_C0_HYSTCTR_WIDTH (2U) #define CMP_C0_HYSTCTR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_HYSTCTR_SHIFT)) & CMP_C0_HYSTCTR_MASK) #define CMP_C0_OFFSET_MASK (0x4U) #define CMP_C0_OFFSET_SHIFT (2U) #define CMP_C0_OFFSET_WIDTH (1U) #define CMP_C0_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_OFFSET_SHIFT)) & CMP_C0_OFFSET_MASK) #define CMP_C0_FILTER_CNT_MASK (0x70U) #define CMP_C0_FILTER_CNT_SHIFT (4U) #define CMP_C0_FILTER_CNT_WIDTH (3U) #define CMP_C0_FILTER_CNT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FILTER_CNT_SHIFT)) & CMP_C0_FILTER_CNT_MASK) #define CMP_C0_EN_MASK (0x100U) #define CMP_C0_EN_SHIFT (8U) #define CMP_C0_EN_WIDTH (1U) #define CMP_C0_EN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_EN_SHIFT)) & CMP_C0_EN_MASK) #define CMP_C0_OPE_MASK (0x200U) #define CMP_C0_OPE_SHIFT (9U) #define CMP_C0_OPE_WIDTH (1U) #define CMP_C0_OPE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_OPE_SHIFT)) & CMP_C0_OPE_MASK) #define CMP_C0_COS_MASK (0x400U) #define CMP_C0_COS_SHIFT (10U) #define CMP_C0_COS_WIDTH (1U) #define CMP_C0_COS(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COS_SHIFT)) & CMP_C0_COS_MASK) #define CMP_C0_INVT_MASK (0x800U) #define CMP_C0_INVT_SHIFT (11U) #define CMP_C0_INVT_WIDTH (1U) #define CMP_C0_INVT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_INVT_SHIFT)) & CMP_C0_INVT_MASK) #define CMP_C0_PMODE_MASK (0x1000U) #define CMP_C0_PMODE_SHIFT (12U) #define CMP_C0_PMODE_WIDTH (1U) #define CMP_C0_PMODE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_PMODE_SHIFT)) & CMP_C0_PMODE_MASK) #define CMP_C0_WE_MASK (0x4000U) #define CMP_C0_WE_SHIFT (14U) #define CMP_C0_WE_WIDTH (1U) #define CMP_C0_WE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_WE_SHIFT)) & CMP_C0_WE_MASK) #define CMP_C0_SE_MASK (0x8000U) #define CMP_C0_SE_SHIFT (15U) #define CMP_C0_SE_WIDTH (1U) #define CMP_C0_SE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_SE_SHIFT)) & CMP_C0_SE_MASK) #define CMP_C0_FPR_MASK (0xFF0000U) #define CMP_C0_FPR_SHIFT (16U) #define CMP_C0_FPR_WIDTH (8U) #define CMP_C0_FPR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FPR_SHIFT)) & CMP_C0_FPR_MASK) #define CMP_C0_COUT_MASK (0x1000000U) #define CMP_C0_COUT_SHIFT (24U) #define CMP_C0_COUT_WIDTH (1U) #define CMP_C0_COUT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COUT_SHIFT)) & CMP_C0_COUT_MASK) #define CMP_C0_CFF_MASK (0x2000000U) #define CMP_C0_CFF_SHIFT (25U) #define CMP_C0_CFF_WIDTH (1U) #define CMP_C0_CFF(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFF_SHIFT)) & CMP_C0_CFF_MASK) #define CMP_C0_CFR_MASK (0x4000000U) #define CMP_C0_CFR_SHIFT (26U) #define CMP_C0_CFR_WIDTH (1U) #define CMP_C0_CFR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK) #define CMP_C0_IEF_MASK (0x8000000U) #define CMP_C0_IEF_SHIFT (27U) #define CMP_C0_IEF_WIDTH (1U) #define CMP_C0_IEF(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IEF_SHIFT)) & CMP_C0_IEF_MASK) #define CMP_C0_IER_MASK (0x10000000U) #define CMP_C0_IER_SHIFT (28U) #define CMP_C0_IER_WIDTH (1U) #define CMP_C0_IER(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IER_SHIFT)) & CMP_C0_IER_MASK) #define CMP_C0_DMAEN_MASK (0x40000000U) #define CMP_C0_DMAEN_SHIFT (30U) #define CMP_C0_DMAEN_WIDTH (1U) #define CMP_C0_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_DMAEN_SHIFT)) & CMP_C0_DMAEN_MASK) /*! @} */ /*! @name C1 - CMP Control Register 1 */ /*! @{ */ #define CMP_C1_VOSEL_MASK (0xFFU) #define CMP_C1_VOSEL_SHIFT (0U) #define CMP_C1_VOSEL_WIDTH (8U) #define CMP_C1_VOSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VOSEL_SHIFT)) & CMP_C1_VOSEL_MASK) #define CMP_C1_MSEL_MASK (0x700U) #define CMP_C1_MSEL_SHIFT (8U) #define CMP_C1_MSEL_WIDTH (3U) #define CMP_C1_MSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_MSEL_SHIFT)) & CMP_C1_MSEL_MASK) #define CMP_C1_PSEL_MASK (0x3800U) #define CMP_C1_PSEL_SHIFT (11U) #define CMP_C1_PSEL_WIDTH (3U) #define CMP_C1_PSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_PSEL_SHIFT)) & CMP_C1_PSEL_MASK) #define CMP_C1_VRSEL_MASK (0x4000U) #define CMP_C1_VRSEL_SHIFT (14U) #define CMP_C1_VRSEL_WIDTH (1U) #define CMP_C1_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VRSEL_SHIFT)) & CMP_C1_VRSEL_MASK) #define CMP_C1_DACEN_MASK (0x8000U) #define CMP_C1_DACEN_SHIFT (15U) #define CMP_C1_DACEN_WIDTH (1U) #define CMP_C1_DACEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DACEN_SHIFT)) & CMP_C1_DACEN_MASK) #define CMP_C1_CHN0_MASK (0x10000U) #define CMP_C1_CHN0_SHIFT (16U) #define CMP_C1_CHN0_WIDTH (1U) #define CMP_C1_CHN0(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN0_SHIFT)) & CMP_C1_CHN0_MASK) #define CMP_C1_CHN1_MASK (0x20000U) #define CMP_C1_CHN1_SHIFT (17U) #define CMP_C1_CHN1_WIDTH (1U) #define CMP_C1_CHN1(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN1_SHIFT)) & CMP_C1_CHN1_MASK) #define CMP_C1_CHN2_MASK (0x40000U) #define CMP_C1_CHN2_SHIFT (18U) #define CMP_C1_CHN2_WIDTH (1U) #define CMP_C1_CHN2(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN2_SHIFT)) & CMP_C1_CHN2_MASK) #define CMP_C1_CHN3_MASK (0x80000U) #define CMP_C1_CHN3_SHIFT (19U) #define CMP_C1_CHN3_WIDTH (1U) #define CMP_C1_CHN3(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN3_SHIFT)) & CMP_C1_CHN3_MASK) #define CMP_C1_CHN4_MASK (0x100000U) #define CMP_C1_CHN4_SHIFT (20U) #define CMP_C1_CHN4_WIDTH (1U) #define CMP_C1_CHN4(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN4_SHIFT)) & CMP_C1_CHN4_MASK) #define CMP_C1_CHN5_MASK (0x200000U) #define CMP_C1_CHN5_SHIFT (21U) #define CMP_C1_CHN5_WIDTH (1U) #define CMP_C1_CHN5(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN5_SHIFT)) & CMP_C1_CHN5_MASK) #define CMP_C1_CHN6_MASK (0x400000U) #define CMP_C1_CHN6_SHIFT (22U) #define CMP_C1_CHN6_WIDTH (1U) #define CMP_C1_CHN6(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN6_SHIFT)) & CMP_C1_CHN6_MASK) #define CMP_C1_CHN7_MASK (0x800000U) #define CMP_C1_CHN7_SHIFT (23U) #define CMP_C1_CHN7_WIDTH (1U) #define CMP_C1_CHN7(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN7_SHIFT)) & CMP_C1_CHN7_MASK) #define CMP_C1_INNSEL_MASK (0x3000000U) #define CMP_C1_INNSEL_SHIFT (24U) #define CMP_C1_INNSEL_WIDTH (2U) #define CMP_C1_INNSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_INNSEL_SHIFT)) & CMP_C1_INNSEL_MASK) #define CMP_C1_INPSEL_MASK (0x18000000U) #define CMP_C1_INPSEL_SHIFT (27U) #define CMP_C1_INPSEL_WIDTH (2U) #define CMP_C1_INPSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_INPSEL_SHIFT)) & CMP_C1_INPSEL_MASK) /*! @} */ /*! @name C2 - CMP Control Register 2 */ /*! @{ */ #define CMP_C2_ACOn_MASK (0xFFU) #define CMP_C2_ACOn_SHIFT (0U) #define CMP_C2_ACOn_WIDTH (8U) #define CMP_C2_ACOn(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_ACOn_SHIFT)) & CMP_C2_ACOn_MASK) #define CMP_C2_INITMOD_MASK (0x3F00U) #define CMP_C2_INITMOD_SHIFT (8U) #define CMP_C2_INITMOD_WIDTH (6U) #define CMP_C2_INITMOD(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_INITMOD_SHIFT)) & CMP_C2_INITMOD_MASK) #define CMP_C2_NSAM_MASK (0xC000U) #define CMP_C2_NSAM_SHIFT (14U) #define CMP_C2_NSAM_WIDTH (2U) #define CMP_C2_NSAM(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_NSAM_SHIFT)) & CMP_C2_NSAM_MASK) #define CMP_C2_CH0F_MASK (0x10000U) #define CMP_C2_CH0F_SHIFT (16U) #define CMP_C2_CH0F_WIDTH (1U) #define CMP_C2_CH0F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH0F_SHIFT)) & CMP_C2_CH0F_MASK) #define CMP_C2_CH1F_MASK (0x20000U) #define CMP_C2_CH1F_SHIFT (17U) #define CMP_C2_CH1F_WIDTH (1U) #define CMP_C2_CH1F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH1F_SHIFT)) & CMP_C2_CH1F_MASK) #define CMP_C2_CH2F_MASK (0x40000U) #define CMP_C2_CH2F_SHIFT (18U) #define CMP_C2_CH2F_WIDTH (1U) #define CMP_C2_CH2F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH2F_SHIFT)) & CMP_C2_CH2F_MASK) #define CMP_C2_CH3F_MASK (0x80000U) #define CMP_C2_CH3F_SHIFT (19U) #define CMP_C2_CH3F_WIDTH (1U) #define CMP_C2_CH3F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH3F_SHIFT)) & CMP_C2_CH3F_MASK) #define CMP_C2_CH4F_MASK (0x100000U) #define CMP_C2_CH4F_SHIFT (20U) #define CMP_C2_CH4F_WIDTH (1U) #define CMP_C2_CH4F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH4F_SHIFT)) & CMP_C2_CH4F_MASK) #define CMP_C2_CH5F_MASK (0x200000U) #define CMP_C2_CH5F_SHIFT (21U) #define CMP_C2_CH5F_WIDTH (1U) #define CMP_C2_CH5F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH5F_SHIFT)) & CMP_C2_CH5F_MASK) #define CMP_C2_CH6F_MASK (0x400000U) #define CMP_C2_CH6F_SHIFT (22U) #define CMP_C2_CH6F_WIDTH (1U) #define CMP_C2_CH6F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH6F_SHIFT)) & CMP_C2_CH6F_MASK) #define CMP_C2_CH7F_MASK (0x800000U) #define CMP_C2_CH7F_SHIFT (23U) #define CMP_C2_CH7F_WIDTH (1U) #define CMP_C2_CH7F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH7F_SHIFT)) & CMP_C2_CH7F_MASK) #define CMP_C2_FXMXCH_MASK (0xE000000U) #define CMP_C2_FXMXCH_SHIFT (25U) #define CMP_C2_FXMXCH_WIDTH (3U) #define CMP_C2_FXMXCH(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMXCH_SHIFT)) & CMP_C2_FXMXCH_MASK) #define CMP_C2_FXMP_MASK (0x20000000U) #define CMP_C2_FXMP_SHIFT (29U) #define CMP_C2_FXMP_WIDTH (1U) #define CMP_C2_FXMP(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMP_SHIFT)) & CMP_C2_FXMP_MASK) #define CMP_C2_RRIE_MASK (0x40000000U) #define CMP_C2_RRIE_SHIFT (30U) #define CMP_C2_RRIE_WIDTH (1U) #define CMP_C2_RRIE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_RRIE_SHIFT)) & CMP_C2_RRIE_MASK) #define CMP_C2_RRE_MASK (0x80000000U) #define CMP_C2_RRE_SHIFT (31U) #define CMP_C2_RRE_WIDTH (1U) #define CMP_C2_RRE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_RRE_SHIFT)) & CMP_C2_RRE_MASK) /*! @} */ /*! * @} */ /* end of group CMP_Register_Masks */ /*! * @} */ /* end of group CMP_Peripheral_Access_Layer */ #endif /* #if !defined(S32K118_CMP_H_) */