/* ------------------------------------------------------------------------- */ /* @file: startup_MKV10Z1287.s */ /* @purpose: CMSIS Cortex-M0P Core Device Startup File */ /* MKV10Z1287 */ /* @version: 1.1 */ /* @date: 2017-3-22 */ /* @build: b190918 */ /* ------------------------------------------------------------------------- */ /* */ /* Copyright 1997-2016 Freescale Semiconductor, Inc. */ /* Copyright 2016-2019 NXP */ /* All rights reserved. */ /* */ /* SPDX-License-Identifier: BSD-3-Clause */ /*****************************************************************************/ /* Version: GCC for ARM Embedded Processors */ /*****************************************************************************/ .syntax unified .arch armv6-m .section .isr_vector, "a" .align 2 .globl __isr_vector __isr_vector: .long __StackTop /* Top of Stack */ .long Reset_Handler /* Reset Handler */ .long NMI_Handler /* NMI Handler*/ .long HardFault_Handler /* Hard Fault Handler*/ .long 0 /* Reserved*/ .long 0 /* Reserved*/ .long 0 /* Reserved*/ .long 0 /* Reserved*/ .long 0 /* Reserved*/ .long 0 /* Reserved*/ .long 0 /* Reserved*/ .long SVC_Handler /* SVCall Handler*/ .long 0 /* Reserved*/ .long 0 /* Reserved*/ .long PendSV_Handler /* PendSV Handler*/ .long SysTick_Handler /* SysTick Handler*/ /* External Interrupts*/ .long DMA0_DMA4_IRQHandler /* DMA channel 0 and 4 transfer complete*/ .long DMA1_DMA5_IRQHandler /* DMA channel 1 and 5 transfer complete*/ .long DMA2_DMA6_IRQHandler /* DMA channel 2 and 6 transfer complete*/ .long DMA3_DMA7_IRQHandler /* DMA channel 2 and 7 transfer complete*/ .long DMA_Error_IRQHandler /* DMA error interrupt channels 0-7*/ .long FTFA_IRQHandler /* FTFA command complete and read collision*/ .long LVD_LVW_IRQHandler /* Low-voltage detect, low-voltage warning*/ .long LLWU_IRQHandler /* Low Leakage Wakeup*/ .long I2C0_IRQHandler /* I2C0 interrupt*/ .long Reserved25_IRQHandler /* Reserved interrupt*/ .long SPI0_IRQHandler /* SPI0 single interrupt vector for all sources*/ .long Reserved27_IRQHandler /* Reserved interrupt*/ .long UART0_IRQHandler /* UART0 status and error*/ .long UART1_IRQHandler /* UART1 status and error*/ .long Reserved30_IRQHandler /* Reserved interrupt*/ .long ADC0_IRQHandler /* ADC0 interrupt*/ .long ADC1_IRQHandler /* ADC1 interrupt*/ .long FTM0_IRQHandler /* FTM0 single interrupt vector for all sources*/ .long FTM1_IRQHandler /* FTM1 single interrupt vector for all sources*/ .long FTM2_IRQHandler /* FTM2 single interrupt vector for all sources*/ .long CMP0_IRQHandler /* CMP0 interrupt*/ .long CMP1_IRQHandler /* CMP1 interrupt*/ .long FTM3_IRQHandler /* FTM3 single interrupt vector for all sources*/ .long WDOG_EWM_IRQHandler /* Single interrupt vector for WDOG and EWM*/ .long FTM4_IRQHandler /* FTM4 single interrupt vector for all sources*/ .long DAC0_IRQHandler /* DAC0 interrupt*/ .long FTM5_IRQHandler /* FTM5 single interrupt vector for all sources*/ .long MCG_IRQHandler /* MCG interrupt*/ .long LPTMR0_IRQHandler /* LPTMR0 interrupt*/ .long PDB0_PDB1_IRQHandler /* Single interrupt vector for PDB0 and PDB1*/ .long PORTA_IRQHandler /* PORTA pin detect*/ .long PORTB_PORTC_PORTD_PORTE_IRQHandler /* Single interrupt vector for PORTB, PORTC, PORTD and PORTE pin detect*/ .size __isr_vector, . - __isr_vector /* Flash Configuration */ .section .FlashConfig, "a" .long 0xFFFFFFFF .long 0xFFFFFFFF .long 0xFFFFFFFF .long 0xFFFFFFFE .text .thumb /* Reset Handler */ .thumb_func .align 2 .globl Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: cpsid i /* Mask interrupts */ .equ VTOR, 0xE000ED08 ldr r0, =VTOR ldr r1, =__isr_vector str r1, [r0] ldr r2, [r1] msr msp, r2 #ifndef __NO_SYSTEM_INIT ldr r0,=SystemInit blx r0 #endif /* Loop to copy data from read only memory to RAM. The ranges * of copy from/to are specified by following symbols evaluated in * linker script. * __etext: End of code section, i.e., begin of data sections to copy from. * __data_start__/__data_end__: RAM address range that data should be * copied to. Both must be aligned to 4 bytes boundary. */ ldr r1, =__etext ldr r2, =__data_start__ ldr r3, =__data_end__ subs r3, r2 ble .LC0 .LC1: subs r3, 4 ldr r0, [r1,r3] str r0, [r2,r3] bgt .LC1 .LC0: #ifdef __STARTUP_CLEAR_BSS /* This part of work usually is done in C library startup code. Otherwise, * define this macro to enable it in this startup. * * Loop to zero out BSS section, which uses following symbols * in linker script: * __bss_start__: start of BSS section. Must align to 4 * __bss_end__: end of BSS section. Must align to 4 */ ldr r1, =__bss_start__ ldr r2, =__bss_end__ subs r2, r1 ble .LC3 movs r0, 0 .LC2: subs r2, 4 str r0, [r1, r2] bge .LC2 .LC3: #endif cpsie i /* Unmask interrupts */ #ifndef __START #define __START _start #endif #ifndef __ATOLLIC__ ldr r0,=__START blx r0 #else ldr r0,=__libc_init_array blx r0 ldr r0,=main bx r0 #endif .pool .size Reset_Handler, . - Reset_Handler .align 1 .thumb_func .weak DefaultISR .type DefaultISR, %function DefaultISR: ldr r0, =DefaultISR bx r0 .size DefaultISR, . - DefaultISR .align 1 .thumb_func .weak NMI_Handler .type NMI_Handler, %function NMI_Handler: ldr r0,=NMI_Handler bx r0 .size NMI_Handler, . - NMI_Handler .align 1 .thumb_func .weak HardFault_Handler .type HardFault_Handler, %function HardFault_Handler: ldr r0,=HardFault_Handler bx r0 .size HardFault_Handler, . - HardFault_Handler .align 1 .thumb_func .weak SVC_Handler .type SVC_Handler, %function SVC_Handler: ldr r0,=SVC_Handler bx r0 .size SVC_Handler, . - SVC_Handler .align 1 .thumb_func .weak PendSV_Handler .type PendSV_Handler, %function PendSV_Handler: ldr r0,=PendSV_Handler bx r0 .size PendSV_Handler, . - PendSV_Handler .align 1 .thumb_func .weak SysTick_Handler .type SysTick_Handler, %function SysTick_Handler: ldr r0,=SysTick_Handler bx r0 .size SysTick_Handler, . - SysTick_Handler .align 1 .thumb_func .weak DMA0_DMA4_IRQHandler .type DMA0_DMA4_IRQHandler, %function DMA0_DMA4_IRQHandler: ldr r0,=DMA0_DMA4_DriverIRQHandler bx r0 .size DMA0_DMA4_IRQHandler, . - DMA0_DMA4_IRQHandler .align 1 .thumb_func .weak DMA1_DMA5_IRQHandler .type DMA1_DMA5_IRQHandler, %function DMA1_DMA5_IRQHandler: ldr r0,=DMA1_DMA5_DriverIRQHandler bx r0 .size DMA1_DMA5_IRQHandler, . - DMA1_DMA5_IRQHandler .align 1 .thumb_func .weak DMA2_DMA6_IRQHandler .type DMA2_DMA6_IRQHandler, %function DMA2_DMA6_IRQHandler: ldr r0,=DMA2_DMA6_DriverIRQHandler bx r0 .size DMA2_DMA6_IRQHandler, . - DMA2_DMA6_IRQHandler .align 1 .thumb_func .weak DMA3_DMA7_IRQHandler .type DMA3_DMA7_IRQHandler, %function DMA3_DMA7_IRQHandler: ldr r0,=DMA3_DMA7_DriverIRQHandler bx r0 .size DMA3_DMA7_IRQHandler, . - DMA3_DMA7_IRQHandler .align 1 .thumb_func .weak DMA_Error_IRQHandler .type DMA_Error_IRQHandler, %function DMA_Error_IRQHandler: ldr r0,=DMA_Error_DriverIRQHandler bx r0 .size DMA_Error_IRQHandler, . - DMA_Error_IRQHandler .align 1 .thumb_func .weak I2C0_IRQHandler .type I2C0_IRQHandler, %function I2C0_IRQHandler: ldr r0,=I2C0_DriverIRQHandler bx r0 .size I2C0_IRQHandler, . - I2C0_IRQHandler .align 1 .thumb_func .weak SPI0_IRQHandler .type SPI0_IRQHandler, %function SPI0_IRQHandler: ldr r0,=SPI0_DriverIRQHandler bx r0 .size SPI0_IRQHandler, . - SPI0_IRQHandler .align 1 .thumb_func .weak UART0_IRQHandler .type UART0_IRQHandler, %function UART0_IRQHandler: ldr r0,=UART0_DriverIRQHandler bx r0 .size UART0_IRQHandler, . - UART0_IRQHandler .align 1 .thumb_func .weak UART1_IRQHandler .type UART1_IRQHandler, %function UART1_IRQHandler: ldr r0,=UART1_DriverIRQHandler bx r0 .size UART1_IRQHandler, . - UART1_IRQHandler /* Macro to define default handlers. Default handler * will be weak symbol and just dead loops. They can be * overwritten by other handlers */ .macro def_irq_handler handler_name .weak \handler_name .set \handler_name, DefaultISR .endm /* Exception Handlers */ def_irq_handler DMA0_DMA4_DriverIRQHandler def_irq_handler DMA1_DMA5_DriverIRQHandler def_irq_handler DMA2_DMA6_DriverIRQHandler def_irq_handler DMA3_DMA7_DriverIRQHandler def_irq_handler DMA_Error_DriverIRQHandler def_irq_handler FTFA_IRQHandler def_irq_handler LVD_LVW_IRQHandler def_irq_handler LLWU_IRQHandler def_irq_handler I2C0_DriverIRQHandler def_irq_handler Reserved25_IRQHandler def_irq_handler SPI0_DriverIRQHandler def_irq_handler Reserved27_IRQHandler def_irq_handler UART0_DriverIRQHandler def_irq_handler UART1_DriverIRQHandler def_irq_handler Reserved30_IRQHandler def_irq_handler ADC0_IRQHandler def_irq_handler ADC1_IRQHandler def_irq_handler FTM0_IRQHandler def_irq_handler FTM1_IRQHandler def_irq_handler FTM2_IRQHandler def_irq_handler CMP0_IRQHandler def_irq_handler CMP1_IRQHandler def_irq_handler FTM3_IRQHandler def_irq_handler WDOG_EWM_IRQHandler def_irq_handler FTM4_IRQHandler def_irq_handler DAC0_IRQHandler def_irq_handler FTM5_IRQHandler def_irq_handler MCG_IRQHandler def_irq_handler LPTMR0_IRQHandler def_irq_handler PDB0_PDB1_IRQHandler def_irq_handler PORTA_IRQHandler def_irq_handler PORTB_PORTC_PORTD_PORTE_IRQHandler .end