/* ** ################################################################### ** Processors: MKE14Z128VLH7 ** MKE14Z128VLL7 ** MKE14Z256VLH7 ** MKE14Z256VLL7 ** ** Compilers: Freescale C/C++ for Embedded ARM ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** ** Reference manual: KE1xZP100M72SF0RM, Rev. 2, Aug. 2016 ** Version: rev. 6.0, 2016-09-20 ** Build: b201123 ** ** Abstract: ** Provides a system configuration function and a global variable that ** contains the system frequency. It configures the device and initializes ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. ** Copyright 2016-2020 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com ** ** Revisions: ** - rev. 1.0 (2015-08-19) ** Initial version. ** - rev. 2.0 (2015-09-22) ** Based on rev0final RDP, add PCC/TRGMUX. ** - rev. 3.0 (2015-12-29) ** Align LPFLL register names. ** - rev. 4.0 (2016-02-19) ** Based on rev1final RDP. ** - rev. 5.0 (2016-08-02) ** Based on rev1.x RDP. ** - rev. 6.0 (2016-09-20) ** Based on rev2 RDP. ** ** ################################################################### */ /*! * @file MKE14Z7 * @version 6.0 * @date 2016-09-20 * @brief Device specific configuration file for MKE14Z7 (implementation file) * * Provides a system configuration function and a global variable that contains * the system frequency. It configures the device and initializes the oscillator * (PLL) that is part of the microcontroller device. */ #include #include "fsl_device_registers.h" /* ---------------------------------------------------------------------------- -- Core clock ---------------------------------------------------------------------------- */ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; /* ---------------------------------------------------------------------------- -- SystemInit() ---------------------------------------------------------------------------- */ void SystemInit (void) { /* Redirect vector table to Flash, in case of boot from ROM without overwriting FOPT boot option */ RCM->MR = 3UL << 1U; #if (DISABLE_WDOG) if ((WDOG->CS & WDOG_CS_CMD32EN_MASK) != 0U) { WDOG->CNT = WDOG_UPDATE_KEY; } else { WDOG->CNT = WDOG_UPDATE_KEY & 0xFFFFU; WDOG->CNT = (WDOG_UPDATE_KEY >> 16U) & 0xFFFFU; } WDOG->TOVAL = 0xFFFFU; WDOG->CS = (uint32_t) ((WDOG->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK; #endif /* (DISABLE_WDOG) */ SystemInitHook(); } /* ---------------------------------------------------------------------------- -- SystemCoreClockUpdate() ---------------------------------------------------------------------------- */ void SystemCoreClockUpdate (void) { uint32_t SCGOUTClock; /* Variable to store output clock frequency of the SCG module */ uint16_t Divider; Divider = (uint16_t)(((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U); switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) { case 0x1: /* System OSC */ SCGOUTClock = CPU_XTAL_CLK_HZ; break; case 0x2: /* Slow IRC */ SCGOUTClock = ((((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT) != 0U) ? 8000000U : 2000000U); break; case 0x3: /* Fast IRC */ SCGOUTClock = 48000000U + ((SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * 4000000U; break; case 0x5: /* Low Power FLL */ SCGOUTClock = 48000000U + ((SCG->LPFLLCFG & SCG_LPFLLCFG_FSEL_MASK) >> SCG_LPFLLCFG_FSEL_SHIFT) * 24000000U; break; default: SCGOUTClock = 0U; break; } SystemCoreClock = (SCGOUTClock / Divider); } /* ---------------------------------------------------------------------------- -- SystemInitHook() ---------------------------------------------------------------------------- */ __attribute__ ((weak)) void SystemInitHook (void) { /* Void implementation of the weak function. */ }